ARM: stm32mp: enable data cache after LMB configuration for STM32MP1
Move the stm32mp1 data cache reconfiguration after the lmb init call
board_r::initr_lmb to allow parsing of the reserved region with
no-map tag.
After this patch the DDR is not fully mapped up to arch_early_init_r()
call, only the relocation region is mapped, but it is enough for
the first board_r initialization phases; later, when arch_early_init_r()
is called, the LMB is already initialized and the function
lmb_is_reserved_flags() function is functional, this LMB function
is called in the weak function dram_bank_mmu_setup() when
dcache_enable() is executed.
Without this change, as LMB is not initialized when it is used in
dram_bank_mmu_setup, the OP-TEE region is mapped cache-able by U-Boot
and we have some firewall violation since "LMB memory map global and
persistent" series.
Fixes: ed17a33fed29 ("lmb: make LMB memory map persistent and global")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d5934a9..25663a9 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -39,6 +39,7 @@
config STM32MP13X
bool "Support STMicroelectronics STM32MP13x Soc"
+ select ARCH_EARLY_INIT_R
select ARM_SMCCC
select CPU_V7A
select CPU_V7_HAS_NONSEC
@@ -57,6 +58,7 @@
config STM32MP15X
bool "Support STMicroelectronics STM32MP15x Soc"
+ select ARCH_EARLY_INIT_R
select ARCH_SUPPORT_PSCI
select BINMAN
select CPU_V7A