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git01.mediatek.com / filogic / uboot / 751c6c6446b292d9e9ae8a88f7bd90f196c40950 / . / drivers / clk / sunxi / clk_a83t.c
blob: 3562da61d14af3eb762ca405bf4866884c48b002 [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]15
16static struct ccu_clk_gate a83t_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
27
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]28 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
29
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]30 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
31 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
32 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]33 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
34 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
35 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
36 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
37 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
38
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]39 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
41
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]42 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
43 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
44 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
45 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
46 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
47};
48
49static struct ccu_reset a83t_resets[] = {
50 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
51 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
52 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
53
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]54 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
55 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
56 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]57 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]58 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
59 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]60 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
61 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
62 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
63 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]64
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]65 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
66 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
67 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]68 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
69 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
70 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
71 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
72 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]73};
74
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame^]75const struct ccu_desc a83t_ccu_desc = {
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]76 .gates = a83t_gates,
77 .resets = a83t_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]78 .num_gates = ARRAY_SIZE(a83t_gates),
79 .num_resets = ARRAY_SIZE(a83t_resets),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]80};