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git01.mediatek.com / filogic / uboot / ddf33c1e3a8e3d7ccbb70f88801da0574fb99169 / . / drivers / clk / sunxi / clk_a83t.c
blob: b5a555da36d4f71630ffca511326a583a26c8538 [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
14
15static struct ccu_clk_gate a83t_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame^]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]19 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
20 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
21 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
22 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
23
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]24 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
25 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
26 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
27 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
28 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
29
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]30 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
31 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
32 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
33 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
34 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
35};
36
37static struct ccu_reset a83t_resets[] = {
38 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
39 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
40 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
41
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame^]42 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
43 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
44 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]45 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
46 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
47 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
48 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]49
50 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
51 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
52 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
53 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
54 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]55};
56
57static const struct ccu_desc a83t_ccu_desc = {
58 .gates = a83t_gates,
59 .resets = a83t_resets,
60};
61
62static int a83t_clk_bind(struct udevice *dev)
63{
64 return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
65}
66
67static const struct udevice_id a83t_clk_ids[] = {
68 { .compatible = "allwinner,sun8i-a83t-ccu",
69 .data = (ulong)&a83t_ccu_desc },
70 { }
71};
72
73U_BOOT_DRIVER(clk_sun8i_a83t) = {
74 .name = "sun8i_a83t_ccu",
75 .id = UCLASS_CLK,
76 .of_match = a83t_clk_ids,
77 .priv_auto_alloc_size = sizeof(struct ccu_priv),
78 .ops = &sunxi_clk_ops,
79 .probe = sunxi_clk_probe,
80 .bind = a83t_clk_bind,
81};