blob: 464e95c07da13addc605f0716bf90db7bd5affba [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +05301// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -050011#include <clk/sunxi.h>
Jagan Teki24740332018-08-02 23:33:55 +053012#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060014#include <linux/bitops.h>
Jagan Teki24740332018-08-02 23:33:55 +053015
16static struct ccu_clk_gate a83t_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +000017 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +053020 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +053021 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +053023 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
27
Andre Przywara3e9aa0b2022-05-04 22:10:28 +010028 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
29
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050030 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
31 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
32 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +053033 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
34 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
35 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
36 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
37 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
38
Jagan Tekibc123132019-02-27 20:02:06 +053039 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
40 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
41
Jagan Teki24740332018-08-02 23:33:55 +053042 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
43 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
44 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
45 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
46 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
47};
48
49static struct ccu_reset a83t_resets[] = {
50 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
51 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
52 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
53
Andre Przywaraddf33c12019-01-29 15:54:09 +000054 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
55 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
56 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +053057 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +053058 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
59 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +053060 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
61 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
62 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
63 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +053064
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050065 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
66 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
67 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Tekib490aa52018-12-30 21:37:31 +053068 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
69 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
70 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
71 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
72 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +053073};
74
75static const struct ccu_desc a83t_ccu_desc = {
76 .gates = a83t_gates,
77 .resets = a83t_resets,
Samuel Holland84436502022-05-09 00:29:31 -050078 .num_gates = ARRAY_SIZE(a83t_gates),
79 .num_resets = ARRAY_SIZE(a83t_resets),
Jagan Teki24740332018-08-02 23:33:55 +053080};
81
Jagan Teki24740332018-08-02 23:33:55 +053082static const struct udevice_id a83t_clk_ids[] = {
83 { .compatible = "allwinner,sun8i-a83t-ccu",
84 .data = (ulong)&a83t_ccu_desc },
85 { }
86};
87
88U_BOOT_DRIVER(clk_sun8i_a83t) = {
89 .name = "sun8i_a83t_ccu",
90 .id = UCLASS_CLK,
91 .of_match = a83t_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -070092 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki24740332018-08-02 23:33:55 +053093 .ops = &sunxi_clk_ops,
94 .probe = sunxi_clk_probe,
Samuel Holland1567fdf2022-05-09 00:29:33 -050095 .bind = sunxi_clk_bind,
Jagan Teki24740332018-08-02 23:33:55 +053096};