Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 836631bc4ee5c33190674f2fa3047832649292e1 / . / drivers / clk / sunxi / clk_a83t.c
blob: 2be87a31fd5301f7c6b9e8dd8cabaff3edaa4b56 [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
14
15static struct ccu_clk_gate a83t_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame^]19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
26
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]27 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
28 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
29 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
30 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
31 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
32
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]33 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
34 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
35
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]36 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
37 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
38 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
39 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
40 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
41};
42
43static struct ccu_reset a83t_resets[] = {
44 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
45 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
46 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
47
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]48 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
49 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
50 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame^]51 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]52 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
53 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]54 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
55 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
56 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
57 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]58
59 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
60 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
61 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
62 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
63 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]64};
65
66static const struct ccu_desc a83t_ccu_desc = {
67 .gates = a83t_gates,
68 .resets = a83t_resets,
69};
70
71static int a83t_clk_bind(struct udevice *dev)
72{
73 return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
74}
75
76static const struct udevice_id a83t_clk_ids[] = {
77 { .compatible = "allwinner,sun8i-a83t-ccu",
78 .data = (ulong)&a83t_ccu_desc },
79 { }
80};
81
82U_BOOT_DRIVER(clk_sun8i_a83t) = {
83 .name = "sun8i_a83t_ccu",
84 .id = UCLASS_CLK,
85 .of_match = a83t_clk_ids,
86 .priv_auto_alloc_size = sizeof(struct ccu_priv),
87 .ops = &sunxi_clk_ops,
88 .probe = sunxi_clk_probe,
89 .bind = a83t_clk_bind,
90};