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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +02002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +02005 */
6
Simon Glass1d91ba72019-11-14 12:57:37 -07007#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -06008#include <log.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Tom Rini643dc102024-04-30 07:35:59 -060010#include <asm/u-boot.h>
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020011#include <asm/system.h>
R Sricharan08716072013-03-04 20:04:44 +000012#include <asm/cache.h>
13#include <linux/compiler.h>
Lokesh Vutla19858f92018-04-26 18:21:31 +053014#include <asm/armv7_mpu.h>
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020015
Trevor Woerner43ec7e02019-05-03 09:41:00 -040016#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
Heiko Schocher69f1d0c2010-09-17 13:10:29 +020017
Heiko Schocher69f1d0c2010-09-17 13:10:29 +020018DECLARE_GLOBAL_DATA_PTR;
19
Lokesh Vutla19858f92018-04-26 18:21:31 +053020#ifdef CONFIG_SYS_ARM_MMU
Jeroen Hofsteed7460772014-06-23 22:07:04 +020021__weak void arm_init_before_mmu(void)
Aneesh V3e3bc1e2011-06-16 23:30:49 +000022{
23}
Aneesh V3e3bc1e2011-06-16 23:30:49 +000024
Marek Szyprowskif76fb512020-06-03 14:43:42 +020025static void set_section_phys(int section, phys_addr_t phys,
26 enum dcache_option option)
Heiko Schocheraeb29912010-09-17 13:10:39 +020027{
Alexander Grafae6c2bc2016-03-16 15:41:21 +010028#ifdef CONFIG_ARMV7_LPAE
29 u64 *page_table = (u64 *)gd->arch.tlb_addr;
30 /* Need to set the access flag to not fault */
31 u64 value = TTB_SECT_AP | TTB_SECT_AF;
32#else
Simon Glass6b4ee152012-12-13 20:48:39 +000033 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Alexander Grafae6c2bc2016-03-16 15:41:21 +010034 u32 value = TTB_SECT_AP;
35#endif
36
37 /* Add the page offset */
Marek Szyprowskif76fb512020-06-03 14:43:42 +020038 value |= phys;
Simon Glassa4f20792012-10-17 13:24:53 +000039
Alexander Grafae6c2bc2016-03-16 15:41:21 +010040 /* Add caching bits */
Simon Glassa4f20792012-10-17 13:24:53 +000041 value |= option;
Alexander Grafae6c2bc2016-03-16 15:41:21 +010042
43 /* Set PTE */
Simon Glassa4f20792012-10-17 13:24:53 +000044 page_table[section] = value;
45}
46
Marek Szyprowskif76fb512020-06-03 14:43:42 +020047void set_section_dcache(int section, enum dcache_option option)
48{
49 set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
50}
51
Jeroen Hofsteed7460772014-06-23 22:07:04 +020052__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
Simon Glassa4f20792012-10-17 13:24:53 +000053{
54 debug("%s: Warning: not implemented\n", __func__);
55}
56
Marek Szyprowskif76fb512020-06-03 14:43:42 +020057void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
58 size_t size, enum dcache_option option)
Simon Glassa4f20792012-10-17 13:24:53 +000059{
Stefan Agnerc4a73222016-08-14 21:33:00 -070060#ifdef CONFIG_ARMV7_LPAE
61 u64 *page_table = (u64 *)gd->arch.tlb_addr;
62#else
Simon Glass6b4ee152012-12-13 20:48:39 +000063 u32 *page_table = (u32 *)gd->arch.tlb_addr;
Stefan Agnerc4a73222016-08-14 21:33:00 -070064#endif
Stefan Agnerbae14802016-08-14 21:33:01 -070065 unsigned long startpt, stoppt;
Thierry Redingfe2007152014-08-26 17:34:21 +020066 unsigned long upto, end;
Simon Glassa4f20792012-10-17 13:24:53 +000067
Patrick Delaunay594b7cf2020-04-24 20:20:17 +020068 /* div by 2 before start + size to avoid phys_addr_t overflow */
69 end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2)
70 >> (MMU_SECTION_SHIFT - 1);
Simon Glassa4f20792012-10-17 13:24:53 +000071 start = start >> MMU_SECTION_SHIFT;
Patrick Delaunay594b7cf2020-04-24 20:20:17 +020072
Keerthy266c8c12016-10-29 15:19:10 +053073#ifdef CONFIG_ARMV7_LPAE
74 debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
75 option);
76#else
Keerthy485110a2016-10-29 15:19:09 +053077 debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
Simon Glassa4f20792012-10-17 13:24:53 +000078 option);
Keerthy266c8c12016-10-29 15:19:10 +053079#endif
Marek Szyprowskif76fb512020-06-03 14:43:42 +020080 for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
81 set_section_phys(upto, phys, option);
Stefan Agnerbae14802016-08-14 21:33:01 -070082
83 /*
84 * Make sure range is cache line aligned
85 * Only CPU maintains page tables, hence it is safe to always
86 * flush complete cache lines...
87 */
88
89 startpt = (unsigned long)&page_table[start];
90 startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
91 stoppt = (unsigned long)&page_table[end];
92 stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
93 mmu_page_table_flush(startpt, stoppt);
Simon Glassa4f20792012-10-17 13:24:53 +000094}
95
R Sricharan08716072013-03-04 20:04:44 +000096__weak void dram_bank_mmu_setup(int bank)
Simon Glassa4f20792012-10-17 13:24:53 +000097{
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090098 struct bd_info *bd = gd->bd;
Heiko Schocheraeb29912010-09-17 13:10:39 +020099 int i;
100
Patrick Delaunay77cc8b22020-04-24 20:20:15 +0200101 /* bd->bi_dram is available only after relocation */
102 if ((gd->flags & GD_FLG_RELOC) == 0)
103 return;
104
Heiko Schocheraeb29912010-09-17 13:10:39 +0200105 debug("%s: bank: %d\n", __func__, bank);
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100106 for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
107 i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
108 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
Patrick Delaunayd7e6a1d2020-04-24 20:20:16 +0200109 i++)
110 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
Heiko Schocheraeb29912010-09-17 13:10:39 +0200111}
Heiko Schocheraeb29912010-09-17 13:10:39 +0200112
113/* to activate the MMU we need to set up virtual memory: use 1M areas */
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200114static inline void mmu_setup(void)
115{
Heiko Schocheraeb29912010-09-17 13:10:39 +0200116 int i;
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200117 u32 reg;
118
Aneesh V3e3bc1e2011-06-16 23:30:49 +0000119 arm_init_before_mmu();
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200120 /* Set up an identity-mapping for all 4GB, rw for everyone */
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100121 for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
Simon Glassa4f20792012-10-17 13:24:53 +0000122 set_section_dcache(i, DCACHE_OFF);
Heiko Schocheraeb29912010-09-17 13:10:39 +0200123
Heiko Schocheraeb29912010-09-17 13:10:39 +0200124 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
125 dram_bank_mmu_setup(i);
126 }
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200127
Simon Glass5bfd41d2017-05-31 17:57:13 -0600128#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100129 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
130 for (i = 0; i < 4; i++) {
131 u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
132 u64 tpt = gd->arch.tlb_addr + (4096 * i);
133 page_table[i] = tpt | TTB_PAGETABLE;
134 }
135
136 reg = TTBCR_EAE;
137#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
138 reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
139#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
140 reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
141#else
142 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
143#endif
144
145 if (is_hyp()) {
Simon Glass3b372472017-05-31 17:57:12 -0600146 /* Set HTCR to enable LPAE */
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100147 asm volatile("mcr p15, 4, %0, c2, c0, 2"
148 : : "r" (reg) : "memory");
149 /* Set HTTBR0 */
150 asm volatile("mcrr p15, 4, %0, %1, c2"
151 :
152 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
153 : "memory");
154 /* Set HMAIR */
155 asm volatile("mcr p15, 4, %0, c10, c2, 0"
156 : : "r" (MEMORY_ATTRIBUTES) : "memory");
157 } else {
158 /* Set TTBCR to enable LPAE */
159 asm volatile("mcr p15, 0, %0, c2, c0, 2"
160 : : "r" (reg) : "memory");
161 /* Set 64-bit TTBR0 */
162 asm volatile("mcrr p15, 0, %0, %1, c2"
163 :
164 : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
165 : "memory");
166 /* Set MAIR */
167 asm volatile("mcr p15, 0, %0, c10, c2, 0"
168 : : "r" (MEMORY_ATTRIBUTES) : "memory");
169 }
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530170#elif defined(CONFIG_CPU_V7A)
Simon Glass1375e582017-05-31 17:57:14 -0600171 if (is_hyp()) {
172 /* Set HTCR to disable LPAE */
173 asm volatile("mcr p15, 4, %0, c2, c0, 2"
174 : : "r" (0) : "memory");
175 } else {
176 /* Set TTBCR to disable LPAE */
177 asm volatile("mcr p15, 0, %0, c2, c0, 2"
178 : : "r" (0) : "memory");
179 }
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500180 /* Set TTBR0 */
181 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
182#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
183 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
184#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
185 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
186#else
187 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
188#endif
189 asm volatile("mcr p15, 0, %0, c2, c0, 0"
190 : : "r" (reg) : "memory");
191#else
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200192 /* Copy the page table address to cp15 */
193 asm volatile("mcr p15, 0, %0, c2, c0, 0"
Simon Glass6b4ee152012-12-13 20:48:39 +0000194 : : "r" (gd->arch.tlb_addr) : "memory");
Bryan Brinsko29d23ec2015-03-24 11:25:12 -0500195#endif
Patrick Delaunay4aae24d2021-02-05 13:53:36 +0100196 /*
197 * initial value of Domain Access Control Register (DACR)
198 * Set the access control to client (1U) for each of the 16 domains
199 */
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200200 asm volatile("mcr p15, 0, %0, c3, c0, 0"
Patrick Delaunay4aae24d2021-02-05 13:53:36 +0100201 : : "r" (0x55555555));
R Sricharan06396c12013-03-04 20:04:45 +0000202
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200203 /* and enable the mmu */
204 reg = get_cr(); /* get control reg. */
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200205 set_cr(reg | CR_M);
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200206}
207
Aneesh V3bda3772011-06-16 23:30:50 +0000208static int mmu_enabled(void)
209{
210 return get_cr() & CR_M;
211}
Lokesh Vutla19858f92018-04-26 18:21:31 +0530212#endif /* CONFIG_SYS_ARM_MMU */
Aneesh V3bda3772011-06-16 23:30:50 +0000213
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200214/* cache_bit must be either CR_I or CR_C */
215static void cache_enable(uint32_t cache_bit)
216{
217 uint32_t reg;
218
Lokesh Vutla19858f92018-04-26 18:21:31 +0530219 /* The data cache is not active unless the mmu/mpu is enabled too */
220#ifdef CONFIG_SYS_ARM_MMU
Aneesh V3bda3772011-06-16 23:30:50 +0000221 if ((cache_bit == CR_C) && !mmu_enabled())
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200222 mmu_setup();
Lokesh Vutla19858f92018-04-26 18:21:31 +0530223#elif defined(CONFIG_SYS_ARM_MPU)
224 if ((cache_bit == CR_C) && !mpu_enabled()) {
225 printf("Consider enabling MPU before enabling caches\n");
226 return;
227 }
228#endif
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200229 reg = get_cr(); /* get control reg. */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200230 set_cr(reg | cache_bit);
231}
232
233/* cache_bit must be either CR_I or CR_C */
234static void cache_disable(uint32_t cache_bit)
235{
236 uint32_t reg;
237
SRICHARAN R88f4bf22012-05-16 23:52:54 +0000238 reg = get_cr();
SRICHARAN R88f4bf22012-05-16 23:52:54 +0000239
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200240 if (cache_bit == CR_C) {
Heiko Schocheraeb29912010-09-17 13:10:39 +0200241 /* if cache isn;t enabled no need to disable */
Heiko Schocheraeb29912010-09-17 13:10:39 +0200242 if ((reg & CR_C) != CR_C)
243 return;
Lokesh Vutla9ac1d172019-10-30 15:55:41 +0530244#ifdef CONFIG_SYS_ARM_MMU
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200245 /* if disabling data cache, disable mmu too */
246 cache_bit |= CR_M;
Lokesh Vutla9ac1d172019-10-30 15:55:41 +0530247#endif
Heiko Schocher69f1d0c2010-09-17 13:10:29 +0200248 }
Arun Mankuzhi7a7825f2012-11-30 13:01:14 +0000249 reg = get_cr();
Lothar Waßmannbded0c82017-06-08 09:48:41 +0200250
Lokesh Vutla9ac1d172019-10-30 15:55:41 +0530251#ifdef CONFIG_SYS_ARM_MMU
Arun Mankuzhi7a7825f2012-11-30 13:01:14 +0000252 if (cache_bit == (CR_C | CR_M))
Lokesh Vutla9ac1d172019-10-30 15:55:41 +0530253#elif defined(CONFIG_SYS_ARM_MPU)
254 if (cache_bit == CR_C)
255#endif
Arun Mankuzhi7a7825f2012-11-30 13:01:14 +0000256 flush_dcache_all();
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200257 set_cr(reg & ~cache_bit);
258}
259#endif
260
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400261#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
Simon Glassfbf091b2019-11-14 12:57:36 -0700262void icache_enable(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200263{
264 return;
265}
266
Simon Glassfbf091b2019-11-14 12:57:36 -0700267void icache_disable(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200268{
269 return;
270}
271
Simon Glassfbf091b2019-11-14 12:57:36 -0700272int icache_status(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200273{
274 return 0; /* always off */
275}
276#else
277void icache_enable(void)
278{
279 cache_enable(CR_I);
280}
281
282void icache_disable(void)
283{
284 cache_disable(CR_I);
285}
286
287int icache_status(void)
288{
289 return (get_cr() & CR_I) != 0;
290}
291#endif
292
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400293#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Simon Glassfbf091b2019-11-14 12:57:36 -0700294void dcache_enable(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200295{
296 return;
297}
298
Simon Glassfbf091b2019-11-14 12:57:36 -0700299void dcache_disable(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200300{
301 return;
302}
303
Simon Glassfbf091b2019-11-14 12:57:36 -0700304int dcache_status(void)
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200305{
306 return 0; /* always off */
307}
Patrice Chotard28522a62021-02-24 13:48:42 +0100308
309void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
310 enum dcache_option option)
311{
312}
313
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200314#else
315void dcache_enable(void)
316{
317 cache_enable(CR_C);
318}
319
320void dcache_disable(void)
321{
322 cache_disable(CR_C);
323}
324
325int dcache_status(void)
326{
327 return (get_cr() & CR_C) != 0;
328}
Patrice Chotard28522a62021-02-24 13:48:42 +0100329
330void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
331 enum dcache_option option)
332{
333 mmu_set_region_dcache_behaviour_phys(start, start, size, option);
334}
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +0200335#endif