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git01.mediatek.com / filogic / uboot / 600c731a336e53bb1435c10c973b5248366f19ad / . / arch / arm / mach-socfpga / Kconfig
blob: 3770e0725857859c1606bccbc836c54e42304426 [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Goldschmidt17d78522019-10-22 21:29:48 +0200[diff] [blame]3config ERR_PTR_OFFSET
4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
5
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]6config NR_DRAM_BANKS
7 default 1
8
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200[diff] [blame]9config SPL_SIZE_LIMIT
Simon Glassa8f0c942019-09-25 08:56:28 -0600[diff] [blame]10 default 0x10000 if TARGET_SOCFPGA_GEN5
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200[diff] [blame]11
12config SPL_SIZE_LIMIT_PROVIDE_STACK
13 default 0x200 if TARGET_SOCFPGA_GEN5
14
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]15config SPL_STACK_R_ADDR
16 default 0x00800000 if TARGET_SOCFPGA_GEN5
17
Simon Goldschmidt4f57b9a2019-04-09 21:02:06 +0200[diff] [blame]18config SPL_SYS_MALLOC_F_LEN
19 default 0x800 if TARGET_SOCFPGA_GEN5
20
Dalon Westergreen8d770f42017-02-10 17:15:34 -0800[diff] [blame]21config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
22 default 0xa2
23
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]24config SYS_MALLOC_F_LEN
25 default 0x2000 if TARGET_SOCFPGA_ARRIA10
26 default 0x2000 if TARGET_SOCFPGA_GEN5
27
28config SYS_TEXT_BASE
29 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
30 default 0x01000040 if TARGET_SOCFPGA_GEN5
31
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]32config TARGET_SOCFPGA_ARRIA5
33 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]34 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]35
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]36config TARGET_SOCFPGA_ARRIA10
37 bool
Ley Foon Tan17b9ba62019-05-06 09:55:59 +0800[diff] [blame]38 select SPL_ALTERA_SDRAM
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]39 select SPL_BOARD_INIT if SPL
Marek Vasute1dcd622018-07-30 15:56:19 +0200[diff] [blame]40 select CLK
41 select SPL_CLK if SPL
Marek Vasut69fbb882018-08-13 18:32:38 +0200[diff] [blame]42 select DM_I2C
Marek Vasut700b2c62018-08-13 18:32:38 +0200[diff] [blame]43 select DM_RESET
44 select SPL_DM_RESET if SPL
Marek Vasut04c8f4f2018-08-13 20:06:46 +0200[diff] [blame]45 select REGMAP
46 select SPL_REGMAP if SPL
47 select SYSCON
48 select SPL_SYSCON if SPL
49 select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]50 imply FPGA_SOCFPGA
Simon Glass7611ac62019-09-25 08:56:27 -0600[diff] [blame]51 imply SPL_USE_TINY_PRINTF
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]52
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]53config TARGET_SOCFPGA_CYCLONE5
54 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]55 select TARGET_SOCFPGA_GEN5
56
57config TARGET_SOCFPGA_GEN5
58 bool
Ley Foon Tan17b9ba62019-05-06 09:55:59 +0800[diff] [blame]59 select SPL_ALTERA_SDRAM
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]60 imply FPGA_SOCFPGA
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200[diff] [blame]61 imply SPL_SIZE_LIMIT_SUBTRACT_GD
62 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame]63 imply SPL_STACK_R
64 imply SPL_SYS_MALLOC_SIMPLE
Simon Glass7611ac62019-09-25 08:56:27 -0600[diff] [blame]65 imply SPL_USE_TINY_PRINTF
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]66
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]67config TARGET_SOCFPGA_STRATIX10
68 bool
69 select ARMV8_MULTIENTRY
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]70 select ARMV8_SET_SMPEN
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]71 select ARMV8_SPIN_TABLE
Ang, Chee Hongda9640e2018-12-19 18:35:16 -0800[diff] [blame]72 select FPGA_STRATIX10
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]73
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]74choice
75 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]76 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]77
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]78config TARGET_SOCFPGA_ARIES_MCVEVK
79 bool "Aries MCVEVK (Cyclone V)"
80 select TARGET_SOCFPGA_CYCLONE5
81
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]82config TARGET_SOCFPGA_ARRIA10_SOCDK
83 bool "Altera SOCFPGA SoCDK (Arria 10)"
84 select TARGET_SOCFPGA_ARRIA10
85
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]86config TARGET_SOCFPGA_ARRIA5_SOCDK
87 bool "Altera SOCFPGA SoCDK (Arria V)"
88 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]89
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]90config TARGET_SOCFPGA_CYCLONE5_SOCDK
91 bool "Altera SOCFPGA SoCDK (Cyclone V)"
92 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]93
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]94config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
95 bool "Devboards DBM-SoC1 (Cyclone V)"
96 select TARGET_SOCFPGA_CYCLONE5
97
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]98config TARGET_SOCFPGA_EBV_SOCRATES
99 bool "EBV SoCrates (Cyclone V)"
100 select TARGET_SOCFPGA_CYCLONE5
101
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]102config TARGET_SOCFPGA_IS1
103 bool "IS1 (Cyclone V)"
104 select TARGET_SOCFPGA_CYCLONE5
105
Marek Vasut13da18c2019-06-27 00:19:31 +0200[diff] [blame]106config TARGET_SOCFPGA_SOFTING_VINING_FPGA
107 bool "Softing VIN|ING FPGA (Cyclone V)"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]108 select BOARD_LATE_INIT
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]109 select TARGET_SOCFPGA_CYCLONE5
110
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]111config TARGET_SOCFPGA_SR1500
112 bool "SR1500 (Cyclone V)"
113 select TARGET_SOCFPGA_CYCLONE5
114
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]115config TARGET_SOCFPGA_STRATIX10_SOCDK
116 bool "Intel SOCFPGA SoCDK (Stratix 10)"
117 select TARGET_SOCFPGA_STRATIX10
118
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]119config TARGET_SOCFPGA_TERASIC_DE0_NANO
120 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
121 select TARGET_SOCFPGA_CYCLONE5
122
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]123config TARGET_SOCFPGA_TERASIC_DE10_NANO
124 bool "Terasic DE10-Nano (Cyclone V)"
125 select TARGET_SOCFPGA_CYCLONE5
126
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]127config TARGET_SOCFPGA_TERASIC_DE1_SOC
128 bool "Terasic DE1-SoC (Cyclone V)"
129 select TARGET_SOCFPGA_CYCLONE5
130
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]131config TARGET_SOCFPGA_TERASIC_SOCKIT
132 bool "Terasic SoCkit (Cyclone V)"
133 select TARGET_SOCFPGA_CYCLONE5
134
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]135endchoice
136
137config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]138 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]139 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]140 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]141 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]142 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]143 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]144 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]145 default "is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]146 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]147 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]148 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]149 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]150 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut13da18c2019-06-27 00:19:31 +0200[diff] [blame]151 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]152
153config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]154 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]155 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]156 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]157 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]158 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]159 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]160 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut13da18c2019-06-27 00:19:31 +0200[diff] [blame]161 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]162 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]163 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]164 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]165 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]166
167config SYS_SOC
168 default "socfpga"
169
170config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]171 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]172 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]173 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]174 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]175 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]176 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]177 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]178 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200[diff] [blame]179 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]180 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]181 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]182 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]183 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut13da18c2019-06-27 00:19:31 +0200[diff] [blame]184 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]185
186endif