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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / usb / host / Kconfig
blob: 3dc79770eeb16a0a5bef286865c9d744f8bebcd1 [file] [log] [blame]
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]1#
2# USB Host Controller Drivers
3#
4comment "USB Host Controller Drivers"
5
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]6config USB_HOST
7 bool
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]8 select DM_USB
Marek Vasut1d5c59c2023-05-06 16:42:37 +0200[diff] [blame]9 help
10 Enable access to USB (Universal Serial Bus) host devices so that
11 SPL can load U-Boot from a connected USB peripheral, such as a USB
12 flash stick. While USB takes a little longer to start up than most
13 buses, it is very flexible since many different types of storage
14 device can be attached.
15
16config SPL_USB_HOST
17 bool "Support USB host drivers"
18 depends on SPL
19 help
20 For detailed help see USB_HOST Kconfig symbol. This option enables
21 the drivers in drivers/usb/host as part of an SPL build.
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]22
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]23config USB_XHCI_HCD
24 bool "xHCI HCD (USB 3.0) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]25 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]26 select USB_HOST
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]27 ---help---
28 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
29 "SuperSpeed" host controller hardware.
30
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]31if USB_XHCI_HCD
32
Masahiro Yamadad3b72ca2016-06-04 07:35:04 +0900[diff] [blame]33config USB_XHCI_DWC3
34 bool "DesignWare USB3 DRD Core Support"
35 help
36 Say Y or if your system has a Dual Role SuperSpeed
37 USB controller based on the DesignWare USB3 IP Core.
38
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]39config USB_XHCI_DWC3_OF_SIMPLE
40 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
Jean-Jacques Hiblot74d9a9d2018-04-12 10:41:10 +0200[diff] [blame]41 depends on DM_USB
Jean-Jacques Hiblot6c705f42018-04-12 10:41:11 +0200[diff] [blame]42 default y if DRA7XX
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]43 help
44 Support USB2/3 functionality in simple SoC integrations with
45 USB controller based on the DesignWare USB3 IP Core.
46
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]47config USB_XHCI_EXYNOS
48 bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
49 depends on ARCH_EXYNOS5
50 default y
51 help
52 Enables support for he on-chip xHCI controller on Samsung Exynos5
53 SoCs.
54
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]55config USB_XHCI_MTK
56 bool "Support for MediaTek on-chip xHCI USB controller"
developer4adcdca2022-05-20 11:22:56 +0800[diff] [blame]57 depends on ARCH_MEDIATEK || SOC_MT7621
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]58 help
59 Enables support for the on-chip xHCI controller on MediaTek SoCs.
60
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]61config USB_XHCI_MVEBU
62 bool "MVEBU USB 3.0 support"
63 default y
64 depends on ARCH_MVEBU
Konstantin Porotchkin1b5ed4d2017-02-12 11:10:30 +0200[diff] [blame]65 select DM_REGULATOR
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]66 help
67 Choose this option to add support for USB 3.0 driver on mvebu
68 SoCs, which includes Armada8K, Armada3700 and other Armada
69 family SoCs.
70
Patrick Rudolpha3782b12024-10-23 15:19:59 +0200[diff] [blame]71config USB_XHCI_GENERIC
72 bool "Generic SoC USB 3.0 support"
73 depends on OF_CONTROL
74 default n
75 help
76 Choose this option to add support for USB 3.0 driver for SoCs
77 that do not need platform specific code, like on emulated targets.
78
Stefan Roesedf33b572020-08-24 13:04:38 +0200[diff] [blame]79config USB_XHCI_OCTEON
80 bool "Support for Marvell Octeon family on-chip xHCI USB controller"
81 depends on ARCH_OCTEON
82 default y
83 help
84 Enables support for the on-chip xHCI controller on Marvell Octeon
85 family SoCs. This is a driver for the dwc3 to provide the glue logic
86 to configure the controller.
87
Tom Riniebc1c842021-09-12 20:32:22 -0400[diff] [blame]88config USB_XHCI_OMAP
89 bool "Support for TI OMAP family xHCI USB controller"
90 depends on ARCH_OMAP2PLUS
91 help
92 Enables support for the on-chip xHCI controller found on some TI SoC
93 families. Note that some families have multiple contollers while
94 others only have something such as DesignWare-based controllers.
95 Consult the SoC documentation to determine if this option applies
96 to your hardware.
97
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]98config USB_XHCI_PCI
99 bool "Support for PCI-based xHCI USB controller"
Heinrich Schuchardt9c83bad2023-11-20 15:56:36 +0100[diff] [blame]100 depends on DM_USB && PCI
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]101 default y if X86
102 help
103 Enables support for the PCI-based xHCI controller.
104
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]105config USB_XHCI_RCAR
Marek Vasut8a3f8f62024-12-11 08:30:37 +0100[diff] [blame]106 bool "Renesas R-Car USB 3.0 support"
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]107 default y
Marek Vasut6468c4c2024-02-27 17:05:55 +0100[diff] [blame]108 depends on ARCH_RENESAS
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]109 help
110 Choose this option to add support for USB 3.0 driver on Renesas
Marek Vasut8a3f8f62024-12-11 08:30:37 +0100[diff] [blame]111 R-Car Gen3 SoCs.
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]112
Uri Mashiachf6ff74e2017-02-23 15:39:36 +0200[diff] [blame]113config USB_XHCI_DRA7XX_INDEX
114 int "DRA7XX xHCI USB index"
115 range 0 1
116 default 0
117 depends on DRA7XX
118 help
119 Select the DRA7XX xHCI USB index.
120 Current supported values: 0, 1.
121
Ran Wanga5a97352017-10-23 10:09:22 +0800[diff] [blame]122config USB_XHCI_FSL
123 bool "Support for NXP Layerscape on-chip xHCI USB controller"
124 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
125 depends on !SPL_NO_USB
126 help
127 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
Rayagonda Kokatanurf59d24e2020-04-09 09:23:15 +0530[diff] [blame]128
129config USB_XHCI_BRCM
130 bool "Broadcom USB3 Host XHCI controller"
131 depends on DM_USB
132 help
133 USB controller based on the Broadcom USB3 IP Core.
134 Supports USB2/3 functionality.
135
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]136endif # USB_XHCI_HCD
Alexey Brodkin83fd3122015-12-14 17:18:50 +0300[diff] [blame]137
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]138config EHCI_DESC_BIG_ENDIAN
139 bool
140
141config EHCI_MMIO_BIG_ENDIAN
142 bool
143
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]144config USB_EHCI_HCD
145 bool "EHCI HCD (USB 2.0) support"
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]146 default y if ARCH_MX5 || ARCH_MX6
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]147 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]148 select USB_HOST
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]149 select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN
150 select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]151 ---help---
152 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
153 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
154 If your USB host controller supports USB 2.0, you will likely want to
155 configure this Host Controller Driver.
156
157 EHCI controllers are packaged with "companion" host controllers (OHCI
158 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
159 will connect to EHCI if the device is high speed, otherwise they
160 connect to a companion controller. If you configure EHCI, you should
161 probably configure the OHCI (for NEC and some other vendors) USB Host
162 Controller Driver or UHCI (for Via motherboards) Host Controller
163 Driver too.
164
165 You may want to read <file:Documentation/usb/ehci.txt>.
166
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]167if USB_EHCI_HCD
168
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]169config USB_EHCI_IS_TDI
170 bool
171
Wenyou Yang11e26652016-08-05 08:57:35 +0800[diff] [blame]172config USB_EHCI_ATMEL
173 bool "Support for Atmel on-chip EHCI USB controller"
174 depends on ARCH_AT91
175 default y
176 ---help---
177 Enables support for the on-chip EHCI controller on Atmel chips.
178
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]179config USB_EHCI_EXYNOS
180 bool "Support for Samsung Exynos EHCI USB controller"
181 depends on ARCH_EXYNOS
182 default y
183 ---help---
184 Enables support for the on-chip EHCI controller on Samsung Exynos
185 SoCs.
186
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]187config USB_EHCI_MARVELL
Tom Rini496a4172017-05-12 22:33:29 -0400[diff] [blame]188 bool "Support for Marvell on-chip EHCI USB controller"
Trevor Woernerbb7ab072020-05-06 08:02:40 -0400[diff] [blame]189 depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]190 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]191 select USB_EHCI_IS_TDI if !ARM64
Chris Packham927671e2022-11-05 17:23:57 +1300[diff] [blame]192 select USB_EHCI_IS_TDI if ALLEYCAT_5
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]193 ---help---
194 Enables support for the on-chip EHCI controller on MVEBU SoCs.
195
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]196config USB_EHCI_MX5
197 bool "Support for i.MX5 on-chip EHCI USB controller"
198 depends on ARCH_MX5
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]199 help
200 Enables support for the on-chip EHCI controller on i.MX5 SoCs.
201
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]202config USB_EHCI_MX6
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]203 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200[diff] [blame]204 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]205 select EHCI_HCD_INIT_AFTER_RESET
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]206 default y
207 ---help---
208 Enables support for the on-chip EHCI controller on i.MX6 SoCs.
209
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]210config USB_EHCI_MX7
Marek Vasut5d96cee2025-01-07 23:59:07 +0100[diff] [blame]211 bool "Support for i.MX7/i.MX8M/i.MX9 on-chip EHCI USB controller"
212 depends on ARCH_MX7 || IMX8M || IMX93 || IMX95
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]213 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
Marek Vasut5d96cee2025-01-07 23:59:07 +0100[diff] [blame]214 select PHY if IMX8M || IMX93 || IMX95
215 select NOP_PHY if IMX8M || IMX93 || IMX95
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]216 default y
217 ---help---
Marek Vasut5d96cee2025-01-07 23:59:07 +0100[diff] [blame]218 Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs.
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]219
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]220config USB_EHCI_MXS
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]221 bool "Support for i.MX23/i.MX28 EHCI USB controller"
222 depends on ARCH_MX23 || ARCH_MX28
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]223 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]224 select USB_EHCI_IS_TDI
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]225 help
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]226 Enables support for the on-chip EHCI controller on i.MX23 and
227 i.MX28 SoCs.
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]228
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]229config USB_EHCI_NPCM
230 bool "Support for Nuvoton NPCM on-chip EHCI USB controller"
231 depends on ARCH_NPCM
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]232 ---help---
233 Enables support for the on-chip EHCI controller on
234 Nuvoton NPCM chips.
235
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]236config USB_EHCI_OMAP
237 bool "Support for OMAP3+ on-chip EHCI USB controller"
238 depends on ARCH_OMAP2PLUS
Adam Fordcb9a3562022-02-19 17:08:44 -0600[diff] [blame]239 select PHY
240 imply NOP_PHY
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]241 default y
242 ---help---
243 Enables support for the on-chip EHCI controller on OMAP3 and later
244 SoCs.
245
Marcel Ziswiler31f44952019-03-25 17:24:54 +0100[diff] [blame]246config USB_EHCI_VF
247 bool "Support for Vybrid on-chip EHCI USB controller"
248 depends on ARCH_VF610
249 default y
250 help
251 Enables support for the on-chip EHCI controller on Vybrid SoCs.
252
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]253if USB_EHCI_MX6 || USB_EHCI_MX7
Stefan Agner8652ce92016-07-13 00:25:38 -0700[diff] [blame]254
255config MXC_USB_OTG_HACTIVE
256 bool "USB Power pin high active"
257 ---help---
258 Set the USB Power pin polarity to be high active (PWR_POL)
259
260endif
261
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]262config USB_EHCI_MSM
263 bool "Support for Qualcomm on-chip EHCI USB controller"
264 depends on DM_USB
265 select USB_ULPI_VIEWPORT
Ramon Fried7e365962018-09-21 13:35:50 +0300[diff] [blame]266 select MSM8916_USB_PHY
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]267 ---help---
268 Enables support for the on-chip EHCI controller on Qualcomm
269 Snapdragon SoCs.
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]270
Bin Mengec4b5732017-08-09 00:21:54 -0700[diff] [blame]271config USB_EHCI_PCI
272 bool "Support for PCI-based EHCI USB controller"
273 default y if X86
274 help
275 Enables support for the PCI-based EHCI controller.
276
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]277config USB_EHCI_TEGRA
278 bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]279 depends on ARCH_TEGRA
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]280 select USB_EHCI_IS_TDI
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]281 ---help---
282 Enable support for Tegra on-chip EHCI USB controller
283
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]284config USB_EHCI_ZYNQ
285 bool "Support for Xilinx Zynq on-chip EHCI USB controller"
Michal Simek3239d712020-08-24 14:41:51 +0200[diff] [blame]286 default y if ARCH_ZYNQ
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]287 select USB_EHCI_IS_TDI
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]288 ---help---
289 Enable support for Zynq on-chip EHCI USB controller
290
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]291config USB_EHCI_GENERIC
292 bool "Support for generic EHCI USB controller"
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]293 depends on DM_USB
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]294 default ARCH_SUNXI
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]295 ---help---
296 Enables support for generic EHCI controller.
297
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]298config EHCI_HCD_INIT_AFTER_RESET
299 bool
300
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]301config USB_EHCI_FSL
302 bool "Support for FSL on-chip EHCI USB controller"
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]303 select EHCI_HCD_INIT_AFTER_RESET
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]304 select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
305 !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]306 ---help---
307 Enables support for the on-chip EHCI controller on FSL chips.
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]308
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]309config SYS_FSL_USB_INTERNAL_UTMI_PHY
310 bool
311 depends on USB_EHCI_FSL
312
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]313config USB_EHCI_TXFIFO_THRESH
314 hex
315 depends on USB_EHCI_TEGRA
316 default 0x10
317 help
318 This parameter affects a TXFILLTUNING field that controls how much
319 data is sent to the latency fifo before it is sent to the wire.
320 Without this parameter, the default (2) causes occasional Data Buffer
321 Errors in OUT packets depending on the buffer address and size.
322
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]323endif # USB_EHCI_HCD
324
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]325config USB_OHCI_NEW
326 bool
327
328config SYS_USB_OHCI_CPU_INIT
329 bool
330
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]331config USB_OHCI_HCD
332 bool "OHCI HCD (USB 1.1) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]333 depends on DM && OF_CONTROL
334 select USB_HOST
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]335 select USB_OHCI_NEW
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]336 ---help---
337 The Open Host Controller Interface (OHCI) is a standard for accessing
338 USB 1.1 host controller hardware. It does more in hardware than Intel's
339 UHCI specification. If your USB host controller follows the OHCI spec,
340 say Y. On most non-x86 systems, and on x86 hardware that's not using a
341 USB controller from Intel or VIA, this is appropriate. If your host
342 controller doesn't use PCI, this is probably appropriate. For a PCI
343 based system where you're not sure, the "lspci -v" entry will list the
344 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
345
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]346if USB_OHCI_HCD
347
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]348config USB_OHCI_PCI
349 bool "Support for PCI-based OHCI USB controller"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]350 depends on PCI
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]351 help
352 Enables support for the PCI-based OHCI controller.
353
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]354config USB_OHCI_GENERIC
355 bool "Support for generic OHCI USB controller"
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]356 default ARCH_SUNXI
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]357 ---help---
358 Enables support for generic OHCI controller.
359
Adam Ford5f364f52019-04-30 05:21:41 -0500[diff] [blame]360config USB_OHCI_DA8XX
361 bool "Support for da850 OHCI USB controller"
362 help
363 Enable support for the da850 USB controller.
364
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]365config USB_OHCI_NPCM
366 bool "Support for Nuvoton NPCM on-chip OHCI USB controller"
367 depends on ARCH_NPCM
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]368 ---help---
369 Enables support for the on-chip OHCI controller on
370 Nuvoton NPCM chips.
371
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]372endif # USB_OHCI_HCD
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]373
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]374config SYS_USB_OHCI_SLOT_NAME
375 string "Display name for the OHCI controller"
376 depends on USB_OHCI_NEW && !DM_USB
377
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]378config SYS_OHCI_SWAP_REG_ACCESS
379 bool "Perform byte swapping on OHCI controller register accesses"
380 depends on USB_OHCI_NEW
381
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]382config USB_UHCI_HCD
383 bool "UHCI HCD (most Intel and VIA) support"
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]384 select USB_HOST
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]385 ---help---
386 The Universal Host Controller Interface is a standard by Intel for
387 accessing the USB hardware in the PC (which is also called the USB
388 host controller). If your USB host controller conforms to this
389 standard, you may want to say Y, but see below. All recent boards
390 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
391 i810, i820) conform to this standard. Also all VIA PCI chipsets
392 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
393 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
394 If unsure, say Y.
395
396if USB_UHCI_HCD
397
398endif # USB_UHCI_HCD
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]399
400config USB_DWC2
401 bool "DesignWare USB2 Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]402 depends on DM && OF_CONTROL
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]403 select USB_HOST
404 ---help---
405 The DesignWare USB 2.0 controller is compliant with the
406 USB-Implementers Forum (USB-IF) USB 2.0 specifications.
407 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
408 operation is compliant to the controller Supplement. If you want to
409 enable this controller in host mode, say Y.
Alexey Brodkinf19414b2018-02-28 16:16:58 +0300[diff] [blame]410
411if USB_DWC2
412config USB_DWC2_BUFFER_SIZE
413 int "Data buffer size in kB"
414 default 64
415 ---help---
416 By default 64 kB buffer is used but if amount of RAM avaialble on
417 the target is not enough to accommodate allocation of buffer of
418 that size it is possible to shrink it. Smaller sizes should be fine
419 because larger transactions could be split in smaller ones.
420
421endif # USB_DWC2
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]422
423config USB_R8A66597_HCD
424 bool "Renesas R8A66597 USB Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]425 depends on DM && OF_CONTROL
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]426 select USB_HOST
427 ---help---
428 This enables support for the on-chip Renesas R8A66597 USB 2.0
429 controller, present in various RZ and SH SoCs.
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]430
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]431config USB_ATMEL
432 bool "AT91 OHCI USB support"
433 depends on ARCH_AT91
434 select SYS_USB_OHCI_CPU_INIT
435 select USB_OHCI_NEW
436
437choice
438 prompt "Clock for OHCI"
439 depends on USB_ATMEL
440
441config USB_ATMEL_CLK_SEL_PLLB
442 bool "PLLB"
443
444config USB_ATMEL_CLK_SEL_UPLL
445 bool "UPLL"
446
447endchoice
448
449config USB_OHCI_LPC32XX
450 bool "LPC32xx USB OHCI support"
451 depends on ARCH_LPC32XX
452 select SYS_USB_OHCI_CPU_INIT
453 select USB_OHCI_NEW
454
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]455config USB_MAX_CONTROLLER_COUNT
456 int "Maximum number of USB host controllers"
457 depends on USB_EHCI_FSL || USB_XHCI_FSL || \
458 (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB)
459 default 1