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git01.mediatek.com / filogic / uboot / 1fd3b3dfac0295dd4f01407289b25cf803b92687 / . / drivers / usb / host / Kconfig
blob: 1aabe062fb34fc9d9625967d805a19cf581a3cb3 [file] [log] [blame]
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]1#
2# USB Host Controller Drivers
3#
4comment "USB Host Controller Drivers"
5
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]6config USB_HOST
7 bool
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]8 select DM_USB
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]9
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]10config USB_XHCI_HCD
11 bool "xHCI HCD (USB 3.0) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]12 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]13 select USB_HOST
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]14 ---help---
15 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
16 "SuperSpeed" host controller hardware.
17
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]18if USB_XHCI_HCD
19
Masahiro Yamadad3b72ca2016-06-04 07:35:04 +0900[diff] [blame]20config USB_XHCI_DWC3
21 bool "DesignWare USB3 DRD Core Support"
22 help
23 Say Y or if your system has a Dual Role SuperSpeed
24 USB controller based on the DesignWare USB3 IP Core.
25
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]26config USB_XHCI_DWC3_OF_SIMPLE
27 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
Jean-Jacques Hiblot74d9a9d2018-04-12 10:41:10 +0200[diff] [blame]28 depends on DM_USB
Mark Kettenis06ec9132019-06-30 18:01:54 +0200[diff] [blame]29 default y if ARCH_ROCKCHIP
Jean-Jacques Hiblot6c705f42018-04-12 10:41:11 +0200[diff] [blame]30 default y if DRA7XX
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]31 help
32 Support USB2/3 functionality in simple SoC integrations with
33 USB controller based on the DesignWare USB3 IP Core.
34
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]35config USB_XHCI_EXYNOS
36 bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
37 depends on ARCH_EXYNOS5
38 default y
39 help
40 Enables support for he on-chip xHCI controller on Samsung Exynos5
41 SoCs.
42
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]43config USB_XHCI_MTK
44 bool "Support for MediaTek on-chip xHCI USB controller"
developer4adcdca2022-05-20 11:22:56 +0800[diff] [blame]45 depends on ARCH_MEDIATEK || SOC_MT7621
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]46 help
47 Enables support for the on-chip xHCI controller on MediaTek SoCs.
48
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]49config USB_XHCI_MVEBU
50 bool "MVEBU USB 3.0 support"
51 default y
52 depends on ARCH_MVEBU
Konstantin Porotchkin1b5ed4d2017-02-12 11:10:30 +0200[diff] [blame]53 select DM_REGULATOR
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]54 help
55 Choose this option to add support for USB 3.0 driver on mvebu
56 SoCs, which includes Armada8K, Armada3700 and other Armada
57 family SoCs.
58
Stefan Roesedf33b572020-08-24 13:04:38 +0200[diff] [blame]59config USB_XHCI_OCTEON
60 bool "Support for Marvell Octeon family on-chip xHCI USB controller"
61 depends on ARCH_OCTEON
62 default y
63 help
64 Enables support for the on-chip xHCI controller on Marvell Octeon
65 family SoCs. This is a driver for the dwc3 to provide the glue logic
66 to configure the controller.
67
Tom Riniebc1c842021-09-12 20:32:22 -0400[diff] [blame]68config USB_XHCI_OMAP
69 bool "Support for TI OMAP family xHCI USB controller"
70 depends on ARCH_OMAP2PLUS
71 help
72 Enables support for the on-chip xHCI controller found on some TI SoC
73 families. Note that some families have multiple contollers while
74 others only have something such as DesignWare-based controllers.
75 Consult the SoC documentation to determine if this option applies
76 to your hardware.
77
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]78config USB_XHCI_PCI
79 bool "Support for PCI-based xHCI USB controller"
Bin Meng7e8644d2017-07-19 21:51:07 +0800[diff] [blame]80 depends on DM_USB
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]81 default y if X86
82 help
83 Enables support for the PCI-based xHCI controller.
84
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]85config USB_XHCI_RCAR
86 bool "Renesas RCar USB 3.0 support"
87 default y
88 depends on ARCH_RMOBILE
89 help
90 Choose this option to add support for USB 3.0 driver on Renesas
91 RCar Gen3 SoCs.
92
Patrice Chotardf2505b12017-09-05 11:04:24 +0200[diff] [blame]93config USB_XHCI_STI
94 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
95 depends on ARCH_STI
96 default y
97 help
98 Enables support for the on-chip xHCI controller on STMicroelectronics
99 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
100 to configure the controller.
101
Uri Mashiachf6ff74e2017-02-23 15:39:36 +0200[diff] [blame]102config USB_XHCI_DRA7XX_INDEX
103 int "DRA7XX xHCI USB index"
104 range 0 1
105 default 0
106 depends on DRA7XX
107 help
108 Select the DRA7XX xHCI USB index.
109 Current supported values: 0, 1.
110
Ran Wanga5a97352017-10-23 10:09:22 +0800[diff] [blame]111config USB_XHCI_FSL
112 bool "Support for NXP Layerscape on-chip xHCI USB controller"
113 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
114 depends on !SPL_NO_USB
115 help
116 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
Rayagonda Kokatanurf59d24e2020-04-09 09:23:15 +0530[diff] [blame]117
118config USB_XHCI_BRCM
119 bool "Broadcom USB3 Host XHCI controller"
120 depends on DM_USB
121 help
122 USB controller based on the Broadcom USB3 IP Core.
123 Supports USB2/3 functionality.
124
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]125endif # USB_XHCI_HCD
Alexey Brodkin83fd3122015-12-14 17:18:50 +0300[diff] [blame]126
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]127config EHCI_DESC_BIG_ENDIAN
128 bool
129
130config EHCI_MMIO_BIG_ENDIAN
131 bool
132
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]133config USB_EHCI_HCD
134 bool "EHCI HCD (USB 2.0) support"
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]135 default y if ARCH_MX5 || ARCH_MX6
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]136 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]137 select USB_HOST
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]138 select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN
139 select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]140 ---help---
141 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
142 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
143 If your USB host controller supports USB 2.0, you will likely want to
144 configure this Host Controller Driver.
145
146 EHCI controllers are packaged with "companion" host controllers (OHCI
147 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
148 will connect to EHCI if the device is high speed, otherwise they
149 connect to a companion controller. If you configure EHCI, you should
150 probably configure the OHCI (for NEC and some other vendors) USB Host
151 Controller Driver or UHCI (for Via motherboards) Host Controller
152 Driver too.
153
154 You may want to read <file:Documentation/usb/ehci.txt>.
155
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]156if USB_EHCI_HCD
157
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]158config USB_EHCI_IS_TDI
159 bool
160
Wenyou Yang11e26652016-08-05 08:57:35 +0800[diff] [blame]161config USB_EHCI_ATMEL
162 bool "Support for Atmel on-chip EHCI USB controller"
163 depends on ARCH_AT91
164 default y
165 ---help---
166 Enables support for the on-chip EHCI controller on Atmel chips.
167
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]168config USB_EHCI_EXYNOS
169 bool "Support for Samsung Exynos EHCI USB controller"
170 depends on ARCH_EXYNOS
171 default y
172 ---help---
173 Enables support for the on-chip EHCI controller on Samsung Exynos
174 SoCs.
175
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]176config USB_EHCI_MARVELL
Tom Rini496a4172017-05-12 22:33:29 -0400[diff] [blame]177 bool "Support for Marvell on-chip EHCI USB controller"
Trevor Woernerbb7ab072020-05-06 08:02:40 -0400[diff] [blame]178 depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]179 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]180 select USB_EHCI_IS_TDI if !ARM64
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]181 ---help---
182 Enables support for the on-chip EHCI controller on MVEBU SoCs.
183
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]184config USB_EHCI_MX5
185 bool "Support for i.MX5 on-chip EHCI USB controller"
186 depends on ARCH_MX5
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]187 help
188 Enables support for the on-chip EHCI controller on i.MX5 SoCs.
189
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]190config USB_EHCI_MX6
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]191 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200[diff] [blame]192 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]193 select EHCI_HCD_INIT_AFTER_RESET
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]194 default y
195 ---help---
196 Enables support for the on-chip EHCI controller on i.MX6 SoCs.
197
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]198config USB_EHCI_MX7
199 bool "Support for i.MX7 on-chip EHCI USB controller"
Marek Vasute15971f2021-04-02 14:07:22 +0200[diff] [blame]200 depends on ARCH_MX7 || IMX8M
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]201 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
Marek Vasute15971f2021-04-02 14:07:22 +0200[diff] [blame]202 select PHY if IMX8M
203 select NOP_PHY if IMX8M
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]204 default y
205 ---help---
206 Enables support for the on-chip EHCI controller on i.MX7 SoCs.
207
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]208config USB_EHCI_MXS
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]209 bool "Support for i.MX23/i.MX28 EHCI USB controller"
210 depends on ARCH_MX23 || ARCH_MX28
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]211 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]212 select USB_EHCI_IS_TDI
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]213 help
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]214 Enables support for the on-chip EHCI controller on i.MX23 and
215 i.MX28 SoCs.
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]216
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame^]217config USB_EHCI_NPCM
218 bool "Support for Nuvoton NPCM on-chip EHCI USB controller"
219 depends on ARCH_NPCM
220 default n
221 ---help---
222 Enables support for the on-chip EHCI controller on
223 Nuvoton NPCM chips.
224
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]225config USB_EHCI_OMAP
226 bool "Support for OMAP3+ on-chip EHCI USB controller"
227 depends on ARCH_OMAP2PLUS
Adam Fordcb9a3562022-02-19 17:08:44 -0600[diff] [blame]228 select PHY
229 imply NOP_PHY
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]230 default y
231 ---help---
232 Enables support for the on-chip EHCI controller on OMAP3 and later
233 SoCs.
234
Marcel Ziswiler31f44952019-03-25 17:24:54 +0100[diff] [blame]235config USB_EHCI_VF
236 bool "Support for Vybrid on-chip EHCI USB controller"
237 depends on ARCH_VF610
238 default y
239 help
240 Enables support for the on-chip EHCI controller on Vybrid SoCs.
241
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]242if USB_EHCI_MX6 || USB_EHCI_MX7
Stefan Agner8652ce92016-07-13 00:25:38 -0700[diff] [blame]243
244config MXC_USB_OTG_HACTIVE
245 bool "USB Power pin high active"
246 ---help---
247 Set the USB Power pin polarity to be high active (PWR_POL)
248
249endif
250
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]251config USB_EHCI_MSM
252 bool "Support for Qualcomm on-chip EHCI USB controller"
253 depends on DM_USB
254 select USB_ULPI_VIEWPORT
Ramon Fried7e365962018-09-21 13:35:50 +0300[diff] [blame]255 select MSM8916_USB_PHY
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]256 ---help---
257 Enables support for the on-chip EHCI controller on Qualcomm
258 Snapdragon SoCs.
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]259
Bin Mengec4b5732017-08-09 00:21:54 -0700[diff] [blame]260config USB_EHCI_PCI
261 bool "Support for PCI-based EHCI USB controller"
262 default y if X86
263 help
264 Enables support for the PCI-based EHCI controller.
265
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]266config USB_EHCI_TEGRA
267 bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]268 depends on ARCH_TEGRA
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]269 select USB_EHCI_IS_TDI
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]270 ---help---
271 Enable support for Tegra on-chip EHCI USB controller
272
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]273config USB_EHCI_ZYNQ
274 bool "Support for Xilinx Zynq on-chip EHCI USB controller"
Michal Simek3239d712020-08-24 14:41:51 +0200[diff] [blame]275 default y if ARCH_ZYNQ
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]276 select USB_EHCI_IS_TDI
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]277 ---help---
278 Enable support for Zynq on-chip EHCI USB controller
279
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]280config USB_EHCI_GENERIC
281 bool "Support for generic EHCI USB controller"
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]282 depends on DM_USB
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]283 default ARCH_SUNXI
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]284 ---help---
285 Enables support for generic EHCI controller.
286
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]287config EHCI_HCD_INIT_AFTER_RESET
288 bool
289
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]290config USB_EHCI_FSL
291 bool "Support for FSL on-chip EHCI USB controller"
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]292 select EHCI_HCD_INIT_AFTER_RESET
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]293 select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
294 !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]295 ---help---
296 Enables support for the on-chip EHCI controller on FSL chips.
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]297
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]298config SYS_FSL_USB_INTERNAL_UTMI_PHY
299 bool
300 depends on USB_EHCI_FSL
301
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]302config USB_EHCI_TXFIFO_THRESH
303 hex
304 depends on USB_EHCI_TEGRA
305 default 0x10
306 help
307 This parameter affects a TXFILLTUNING field that controls how much
308 data is sent to the latency fifo before it is sent to the wire.
309 Without this parameter, the default (2) causes occasional Data Buffer
310 Errors in OUT packets depending on the buffer address and size.
311
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]312endif # USB_EHCI_HCD
313
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]314config USB_OHCI_NEW
315 bool
316
317config SYS_USB_OHCI_CPU_INIT
318 bool
319
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]320config USB_OHCI_HCD
321 bool "OHCI HCD (USB 1.1) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]322 depends on DM && OF_CONTROL
323 select USB_HOST
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]324 select USB_OHCI_NEW
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]325 ---help---
326 The Open Host Controller Interface (OHCI) is a standard for accessing
327 USB 1.1 host controller hardware. It does more in hardware than Intel's
328 UHCI specification. If your USB host controller follows the OHCI spec,
329 say Y. On most non-x86 systems, and on x86 hardware that's not using a
330 USB controller from Intel or VIA, this is appropriate. If your host
331 controller doesn't use PCI, this is probably appropriate. For a PCI
332 based system where you're not sure, the "lspci -v" entry will list the
333 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
334
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]335if USB_OHCI_HCD
336
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]337config USB_OHCI_PCI
338 bool "Support for PCI-based OHCI USB controller"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]339 depends on PCI
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]340 help
341 Enables support for the PCI-based OHCI controller.
342
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]343config USB_OHCI_GENERIC
344 bool "Support for generic OHCI USB controller"
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]345 default ARCH_SUNXI
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]346 ---help---
347 Enables support for generic OHCI controller.
348
Adam Ford5f364f52019-04-30 05:21:41 -0500[diff] [blame]349config USB_OHCI_DA8XX
350 bool "Support for da850 OHCI USB controller"
351 help
352 Enable support for the da850 USB controller.
353
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame^]354config USB_OHCI_NPCM
355 bool "Support for Nuvoton NPCM on-chip OHCI USB controller"
356 depends on ARCH_NPCM
357 default n
358 ---help---
359 Enables support for the on-chip OHCI controller on
360 Nuvoton NPCM chips.
361
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]362endif # USB_OHCI_HCD
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]363
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]364config SYS_USB_OHCI_SLOT_NAME
365 string "Display name for the OHCI controller"
366 depends on USB_OHCI_NEW && !DM_USB
367
368config SYS_USB_OHCI_MAX_ROOT_PORTS
369 int "Maximal number of ports of the root hub"
370 depends on USB_OHCI_NEW
371 default 1 if ARCH_SUNXI
372
373config SYS_OHCI_SWAP_REG_ACCESS
374 bool "Perform byte swapping on OHCI controller register accesses"
375 depends on USB_OHCI_NEW
376
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]377config USB_UHCI_HCD
378 bool "UHCI HCD (most Intel and VIA) support"
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]379 select USB_HOST
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]380 ---help---
381 The Universal Host Controller Interface is a standard by Intel for
382 accessing the USB hardware in the PC (which is also called the USB
383 host controller). If your USB host controller conforms to this
384 standard, you may want to say Y, but see below. All recent boards
385 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
386 i810, i820) conform to this standard. Also all VIA PCI chipsets
387 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
388 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
389 If unsure, say Y.
390
391if USB_UHCI_HCD
392
393endif # USB_UHCI_HCD
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]394
395config USB_DWC2
396 bool "DesignWare USB2 Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]397 depends on DM && OF_CONTROL
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]398 select USB_HOST
399 ---help---
400 The DesignWare USB 2.0 controller is compliant with the
401 USB-Implementers Forum (USB-IF) USB 2.0 specifications.
402 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
403 operation is compliant to the controller Supplement. If you want to
404 enable this controller in host mode, say Y.
Alexey Brodkinf19414b2018-02-28 16:16:58 +0300[diff] [blame]405
406if USB_DWC2
407config USB_DWC2_BUFFER_SIZE
408 int "Data buffer size in kB"
409 default 64
410 ---help---
411 By default 64 kB buffer is used but if amount of RAM avaialble on
412 the target is not enough to accommodate allocation of buffer of
413 that size it is possible to shrink it. Smaller sizes should be fine
414 because larger transactions could be split in smaller ones.
415
416endif # USB_DWC2
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]417
418config USB_R8A66597_HCD
419 bool "Renesas R8A66597 USB Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]420 depends on DM && OF_CONTROL
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]421 select USB_HOST
422 ---help---
423 This enables support for the on-chip Renesas R8A66597 USB 2.0
424 controller, present in various RZ and SH SoCs.
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]425
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]426config USB_ATMEL
427 bool "AT91 OHCI USB support"
428 depends on ARCH_AT91
429 select SYS_USB_OHCI_CPU_INIT
430 select USB_OHCI_NEW
431
432choice
433 prompt "Clock for OHCI"
434 depends on USB_ATMEL
435
436config USB_ATMEL_CLK_SEL_PLLB
437 bool "PLLB"
438
439config USB_ATMEL_CLK_SEL_UPLL
440 bool "UPLL"
441
442endchoice
443
444config USB_OHCI_LPC32XX
445 bool "LPC32xx USB OHCI support"
446 depends on ARCH_LPC32XX
447 select SYS_USB_OHCI_CPU_INIT
448 select USB_OHCI_NEW
449
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]450config USB_MAX_CONTROLLER_COUNT
451 int "Maximum number of USB host controllers"
452 depends on USB_EHCI_FSL || USB_XHCI_FSL || \
453 (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB)
454 default 1