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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren41b68382011-01-27 10:58:05 +00002/*
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warren41b68382011-01-27 10:58:05 +00005 */
6
7#include <common.h>
Simon Glass74472ac2014-11-10 17:16:51 -07008#include <dm.h>
Simon Glass5e6201b2019-08-01 09:46:51 -06009#include <env.h>
Simon Glass0655c912015-04-14 21:03:28 -060010#include <errno.h>
Simon Glass6980b6b2019-11-14 12:57:45 -070011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Tom Warren41b68382011-01-27 10:58:05 +000013#include <ns16550.h>
Simon Glass15023922017-06-12 06:21:39 -060014#include <usb.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Tom Warren41b68382011-01-27 10:58:05 +000016#include <asm/io.h>
Stephen Warren8d1fb312015-01-19 16:25:52 -070017#include <asm/arch-tegra/ap.h>
Tom Warrenab371962012-09-19 15:50:56 -070018#include <asm/arch-tegra/board.h>
Thierry Reding7cef2b22019-04-15 11:32:28 +020019#include <asm/arch-tegra/cboot.h>
Tom Warrenab371962012-09-19 15:50:56 -070020#include <asm/arch-tegra/clk_rst.h>
21#include <asm/arch-tegra/pmc.h>
Thierry Redingcf390082019-04-15 11:32:17 +020022#include <asm/arch-tegra/pmu.h>
Tom Warrenab371962012-09-19 15:50:56 -070023#include <asm/arch-tegra/sys_proto.h>
24#include <asm/arch-tegra/uart.h>
25#include <asm/arch-tegra/warmboot.h>
Alexandre Courbot7f936d42015-07-09 16:33:00 +090026#include <asm/arch-tegra/gpu.h>
Simon Glass15023922017-06-12 06:21:39 -060027#include <asm/arch-tegra/usb.h>
28#include <asm/arch-tegra/xusb-padctl.h>
Thierry Reding45ad0b02019-04-15 11:32:18 +020029#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
Simon Glass15023922017-06-12 06:21:39 -060030#include <asm/arch/clock.h>
Thierry Reding45ad0b02019-04-15 11:32:18 +020031#endif
Thierry Reding7c0b1502019-04-15 11:32:21 +020032#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
Simon Glass15023922017-06-12 06:21:39 -060033#include <asm/arch/funcmux.h>
34#include <asm/arch/pinmux.h>
Thierry Reding7c0b1502019-04-15 11:32:21 +020035#endif
Simon Glass15023922017-06-12 06:21:39 -060036#include <asm/arch/tegra.h>
Tom Warrend32b2a42012-12-11 13:34:17 +000037#ifdef CONFIG_TEGRA_CLOCK_SCALING
38#include <asm/arch/emc.h>
39#endif
Jimmy Zhanga308d462012-04-10 05:17:06 +000040#include "emc.h"
Tom Warren41b68382011-01-27 10:58:05 +000041
42DECLARE_GLOBAL_DATA_PTR;
43
Simon Glass74472ac2014-11-10 17:16:51 -070044#ifdef CONFIG_SPL_BUILD
45/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
Simon Glass1d8364a2020-12-28 20:34:54 -070046U_BOOT_DRVINFO(tegra_gpios) = {
Simon Glass74472ac2014-11-10 17:16:51 -070047 "gpio_tegra"
48};
49#endif
50
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020051__weak void pinmux_init(void) {}
52__weak void pin_mux_usb(void) {}
53__weak void pin_mux_spi(void) {}
Stephen Warrenc044fe22016-09-13 10:45:47 -060054__weak void pin_mux_mmc(void) {}
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020055__weak void gpio_early_init_uart(void) {}
56__weak void pin_mux_display(void) {}
Tom Warrenf3035ca2015-02-20 12:22:22 -070057__weak void start_cpu_fan(void) {}
Thierry Reding7cef2b22019-04-15 11:32:28 +020058__weak void cboot_late_init(void) {}
Lucas Stach18561f72012-09-25 20:21:14 +000059
Tom Warren6b33c832014-01-24 12:46:11 -070060#if defined(CONFIG_TEGRA_NAND)
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020061__weak void pin_mux_nand(void)
Lucas Stach04585842012-09-29 10:02:09 +000062{
63 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
64}
Tom Warren6b33c832014-01-24 12:46:11 -070065#endif
Lucas Stach04585842012-09-29 10:02:09 +000066
Tom Warren41b68382011-01-27 10:58:05 +000067/*
Wei Ni39d45ed2012-04-02 13:18:58 +000068 * Routine: power_det_init
69 * Description: turn off power detects
70 */
71static void power_det_init(void)
72{
Allen Martin55d98a12012-08-31 08:30:00 +000073#if defined(CONFIG_TEGRA20)
Tom Warren22562a42012-09-04 17:00:24 -070074 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
Wei Ni39d45ed2012-04-02 13:18:58 +000075
76 /* turn off power detects */
77 writel(0, &pmc->pmc_pwr_det_latch);
78 writel(0, &pmc->pmc_pwr_det);
79#endif
80}
Simon Glass675804d2015-04-14 21:03:24 -060081
Simon Glass69c93c72015-04-14 21:03:25 -060082__weak int tegra_board_id(void)
83{
84 return -1;
85}
86
Simon Glass675804d2015-04-14 21:03:24 -060087#ifdef CONFIG_DISPLAY_BOARDINFO
88int checkboard(void)
89{
Simon Glass69c93c72015-04-14 21:03:25 -060090 int board_id = tegra_board_id();
91
Tom Rinica2e1a52022-12-04 10:13:58 -050092 printf("Board: %s", CFG_TEGRA_BOARD_STRING);
Simon Glass69c93c72015-04-14 21:03:25 -060093 if (board_id != -1)
94 printf(", ID: %d\n", board_id);
95 printf("\n");
Simon Glass675804d2015-04-14 21:03:24 -060096
97 return 0;
98}
99#endif /* CONFIG_DISPLAY_BOARDINFO */
Wei Ni39d45ed2012-04-02 13:18:58 +0000100
Simon Glass0cf62dd2015-04-14 21:03:27 -0600101__weak int tegra_lcd_pmic_init(int board_it)
102{
103 return 0;
104}
105
Simon Glass44a68082015-06-05 14:39:42 -0600106__weak int nvidia_board_init(void)
107{
108 return 0;
109}
110
Wei Ni39d45ed2012-04-02 13:18:58 +0000111/*
Tom Warren41b68382011-01-27 10:58:05 +0000112 * Routine: board_init
113 * Description: Early hardware init.
114 */
115int board_init(void)
116{
Jimmy Zhanga308d462012-04-10 05:17:06 +0000117 __maybe_unused int err;
Simon Glass0cf62dd2015-04-14 21:03:27 -0600118 __maybe_unused int board_id;
Jimmy Zhanga308d462012-04-10 05:17:06 +0000119
Simon Glass704e60d2011-11-05 04:46:51 +0000120 /* Do clocks and UART first so that printf() works */
Thierry Reding45ad0b02019-04-15 11:32:18 +0200121#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
Simon Glassc2ea5e42011-09-21 12:40:04 +0000122 clock_init();
123 clock_verify();
Thierry Reding45ad0b02019-04-15 11:32:18 +0200124#endif
Simon Glassc2ea5e42011-09-21 12:40:04 +0000125
Alexandre Courbotf36729d2015-10-19 13:57:03 +0900126 tegra_gpu_config();
Alexandre Courbot7f936d42015-07-09 16:33:00 +0900127
Simon Glass1121b1b2014-10-13 23:42:13 -0600128#ifdef CONFIG_TEGRA_SPI
Stephen Warrend2f67fe2012-06-12 08:33:40 +0000129 pin_mux_spi();
Tom Warrenee554f82011-11-05 09:48:11 +0000130#endif
Allen Martinba4fb9b2013-01-29 13:51:28 +0000131
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900132#ifdef CONFIG_MMC_SDHCI_TEGRA
Stephen Warrenc044fe22016-09-13 10:45:47 -0600133 pin_mux_mmc();
134#endif
135
Simon Glasseb210832016-01-30 16:37:48 -0700136 /* Init is handled automatically in the driver-model case */
Simon Glass52cb5042022-10-18 07:46:31 -0600137#if defined(CONFIG_VIDEO)
Marc Dietrich9bbe64b2012-11-25 11:26:11 +0000138 pin_mux_display();
Simon Glass3e2b2d92016-01-30 16:37:49 -0700139#endif
Tom Warren41b68382011-01-27 10:58:05 +0000140 /* boot param addr */
141 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
Wei Ni39d45ed2012-04-02 13:18:58 +0000142
143 power_det_init();
144
Simon Glass026fefb2012-10-30 07:28:53 +0000145#ifdef CONFIG_SYS_I2C_TEGRA
Simon Glasse772be82012-04-02 13:18:54 +0000146# ifdef CONFIG_TEGRA_PMU
147 if (pmu_set_nominal())
148 debug("Failed to select nominal voltages\n");
Jimmy Zhanga308d462012-04-10 05:17:06 +0000149# ifdef CONFIG_TEGRA_CLOCK_SCALING
150 err = board_emc_init();
151 if (err)
152 debug("Memory controller init failed: %d\n", err);
153# endif
154# endif /* CONFIG_TEGRA_PMU */
Simon Glass026fefb2012-10-30 07:28:53 +0000155#endif /* CONFIG_SYS_I2C_TEGRA */
Tom Warren41b68382011-01-27 10:58:05 +0000156
Simon Glass5d73a8d2012-02-27 10:52:50 +0000157#ifdef CONFIG_USB_EHCI_TEGRA
158 pin_mux_usb();
Simon Glass5d73a8d2012-02-27 10:52:50 +0000159#endif
Mateusz Zalegad862f892013-10-04 19:22:26 +0200160
Simon Glass52cb5042022-10-18 07:46:31 -0600161#if defined(CONFIG_VIDEO)
Simon Glass0cf62dd2015-04-14 21:03:27 -0600162 board_id = tegra_board_id();
163 err = tegra_lcd_pmic_init(board_id);
Simon Glass9d8271e2017-06-12 06:21:59 -0600164 if (err) {
165 debug("Failed to set up LCD PMIC\n");
Simon Glass0cf62dd2015-04-14 21:03:27 -0600166 return err;
Simon Glass9d8271e2017-06-12 06:21:59 -0600167 }
Simon Glass3e2b2d92016-01-30 16:37:49 -0700168#endif
Simon Glass5d73a8d2012-02-27 10:52:50 +0000169
Lucas Stach04585842012-09-29 10:02:09 +0000170#ifdef CONFIG_TEGRA_NAND
171 pin_mux_nand();
172#endif
173
Simon Glasscf0c6e22017-07-25 08:29:59 -0600174 tegra_xusb_padctl_init();
Thierry Redingf202e022014-12-09 22:25:09 -0700175
Tom Warren22562a42012-09-04 17:00:24 -0700176#ifdef CONFIG_TEGRA_LP0
Allen Martin0ca1a452012-08-31 08:30:11 +0000177 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
178 warmboot_save_sdram_params();
179
Simon Glass8cc8f612012-04-02 13:18:57 +0000180 /* prepare the WB code to LP0 location */
181 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
182#endif
Simon Glass44a68082015-06-05 14:39:42 -0600183 return nvidia_board_init();
Tom Warren41b68382011-01-27 10:58:05 +0000184}
Simon Glassdfcee792011-09-21 12:40:03 +0000185
JC Kuof479aca2020-03-26 16:10:09 -0700186void board_cleanup_before_linux(void)
187{
188 /* power down UPHY PLL */
189 tegra_xusb_padctl_exit();
190}
191
Simon Glassdfcee792011-09-21 12:40:03 +0000192#ifdef CONFIG_BOARD_EARLY_INIT_F
Thierry Reding2fa4db02012-06-04 20:02:27 +0000193static void __gpio_early_init(void)
194{
195}
196
197void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
198
Simon Glassdfcee792011-09-21 12:40:03 +0000199int board_early_init_f(void)
200{
Thierry Reding45ad0b02019-04-15 11:32:18 +0200201#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
Simon Glass2b4029a2017-05-31 17:57:16 -0600202 if (!clock_early_init_done())
203 clock_early_init();
Thierry Reding45ad0b02019-04-15 11:32:18 +0200204#endif
Simon Glass2b4029a2017-05-31 17:57:16 -0600205
Stephen Warren5a44ab42016-01-26 10:59:42 -0700206#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
207#define USBCMD_FS2 (1 << 15)
208 {
209 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
210 writel(USBCMD_FS2, &usbctlr->usb_cmd);
211 }
212#endif
213
Thierry Redingff81d752015-07-28 11:35:53 +0200214 /* Do any special system timer/TSC setup */
Thierry Reding45ad0b02019-04-15 11:32:18 +0200215#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
216# if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
Thierry Redingff81d752015-07-28 11:35:53 +0200217 if (!tegra_cpu_is_non_secure())
Thierry Reding45ad0b02019-04-15 11:32:18 +0200218# endif
Thierry Redingff81d752015-07-28 11:35:53 +0200219 arch_timer_init();
Thierry Reding45ad0b02019-04-15 11:32:18 +0200220#endif
Thierry Redingff81d752015-07-28 11:35:53 +0200221
Tom Warren872111a2020-02-28 16:17:07 -0700222#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
223 /*
224 * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
225 * We do this because earlier bootloaders have enabled power to
226 * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
227 * results in power being back-driven into the SD-card and SDMMC1
228 * HW, which is 'bad' as per the HW team.
229 *
230 * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
231 * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
232 * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
233 * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
234 * voltage turns off. Since the SDCard voltage is no longer there, the
235 * SDMMC CLK/DAT lines are backdriving into what essentially is a
236 * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
237 *
238 * Note that this can probably be removed when we change over to storing
239 * all BL components on QSPI on Nano, and U-Boot then becomes the first
240 * one to turn on SDMMC1 power. Another fix would be to have CBoot
241 * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
242 */
243 reset_set_enable(PERIPH_ID_SDMMC1, 1);
244 clock_set_enable(PERIPH_ID_SDMMC1, 0);
245#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
246
Tom Warrend32b2a42012-12-11 13:34:17 +0000247 pinmux_init();
Simon Glassa8ccc8b2011-11-28 15:04:40 +0000248 board_init_uart_f();
Simon Glassdfcee792011-09-21 12:40:03 +0000249
250 /* Initialize periph GPIOs */
Thierry Reding2fa4db02012-06-04 20:02:27 +0000251 gpio_early_init();
Simon Glass704e60d2011-11-05 04:46:51 +0000252 gpio_early_init_uart();
Lucas Stach18561f72012-09-25 20:21:14 +0000253
Simon Glassdfcee792011-09-21 12:40:03 +0000254 return 0;
255}
256#endif /* EARLY_INIT */
Simon Glass4f476f32012-10-17 13:24:52 +0000257
258int board_late_init(void)
259{
Stephen Warren8d1fb312015-01-19 16:25:52 -0700260#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
261 if (tegra_cpu_is_non_secure()) {
262 printf("CPU is in NS mode\n");
Simon Glass6a38e412017-08-03 12:22:09 -0600263 env_set("cpu_ns_mode", "1");
Stephen Warren8d1fb312015-01-19 16:25:52 -0700264 } else {
Simon Glass6a38e412017-08-03 12:22:09 -0600265 env_set("cpu_ns_mode", "");
Stephen Warren8d1fb312015-01-19 16:25:52 -0700266 }
267#endif
Tom Warrenf3035ca2015-02-20 12:22:22 -0700268 start_cpu_fan();
Thierry Reding7cef2b22019-04-15 11:32:28 +0200269 cboot_late_init();
Tom Warrenf3035ca2015-02-20 12:22:22 -0700270
Simon Glass4f476f32012-10-17 13:24:52 +0000271 return 0;
272}
Thierry Reding6d835fa2015-07-27 11:45:24 -0600273
Stephen Warren3ffd0902015-08-07 16:12:45 -0600274/*
275 * In some SW environments, a memory carve-out exists to house a secure
276 * monitor, a trusted OS, and/or various statically allocated media buffers.
277 *
278 * This carveout exists at the highest possible address that is within a
279 * 32-bit physical address space.
280 *
281 * This function returns the total size of this carve-out. At present, the
282 * returned value is hard-coded for simplicity. In the future, it may be
283 * possible to determine the carve-out size:
284 * - By querying some run-time information source, such as:
285 * - A structure passed to U-Boot by earlier boot software.
286 * - SoC registers.
287 * - A call into the secure monitor.
288 * - In the per-board U-Boot configuration header, based on knowledge of the
289 * SW environment that U-Boot is being built for.
290 *
291 * For now, we support two configurations in U-Boot:
292 * - 32-bit ports without any form of carve-out.
293 * - 64 bit ports which are assumed to use a carve-out of a conservatively
294 * hard-coded size.
295 */
296static ulong carveout_size(void)
297{
Thierry Reding6d835fa2015-07-27 11:45:24 -0600298#ifdef CONFIG_ARM64
Stephen Warren3ffd0902015-08-07 16:12:45 -0600299 return SZ_512M;
Stephen Warrenc12800f2018-06-22 13:03:19 -0600300#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
301 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
302 // from BASE to 4GB, not BASE to BASE+SIZE.
Stephen Warrena963a782018-07-31 12:38:27 -0600303 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
Stephen Warren3ffd0902015-08-07 16:12:45 -0600304#else
305 return 0;
306#endif
307}
308
309/*
310 * Determine the amount of usable RAM below 4GiB, taking into account any
311 * carve-out that may be assigned.
312 */
313static ulong usable_ram_size_below_4g(void)
314{
315 ulong total_size_below_4g;
316 ulong usable_size_below_4g;
317
318 /*
319 * The total size of RAM below 4GiB is the lesser address of:
320 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
321 * (b) The size RAM physically present in the system.
322 */
323 if (gd->ram_size < SZ_2G)
324 total_size_below_4g = gd->ram_size;
325 else
326 total_size_below_4g = SZ_2G;
327
328 /* Calculate usable RAM by subtracting out any carve-out size */
329 usable_size_below_4g = total_size_below_4g - carveout_size();
330
331 return usable_size_below_4g;
332}
333
334/*
335 * Represent all available RAM in either one or two banks.
336 *
337 * The first bank describes any usable RAM below 4GiB.
338 * The second bank describes any RAM above 4GiB.
339 *
340 * This split is driven by the following requirements:
341 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
342 * property for memory below and above the 4GiB boundary. The layout of that
343 * DT property is directly driven by the entries in the U-Boot bank array.
344 * - The potential existence of a carve-out at the end of RAM below 4GiB can
345 * only be represented using multiple banks.
346 *
347 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
348 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
349 * command-line.
350 *
351 * This does mean that the DT U-Boot passes to the Linux kernel will not
352 * include this RAM in /memory/reg at all. An alternative would be to include
353 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
354 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
355 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
356 * mapping, so either way is acceptable.
357 *
358 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
359 * start address of that bank cannot be represented in the 32-bit .size
360 * field.
361 */
Simon Glass2f949c32017-03-31 08:40:32 -0600362int dram_init_banksize(void)
Stephen Warren3ffd0902015-08-07 16:12:45 -0600363{
Thierry Reding7cef2b22019-04-15 11:32:28 +0200364 int err;
365
366 /* try to compute DRAM bank size based on cboot DTB first */
367 err = cboot_dram_init_banksize();
368 if (err == 0)
369 return err;
370
371 /* fall back to default DRAM bank size computation */
372
Tom Rinibb4dd962022-11-16 13:10:37 -0500373 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Stephen Warren3ffd0902015-08-07 16:12:45 -0600374 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
375
Simon Glass46fcfc12015-11-19 20:27:02 -0700376#ifdef CONFIG_PCI
377 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
378#endif
379
Stephen Warren3ffd0902015-08-07 16:12:45 -0600380#ifdef CONFIG_PHYS_64BIT
381 if (gd->ram_size > SZ_2G) {
382 gd->bd->bi_dram[1].start = 0x100000000;
383 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
384 } else
385#endif
386 {
387 gd->bd->bi_dram[1].start = 0;
388 gd->bd->bi_dram[1].size = 0;
389 }
Simon Glass2f949c32017-03-31 08:40:32 -0600390
391 return 0;
Stephen Warren3ffd0902015-08-07 16:12:45 -0600392}
393
Thierry Reding6d835fa2015-07-27 11:45:24 -0600394/*
395 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
396 * 32-bits of the physical address space. Cap the maximum usable RAM area
397 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
Stephen Warren3ffd0902015-08-07 16:12:45 -0600398 * boundary that most devices can address. Also, don't let U-Boot use any
399 * carve-out, as mentioned above.
Stephen Warren30d19662015-07-29 13:47:58 -0600400 *
Stephen Warren3ffd0902015-08-07 16:12:45 -0600401 * This function is called before dram_init_banksize(), so we can't simply
402 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
Thierry Reding6d835fa2015-07-27 11:45:24 -0600403 */
Pali Rohár4f4f5832022-09-09 17:32:40 +0200404phys_size_t board_get_usable_ram_top(phys_size_t total_size)
Thierry Reding6d835fa2015-07-27 11:45:24 -0600405{
Thierry Reding7cef2b22019-04-15 11:32:28 +0200406 ulong ram_top;
407
408 /* try to get top of usable RAM based on cboot DTB first */
409 ram_top = cboot_get_usable_ram_top(total_size);
410 if (ram_top > 0)
411 return ram_top;
412
413 /* fall back to default usable RAM computation */
414
Tom Rinibb4dd962022-11-16 13:10:37 -0500415 return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
Thierry Reding6d835fa2015-07-27 11:45:24 -0600416}