Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010,2011 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 74472ac | 2014-11-10 17:16:51 -0700 | [diff] [blame] | 8 | #include <dm.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 9 | #include <env.h> |
Simon Glass | 0655c91 | 2015-04-14 21:03:28 -0600 | [diff] [blame] | 10 | #include <errno.h> |
Simon Glass | 6980b6b | 2019-11-14 12:57:45 -0700 | [diff] [blame] | 11 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 13 | #include <ns16550.h> |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 14 | #include <usb.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 15 | #include <asm/global_data.h> |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 16 | #include <asm/io.h> |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 17 | #include <asm/arch-tegra/ap.h> |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 18 | #include <asm/arch-tegra/board.h> |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 19 | #include <asm/arch-tegra/cboot.h> |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 20 | #include <asm/arch-tegra/clk_rst.h> |
| 21 | #include <asm/arch-tegra/pmc.h> |
Thierry Reding | cf39008 | 2019-04-15 11:32:17 +0200 | [diff] [blame] | 22 | #include <asm/arch-tegra/pmu.h> |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 23 | #include <asm/arch-tegra/sys_proto.h> |
| 24 | #include <asm/arch-tegra/uart.h> |
| 25 | #include <asm/arch-tegra/warmboot.h> |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 26 | #include <asm/arch-tegra/gpu.h> |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 27 | #include <asm/arch-tegra/usb.h> |
| 28 | #include <asm/arch-tegra/xusb-padctl.h> |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 29 | #if IS_ENABLED(CONFIG_TEGRA_CLKRST) |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 30 | #include <asm/arch/clock.h> |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 31 | #endif |
Thierry Reding | 7c0b150 | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 32 | #if IS_ENABLED(CONFIG_TEGRA_PINCTRL) |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 33 | #include <asm/arch/funcmux.h> |
| 34 | #include <asm/arch/pinmux.h> |
Thierry Reding | 7c0b150 | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 35 | #endif |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 36 | #include <asm/arch/tegra.h> |
Tom Warren | d32b2a4 | 2012-12-11 13:34:17 +0000 | [diff] [blame] | 37 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
| 38 | #include <asm/arch/emc.h> |
| 39 | #endif |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 40 | #include "emc.h" |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 41 | |
| 42 | DECLARE_GLOBAL_DATA_PTR; |
| 43 | |
Simon Glass | 74472ac | 2014-11-10 17:16:51 -0700 | [diff] [blame] | 44 | #ifdef CONFIG_SPL_BUILD |
| 45 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ |
Simon Glass | 1d8364a | 2020-12-28 20:34:54 -0700 | [diff] [blame] | 46 | U_BOOT_DRVINFO(tegra_gpios) = { |
Simon Glass | 74472ac | 2014-11-10 17:16:51 -0700 | [diff] [blame] | 47 | "gpio_tegra" |
| 48 | }; |
| 49 | #endif |
| 50 | |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 51 | __weak void pinmux_init(void) {} |
| 52 | __weak void pin_mux_usb(void) {} |
| 53 | __weak void pin_mux_spi(void) {} |
Stephen Warren | c044fe2 | 2016-09-13 10:45:47 -0600 | [diff] [blame] | 54 | __weak void pin_mux_mmc(void) {} |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 55 | __weak void gpio_early_init_uart(void) {} |
| 56 | __weak void pin_mux_display(void) {} |
Tom Warren | f3035ca | 2015-02-20 12:22:22 -0700 | [diff] [blame] | 57 | __weak void start_cpu_fan(void) {} |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 58 | __weak void cboot_late_init(void) {} |
Lucas Stach | 18561f7 | 2012-09-25 20:21:14 +0000 | [diff] [blame] | 59 | |
Tom Warren | 6b33c83 | 2014-01-24 12:46:11 -0700 | [diff] [blame] | 60 | #if defined(CONFIG_TEGRA_NAND) |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 61 | __weak void pin_mux_nand(void) |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 62 | { |
| 63 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); |
| 64 | } |
Tom Warren | 6b33c83 | 2014-01-24 12:46:11 -0700 | [diff] [blame] | 65 | #endif |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 66 | |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 67 | /* |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 68 | * Routine: power_det_init |
| 69 | * Description: turn off power detects |
| 70 | */ |
| 71 | static void power_det_init(void) |
| 72 | { |
Allen Martin | 55d98a1 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 73 | #if defined(CONFIG_TEGRA20) |
Tom Warren | 22562a4 | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 74 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 75 | |
| 76 | /* turn off power detects */ |
| 77 | writel(0, &pmc->pmc_pwr_det_latch); |
| 78 | writel(0, &pmc->pmc_pwr_det); |
| 79 | #endif |
| 80 | } |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 81 | |
Simon Glass | 69c93c7 | 2015-04-14 21:03:25 -0600 | [diff] [blame] | 82 | __weak int tegra_board_id(void) |
| 83 | { |
| 84 | return -1; |
| 85 | } |
| 86 | |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 87 | #ifdef CONFIG_DISPLAY_BOARDINFO |
| 88 | int checkboard(void) |
| 89 | { |
Simon Glass | 69c93c7 | 2015-04-14 21:03:25 -0600 | [diff] [blame] | 90 | int board_id = tegra_board_id(); |
| 91 | |
Tom Rini | ca2e1a5 | 2022-12-04 10:13:58 -0500 | [diff] [blame] | 92 | printf("Board: %s", CFG_TEGRA_BOARD_STRING); |
Simon Glass | 69c93c7 | 2015-04-14 21:03:25 -0600 | [diff] [blame] | 93 | if (board_id != -1) |
| 94 | printf(", ID: %d\n", board_id); |
| 95 | printf("\n"); |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | #endif /* CONFIG_DISPLAY_BOARDINFO */ |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 100 | |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 101 | __weak int tegra_lcd_pmic_init(int board_it) |
| 102 | { |
| 103 | return 0; |
| 104 | } |
| 105 | |
Simon Glass | 44a6808 | 2015-06-05 14:39:42 -0600 | [diff] [blame] | 106 | __weak int nvidia_board_init(void) |
| 107 | { |
| 108 | return 0; |
| 109 | } |
| 110 | |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 111 | /* |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 112 | * Routine: board_init |
| 113 | * Description: Early hardware init. |
| 114 | */ |
| 115 | int board_init(void) |
| 116 | { |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 117 | __maybe_unused int err; |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 118 | __maybe_unused int board_id; |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 119 | |
Simon Glass | 704e60d | 2011-11-05 04:46:51 +0000 | [diff] [blame] | 120 | /* Do clocks and UART first so that printf() works */ |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 121 | #if IS_ENABLED(CONFIG_TEGRA_CLKRST) |
Simon Glass | c2ea5e4 | 2011-09-21 12:40:04 +0000 | [diff] [blame] | 122 | clock_init(); |
| 123 | clock_verify(); |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 124 | #endif |
Simon Glass | c2ea5e4 | 2011-09-21 12:40:04 +0000 | [diff] [blame] | 125 | |
Alexandre Courbot | f36729d | 2015-10-19 13:57:03 +0900 | [diff] [blame] | 126 | tegra_gpu_config(); |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 127 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 128 | #ifdef CONFIG_TEGRA_SPI |
Stephen Warren | d2f67fe | 2012-06-12 08:33:40 +0000 | [diff] [blame] | 129 | pin_mux_spi(); |
Tom Warren | ee554f8 | 2011-11-05 09:48:11 +0000 | [diff] [blame] | 130 | #endif |
Allen Martin | ba4fb9b | 2013-01-29 13:51:28 +0000 | [diff] [blame] | 131 | |
Masahiro Yamada | b2c8868 | 2017-01-10 13:32:07 +0900 | [diff] [blame] | 132 | #ifdef CONFIG_MMC_SDHCI_TEGRA |
Stephen Warren | c044fe2 | 2016-09-13 10:45:47 -0600 | [diff] [blame] | 133 | pin_mux_mmc(); |
| 134 | #endif |
| 135 | |
Simon Glass | eb21083 | 2016-01-30 16:37:48 -0700 | [diff] [blame] | 136 | /* Init is handled automatically in the driver-model case */ |
Simon Glass | 52cb504 | 2022-10-18 07:46:31 -0600 | [diff] [blame] | 137 | #if defined(CONFIG_VIDEO) |
Marc Dietrich | 9bbe64b | 2012-11-25 11:26:11 +0000 | [diff] [blame] | 138 | pin_mux_display(); |
Simon Glass | 3e2b2d9 | 2016-01-30 16:37:49 -0700 | [diff] [blame] | 139 | #endif |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 140 | /* boot param addr */ |
| 141 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 142 | |
| 143 | power_det_init(); |
| 144 | |
Simon Glass | 026fefb | 2012-10-30 07:28:53 +0000 | [diff] [blame] | 145 | #ifdef CONFIG_SYS_I2C_TEGRA |
Simon Glass | e772be8 | 2012-04-02 13:18:54 +0000 | [diff] [blame] | 146 | # ifdef CONFIG_TEGRA_PMU |
| 147 | if (pmu_set_nominal()) |
| 148 | debug("Failed to select nominal voltages\n"); |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 149 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
| 150 | err = board_emc_init(); |
| 151 | if (err) |
| 152 | debug("Memory controller init failed: %d\n", err); |
| 153 | # endif |
| 154 | # endif /* CONFIG_TEGRA_PMU */ |
Simon Glass | 026fefb | 2012-10-30 07:28:53 +0000 | [diff] [blame] | 155 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 156 | |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 157 | #ifdef CONFIG_USB_EHCI_TEGRA |
| 158 | pin_mux_usb(); |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 159 | #endif |
Mateusz Zalega | d862f89 | 2013-10-04 19:22:26 +0200 | [diff] [blame] | 160 | |
Simon Glass | 52cb504 | 2022-10-18 07:46:31 -0600 | [diff] [blame] | 161 | #if defined(CONFIG_VIDEO) |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 162 | board_id = tegra_board_id(); |
| 163 | err = tegra_lcd_pmic_init(board_id); |
Simon Glass | 9d8271e | 2017-06-12 06:21:59 -0600 | [diff] [blame] | 164 | if (err) { |
| 165 | debug("Failed to set up LCD PMIC\n"); |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 166 | return err; |
Simon Glass | 9d8271e | 2017-06-12 06:21:59 -0600 | [diff] [blame] | 167 | } |
Simon Glass | 3e2b2d9 | 2016-01-30 16:37:49 -0700 | [diff] [blame] | 168 | #endif |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 169 | |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 170 | #ifdef CONFIG_TEGRA_NAND |
| 171 | pin_mux_nand(); |
| 172 | #endif |
| 173 | |
Simon Glass | cf0c6e2 | 2017-07-25 08:29:59 -0600 | [diff] [blame] | 174 | tegra_xusb_padctl_init(); |
Thierry Reding | f202e02 | 2014-12-09 22:25:09 -0700 | [diff] [blame] | 175 | |
Tom Warren | 22562a4 | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 176 | #ifdef CONFIG_TEGRA_LP0 |
Allen Martin | 0ca1a45 | 2012-08-31 08:30:11 +0000 | [diff] [blame] | 177 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
| 178 | warmboot_save_sdram_params(); |
| 179 | |
Simon Glass | 8cc8f61 | 2012-04-02 13:18:57 +0000 | [diff] [blame] | 180 | /* prepare the WB code to LP0 location */ |
| 181 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); |
| 182 | #endif |
Simon Glass | 44a6808 | 2015-06-05 14:39:42 -0600 | [diff] [blame] | 183 | return nvidia_board_init(); |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 184 | } |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 185 | |
JC Kuo | f479aca | 2020-03-26 16:10:09 -0700 | [diff] [blame] | 186 | void board_cleanup_before_linux(void) |
| 187 | { |
| 188 | /* power down UPHY PLL */ |
| 189 | tegra_xusb_padctl_exit(); |
| 190 | } |
| 191 | |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 192 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
Thierry Reding | 2fa4db0 | 2012-06-04 20:02:27 +0000 | [diff] [blame] | 193 | static void __gpio_early_init(void) |
| 194 | { |
| 195 | } |
| 196 | |
| 197 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); |
| 198 | |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 199 | int board_early_init_f(void) |
| 200 | { |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 201 | #if IS_ENABLED(CONFIG_TEGRA_CLKRST) |
Simon Glass | 2b4029a | 2017-05-31 17:57:16 -0600 | [diff] [blame] | 202 | if (!clock_early_init_done()) |
| 203 | clock_early_init(); |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 204 | #endif |
Simon Glass | 2b4029a | 2017-05-31 17:57:16 -0600 | [diff] [blame] | 205 | |
Stephen Warren | 5a44ab4 | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 206 | #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) |
| 207 | #define USBCMD_FS2 (1 << 15) |
| 208 | { |
| 209 | struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; |
| 210 | writel(USBCMD_FS2, &usbctlr->usb_cmd); |
| 211 | } |
| 212 | #endif |
| 213 | |
Thierry Reding | ff81d75 | 2015-07-28 11:35:53 +0200 | [diff] [blame] | 214 | /* Do any special system timer/TSC setup */ |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 215 | #if IS_ENABLED(CONFIG_TEGRA_CLKRST) |
| 216 | # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
Thierry Reding | ff81d75 | 2015-07-28 11:35:53 +0200 | [diff] [blame] | 217 | if (!tegra_cpu_is_non_secure()) |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 218 | # endif |
Thierry Reding | ff81d75 | 2015-07-28 11:35:53 +0200 | [diff] [blame] | 219 | arch_timer_init(); |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 220 | #endif |
Thierry Reding | ff81d75 | 2015-07-28 11:35:53 +0200 | [diff] [blame] | 221 | |
Tom Warren | 872111a | 2020-02-28 16:17:07 -0700 | [diff] [blame] | 222 | #if defined(CONFIG_DISABLE_SDMMC1_EARLY) |
| 223 | /* |
| 224 | * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT. |
| 225 | * We do this because earlier bootloaders have enabled power to |
| 226 | * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init() |
| 227 | * results in power being back-driven into the SD-card and SDMMC1 |
| 228 | * HW, which is 'bad' as per the HW team. |
| 229 | * |
| 230 | * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in |
| 231 | * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT |
| 232 | * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off |
| 233 | * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard |
| 234 | * voltage turns off. Since the SDCard voltage is no longer there, the |
| 235 | * SDMMC CLK/DAT lines are backdriving into what essentially is a |
| 236 | * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V" |
| 237 | * |
| 238 | * Note that this can probably be removed when we change over to storing |
| 239 | * all BL components on QSPI on Nano, and U-Boot then becomes the first |
| 240 | * one to turn on SDMMC1 power. Another fix would be to have CBoot |
| 241 | * disable power/gate SDMMC1 off before handing off to U-Boot/kernel. |
| 242 | */ |
| 243 | reset_set_enable(PERIPH_ID_SDMMC1, 1); |
| 244 | clock_set_enable(PERIPH_ID_SDMMC1, 0); |
| 245 | #endif /* CONFIG_DISABLE_SDMMC1_EARLY */ |
| 246 | |
Tom Warren | d32b2a4 | 2012-12-11 13:34:17 +0000 | [diff] [blame] | 247 | pinmux_init(); |
Simon Glass | a8ccc8b | 2011-11-28 15:04:40 +0000 | [diff] [blame] | 248 | board_init_uart_f(); |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 249 | |
| 250 | /* Initialize periph GPIOs */ |
Thierry Reding | 2fa4db0 | 2012-06-04 20:02:27 +0000 | [diff] [blame] | 251 | gpio_early_init(); |
Simon Glass | 704e60d | 2011-11-05 04:46:51 +0000 | [diff] [blame] | 252 | gpio_early_init_uart(); |
Lucas Stach | 18561f7 | 2012-09-25 20:21:14 +0000 | [diff] [blame] | 253 | |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 254 | return 0; |
| 255 | } |
| 256 | #endif /* EARLY_INIT */ |
Simon Glass | 4f476f3 | 2012-10-17 13:24:52 +0000 | [diff] [blame] | 257 | |
| 258 | int board_late_init(void) |
| 259 | { |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 260 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
| 261 | if (tegra_cpu_is_non_secure()) { |
| 262 | printf("CPU is in NS mode\n"); |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 263 | env_set("cpu_ns_mode", "1"); |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 264 | } else { |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 265 | env_set("cpu_ns_mode", ""); |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 266 | } |
| 267 | #endif |
Tom Warren | f3035ca | 2015-02-20 12:22:22 -0700 | [diff] [blame] | 268 | start_cpu_fan(); |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 269 | cboot_late_init(); |
Tom Warren | f3035ca | 2015-02-20 12:22:22 -0700 | [diff] [blame] | 270 | |
Simon Glass | 4f476f3 | 2012-10-17 13:24:52 +0000 | [diff] [blame] | 271 | return 0; |
| 272 | } |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 273 | |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 274 | /* |
| 275 | * In some SW environments, a memory carve-out exists to house a secure |
| 276 | * monitor, a trusted OS, and/or various statically allocated media buffers. |
| 277 | * |
| 278 | * This carveout exists at the highest possible address that is within a |
| 279 | * 32-bit physical address space. |
| 280 | * |
| 281 | * This function returns the total size of this carve-out. At present, the |
| 282 | * returned value is hard-coded for simplicity. In the future, it may be |
| 283 | * possible to determine the carve-out size: |
| 284 | * - By querying some run-time information source, such as: |
| 285 | * - A structure passed to U-Boot by earlier boot software. |
| 286 | * - SoC registers. |
| 287 | * - A call into the secure monitor. |
| 288 | * - In the per-board U-Boot configuration header, based on knowledge of the |
| 289 | * SW environment that U-Boot is being built for. |
| 290 | * |
| 291 | * For now, we support two configurations in U-Boot: |
| 292 | * - 32-bit ports without any form of carve-out. |
| 293 | * - 64 bit ports which are assumed to use a carve-out of a conservatively |
| 294 | * hard-coded size. |
| 295 | */ |
| 296 | static ulong carveout_size(void) |
| 297 | { |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 298 | #ifdef CONFIG_ARM64 |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 299 | return SZ_512M; |
Stephen Warren | c12800f | 2018-06-22 13:03:19 -0600 | [diff] [blame] | 300 | #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE) |
| 301 | // BASE+SIZE might not == 4GB. If so, we want the carveout to cover |
| 302 | // from BASE to 4GB, not BASE to BASE+SIZE. |
Stephen Warren | a963a78 | 2018-07-31 12:38:27 -0600 | [diff] [blame] | 303 | return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1); |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 304 | #else |
| 305 | return 0; |
| 306 | #endif |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * Determine the amount of usable RAM below 4GiB, taking into account any |
| 311 | * carve-out that may be assigned. |
| 312 | */ |
| 313 | static ulong usable_ram_size_below_4g(void) |
| 314 | { |
| 315 | ulong total_size_below_4g; |
| 316 | ulong usable_size_below_4g; |
| 317 | |
| 318 | /* |
| 319 | * The total size of RAM below 4GiB is the lesser address of: |
| 320 | * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). |
| 321 | * (b) The size RAM physically present in the system. |
| 322 | */ |
| 323 | if (gd->ram_size < SZ_2G) |
| 324 | total_size_below_4g = gd->ram_size; |
| 325 | else |
| 326 | total_size_below_4g = SZ_2G; |
| 327 | |
| 328 | /* Calculate usable RAM by subtracting out any carve-out size */ |
| 329 | usable_size_below_4g = total_size_below_4g - carveout_size(); |
| 330 | |
| 331 | return usable_size_below_4g; |
| 332 | } |
| 333 | |
| 334 | /* |
| 335 | * Represent all available RAM in either one or two banks. |
| 336 | * |
| 337 | * The first bank describes any usable RAM below 4GiB. |
| 338 | * The second bank describes any RAM above 4GiB. |
| 339 | * |
| 340 | * This split is driven by the following requirements: |
| 341 | * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg |
| 342 | * property for memory below and above the 4GiB boundary. The layout of that |
| 343 | * DT property is directly driven by the entries in the U-Boot bank array. |
| 344 | * - The potential existence of a carve-out at the end of RAM below 4GiB can |
| 345 | * only be represented using multiple banks. |
| 346 | * |
| 347 | * Explicitly removing the carve-out RAM from the bank entries makes the RAM |
| 348 | * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot |
| 349 | * command-line. |
| 350 | * |
| 351 | * This does mean that the DT U-Boot passes to the Linux kernel will not |
| 352 | * include this RAM in /memory/reg at all. An alternative would be to include |
| 353 | * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node |
| 354 | * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the |
| 355 | * Linux kernel will ever need to access any RAM in* the carve-out via a CPU |
| 356 | * mapping, so either way is acceptable. |
| 357 | * |
| 358 | * On 32-bit systems, we never define a bank for RAM above 4GiB, since the |
| 359 | * start address of that bank cannot be represented in the 32-bit .size |
| 360 | * field. |
| 361 | */ |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 362 | int dram_init_banksize(void) |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 363 | { |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 364 | int err; |
| 365 | |
| 366 | /* try to compute DRAM bank size based on cboot DTB first */ |
| 367 | err = cboot_dram_init_banksize(); |
| 368 | if (err == 0) |
| 369 | return err; |
| 370 | |
| 371 | /* fall back to default DRAM bank size computation */ |
| 372 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 373 | gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 374 | gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); |
| 375 | |
Simon Glass | 46fcfc1 | 2015-11-19 20:27:02 -0700 | [diff] [blame] | 376 | #ifdef CONFIG_PCI |
| 377 | gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; |
| 378 | #endif |
| 379 | |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 380 | #ifdef CONFIG_PHYS_64BIT |
| 381 | if (gd->ram_size > SZ_2G) { |
| 382 | gd->bd->bi_dram[1].start = 0x100000000; |
| 383 | gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; |
| 384 | } else |
| 385 | #endif |
| 386 | { |
| 387 | gd->bd->bi_dram[1].start = 0; |
| 388 | gd->bd->bi_dram[1].size = 0; |
| 389 | } |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 390 | |
| 391 | return 0; |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 392 | } |
| 393 | |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 394 | /* |
| 395 | * Most hardware on 64-bit Tegra is still restricted to DMA to the lower |
| 396 | * 32-bits of the physical address space. Cap the maximum usable RAM area |
| 397 | * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 398 | * boundary that most devices can address. Also, don't let U-Boot use any |
| 399 | * carve-out, as mentioned above. |
Stephen Warren | 30d1966 | 2015-07-29 13:47:58 -0600 | [diff] [blame] | 400 | * |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 401 | * This function is called before dram_init_banksize(), so we can't simply |
| 402 | * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 403 | */ |
Pali Rohár | 4f4f583 | 2022-09-09 17:32:40 +0200 | [diff] [blame] | 404 | phys_size_t board_get_usable_ram_top(phys_size_t total_size) |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 405 | { |
Thierry Reding | 7cef2b2 | 2019-04-15 11:32:28 +0200 | [diff] [blame] | 406 | ulong ram_top; |
| 407 | |
| 408 | /* try to get top of usable RAM based on cboot DTB first */ |
| 409 | ram_top = cboot_get_usable_ram_top(total_size); |
| 410 | if (ram_top > 0) |
| 411 | return ram_top; |
| 412 | |
| 413 | /* fall back to default usable RAM computation */ |
| 414 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 415 | return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 416 | } |