Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 51e11ed6703e47150597621864fe22343eb5e3c1 / . / configs / xilinx_zynqmp_zc1751_xm018_dc4_defconfig
blob: c5dcf2e2dce00e8a425699458fa3ccc2330cf804 [file] [log] [blame]
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]1CONFIG_ARM=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]2CONFIG_ARCH_ZYNQMP=y
Michal Simek19abc1d2017-02-10 13:57:35 +0100[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x8000000
Michal Simekcbd91182016-06-03 11:35:17 +0200[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x8000
Michal Simek040050b2018-03-23 09:34:00 +0100[diff] [blame]5CONFIG_SPL=y
Michal Simeka932ae72018-06-04 08:33:30 +0200[diff] [blame]6CONFIG_DEBUG_UART_BASE=0xff000000
7CONFIG_DEBUG_UART_CLOCK=100000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]8CONFIG_DEBUG_UART=y
Tom Rini8db91cf2016-11-29 09:14:57 -0500[diff] [blame]9CONFIG_DISTRO_DEFAULTS=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]10CONFIG_FIT=y
11CONFIG_FIT_VERBOSE=y
Michal Simek437c59c2016-05-17 08:38:53 +0200[diff] [blame]12CONFIG_SPL_LOAD_FIT=y
Lokesh Vutlafbad3702016-10-08 14:41:44 -0400[diff] [blame]13# CONFIG_DISPLAY_CPUINFO is not set
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]14CONFIG_BOARD_EARLY_INIT_R=y
Heiko Schocher1d12ba22016-10-06 07:55:15 +0200[diff] [blame]15CONFIG_SPL_OS_BOOT=y
Michal Simek406d1c62017-12-08 15:01:19 +0100[diff] [blame]16CONFIG_SPL_RAM_SUPPORT=y
17CONFIG_SPL_RAM_DEVICE=y
Luca Ceresoli560f4192018-03-12 17:18:38 +0100[diff] [blame]18CONFIG_SPL_ATF=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]19CONFIG_SYS_PROMPT="ZynqMP> "
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]20CONFIG_CMD_MEMTEST=y
Mario Six00518992018-03-28 14:38:14 +0200[diff] [blame]21CONFIG_SYS_ALT_MEMTEST=y
Michal Simek41f70e22017-12-01 15:35:43 +0100[diff] [blame]22CONFIG_CMD_CLK=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]23# CONFIG_CMD_FLASH is not set
Michal Simek8bfe60b2017-12-08 15:03:26 +0100[diff] [blame]24CONFIG_CMD_FPGA_LOADBP=y
25CONFIG_CMD_FPGA_LOADP=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]26CONFIG_CMD_I2C=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]27CONFIG_CMD_MMC=y
Michal Simekeade1da2019-01-15 09:30:38 +0100[diff] [blame]28CONFIG_CMD_SF=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]29CONFIG_CMD_TFTPPUT=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]30CONFIG_CMD_TIME=y
31CONFIG_CMD_TIMER=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]32CONFIG_CMD_EXT4_WRITE=y
Michal Simek4c1f7f82016-07-15 08:41:46 +0200[diff] [blame]33CONFIG_SPL_OF_CONTROL=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]34CONFIG_OF_EMBED=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]35CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]36CONFIG_ENV_IS_IN_FAT=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]37CONFIG_NET_RANDOM_ETHADDR=y
Michal Simekb9c5d132016-07-27 15:08:03 +0200[diff] [blame]38CONFIG_SPL_DM=y
Michal Simek4c1f7f82016-07-15 08:41:46 +0200[diff] [blame]39CONFIG_SPL_DM_SEQ_ALIAS=y
Michal Simeka6604b62017-12-08 14:50:42 +0100[diff] [blame]40CONFIG_CLK_ZYNQMP=y
Siva Durga Prasad Paladugu460fdce2016-01-13 16:25:37 +0530[diff] [blame]41CONFIG_FPGA_XILINX=y
42CONFIG_FPGA_ZYNQMPPL=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]43CONFIG_DM_GPIO=y
Michal Simekb9c5d132016-07-27 15:08:03 +0200[diff] [blame]44CONFIG_DM_I2C=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]45CONFIG_SYS_I2C_CADENCE=y
Michal Simek46408712017-12-08 14:46:30 +0100[diff] [blame]46CONFIG_MISC=y
Masahiro Yamada7db8c172016-12-07 22:10:28 +0900[diff] [blame]47CONFIG_MMC_SDHCI=y
Michal Simek19abc1d2017-02-10 13:57:35 +0100[diff] [blame]48CONFIG_MMC_SDHCI_ZYNQ=y
Michal Simek0bda0792017-12-08 15:18:05 +0100[diff] [blame]49CONFIG_SPI_FLASH=y
50CONFIG_SPI_FLASH_BAR=y
Michal Simekeade1da2019-01-15 09:30:38 +0100[diff] [blame]51CONFIG_SF_DUAL_FLASH=y
Michal Simek51e11ed2019-01-15 10:45:41 +0100[diff] [blame^]52CONFIG_SPI_FLASH_ISSI=y
Michal Simek0bda0792017-12-08 15:18:05 +0100[diff] [blame]53CONFIG_SPI_FLASH_MACRONIX=y
54CONFIG_SPI_FLASH_SPANSION=y
55CONFIG_SPI_FLASH_STMICRO=y
56CONFIG_SPI_FLASH_WINBOND=y
Siva Durga Prasad Paladugu4b403272017-01-31 10:44:06 +0530[diff] [blame]57# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Vipul Kumar6124b052018-01-24 10:51:31 +0530[diff] [blame]58CONFIG_PHY_MARVELL=y
59CONFIG_PHY_NATSEMI=y
60CONFIG_PHY_REALTEK=y
61CONFIG_PHY_TI=y
62CONFIG_PHY_VITESSE=y
Michal Simekf77f81c2018-03-28 14:18:19 +0200[diff] [blame]63CONFIG_PHY_FIXED=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]64CONFIG_PHY_GIGE=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]65CONFIG_MII=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]66CONFIG_ZYNQ_GEM=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]67CONFIG_DEBUG_UART_ZYNQ=y
Michal Simek61015152016-05-26 08:06:38 +0200[diff] [blame]68CONFIG_DEBUG_UART_ANNOUNCE=y
Michal Simekab754532017-11-06 09:16:05 +0100[diff] [blame]69CONFIG_ZYNQ_SERIAL=y
Michal Simekeade1da2019-01-15 09:30:38 +0100[diff] [blame]70CONFIG_SPI=y
71CONFIG_ZYNQMP_GQSPI=y