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git01.mediatek.com / filogic / uboot / 4ac0140018315b71109de716d49f7a935b2f9f30 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 97bbfe2e65e887991899889df3fb23e55052a43e [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#ifndef _DDR_DEFS_H
12#define _DDR_DEFS_H
13
14#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]15#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]16
17/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]18#define VTP_CTRL_READY (0x1 << 5)
19#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]20#define VTP_CTRL_START_EN (0x1)
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]21#ifdef CONFIG_AM43XX
22#define DDR_CKE_CTRL_NORMAL 0x3
23#else
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]24#define DDR_CKE_CTRL_NORMAL 0x1
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]25#endif
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]26#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]27
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]28/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]29#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]35#define MT47H128M16RT25E_RATIO 0x80
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]36#define MT47H128M16RT25E_RD_DQS 0x12
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]37#define MT47H128M16RT25E_PHY_WR_DATA 0x40
38#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]39#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]40
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]41/* Micron MT41J128M16JT-125 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]42#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]43#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
44#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
45#define MT41J128MJT125_EMIF_TIM3 0x501F830F
46#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
47#define MT41J128MJT125_EMIF_SDREF 0x0000093B
48#define MT41J128MJT125_ZQ_CFG 0x50074BE4
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]49#define MT41J128MJT125_RATIO 0x40
50#define MT41J128MJT125_INVERT_CLKOUT 0x1
51#define MT41J128MJT125_RD_DQS 0x3B
52#define MT41J128MJT125_WR_DQS 0x85
53#define MT41J128MJT125_PHY_WR_DATA 0xC1
54#define MT41J128MJT125_PHY_FIFO_WE 0x100
55#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]56
Lothar Felten8c6324f2014-01-31 17:34:14 +0100[diff] [blame]57/* Micron MT41K128M16JT-187E */
58#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
59#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
60#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
61#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
62#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
63#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
64#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
65#define MT41K128MJT187E_RATIO 0x40
66#define MT41K128MJT187E_INVERT_CLKOUT 0x1
67#define MT41K128MJT187E_RD_DQS 0x3B
68#define MT41K128MJT187E_WR_DQS 0x85
69#define MT41K128MJT187E_PHY_WR_DATA 0xC1
70#define MT41K128MJT187E_PHY_FIFO_WE 0x100
71#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
72
Ilya Ledvich791ca182013-11-07 07:57:33 +0200[diff] [blame]73/* Micron MT41J64M16JT-125 */
74#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
75
76/* Micron MT41J256M16JT-125 */
77#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
78
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]79/* Micron MT41J256M8HX-15E */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]80#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]81#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
82#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
83#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
84#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
85#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
86#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]87#define MT41J256M8HX15E_RATIO 0x40
88#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
89#define MT41J256M8HX15E_RD_DQS 0x3B
90#define MT41J256M8HX15E_WR_DQS 0x85
91#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
92#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
93#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]95/* Micron MT41K256M16HA-125E */
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]96#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
97#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]98#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
99#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
100#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]101#define MT41K256M16HA125E_EMIF_SDREF 0xC30
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]102#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]103#define MT41K256M16HA125E_RATIO 0x80
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]104#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]105#define MT41K256M16HA125E_RD_DQS 0x38
106#define MT41K256M16HA125E_WR_DQS 0x44
107#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
108#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]109#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
110
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]111/* Micron MT41J512M8RH-125 on EVM v1.5 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]112#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]113#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
114#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
115#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
116#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
117#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
118#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]119#define MT41J512M8RH125_RATIO 0x80
120#define MT41J512M8RH125_INVERT_CLKOUT 0x0
121#define MT41J512M8RH125_RD_DQS 0x3B
122#define MT41J512M8RH125_WR_DQS 0x3C
123#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
124#define MT41J512M8RH125_PHY_WR_DATA 0x74
125#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]126
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]127/* Samsung K4B2G1646E-BIH9 */
Satyanarayana, Sandhyac698a1a2013-12-19 10:00:29 +0530[diff] [blame]128#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]129#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
130#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
131#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
132#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
133#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]134#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]135#define K4B2G1646EBIH9_RATIO 0x80
136#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
137#define K4B2G1646EBIH9_RD_DQS 0x35
138#define K4B2G1646EBIH9_WR_DQS 0x3A
139#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
140#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]141#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
142
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]143#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
144#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
145#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
146#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
147#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
148#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
149#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
150
Lokesh Vutladd0037a2013-12-10 15:02:23 +0530[diff] [blame]151#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
152#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
153#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
154#define DDR3_DATA0_IOCTRL_VALUE 0x84
155#define DDR3_DATA1_IOCTRL_VALUE 0x84
156#define DDR3_DATA2_IOCTRL_VALUE 0x84
157#define DDR3_DATA3_IOCTRL_VALUE 0x84
158
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]159/**
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]160 * Configure DMM
161 */
162void config_dmm(const struct dmm_lisa_map_regs *regs);
163
164/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]165 * Configure SDRAM
166 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]167void config_sdram(const struct emif_regs *regs, int nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]168void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]169
170/**
171 * Set SDRAM timings
172 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]173void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]174
175/**
176 * Configure DDR PHY
177 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]178void config_ddr_phy(const struct emif_regs *regs, int nr);
179
180struct ddr_cmd_regs {
181 unsigned int resv0[7];
182 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]183 unsigned int resv1[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]184 unsigned int cm0iclkout; /* offset 0x02C */
185 unsigned int resv2[8];
186 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]187 unsigned int resv3[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]188 unsigned int cm1iclkout; /* offset 0x060 */
189 unsigned int resv4[8];
190 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]191 unsigned int resv5[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]192 unsigned int cm2iclkout; /* offset 0x094 */
193 unsigned int resv6[3];
194};
195
196struct ddr_data_regs {
197 unsigned int dt0rdsratio0; /* offset 0x0C8 */
198 unsigned int resv1[4];
199 unsigned int dt0wdsratio0; /* offset 0x0DC */
200 unsigned int resv2[4];
201 unsigned int dt0wiratio0; /* offset 0x0F0 */
202 unsigned int resv3;
203 unsigned int dt0wimode0; /* offset 0x0F8 */
204 unsigned int dt0giratio0; /* offset 0x0FC */
205 unsigned int resv4;
206 unsigned int dt0gimode0; /* offset 0x104 */
207 unsigned int dt0fwsratio0; /* offset 0x108 */
208 unsigned int resv5[4];
209 unsigned int dt0dqoffset; /* offset 0x11C */
210 unsigned int dt0wrsratio0; /* offset 0x120 */
211 unsigned int resv6[4];
212 unsigned int dt0rdelays0; /* offset 0x134 */
213 unsigned int dt0dldiff0; /* offset 0x138 */
214 unsigned int resv7[12];
215};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]216
217/**
218 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]219 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
220 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]221 */
222struct ddr_regs {
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]223 unsigned int resv0[3];
224 unsigned int cm0config; /* offset 0x00C */
225 unsigned int cm0configclk; /* offset 0x010 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]226 unsigned int resv1[2];
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]227 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]228 unsigned int resv2[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]229 unsigned int cm0iclkout; /* offset 0x02C */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]230 unsigned int resv3[4];
231 unsigned int cm1config; /* offset 0x040 */
232 unsigned int cm1configclk; /* offset 0x044 */
233 unsigned int resv4[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]234 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]235 unsigned int resv5[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]236 unsigned int cm1iclkout; /* offset 0x060 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]237 unsigned int resv6[4];
238 unsigned int cm2config; /* offset 0x074 */
239 unsigned int cm2configclk; /* offset 0x078 */
240 unsigned int resv7[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]241 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]242 unsigned int resv8[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]243 unsigned int cm2iclkout; /* offset 0x094 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]244 unsigned int resv9[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]245 unsigned int dt0rdsratio0; /* offset 0x0C8 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]246 unsigned int resv10[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]247 unsigned int dt0wdsratio0; /* offset 0x0DC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]248 unsigned int resv11[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]249 unsigned int dt0wiratio0; /* offset 0x0F0 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]250 unsigned int resv12;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]251 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]252 unsigned int dt0giratio0; /* offset 0x0FC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]253 unsigned int resv13;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]254 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]255 unsigned int dt0fwsratio0; /* offset 0x108 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]256 unsigned int resv14[4];
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]257 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]258 unsigned int dt0wrsratio0; /* offset 0x120 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]259 unsigned int resv15[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]260 unsigned int dt0rdelays0; /* offset 0x134 */
261 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]262};
263
264/**
265 * Encapsulates DDR CMD control registers.
266 */
267struct cmd_control {
268 unsigned long cmd0csratio;
269 unsigned long cmd0csforce;
270 unsigned long cmd0csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]271 unsigned long cmd0iclkout;
272 unsigned long cmd1csratio;
273 unsigned long cmd1csforce;
274 unsigned long cmd1csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]275 unsigned long cmd1iclkout;
276 unsigned long cmd2csratio;
277 unsigned long cmd2csforce;
278 unsigned long cmd2csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]279 unsigned long cmd2iclkout;
280};
281
282/**
283 * Encapsulates DDR DATA registers.
284 */
285struct ddr_data {
286 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]287 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]288 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]289 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]290 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]291 unsigned long datawrsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]292};
293
294/**
295 * Configure DDR CMD control registers
296 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]297void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]298
299/**
300 * Configure DDR DATA registers
301 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]302void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]303
304/**
305 * This structure represents the DDR io control on AM33XX devices.
306 */
307struct ddr_cmdtctrl {
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]308 unsigned int cm0ioctl;
309 unsigned int cm1ioctl;
310 unsigned int cm2ioctl;
311 unsigned int resv2[12];
312 unsigned int dt0ioctl;
313 unsigned int dt1ioctl;
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]314 unsigned int dt2ioctrl;
315 unsigned int dt3ioctrl;
316 unsigned int resv3[4];
317 unsigned int emif_sdram_config_ext;
318};
319
320struct ctrl_ioregs {
321 unsigned int cm0ioctl;
322 unsigned int cm1ioctl;
323 unsigned int cm2ioctl;
324 unsigned int dt0ioctl;
325 unsigned int dt1ioctl;
326 unsigned int dt2ioctrl;
327 unsigned int dt3ioctrl;
328 unsigned int emif_sdram_config_ext;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]329};
330
331/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]332 * Configure DDR io control registers
333 */
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]334void config_io_ctrl(const struct ctrl_ioregs *ioregs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]335
336struct ddr_ctrl {
337 unsigned int ddrioctrl;
338 unsigned int resv1[325];
339 unsigned int ddrckectrl;
340};
341
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]342void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]343 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]344 const struct emif_regs *regs, int nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]345void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]346
347#endif /* _DDR_DEFS_H */