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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese93e6bf42014-10-22 12:13:17 +02002/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefan Roese93e6bf42014-10-22 12:13:17 +02006 */
7
Stefan Roeseebda3ec2015-04-25 06:29:47 +02008#ifndef _MVEBU_CPU_H
9#define _MVEBU_CPU_H
Stefan Roese93e6bf42014-10-22 12:13:17 +020010
11#include <asm/system.h>
12
13#ifndef __ASSEMBLY__
14
15#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
16#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
17
18enum memory_bank {
19 BANK0,
20 BANK1,
21 BANK2,
22 BANK3
23};
24
25enum cpu_winen {
26 CPU_WIN_DISABLE,
27 CPU_WIN_ENABLE
28};
29
30enum cpu_target {
31 CPU_TARGET_DRAM = 0x0,
32 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
33 CPU_TARGET_ETH23 = 0x3,
34 CPU_TARGET_PCIE02 = 0x4,
35 CPU_TARGET_ETH01 = 0x7,
36 CPU_TARGET_PCIE13 = 0x8,
Chris Packhama8f845e2019-04-11 22:22:50 +120037 CPU_TARGET_DFX = 0x8,
Stefan Roese93e6bf42014-10-22 12:13:17 +020038 CPU_TARGET_SASRAM = 0x9,
Mario Six10d14492017-01-11 16:01:00 +010039 CPU_TARGET_SATA01 = 0xa, /* A38X */
Stefan Roese93e6bf42014-10-22 12:13:17 +020040 CPU_TARGET_NAND = 0xd,
Mario Six10d14492017-01-11 16:01:00 +010041 CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
Stefan Roese93e6bf42014-10-22 12:13:17 +020042};
43
44enum cpu_attrib {
45 CPU_ATTR_SASRAM = 0x01,
46 CPU_ATTR_DRAM_CS0 = 0x0e,
47 CPU_ATTR_DRAM_CS1 = 0x0d,
48 CPU_ATTR_DRAM_CS2 = 0x0b,
49 CPU_ATTR_DRAM_CS3 = 0x07,
50 CPU_ATTR_NANDFLASH = 0x2f,
51 CPU_ATTR_SPIFLASH = 0x1e,
Stefan Roesebca3d862016-02-12 13:52:16 +010052 CPU_ATTR_SPI0_CS0 = 0x1e,
53 CPU_ATTR_SPI0_CS1 = 0x5e,
54 CPU_ATTR_SPI1_CS2 = 0x9a,
Stefan Roese93e6bf42014-10-22 12:13:17 +020055 CPU_ATTR_BOOTROM = 0x1d,
56 CPU_ATTR_PCIE_IO = 0xe0,
57 CPU_ATTR_PCIE_MEM = 0xe8,
58 CPU_ATTR_DEV_CS0 = 0x3e,
59 CPU_ATTR_DEV_CS1 = 0x3d,
60 CPU_ATTR_DEV_CS2 = 0x3b,
61 CPU_ATTR_DEV_CS3 = 0x37,
62};
63
Stefan Roese174d23e2015-04-25 06:29:51 +020064enum {
65 MVEBU_SOC_AXP,
Stefan Roese479f9af2016-02-10 07:23:00 +010066 MVEBU_SOC_A375,
Stefan Roese174d23e2015-04-25 06:29:51 +020067 MVEBU_SOC_A38X,
Chris Packham348109d2017-09-04 17:38:31 +120068 MVEBU_SOC_MSYS,
Stefan Roese174d23e2015-04-25 06:29:51 +020069 MVEBU_SOC_UNKNOWN,
70};
71
Stefan Roese10fa44b2018-10-22 14:21:17 +020072#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
73
Stefan Roese93e6bf42014-10-22 12:13:17 +020074/*
75 * Default Device Address MAP BAR values
76 */
Stefan Roese10fa44b2018-10-22 14:21:17 +020077#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
Stefan Roese13b109f2015-07-01 12:55:07 +020078#define MBUS_PCI_MEM_SIZE (128 << 20)
79#define MBUS_PCI_IO_BASE 0xF1100000
80#define MBUS_PCI_IO_SIZE (64 << 10)
81#define MBUS_SPI_BASE 0xF4000000
82#define MBUS_SPI_SIZE (8 << 20)
Chris Packhama8f845e2019-04-11 22:22:50 +120083#define MBUS_DFX_BASE 0xF6000000
84#define MBUS_DFX_SIZE (1 << 20)
Stefan Roese13b109f2015-07-01 12:55:07 +020085#define MBUS_BOOTROM_BASE 0xF8000000
86#define MBUS_BOOTROM_SIZE (8 << 20)
Stefan Roese93e6bf42014-10-22 12:13:17 +020087
88struct mbus_win {
89 u32 base;
90 u32 size;
91 u8 target;
92 u8 attr;
93};
94
95/*
96 * System registers
97 * Ref: Datasheet sec:A.28
98 */
99struct mvebu_system_registers {
Stefan Roese479f9af2016-02-10 07:23:00 +0100100#if defined(CONFIG_ARMADA_375)
101 u8 pad1[0x54];
102#else
Stefan Roese93e6bf42014-10-22 12:13:17 +0200103 u8 pad1[0x60];
Stefan Roese479f9af2016-02-10 07:23:00 +0100104#endif
Stefan Roese93e6bf42014-10-22 12:13:17 +0200105 u32 rstoutn_mask; /* 0x60 */
106 u32 sys_soft_rst; /* 0x64 */
107};
108
109/*
110 * GPIO Registers
111 * Ref: Datasheet sec:A.19
112 */
113struct kwgpio_registers {
114 u32 dout;
115 u32 oe;
116 u32 blink_en;
117 u32 din_pol;
118 u32 din;
119 u32 irq_cause;
120 u32 irq_mask;
121 u32 irq_level;
122};
123
Stefan Roese2a539c82015-12-21 12:36:40 +0100124struct sar_freq_modes {
125 u8 val;
126 u8 ffc; /* Fabric Frequency Configuration */
127 u32 p_clk;
128 u32 nb_clk;
129 u32 d_clk;
130};
131
Stefan Roese1a16a0c2015-01-19 11:33:47 +0100132/* Needed for dynamic (board-specific) mbus configuration */
133extern struct mvebu_mbus_state mbus_state;
134
Stefan Roese93e6bf42014-10-22 12:13:17 +0200135/*
136 * functions
137 */
138unsigned int mvebu_sdram_bar(enum memory_bank bank);
139unsigned int mvebu_sdram_bs(enum memory_bank bank);
140void mvebu_sdram_size_adjust(enum memory_bank bank);
141int mvebu_mbus_probe(struct mbus_win windows[], int count);
Stefan Roese174d23e2015-04-25 06:29:51 +0200142int mvebu_soc_family(void);
Stefan Roesebadccc32015-07-16 10:40:05 +0200143u32 mvebu_get_nand_clock(void);
Stefan Roesee463bf32015-01-19 11:33:42 +0100144
Stefan Roese99b3ea72015-08-25 13:49:41 +0200145void return_to_bootrom(void);
146
Pierre Bourdonb9af62d2019-04-11 04:56:58 +0200147#ifndef CONFIG_DM_MMC
Stefan Roesed3e34732015-06-29 14:58:10 +0200148int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
Pierre Bourdonb9af62d2019-04-11 04:56:58 +0200149#endif
Stefan Roesed3e34732015-06-29 14:58:10 +0200150
Stefan Roese2a539c82015-12-21 12:36:40 +0100151void get_sar_freq(struct sar_freq_modes *sar_freq);
152
Stefan Roesee463bf32015-01-19 11:33:42 +0100153/*
154 * Highspeed SERDES PHY config init, ported from bin_hdr
155 * to mainline U-Boot
156 */
157int serdes_phy_config(void);
158
159/*
160 * DDR3 init / training code ported from Marvell bin_hdr. Now
161 * available in mainline U-Boot in:
Stefan Roeseeb753e92015-03-25 12:51:18 +0100162 * drivers/ddr/marvell
Stefan Roesee463bf32015-01-19 11:33:42 +0100163 */
164int ddr3_init(void);
Stefan Roeseab91fd52016-01-20 08:13:28 +0100165
Stefan Roese05b17652016-05-17 15:00:30 +0200166/*
167 * get_ref_clk
168 *
169 * return: reference clock in MHz (25 or 40)
170 */
171u32 get_ref_clk(void);
172
Stefan Roese93e6bf42014-10-22 12:13:17 +0200173#endif /* __ASSEMBLY__ */
Stefan Roeseebda3ec2015-04-25 06:29:47 +0200174#endif /* _MVEBU_CPU_H */