| Stefan Roese | 93e6bf4 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 |
| 3 | * Marvell Semiconductor <www.marvell.com> |
| 4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef _ARMADA_XP_CPU_H |
| 10 | #define _ARMADA_XP_CPU_H |
| 11 | |
| 12 | #include <asm/system.h> |
| 13 | |
| 14 | #ifndef __ASSEMBLY__ |
| 15 | |
| 16 | #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) |
| 17 | #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) |
| 18 | |
| 19 | enum memory_bank { |
| 20 | BANK0, |
| 21 | BANK1, |
| 22 | BANK2, |
| 23 | BANK3 |
| 24 | }; |
| 25 | |
| 26 | enum cpu_winen { |
| 27 | CPU_WIN_DISABLE, |
| 28 | CPU_WIN_ENABLE |
| 29 | }; |
| 30 | |
| 31 | enum cpu_target { |
| 32 | CPU_TARGET_DRAM = 0x0, |
| 33 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, |
| 34 | CPU_TARGET_ETH23 = 0x3, |
| 35 | CPU_TARGET_PCIE02 = 0x4, |
| 36 | CPU_TARGET_ETH01 = 0x7, |
| 37 | CPU_TARGET_PCIE13 = 0x8, |
| 38 | CPU_TARGET_SASRAM = 0x9, |
| 39 | CPU_TARGET_NAND = 0xd, |
| 40 | }; |
| 41 | |
| 42 | enum cpu_attrib { |
| 43 | CPU_ATTR_SASRAM = 0x01, |
| 44 | CPU_ATTR_DRAM_CS0 = 0x0e, |
| 45 | CPU_ATTR_DRAM_CS1 = 0x0d, |
| 46 | CPU_ATTR_DRAM_CS2 = 0x0b, |
| 47 | CPU_ATTR_DRAM_CS3 = 0x07, |
| 48 | CPU_ATTR_NANDFLASH = 0x2f, |
| 49 | CPU_ATTR_SPIFLASH = 0x1e, |
| 50 | CPU_ATTR_BOOTROM = 0x1d, |
| 51 | CPU_ATTR_PCIE_IO = 0xe0, |
| 52 | CPU_ATTR_PCIE_MEM = 0xe8, |
| 53 | CPU_ATTR_DEV_CS0 = 0x3e, |
| 54 | CPU_ATTR_DEV_CS1 = 0x3d, |
| 55 | CPU_ATTR_DEV_CS2 = 0x3b, |
| 56 | CPU_ATTR_DEV_CS3 = 0x37, |
| 57 | }; |
| 58 | |
| 59 | /* |
| 60 | * Default Device Address MAP BAR values |
| 61 | */ |
| 62 | #define DEFADR_PCI_MEM 0x90000000 |
| 63 | #define DEFADR_PCI_IO 0xC0000000 |
| 64 | #define DEFADR_SPIF 0xF4000000 |
| 65 | #define DEFADR_BOOTROM 0xF8000000 |
| 66 | |
| 67 | struct mbus_win { |
| 68 | u32 base; |
| 69 | u32 size; |
| 70 | u8 target; |
| 71 | u8 attr; |
| 72 | }; |
| 73 | |
| 74 | /* |
| 75 | * System registers |
| 76 | * Ref: Datasheet sec:A.28 |
| 77 | */ |
| 78 | struct mvebu_system_registers { |
| 79 | u8 pad1[0x60]; |
| 80 | u32 rstoutn_mask; /* 0x60 */ |
| 81 | u32 sys_soft_rst; /* 0x64 */ |
| 82 | }; |
| 83 | |
| 84 | /* |
| 85 | * GPIO Registers |
| 86 | * Ref: Datasheet sec:A.19 |
| 87 | */ |
| 88 | struct kwgpio_registers { |
| 89 | u32 dout; |
| 90 | u32 oe; |
| 91 | u32 blink_en; |
| 92 | u32 din_pol; |
| 93 | u32 din; |
| 94 | u32 irq_cause; |
| 95 | u32 irq_mask; |
| 96 | u32 irq_level; |
| 97 | }; |
| 98 | |
| Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 99 | /* Needed for dynamic (board-specific) mbus configuration */ |
| 100 | extern struct mvebu_mbus_state mbus_state; |
| 101 | |
| Stefan Roese | 93e6bf4 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 102 | /* |
| 103 | * functions |
| 104 | */ |
| 105 | unsigned int mvebu_sdram_bar(enum memory_bank bank); |
| 106 | unsigned int mvebu_sdram_bs(enum memory_bank bank); |
| 107 | void mvebu_sdram_size_adjust(enum memory_bank bank); |
| 108 | int mvebu_mbus_probe(struct mbus_win windows[], int count); |
| Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame^] | 109 | |
| 110 | /* |
| 111 | * Highspeed SERDES PHY config init, ported from bin_hdr |
| 112 | * to mainline U-Boot |
| 113 | */ |
| 114 | int serdes_phy_config(void); |
| 115 | |
| 116 | /* |
| 117 | * DDR3 init / training code ported from Marvell bin_hdr. Now |
| 118 | * available in mainline U-Boot in: |
| 119 | * drivers/ddr/mvebu/ |
| 120 | */ |
| 121 | int ddr3_init(void); |
| Stefan Roese | 93e6bf4 | 2014-10-22 12:13:17 +0200 | [diff] [blame] | 122 | #endif /* __ASSEMBLY__ */ |
| 123 | #endif /* _ARMADA_XP_CPU_H */ |