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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese93e6bf42014-10-22 12:13:17 +02002/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefan Roese93e6bf42014-10-22 12:13:17 +02006 */
7
Stefan Roeseebda3ec2015-04-25 06:29:47 +02008#ifndef _MVEBU_CPU_H
9#define _MVEBU_CPU_H
Stefan Roese93e6bf42014-10-22 12:13:17 +020010
11#include <asm/system.h>
12
13#ifndef __ASSEMBLY__
14
15#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
16#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
17
18enum memory_bank {
19 BANK0,
20 BANK1,
21 BANK2,
22 BANK3
23};
24
25enum cpu_winen {
26 CPU_WIN_DISABLE,
27 CPU_WIN_ENABLE
28};
29
30enum cpu_target {
31 CPU_TARGET_DRAM = 0x0,
32 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
33 CPU_TARGET_ETH23 = 0x3,
34 CPU_TARGET_PCIE02 = 0x4,
35 CPU_TARGET_ETH01 = 0x7,
36 CPU_TARGET_PCIE13 = 0x8,
37 CPU_TARGET_SASRAM = 0x9,
Mario Six10d14492017-01-11 16:01:00 +010038 CPU_TARGET_SATA01 = 0xa, /* A38X */
Stefan Roese93e6bf42014-10-22 12:13:17 +020039 CPU_TARGET_NAND = 0xd,
Mario Six10d14492017-01-11 16:01:00 +010040 CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
Stefan Roese93e6bf42014-10-22 12:13:17 +020041};
42
43enum cpu_attrib {
44 CPU_ATTR_SASRAM = 0x01,
45 CPU_ATTR_DRAM_CS0 = 0x0e,
46 CPU_ATTR_DRAM_CS1 = 0x0d,
47 CPU_ATTR_DRAM_CS2 = 0x0b,
48 CPU_ATTR_DRAM_CS3 = 0x07,
49 CPU_ATTR_NANDFLASH = 0x2f,
50 CPU_ATTR_SPIFLASH = 0x1e,
Stefan Roesebca3d862016-02-12 13:52:16 +010051 CPU_ATTR_SPI0_CS0 = 0x1e,
52 CPU_ATTR_SPI0_CS1 = 0x5e,
53 CPU_ATTR_SPI1_CS2 = 0x9a,
Stefan Roese93e6bf42014-10-22 12:13:17 +020054 CPU_ATTR_BOOTROM = 0x1d,
55 CPU_ATTR_PCIE_IO = 0xe0,
56 CPU_ATTR_PCIE_MEM = 0xe8,
57 CPU_ATTR_DEV_CS0 = 0x3e,
58 CPU_ATTR_DEV_CS1 = 0x3d,
59 CPU_ATTR_DEV_CS2 = 0x3b,
60 CPU_ATTR_DEV_CS3 = 0x37,
61};
62
Stefan Roese174d23e2015-04-25 06:29:51 +020063enum {
64 MVEBU_SOC_AXP,
Stefan Roese479f9af2016-02-10 07:23:00 +010065 MVEBU_SOC_A375,
Stefan Roese174d23e2015-04-25 06:29:51 +020066 MVEBU_SOC_A38X,
Chris Packham348109d2017-09-04 17:38:31 +120067 MVEBU_SOC_MSYS,
Stefan Roese174d23e2015-04-25 06:29:51 +020068 MVEBU_SOC_UNKNOWN,
69};
70
Stefan Roese93e6bf42014-10-22 12:13:17 +020071/*
72 * Default Device Address MAP BAR values
73 */
Stefan Roese13b109f2015-07-01 12:55:07 +020074#define MBUS_PCI_MEM_BASE 0xE8000000
75#define MBUS_PCI_MEM_SIZE (128 << 20)
76#define MBUS_PCI_IO_BASE 0xF1100000
77#define MBUS_PCI_IO_SIZE (64 << 10)
78#define MBUS_SPI_BASE 0xF4000000
79#define MBUS_SPI_SIZE (8 << 20)
80#define MBUS_BOOTROM_BASE 0xF8000000
81#define MBUS_BOOTROM_SIZE (8 << 20)
Stefan Roese93e6bf42014-10-22 12:13:17 +020082
83struct mbus_win {
84 u32 base;
85 u32 size;
86 u8 target;
87 u8 attr;
88};
89
90/*
91 * System registers
92 * Ref: Datasheet sec:A.28
93 */
94struct mvebu_system_registers {
Stefan Roese479f9af2016-02-10 07:23:00 +010095#if defined(CONFIG_ARMADA_375)
96 u8 pad1[0x54];
97#else
Stefan Roese93e6bf42014-10-22 12:13:17 +020098 u8 pad1[0x60];
Stefan Roese479f9af2016-02-10 07:23:00 +010099#endif
Stefan Roese93e6bf42014-10-22 12:13:17 +0200100 u32 rstoutn_mask; /* 0x60 */
101 u32 sys_soft_rst; /* 0x64 */
102};
103
104/*
105 * GPIO Registers
106 * Ref: Datasheet sec:A.19
107 */
108struct kwgpio_registers {
109 u32 dout;
110 u32 oe;
111 u32 blink_en;
112 u32 din_pol;
113 u32 din;
114 u32 irq_cause;
115 u32 irq_mask;
116 u32 irq_level;
117};
118
Stefan Roese2a539c82015-12-21 12:36:40 +0100119struct sar_freq_modes {
120 u8 val;
121 u8 ffc; /* Fabric Frequency Configuration */
122 u32 p_clk;
123 u32 nb_clk;
124 u32 d_clk;
125};
126
Stefan Roese1a16a0c2015-01-19 11:33:47 +0100127/* Needed for dynamic (board-specific) mbus configuration */
128extern struct mvebu_mbus_state mbus_state;
129
Stefan Roese93e6bf42014-10-22 12:13:17 +0200130/*
131 * functions
132 */
133unsigned int mvebu_sdram_bar(enum memory_bank bank);
134unsigned int mvebu_sdram_bs(enum memory_bank bank);
135void mvebu_sdram_size_adjust(enum memory_bank bank);
136int mvebu_mbus_probe(struct mbus_win windows[], int count);
Stefan Roese174d23e2015-04-25 06:29:51 +0200137int mvebu_soc_family(void);
Stefan Roesebadccc32015-07-16 10:40:05 +0200138u32 mvebu_get_nand_clock(void);
Stefan Roesee463bf32015-01-19 11:33:42 +0100139
Stefan Roese99b3ea72015-08-25 13:49:41 +0200140void return_to_bootrom(void);
141
Stefan Roesed3e34732015-06-29 14:58:10 +0200142int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
143
Stefan Roese2a539c82015-12-21 12:36:40 +0100144void get_sar_freq(struct sar_freq_modes *sar_freq);
145
Stefan Roesee463bf32015-01-19 11:33:42 +0100146/*
147 * Highspeed SERDES PHY config init, ported from bin_hdr
148 * to mainline U-Boot
149 */
150int serdes_phy_config(void);
151
152/*
153 * DDR3 init / training code ported from Marvell bin_hdr. Now
154 * available in mainline U-Boot in:
Stefan Roeseeb753e92015-03-25 12:51:18 +0100155 * drivers/ddr/marvell
Stefan Roesee463bf32015-01-19 11:33:42 +0100156 */
157int ddr3_init(void);
Stefan Roeseab91fd52016-01-20 08:13:28 +0100158
159struct mvebu_lcd_info {
160 u32 fb_base;
161 int x_res;
162 int y_res;
163 int x_fp; /* frontporch */
164 int y_fp;
165 int x_bp; /* backporch */
166 int y_bp;
167};
168
169int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
170
Stefan Roese05b17652016-05-17 15:00:30 +0200171/*
172 * get_ref_clk
173 *
174 * return: reference clock in MHz (25 or 40)
175 */
176u32 get_ref_clk(void);
177
Stefan Roese93e6bf42014-10-22 12:13:17 +0200178#endif /* __ASSEMBLY__ */
Stefan Roeseebda3ec2015-04-25 06:29:47 +0200179#endif /* _MVEBU_CPU_H */