Tom Rini | f48e025 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 1 | menuconfig PCI |
| 2 | bool "PCI support" |
Tom Rini | 5dec075 | 2021-05-14 21:34:32 -0400 | [diff] [blame] | 3 | depends on DM |
Bin Meng | 00a17fd | 2017-07-30 06:23:09 -0700 | [diff] [blame] | 4 | default y if PPC |
Tom Rini | f48e025 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 5 | help |
| 6 | Enable support for PCI (Peripheral Interconnect Bus), a type of bus |
| 7 | used on some devices to allow the CPU to communicate with its |
| 8 | peripherals. |
| 9 | |
Simon Glass | 3933d29 | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 10 | This subsystem requires driver model. |
Simon Glass | b94dc89 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 11 | |
Tom Rini | 5dec075 | 2021-05-14 21:34:32 -0400 | [diff] [blame] | 12 | if PCI |
| 13 | |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 14 | config DM_PCI_COMPAT |
| 15 | bool "Enable compatible functions for PCI" |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 16 | help |
| 17 | Enable compatibility functions for PCI so that old code can be used |
Simon Glass | 3933d29 | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 18 | with CONFIG_PCI enabled. This should be used as an interim |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 19 | measure when porting a board to use driver model for PCI. Once the |
| 20 | board is fully supported, this option should be disabled. |
| 21 | |
Tom Rini | 50e6f1b | 2021-12-12 22:12:32 -0500 | [diff] [blame] | 22 | config SYS_PCI_64BIT |
| 23 | bool "Enable 64-bit PCI resources" |
| 24 | default y if PPC |
| 25 | help |
| 26 | Enable 64-bit PCI resource access. |
| 27 | |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 28 | config PCI_AARDVARK |
| 29 | bool "Enable Aardvark PCIe driver" |
Pali Rohár | 5c6edca | 2020-08-25 10:45:04 +0200 | [diff] [blame] | 30 | depends on DM_GPIO |
Wilson Ding | a6bdc86 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 31 | depends on ARMADA_3700 |
| 32 | help |
| 33 | Say Y here if you want to enable PCIe controller support on |
| 34 | Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on |
| 35 | Aardvark hardware. |
| 36 | |
Bin Meng | 2f49e2e | 2016-10-16 23:35:18 -0700 | [diff] [blame] | 37 | config PCI_PNP |
| 38 | bool "Enable Plug & Play support for PCI" |
Bin Meng | 2f49e2e | 2016-10-16 23:35:18 -0700 | [diff] [blame] | 39 | default y |
| 40 | help |
| 41 | Enable PCI memory and I/O space resource allocation and assignment. |
| 42 | |
Mayuresh Chitale | 1cee77e | 2023-06-03 19:32:55 +0530 | [diff] [blame] | 43 | config SPL_PCI_PNP |
Heinrich Schuchardt | 3bccce3 | 2023-07-24 21:27:26 +0200 | [diff] [blame] | 44 | bool "Enable Plug & Play support for PCI in SPL" |
| 45 | depends on SPL_PCI |
Mayuresh Chitale | 1cee77e | 2023-06-03 19:32:55 +0530 | [diff] [blame] | 46 | help |
| 47 | Enable PCI memory and I/O space resource allocation and assignment. |
Simon Glass | 797b8e8 | 2023-07-15 21:38:55 -0600 | [diff] [blame] | 48 | |
Mayuresh Chitale | 1cee77e | 2023-06-03 19:32:55 +0530 | [diff] [blame] | 49 | This is required to auto configure the enumerated devices. |
| 50 | |
Simon Glass | 797b8e8 | 2023-07-15 21:38:55 -0600 | [diff] [blame] | 51 | This is normally not done in SPL, but can be enabled if devices must |
| 52 | be set up in the SPL phase. Often it is enough to manually configure |
| 53 | one device, so this option can be disabled. |
| 54 | |
Suneel Garapati | 3ac3aec | 2019-10-19 17:10:20 -0700 | [diff] [blame] | 55 | config PCI_REGION_MULTI_ENTRY |
| 56 | bool "Enable Multiple entries of region type MEMORY in ranges for PCI" |
Suneel Garapati | 3ac3aec | 2019-10-19 17:10:20 -0700 | [diff] [blame] | 57 | help |
| 58 | Enable PCI memory regions to be of multiple entry. Multiple entry |
| 59 | here refers to allow more than one count of address ranges for MEMORY |
| 60 | region type. This helps to add support for SoC's like OcteonTX/TX2 |
| 61 | where every peripheral is on the PCI bus. |
| 62 | |
Tom Rini | 77d9e9f | 2022-06-20 08:07:50 -0400 | [diff] [blame] | 63 | config PCI_CONFIG_HOST_BRIDGE |
| 64 | bool "Configure PCI host bridges" |
| 65 | default y if X86 |
| 66 | |
Daniel Schwierzeck | f59925e | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 67 | config PCI_MAP_SYSTEM_MEMORY |
| 68 | bool "Map local system memory from a virtual base address" |
Daniel Schwierzeck | f59925e | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 69 | depends on MIPS |
Daniel Schwierzeck | f59925e | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 70 | help |
| 71 | Say Y if base address of system memory is being used as a virtual address |
| 72 | instead of a physical address (e.g. on MIPS). The PCI core will then remap |
| 73 | the virtual memory base address to a physical address when adding the PCI |
| 74 | region of type PCI_REGION_SYS_MEMORY. |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 75 | This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still |
Daniel Schwierzeck | f59925e | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 76 | being used as virtual address. |
| 77 | |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 78 | config PCI_SRIOV |
| 79 | bool "Enable Single Root I/O Virtualization support for PCI" |
Suneel Garapati | 13822f7 | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 80 | help |
| 81 | Say Y here if you want to enable PCI Single Root I/O Virtualization |
| 82 | capability support. This helps to enumerate Virtual Function devices |
| 83 | if available on a PCI Physical Function device and probe for |
| 84 | applicable drivers. |
| 85 | |
Andrew Scull | 71e7e1a | 2022-04-21 16:11:16 +0000 | [diff] [blame] | 86 | config PCI_ENHANCED_ALLOCATION |
| 87 | bool "Enable support for Enhanced Allocation of resources" |
| 88 | default y |
| 89 | help |
| 90 | Enable support for Enhanced Allocation which can be used by supported |
| 91 | devices in place of traditional BARS for allocation of resources. |
| 92 | |
Suneel Garapati | a99a5eb | 2019-10-23 18:40:36 -0700 | [diff] [blame] | 93 | config PCI_ARID |
| 94 | bool "Enable Alternate Routing-ID support for PCI" |
Suneel Garapati | a99a5eb | 2019-10-23 18:40:36 -0700 | [diff] [blame] | 95 | help |
| 96 | Say Y here if you want to enable Alternate Routing-ID capability |
| 97 | support on PCI devices. This helps to skip some devices in BDF |
| 98 | scan that are not present. |
| 99 | |
Tom Rini | 6fe7270 | 2022-06-20 08:07:48 -0400 | [diff] [blame] | 100 | config PCI_SCAN_SHOW |
| 101 | bool "Show PCI devices during startup" |
| 102 | depends on PCIE_IMX |
| 103 | |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 104 | config PCIE_ECAM_GENERIC |
| 105 | bool "Generic ECAM-based PCI host controller support" |
Tuomas Tynkkynen | a765f71 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 106 | help |
| 107 | Say Y here if you want to enable support for generic ECAM-based |
| 108 | PCIe host controllers, such as the one emulated by QEMU. |
| 109 | |
Masami Hiramatsu | 0685020 | 2021-06-04 18:44:06 +0900 | [diff] [blame] | 110 | config PCIE_ECAM_SYNQUACER |
| 111 | bool "SynQuacer ECAM-based PCI host controller support" |
Masami Hiramatsu | 0685020 | 2021-06-04 18:44:06 +0900 | [diff] [blame] | 112 | select PCI_INIT_R |
| 113 | select PCI_REGION_MULTI_ENTRY |
| 114 | help |
| 115 | Say Y here if you want to enable support for Socionext |
| 116 | SynQuacer SoC's ECAM-based PCIe host controllers. |
| 117 | Note that this must be configured when boot because Linux driver |
| 118 | expects the PCIe RC has been configured in the bootloader. |
| 119 | |
Mark Kettenis | 59b09ba | 2023-01-21 20:27:58 +0100 | [diff] [blame] | 120 | config PCIE_APPLE |
| 121 | bool "Enable Apple PCIe driver" |
| 122 | depends on ARCH_APPLE |
| 123 | imply PCI_INIT_R |
Mark Kettenis | 973fbb5 | 2023-07-14 21:15:16 +0200 | [diff] [blame] | 124 | select SYS_PCI_64BIT |
Mark Kettenis | 59b09ba | 2023-01-21 20:27:58 +0100 | [diff] [blame] | 125 | default y |
| 126 | help |
| 127 | Say Y here if you want to enable PCIe controller support on |
| 128 | Apple SoCs. |
| 129 | |
Sergei Antonov | 026f1e9 | 2023-07-30 21:17:09 +0300 | [diff] [blame] | 130 | config PCI_FTPCI100 |
| 131 | bool "Enable Faraday FTPCI100 PCI Bridge Controller driver" |
| 132 | help |
| 133 | Say Y here if you want to enable Faraday FTPCI100 PCI. |
| 134 | FTPCI100 IP is used in SoC chip designs. |
| 135 | |
Tom Rini | e9e5758 | 2022-06-20 08:07:49 -0400 | [diff] [blame] | 136 | config PCI_GT64120 |
| 137 | bool "GT64120 PCI support" |
| 138 | depends on MIPS |
| 139 | |
liu hao | 1c4a2c4 | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 140 | config PCI_PHYTIUM |
| 141 | bool "Phytium PCIe support" |
liu hao | 1c4a2c4 | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 142 | help |
| 143 | Say Y here if you want to enable PCIe controller support on |
| 144 | Phytium SoCs. |
| 145 | |
Shadi Ammouri | 3b38645 | 2016-10-27 13:29:41 +0200 | [diff] [blame] | 146 | config PCIE_DW_MVEBU |
| 147 | bool "Enable Armada-8K PCIe driver (DesignWare core)" |
Shadi Ammouri | 3b38645 | 2016-10-27 13:29:41 +0200 | [diff] [blame] | 148 | depends on ARMADA_8K |
| 149 | help |
| 150 | Say Y here if you want to enable PCIe controller support on |
| 151 | Armada-8K SoCs. The PCIe controller on Armada-8K is based on |
| 152 | DesignWare hardware. |
| 153 | |
Green Wan | ba5919b | 2021-05-27 06:52:10 -0700 | [diff] [blame] | 154 | config PCIE_DW_SIFIVE |
| 155 | bool "Enable SiFive FU740 PCIe" |
| 156 | depends on CLK_SIFIVE_PRCI |
| 157 | depends on RESET_SIFIVE |
| 158 | depends on SIFIVE_GPIO |
| 159 | select PCIE_DW_COMMON |
| 160 | help |
| 161 | Say Y here if you want to enable PCIe controller support on |
| 162 | FU740. |
| 163 | |
Tom Rini | f24d48a | 2022-06-20 08:07:56 -0400 | [diff] [blame] | 164 | config SYS_FSL_PCI_VER_3_X |
| 165 | bool |
| 166 | |
Hou Zhiqiang | 25ff98c | 2019-04-24 22:33:02 +0800 | [diff] [blame] | 167 | config PCIE_FSL |
| 168 | bool "FSL PowerPC PCIe support" |
Tom Rini | f24d48a | 2022-06-20 08:07:56 -0400 | [diff] [blame] | 169 | select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 |
Hou Zhiqiang | 25ff98c | 2019-04-24 22:33:02 +0800 | [diff] [blame] | 170 | help |
| 171 | Say Y here if you want to enable PCIe controller support on FSL |
| 172 | PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. |
| 173 | This driver does not support SRIO_PCIE_BOOT feature. |
| 174 | |
Heiko Schocher | d647b46 | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 175 | config PCI_MPC85XX |
| 176 | bool "MPC85XX PowerPC PCI support" |
Heiko Schocher | d647b46 | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 177 | help |
| 178 | Say Y here if you want to enable PCI controller support on FSL |
| 179 | PowerPC MPC85xx SoC. |
| 180 | |
Tom Rini | b81d0d9 | 2022-06-20 08:07:55 -0400 | [diff] [blame] | 181 | config PCI_MSC01 |
| 182 | bool "MSC01 PCI support" |
| 183 | depends on TARGET_MALTA |
| 184 | |
Marek Vasut | 5012d1e | 2018-01-18 14:35:35 +0100 | [diff] [blame] | 185 | config PCI_RCAR_GEN2 |
| 186 | bool "Renesas RCar Gen2 PCIe driver" |
Marek Vasut | 5012d1e | 2018-01-18 14:35:35 +0100 | [diff] [blame] | 187 | depends on RCAR_32 |
| 188 | help |
| 189 | Say Y here if you want to enable PCIe controller support on |
| 190 | Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is |
| 191 | also used to access EHCI USB controller on the SoC. |
| 192 | |
Marek Vasut | 879b4a3 | 2018-10-16 12:49:19 +0200 | [diff] [blame] | 193 | config PCI_RCAR_GEN3 |
| 194 | bool "Renesas RCar Gen3 PCIe driver" |
Marek Vasut | 879b4a3 | 2018-10-16 12:49:19 +0200 | [diff] [blame] | 195 | depends on RCAR_GEN3 |
| 196 | help |
| 197 | Say Y here if you want to enable PCIe controller support on |
| 198 | Renesas RCar Gen3 SoCs. |
| 199 | |
Simon Glass | 4d85755 | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 200 | config PCI_SANDBOX |
| 201 | bool "Sandbox PCI support" |
Simon Glass | 3933d29 | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 202 | depends on SANDBOX |
Simon Glass | 4d85755 | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 203 | help |
| 204 | Support PCI on sandbox, as an emulated bus. This permits testing of |
| 205 | PCI feature such as bus scanning, device configuration and device |
| 206 | access. The available (emulated) devices are defined statically in |
| 207 | the device tree but the normal PCI scan technique is used to find |
| 208 | then. |
| 209 | |
Tom Rini | 6c2722e | 2022-06-20 08:07:53 -0400 | [diff] [blame] | 210 | config SH7751_PCI |
| 211 | bool "SH7751 PCI controller support" |
| 212 | depends on SH |
| 213 | help |
| 214 | SuperH PCI Bridge Configuration |
| 215 | |
Simon Glass | c78e327 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 216 | config PCI_TEGRA |
| 217 | bool "Tegra PCI support" |
Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 218 | depends on ARCH_TEGRA |
Stephen Warren | 86f6a94 | 2016-08-05 16:10:34 -0600 | [diff] [blame] | 219 | depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) |
Simon Glass | c78e327 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 220 | help |
| 221 | Enable support for the PCIe controller found on some generations of |
| 222 | Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has |
| 223 | 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports |
| 224 | with a total of 5 lanes. Some boards require this for Ethernet |
| 225 | support to work (e.g. beaver, jetson-tk1). |
| 226 | |
Suneel Garapati | 4c7d28c | 2019-10-19 17:28:01 -0700 | [diff] [blame] | 227 | config PCI_OCTEONTX |
| 228 | bool "OcteonTX PCI support" |
| 229 | depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2) |
| 230 | help |
| 231 | Enable support for the OcteonTX/TX2 SoC family ECAM/PEM controllers. |
| 232 | These controllers provide PCI configuration access to all on-board |
| 233 | peripherals so it should only be disabled for testing purposes |
| 234 | |
Stefan Roese | 098c773 | 2021-04-07 08:43:35 +0200 | [diff] [blame] | 235 | config PCIE_OCTEON |
| 236 | bool "MIPS Octeon PCIe support" |
| 237 | depends on ARCH_OCTEON |
| 238 | help |
| 239 | Enable support for the MIPS Octeon SoC family PCIe controllers. |
| 240 | |
Paul Burton | c893f21 | 2016-09-08 07:47:31 +0100 | [diff] [blame] | 241 | config PCI_XILINX |
| 242 | bool "Xilinx AXI Bridge for PCI Express" |
Paul Burton | c893f21 | 2016-09-08 07:47:31 +0100 | [diff] [blame] | 243 | help |
| 244 | Enable support for the Xilinx AXI bridge for PCI express, an IP block |
| 245 | which can be used on some generations of Xilinx FPGAs. |
| 246 | |
Minghuan Lian | c106784 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 247 | config PCIE_LAYERSCAPE |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 248 | bool |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 249 | |
| 250 | config PCIE_LAYERSCAPE_RC |
| 251 | bool "Layerscape PCIe Root Complex mode support" |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 252 | select PCIE_LAYERSCAPE |
| 253 | help |
| 254 | Enable Layerscape PCIe Root Complex mode driver support. The Layerscape |
| 255 | SoC may have one or several PCIe controllers. Each controller can be |
| 256 | configured to Root Complex mode by clearing the corresponding bit of |
| 257 | RCW[HOST_AGT_PEX]. |
| 258 | |
Laurentiu Tudor | 7fd2350 | 2020-09-10 12:42:19 +0300 | [diff] [blame] | 259 | config PCI_IOMMU_EXTRA_MAPPINGS |
| 260 | bool "Support for specifying extra IOMMU mappings for PCI" |
| 261 | depends on PCIE_LAYERSCAPE_RC |
| 262 | help |
| 263 | Enable support for specifying extra IOMMU mappings for PCI |
| 264 | controllers through a special env var called "pci_iommu_extra" or |
| 265 | through a device tree property named "pci-iommu-extra" placed in |
| 266 | the node describing the PCI controller. |
| 267 | The intent is to cover SR-IOV scenarios which need mappings for VFs |
| 268 | and PCI hot-plug scenarios. More documentation can be found under: |
| 269 | arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra |
| 270 | |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 271 | config PCIE_LAYERSCAPE_EP |
| 272 | bool "Layerscape PCIe Endpoint mode support" |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 273 | select PCIE_LAYERSCAPE |
| 274 | select PCI_ENDPOINT |
Minghuan Lian | c106784 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 275 | help |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 276 | Enable Layerscape PCIe Endpoint mode driver support. The Layerscape |
| 277 | SoC may have one or several PCIe controllers. Each controller can be |
| 278 | configured to Endpoint mode by setting the corresponding bit of |
| 279 | RCW[HOST_AGT_PEX]. |
Minghuan Lian | c106784 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 280 | |
Hou Zhiqiang | e5d79c4 | 2019-04-08 10:15:46 +0000 | [diff] [blame] | 281 | config PCIE_LAYERSCAPE_GEN4 |
| 282 | bool "Layerscape Gen4 PCIe support" |
Hou Zhiqiang | e5d79c4 | 2019-04-08 10:15:46 +0000 | [diff] [blame] | 283 | help |
| 284 | Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or |
| 285 | several PCIe controllers. The PCIe controller can work in RC or |
| 286 | EP mode according to RCW[HOST_AGT_PEX] setting. |
| 287 | |
Pankaj Bansal | 4c65678 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 288 | config FSL_PCIE_COMPAT |
| 289 | string "PCIe compatible of Kernel DT" |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 290 | depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 |
Pankaj Bansal | 4c65678 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 291 | default "fsl,ls1012a-pcie" if ARCH_LS1012A |
| 292 | default "fsl,ls1028a-pcie" if ARCH_LS1028A |
| 293 | default "fsl,ls1043a-pcie" if ARCH_LS1043A |
| 294 | default "fsl,ls1046a-pcie" if ARCH_LS1046A |
| 295 | default "fsl,ls2080a-pcie" if ARCH_LS2080A |
| 296 | default "fsl,ls1088a-pcie" if ARCH_LS1088A |
Hou Zhiqiang | 14de76e | 2021-12-07 18:13:12 +0800 | [diff] [blame] | 297 | default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A |
Pankaj Bansal | 4c65678 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 298 | default "fsl,ls1021a-pcie" if ARCH_LS1021A |
| 299 | help |
| 300 | This compatible is used to find pci controller node in Kernel DT |
| 301 | to complete fixup. |
| 302 | |
Pankaj Bansal | 64d85a2 | 2019-11-30 13:14:10 +0000 | [diff] [blame] | 303 | config FSL_PCIE_EP_COMPAT |
| 304 | string "PCIe EP compatible of Kernel DT" |
Hou Zhiqiang | 02f1f06 | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 305 | depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 |
Pankaj Bansal | 64d85a2 | 2019-11-30 13:14:10 +0000 | [diff] [blame] | 306 | default "fsl,ls-pcie-ep" |
| 307 | help |
| 308 | This compatible is used to find pci controller ep node in Kernel DT |
| 309 | to complete fixup. |
| 310 | |
Tom Rini | 2c7b8ec | 2022-06-20 08:07:46 -0400 | [diff] [blame] | 311 | config PCIE_IMX |
| 312 | bool "i.MX PCIe support" |
| 313 | depends on ARCH_MX6 |
| 314 | |
Ley Foon Tan | dc05e63 | 2018-04-20 21:55:45 +0800 | [diff] [blame] | 315 | config PCIE_INTEL_FPGA |
| 316 | bool "Intel FPGA PCIe support" |
Ley Foon Tan | dc05e63 | 2018-04-20 21:55:45 +0800 | [diff] [blame] | 317 | help |
| 318 | Say Y here if you want to enable PCIe controller support on Intel |
| 319 | FPGA, example Stratix 10. |
| 320 | |
Srinath Mannam | d90ba42 | 2020-05-12 13:29:50 +0530 | [diff] [blame] | 321 | config PCIE_IPROC |
| 322 | bool "Iproc PCIe support" |
Srinath Mannam | d90ba42 | 2020-05-12 13:29:50 +0530 | [diff] [blame] | 323 | help |
| 324 | Broadcom iProc PCIe controller driver. |
| 325 | Say Y here if you want to enable Broadcom iProc PCIe controller, |
| 326 | |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 327 | config PCI_MVEBU |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 328 | bool "Enable Kirkwood / Armada 370/XP/375/38x PCIe driver" |
| 329 | depends on (ARCH_KIRKWOOD || ARCH_MVEBU) |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 330 | select MISC |
Pali Rohár | 5fc93e2 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 331 | select DM_RESET |
Pali Rohár | 62297ec | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 332 | select DM_GPIO |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 333 | help |
| 334 | Say Y here if you want to enable PCIe controller support on |
Pali Rohár | ed9bcb9 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 335 | Kirkwood and Armada 370/XP/375/38x SoCs. |
Stefan Roese | 3179ec6 | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 336 | |
Neil Armstrong | b46caff | 2021-03-25 15:49:18 +0100 | [diff] [blame] | 337 | config PCIE_DW_COMMON |
| 338 | bool |
Neil Armstrong | b46caff | 2021-03-25 15:49:18 +0100 | [diff] [blame] | 339 | |
Sekhar Nori | 18db23d | 2019-08-01 19:12:57 +0530 | [diff] [blame] | 340 | config PCI_KEYSTONE |
| 341 | bool "TI Keystone PCIe controller" |
Neil Armstrong | c0c39ce | 2021-03-25 15:49:19 +0100 | [diff] [blame] | 342 | select PCIE_DW_COMMON |
Sekhar Nori | 18db23d | 2019-08-01 19:12:57 +0530 | [diff] [blame] | 343 | help |
| 344 | Say Y here if you want to enable PCI controller support on AM654 SoC. |
| 345 | |
developer | ad76773 | 2019-08-22 12:26:49 +0200 | [diff] [blame] | 346 | config PCIE_MEDIATEK |
| 347 | bool "MediaTek PCIe Gen2 controller" |
developer | ad76773 | 2019-08-22 12:26:49 +0200 | [diff] [blame] | 348 | depends on ARCH_MEDIATEK |
| 349 | help |
| 350 | Say Y here if you want to enable Gen2 PCIe controller, |
| 351 | which could be found on MT7623 SoC family. |
| 352 | |
Neil Armstrong | 06e006b | 2021-03-25 15:49:21 +0100 | [diff] [blame] | 353 | config PCIE_DW_MESON |
| 354 | bool "Amlogic Meson DesignWare based PCIe controller" |
| 355 | depends on ARCH_MESON |
| 356 | select PCIE_DW_COMMON |
| 357 | help |
| 358 | Say Y here if you want to enable DW PCIe controller support on |
| 359 | Amlogic SoCs. |
| 360 | |
Jagan Teki | 0226247 | 2020-05-09 22:26:21 +0530 | [diff] [blame] | 361 | config PCIE_ROCKCHIP |
| 362 | bool "Enable Rockchip PCIe driver" |
Michal Simek | 7f6d294 | 2020-08-19 10:44:15 +0200 | [diff] [blame] | 363 | depends on ARCH_ROCKCHIP |
Jagan Teki | 427603b | 2020-07-09 23:41:02 +0530 | [diff] [blame] | 364 | select PHY_ROCKCHIP_PCIE |
Jagan Teki | 0226247 | 2020-05-09 22:26:21 +0530 | [diff] [blame] | 365 | default y if ROCKCHIP_RK3399 |
| 366 | help |
| 367 | Say Y here if you want to enable PCIe controller support on |
| 368 | Rockchip SoCs. |
| 369 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 370 | config PCIE_DW_ROCKCHIP |
| 371 | bool "Rockchip DesignWare based PCIe controller" |
| 372 | depends on ARCH_ROCKCHIP |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 373 | select PCIE_DW_COMMON |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 374 | select PHY_ROCKCHIP_SNPS_PCIE3 |
| 375 | help |
| 376 | Say Y here if you want to enable DW PCIe controller support on |
| 377 | Rockchip SoCs. |
| 378 | |
Sylwester Nawrocki | 88f51f7 | 2020-05-25 13:39:58 +0200 | [diff] [blame] | 379 | config PCI_BRCMSTB |
| 380 | bool "Broadcom STB PCIe controller" |
Sylwester Nawrocki | 88f51f7 | 2020-05-25 13:39:58 +0200 | [diff] [blame] | 381 | depends on ARCH_BCM283X |
| 382 | help |
| 383 | Say Y here if you want to enable support for PCIe controller |
| 384 | on Broadcom set-top-box (STB) SoCs. |
| 385 | This driver currently supports only BCM2711 SoC and RC mode |
| 386 | of the controller. |
Kunihiko Hayashi | 741a1f9 | 2021-07-06 19:01:09 +0900 | [diff] [blame] | 387 | |
| 388 | config PCIE_UNIPHIER |
| 389 | bool "Socionext UniPhier PCIe driver" |
Kunihiko Hayashi | 741a1f9 | 2021-07-06 19:01:09 +0900 | [diff] [blame] | 390 | depends on ARCH_UNIPHIER |
| 391 | select PHY_UNIPHIER_PCIE |
| 392 | help |
| 393 | Say Y here if you want to enable PCIe controller support on |
| 394 | UniPhier SoCs. |
| 395 | |
Stefan Roese | 038a343 | 2023-05-25 11:49:18 +0200 | [diff] [blame] | 396 | config PCIE_XILINX_NWL |
| 397 | bool "Xilinx NWL PCIe controller" |
| 398 | depends on ARCH_ZYNQMP |
| 399 | help |
| 400 | Say 'Y' here if you want support for Xilinx / AMD NWL PCIe |
| 401 | controller as Root Port. |
| 402 | |
Mason Huo | 08059f0 | 2023-07-25 17:46:48 +0800 | [diff] [blame] | 403 | config PCIE_PLDA_COMMON |
| 404 | bool |
| 405 | |
| 406 | config PCIE_STARFIVE_JH7110 |
| 407 | bool "Enable Starfive JH7110 PCIe driver" |
| 408 | select PCIE_PLDA_COMMON |
| 409 | imply STARFIVE_JH7110 |
| 410 | imply CLK_JH7110 |
| 411 | imply RESET_JH7110 |
| 412 | help |
| 413 | Say Y here if you want to enable PLDA XpressRich PCIe controller |
| 414 | support on StarFive JH7110 SoC. |
| 415 | |
Sumit Garg | 3aa5088 | 2024-03-21 20:25:03 +0530 | [diff] [blame^] | 416 | config PCIE_DW_IMX |
| 417 | bool "i.MX DW PCIe controller support" |
| 418 | depends on ARCH_IMX8M |
| 419 | select PCIE_DW_COMMON |
| 420 | select DM_REGULATOR |
| 421 | select REGMAP |
| 422 | select SYSCON |
| 423 | help |
| 424 | Say Y here if you want to enable DW PCIe controller support on |
| 425 | iMX SoCs. |
| 426 | |
Tom Rini | f48e025 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 427 | endif |