pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.
On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 26aa2b0..669e37b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -31,6 +31,7 @@
config PCI_TEGRA
bool "Tegra PCI support"
depends on TEGRA
+ depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
help
Enable support for the PCIe controller found on some generations of
Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has