blob: bdfd1f03e792be981804f3d1425eb2186c074733 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glassf87bbff2014-11-14 20:56:33 -07002/*
3 * Copyright (C) 2014 Google, Inc
4 *
5 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
6 *
7 * Modifications are:
8 * Copyright (C) 2003-2004 Linux Networx
9 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
10 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
11 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
12 * Copyright (C) 2005-2006 Tyan
13 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14 * Copyright (C) 2005-2009 coresystems GmbH
15 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
16 *
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
18 *
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
21 *
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
Simon Glassf87bbff2014-11-14 20:56:33 -070023 */
24
Simon Glass3ed840c2020-07-02 21:12:30 -060025#define LOG_CATEGORY UCLASS_PCI
26
Simon Glassf87bbff2014-11-14 20:56:33 -070027#include <common.h>
28#include <bios_emul.h>
Simon Glass358077b2023-07-15 21:38:59 -060029#include <bloblist.h>
Simon Glass1ea97892020-05-10 11:40:00 -060030#include <bootstage.h>
Simon Glassf9d94d32015-11-29 13:17:57 -070031#include <dm.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070032#include <errno.h>
Simon Glassda25eff2019-12-28 10:44:56 -070033#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060034#include <log.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070035#include <malloc.h>
36#include <pci.h>
37#include <pci_rom.h>
Simon Glass358077b2023-07-15 21:38:59 -060038#include <spl.h>
Simon Glassec86bc62022-07-30 15:52:04 -060039#include <vesa.h>
Simon Glass4ef5d2d2016-10-05 20:42:17 -060040#include <video.h>
Simon Glass50461092020-04-08 16:57:35 -060041#include <acpi/acpi_s3.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060042#include <asm/global_data.h>
Bin Mengf6d504f2015-07-06 16:31:36 +080043#include <linux/screen_info.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070044
Bin Meng62a8f7d2017-04-21 07:24:46 -070045DECLARE_GLOBAL_DATA_PTR;
Bin Meng62a8f7d2017-04-21 07:24:46 -070046
Simon Glassf9d94d32015-11-29 13:17:57 -070047__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glassf87bbff2014-11-14 20:56:33 -070048{
Bin Meng62a8f7d2017-04-21 07:24:46 -070049#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
50 if (gd->arch.prev_sleep_state == ACPI_S3) {
51 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
52 return true;
53 else
54 return false;
55 }
56#endif
57
Simon Glassf87bbff2014-11-14 20:56:33 -070058 return true;
59}
60
Bin Mengf49c4852016-06-14 02:02:40 -070061__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glassf87bbff2014-11-14 20:56:33 -070062{
Bin Meng0ea6bcb2016-06-14 02:02:39 -070063 return true;
Simon Glassf87bbff2014-11-14 20:56:33 -070064}
65
66__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
67{
68 return vendev;
69}
70
Simon Glassf9d94d32015-11-29 13:17:57 -070071static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glassf87bbff2014-11-14 20:56:33 -070072{
Simon Glassb75b15b2020-12-03 16:55:23 -070073 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Simon Glassf87bbff2014-11-14 20:56:33 -070074 struct pci_rom_header *rom_header;
75 struct pci_rom_data *rom_data;
Simon Glassdfca4462014-12-29 19:32:23 -070076 u16 rom_vendor, rom_device;
Bin Meng932f80e2015-04-24 15:48:03 +080077 u32 rom_class;
Simon Glassf87bbff2014-11-14 20:56:33 -070078 u32 vendev;
79 u32 mapped_vendev;
80 u32 rom_address;
81
Simon Glassf9d94d32015-11-29 13:17:57 -070082 vendev = pplat->vendor << 16 | pplat->device;
Simon Glassf87bbff2014-11-14 20:56:33 -070083 mapped_vendev = board_map_oprom_vendev(vendev);
84 if (vendev != mapped_vendev)
85 debug("Device ID mapped to %#08x\n", mapped_vendev);
86
Bin Meng4de38862015-07-06 16:31:33 +080087#ifdef CONFIG_VGA_BIOS_ADDR
88 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glassf87bbff2014-11-14 20:56:33 -070089#else
Simon Glass1c1695b2015-01-14 21:37:04 -070090
Simon Glassf9d94d32015-11-29 13:17:57 -070091 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glassf87bbff2014-11-14 20:56:33 -070092 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
93 debug("%s: rom_address=%x\n", __func__, rom_address);
94 return -ENOENT;
95 }
96
97 /* Enable expansion ROM address decoding. */
Simon Glassf9d94d32015-11-29 13:17:57 -070098 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
99 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glassf87bbff2014-11-14 20:56:33 -0700100#endif
101 debug("Option ROM address %x\n", rom_address);
Minghuan Lianf40ad9f2015-01-22 13:21:55 +0800102 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glassf87bbff2014-11-14 20:56:33 -0700103
104 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700105 le16_to_cpu(rom_header->signature),
106 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glassf87bbff2014-11-14 20:56:33 -0700107
Simon Glassdfca4462014-12-29 19:32:23 -0700108 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glassf87bbff2014-11-14 20:56:33 -0700109 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700110 le16_to_cpu(rom_header->signature));
Bin Menga9664732015-07-08 13:06:41 +0800111#ifndef CONFIG_VGA_BIOS_ADDR
112 /* Disable expansion ROM address decoding */
Simon Glassf9d94d32015-11-29 13:17:57 -0700113 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Menga9664732015-07-08 13:06:41 +0800114#endif
Simon Glassf87bbff2014-11-14 20:56:33 -0700115 return -EINVAL;
116 }
117
Simon Glassdfca4462014-12-29 19:32:23 -0700118 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
119 rom_vendor = le16_to_cpu(rom_data->vendor);
120 rom_device = le16_to_cpu(rom_data->device);
Simon Glassf87bbff2014-11-14 20:56:33 -0700121
122 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700123 rom_vendor, rom_device);
Simon Glassf87bbff2014-11-14 20:56:33 -0700124
125 /* If the device id is mapped, a mismatch is expected */
Simon Glassf9d94d32015-11-29 13:17:57 -0700126 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glassf87bbff2014-11-14 20:56:33 -0700127 (vendev == mapped_vendev)) {
128 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700129 rom_vendor, rom_device);
Simon Glass02db2172014-12-29 19:32:27 -0700130 /* Continue anyway */
Simon Glassf87bbff2014-11-14 20:56:33 -0700131 }
132
Bin Meng932f80e2015-04-24 15:48:03 +0800133 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
134 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
135 rom_class, rom_data->type);
Simon Glassf87bbff2014-11-14 20:56:33 -0700136
Simon Glassf9d94d32015-11-29 13:17:57 -0700137 if (pplat->class != rom_class) {
Bin Meng932f80e2015-04-24 15:48:03 +0800138 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glassf9d94d32015-11-29 13:17:57 -0700139 rom_class, pplat->class);
Simon Glassf87bbff2014-11-14 20:56:33 -0700140 }
141 *hdrp = rom_header;
142
143 return 0;
144}
145
Simon Glass7548d642016-01-15 05:23:22 -0700146/**
147 * pci_rom_load() - Load a ROM image and return a pointer to it
148 *
149 * @rom_header: Pointer to ROM image
150 * @ram_headerp: Returns a pointer to the image in RAM
151 * @allocedp: Returns true if @ram_headerp was allocated and needs
152 * to be freed
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100153 * Return: 0 if OK, -ve on error. Note that @allocedp is set up regardless of
Simon Glass7548d642016-01-15 05:23:22 -0700154 * the error state. Even if this function returns an error, it may have
155 * allocated memory.
156 */
157static int pci_rom_load(struct pci_rom_header *rom_header,
158 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glassf87bbff2014-11-14 20:56:33 -0700159{
160 struct pci_rom_data *rom_data;
161 unsigned int rom_size;
162 unsigned int image_size = 0;
163 void *target;
164
Simon Glass7548d642016-01-15 05:23:22 -0700165 *allocedp = false;
Simon Glassf87bbff2014-11-14 20:56:33 -0700166 do {
167 /* Get next image, until we see an x86 version */
168 rom_header = (struct pci_rom_header *)((void *)rom_header +
169 image_size);
170
171 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glassdfca4462014-12-29 19:32:23 -0700172 le16_to_cpu(rom_header->data));
Simon Glassf87bbff2014-11-14 20:56:33 -0700173
Simon Glassdfca4462014-12-29 19:32:23 -0700174 image_size = le16_to_cpu(rom_data->ilen) * 512;
175 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glassf87bbff2014-11-14 20:56:33 -0700176
177 if (rom_data->type != 0)
178 return -EACCES;
179
180 rom_size = rom_header->size * 512;
181
Simon Glass1b6b9b92014-12-29 19:32:24 -0700182#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glassf87bbff2014-11-14 20:56:33 -0700183 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glass1b6b9b92014-12-29 19:32:24 -0700184#else
185 target = (void *)malloc(rom_size);
186 if (!target)
187 return -ENOMEM;
Simon Glass7548d642016-01-15 05:23:22 -0700188 *allocedp = true;
Simon Glass1b6b9b92014-12-29 19:32:24 -0700189#endif
Simon Glassf87bbff2014-11-14 20:56:33 -0700190 if (target != rom_header) {
Simon Glassf6898082015-01-01 16:18:01 -0700191 ulong start = get_timer(0);
192
Simon Glassf87bbff2014-11-14 20:56:33 -0700193 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
194 rom_header, target, rom_size);
195 memcpy(target, rom_header, rom_size);
196 if (memcmp(target, rom_header, rom_size)) {
197 printf("VGA ROM copy failed\n");
198 return -EFAULT;
199 }
Simon Glassf6898082015-01-01 16:18:01 -0700200 debug("Copy took %lums\n", get_timer(start));
Simon Glassf87bbff2014-11-14 20:56:33 -0700201 }
202 *ram_headerp = target;
203
204 return 0;
205}
206
Simon Glass5b925202022-07-30 15:52:05 -0600207struct vesa_state mode_info;
Simon Glassf87bbff2014-11-14 20:56:33 -0700208
Bin Mengf6d504f2015-07-06 16:31:36 +0800209void setup_video(struct screen_info *screen_info)
210{
Bin Mengf6d504f2015-07-06 16:31:36 +0800211 struct vesa_mode_info *vesa = &mode_info.vesa;
212
Bin Menge7518442015-07-30 03:49:13 -0700213 /* Sanity test on VESA parameters */
214 if (!vesa->x_resolution || !vesa->y_resolution)
215 return;
216
Bin Mengf6d504f2015-07-06 16:31:36 +0800217 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
218
219 screen_info->lfb_width = vesa->x_resolution;
220 screen_info->lfb_height = vesa->y_resolution;
221 screen_info->lfb_depth = vesa->bits_per_pixel;
222 screen_info->lfb_linelength = vesa->bytes_per_scanline;
223 screen_info->lfb_base = vesa->phys_base_ptr;
224 screen_info->lfb_size =
225 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
226 65536);
227 screen_info->lfb_size >>= 16;
228 screen_info->red_size = vesa->red_mask_size;
229 screen_info->red_pos = vesa->red_mask_pos;
230 screen_info->green_size = vesa->green_mask_size;
231 screen_info->green_pos = vesa->green_mask_pos;
232 screen_info->blue_size = vesa->blue_mask_size;
233 screen_info->blue_pos = vesa->blue_mask_pos;
234 screen_info->rsvd_size = vesa->reserved_mask_size;
235 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Mengf6d504f2015-07-06 16:31:36 +0800236}
237
Simon Glassf9d94d32015-11-29 13:17:57 -0700238int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
239 int exec_method)
Simon Glassf87bbff2014-11-14 20:56:33 -0700240{
Simon Glassb75b15b2020-12-03 16:55:23 -0700241 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Andreas Bießmanncb8aefa2016-02-16 23:29:31 +0100242 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glassf87bbff2014-11-14 20:56:33 -0700243 int vesa_mode = -1;
Simon Glass7548d642016-01-15 05:23:22 -0700244 bool emulate, alloced;
Simon Glassf87bbff2014-11-14 20:56:33 -0700245 int ret;
246
247 /* Only execute VGA ROMs */
Simon Glassf9d94d32015-11-29 13:17:57 -0700248 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
249 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glassf87bbff2014-11-14 20:56:33 -0700250 PCI_CLASS_DISPLAY_VGA);
251 return -ENODEV;
252 }
253
Bin Mengf49c4852016-06-14 02:02:40 -0700254 if (!board_should_load_oprom(dev))
Simon Glassbaac4eb2018-10-01 12:22:44 -0600255 return log_msg_ret("Should not load OPROM", -ENXIO);
Simon Glassf87bbff2014-11-14 20:56:33 -0700256
Simon Glassf9d94d32015-11-29 13:17:57 -0700257 ret = pci_rom_probe(dev, &rom);
Simon Glassf87bbff2014-11-14 20:56:33 -0700258 if (ret)
Simon Glass528d4832023-07-15 21:38:57 -0600259 return log_msg_ret("pro", ret);
Simon Glassf87bbff2014-11-14 20:56:33 -0700260
Simon Glass7548d642016-01-15 05:23:22 -0700261 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glass528d4832023-07-15 21:38:57 -0600262 if (ret) {
263 ret = log_msg_ret("ld", ret);
Simon Glass7548d642016-01-15 05:23:22 -0700264 goto err;
Simon Glass528d4832023-07-15 21:38:57 -0600265 }
Simon Glassf87bbff2014-11-14 20:56:33 -0700266
Simon Glass7548d642016-01-15 05:23:22 -0700267 if (!board_should_run_oprom(dev)) {
Simon Glass528d4832023-07-15 21:38:57 -0600268 ret = log_msg_ret("run", -ENXIO);
Simon Glass7548d642016-01-15 05:23:22 -0700269 goto err;
270 }
Simon Glassf87bbff2014-11-14 20:56:33 -0700271
272#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
273 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
274 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
275#endif
Simon Glassc49a8f82015-01-01 16:18:05 -0700276 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glass684818d2015-01-27 22:13:34 -0700277
278 if (exec_method & PCI_ROM_USE_NATIVE) {
279#ifdef CONFIG_X86
280 emulate = false;
281#else
282 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
283 printf("BIOS native execution is only available on x86\n");
Simon Glass7548d642016-01-15 05:23:22 -0700284 ret = -ENOSYS;
285 goto err;
Simon Glass684818d2015-01-27 22:13:34 -0700286 }
287 emulate = true;
288#endif
289 } else {
290#ifdef CONFIG_BIOSEMU
291 emulate = true;
292#else
293 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
294 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glass7548d642016-01-15 05:23:22 -0700295 ret = -ENOSYS;
296 goto err;
Simon Glass684818d2015-01-27 22:13:34 -0700297 }
298 emulate = false;
299#endif
300 }
301
Simon Glassf87bbff2014-11-14 20:56:33 -0700302 if (emulate) {
Simon Glassee95ec12023-07-15 21:38:58 -0600303 if (CONFIG_IS_ENABLED(BIOSEMU)) {
304 BE_VGAInfo *info;
Simon Glassf87bbff2014-11-14 20:56:33 -0700305
Simon Glassee95ec12023-07-15 21:38:58 -0600306 log_debug("Running video BIOS with emulator...");
307 ret = biosemu_setup(dev, &info);
308 if (ret)
309 goto err;
310 biosemu_set_interrupt_handler(0x15, int15_handler);
311 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
312 true, vesa_mode, &mode_info);
313 log_debug("done\n");
314 if (ret)
315 goto err;
316 }
Simon Glassf87bbff2014-11-14 20:56:33 -0700317 } else {
Simon Glass69c5b2d2019-04-25 21:59:08 -0600318#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
Simon Glass528d4832023-07-15 21:38:57 -0600319 log_debug("Running video BIOS...");
Simon Glassf87bbff2014-11-14 20:56:33 -0700320 bios_set_interrupt_handler(0x15, int15_handler);
321
Simon Glassa0630862015-11-29 13:17:58 -0700322 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
323 &mode_info);
Simon Glass528d4832023-07-15 21:38:57 -0600324 log_debug("done\n");
Simon Glassf87bbff2014-11-14 20:56:33 -0700325#endif
326 }
Simon Glassc49a8f82015-01-01 16:18:05 -0700327 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glass7548d642016-01-15 05:23:22 -0700328 ret = 0;
Simon Glassf87bbff2014-11-14 20:56:33 -0700329
Simon Glass7548d642016-01-15 05:23:22 -0700330err:
331 if (alloced)
332 free(ram);
333 return ret;
Simon Glassf87bbff2014-11-14 20:56:33 -0700334}
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600335
Simon Glassc1e9eab2023-03-10 12:47:13 -0800336int vesa_setup_video_priv(struct vesa_mode_info *vesa, u64 fb,
Simon Glass5b925202022-07-30 15:52:05 -0600337 struct video_priv *uc_priv,
338 struct video_uc_plat *plat)
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600339{
340 if (!vesa->x_resolution)
Simon Glassbaac4eb2018-10-01 12:22:44 -0600341 return log_msg_ret("No x resolution", -ENXIO);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600342 uc_priv->xsize = vesa->x_resolution;
343 uc_priv->ysize = vesa->y_resolution;
Simon Glass7d186732018-11-29 15:08:52 -0700344 uc_priv->line_length = vesa->bytes_per_scanline;
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600345 switch (vesa->bits_per_pixel) {
346 case 32:
347 case 24:
348 uc_priv->bpix = VIDEO_BPP32;
349 break;
350 case 16:
351 uc_priv->bpix = VIDEO_BPP16;
352 break;
353 default:
354 return -EPROTONOSUPPORT;
355 }
Simon Glass3ed840c2020-07-02 21:12:30 -0600356
357 /* Use double buffering if enabled */
Simon Glass98145af2021-03-15 18:00:26 +1300358 if (IS_ENABLED(CONFIG_VIDEO_COPY) && plat->base)
Simon Glassc1e9eab2023-03-10 12:47:13 -0800359 plat->copy_base = fb;
Simon Glass98145af2021-03-15 18:00:26 +1300360 else
Simon Glassc1e9eab2023-03-10 12:47:13 -0800361 plat->base = fb;
Simon Glass3ed840c2020-07-02 21:12:30 -0600362 log_debug("base = %lx, copy_base = %lx\n", plat->base, plat->copy_base);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600363 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
364
365 return 0;
366}
367
Simon Glass5b925202022-07-30 15:52:05 -0600368int vesa_setup_video(struct udevice *dev, int (*int15_handler)(void))
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600369{
Simon Glassb75b15b2020-12-03 16:55:23 -0700370 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600371 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
372 int ret;
373
374 /* If we are running from EFI or coreboot, this can't work */
Bin Meng57b65e62016-10-09 04:14:12 -0700375 if (!ll_boot_init()) {
376 printf("Not available (previous bootloader prevents it)\n");
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600377 return -EPERM;
Bin Meng57b65e62016-10-09 04:14:12 -0700378 }
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600379
Simon Glass358077b2023-07-15 21:38:59 -0600380 /* In U-Boot proper, collect the information added by SPL (see below) */
381 if (IS_ENABLED(CONFIG_SPL_VIDEO) && spl_phase() > PHASE_SPL &&
382 CONFIG_IS_ENABLED(BLOBLIST)) {
383 struct video_handoff *ho;
384
385 ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
386 if (!ho)
387 return log_msg_ret("blf", -ENOENT);
388 plat->base = ho->fb;
389 plat->size = ho->size;
390 uc_priv->xsize = ho->xsize;
391 uc_priv->ysize = ho->ysize;
392 uc_priv->line_length = ho->line_length;
393 uc_priv->bpix = ho->bpix;
394 } else {
395 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
396 ret = dm_pci_run_vga_bios(dev, int15_handler,
397 PCI_ROM_USE_NATIVE |
398 PCI_ROM_ALLOW_FALLBACK);
399 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
400 if (ret) {
401 debug("failed to run video BIOS: %d\n", ret);
402 return ret;
Simon Glass3ed840c2020-07-02 21:12:30 -0600403 }
404
Simon Glass358077b2023-07-15 21:38:59 -0600405 ret = vesa_setup_video_priv(&mode_info.vesa,
406 mode_info.vesa.phys_base_ptr,
407 uc_priv, plat);
408 if (ret) {
409 if (ret == -ENFILE) {
410 /*
411 * See video-uclass.c for how to set up reserved
412 * memory in your video driver
413 */
414 log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n",
415 dev->driver->name);
416 }
417
418 debug("No video mode configured\n");
419 return ret;
420 }
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600421 }
422
Bin Mengbe4551e2018-04-11 22:02:18 -0700423 printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
Bin Meng57b65e62016-10-09 04:14:12 -0700424 mode_info.vesa.bits_per_pixel);
425
Simon Glass358077b2023-07-15 21:38:59 -0600426 /* In SPL, store the information for use by U-Boot proper */
427 if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(BLOBLIST)) {
428 struct video_handoff *ho;
429
430 ho = bloblist_add(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho), 0);
431 if (!ho)
432 return log_msg_ret("blc", -ENOMEM);
433
434 ho->fb = plat->base;
435 ho->size = plat->size;
436 ho->xsize = uc_priv->xsize;
437 ho->ysize = uc_priv->ysize;
438 ho->line_length = uc_priv->line_length;
439 ho->bpix = uc_priv->bpix;
440 }
441
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600442 return 0;
443}