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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glassf87bbff2014-11-14 20:56:33 -07002/*
3 * Copyright (C) 2014 Google, Inc
4 *
5 * From coreboot, originally based on the Linux kernel (drivers/pci/pci.c).
6 *
7 * Modifications are:
8 * Copyright (C) 2003-2004 Linux Networx
9 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
10 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
11 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
12 * Copyright (C) 2005-2006 Tyan
13 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14 * Copyright (C) 2005-2009 coresystems GmbH
15 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
16 *
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
18 *
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
21 *
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
Simon Glassf87bbff2014-11-14 20:56:33 -070023 */
24
Simon Glass3ed840c2020-07-02 21:12:30 -060025#define LOG_CATEGORY UCLASS_PCI
26
Simon Glassf87bbff2014-11-14 20:56:33 -070027#include <common.h>
28#include <bios_emul.h>
Simon Glass1ea97892020-05-10 11:40:00 -060029#include <bootstage.h>
Simon Glassf9d94d32015-11-29 13:17:57 -070030#include <dm.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070031#include <errno.h>
Simon Glassda25eff2019-12-28 10:44:56 -070032#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060033#include <log.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070034#include <malloc.h>
35#include <pci.h>
36#include <pci_rom.h>
37#include <vbe.h>
Simon Glass4ef5d2d2016-10-05 20:42:17 -060038#include <video.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070039#include <video_fb.h>
Simon Glass50461092020-04-08 16:57:35 -060040#include <acpi/acpi_s3.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060041#include <asm/global_data.h>
Bin Mengf6d504f2015-07-06 16:31:36 +080042#include <linux/screen_info.h>
Simon Glassf87bbff2014-11-14 20:56:33 -070043
Bin Meng62a8f7d2017-04-21 07:24:46 -070044DECLARE_GLOBAL_DATA_PTR;
Bin Meng62a8f7d2017-04-21 07:24:46 -070045
Simon Glassf9d94d32015-11-29 13:17:57 -070046__weak bool board_should_run_oprom(struct udevice *dev)
Simon Glassf87bbff2014-11-14 20:56:33 -070047{
Bin Meng62a8f7d2017-04-21 07:24:46 -070048#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME)
49 if (gd->arch.prev_sleep_state == ACPI_S3) {
50 if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN))
51 return true;
52 else
53 return false;
54 }
55#endif
56
Simon Glassf87bbff2014-11-14 20:56:33 -070057 return true;
58}
59
Bin Mengf49c4852016-06-14 02:02:40 -070060__weak bool board_should_load_oprom(struct udevice *dev)
Simon Glassf87bbff2014-11-14 20:56:33 -070061{
Bin Meng0ea6bcb2016-06-14 02:02:39 -070062 return true;
Simon Glassf87bbff2014-11-14 20:56:33 -070063}
64
65__weak uint32_t board_map_oprom_vendev(uint32_t vendev)
66{
67 return vendev;
68}
69
Simon Glassf9d94d32015-11-29 13:17:57 -070070static int pci_rom_probe(struct udevice *dev, struct pci_rom_header **hdrp)
Simon Glassf87bbff2014-11-14 20:56:33 -070071{
Simon Glassb75b15b2020-12-03 16:55:23 -070072 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Simon Glassf87bbff2014-11-14 20:56:33 -070073 struct pci_rom_header *rom_header;
74 struct pci_rom_data *rom_data;
Simon Glassdfca4462014-12-29 19:32:23 -070075 u16 rom_vendor, rom_device;
Bin Meng932f80e2015-04-24 15:48:03 +080076 u32 rom_class;
Simon Glassf87bbff2014-11-14 20:56:33 -070077 u32 vendev;
78 u32 mapped_vendev;
79 u32 rom_address;
80
Simon Glassf9d94d32015-11-29 13:17:57 -070081 vendev = pplat->vendor << 16 | pplat->device;
Simon Glassf87bbff2014-11-14 20:56:33 -070082 mapped_vendev = board_map_oprom_vendev(vendev);
83 if (vendev != mapped_vendev)
84 debug("Device ID mapped to %#08x\n", mapped_vendev);
85
Bin Meng4de38862015-07-06 16:31:33 +080086#ifdef CONFIG_VGA_BIOS_ADDR
87 rom_address = CONFIG_VGA_BIOS_ADDR;
Simon Glassf87bbff2014-11-14 20:56:33 -070088#else
Simon Glass1c1695b2015-01-14 21:37:04 -070089
Simon Glassf9d94d32015-11-29 13:17:57 -070090 dm_pci_read_config32(dev, PCI_ROM_ADDRESS, &rom_address);
Simon Glassf87bbff2014-11-14 20:56:33 -070091 if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
92 debug("%s: rom_address=%x\n", __func__, rom_address);
93 return -ENOENT;
94 }
95
96 /* Enable expansion ROM address decoding. */
Simon Glassf9d94d32015-11-29 13:17:57 -070097 dm_pci_write_config32(dev, PCI_ROM_ADDRESS,
98 rom_address | PCI_ROM_ADDRESS_ENABLE);
Simon Glassf87bbff2014-11-14 20:56:33 -070099#endif
100 debug("Option ROM address %x\n", rom_address);
Minghuan Lianf40ad9f2015-01-22 13:21:55 +0800101 rom_header = (struct pci_rom_header *)(unsigned long)rom_address;
Simon Glassf87bbff2014-11-14 20:56:33 -0700102
103 debug("PCI expansion ROM, signature %#04x, INIT size %#04x, data ptr %#04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700104 le16_to_cpu(rom_header->signature),
105 rom_header->size * 512, le16_to_cpu(rom_header->data));
Simon Glassf87bbff2014-11-14 20:56:33 -0700106
Simon Glassdfca4462014-12-29 19:32:23 -0700107 if (le16_to_cpu(rom_header->signature) != PCI_ROM_HDR) {
Simon Glassf87bbff2014-11-14 20:56:33 -0700108 printf("Incorrect expansion ROM header signature %04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700109 le16_to_cpu(rom_header->signature));
Bin Menga9664732015-07-08 13:06:41 +0800110#ifndef CONFIG_VGA_BIOS_ADDR
111 /* Disable expansion ROM address decoding */
Simon Glassf9d94d32015-11-29 13:17:57 -0700112 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
Bin Menga9664732015-07-08 13:06:41 +0800113#endif
Simon Glassf87bbff2014-11-14 20:56:33 -0700114 return -EINVAL;
115 }
116
Simon Glassdfca4462014-12-29 19:32:23 -0700117 rom_data = (((void *)rom_header) + le16_to_cpu(rom_header->data));
118 rom_vendor = le16_to_cpu(rom_data->vendor);
119 rom_device = le16_to_cpu(rom_data->device);
Simon Glassf87bbff2014-11-14 20:56:33 -0700120
121 debug("PCI ROM image, vendor ID %04x, device ID %04x,\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700122 rom_vendor, rom_device);
Simon Glassf87bbff2014-11-14 20:56:33 -0700123
124 /* If the device id is mapped, a mismatch is expected */
Simon Glassf9d94d32015-11-29 13:17:57 -0700125 if ((pplat->vendor != rom_vendor || pplat->device != rom_device) &&
Simon Glassf87bbff2014-11-14 20:56:33 -0700126 (vendev == mapped_vendev)) {
127 printf("ID mismatch: vendor ID %04x, device ID %04x\n",
Simon Glassdfca4462014-12-29 19:32:23 -0700128 rom_vendor, rom_device);
Simon Glass02db2172014-12-29 19:32:27 -0700129 /* Continue anyway */
Simon Glassf87bbff2014-11-14 20:56:33 -0700130 }
131
Bin Meng932f80e2015-04-24 15:48:03 +0800132 rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
133 debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
134 rom_class, rom_data->type);
Simon Glassf87bbff2014-11-14 20:56:33 -0700135
Simon Glassf9d94d32015-11-29 13:17:57 -0700136 if (pplat->class != rom_class) {
Bin Meng932f80e2015-04-24 15:48:03 +0800137 debug("Class Code mismatch ROM %06x, dev %06x\n",
Simon Glassf9d94d32015-11-29 13:17:57 -0700138 rom_class, pplat->class);
Simon Glassf87bbff2014-11-14 20:56:33 -0700139 }
140 *hdrp = rom_header;
141
142 return 0;
143}
144
Simon Glass7548d642016-01-15 05:23:22 -0700145/**
146 * pci_rom_load() - Load a ROM image and return a pointer to it
147 *
148 * @rom_header: Pointer to ROM image
149 * @ram_headerp: Returns a pointer to the image in RAM
150 * @allocedp: Returns true if @ram_headerp was allocated and needs
151 * to be freed
152 * @return 0 if OK, -ve on error. Note that @allocedp is set up regardless of
153 * the error state. Even if this function returns an error, it may have
154 * allocated memory.
155 */
156static int pci_rom_load(struct pci_rom_header *rom_header,
157 struct pci_rom_header **ram_headerp, bool *allocedp)
Simon Glassf87bbff2014-11-14 20:56:33 -0700158{
159 struct pci_rom_data *rom_data;
160 unsigned int rom_size;
161 unsigned int image_size = 0;
162 void *target;
163
Simon Glass7548d642016-01-15 05:23:22 -0700164 *allocedp = false;
Simon Glassf87bbff2014-11-14 20:56:33 -0700165 do {
166 /* Get next image, until we see an x86 version */
167 rom_header = (struct pci_rom_header *)((void *)rom_header +
168 image_size);
169
170 rom_data = (struct pci_rom_data *)((void *)rom_header +
Simon Glassdfca4462014-12-29 19:32:23 -0700171 le16_to_cpu(rom_header->data));
Simon Glassf87bbff2014-11-14 20:56:33 -0700172
Simon Glassdfca4462014-12-29 19:32:23 -0700173 image_size = le16_to_cpu(rom_data->ilen) * 512;
174 } while ((rom_data->type != 0) && (rom_data->indicator == 0));
Simon Glassf87bbff2014-11-14 20:56:33 -0700175
176 if (rom_data->type != 0)
177 return -EACCES;
178
179 rom_size = rom_header->size * 512;
180
Simon Glass1b6b9b92014-12-29 19:32:24 -0700181#ifdef PCI_VGA_RAM_IMAGE_START
Simon Glassf87bbff2014-11-14 20:56:33 -0700182 target = (void *)PCI_VGA_RAM_IMAGE_START;
Simon Glass1b6b9b92014-12-29 19:32:24 -0700183#else
184 target = (void *)malloc(rom_size);
185 if (!target)
186 return -ENOMEM;
Simon Glass7548d642016-01-15 05:23:22 -0700187 *allocedp = true;
Simon Glass1b6b9b92014-12-29 19:32:24 -0700188#endif
Simon Glassf87bbff2014-11-14 20:56:33 -0700189 if (target != rom_header) {
Simon Glassf6898082015-01-01 16:18:01 -0700190 ulong start = get_timer(0);
191
Simon Glassf87bbff2014-11-14 20:56:33 -0700192 debug("Copying VGA ROM Image from %p to %p, 0x%x bytes\n",
193 rom_header, target, rom_size);
194 memcpy(target, rom_header, rom_size);
195 if (memcmp(target, rom_header, rom_size)) {
196 printf("VGA ROM copy failed\n");
197 return -EFAULT;
198 }
Simon Glassf6898082015-01-01 16:18:01 -0700199 debug("Copy took %lums\n", get_timer(start));
Simon Glassf87bbff2014-11-14 20:56:33 -0700200 }
201 *ram_headerp = target;
202
203 return 0;
204}
205
Bin Mengc8990bd2015-08-13 00:29:16 -0700206struct vbe_mode_info mode_info;
Simon Glassf87bbff2014-11-14 20:56:33 -0700207
Bin Mengf6d504f2015-07-06 16:31:36 +0800208void setup_video(struct screen_info *screen_info)
209{
Bin Mengf6d504f2015-07-06 16:31:36 +0800210 struct vesa_mode_info *vesa = &mode_info.vesa;
211
Bin Menge7518442015-07-30 03:49:13 -0700212 /* Sanity test on VESA parameters */
213 if (!vesa->x_resolution || !vesa->y_resolution)
214 return;
215
Bin Mengf6d504f2015-07-06 16:31:36 +0800216 screen_info->orig_video_isVGA = VIDEO_TYPE_VLFB;
217
218 screen_info->lfb_width = vesa->x_resolution;
219 screen_info->lfb_height = vesa->y_resolution;
220 screen_info->lfb_depth = vesa->bits_per_pixel;
221 screen_info->lfb_linelength = vesa->bytes_per_scanline;
222 screen_info->lfb_base = vesa->phys_base_ptr;
223 screen_info->lfb_size =
224 ALIGN(screen_info->lfb_linelength * screen_info->lfb_height,
225 65536);
226 screen_info->lfb_size >>= 16;
227 screen_info->red_size = vesa->red_mask_size;
228 screen_info->red_pos = vesa->red_mask_pos;
229 screen_info->green_size = vesa->green_mask_size;
230 screen_info->green_pos = vesa->green_mask_pos;
231 screen_info->blue_size = vesa->blue_mask_size;
232 screen_info->blue_pos = vesa->blue_mask_pos;
233 screen_info->rsvd_size = vesa->reserved_mask_size;
234 screen_info->rsvd_pos = vesa->reserved_mask_pos;
Bin Mengf6d504f2015-07-06 16:31:36 +0800235}
236
Simon Glassf9d94d32015-11-29 13:17:57 -0700237int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
238 int exec_method)
Simon Glassf87bbff2014-11-14 20:56:33 -0700239{
Simon Glassb75b15b2020-12-03 16:55:23 -0700240 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
Andreas Bießmanncb8aefa2016-02-16 23:29:31 +0100241 struct pci_rom_header *rom = NULL, *ram = NULL;
Simon Glassf87bbff2014-11-14 20:56:33 -0700242 int vesa_mode = -1;
Simon Glass7548d642016-01-15 05:23:22 -0700243 bool emulate, alloced;
Simon Glassf87bbff2014-11-14 20:56:33 -0700244 int ret;
245
246 /* Only execute VGA ROMs */
Simon Glassf9d94d32015-11-29 13:17:57 -0700247 if (((pplat->class >> 8) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
248 debug("%s: Class %#x, should be %#x\n", __func__, pplat->class,
Simon Glassf87bbff2014-11-14 20:56:33 -0700249 PCI_CLASS_DISPLAY_VGA);
250 return -ENODEV;
251 }
252
Bin Mengf49c4852016-06-14 02:02:40 -0700253 if (!board_should_load_oprom(dev))
Simon Glassbaac4eb2018-10-01 12:22:44 -0600254 return log_msg_ret("Should not load OPROM", -ENXIO);
Simon Glassf87bbff2014-11-14 20:56:33 -0700255
Simon Glassf9d94d32015-11-29 13:17:57 -0700256 ret = pci_rom_probe(dev, &rom);
Simon Glassf87bbff2014-11-14 20:56:33 -0700257 if (ret)
258 return ret;
259
Simon Glass7548d642016-01-15 05:23:22 -0700260 ret = pci_rom_load(rom, &ram, &alloced);
Simon Glassf87bbff2014-11-14 20:56:33 -0700261 if (ret)
Simon Glass7548d642016-01-15 05:23:22 -0700262 goto err;
Simon Glassf87bbff2014-11-14 20:56:33 -0700263
Simon Glass7548d642016-01-15 05:23:22 -0700264 if (!board_should_run_oprom(dev)) {
265 ret = -ENXIO;
266 goto err;
267 }
Simon Glassf87bbff2014-11-14 20:56:33 -0700268
269#if defined(CONFIG_FRAMEBUFFER_SET_VESA_MODE) && \
270 defined(CONFIG_FRAMEBUFFER_VESA_MODE)
271 vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
272#endif
Simon Glassc49a8f82015-01-01 16:18:05 -0700273 debug("Selected vesa mode %#x\n", vesa_mode);
Simon Glass684818d2015-01-27 22:13:34 -0700274
275 if (exec_method & PCI_ROM_USE_NATIVE) {
276#ifdef CONFIG_X86
277 emulate = false;
278#else
279 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
280 printf("BIOS native execution is only available on x86\n");
Simon Glass7548d642016-01-15 05:23:22 -0700281 ret = -ENOSYS;
282 goto err;
Simon Glass684818d2015-01-27 22:13:34 -0700283 }
284 emulate = true;
285#endif
286 } else {
287#ifdef CONFIG_BIOSEMU
288 emulate = true;
289#else
290 if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
291 printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
Simon Glass7548d642016-01-15 05:23:22 -0700292 ret = -ENOSYS;
293 goto err;
Simon Glass684818d2015-01-27 22:13:34 -0700294 }
295 emulate = false;
296#endif
297 }
298
Simon Glassf87bbff2014-11-14 20:56:33 -0700299 if (emulate) {
300#ifdef CONFIG_BIOSEMU
301 BE_VGAInfo *info;
302
Simon Glassd3e0c8f2016-01-17 16:11:09 -0700303 ret = biosemu_setup(dev, &info);
Simon Glassf87bbff2014-11-14 20:56:33 -0700304 if (ret)
Simon Glass7548d642016-01-15 05:23:22 -0700305 goto err;
Simon Glassf87bbff2014-11-14 20:56:33 -0700306 biosemu_set_interrupt_handler(0x15, int15_handler);
Simon Glassd3e0c8f2016-01-17 16:11:09 -0700307 ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info,
308 true, vesa_mode, &mode_info);
Simon Glassf87bbff2014-11-14 20:56:33 -0700309 if (ret)
Simon Glass7548d642016-01-15 05:23:22 -0700310 goto err;
Simon Glassf87bbff2014-11-14 20:56:33 -0700311#endif
312 } else {
Simon Glass69c5b2d2019-04-25 21:59:08 -0600313#if defined(CONFIG_X86) && (CONFIG_IS_ENABLED(X86_32BIT_INIT) || CONFIG_TPL)
Simon Glassf87bbff2014-11-14 20:56:33 -0700314 bios_set_interrupt_handler(0x15, int15_handler);
315
Simon Glassa0630862015-11-29 13:17:58 -0700316 bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
317 &mode_info);
Simon Glassf87bbff2014-11-14 20:56:33 -0700318#endif
319 }
Simon Glassc49a8f82015-01-01 16:18:05 -0700320 debug("Final vesa mode %#x\n", mode_info.video_mode);
Simon Glass7548d642016-01-15 05:23:22 -0700321 ret = 0;
Simon Glassf87bbff2014-11-14 20:56:33 -0700322
Simon Glass7548d642016-01-15 05:23:22 -0700323err:
324 if (alloced)
325 free(ram);
326 return ret;
Simon Glassf87bbff2014-11-14 20:56:33 -0700327}
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600328
329#ifdef CONFIG_DM_VIDEO
Bin Meng23f5cb52016-10-09 04:14:15 -0700330int vbe_setup_video_priv(struct vesa_mode_info *vesa,
331 struct video_priv *uc_priv,
Simon Glassb75b15b2020-12-03 16:55:23 -0700332 struct video_uc_plat *plat)
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600333{
334 if (!vesa->x_resolution)
Simon Glassbaac4eb2018-10-01 12:22:44 -0600335 return log_msg_ret("No x resolution", -ENXIO);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600336 uc_priv->xsize = vesa->x_resolution;
337 uc_priv->ysize = vesa->y_resolution;
Simon Glass7d186732018-11-29 15:08:52 -0700338 uc_priv->line_length = vesa->bytes_per_scanline;
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600339 switch (vesa->bits_per_pixel) {
340 case 32:
341 case 24:
342 uc_priv->bpix = VIDEO_BPP32;
343 break;
344 case 16:
345 uc_priv->bpix = VIDEO_BPP16;
346 break;
347 default:
348 return -EPROTONOSUPPORT;
349 }
Simon Glass3ed840c2020-07-02 21:12:30 -0600350
351 /* Use double buffering if enabled */
352 if (IS_ENABLED(CONFIG_VIDEO_COPY)) {
353 if (!plat->base)
354 return log_msg_ret("copy", -ENFILE);
355 plat->copy_base = vesa->phys_base_ptr;
356 } else {
357 plat->base = vesa->phys_base_ptr;
358 }
359 log_debug("base = %lx, copy_base = %lx\n", plat->base, plat->copy_base);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600360 plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
361
362 return 0;
363}
364
365int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
366{
Simon Glassb75b15b2020-12-03 16:55:23 -0700367 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600368 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
369 int ret;
370
371 /* If we are running from EFI or coreboot, this can't work */
Bin Meng57b65e62016-10-09 04:14:12 -0700372 if (!ll_boot_init()) {
373 printf("Not available (previous bootloader prevents it)\n");
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600374 return -EPERM;
Bin Meng57b65e62016-10-09 04:14:12 -0700375 }
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600376 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
377 ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
378 PCI_ROM_ALLOW_FALLBACK);
379 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
380 if (ret) {
381 debug("failed to run video BIOS: %d\n", ret);
382 return ret;
383 }
384
385 ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
386 if (ret) {
Simon Glass3ed840c2020-07-02 21:12:30 -0600387 if (ret == -ENFILE) {
388 /*
389 * See video-uclass.c for how to set up reserved memory
390 * in your video driver
391 */
392 log_err("CONFIG_VIDEO_COPY enabled but driver '%s' set up no reserved memory\n",
393 dev->driver->name);
394 }
395
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600396 debug("No video mode configured\n");
397 return ret;
398 }
399
Bin Mengbe4551e2018-04-11 22:02:18 -0700400 printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
Bin Meng57b65e62016-10-09 04:14:12 -0700401 mode_info.vesa.bits_per_pixel);
402
Simon Glass4ef5d2d2016-10-05 20:42:17 -0600403 return 0;
404}
405#endif