Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2013 Google, Inc |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <clk.h> |
| 8 | #include <dm.h> |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 9 | #include <dt-structs.h> |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 10 | #include <dwmmc.h> |
| 11 | #include <errno.h> |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 12 | #include <mapmem.h> |
Simon Glass | 947fd98 | 2016-01-21 19:43:34 -0700 | [diff] [blame] | 13 | #include <pwrseq.h> |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 14 | #include <syscon.h> |
Simon Glass | 947fd98 | 2016-01-21 19:43:34 -0700 | [diff] [blame] | 15 | #include <asm/gpio.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 16 | #include <asm/arch-rockchip/clock.h> |
| 17 | #include <asm/arch-rockchip/periph.h> |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 18 | #include <linux/err.h> |
| 19 | |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 20 | struct rockchip_mmc_plat { |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 21 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 22 | struct dtd_rockchip_rk3288_dw_mshc dtplat; |
| 23 | #endif |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 24 | struct mmc_config cfg; |
| 25 | struct mmc mmc; |
| 26 | }; |
| 27 | |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 28 | struct rockchip_dwmmc_priv { |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 29 | struct clk clk; |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 30 | struct dwmci_host host; |
Simon Glass | 4188d94 | 2016-07-04 11:58:26 -0600 | [diff] [blame] | 31 | int fifo_depth; |
| 32 | bool fifo_mode; |
| 33 | u32 minmax[2]; |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) |
| 37 | { |
| 38 | struct udevice *dev = host->priv; |
| 39 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); |
| 40 | int ret; |
| 41 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 42 | ret = clk_set_rate(&priv->clk, freq); |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 43 | if (ret < 0) { |
Kever Yang | a70d1ea | 2017-06-14 16:31:49 +0800 | [diff] [blame] | 44 | debug("%s: err=%d\n", __func__, ret); |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 45 | return ret; |
| 46 | } |
| 47 | |
| 48 | return freq; |
| 49 | } |
| 50 | |
| 51 | static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) |
| 52 | { |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 53 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 54 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); |
| 55 | struct dwmci_host *host = &priv->host; |
| 56 | |
| 57 | host->name = dev->name; |
Philipp Tomsich | ff78881 | 2017-09-11 22:04:15 +0200 | [diff] [blame] | 58 | host->ioaddr = dev_read_addr_ptr(dev); |
Philipp Tomsich | 9b4c380 | 2017-06-07 18:46:00 +0200 | [diff] [blame] | 59 | host->buswidth = dev_read_u32_default(dev, "bus-width", 4); |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 60 | host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; |
| 61 | host->priv = dev; |
| 62 | |
huang lin | 8799fc1 | 2015-11-18 09:37:25 +0800 | [diff] [blame] | 63 | /* use non-removeable as sdcard and emmc as judgement */ |
Philipp Tomsich | 9b4c380 | 2017-06-07 18:46:00 +0200 | [diff] [blame] | 64 | if (dev_read_bool(dev, "non-removable")) |
huang lin | b06352f | 2016-01-08 14:06:49 +0800 | [diff] [blame] | 65 | host->dev_index = 0; |
| 66 | else |
huang lin | 8799fc1 | 2015-11-18 09:37:25 +0800 | [diff] [blame] | 67 | host->dev_index = 1; |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 68 | |
Philipp Tomsich | 9b4c380 | 2017-06-07 18:46:00 +0200 | [diff] [blame] | 69 | priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); |
| 70 | |
Simon Glass | 4188d94 | 2016-07-04 11:58:26 -0600 | [diff] [blame] | 71 | if (priv->fifo_depth < 0) |
| 72 | return -EINVAL; |
Philipp Tomsich | 9b4c380 | 2017-06-07 18:46:00 +0200 | [diff] [blame] | 73 | priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); |
Philipp Tomsich | 56b38d8 | 2017-04-25 09:52:07 +0200 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * 'clock-freq-min-max' is deprecated |
| 77 | * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) |
| 78 | */ |
Philipp Tomsich | 9b4c380 | 2017-06-07 18:46:00 +0200 | [diff] [blame] | 79 | if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { |
| 80 | int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); |
Philipp Tomsich | 56b38d8 | 2017-04-25 09:52:07 +0200 | [diff] [blame] | 81 | |
| 82 | if (val < 0) |
| 83 | return val; |
| 84 | |
| 85 | priv->minmax[0] = 400000; /* 400 kHz */ |
| 86 | priv->minmax[1] = val; |
| 87 | } else { |
| 88 | debug("%s: 'clock-freq-min-max' property was deprecated.\n", |
| 89 | __func__); |
| 90 | } |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 91 | #endif |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static int rockchip_dwmmc_probe(struct udevice *dev) |
| 96 | { |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 97 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 98 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 99 | struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); |
| 100 | struct dwmci_host *host = &priv->host; |
Simon Glass | 947fd98 | 2016-01-21 19:43:34 -0700 | [diff] [blame] | 101 | struct udevice *pwr_dev __maybe_unused; |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 102 | int ret; |
| 103 | |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 104 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 105 | struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; |
| 106 | |
| 107 | host->name = dev->name; |
| 108 | host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); |
| 109 | host->buswidth = dtplat->bus_width; |
| 110 | host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; |
| 111 | host->priv = dev; |
| 112 | host->dev_index = 0; |
| 113 | priv->fifo_depth = dtplat->fifo_depth; |
| 114 | priv->fifo_mode = 0; |
Kever Yang | 9708739 | 2017-06-14 16:31:46 +0800 | [diff] [blame] | 115 | priv->minmax[0] = 400000; /* 400 kHz */ |
| 116 | priv->minmax[1] = dtplat->max_frequency; |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 117 | |
| 118 | ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); |
| 119 | if (ret < 0) |
| 120 | return ret; |
| 121 | #else |
Kever Yang | a70d1ea | 2017-06-14 16:31:49 +0800 | [diff] [blame] | 122 | ret = clk_get_by_index(dev, 0, &priv->clk); |
Simon Glass | 8d32f4b | 2016-01-21 19:43:38 -0700 | [diff] [blame] | 123 | if (ret < 0) |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 124 | return ret; |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 125 | #endif |
huang lin | b1b71cd | 2015-11-17 14:20:24 +0800 | [diff] [blame] | 126 | host->fifoth_val = MSIZE(0x2) | |
Simon Glass | 4188d94 | 2016-07-04 11:58:26 -0600 | [diff] [blame] | 127 | RX_WMARK(priv->fifo_depth / 2 - 1) | |
| 128 | TX_WMARK(priv->fifo_depth / 2); |
huang lin | b1b71cd | 2015-11-17 14:20:24 +0800 | [diff] [blame] | 129 | |
Simon Glass | 4188d94 | 2016-07-04 11:58:26 -0600 | [diff] [blame] | 130 | host->fifo_mode = priv->fifo_mode; |
huang lin | b1b71cd | 2015-11-17 14:20:24 +0800 | [diff] [blame] | 131 | |
Simon Glass | 947fd98 | 2016-01-21 19:43:34 -0700 | [diff] [blame] | 132 | #ifdef CONFIG_PWRSEQ |
| 133 | /* Enable power if needed */ |
| 134 | ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", |
| 135 | &pwr_dev); |
| 136 | if (!ret) { |
| 137 | ret = pwrseq_set_power(pwr_dev, true); |
| 138 | if (ret) |
| 139 | return ret; |
| 140 | } |
| 141 | #endif |
Jaehoon Chung | bf819d0 | 2016-09-23 19:13:16 +0900 | [diff] [blame] | 142 | dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 143 | host->mmc = &plat->mmc; |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 144 | host->mmc->priv = &priv->host; |
Simon Glass | 77ca42b | 2016-05-01 13:52:34 -0600 | [diff] [blame] | 145 | host->mmc->dev = dev; |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 146 | upriv->mmc = host->mmc; |
| 147 | |
Simon Glass | faeef3b | 2016-06-12 23:30:24 -0600 | [diff] [blame] | 148 | return dwmci_probe(dev); |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 149 | } |
| 150 | |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 151 | static int rockchip_dwmmc_bind(struct udevice *dev) |
| 152 | { |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 153 | struct rockchip_mmc_plat *plat = dev_get_platdata(dev); |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 154 | |
Masahiro Yamada | cdb67f3 | 2016-09-06 22:17:32 +0900 | [diff] [blame] | 155 | return dwmci_bind(dev, &plat->mmc, &plat->cfg); |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 156 | } |
| 157 | |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 158 | static const struct udevice_id rockchip_dwmmc_ids[] = { |
Heiko Stuebner | 52c55a2 | 2018-09-21 10:59:46 +0200 | [diff] [blame] | 159 | { .compatible = "rockchip,rk2928-dw-mshc" }, |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 160 | { .compatible = "rockchip,rk3288-dw-mshc" }, |
| 161 | { } |
| 162 | }; |
| 163 | |
| 164 | U_BOOT_DRIVER(rockchip_dwmmc_drv) = { |
Simon Glass | 4bb9ce4 | 2016-07-04 11:58:27 -0600 | [diff] [blame] | 165 | .name = "rockchip_rk3288_dw_mshc", |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 166 | .id = UCLASS_MMC, |
| 167 | .of_match = rockchip_dwmmc_ids, |
| 168 | .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, |
Simon Glass | faeef3b | 2016-06-12 23:30:24 -0600 | [diff] [blame] | 169 | .ops = &dm_dwmci_ops, |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 170 | .bind = rockchip_dwmmc_bind, |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 171 | .probe = rockchip_dwmmc_probe, |
| 172 | .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), |
Simon Glass | ae69610 | 2016-05-14 14:03:08 -0600 | [diff] [blame] | 173 | .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat), |
Simon Glass | 4ecaa6d | 2015-08-30 16:55:37 -0600 | [diff] [blame] | 174 | }; |
Simon Glass | 947fd98 | 2016-01-21 19:43:34 -0700 | [diff] [blame] | 175 | |
| 176 | #ifdef CONFIG_PWRSEQ |
| 177 | static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable) |
| 178 | { |
| 179 | struct gpio_desc reset; |
| 180 | int ret; |
| 181 | |
| 182 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT); |
| 183 | if (ret) |
| 184 | return ret; |
| 185 | dm_gpio_set_value(&reset, 1); |
| 186 | udelay(1); |
| 187 | dm_gpio_set_value(&reset, 0); |
| 188 | udelay(200); |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = { |
| 194 | .set_power = rockchip_dwmmc_pwrseq_set_power, |
| 195 | }; |
| 196 | |
| 197 | static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = { |
| 198 | { .compatible = "mmc-pwrseq-emmc" }, |
| 199 | { } |
| 200 | }; |
| 201 | |
| 202 | U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = { |
| 203 | .name = "mmc_pwrseq_emmc", |
| 204 | .id = UCLASS_PWRSEQ, |
| 205 | .of_match = rockchip_dwmmc_pwrseq_ids, |
| 206 | .ops = &rockchip_dwmmc_pwrseq_ops, |
| 207 | }; |
| 208 | #endif |