blob: 0a261c51a84b897139679b9b967d30405ea6cac8 [file] [log] [blame]
Simon Glass4ecaa6d2015-08-30 16:55:37 -06001/*
2 * Copyright (c) 2013 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
10#include <dwmmc.h>
11#include <errno.h>
Simon Glass947fd982016-01-21 19:43:34 -070012#include <pwrseq.h>
Simon Glass4ecaa6d2015-08-30 16:55:37 -060013#include <syscon.h>
Simon Glass947fd982016-01-21 19:43:34 -070014#include <asm/gpio.h>
Simon Glass4ecaa6d2015-08-30 16:55:37 -060015#include <asm/arch/clock.h>
16#include <asm/arch/periph.h>
17#include <linux/err.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21struct rockchip_dwmmc_priv {
22 struct udevice *clk;
Simon Glass8d32f4b2016-01-21 19:43:38 -070023 int periph;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060024 struct dwmci_host host;
25};
26
27static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
28{
29 struct udevice *dev = host->priv;
30 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
31 int ret;
32
Simon Glass8d32f4b2016-01-21 19:43:38 -070033 ret = clk_set_periph_rate(priv->clk, priv->periph, freq);
Simon Glass4ecaa6d2015-08-30 16:55:37 -060034 if (ret < 0) {
35 debug("%s: err=%d\n", __func__, ret);
36 return ret;
37 }
38
39 return freq;
40}
41
42static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
43{
44 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
45 struct dwmci_host *host = &priv->host;
46
47 host->name = dev->name;
48 host->ioaddr = (void *)dev_get_addr(dev);
49 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
50 "bus-width", 4);
51 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
52 host->priv = dev;
53
huang lin8799fc12015-11-18 09:37:25 +080054 /* use non-removeable as sdcard and emmc as judgement */
55 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
huang linb06352f2016-01-08 14:06:49 +080056 host->dev_index = 0;
57 else
huang lin8799fc12015-11-18 09:37:25 +080058 host->dev_index = 1;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060059
60 return 0;
61}
62
63static int rockchip_dwmmc_probe(struct udevice *dev)
64{
65 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
66 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
67 struct dwmci_host *host = &priv->host;
Simon Glass947fd982016-01-21 19:43:34 -070068 struct udevice *pwr_dev __maybe_unused;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060069 u32 minmax[2];
70 int ret;
huang linb1b71cd2015-11-17 14:20:24 +080071 int fifo_depth;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060072
Simon Glass8d32f4b2016-01-21 19:43:38 -070073 ret = clk_get_by_index(dev, 0, &priv->clk);
74 if (ret < 0)
Simon Glass4ecaa6d2015-08-30 16:55:37 -060075 return ret;
Simon Glass8d32f4b2016-01-21 19:43:38 -070076 priv->periph = ret;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060077
huang linb1b71cd2015-11-17 14:20:24 +080078 if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
79 "clock-freq-min-max", minmax, 2))
80 return -EINVAL;
81
82 fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
83 "fifo-depth", 0);
84 if (fifo_depth < 0)
85 return -EINVAL;
86
87 host->fifoth_val = MSIZE(0x2) |
88 RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
89
90 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
91 host->fifo_mode = true;
92
Simon Glass947fd982016-01-21 19:43:34 -070093#ifdef CONFIG_PWRSEQ
94 /* Enable power if needed */
95 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
96 &pwr_dev);
97 if (!ret) {
98 ret = pwrseq_set_power(pwr_dev, true);
99 if (ret)
100 return ret;
101 }
102#endif
huang linb1b71cd2015-11-17 14:20:24 +0800103 ret = add_dwmci(host, minmax[1], minmax[0]);
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600104 if (ret)
105 return ret;
106
Simon Glass77ca42b2016-05-01 13:52:34 -0600107 host->mmc->dev = dev;
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600108 upriv->mmc = host->mmc;
109
110 return 0;
111}
112
113static const struct udevice_id rockchip_dwmmc_ids[] = {
114 { .compatible = "rockchip,rk3288-dw-mshc" },
115 { }
116};
117
118U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
119 .name = "rockchip_dwmmc",
120 .id = UCLASS_MMC,
121 .of_match = rockchip_dwmmc_ids,
122 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
123 .probe = rockchip_dwmmc_probe,
124 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
125};
Simon Glass947fd982016-01-21 19:43:34 -0700126
127#ifdef CONFIG_PWRSEQ
128static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
129{
130 struct gpio_desc reset;
131 int ret;
132
133 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
134 if (ret)
135 return ret;
136 dm_gpio_set_value(&reset, 1);
137 udelay(1);
138 dm_gpio_set_value(&reset, 0);
139 udelay(200);
140
141 return 0;
142}
143
144static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
145 .set_power = rockchip_dwmmc_pwrseq_set_power,
146};
147
148static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
149 { .compatible = "mmc-pwrseq-emmc" },
150 { }
151};
152
153U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
154 .name = "mmc_pwrseq_emmc",
155 .id = UCLASS_PWRSEQ,
156 .of_match = rockchip_dwmmc_pwrseq_ids,
157 .ops = &rockchip_dwmmc_pwrseq_ops,
158};
159#endif