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git01.mediatek.com / filogic / uboot / 273d0ec1baf3b1e05c932098b7fb54400107d4d6 / . / arch / arm / mach-omap2 / am33xx / emif4.c
blob: 3a110f2845707d14c9f5f4f7c39e6f6af1e93a9d [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * emif4.c
3 *
4 * AM33XX emif4 configuration file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/ddr_defs.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/clock.h>
Tom Rini034aba72012-07-03 09:20:06 -0700[diff] [blame]16#include <asm/arch/sys_proto.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]17#include <asm/io.h>
Tom Rini3fd44562012-07-03 08:51:34 -0700[diff] [blame]18#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]19
20DECLARE_GLOBAL_DATA_PTR;
21
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]22int dram_init(void)
23{
Tom Rinicb23d3d2014-05-21 12:57:21 -0400[diff] [blame]24#ifndef CONFIG_SKIP_LOWLEVEL_INIT
25 sdram_init();
26#endif
27
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]28 /* dram_init must store complete ramsize in gd->ram_size */
29 gd->ram_size = get_ram_size(
30 (void *)CONFIG_SYS_SDRAM_BASE,
31 CONFIG_MAX_RAM_BANK_SIZE);
32 return 0;
33}
34
Simon Glass2f949c32017-03-31 08:40:32 -0600[diff] [blame]35int dram_init_banksize(void)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]36{
37 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
38 gd->bd->bi_dram[0].size = gd->ram_size;
Simon Glass2f949c32017-03-31 08:40:32 -0600[diff] [blame]39
40 return 0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]41}
42
43
Tom Rini8de09df2014-04-09 08:25:57 -0400[diff] [blame]44#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]45#ifdef CONFIG_TI81XX
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]46static struct dmm_lisa_map_regs *hw_lisa_map_regs =
47 (struct dmm_lisa_map_regs *)DMM_BASE;
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]48#endif
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]49#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]50static struct vtp_reg *vtpreg[2] = {
51 (struct vtp_reg *)VTP0_CTRL_ADDR,
52 (struct vtp_reg *)VTP1_CTRL_ADDR};
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]53#endif
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]54#ifdef CONFIG_AM33XX
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]55static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]56#endif
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]57#ifdef CONFIG_AM43XX
58static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
59static struct cm_device_inst *cm_device =
60 (struct cm_device_inst *)CM_DEVICE_INST;
61#endif
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]62
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]63#ifdef CONFIG_TI81XX
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]64void config_dmm(const struct dmm_lisa_map_regs *regs)
65{
66 enable_dmm_clocks();
67
68 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
69 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
70 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
71 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
72
73 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
74 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
75 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
76 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
77}
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]78#endif
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]79
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]80#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]81static void config_vtp(int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]82{
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]83 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
84 &vtpreg[nr]->vtp0ctrlreg);
85 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
86 &vtpreg[nr]->vtp0ctrlreg);
87 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
88 &vtpreg[nr]->vtp0ctrlreg);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]89
90 /* Poll for READY */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]91 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]92 VTP_CTRL_READY)
93 ;
94}
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]95#endif
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]96
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]97void __weak ddr_pll_config(unsigned int ddrpll_m)
98{
99}
100
Lokesh Vutla303b2672013-12-10 15:02:21 +0530[diff] [blame]101void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]102 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]103 const struct emif_regs *regs, int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]104{
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]105 ddr_pll_config(pll);
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]106#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]107 config_vtp(nr);
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]108#endif
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]109 config_cmd_ctrl(ctrl, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]110
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]111 config_ddr_data(data, nr);
112#ifdef CONFIG_AM33XX
Lokesh Vutla303b2672013-12-10 15:02:21 +0530[diff] [blame]113 config_io_ctrl(ioregs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]114
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]115 /* Set CKE to be controlled by EMIF/DDR PHY */
116 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]117
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]118#endif
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]119#ifdef CONFIG_AM43XX
120 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
Jeroen Hofstee47c02952014-06-18 21:22:35 +0200[diff] [blame]121 while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]122 ;
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]123
124 config_io_ctrl(ioregs);
125
126 /* Set CKE to be controlled by EMIF/DDR PHY */
127 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]128
Tom Rinibe8d6352015-06-05 15:51:11 +0530[diff] [blame]129 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
130 /* Allow EMIF to control DDR_RESET */
131 writel(0x00000000, &ddrctrl->ddrioctrl);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]132#endif
133
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]134 /* Program EMIF instance */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]135 config_ddr_phy(regs, nr);
136 set_sdram_timings(regs, nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]137 if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
138 config_sdram_emif4d5(regs, nr);
139 else
140 config_sdram(regs, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]141}
142#endif