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git01.mediatek.com / filogic / uboot / 35c7e52280add598193ad953531d0f8198cfe963 / . / arch / arm / cpu / armv7 / am33xx / emif4.c
blob: 59ad25c5b093a30a3b799b69ba878a464678ea90 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * emif4.c
3 *
4 * AM33XX emif4 configuration file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/ddr_defs.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/clock.h>
Tom Rini034aba72012-07-03 09:20:06 -0700[diff] [blame]16#include <asm/arch/sys_proto.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]17#include <asm/io.h>
Tom Rini3fd44562012-07-03 08:51:34 -0700[diff] [blame]18#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]19
20DECLARE_GLOBAL_DATA_PTR;
21
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]22int dram_init(void)
23{
24 /* dram_init must store complete ramsize in gd->ram_size */
25 gd->ram_size = get_ram_size(
26 (void *)CONFIG_SYS_SDRAM_BASE,
27 CONFIG_MAX_RAM_BANK_SIZE);
28 return 0;
29}
30
31void dram_init_banksize(void)
32{
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34 gd->bd->bi_dram[0].size = gd->ram_size;
35}
36
37
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]38#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
39#ifdef CONFIG_TI81XX
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]40static struct dmm_lisa_map_regs *hw_lisa_map_regs =
41 (struct dmm_lisa_map_regs *)DMM_BASE;
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]42#endif
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]43#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]44static struct vtp_reg *vtpreg[2] = {
45 (struct vtp_reg *)VTP0_CTRL_ADDR,
46 (struct vtp_reg *)VTP1_CTRL_ADDR};
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]47#endif
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]48#ifdef CONFIG_AM33XX
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]49static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]50#endif
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]51
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]52#ifdef CONFIG_TI81XX
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]53void config_dmm(const struct dmm_lisa_map_regs *regs)
54{
55 enable_dmm_clocks();
56
57 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
58 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
59 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
60 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
61
62 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
63 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
64 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
65 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
66}
Steve Kipiszc1399b42013-07-18 15:13:04 -0400[diff] [blame]67#endif
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]68
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]69#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]70static void config_vtp(int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]71{
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]72 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
73 &vtpreg[nr]->vtp0ctrlreg);
74 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
75 &vtpreg[nr]->vtp0ctrlreg);
76 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
77 &vtpreg[nr]->vtp0ctrlreg);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]78
79 /* Poll for READY */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]80 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]81 VTP_CTRL_READY)
82 ;
83}
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]84#endif
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]85
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]86void __weak ddr_pll_config(unsigned int ddrpll_m)
87{
88}
89
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]90void config_ddr(unsigned int pll, unsigned int ioctrl,
91 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]92 const struct emif_regs *regs, int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]93{
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]94 ddr_pll_config(pll);
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]95#ifndef CONFIG_TI816X
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]96 config_vtp(nr);
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]97#endif
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]98 config_cmd_ctrl(ctrl, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]99
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]100 config_ddr_data(data, nr);
101#ifdef CONFIG_AM33XX
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]102 config_io_ctrl(ioctrl);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]103
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]104 /* Set CKE to be controlled by EMIF/DDR PHY */
105 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]106#endif
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]107
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]108 /* Program EMIF instance */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]109 config_ddr_phy(regs, nr);
110 set_sdram_timings(regs, nr);
111 config_sdram(regs, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]112}
113#endif