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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00006 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +020010#include <asm-offsets.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050011#include <config.h>
TsiChung Liew0ee47d42010-03-11 22:12:53 -060012#include <asm/cache.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050013
TsiChung Liewf6afe722007-06-18 13:50:13 -050014#define _START _start
15#define _FAULT _fault
16
TsiChung Liewf6afe722007-06-18 13:50:13 -050017#define SAVE_ALL \
18 move.w #0x2700,%sr; /* disable intrs */ \
19 subl #60,%sp; /* space for 15 regs */ \
20 moveml %d0-%d7/%a0-%a6,%sp@;
21
22#define RESTORE_ALL \
23 moveml %sp@,%d0-%d7/%a0-%a6; \
24 addl #60,%sp; /* space for 15 regs */ \
25 rte;
26
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010027#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Angelo Dureghello65d59912016-05-22 00:14:29 +020028
TsiChung Liewf6afe722007-06-18 13:50:13 -050029.text
Angelo Dureghello65d59912016-05-22 00:14:29 +020030
TsiChung Liewf6afe722007-06-18 13:50:13 -050031/*
Angelo Dureghello65d59912016-05-22 00:14:29 +020032 * Vector table. This is used for initial platform startup.
33 * These vectors are to catch any un-intended traps.
TsiChung Liewf6afe722007-06-18 13:50:13 -050034 */
35_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +020036INITSP: .long 0x00000000 /* Initial SP */
37INITPC: .long _START /* Initial PC */
TsiChung Liewf6afe722007-06-18 13:50:13 -050038
Angelo Dureghello65d59912016-05-22 00:14:29 +020039vector02_0F:
40.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
41.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050042
TsiChungLiew8592cda2007-07-05 23:06:55 -050043/* Reserved */
TsiChung Liewf6afe722007-06-18 13:50:13 -050044vector10_17:
45.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
46
Angelo Dureghello65d59912016-05-22 00:14:29 +020047vector18_1F:
48.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050049
50/* TRAP #0 - #15 */
51vector20_2F:
52.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54
55/* Reserved */
56vector30_3F:
57.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59
60vector64_127:
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69
70vector128_191:
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79
80vector192_255:
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010089#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liewf6afe722007-06-18 13:50:13 -050090
Angelo Dureghello65d59912016-05-22 00:14:29 +020091.text
TsiChung Liewf6afe722007-06-18 13:50:13 -050092
Angelo Dureghello65d59912016-05-22 00:14:29 +020093.globl _start
TsiChung Liewf6afe722007-06-18 13:50:13 -050094_start:
95 nop
96 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +020097 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewf6afe722007-06-18 13:50:13 -050098
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010099#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew8592cda2007-07-05 23:06:55 -0500100 /* Set vector base register at the beginning of the Flash */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500101 move.l #CFG_SYS_FLASH_BASE, %d0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500102 movec %d0, %VBR
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100103#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500104
Tom Rini6a5dccc2022-11-16 13:10:41 -0500105 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew942383d2007-10-25 17:12:36 -0500106 movec %d0, %RAMBAR1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500107
108 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600109 move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500110 movec %d0, %CACR /* Invalidate cache */
111 move.l #0, %d0
112 movec %d0, %ACR0
113 movec %d0, %ACR1
114
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000115#ifdef CONFIG_MCF5301x
116 move.l #(0xFC0a0010), %a0
117 move.w (%a0), %d0
118 and.l %d0, 0xEFFF
119
120 move.w %d0, (%a0)
121#endif
122
TsiChung Liewf6afe722007-06-18 13:50:13 -0500123 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200124 move.l #0, %d0
125 move.l #(ICACHE_STATUS), %a1 /* icache */
126 move.l #(DCACHE_STATUS), %a2 /* icache */
127 move.l %d0, (%a1)
128 move.l %d0, (%a2)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500129
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200130 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200131 move.l #__got_start, %a5
TsiChung Liewf6afe722007-06-18 13:50:13 -0500132
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200133 /* setup stack initially on top of internal static ram */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500134 move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200135
136 /*
137 * if configured, malloc_f arena will be reserved first,
138 * then (and always) gd struct space will be reserved
139 */
140 move.l %sp, -(%sp)
141 move.l #board_init_f_alloc_reserve, %a1
142 jsr (%a1)
143
144 /* update stack and frame-pointers */
145 move.l %d0, %sp
146 move.l %sp, %fp
147
148 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200149 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200150 move.l #board_init_f_init_reserve, %a1
151 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500152
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200153 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200154 move.l #cpu_init_f, %a1
155 jsr (%a1)
156
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200157 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200158 clr.l %sp@-
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200159 move.l #board_init_f, %a1
160 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500161
162 /* board_init_f() does not return */
163
Angelo Dureghello65d59912016-05-22 00:14:29 +0200164/******************************************************************************/
TsiChung Liewf6afe722007-06-18 13:50:13 -0500165
166/*
Simon Glass284f71b2019-12-28 10:44:45 -0700167 * void relocate_code(addr_sp, gd, addr_moni)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500168 *
169 * This "function" does not return, instead it continues in RAM
170 * after relocating the monitor code.
171 *
172 * r3 = dest
173 * r4 = src
174 * r5 = length in bytes
175 * r6 = cachelinesize
176 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200177.globl relocate_code
TsiChung Liewf6afe722007-06-18 13:50:13 -0500178relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200179 link.w %a6,#0
180 move.l 8(%a6), %sp /* set new stack pointer */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500181
Angelo Dureghello65d59912016-05-22 00:14:29 +0200182 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
183 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500184
Angelo Dureghello65d59912016-05-22 00:14:29 +0200185 move.l #CONFIG_SYS_MONITOR_BASE, %a1
186 move.l #__init_end, %a2
187 move.l %a0, %a3
TsiChung Liewf6afe722007-06-18 13:50:13 -0500188
189 /* copy the code to RAM */
1901:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200191 move.l (%a1)+, (%a3)+
192 cmp.l %a1,%a2
193 bgt.s 1b
TsiChung Liewf6afe722007-06-18 13:50:13 -0500194
195/*
196 * We are done. Do not return, instead branch to second part of board
197 * initialization, now running from RAM.
198 */
199 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500201 jmp (%a1)
202
203in_ram:
204
205clear_bss:
206 /*
207 * Now clear BSS segment
208 */
209 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500211 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChung Liewf6afe722007-06-18 13:50:13 -05002136:
214 clr.l (%a1)+
215 cmp.l %a1,%d1
216 bgt.s 6b
217
218 /*
219 * fix got table in RAM
220 */
221 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200223 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500224
225 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChung Liewf6afe722007-06-18 13:50:13 -0500227
2287:
229 move.l (%a1),%d1
230 sub.l #_start,%d1
231 add.l %a0,%d1
232 move.l %d1,(%a1)+
233 cmp.l %a2, %a1
234 bne 7b
235
236 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200237 move.l %a0, %a1
238 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500239
240 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200241 move.l %a0,-(%sp) /* dest_addr */
242 move.l %d0,-(%sp) /* gd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500243 jsr (%a1)
244
Angelo Dureghello65d59912016-05-22 00:14:29 +0200245/******************************************************************************/
246
TsiChung Liewf6afe722007-06-18 13:50:13 -0500247/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200248.globl _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500249_fault:
Marek Vasut876813b2012-10-03 13:28:43 +0000250 bra _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500251
Angelo Dureghello65d59912016-05-22 00:14:29 +0200252.globl _exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500253_exc_handler:
254 SAVE_ALL
255 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200256 bsr exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500257 addql #4,%sp
258 RESTORE_ALL
259
Angelo Dureghello65d59912016-05-22 00:14:29 +0200260.globl _int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500261_int_handler:
262 SAVE_ALL
263 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200264 bsr int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500265 addql #4,%sp
266 RESTORE_ALL
267
Angelo Dureghello65d59912016-05-22 00:14:29 +0200268/******************************************************************************/
269
Angelo Dureghello65d59912016-05-22 00:14:29 +0200270.align 4