Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 4 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
| 5 | * |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 6 | * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. |
| 7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 10 | #include <asm-offsets.h> |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 11 | #include <config.h> |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 12 | #include <asm/cache.h> |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 13 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 14 | #define _START _start |
| 15 | #define _FAULT _fault |
| 16 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 17 | #define SAVE_ALL \ |
| 18 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 19 | subl #60,%sp; /* space for 15 regs */ \ |
| 20 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 21 | |
| 22 | #define RESTORE_ALL \ |
| 23 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 24 | addl #60,%sp; /* space for 15 regs */ \ |
| 25 | rte; |
| 26 | |
Wolfgang Wegner | ea32ab2 | 2010-03-02 10:59:20 +0100 | [diff] [blame] | 27 | #if !defined(CONFIG_MONITOR_IS_IN_RAM) |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 28 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 29 | .text |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 30 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 31 | /* |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 32 | * Vector table. This is used for initial platform startup. |
| 33 | * These vectors are to catch any un-intended traps. |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 34 | */ |
| 35 | _vectors: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 36 | INITSP: .long 0x00000000 /* Initial SP */ |
| 37 | INITPC: .long _START /* Initial PC */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 38 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 39 | vector02_0F: |
| 40 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 41 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 42 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 43 | /* Reserved */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 44 | vector10_17: |
| 45 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 46 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 47 | vector18_1F: |
| 48 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 49 | |
| 50 | /* TRAP #0 - #15 */ |
| 51 | vector20_2F: |
| 52 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 53 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 54 | |
| 55 | /* Reserved */ |
| 56 | vector30_3F: |
| 57 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 58 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 59 | |
| 60 | vector64_127: |
| 61 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 62 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 63 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 64 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 65 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 66 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 67 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 68 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 69 | |
| 70 | vector128_191: |
| 71 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 72 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 73 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 74 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 75 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 76 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 77 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 78 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 79 | |
| 80 | vector192_255: |
| 81 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 82 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 83 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 84 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 85 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 86 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 87 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 88 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
Wolfgang Wegner | ea32ab2 | 2010-03-02 10:59:20 +0100 | [diff] [blame] | 89 | #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 90 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 91 | .text |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 92 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 93 | .globl _start |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 94 | _start: |
| 95 | nop |
| 96 | nop |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 97 | move.w #0x2700,%sr /* Mask off Interrupt */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 98 | |
Wolfgang Wegner | ea32ab2 | 2010-03-02 10:59:20 +0100 | [diff] [blame] | 99 | #if !defined(CONFIG_MONITOR_IS_IN_RAM) |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 100 | /* Set vector base register at the beginning of the Flash */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 101 | move.l #CFG_SYS_FLASH_BASE, %d0 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 102 | movec %d0, %VBR |
Wolfgang Wegner | ea32ab2 | 2010-03-02 10:59:20 +0100 | [diff] [blame] | 103 | #endif |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 104 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 105 | move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | 942383d | 2007-10-25 17:12:36 -0500 | [diff] [blame] | 106 | movec %d0, %RAMBAR1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 107 | |
| 108 | /* invalidate and disable cache */ |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 109 | move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 110 | movec %d0, %CACR /* Invalidate cache */ |
| 111 | move.l #0, %d0 |
| 112 | movec %d0, %ACR0 |
| 113 | movec %d0, %ACR1 |
| 114 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 115 | #ifdef CONFIG_MCF5301x |
| 116 | move.l #(0xFC0a0010), %a0 |
| 117 | move.w (%a0), %d0 |
| 118 | and.l %d0, 0xEFFF |
| 119 | |
| 120 | move.w %d0, (%a0) |
| 121 | #endif |
| 122 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 123 | /* initialize general use internal ram */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 124 | move.l #0, %d0 |
| 125 | move.l #(ICACHE_STATUS), %a1 /* icache */ |
| 126 | move.l #(DCACHE_STATUS), %a2 /* icache */ |
| 127 | move.l %d0, (%a1) |
| 128 | move.l %d0, (%a2) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 129 | |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 130 | /* put relocation table address to a5 */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 131 | move.l #__got_start, %a5 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 132 | |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 133 | /* setup stack initially on top of internal static ram */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 134 | move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 135 | |
| 136 | /* |
| 137 | * if configured, malloc_f arena will be reserved first, |
| 138 | * then (and always) gd struct space will be reserved |
| 139 | */ |
| 140 | move.l %sp, -(%sp) |
| 141 | move.l #board_init_f_alloc_reserve, %a1 |
| 142 | jsr (%a1) |
| 143 | |
| 144 | /* update stack and frame-pointers */ |
| 145 | move.l %d0, %sp |
| 146 | move.l %sp, %fp |
| 147 | |
| 148 | /* initialize reserved area */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 149 | move.l %d0, -(%sp) |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 150 | move.l #board_init_f_init_reserve, %a1 |
| 151 | jsr (%a1) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 152 | |
angelo@sysam.it | b8cd132 | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 153 | /* run low-level CPU init code (from flash) */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 154 | move.l #cpu_init_f, %a1 |
| 155 | jsr (%a1) |
| 156 | |
angelo@sysam.it | b8cd132 | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 157 | /* run low-level board init code (from flash) */ |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 158 | clr.l %sp@- |
angelo@sysam.it | b8cd132 | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 159 | move.l #board_init_f, %a1 |
| 160 | jsr (%a1) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 161 | |
| 162 | /* board_init_f() does not return */ |
| 163 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 164 | /******************************************************************************/ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 165 | |
| 166 | /* |
Simon Glass | 284f71b | 2019-12-28 10:44:45 -0700 | [diff] [blame] | 167 | * void relocate_code(addr_sp, gd, addr_moni) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 168 | * |
| 169 | * This "function" does not return, instead it continues in RAM |
| 170 | * after relocating the monitor code. |
| 171 | * |
| 172 | * r3 = dest |
| 173 | * r4 = src |
| 174 | * r5 = length in bytes |
| 175 | * r6 = cachelinesize |
| 176 | */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 177 | .globl relocate_code |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 178 | relocate_code: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 179 | link.w %a6,#0 |
| 180 | move.l 8(%a6), %sp /* set new stack pointer */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 181 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 182 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 183 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 184 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 185 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
| 186 | move.l #__init_end, %a2 |
| 187 | move.l %a0, %a3 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 188 | |
| 189 | /* copy the code to RAM */ |
| 190 | 1: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 191 | move.l (%a1)+, (%a3)+ |
| 192 | cmp.l %a1,%a2 |
| 193 | bgt.s 1b |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 194 | |
| 195 | /* |
| 196 | * We are done. Do not return, instead branch to second part of board |
| 197 | * initialization, now running from RAM. |
| 198 | */ |
| 199 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 201 | jmp (%a1) |
| 202 | |
| 203 | in_ram: |
| 204 | |
| 205 | clear_bss: |
| 206 | /* |
| 207 | * Now clear BSS segment |
| 208 | */ |
| 209 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 211 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 213 | 6: |
| 214 | clr.l (%a1)+ |
| 215 | cmp.l %a1,%d1 |
| 216 | bgt.s 6b |
| 217 | |
| 218 | /* |
| 219 | * fix got table in RAM |
| 220 | */ |
| 221 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 222 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 223 | move.l %a1,%a5 /* fix got pointer register a5 */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 224 | |
| 225 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 227 | |
| 228 | 7: |
| 229 | move.l (%a1),%d1 |
| 230 | sub.l #_start,%d1 |
| 231 | add.l %a0,%d1 |
| 232 | move.l %d1,(%a1)+ |
| 233 | cmp.l %a2, %a1 |
| 234 | bne 7b |
| 235 | |
| 236 | /* calculate relative jump to board_init_r in ram */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 237 | move.l %a0, %a1 |
| 238 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 239 | |
| 240 | /* set parameters for board_init_r */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 241 | move.l %a0,-(%sp) /* dest_addr */ |
| 242 | move.l %d0,-(%sp) /* gd */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 243 | jsr (%a1) |
| 244 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 245 | /******************************************************************************/ |
| 246 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 247 | /* exception code */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 248 | .globl _fault |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 249 | _fault: |
Marek Vasut | 876813b | 2012-10-03 13:28:43 +0000 | [diff] [blame] | 250 | bra _fault |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 251 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 252 | .globl _exc_handler |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 253 | _exc_handler: |
| 254 | SAVE_ALL |
| 255 | movel %sp,%sp@- |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 256 | bsr exc_handler |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 257 | addql #4,%sp |
| 258 | RESTORE_ALL |
| 259 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 260 | .globl _int_handler |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 261 | _int_handler: |
| 262 | SAVE_ALL |
| 263 | movel %sp,%sp@- |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 264 | bsr int_handler |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 265 | addql #4,%sp |
| 266 | RESTORE_ALL |
| 267 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 268 | /******************************************************************************/ |
| 269 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 270 | .align 4 |