blob: 4411e5fe28c640c7808637dac0042c2818350021 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liewf6afe722007-06-18 13:50:13 -05002/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00006 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liewf6afe722007-06-18 13:50:13 -05008 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +020010#include <asm-offsets.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050011#include <config.h>
12#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -060013#include <asm/cache.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050014
TsiChung Liewf6afe722007-06-18 13:50:13 -050015#define _START _start
16#define _FAULT _fault
17
TsiChung Liewf6afe722007-06-18 13:50:13 -050018#define SAVE_ALL \
19 move.w #0x2700,%sr; /* disable intrs */ \
20 subl #60,%sp; /* space for 15 regs */ \
21 moveml %d0-%d7/%a0-%a6,%sp@;
22
23#define RESTORE_ALL \
24 moveml %sp@,%d0-%d7/%a0-%a6; \
25 addl #60,%sp; /* space for 15 regs */ \
26 rte;
27
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010028#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Angelo Dureghello65d59912016-05-22 00:14:29 +020029
TsiChung Liewf6afe722007-06-18 13:50:13 -050030.text
Angelo Dureghello65d59912016-05-22 00:14:29 +020031
TsiChung Liewf6afe722007-06-18 13:50:13 -050032/*
Angelo Dureghello65d59912016-05-22 00:14:29 +020033 * Vector table. This is used for initial platform startup.
34 * These vectors are to catch any un-intended traps.
TsiChung Liewf6afe722007-06-18 13:50:13 -050035 */
36_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +020037INITSP: .long 0x00000000 /* Initial SP */
38INITPC: .long _START /* Initial PC */
TsiChung Liewf6afe722007-06-18 13:50:13 -050039
Angelo Dureghello65d59912016-05-22 00:14:29 +020040vector02_0F:
41.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
42.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050043
TsiChungLiew8592cda2007-07-05 23:06:55 -050044/* Reserved */
TsiChung Liewf6afe722007-06-18 13:50:13 -050045vector10_17:
46.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
47
Angelo Dureghello65d59912016-05-22 00:14:29 +020048vector18_1F:
49.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050050
51/* TRAP #0 - #15 */
52vector20_2F:
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55
56/* Reserved */
57vector30_3F:
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60
61vector64_127:
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70
71vector128_191:
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80
81vector192_255:
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010090#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liewf6afe722007-06-18 13:50:13 -050091
Angelo Dureghello65d59912016-05-22 00:14:29 +020092.text
TsiChung Liewf6afe722007-06-18 13:50:13 -050093
Angelo Dureghello65d59912016-05-22 00:14:29 +020094.globl _start
TsiChung Liewf6afe722007-06-18 13:50:13 -050095_start:
96 nop
97 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +020098 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewf6afe722007-06-18 13:50:13 -050099
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100100#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew8592cda2007-07-05 23:06:55 -0500101 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500103 movec %d0, %VBR
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100104#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500105
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew942383d2007-10-25 17:12:36 -0500107 movec %d0, %RAMBAR1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500108
109 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600110 move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500111 movec %d0, %CACR /* Invalidate cache */
112 move.l #0, %d0
113 movec %d0, %ACR0
114 movec %d0, %ACR1
115
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000116#ifdef CONFIG_MCF5301x
117 move.l #(0xFC0a0010), %a0
118 move.w (%a0), %d0
119 and.l %d0, 0xEFFF
120
121 move.w %d0, (%a0)
122#endif
123
TsiChung Liewf6afe722007-06-18 13:50:13 -0500124 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200125 move.l #0, %d0
126 move.l #(ICACHE_STATUS), %a1 /* icache */
127 move.l #(DCACHE_STATUS), %a2 /* icache */
128 move.l %d0, (%a1)
129 move.l %d0, (%a2)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500130
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200131 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200132 move.l #__got_start, %a5
TsiChung Liewf6afe722007-06-18 13:50:13 -0500133
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200134 /* setup stack initially on top of internal static ram */
135 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
136
137 /*
138 * if configured, malloc_f arena will be reserved first,
139 * then (and always) gd struct space will be reserved
140 */
141 move.l %sp, -(%sp)
142 move.l #board_init_f_alloc_reserve, %a1
143 jsr (%a1)
144
145 /* update stack and frame-pointers */
146 move.l %d0, %sp
147 move.l %sp, %fp
148
149 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200150 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200151 move.l #board_init_f_init_reserve, %a1
152 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500153
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200154 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200155 move.l #cpu_init_f, %a1
156 jsr (%a1)
157
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200158 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200159 clr.l %sp@-
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200160 move.l #board_init_f, %a1
161 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500162
163 /* board_init_f() does not return */
164
Angelo Dureghello65d59912016-05-22 00:14:29 +0200165/******************************************************************************/
TsiChung Liewf6afe722007-06-18 13:50:13 -0500166
167/*
168 * void relocate_code (addr_sp, gd, addr_moni)
169 *
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
172 *
173 * r3 = dest
174 * r4 = src
175 * r5 = length in bytes
176 * r6 = cachelinesize
177 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200178.globl relocate_code
TsiChung Liewf6afe722007-06-18 13:50:13 -0500179relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200180 link.w %a6,#0
181 move.l 8(%a6), %sp /* set new stack pointer */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500182
Angelo Dureghello65d59912016-05-22 00:14:29 +0200183 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
184 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500185
Angelo Dureghello65d59912016-05-22 00:14:29 +0200186 move.l #CONFIG_SYS_MONITOR_BASE, %a1
187 move.l #__init_end, %a2
188 move.l %a0, %a3
TsiChung Liewf6afe722007-06-18 13:50:13 -0500189
190 /* copy the code to RAM */
1911:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200192 move.l (%a1)+, (%a3)+
193 cmp.l %a1,%a2
194 bgt.s 1b
TsiChung Liewf6afe722007-06-18 13:50:13 -0500195
196/*
197 * We are done. Do not return, instead branch to second part of board
198 * initialization, now running from RAM.
199 */
200 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500202 jmp (%a1)
203
204in_ram:
205
206clear_bss:
207 /*
208 * Now clear BSS segment
209 */
210 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500212 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChung Liewf6afe722007-06-18 13:50:13 -05002146:
215 clr.l (%a1)+
216 cmp.l %a1,%d1
217 bgt.s 6b
218
219 /*
220 * fix got table in RAM
221 */
222 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200224 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500225
226 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChung Liewf6afe722007-06-18 13:50:13 -0500228
2297:
230 move.l (%a1),%d1
231 sub.l #_start,%d1
232 add.l %a0,%d1
233 move.l %d1,(%a1)+
234 cmp.l %a2, %a1
235 bne 7b
236
237 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200238 move.l %a0, %a1
239 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500240
241 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200242 move.l %a0,-(%sp) /* dest_addr */
243 move.l %d0,-(%sp) /* gd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500244 jsr (%a1)
245
Angelo Dureghello65d59912016-05-22 00:14:29 +0200246/******************************************************************************/
247
TsiChung Liewf6afe722007-06-18 13:50:13 -0500248/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200249.globl _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500250_fault:
Marek Vasut876813b2012-10-03 13:28:43 +0000251 bra _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500252
Angelo Dureghello65d59912016-05-22 00:14:29 +0200253.globl _exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500254_exc_handler:
255 SAVE_ALL
256 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200257 bsr exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500258 addql #4,%sp
259 RESTORE_ALL
260
Angelo Dureghello65d59912016-05-22 00:14:29 +0200261.globl _int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500262_int_handler:
263 SAVE_ALL
264 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200265 bsr int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500266 addql #4,%sp
267 RESTORE_ALL
268
Angelo Dureghello65d59912016-05-22 00:14:29 +0200269/******************************************************************************/
270
271.globl version_string
TsiChung Liewf6afe722007-06-18 13:50:13 -0500272version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200273.ascii U_BOOT_VERSION_STRING, "\0"
274.align 4