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git01.mediatek.com / filogic / uboot / 1e73639b5dbcb1f93b6d6b37e4b970ac5122b672 / . / drivers / clk / sunxi / clk_a31.c
blob: 04f76a7c2a38f8818421ce91300e3619738f1762 [file] [log] [blame]
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]7#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]10#include <clk/sunxi.h>
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]11#include <dt-bindings/clock/sun6i-a31-ccu.h>
12#include <dt-bindings/reset/sun6i-a31-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]13#include <linux/bitops.h>
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]14
15static struct ccu_clk_gate a31_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]20 [CLK_AHB1_NAND1] = GATE(0x060, BIT(12)),
21 [CLK_AHB1_NAND0] = GATE(0x060, BIT(13)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]22 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]23 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
24 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
25 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
26 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]27 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
28 [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
29 [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
30 [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
31 [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
32 [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
33
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]34 [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
35
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]36 [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
37 [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
38 [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
39 [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]40 [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
41 [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
42 [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
43 [CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
44 [CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
45 [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
46
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]47 [CLK_NAND0] = GATE(0x080, BIT(31)),
48 [CLK_NAND1] = GATE(0x084, BIT(31)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]49 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
50 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
51 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
52 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
53
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]54 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
55 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
56 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
57 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
58 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
59 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
60};
61
62static struct ccu_reset a31_resets[] = {
63 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
64 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
65 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
66
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]67 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
68 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
69 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
70 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]71 [RST_AHB1_NAND1] = RESET(0x2c0, BIT(12)),
72 [RST_AHB1_NAND0] = RESET(0x2c0, BIT(13)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]73 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]74 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
75 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
76 [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
77 [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]78 [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
79 [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
80 [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
81 [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
82 [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
83 [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]84
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]85 [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
86 [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
87 [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
88 [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]89 [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
90 [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
91 [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
92 [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
93 [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
94 [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]95};
96
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame]97const struct ccu_desc a31_ccu_desc = {
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]98 .gates = a31_gates,
99 .resets = a31_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]100 .num_gates = ARRAY_SIZE(a31_gates),
101 .num_resets = ARRAY_SIZE(a31_resets),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]102};