clk: sunxi: Implement UART resets
Implement UART resets for all relevant Allwinner SoC
clock drivers via ccu reset table.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 145df5c..a38d76c 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -46,6 +46,13 @@
[RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+
+ [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
+ [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
+ [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
+ [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
+ [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
+ [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
};
static const struct ccu_desc a31_ccu_desc = {