8cf08ea958eaee5836f2488a06028f486ba87027 - filogic/uboot

commit	8cf08ea958eaee5836f2488a06028f486ba87027	[log] [tgz]
author	Jagan Teki <jagan@amarulasolutions.com>	Sun Dec 30 21:29:24 2018 +0530
committer	Jagan Teki <jagan@amarulasolutions.com>	Fri Jan 18 22:19:09 2019 +0530
tree	ee9b6597621711f5a8b28d18d96eb6eafca0ee09
parent	d69bf0b69540d9af1e7fea54c772c84a68471424 [diff]

clk: sunxi: Implement UART clocks

Implement UART clocks for all Allwinner SoC
clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

drivers/clk/sunxi/clk_a10.c[diff]
drivers/clk/sunxi/clk_a10s.c[diff]
drivers/clk/sunxi/clk_a23.c[diff]
drivers/clk/sunxi/clk_a31.c[diff]
drivers/clk/sunxi/clk_a64.c[diff]
drivers/clk/sunxi/clk_a83t.c[diff]
drivers/clk/sunxi/clk_h3.c[diff]
drivers/clk/sunxi/clk_r40.c[diff]
drivers/clk/sunxi/clk_v3s.c[diff]

9 files changed

tree: ee9b6597621711f5a8b28d18d96eb6eafca0ee09