Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2018 Amarula Solutions B.V. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Samuel Holland | 12e3faa | 2021-09-12 11:48:43 -0500 | [diff] [blame] | 11 | #include <clk/sunxi.h> |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 12 | #include <dt-bindings/clock/sun6i-a31-ccu.h> |
| 13 | #include <dt-bindings/reset/sun6i-a31-ccu.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 15 | |
| 16 | static struct ccu_clk_gate a31_gates[] = { |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 17 | [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), |
| 18 | [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), |
| 19 | [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), |
| 20 | [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), |
Jagan Teki | 836631b | 2019-02-28 00:26:57 +0530 | [diff] [blame] | 21 | [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 22 | [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), |
| 23 | [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), |
| 24 | [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)), |
| 25 | [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)), |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 26 | [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), |
| 27 | [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), |
| 28 | [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), |
| 29 | [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)), |
| 30 | [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), |
| 31 | [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)), |
| 32 | |
Andre Przywara | 3e9aa0b | 2022-05-04 22:10:28 +0100 | [diff] [blame] | 33 | [CLK_APB1_PIO] = GATE(0x068, BIT(5)), |
| 34 | |
Samuel Holland | fa7a7fa | 2021-09-12 09:47:24 -0500 | [diff] [blame] | 35 | [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)), |
| 36 | [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)), |
| 37 | [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)), |
| 38 | [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)), |
Jagan Teki | 8cf08ea | 2018-12-30 21:29:24 +0530 | [diff] [blame] | 39 | [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), |
| 40 | [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), |
| 41 | [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), |
| 42 | [CLK_APB2_UART3] = GATE(0x06c, BIT(19)), |
| 43 | [CLK_APB2_UART4] = GATE(0x06c, BIT(20)), |
| 44 | [CLK_APB2_UART5] = GATE(0x06c, BIT(21)), |
| 45 | |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 46 | [CLK_SPI0] = GATE(0x0a0, BIT(31)), |
| 47 | [CLK_SPI1] = GATE(0x0a4, BIT(31)), |
| 48 | [CLK_SPI2] = GATE(0x0a8, BIT(31)), |
| 49 | [CLK_SPI3] = GATE(0x0ac, BIT(31)), |
| 50 | |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 51 | [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), |
| 52 | [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), |
| 53 | [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), |
| 54 | [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), |
| 55 | [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), |
| 56 | [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), |
| 57 | }; |
| 58 | |
| 59 | static struct ccu_reset a31_resets[] = { |
| 60 | [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), |
| 61 | [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), |
| 62 | [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), |
| 63 | |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 64 | [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), |
| 65 | [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), |
| 66 | [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), |
| 67 | [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), |
Jagan Teki | 836631b | 2019-02-28 00:26:57 +0530 | [diff] [blame] | 68 | [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 69 | [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)), |
| 70 | [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)), |
| 71 | [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)), |
| 72 | [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)), |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 73 | [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), |
| 74 | [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), |
| 75 | [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), |
| 76 | [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)), |
| 77 | [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)), |
| 78 | [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)), |
Jagan Teki | b490aa5 | 2018-12-30 21:37:31 +0530 | [diff] [blame] | 79 | |
Samuel Holland | fa7a7fa | 2021-09-12 09:47:24 -0500 | [diff] [blame] | 80 | [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)), |
| 81 | [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)), |
| 82 | [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)), |
| 83 | [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)), |
Jagan Teki | b490aa5 | 2018-12-30 21:37:31 +0530 | [diff] [blame] | 84 | [RST_APB2_UART0] = RESET(0x2d8, BIT(16)), |
| 85 | [RST_APB2_UART1] = RESET(0x2d8, BIT(17)), |
| 86 | [RST_APB2_UART2] = RESET(0x2d8, BIT(18)), |
| 87 | [RST_APB2_UART3] = RESET(0x2d8, BIT(19)), |
| 88 | [RST_APB2_UART4] = RESET(0x2d8, BIT(20)), |
| 89 | [RST_APB2_UART5] = RESET(0x2d8, BIT(21)), |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 90 | }; |
| 91 | |
Samuel Holland | 751c6c6 | 2022-05-09 00:29:34 -0500 | [diff] [blame^] | 92 | const struct ccu_desc a31_ccu_desc = { |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 93 | .gates = a31_gates, |
| 94 | .resets = a31_resets, |
Samuel Holland | 8443650 | 2022-05-09 00:29:31 -0500 | [diff] [blame] | 95 | .num_gates = ARRAY_SIZE(a31_gates), |
| 96 | .num_resets = ARRAY_SIZE(a31_resets), |
Jagan Teki | 438e8f6 | 2018-08-02 23:15:34 +0530 | [diff] [blame] | 97 | }; |