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git01.mediatek.com / filogic / uboot / fa7a7fab59e6b829bdbea44d8871dc1d4d656884 / . / drivers / clk / sunxi / clk_a31.c
blob: 251fc3b705ecdf1596bb4ca3c4223ddad4890854 [file] [log] [blame]
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]12#include <dt-bindings/clock/sun6i-a31-ccu.h>
13#include <dt-bindings/reset/sun6i-a31-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]15
16static struct ccu_clk_gate a31_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
20 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]21 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]22 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
23 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
24 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
25 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]26 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
27 [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
28 [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
29 [CLK_AHB1_OHCI0] = GATE(0x060, BIT(29)),
30 [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
31 [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
32
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame^]33 [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
34 [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
35 [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
36 [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]37 [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
38 [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
39 [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
40 [CLK_APB2_UART3] = GATE(0x06c, BIT(19)),
41 [CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
42 [CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
43
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]44 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
45 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
46 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
47 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
48
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]49 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
50 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
51 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
52 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
53 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
54 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
55};
56
57static struct ccu_reset a31_resets[] = {
58 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
59 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
60 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
61
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]62 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
63 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
64 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
65 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]66 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]67 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
68 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
69 [RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
70 [RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]71 [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
72 [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
73 [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),
74 [RST_AHB1_OHCI0] = RESET(0x2c0, BIT(29)),
75 [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
76 [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]77
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame^]78 [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
79 [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
80 [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
81 [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]82 [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
83 [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
84 [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
85 [RST_APB2_UART3] = RESET(0x2d8, BIT(19)),
86 [RST_APB2_UART4] = RESET(0x2d8, BIT(20)),
87 [RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]88};
89
90static const struct ccu_desc a31_ccu_desc = {
91 .gates = a31_gates,
92 .resets = a31_resets,
93};
94
95static int a31_clk_bind(struct udevice *dev)
96{
97 return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
98}
99
100static const struct udevice_id a31_clk_ids[] = {
101 { .compatible = "allwinner,sun6i-a31-ccu",
102 .data = (ulong)&a31_ccu_desc },
103 { }
104};
105
106U_BOOT_DRIVER(clk_sun6i_a31) = {
107 .name = "sun6i_a31_ccu",
108 .id = UCLASS_CLK,
109 .of_match = a31_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]110 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki438e8f62018-08-02 23:15:34 +0530[diff] [blame]111 .ops = &sunxi_clk_ops,
112 .probe = sunxi_clk_probe,
113 .bind = a31_clk_bind,
114};