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git01.mediatek.com / filogic / uboot / 1681ca024e9ba41cad76b507c9547477908cc6f2 / . / drivers / clk / sunxi / clk_a83t.c
blob: 760d98cd620c5565df11c635befc351262b64272 [file] [log] [blame]
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
Tom Riniabb9a042024-05-18 20:20:43 -0600[diff] [blame]7#include <common.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]15
16static struct ccu_clk_gate a83t_gates[] = {
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]17 [CLK_BUS_MIPI_DSI] = GATE(0x060, BIT(1)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]18 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
19 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
20 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]21 [CLK_BUS_NAND] = GATE(0x060, BIT(13)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]22 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]23 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
24 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]25 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
26 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
27 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
28 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
29
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]30 [CLK_BUS_TCON0] = GATE(0x064, BIT(4)),
31 [CLK_BUS_TCON1] = GATE(0x064, BIT(5)),
32 [CLK_BUS_HDMI] = GATE(0x064, BIT(11)),
33 [CLK_BUS_DE] = GATE(0x064, BIT(12)),
34
Andre Przywara3e9aa0b2022-05-04 22:10:28 +0100[diff] [blame]35 [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
36
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]37 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
38 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
39 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki8cf08ea2018-12-30 21:29:24 +0530[diff] [blame]40 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
41 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
42 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
43 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
44 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
45
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]46 [CLK_NAND] = GATE(0x080, BIT(31)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]47 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
48 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
49
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]50 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
51 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
52 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
53 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
54 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]55
56 [CLK_TCON0] = GATE(0x118, BIT(31)),
57 [CLK_TCON1] = GATE(0x11c, BIT(31)),
58
59 [CLK_HDMI] = GATE(0x150, BIT(31)),
60 [CLK_HDMI_SLOW] = GATE(0x154, BIT(31)),
61
62 [CLK_MIPI_DSI0] = GATE(0x168, BIT(31)),
63 [CLK_MIPI_DSI1] = GATE(0x16c, BIT(31)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]64};
65
66static struct ccu_reset a83t_resets[] = {
67 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
68 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
69 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
70
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]71 [RST_BUS_MIPI_DSI] = RESET(0x2c0, BIT(1)),
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]72 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
73 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
74 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -0600[diff] [blame]75 [RST_BUS_NAND] = RESET(0x2c0, BIT(13)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]76 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]77 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
78 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]79 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
80 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
81 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
82 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]83
Samuel Holland1467d442022-11-28 01:02:24 -0600[diff] [blame]84 [RST_BUS_TCON0] = RESET(0x2c4, BIT(4)),
85 [RST_BUS_TCON1] = RESET(0x2c4, BIT(5)),
86 [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)),
87 [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)),
88 [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
89
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500[diff] [blame]90 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
91 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
92 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Tekib490aa52018-12-30 21:37:31 +0530[diff] [blame]93 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
94 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
95 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
96 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
97 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]98};
99
Samuel Holland751c6c62022-05-09 00:29:34 -0500[diff] [blame]100const struct ccu_desc a83t_ccu_desc = {
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]101 .gates = a83t_gates,
102 .resets = a83t_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500[diff] [blame]103 .num_gates = ARRAY_SIZE(a83t_gates),
104 .num_resets = ARRAY_SIZE(a83t_resets),
Jagan Teki24740332018-08-02 23:33:55 +0530[diff] [blame]105};