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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +02002/*
3 * Copyright (C) 2004-2006 Atmel Corporation
4 *
Andreas Bießmannfb378682010-09-03 10:28:05 +02005 * Modified to support C structur SoC access by
6 * Andreas Bießmann <biessmann@corscience.de>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +02007 */
8#include <common.h>
Wenyou Yang7c56e102017-04-14 15:01:28 +08009#include <clk.h>
Simon Glass7cbab242014-10-29 13:09:00 -060010#include <dm.h>
11#include <errno.h>
Simon Glass9bc15642020-02-03 07:36:16 -070012#include <malloc.h>
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +010013#include <watchdog.h>
Marek Vasutff093ed2012-09-13 16:50:30 +020014#include <serial.h>
Wenyou Yang6b611e62016-10-17 09:49:55 +080015#include <debug_uart.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Marek Vasutff093ed2012-09-13 16:50:30 +020017#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020019
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020020#include <asm/io.h>
Simon Glass7cbab242014-10-29 13:09:00 -060021#ifdef CONFIG_DM_SERIAL
22#include <asm/arch/atmel_serial.h>
23#endif
Haavard Skinnemoen0a2743f2006-11-19 18:06:53 +010024#include <asm/arch/clk.h>
Reinhard Meyer7f619cb2010-11-03 16:32:56 +010025#include <asm/arch/hardware.h>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020026
27#include "atmel_usart.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
Wenyou Yangb045a602017-04-14 15:01:27 +080031#ifndef CONFIG_DM_SERIAL
Simon Glass1e5c2a82014-10-29 13:08:59 -060032static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
33 int baudrate)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020034{
35 unsigned long divisor;
36 unsigned long usart_hz;
37
38 /*
39 * Master Clock
40 * Baud Rate = --------------
41 * 16 * CD
42 */
Simon Glass1e5c2a82014-10-29 13:08:59 -060043 usart_hz = get_usart_clk_rate(id);
44 divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
Andreas Bießmannfb378682010-09-03 10:28:05 +020045 writel(USART3_BF(CD, divisor), &usart->brgr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020046}
47
Simon Glass1e5c2a82014-10-29 13:08:59 -060048static void atmel_serial_init_internal(atmel_usart3_t *usart)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020049{
Xu, Hong9db57992011-08-02 01:05:04 +000050 /*
51 * Just in case: drain transmitter register
52 * 1000us is enough for baudrate >= 9600
53 */
54 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
55 __udelay(1000);
56
Andreas Bießmannfb378682010-09-03 10:28:05 +020057 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
Simon Glass1e5c2a82014-10-29 13:08:59 -060058}
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020059
Simon Glass1e5c2a82014-10-29 13:08:59 -060060static void atmel_serial_activate(atmel_usart3_t *usart)
61{
Andreas Bießmannfb378682010-09-03 10:28:05 +020062 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
Haavard Skinnemoen0a2743f2006-11-19 18:06:53 +010063 | USART3_BF(USCLKS, USART3_USCLKS_MCK)
64 | USART3_BF(CHRL, USART3_CHRL_8)
65 | USART3_BF(PAR, USART3_PAR_NONE)
Andreas Bießmannfb378682010-09-03 10:28:05 +020066 | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
67 &usart->mr);
Xu, Hong9db57992011-08-02 01:05:04 +000068 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
69 /* 100us is enough for the new settings to be settled */
70 __udelay(100);
Simon Glass1e5c2a82014-10-29 13:08:59 -060071}
72
73static void atmel_serial_setbrg(void)
74{
75 atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
76 CONFIG_USART_ID, gd->baudrate);
77}
78
79static int atmel_serial_init(void)
80{
81 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
82
83 atmel_serial_init_internal(usart);
84 serial_setbrg();
85 atmel_serial_activate(usart);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020086
87 return 0;
88}
89
Marek Vasutff093ed2012-09-13 16:50:30 +020090static void atmel_serial_putc(char c)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020091{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +010092 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +020093
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020094 if (c == '\n')
95 serial_putc('\r');
96
Andreas Bießmannfb378682010-09-03 10:28:05 +020097 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
98 writel(c, &usart->thr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020099}
100
Marek Vasutff093ed2012-09-13 16:50:30 +0200101static int atmel_serial_getc(void)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200102{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +0100103 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +0200104
105 while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
Stefan Roese80877fa2022-09-02 14:10:46 +0200106 schedule();
Andreas Bießmannfb378682010-09-03 10:28:05 +0200107 return readl(&usart->rhr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200108}
109
Marek Vasutff093ed2012-09-13 16:50:30 +0200110static int atmel_serial_tstc(void)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200111{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +0100112 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +0200113 return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200114}
Marek Vasutff093ed2012-09-13 16:50:30 +0200115
Marek Vasutff093ed2012-09-13 16:50:30 +0200116static struct serial_device atmel_serial_drv = {
117 .name = "atmel_serial",
118 .start = atmel_serial_init,
119 .stop = NULL,
120 .setbrg = atmel_serial_setbrg,
121 .putc = atmel_serial_putc,
Marek Vasutd9c64492012-10-06 14:07:02 +0000122 .puts = default_serial_puts,
Marek Vasutff093ed2012-09-13 16:50:30 +0200123 .getc = atmel_serial_getc,
124 .tstc = atmel_serial_tstc,
125};
126
127void atmel_serial_initialize(void)
128{
129 serial_register(&atmel_serial_drv);
130}
131
132__weak struct serial_device *default_serial_console(void)
133{
134 return &atmel_serial_drv;
135}
Simon Glass7cbab242014-10-29 13:09:00 -0600136#endif
137
138#ifdef CONFIG_DM_SERIAL
Wenyou Yang7c56e102017-04-14 15:01:28 +0800139enum serial_clk_type {
140 CLK_TYPE_NORMAL = 0,
141 CLK_TYPE_DBGU,
142};
Simon Glass7cbab242014-10-29 13:09:00 -0600143
144struct atmel_serial_priv {
145 atmel_usart3_t *usart;
Wenyou Yang7c56e102017-04-14 15:01:28 +0800146 ulong usart_clk_rate;
Simon Glass7cbab242014-10-29 13:09:00 -0600147};
148
Wenyou Yangb045a602017-04-14 15:01:27 +0800149static void _atmel_serial_set_brg(atmel_usart3_t *usart,
150 ulong usart_clk_rate, int baudrate)
151{
152 unsigned long divisor;
153
154 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
155 writel(USART3_BF(CD, divisor), &usart->brgr);
156}
157
158void _atmel_serial_init(atmel_usart3_t *usart,
159 ulong usart_clk_rate, int baudrate)
160{
161 writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
162
163 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
164 USART3_BF(USCLKS, USART3_USCLKS_MCK) |
165 USART3_BF(CHRL, USART3_CHRL_8) |
166 USART3_BF(PAR, USART3_PAR_NONE) |
167 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
168
169 _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
170
171 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
172 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
173}
174
Simon Glass7cbab242014-10-29 13:09:00 -0600175int atmel_serial_setbrg(struct udevice *dev, int baudrate)
176{
177 struct atmel_serial_priv *priv = dev_get_priv(dev);
178
Wenyou Yang7c56e102017-04-14 15:01:28 +0800179 _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
Simon Glass7cbab242014-10-29 13:09:00 -0600180
181 return 0;
182}
183
184static int atmel_serial_getc(struct udevice *dev)
185{
186 struct atmel_serial_priv *priv = dev_get_priv(dev);
187
188 if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
189 return -EAGAIN;
190
191 return readl(&priv->usart->rhr);
192}
193
194static int atmel_serial_putc(struct udevice *dev, const char ch)
195{
196 struct atmel_serial_priv *priv = dev_get_priv(dev);
197
198 if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
199 return -EAGAIN;
200
201 writel(ch, &priv->usart->thr);
202
203 return 0;
204}
205
206static int atmel_serial_pending(struct udevice *dev, bool input)
207{
208 struct atmel_serial_priv *priv = dev_get_priv(dev);
209 uint32_t csr = readl(&priv->usart->csr);
210
211 if (input)
212 return csr & USART3_BIT(RXRDY) ? 1 : 0;
213 else
214 return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
215}
216
217static const struct dm_serial_ops atmel_serial_ops = {
218 .putc = atmel_serial_putc,
219 .pending = atmel_serial_pending,
220 .getc = atmel_serial_getc,
221 .setbrg = atmel_serial_setbrg,
222};
223
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200224#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
Wenyou Yang7c56e102017-04-14 15:01:28 +0800225static int atmel_serial_enable_clk(struct udevice *dev)
226{
227 struct atmel_serial_priv *priv = dev_get_priv(dev);
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200228
229 /* Use fixed clock value in SPL */
230 priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
231
232 return 0;
233}
234#else
235static int atmel_serial_enable_clk(struct udevice *dev)
236{
237 struct atmel_serial_priv *priv = dev_get_priv(dev);
Wenyou Yang7c56e102017-04-14 15:01:28 +0800238 struct clk clk;
239 ulong clk_rate;
240 int ret;
241
242 ret = clk_get_by_index(dev, 0, &clk);
243 if (ret)
244 return -EINVAL;
245
246 if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
247 ret = clk_enable(&clk);
248 if (ret)
249 return ret;
250 }
251
252 clk_rate = clk_get_rate(&clk);
253 if (!clk_rate)
254 return -EINVAL;
255
256 priv->usart_clk_rate = clk_rate;
257
258 clk_free(&clk);
259
260 return 0;
261}
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200262#endif
Wenyou Yang7c56e102017-04-14 15:01:28 +0800263
Simon Glass7cbab242014-10-29 13:09:00 -0600264static int atmel_serial_probe(struct udevice *dev)
265{
Simon Glass95588622020-12-22 19:30:28 -0700266 struct atmel_serial_plat *plat = dev_get_plat(dev);
Simon Glass7cbab242014-10-29 13:09:00 -0600267 struct atmel_serial_priv *priv = dev_get_priv(dev);
Wenyou Yang7c56e102017-04-14 15:01:28 +0800268 int ret;
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800269#if CONFIG_IS_ENABLED(OF_CONTROL)
270 fdt_addr_t addr_base;
Simon Glass7cbab242014-10-29 13:09:00 -0600271
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900272 addr_base = dev_read_addr(dev);
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800273 if (addr_base == FDT_ADDR_T_NONE)
274 return -ENODEV;
275
276 plat->base_addr = (uint32_t)addr_base;
277#endif
Simon Glass7cbab242014-10-29 13:09:00 -0600278 priv->usart = (atmel_usart3_t *)plat->base_addr;
Wenyou Yangb045a602017-04-14 15:01:27 +0800279
Wenyou Yang7c56e102017-04-14 15:01:28 +0800280 ret = atmel_serial_enable_clk(dev);
281 if (ret)
282 return ret;
283
284 _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
Simon Glass7cbab242014-10-29 13:09:00 -0600285
286 return 0;
287}
288
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800289#if CONFIG_IS_ENABLED(OF_CONTROL)
290static const struct udevice_id atmel_serial_ids[] = {
Wenyou Yang7c56e102017-04-14 15:01:28 +0800291 {
292 .compatible = "atmel,at91sam9260-dbgu",
293 .data = CLK_TYPE_DBGU,
294 },
295 {
296 .compatible = "atmel,at91sam9260-usart",
297 .data = CLK_TYPE_NORMAL,
298 },
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800299 { }
300};
301#endif
302
Simon Glass7cbab242014-10-29 13:09:00 -0600303U_BOOT_DRIVER(serial_atmel) = {
304 .name = "serial_atmel",
305 .id = UCLASS_SERIAL,
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800306#if CONFIG_IS_ENABLED(OF_CONTROL)
307 .of_match = atmel_serial_ids,
Simon Glassb75b15b2020-12-03 16:55:23 -0700308 .plat_auto = sizeof(struct atmel_serial_plat),
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800309#endif
Simon Glass7cbab242014-10-29 13:09:00 -0600310 .probe = atmel_serial_probe,
311 .ops = &atmel_serial_ops,
Bin Mengbdb33d82018-10-24 06:36:36 -0700312#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass7cbab242014-10-29 13:09:00 -0600313 .flags = DM_FLAG_PRE_RELOC,
Bin Mengbdb33d82018-10-24 06:36:36 -0700314#endif
Simon Glass8a2b47f2020-12-03 16:55:17 -0700315 .priv_auto = sizeof(struct atmel_serial_priv),
Simon Glass7cbab242014-10-29 13:09:00 -0600316};
317#endif
Wenyou Yang6b611e62016-10-17 09:49:55 +0800318
319#ifdef CONFIG_DEBUG_UART_ATMEL
320static inline void _debug_uart_init(void)
321{
Pali Rohár8864b352022-05-27 22:15:24 +0200322 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
Wenyou Yang6b611e62016-10-17 09:49:55 +0800323
Wenyou Yangb045a602017-04-14 15:01:27 +0800324 _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
Wenyou Yang6b611e62016-10-17 09:49:55 +0800325}
326
327static inline void _debug_uart_putc(int ch)
328{
Pali Rohár8864b352022-05-27 22:15:24 +0200329 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
Wenyou Yang6b611e62016-10-17 09:49:55 +0800330
331 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
332 ;
333
334 writel(ch, &usart->thr);
335}
336
337DEBUG_UART_FUNCS
338#endif