blob: 78d317d8647012dea90d3efd7a358a63d78e42fd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tim Harvey552c3582014-03-06 07:46:30 -08002/*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
Tim Harvey552c3582014-03-06 07:46:30 -08006 */
7
Tim Harvey41377852022-04-13 09:29:16 -07008#include <command.h>
Tim Harvey552c3582014-03-06 07:46:30 -08009#include <common.h>
Tim Harvey41377852022-04-13 09:29:16 -070010#include <fdt_support.h>
11#include <gsc.h>
12#include <hwconfig.h>
13#include <i2c.h>
14#include <miiphy.h>
15#include <mtd_node.h>
Tim Harvey552c3582014-03-06 07:46:30 -080016#include <asm/arch/clock.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070017#include <asm/arch/crm_regs.h>
Tim Harvey552c3582014-03-06 07:46:30 -080018#include <asm/arch/mx6-pins.h>
Tim Harveyfb64cc72014-04-25 15:39:07 -070019#include <asm/arch/mxc_hdmi.h>
Tim Harvey552c3582014-03-06 07:46:30 -080020#include <asm/arch/sys_proto.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020021#include <asm/mach-imx/boot_mode.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020022#include <asm/mach-imx/video.h>
Tim Harvey41377852022-04-13 09:29:16 -070023#include <jffs2/load_kernel.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070024#include <linux/ctype.h>
Simon Glassdbd79542020-05-10 11:40:11 -060025#include <linux/delay.h>
Tim Harvey552c3582014-03-06 07:46:30 -080026
Tim Harvey0cee2242015-05-08 18:28:35 -070027#include "common.h"
Tim Harvey552c3582014-03-06 07:46:30 -080028
29DECLARE_GLOBAL_DATA_PTR;
30
Tim Harvey552c3582014-03-06 07:46:30 -080031/* configure eth0 PHY board-specific LED behavior */
32int board_phy_config(struct phy_device *phydev)
33{
34 unsigned short val;
Tim Harveyb9d23522022-04-29 13:51:02 -070035 ofnode node;
Tim Harvey552c3582014-03-06 07:46:30 -080036
Tim Harveyb9d23522022-04-29 13:51:02 -070037 switch (phydev->phy_id) {
38 case 0x1410dd1:
Tim Harveyb25b7582021-06-11 12:46:26 -070039 puts("MV88E1510");
Tim Harvey552c3582014-03-06 07:46:30 -080040 /*
41 * Page 3, Register 16: LED[2:0] Function Control Register
42 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
43 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
44 */
45 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
46 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
47 val &= 0xff00;
48 val |= 0x0017;
49 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
Tim Harveyb9d23522022-04-29 13:51:02 -070051 break;
52 case 0x2000a231:
Tim Harveyb25b7582021-06-11 12:46:26 -070053 puts("TIDP83867 ");
Tim Harvey1662ad32021-06-11 12:46:25 -070054 /* LED configuration */
55 val = 0;
56 val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
57 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
58 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
59
Tim Harvey4533c902017-03-17 07:32:21 -070060 /* configure register 0x170 for ref CLKOUT */
61 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
62 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
63 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
64 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
65 val &= ~0x1f00;
66 val |= 0x0b00; /* chD tx clock*/
67 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
Tim Harveyb9d23522022-04-29 13:51:02 -070068 break;
69 case 0xd565a401:
70 puts("GPY111 ");
71 node = phy_get_ofnode(phydev);
72 if (ofnode_valid(node)) {
73 u32 rx_delay, tx_delay;
74
75 rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
76 tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
77 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
78 val &= ~((0x7 << 12) | (0x7 << 8));
79 val |= (rx_delay / 500) << 12;
80 val |= (tx_delay / 500) << 8;
81 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
82 }
83 break;
Tim Harvey4533c902017-03-17 07:32:21 -070084 }
85
Tim Harvey552c3582014-03-06 07:46:30 -080086 if (phydev->drv->config)
87 phydev->drv->config(phydev);
88
89 return 0;
90}
Tim Harvey63537792017-03-17 07:30:38 -070091
92#ifdef CONFIG_MV88E61XX_SWITCH
93int mv88e61xx_hw_reset(struct phy_device *phydev)
94{
95 struct mii_dev *bus = phydev->bus;
96
97 /* GPIO[0] output, CLK125 */
98 debug("enabling RGMII_REFCLK\n");
99 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
100 0x1a /*MV_SCRATCH_MISC*/,
101 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
102 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
103 0x1a /*MV_SCRATCH_MISC*/,
104 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
105
106 /* RGMII delay - Physical Control register bit[15:14] */
107 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
108 /* forced 1000mbps full-duplex link */
109 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
110 phydev->autoneg = AUTONEG_DISABLE;
111 phydev->speed = SPEED_1000;
112 phydev->duplex = DUPLEX_FULL;
113
Tim Harvey8c9d3932019-02-04 13:10:47 -0800114 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
115 bus->write(bus, 0x10, 0, 0x16, 0x8088);
116 bus->write(bus, 0x11, 0, 0x16, 0x8088);
117 bus->write(bus, 0x12, 0, 0x16, 0x8088);
118 bus->write(bus, 0x13, 0, 0x16, 0x8088);
Tim Harvey63537792017-03-17 07:30:38 -0700119
120 return 0;
121}
122#endif // CONFIG_MV88E61XX_SWITCH
Tim Harvey552c3582014-03-06 07:46:30 -0800123
Tim Harveyfb64cc72014-04-25 15:39:07 -0700124#if defined(CONFIG_VIDEO_IPUV3)
Tim Harveyfb64cc72014-04-25 15:39:07 -0700125static void enable_hdmi(struct display_info_t const *dev)
126{
127 imx_enable_hdmi_phy();
128}
129
Tim Harveyceb79f52021-09-29 15:04:21 -0700130static int detect_lvds(struct display_info_t const *dev)
Tim Harveyfb64cc72014-04-25 15:39:07 -0700131{
Tim Harveyceb79f52021-09-29 15:04:21 -0700132 /* only the following boards support LVDS connectors */
133 switch (board_type) {
134 case GW52xx:
135 case GW53xx:
136 case GW54xx:
137 case GW560x:
138 case GW5905:
139 case GW5909:
140 break;
141 default:
142 return 0;
143 }
144
Tim Harvey895aace2022-03-07 16:24:00 -0800145 return (i2c_get_dev(dev->bus, dev->addr) ? 1 : 0);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700146}
147
148static void enable_lvds(struct display_info_t const *dev)
149{
Tim Harveyceb79f52021-09-29 15:04:21 -0700150 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
Tim Harveyfb64cc72014-04-25 15:39:07 -0700151
152 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
153 u32 reg = readl(&iomux->gpr[2]);
154 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
155 writel(reg, &iomux->gpr[2]);
156
Tim Harveyceb79f52021-09-29 15:04:21 -0700157 /* Configure GPIO */
158 switch (board_type) {
159 case GW52xx:
160 case GW53xx:
161 case GW54xx:
162 if (!strncmp(dev->mode.name, "Hannstar", 8)) {
163 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
164 gpio_request(IMX_GPIO_NR(1, 10), "cabc");
165 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
166 } else if (!strncmp(dev->mode.name, "DLC", 3)) {
167 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
168 gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
169 gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
170 }
171 break;
172 default:
173 break;
174 }
175
176 /* Configure backlight */
Tim Harveyf1f41db2015-05-08 18:28:28 -0700177 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
Tim Harvey26993362014-08-07 22:35:49 -0700178 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700179 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
180}
181
182struct display_info_t const displays[] = {{
183 /* HDMI Output */
184 .bus = -1,
185 .addr = 0,
186 .pixfmt = IPU_PIX_FMT_RGB24,
187 .detect = detect_hdmi,
188 .enable = enable_hdmi,
189 .mode = {
190 .name = "HDMI",
191 .refresh = 60,
192 .xres = 1024,
193 .yres = 768,
194 .pixclock = 15385,
195 .left_margin = 220,
196 .right_margin = 40,
197 .upper_margin = 21,
198 .lower_margin = 7,
199 .hsync_len = 60,
200 .vsync_len = 10,
201 .sync = FB_SYNC_EXT,
202 .vmode = FB_VMODE_NONINTERLACED
203} }, {
204 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
205 .bus = 2,
206 .addr = 0x4,
207 .pixfmt = IPU_PIX_FMT_LVDS666,
Tim Harveyceb79f52021-09-29 15:04:21 -0700208 .detect = detect_lvds,
Tim Harveyfb64cc72014-04-25 15:39:07 -0700209 .enable = enable_lvds,
210 .mode = {
211 .name = "Hannstar-XGA",
212 .refresh = 60,
213 .xres = 1024,
214 .yres = 768,
215 .pixclock = 15385,
216 .left_margin = 220,
217 .right_margin = 40,
218 .upper_margin = 21,
219 .lower_margin = 7,
220 .hsync_len = 60,
221 .vsync_len = 10,
222 .sync = FB_SYNC_EXT,
223 .vmode = FB_VMODE_NONINTERLACED
Tim Harveya20bd632015-04-08 12:54:57 -0700224} }, {
225 /* DLC700JMG-T-4 */
Tim Harveybe786e72019-02-04 13:10:53 -0800226 .bus = 2,
227 .addr = 0x38,
Tim Harveyceb79f52021-09-29 15:04:21 -0700228 .detect = detect_lvds,
Tim Harveya20bd632015-04-08 12:54:57 -0700229 .enable = enable_lvds,
230 .pixfmt = IPU_PIX_FMT_LVDS666,
231 .mode = {
232 .name = "DLC700JMGT4",
233 .refresh = 60,
234 .xres = 1024, /* 1024x600active pixels */
235 .yres = 600,
236 .pixclock = 15385, /* 64MHz */
237 .left_margin = 220,
238 .right_margin = 40,
239 .upper_margin = 21,
240 .lower_margin = 7,
241 .hsync_len = 60,
242 .vsync_len = 10,
243 .sync = FB_SYNC_EXT,
244 .vmode = FB_VMODE_NONINTERLACED
245} }, {
Tim Harvey87a86452021-06-11 12:46:27 -0700246 /* DLC0700XDP21LF-C-1 */
Tim Harveyceb79f52021-09-29 15:04:21 -0700247 .bus = 2,
248 .addr = 0x38,
249 .detect = detect_lvds,
Tim Harvey87a86452021-06-11 12:46:27 -0700250 .enable = enable_lvds,
251 .pixfmt = IPU_PIX_FMT_LVDS666,
252 .mode = {
253 .name = "DLC0700XDP21LF",
254 .refresh = 60,
255 .xres = 1024, /* 1024x600active pixels */
256 .yres = 600,
257 .pixclock = 15385, /* 64MHz */
258 .left_margin = 220,
259 .right_margin = 40,
260 .upper_margin = 21,
261 .lower_margin = 7,
262 .hsync_len = 60,
263 .vsync_len = 10,
264 .sync = FB_SYNC_EXT,
265 .vmode = FB_VMODE_NONINTERLACED
266} }, {
Tim Harveya20bd632015-04-08 12:54:57 -0700267 /* DLC800FIG-T-3 */
Tim Harveybe786e72019-02-04 13:10:53 -0800268 .bus = 2,
269 .addr = 0x14,
Tim Harveyceb79f52021-09-29 15:04:21 -0700270 .detect = detect_lvds,
Tim Harveya20bd632015-04-08 12:54:57 -0700271 .enable = enable_lvds,
272 .pixfmt = IPU_PIX_FMT_LVDS666,
273 .mode = {
274 .name = "DLC800FIGT3",
275 .refresh = 60,
276 .xres = 1024, /* 1024x768 active pixels */
277 .yres = 768,
278 .pixclock = 15385, /* 64MHz */
279 .left_margin = 220,
280 .right_margin = 40,
281 .upper_margin = 21,
282 .lower_margin = 7,
283 .hsync_len = 60,
284 .vsync_len = 10,
285 .sync = FB_SYNC_EXT,
286 .vmode = FB_VMODE_NONINTERLACED
Tim Harveyc34e59e2019-02-04 13:10:51 -0800287} }, {
288 .bus = 2,
289 .addr = 0x5d,
Tim Harveyceb79f52021-09-29 15:04:21 -0700290 .detect = detect_lvds,
Tim Harveyc34e59e2019-02-04 13:10:51 -0800291 .enable = enable_lvds,
292 .pixfmt = IPU_PIX_FMT_LVDS666,
293 .mode = {
294 .name = "Z101WX01",
295 .refresh = 60,
296 .xres = 1280,
297 .yres = 800,
298 .pixclock = 15385, /* 64MHz */
299 .left_margin = 220,
300 .right_margin = 40,
301 .upper_margin = 21,
302 .lower_margin = 7,
303 .hsync_len = 60,
304 .vsync_len = 10,
305 .sync = FB_SYNC_EXT,
306 .vmode = FB_VMODE_NONINTERLACED
307 }
308},
309};
Tim Harveyfb64cc72014-04-25 15:39:07 -0700310size_t display_count = ARRAY_SIZE(displays);
311
312static void setup_display(void)
313{
314 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
315 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
316 int reg;
317
318 enable_ipu_clock();
319 imx_setup_hdmi();
320 /* Turn on LDB0,IPU,IPU DI0 clocks */
321 reg = __raw_readl(&mxc_ccm->CCGR3);
322 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
323 writel(reg, &mxc_ccm->CCGR3);
324
325 /* set LDB0, LDB1 clk select to 011/011 */
326 reg = readl(&mxc_ccm->cs2cdr);
327 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
328 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
329 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
330 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
331 writel(reg, &mxc_ccm->cs2cdr);
332
333 reg = readl(&mxc_ccm->cscmr2);
334 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
335 writel(reg, &mxc_ccm->cscmr2);
336
337 reg = readl(&mxc_ccm->chsccdr);
338 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
339 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
340 writel(reg, &mxc_ccm->chsccdr);
341
342 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
343 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
344 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
345 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
346 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
347 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
348 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
349 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
350 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
351 writel(reg, &iomux->gpr[2]);
352
353 reg = readl(&iomux->gpr[3]);
354 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
355 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
356 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
357 writel(reg, &iomux->gpr[3]);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700358}
359#endif /* CONFIG_VIDEO_IPUV3 */
360
Tim Harvey33791d52014-08-07 22:49:57 -0700361/*
362 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
363 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
364 * properly and assert reset for 100ms.
365 */
Tim Harveybfb240a2016-06-17 06:10:41 -0700366#define MAX_PCI_DEVS 32
367struct pci_dev {
368 pci_dev_t devfn;
Tim Harvey6ce10d52021-05-03 11:21:27 -0700369 struct udevice *dev;
Tim Harveybfb240a2016-06-17 06:10:41 -0700370 unsigned short vendor;
371 unsigned short device;
372 unsigned short class;
373 unsigned short busno; /* subbordinate busno */
374 struct pci_dev *ppar;
375};
376struct pci_dev pci_devs[MAX_PCI_DEVS];
377int pci_devno;
378int pci_bridgeno;
379
Tim Harvey6ce10d52021-05-03 11:21:27 -0700380void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
Tim Harvey33791d52014-08-07 22:49:57 -0700381{
Tim Harvey6ce10d52021-05-03 11:21:27 -0700382 struct pci_child_plat *pdata = dev_get_parent_plat(udev);
Tim Harveybfb240a2016-06-17 06:10:41 -0700383 struct pci_dev *pdev = &pci_devs[pci_devno++];
Tim Harvey6ce10d52021-05-03 11:21:27 -0700384 unsigned short vendor = pdata->vendor;
385 unsigned short device = pdata->device;
386 unsigned int class = pdata->class;
387 pci_dev_t dev = dm_pci_get_bdf(udev);
388 int i;
Tim Harvey33791d52014-08-07 22:49:57 -0700389
390 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
391 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
Tim Harveybfb240a2016-06-17 06:10:41 -0700392
393 /* store array of devs for later use in device-tree fixup */
Tim Harvey6ce10d52021-05-03 11:21:27 -0700394 pdev->dev = udev;
Tim Harveybfb240a2016-06-17 06:10:41 -0700395 pdev->devfn = dev;
396 pdev->vendor = vendor;
397 pdev->device = device;
398 pdev->class = class;
399 pdev->ppar = NULL;
400 if (class == PCI_CLASS_BRIDGE_PCI)
401 pdev->busno = ++pci_bridgeno;
402 else
403 pdev->busno = 0;
404
405 /* fixup RC - it should be 00:00.0 not 00:01.0 */
406 if (PCI_BUS(dev) == 0)
407 pdev->devfn = 0;
408
409 /* find dev's parent */
410 for (i = 0; i < pci_devno; i++) {
411 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
412 pdev->ppar = &pci_devs[i];
413 break;
414 }
415 }
416
417 /* assert downstream PERST# */
Tim Harvey33791d52014-08-07 22:49:57 -0700418 if (vendor == PCI_VENDOR_ID_PLX &&
419 (device & 0xfff0) == 0x8600 &&
420 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
Tim Harvey6ce10d52021-05-03 11:21:27 -0700421 ulong val;
Tim Harvey33791d52014-08-07 22:49:57 -0700422 debug("configuring PLX 860X downstream PERST#\n");
Tim Harvey6ce10d52021-05-03 11:21:27 -0700423 pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
424 val |= 0xaaa8; /* GPIO1-7 outputs */
425 pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
Tim Harvey33791d52014-08-07 22:49:57 -0700426
Tim Harvey6ce10d52021-05-03 11:21:27 -0700427 pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
428 val |= 0xfe; /* GPIO1-7 output high */
429 pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
Tim Harvey33791d52014-08-07 22:49:57 -0700430
431 mdelay(100);
432 }
433}
Tim Harvey552c3582014-03-06 07:46:30 -0800434
435#ifdef CONFIG_SERIAL_TAG
436/*
437 * called when setting up ATAGS before booting kernel
438 * populate serialnum from the following (in order of priority):
439 * serial# env var
440 * eeprom
441 */
442void get_board_serial(struct tag_serialnr *serialnr)
443{
Simon Glass64b723f2017-08-03 12:22:12 -0600444 char *serial = env_get("serial#");
Tim Harvey552c3582014-03-06 07:46:30 -0800445
446 if (serial) {
447 serialnr->high = 0;
Simon Glassff9b9032021-07-24 09:03:30 -0600448 serialnr->low = dectoul(serial, NULL);
Tim Harvey552c3582014-03-06 07:46:30 -0800449 } else if (ventana_info.model[0]) {
450 serialnr->high = 0;
451 serialnr->low = ventana_info.serial;
452 } else {
453 serialnr->high = 0;
454 serialnr->low = 0;
455 }
456}
457#endif
458
459/*
460 * Board Support
461 */
462
463int board_early_init_f(void)
464{
Tim Harveyfb64cc72014-04-25 15:39:07 -0700465#if defined(CONFIG_VIDEO_IPUV3)
466 setup_display();
467#endif
Tim Harvey552c3582014-03-06 07:46:30 -0800468 return 0;
469}
470
471int dram_init(void)
472{
Tim Harveybfa2dae2014-06-02 16:13:27 -0700473 gd->ram_size = imx_ddr_size();
Tim Harvey552c3582014-03-06 07:46:30 -0800474 return 0;
475}
476
477int board_init(void)
478{
Fabio Estevamceb74c42014-07-09 17:59:54 -0300479 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
Tim Harvey552c3582014-03-06 07:46:30 -0800480
481 clrsetbits_le32(&iomuxc_regs->gpr[1],
482 IOMUXC_GPR1_OTG_ID_MASK,
483 IOMUXC_GPR1_OTG_ID_GPIO1);
484
485 /* address of linux boot parameters */
486 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
487
Tim Harveyba9f2342019-02-04 13:10:52 -0800488 /* read Gateworks EEPROM into global struct (used later) */
Tim Harvey41377852022-04-13 09:29:16 -0700489 board_type = read_eeprom(&ventana_info);
Tim Harveyba9f2342019-02-04 13:10:52 -0800490
Tim Harvey41377852022-04-13 09:29:16 -0700491 setup_iomux_gpio(board_type);
492
493 /* show GSC details */
494 run_command("gsc", 0);
Tim Harvey552c3582014-03-06 07:46:30 -0800495
496 return 0;
497}
498
Tim Harvey948202c2021-03-01 14:33:32 -0800499int board_fit_config_name_match(const char *name)
500{
501 static char init;
502 const char *dtb;
503 char buf[32];
504 int i = 0;
505
506 do {
507 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
508 if (dtb && !strcmp(dtb, name)) {
509 if (!init++)
510 printf("DTB: %s\n", name);
511 return 0;
512 }
513 } while (dtb);
514
515 return -1;
516}
517
Tim Harvey552c3582014-03-06 07:46:30 -0800518#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
519/*
520 * called during late init (after relocation and after board_init())
521 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
522 * EEPROM read.
523 */
524int checkboard(void)
525{
526 struct ventana_board_info *info = &ventana_info;
Tim Harvey552c3582014-03-06 07:46:30 -0800527 const char *p;
528 int quiet; /* Quiet or minimal output mode */
529
530 quiet = 0;
Simon Glass64b723f2017-08-03 12:22:12 -0600531 p = env_get("quiet");
Tim Harvey552c3582014-03-06 07:46:30 -0800532 if (p)
533 quiet = simple_strtol(p, NULL, 10);
534 else
Simon Glass6a38e412017-08-03 12:22:09 -0600535 env_set("quiet", "0");
Tim Harvey552c3582014-03-06 07:46:30 -0800536
537 puts("\nGateworks Corporation Copyright 2014\n");
538 if (info->model[0]) {
539 printf("Model: %s\n", info->model);
540 printf("MFGDate: %02x-%02x-%02x%02x\n",
541 info->mfgdate[0], info->mfgdate[1],
542 info->mfgdate[2], info->mfgdate[3]);
543 printf("Serial:%d\n", info->serial);
544 } else {
545 puts("Invalid EEPROM - board will not function fully\n");
546 }
547 if (quiet)
548 return 0;
549
Tim Harvey552c3582014-03-06 07:46:30 -0800550 return 0;
551}
552#endif
553
554#ifdef CONFIG_CMD_BMODE
555/*
556 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
557 * see Table 8-11 and Table 5-9
558 * BOOT_CFG1[7] = 1 (boot from NAND)
559 * BOOT_CFG1[5] = 0 - raw NAND
560 * BOOT_CFG1[4] = 0 - default pad settings
561 * BOOT_CFG1[3:2] = 00 - devices = 1
562 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
563 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
564 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
565 * BOOT_CFG2[0] = 0 - Reset time 12ms
566 */
567static const struct boot_mode board_boot_modes[] = {
568 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
569 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
Tim Harvey659441b2017-03-17 07:31:02 -0700570 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
Tim Harveya2d24c92019-02-04 13:10:50 -0800571 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
Tim Harvey552c3582014-03-06 07:46:30 -0800572 { NULL, 0 },
573};
574#endif
575
Tim Harvey55c33cb2022-03-07 16:24:02 -0800576/* setup GPIO pinmux and default configuration per baseboard and env */
577void setup_board_gpio(int board, struct ventana_board_info *info)
578{
579 const char *s;
580 char arg[10];
581 size_t len;
582 int i;
583 int quiet = simple_strtol(env_get("quiet"), NULL, 10);
584
585 if (board >= GW_UNKNOWN)
586 return;
587
588 /* RS232_EN# */
589 if (gpio_cfg[board].rs232_en) {
590 gpio_direction_output(gpio_cfg[board].rs232_en,
591 (hwconfig("rs232")) ? 0 : 1);
592 }
593
594 /* MSATA Enable */
595 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
596 gpio_direction_output(GP_MSATA_SEL,
597 (hwconfig("msata")) ? 1 : 0);
598 }
599
600 /* USBOTG Select (PCISKT or FrontPanel) */
601 if (gpio_cfg[board].usb_sel) {
602 gpio_direction_output(gpio_cfg[board].usb_sel,
603 (hwconfig("usb_pcisel")) ? 1 : 0);
604 }
605
606 /*
607 * Configure DIO pinmux/padctl registers
608 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
609 */
610 for (i = 0; i < gpio_cfg[board].dio_num; i++) {
611 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
612 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
613 unsigned int cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
614
615 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
616 continue;
617 sprintf(arg, "dio%d", i);
618 if (!hwconfig(arg))
619 continue;
620 s = hwconfig_subarg(arg, "padctrl", &len);
621 if (s) {
622 ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
623 & 0x1ffff) | MUX_MODE_SION;
624 }
625 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
626 if (!quiet) {
627 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
628 (cfg->gpio_param / 32) + 1,
629 cfg->gpio_param % 32,
630 cfg->gpio_param);
631 }
632 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
633 ctrl);
634 gpio_requestf(cfg->gpio_param, "dio%d", i);
635 gpio_direction_input(cfg->gpio_param);
Heinrich Schuchardt151462b2022-10-12 18:59:27 +0200636 } else if (hwconfig_subarg_cmp(arg, "mode", "pwm")) {
Tim Harvey55c33cb2022-03-07 16:24:02 -0800637 if (!cfg->pwm_param) {
638 printf("DIO%d: Error: pwm config invalid\n",
639 i);
640 continue;
641 }
642 if (!quiet)
643 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
644 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
645 MUX_PAD_CTRL(ctrl));
646 }
647 }
648
649 if (!quiet) {
650 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
651 printf("MSATA: %s\n", (hwconfig("msata") ?
652 "enabled" : "disabled"));
653 }
654 if (gpio_cfg[board].rs232_en) {
655 printf("RS232: %s\n", (hwconfig("rs232")) ?
656 "enabled" : "disabled");
657 }
658 }
659}
Tim Harvey552c3582014-03-06 07:46:30 -0800660/* late init */
661int misc_init_r(void)
662{
663 struct ventana_board_info *info = &ventana_info;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700664 char buf[256];
665 int i;
Tim Harvey552c3582014-03-06 07:46:30 -0800666
667 /* set env vars based on EEPROM data */
668 if (ventana_info.model[0]) {
669 char str[16], fdt[36];
670 char *p;
671 const char *cputype = "";
Tim Harvey552c3582014-03-06 07:46:30 -0800672
673 /*
674 * FDT name will be prefixed with CPU type. Three versions
675 * will be created each increasingly generic and bootloader
676 * env scripts will try loading each from most specific to
677 * least.
678 */
Tim Harveybfa2dae2014-06-02 16:13:27 -0700679 if (is_cpu_type(MXC_CPU_MX6Q) ||
680 is_cpu_type(MXC_CPU_MX6D))
Tim Harvey552c3582014-03-06 07:46:30 -0800681 cputype = "imx6q";
Tim Harveybfa2dae2014-06-02 16:13:27 -0700682 else if (is_cpu_type(MXC_CPU_MX6DL) ||
683 is_cpu_type(MXC_CPU_MX6SOLO))
Tim Harvey552c3582014-03-06 07:46:30 -0800684 cputype = "imx6dl";
Simon Glass6a38e412017-08-03 12:22:09 -0600685 env_set("soctype", cputype);
Tim Harvey06d87432014-08-07 22:35:41 -0700686 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
Simon Glass6a38e412017-08-03 12:22:09 -0600687 env_set("flash_layout", "large");
Tim Harvey06d87432014-08-07 22:35:41 -0700688 else
Simon Glass6a38e412017-08-03 12:22:09 -0600689 env_set("flash_layout", "normal");
Tim Harvey552c3582014-03-06 07:46:30 -0800690 memset(str, 0, sizeof(str));
691 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
692 str[i] = tolower(info->model[i]);
Simon Glass6a38e412017-08-03 12:22:09 -0600693 env_set("model", str);
Simon Glass64b723f2017-08-03 12:22:12 -0600694 if (!env_get("fdt_file")) {
Tim Harvey552c3582014-03-06 07:46:30 -0800695 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600696 env_set("fdt_file", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800697 }
698 p = strchr(str, '-');
699 if (p) {
700 *p++ = 0;
701
Simon Glass6a38e412017-08-03 12:22:09 -0600702 env_set("model_base", str);
Tim Harveyf6db79a2015-05-26 11:04:56 -0700703 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600704 env_set("fdt_file1", fdt);
Tim Harvey892068c2016-05-24 11:03:58 -0700705 if (board_type != GW551x &&
706 board_type != GW552x &&
Tim Harvey659441b2017-03-17 07:31:02 -0700707 board_type != GW553x &&
708 board_type != GW560x)
Tim Harvey50581832014-08-20 23:35:14 -0700709 str[4] = 'x';
Tim Harvey552c3582014-03-06 07:46:30 -0800710 str[5] = 'x';
711 str[6] = 0;
Tim Harveyf6db79a2015-05-26 11:04:56 -0700712 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600713 env_set("fdt_file2", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800714 }
715
716 /* initialize env from EEPROM */
717 if (test_bit(EECONFIG_ETH0, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600718 !env_get("ethaddr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600719 eth_env_set_enetaddr("ethaddr", info->mac0);
Tim Harvey552c3582014-03-06 07:46:30 -0800720 }
721 if (test_bit(EECONFIG_ETH1, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600722 !env_get("eth1addr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600723 eth_env_set_enetaddr("eth1addr", info->mac1);
Tim Harvey552c3582014-03-06 07:46:30 -0800724 }
725
726 /* board serial-number */
727 sprintf(str, "%6d", info->serial);
Simon Glass6a38e412017-08-03 12:22:09 -0600728 env_set("serial#", str);
Tim Harvey27770822015-04-08 12:54:51 -0700729
730 /* memory MB */
731 sprintf(str, "%d", (int) (gd->ram_size >> 20));
Simon Glass6a38e412017-08-03 12:22:09 -0600732 env_set("mem_mb", str);
Tim Harvey552c3582014-03-06 07:46:30 -0800733 }
734
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700735 /* Set a non-initialized hwconfig based on board configuration */
Simon Glass64b723f2017-08-03 12:22:12 -0600736 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
Tim Harveyfd6f2392017-03-13 08:51:06 -0700737 buf[0] = 0;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700738 if (gpio_cfg[board_type].rs232_en)
739 strcat(buf, "rs232;");
740 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
741 char buf1[32];
742 sprintf(buf1, "dio%d:mode=gpio;", i);
743 if (strlen(buf) + strlen(buf1) < sizeof(buf))
744 strcat(buf, buf1);
745 }
Simon Glass6a38e412017-08-03 12:22:09 -0600746 env_set("hwconfig", buf);
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700747 }
Tim Harvey552c3582014-03-06 07:46:30 -0800748
Tim Harvey0cee2242015-05-08 18:28:35 -0700749 /* setup baseboard specific GPIO based on board and env */
750 setup_board_gpio(board_type, info);
Tim Harvey552c3582014-03-06 07:46:30 -0800751
752#ifdef CONFIG_CMD_BMODE
753 add_board_boot_modes(board_boot_modes);
754#endif
755
Tim Harvey40feabb2015-05-08 18:28:36 -0700756 /* disable boot watchdog */
757 gsc_boot_wd_disable();
Tim Harvey552c3582014-03-06 07:46:30 -0800758
759 return 0;
760}
761
Robert P. J. Day3c757002016-05-19 15:23:12 -0400762#ifdef CONFIG_OF_BOARD_SETUP
Tim Harvey552c3582014-03-06 07:46:30 -0800763
Tim Harveycf20e552015-04-08 12:55:01 -0700764static int ft_sethdmiinfmt(void *blob, char *mode)
765{
766 int off;
767
768 if (!mode)
769 return -EINVAL;
770
771 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
772 if (off < 0)
773 return off;
774
775 if (0 == strcasecmp(mode, "yuv422bt656")) {
776 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
777 0x00, 0x00, 0x00 };
778 mode = "422_ccir";
779 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
780 fdt_setprop_u32(blob, off, "vidout_trc", 1);
781 fdt_setprop_u32(blob, off, "vidout_blc", 1);
782 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
783 printf(" set HDMI input mode to %s\n", mode);
784 } else if (0 == strcasecmp(mode, "yuv422smp")) {
785 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
786 0x82, 0x81, 0x00 };
787 mode = "422_smp";
788 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
789 fdt_setprop_u32(blob, off, "vidout_trc", 0);
790 fdt_setprop_u32(blob, off, "vidout_blc", 0);
791 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
792 printf(" set HDMI input mode to %s\n", mode);
793 } else {
794 return -EINVAL;
795 }
796
797 return 0;
798}
799
Tim Harveybfb240a2016-06-17 06:10:41 -0700800#if defined(CONFIG_CMD_PCI)
801#define PCI_ID(x) ( \
802 (PCI_BUS(x->devfn)<<16)| \
803 (PCI_DEV(x->devfn)<<11)| \
804 (PCI_FUNC(x->devfn)<<8) \
805 )
Tim Harveybfb240a2016-06-17 06:10:41 -0700806int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
807{
808 uint32_t reg[5];
809 char node[32];
810 int np;
811
812 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
813 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
814
815 np = fdt_subnode_offset(blob, par, node);
816 if (np >= 0)
817 return np;
818 np = fdt_add_subnode(blob, par, node);
819 if (np < 0) {
820 printf(" %s failed: no space\n", __func__);
821 return np;
822 }
823
824 memset(reg, 0, sizeof(reg));
825 reg[0] = cpu_to_fdt32(PCI_ID(dev));
826 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
827
828 return np;
829}
830
831/* build a path of nested PCI devs for all bridges passed through */
832int fdt_add_pci_path(void *blob, struct pci_dev *dev)
833{
834 struct pci_dev *bridges[MAX_PCI_DEVS];
835 int k, np;
836
837 /* build list of parents */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800838 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700839 if (np < 0)
840 return np;
841
842 k = 0;
843 while (dev) {
844 bridges[k++] = dev;
845 dev = dev->ppar;
846 };
847
848 /* now add them the to DT in reverse order */
849 while (k--) {
850 np = fdt_add_pci_node(blob, np, bridges[k]);
851 if (np < 0)
852 break;
853 }
854
855 return np;
856}
857
858/*
859 * The GW16082 has a hardware errata errata such that it's
860 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
861 * of this normal PCI interrupt swizzling will not work so we will
862 * provide an irq-map via device-tree.
863 */
864int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
865{
866 int len;
867 int host;
868 uint32_t imap_new[8*4*4];
869 const uint32_t *imap;
870 uint32_t irq[4];
871 uint32_t reg[4];
872 int i;
873
874 /* build irq-map based on host controllers map */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800875 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700876 if (host < 0) {
877 printf(" %s failed: missing host\n", __func__);
878 return host;
879 }
880
881 /* use interrupt data from root complex's node */
882 imap = fdt_getprop(blob, host, "interrupt-map", &len);
883 if (!imap || len != 128) {
884 printf(" %s failed: invalid interrupt-map\n",
885 __func__);
886 return -FDT_ERR_NOTFOUND;
887 }
888
889 /* obtain irq's of host controller in pin order */
890 for (i = 0; i < 4; i++)
891 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
892
893 /*
894 * determine number of swizzles necessary:
895 * For each bridge we pass through we need to swizzle
896 * the number of the slot we are on.
897 */
898 struct pci_dev *d;
899 int b;
900 b = 0;
901 d = dev->ppar;
902 while(d && d->ppar) {
903 b += PCI_DEV(d->devfn);
904 d = d->ppar;
905 }
906
907 /* create new irq mappings for slots12-15
908 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
909 * J3 AD28 12 INTD INTA
910 * J4 AD29 13 INTC INTD
911 * J5 AD30 14 INTB INTC
912 * J2 AD31 15 INTA INTB
913 */
914 for (i = 0; i < 4; i++) {
915 /* addr matches bus:dev:func */
916 u32 addr = dev->busno << 16 | (12+i) << 11;
917
918 /* default cells from root complex */
919 memcpy(&imap_new[i*32], imap, 128);
920 /* first cell is PCI device address (BDF) */
921 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
922 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
923 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
924 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
925 /* third cell is pin */
926 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
927 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
928 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
929 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
930 /* sixth cell is relative interrupt */
931 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
932 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
933 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
934 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
935 }
936 fdt_setprop(blob, np, "interrupt-map", imap_new,
937 sizeof(imap_new));
938 reg[0] = cpu_to_fdt32(0xfff00);
939 reg[1] = 0;
940 reg[2] = 0;
941 reg[3] = cpu_to_fdt32(0x7);
942 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
943 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
944 fdt_setprop_string(blob, np, "device_type", "pci");
945 fdt_setprop_cell(blob, np, "#address-cells", 3);
946 fdt_setprop_cell(blob, np, "#size-cells", 2);
947 printf(" Added custom interrupt-map for GW16082\n");
948
949 return 0;
950}
951
Tim Harvey77b82a12016-06-17 06:10:42 -0700952/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
953int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
954{
955 char *tmp, *end;
956 char mac[16];
957 unsigned char mac_addr[6];
958 int j;
959
960 sprintf(mac, "eth1addr");
Simon Glass64b723f2017-08-03 12:22:12 -0600961 tmp = env_get(mac);
Tim Harvey77b82a12016-06-17 06:10:42 -0700962 if (tmp) {
963 for (j = 0; j < 6; j++) {
964 mac_addr[j] = tmp ?
Simon Glass3ff49ec2021-07-24 09:03:29 -0600965 hextoul(tmp, &end) : 0;
Tim Harvey77b82a12016-06-17 06:10:42 -0700966 if (tmp)
967 tmp = (*end) ? end+1 : end;
968 }
969 fdt_setprop(blob, np, "local-mac-address", mac_addr,
970 sizeof(mac_addr));
971 printf(" Added mac addr for eth1\n");
972 return 0;
973 }
974
975 return -1;
976}
977
Tim Harveybfb240a2016-06-17 06:10:41 -0700978/*
979 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
980 * we will walk the PCI bus and add bridge nodes up to the device receiving
981 * the fixup.
982 */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900983void ft_board_pci_fixup(void *blob, struct bd_info *bd)
Tim Harveybfb240a2016-06-17 06:10:41 -0700984{
985 int i, np;
986 struct pci_dev *dev;
987
988 for (i = 0; i < pci_devno; i++) {
989 dev = &pci_devs[i];
990
991 /*
992 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
993 * an EEPROM at i2c1-0x50.
994 */
995 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
996 (dev->device == 0x8240) &&
Tim Harvey895aace2022-03-07 16:24:00 -0800997 i2c_get_dev(1, 0x50))
Tim Harveybfb240a2016-06-17 06:10:41 -0700998 {
999 np = fdt_add_pci_path(blob, dev);
1000 if (np > 0)
1001 fdt_fixup_gw16082(blob, np, dev);
1002 }
Tim Harvey77b82a12016-06-17 06:10:42 -07001003
1004 /* ethernet1 mac address */
1005 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1006 (dev->device == 0x4380))
1007 {
1008 np = fdt_add_pci_path(blob, dev);
1009 if (np > 0)
1010 fdt_fixup_sky2(blob, np, dev);
1011 }
Tim Harveybfb240a2016-06-17 06:10:41 -07001012 }
1013}
1014#endif /* if defined(CONFIG_CMD_PCI) */
Tim Harvey147b5762016-05-24 11:03:59 -07001015
Tim Harvey42874232022-03-07 16:24:03 -08001016#define WDOG1_ADDR 0x20bc000
1017#define WDOG2_ADDR 0x20c0000
1018#define GPIO3_ADDR 0x20a4000
1019#define USDHC3_ADDR 0x2198000
1020static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1021{
1022 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1023
1024 if (off) {
1025 fdt_delprop(blob, off, "ext-reset-output");
1026 fdt_delprop(blob, off, "fsl,ext-reset-output");
1027 }
1028}
1029
1030void ft_early_fixup(void *blob, int board_type)
1031{
1032 struct ventana_board_info *info = &ventana_info;
1033 char rev = 0;
1034 int i;
1035
1036 /* determine board revision */
1037 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1038 if (ventana_info.model[i] >= 'A') {
1039 rev = ventana_info.model[i];
1040 break;
1041 }
1042 }
1043
1044 /*
1045 * Board model specific fixups
1046 */
1047 switch (board_type) {
1048 case GW51xx:
1049 /*
1050 * disable wdog node for GW51xx-A/B to work around
1051 * errata causing wdog timer to be unreliable.
1052 */
1053 if (rev >= 'A' && rev < 'C') {
1054 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1055 WDOG1_ADDR);
1056 if (i)
1057 fdt_status_disabled(blob, i);
1058 }
1059
1060 /* GW51xx-E adds WDOG1_B external reset */
1061 if (rev < 'E')
1062 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1063 break;
1064
1065 case GW52xx:
1066 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1067 if (info->model[4] == '2') {
1068 u32 handle = 0;
1069 u32 *range = NULL;
1070
1071 i = fdt_node_offset_by_compatible(blob, -1,
1072 "fsl,imx6q-pcie");
1073 if (i)
1074 range = (u32 *)fdt_getprop(blob, i,
1075 "reset-gpio", NULL);
1076
1077 if (range) {
1078 i = fdt_node_offset_by_compat_reg(blob,
1079 "fsl,imx6q-gpio", GPIO3_ADDR);
1080 if (i)
1081 handle = fdt_get_phandle(blob, i);
1082 if (handle) {
1083 range[0] = cpu_to_fdt32(handle);
1084 range[1] = cpu_to_fdt32(23);
1085 }
1086 }
1087
1088 /* these have broken usd_vsel */
1089 if (strstr((const char *)info->model, "SP318-B") ||
1090 strstr((const char *)info->model, "SP331-B"))
1091 gpio_cfg[board_type].usd_vsel = 0;
1092
1093 /* GW522x-B adds WDOG1_B external reset */
1094 if (rev < 'B')
1095 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1096 }
1097
1098 /* GW520x-E adds WDOG1_B external reset */
1099 else if (info->model[4] == '0' && rev < 'E')
1100 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1101 break;
1102
1103 case GW53xx:
1104 /* GW53xx-E adds WDOG1_B external reset */
1105 if (rev < 'E')
1106 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1107
1108 /* GW53xx-G has an adv7280 instead of an adv7180 */
1109 else if (rev > 'F') {
1110 i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
1111 if (i) {
1112 fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
1113 fdt_setprop_empty(blob, i, "adv,force-bt656-4");
1114 }
1115 }
1116 break;
1117
1118 case GW54xx:
1119 /*
1120 * disable serial2 node for GW54xx for compatibility with older
1121 * 3.10.x kernel that improperly had this node enabled in the DT
1122 */
1123 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED);
1124
1125 /* GW54xx-E adds WDOG2_B external reset */
1126 if (rev < 'E')
1127 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1128
1129 /* GW54xx-G has an adv7280 instead of an adv7180 */
1130 else if (rev > 'F') {
1131 i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180");
1132 if (i) {
1133 fdt_setprop_string(blob, i, "compatible", "adi,adv7280");
1134 fdt_setprop_empty(blob, i, "adv,force-bt656-4");
1135 }
1136 }
1137 break;
1138
1139 case GW551x:
1140 /* GW551x-C adds WDOG1_B external reset */
1141 if (rev < 'C')
1142 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1143 break;
1144 case GW5901:
1145 case GW5902:
1146 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1147 if (rev < 'B')
1148 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1149 break;
1150 }
1151
1152 /* remove no-1-8-v if UHS-I support is present */
1153 if (gpio_cfg[board_type].usd_vsel) {
1154 debug("Enabling UHS-I support\n");
1155 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1156 USDHC3_ADDR);
1157 if (i)
1158 fdt_delprop(blob, i, "no-1-8-v");
1159 }
1160}
1161
Tim Harvey552c3582014-03-06 07:46:30 -08001162/*
1163 * called prior to booting kernel or by 'fdt boardsetup' command
1164 *
1165 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1166 * - mtd partitions based on mtdparts/mtdids env
1167 * - system-serial (board serial num from EEPROM)
1168 * - board (full model from EEPROM)
1169 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1170 */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001171#define PWM0_ADDR 0x2080000
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001172int ft_board_setup(void *blob, struct bd_info *bd)
Tim Harvey552c3582014-03-06 07:46:30 -08001173{
Tim Harvey552c3582014-03-06 07:46:30 -08001174 struct ventana_board_info *info = &ventana_info;
Tim Harvey0da2c522014-08-07 22:35:45 -07001175 struct ventana_eeprom_config *cfg;
Tim Harvey8e502172021-07-24 10:40:33 -07001176 static const struct node_info nand_nodes[] = {
Tim Harvey552c3582014-03-06 07:46:30 -08001177 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1178 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1179 };
Simon Glass64b723f2017-08-03 12:22:12 -06001180 const char *model = env_get("model");
1181 const char *display = env_get("display");
Tim Harvey16e0eae2015-04-08 12:54:44 -07001182 int i;
1183 char rev = 0;
1184
1185 /* determine board revision */
1186 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1187 if (ventana_info.model[i] >= 'A') {
1188 rev = ventana_info.model[i];
1189 break;
1190 }
1191 }
Tim Harvey552c3582014-03-06 07:46:30 -08001192
Simon Glass64b723f2017-08-03 12:22:12 -06001193 if (env_get("fdt_noauto")) {
Tim Harvey552c3582014-03-06 07:46:30 -08001194 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001195 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001196 }
1197
Tim Harvey8e502172021-07-24 10:40:33 -07001198 /* Update MTD partition nodes using info from mtdparts env var */
1199 puts(" Updating MTD partitions...\n");
1200 fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes));
Tim Harvey552c3582014-03-06 07:46:30 -08001201
Tim Harveye4af5d32015-04-08 12:54:58 -07001202 /* Update display timings from display env var */
1203 if (display) {
1204 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1205 display) >= 0)
1206 printf(" Set display timings for %s...\n", display);
1207 }
1208
Tim Harvey552c3582014-03-06 07:46:30 -08001209 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1210
1211 /* board serial number */
Simon Glass64b723f2017-08-03 12:22:12 -06001212 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1213 strlen(env_get("serial#")) + 1);
Tim Harvey552c3582014-03-06 07:46:30 -08001214
1215 /* board (model contains model from device-tree) */
1216 fdt_setprop(blob, 0, "board", info->model,
1217 strlen((const char *)info->model) + 1);
1218
Tim Harveycf20e552015-04-08 12:55:01 -07001219 /* set desired digital video capture format */
Simon Glass64b723f2017-08-03 12:22:12 -06001220 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
Tim Harveycf20e552015-04-08 12:55:01 -07001221
Tim Harvey28db4e42021-07-24 10:40:32 -07001222 /* early board/revision ft fixups */
1223 ft_early_fixup(blob, board_type);
Tim Harvey6944ccf2015-04-08 12:54:53 -07001224
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001225 /* Configure DIO */
Tim Harvey41595b52016-07-15 07:14:23 -07001226 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001227 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1228 char arg[10];
1229
1230 sprintf(arg, "dio%d", i);
1231 if (!hwconfig(arg))
1232 continue;
1233 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1234 {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001235 phys_addr_t addr;
1236 int off;
1237
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001238 printf(" Enabling pwm%d for DIO%d\n",
1239 cfg->pwm_param, i);
Tim Harvey984aa0d2019-02-04 13:11:00 -08001240 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1241 off = fdt_node_offset_by_compat_reg(blob,
1242 "fsl,imx6q-pwm",
1243 addr);
1244 if (off)
1245 fdt_status_okay(blob, off);
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001246 }
1247 }
1248
Tim Harveybfb240a2016-06-17 06:10:41 -07001249#if defined(CONFIG_CMD_PCI)
Simon Glass64b723f2017-08-03 12:22:12 -06001250 if (!env_get("nopcifixup"))
Tim Harveybfb240a2016-06-17 06:10:41 -07001251 ft_board_pci_fixup(blob, bd);
1252#endif
1253
Tim Harvey6944ccf2015-04-08 12:54:53 -07001254 /*
Tim Harvey7ad148a2021-09-29 15:04:18 -07001255 * remove reset gpio control as we configure the PHY registers
1256 * for internal delay, LED config, and clock config in the bootloader
1257 */
1258 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
1259 if (i)
1260 fdt_delprop(blob, i, "phy-reset-gpios");
1261
1262 /*
Tim Harvey552c3582014-03-06 07:46:30 -08001263 * Peripheral Config:
1264 * remove nodes by alias path if EEPROM config tells us the
1265 * peripheral is not loaded on the board.
1266 */
Simon Glass64b723f2017-08-03 12:22:12 -06001267 if (env_get("fdt_noconfig")) {
Tim Harvey0da2c522014-08-07 22:35:45 -07001268 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001269 return 0;
Tim Harvey0da2c522014-08-07 22:35:45 -07001270 }
1271 cfg = econfig;
1272 while (cfg->name) {
1273 if (!test_bit(cfg->bit, info->config)) {
1274 fdt_del_node_and_alias(blob, cfg->dtalias ?
1275 cfg->dtalias : cfg->name);
1276 }
1277 cfg++;
Tim Harvey552c3582014-03-06 07:46:30 -08001278 }
Simon Glass2aec3cc2014-10-23 18:58:47 -06001279
1280 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001281}
Robert P. J. Day3c757002016-05-19 15:23:12 -04001282#endif /* CONFIG_OF_BOARD_SETUP */