blob: fb745ccceee65c79dcd3ebc2610d66f8b99b257b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tim Harvey552c3582014-03-06 07:46:30 -08002/*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
Tim Harvey552c3582014-03-06 07:46:30 -08006 */
7
8#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <net.h>
Tim Harvey552c3582014-03-06 07:46:30 -080012#include <asm/arch/clock.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070013#include <asm/arch/crm_regs.h>
Tim Harvey552c3582014-03-06 07:46:30 -080014#include <asm/arch/iomux.h>
15#include <asm/arch/mx6-pins.h>
Tim Harveyfb64cc72014-04-25 15:39:07 -070016#include <asm/arch/mxc_hdmi.h>
Tim Harvey552c3582014-03-06 07:46:30 -080017#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060018#include <asm/global_data.h>
Tim Harvey552c3582014-03-06 07:46:30 -080019#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020020#include <asm/mach-imx/boot_mode.h>
21#include <asm/mach-imx/sata.h>
22#include <asm/mach-imx/spi.h>
23#include <asm/mach-imx/video.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070024#include <asm/io.h>
Simon Glassd9a766f2017-05-17 08:23:00 -060025#include <asm/setup.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070026#include <dm.h>
Tim Harvey67ed7922015-05-08 18:28:29 -070027#include <dm/platform_data/serial_mxc.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060028#include <env.h>
Tim Harvey8d2d8df2016-05-24 11:03:55 -070029#include <hwconfig.h>
Tim Harvey552c3582014-03-06 07:46:30 -080030#include <i2c.h>
Tim Harvey552c3582014-03-06 07:46:30 -080031#include <fdt_support.h>
Yangbo Lu73340382019-06-21 11:42:28 +080032#include <fsl_esdhc_imx.h>
Tim Harvey0cee2242015-05-08 18:28:35 -070033#include <jffs2/load_kernel.h>
34#include <linux/ctype.h>
Tim Harvey552c3582014-03-06 07:46:30 -080035#include <miiphy.h>
Tim Harvey552c3582014-03-06 07:46:30 -080036#include <mtd_node.h>
37#include <netdev.h>
Tim Harvey33791d52014-08-07 22:49:57 -070038#include <pci.h>
Simon Glassdbd79542020-05-10 11:40:11 -060039#include <linux/delay.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060040#include <linux/libfdt.h>
Tim Harvey552c3582014-03-06 07:46:30 -080041#include <power/pmic.h>
Tim Harvey0dff16f2014-05-05 08:22:25 -070042#include <power/ltc3676_pmic.h>
Tim Harvey552c3582014-03-06 07:46:30 -080043#include <power/pfuze100_pmic.h>
Tim Harvey552c3582014-03-06 07:46:30 -080044#include <fdt_support.h>
45#include <jffs2/load_kernel.h>
46#include <spi_flash.h>
47
48#include "gsc.h"
Tim Harvey0cee2242015-05-08 18:28:35 -070049#include "common.h"
Tim Harvey552c3582014-03-06 07:46:30 -080050
51DECLARE_GLOBAL_DATA_PTR;
52
Tim Harvey26993362014-08-07 22:35:49 -070053
Tim Harvey552c3582014-03-06 07:46:30 -080054/*
55 * EEPROM board info struct populated by read_eeprom so that we only have to
56 * read it once.
57 */
Tim Harvey0da2c522014-08-07 22:35:45 -070058struct ventana_board_info ventana_info;
Tim Harvey8b92bdf2015-04-08 12:54:43 -070059static int board_type;
Tim Harvey552c3582014-03-06 07:46:30 -080060
Tim Harvey552c3582014-03-06 07:46:30 -080061/* ENET */
Tim Harvey8b92bdf2015-04-08 12:54:43 -070062static iomux_v3_cfg_t const enet_pads[] = {
Tim Harvey02fb5922014-06-02 16:13:26 -070063 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
64 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
71 MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
73 MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
80 MUX_PAD_CTRL(ENET_PAD_CTRL)),
Tim Harvey552c3582014-03-06 07:46:30 -080081 /* PHY nRST */
Tim Harvey26993362014-08-07 22:35:49 -070082 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
Tim Harvey552c3582014-03-06 07:46:30 -080083};
84
Tom Rini52a132c2017-05-08 22:14:25 -040085#ifdef CONFIG_CMD_NAND
Tim Harvey8b92bdf2015-04-08 12:54:43 -070086static iomux_v3_cfg_t const nfc_pads[] = {
Tim Harvey02fb5922014-06-02 16:13:26 -070087 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
88 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
Tim Harvey552c3582014-03-06 07:46:30 -0800102};
103
Tim Harvey552c3582014-03-06 07:46:30 -0800104static void setup_gpmi_nand(void)
105{
106 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
107
108 /* config gpmi nand iomux */
Tim Harvey02fb5922014-06-02 16:13:26 -0700109 SETUP_IOMUX_PADS(nfc_pads);
Tim Harvey552c3582014-03-06 07:46:30 -0800110
111 /* config gpmi and bch clock to 100 MHz */
112 clrsetbits_le32(&mxc_ccm->cs2cdr,
113 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
114 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
115 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
116 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
117 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
118 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
119
120 /* enable gpmi and bch clock gating */
121 setbits_le32(&mxc_ccm->CCGR4,
122 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
123 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
124 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
125 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
126 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
127
128 /* enable apbh clock gating */
129 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
130}
131#endif
132
Tim Harveyf1f41db2015-05-08 18:28:28 -0700133static void setup_iomux_enet(int gpio)
Tim Harvey552c3582014-03-06 07:46:30 -0800134{
Tim Harvey02fb5922014-06-02 16:13:26 -0700135 SETUP_IOMUX_PADS(enet_pads);
Tim Harvey552c3582014-03-06 07:46:30 -0800136
137 /* toggle PHY_RST# */
Tim Harveyf1f41db2015-05-08 18:28:28 -0700138 gpio_request(gpio, "phy_rst#");
139 gpio_direction_output(gpio, 0);
Tim Harvey63537792017-03-17 07:30:38 -0700140 mdelay(10);
Tim Harveyf1f41db2015-05-08 18:28:28 -0700141 gpio_set_value(gpio, 1);
Tim Harvey63537792017-03-17 07:30:38 -0700142 mdelay(100);
Tim Harvey552c3582014-03-06 07:46:30 -0800143}
144
Tim Harvey552c3582014-03-06 07:46:30 -0800145#ifdef CONFIG_USB_EHCI_MX6
Tim Harvey8b92bdf2015-04-08 12:54:43 -0700146static iomux_v3_cfg_t const usb_pads[] = {
Tim Harvey26993362014-08-07 22:35:49 -0700147 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
148 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
Tim Harvey02fb5922014-06-02 16:13:26 -0700149 /* OTG PWR */
Tim Harvey26993362014-08-07 22:35:49 -0700150 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
Tim Harvey552c3582014-03-06 07:46:30 -0800151};
152
153int board_ehci_hcd_init(int port)
154{
Tim Harveyf1f41db2015-05-08 18:28:28 -0700155 int gpio;
Tim Harvey552c3582014-03-06 07:46:30 -0800156
Tim Harvey02fb5922014-06-02 16:13:26 -0700157 SETUP_IOMUX_PADS(usb_pads);
Tim Harvey552c3582014-03-06 07:46:30 -0800158
Tim Harveydb7edfa2015-05-26 11:04:54 -0700159 /* Reset USB HUB */
160 switch (board_type) {
161 case GW53xx:
162 case GW552x:
Tim Harveyb7c48a92019-02-04 13:10:54 -0800163 case GW5906:
Tim Harveyf1f41db2015-05-08 18:28:28 -0700164 gpio = (IMX_GPIO_NR(1, 9));
Tim Harvey552c3582014-03-06 07:46:30 -0800165 break;
Tim Harveydb7edfa2015-05-26 11:04:54 -0700166 case GW54proto:
167 case GW54xx:
Tim Harveyf1f41db2015-05-08 18:28:28 -0700168 gpio = (IMX_GPIO_NR(1, 16));
Tim Harvey552c3582014-03-06 07:46:30 -0800169 break;
Tim Harveyf1f41db2015-05-08 18:28:28 -0700170 default:
171 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -0800172 }
173
Tim Harveyf1f41db2015-05-08 18:28:28 -0700174 /* request and toggle hub rst */
175 gpio_request(gpio, "usb_hub_rst#");
176 gpio_direction_output(gpio, 0);
177 mdelay(2);
178 gpio_set_value(gpio, 1);
179
Tim Harvey552c3582014-03-06 07:46:30 -0800180 return 0;
181}
182
183int board_ehci_power(int port, int on)
184{
Tim Harvey9b9e75f2017-03-13 08:51:07 -0700185 /* enable OTG VBUS */
186 if (!port && board_type < GW_UNKNOWN) {
187 if (gpio_cfg[board_type].otgpwr_en)
188 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
189 }
Tim Harvey552c3582014-03-06 07:46:30 -0800190 return 0;
191}
192#endif /* CONFIG_USB_EHCI_MX6 */
193
Tim Harvey552c3582014-03-06 07:46:30 -0800194#ifdef CONFIG_MXC_SPI
195iomux_v3_cfg_t const ecspi1_pads[] = {
196 /* SS1 */
Tim Harvey02fb5922014-06-02 16:13:26 -0700197 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
198 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
199 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
200 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
Tim Harvey552c3582014-03-06 07:46:30 -0800201};
202
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300203int board_spi_cs_gpio(unsigned bus, unsigned cs)
204{
205 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
206}
207
Tim Harvey552c3582014-03-06 07:46:30 -0800208static void setup_spi(void)
209{
Tim Harveyf1f41db2015-05-08 18:28:28 -0700210 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
Nikita Kiryanov00cd7382014-08-20 15:08:50 +0300211 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
Tim Harvey02fb5922014-06-02 16:13:26 -0700212 SETUP_IOMUX_PADS(ecspi1_pads);
Tim Harvey552c3582014-03-06 07:46:30 -0800213}
214#endif
215
216/* configure eth0 PHY board-specific LED behavior */
217int board_phy_config(struct phy_device *phydev)
218{
219 unsigned short val;
220
221 /* Marvel 88E1510 */
222 if (phydev->phy_id == 0x1410dd1) {
223 /*
224 * Page 3, Register 16: LED[2:0] Function Control Register
225 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
226 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
227 */
228 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
229 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
230 val &= 0xff00;
231 val |= 0x0017;
232 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
233 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
234 }
235
Tim Harvey4533c902017-03-17 07:32:21 -0700236 /* TI DP83867 */
237 else if (phydev->phy_id == 0x2000a231) {
238 /* configure register 0x170 for ref CLKOUT */
239 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
240 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
241 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
242 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
243 val &= ~0x1f00;
244 val |= 0x0b00; /* chD tx clock*/
245 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
246 }
247
Tim Harvey552c3582014-03-06 07:46:30 -0800248 if (phydev->drv->config)
249 phydev->drv->config(phydev);
250
251 return 0;
252}
Tim Harvey63537792017-03-17 07:30:38 -0700253
254#ifdef CONFIG_MV88E61XX_SWITCH
255int mv88e61xx_hw_reset(struct phy_device *phydev)
256{
257 struct mii_dev *bus = phydev->bus;
258
259 /* GPIO[0] output, CLK125 */
260 debug("enabling RGMII_REFCLK\n");
261 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
262 0x1a /*MV_SCRATCH_MISC*/,
263 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
264 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
265 0x1a /*MV_SCRATCH_MISC*/,
266 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
267
268 /* RGMII delay - Physical Control register bit[15:14] */
269 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
270 /* forced 1000mbps full-duplex link */
271 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
272 phydev->autoneg = AUTONEG_DISABLE;
273 phydev->speed = SPEED_1000;
274 phydev->duplex = DUPLEX_FULL;
275
Tim Harvey8c9d3932019-02-04 13:10:47 -0800276 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
277 bus->write(bus, 0x10, 0, 0x16, 0x8088);
278 bus->write(bus, 0x11, 0, 0x16, 0x8088);
279 bus->write(bus, 0x12, 0, 0x16, 0x8088);
280 bus->write(bus, 0x13, 0, 0x16, 0x8088);
Tim Harvey63537792017-03-17 07:30:38 -0700281
282 return 0;
283}
284#endif // CONFIG_MV88E61XX_SWITCH
Tim Harvey552c3582014-03-06 07:46:30 -0800285
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900286int board_eth_init(struct bd_info *bis)
Tim Harvey552c3582014-03-06 07:46:30 -0800287{
Tim Harvey552c3582014-03-06 07:46:30 -0800288#ifdef CONFIG_FEC_MXC
Tim Harvey892068c2016-05-24 11:03:58 -0700289 struct ventana_board_info *info = &ventana_info;
290
291 if (test_bit(EECONFIG_ETH0, info->config)) {
Tim Harveyf1f41db2015-05-08 18:28:28 -0700292 setup_iomux_enet(GP_PHY_RST);
Tim Harvey50581832014-08-20 23:35:14 -0700293 cpu_eth_init(bis);
Tim Harvey85331822015-04-08 12:54:48 -0700294 }
Tim Harvey552c3582014-03-06 07:46:30 -0800295#endif
296
Tim Harvey472884d2015-04-08 12:54:32 -0700297#ifdef CONFIG_E1000
298 e1000_initialize(bis);
299#endif
300
Tim Harvey552c3582014-03-06 07:46:30 -0800301#ifdef CONFIG_CI_UDC
302 /* For otg ethernet*/
303 usb_eth_initialize(bis);
304#endif
305
Tim Harveyfc5ff942015-04-08 12:54:33 -0700306 /* default to the first detected enet dev */
Simon Glass64b723f2017-08-03 12:22:12 -0600307 if (!env_get("ethprime")) {
Tim Harveyfc5ff942015-04-08 12:54:33 -0700308 struct eth_device *dev = eth_get_dev_by_index(0);
309 if (dev) {
Simon Glass6a38e412017-08-03 12:22:09 -0600310 env_set("ethprime", dev->name);
Simon Glass64b723f2017-08-03 12:22:12 -0600311 printf("set ethprime to %s\n", env_get("ethprime"));
Tim Harveyfc5ff942015-04-08 12:54:33 -0700312 }
313 }
314
Tim Harvey552c3582014-03-06 07:46:30 -0800315 return 0;
316}
317
Tim Harveyfb64cc72014-04-25 15:39:07 -0700318#if defined(CONFIG_VIDEO_IPUV3)
319
320static void enable_hdmi(struct display_info_t const *dev)
321{
322 imx_enable_hdmi_phy();
323}
324
325static int detect_i2c(struct display_info_t const *dev)
326{
327 return i2c_set_bus_num(dev->bus) == 0 &&
328 i2c_probe(dev->addr) == 0;
329}
330
331static void enable_lvds(struct display_info_t const *dev)
332{
333 struct iomuxc *iomux = (struct iomuxc *)
334 IOMUXC_BASE_ADDR;
335
336 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
337 u32 reg = readl(&iomux->gpr[2]);
338 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
339 writel(reg, &iomux->gpr[2]);
340
341 /* Enable Backlight */
Tim Harveya67e07f2016-05-24 11:03:53 -0700342 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
343 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
Tim Harveyf1f41db2015-05-08 18:28:28 -0700344 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
Tim Harvey26993362014-08-07 22:35:49 -0700345 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700346 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
347}
348
349struct display_info_t const displays[] = {{
350 /* HDMI Output */
351 .bus = -1,
352 .addr = 0,
353 .pixfmt = IPU_PIX_FMT_RGB24,
354 .detect = detect_hdmi,
355 .enable = enable_hdmi,
356 .mode = {
357 .name = "HDMI",
358 .refresh = 60,
359 .xres = 1024,
360 .yres = 768,
361 .pixclock = 15385,
362 .left_margin = 220,
363 .right_margin = 40,
364 .upper_margin = 21,
365 .lower_margin = 7,
366 .hsync_len = 60,
367 .vsync_len = 10,
368 .sync = FB_SYNC_EXT,
369 .vmode = FB_VMODE_NONINTERLACED
370} }, {
371 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
372 .bus = 2,
373 .addr = 0x4,
374 .pixfmt = IPU_PIX_FMT_LVDS666,
375 .detect = detect_i2c,
376 .enable = enable_lvds,
377 .mode = {
378 .name = "Hannstar-XGA",
379 .refresh = 60,
380 .xres = 1024,
381 .yres = 768,
382 .pixclock = 15385,
383 .left_margin = 220,
384 .right_margin = 40,
385 .upper_margin = 21,
386 .lower_margin = 7,
387 .hsync_len = 60,
388 .vsync_len = 10,
389 .sync = FB_SYNC_EXT,
390 .vmode = FB_VMODE_NONINTERLACED
Tim Harveya20bd632015-04-08 12:54:57 -0700391} }, {
392 /* DLC700JMG-T-4 */
Tim Harveybe786e72019-02-04 13:10:53 -0800393 .bus = 2,
394 .addr = 0x38,
Tim Harveya20bd632015-04-08 12:54:57 -0700395 .detect = NULL,
396 .enable = enable_lvds,
397 .pixfmt = IPU_PIX_FMT_LVDS666,
398 .mode = {
399 .name = "DLC700JMGT4",
400 .refresh = 60,
401 .xres = 1024, /* 1024x600active pixels */
402 .yres = 600,
403 .pixclock = 15385, /* 64MHz */
404 .left_margin = 220,
405 .right_margin = 40,
406 .upper_margin = 21,
407 .lower_margin = 7,
408 .hsync_len = 60,
409 .vsync_len = 10,
410 .sync = FB_SYNC_EXT,
411 .vmode = FB_VMODE_NONINTERLACED
412} }, {
413 /* DLC800FIG-T-3 */
Tim Harveybe786e72019-02-04 13:10:53 -0800414 .bus = 2,
415 .addr = 0x14,
Tim Harveya20bd632015-04-08 12:54:57 -0700416 .detect = NULL,
417 .enable = enable_lvds,
418 .pixfmt = IPU_PIX_FMT_LVDS666,
419 .mode = {
420 .name = "DLC800FIGT3",
421 .refresh = 60,
422 .xres = 1024, /* 1024x768 active pixels */
423 .yres = 768,
424 .pixclock = 15385, /* 64MHz */
425 .left_margin = 220,
426 .right_margin = 40,
427 .upper_margin = 21,
428 .lower_margin = 7,
429 .hsync_len = 60,
430 .vsync_len = 10,
431 .sync = FB_SYNC_EXT,
432 .vmode = FB_VMODE_NONINTERLACED
Tim Harveyc34e59e2019-02-04 13:10:51 -0800433} }, {
434 .bus = 2,
435 .addr = 0x5d,
436 .detect = detect_i2c,
437 .enable = enable_lvds,
438 .pixfmt = IPU_PIX_FMT_LVDS666,
439 .mode = {
440 .name = "Z101WX01",
441 .refresh = 60,
442 .xres = 1280,
443 .yres = 800,
444 .pixclock = 15385, /* 64MHz */
445 .left_margin = 220,
446 .right_margin = 40,
447 .upper_margin = 21,
448 .lower_margin = 7,
449 .hsync_len = 60,
450 .vsync_len = 10,
451 .sync = FB_SYNC_EXT,
452 .vmode = FB_VMODE_NONINTERLACED
453 }
454},
455};
Tim Harveyfb64cc72014-04-25 15:39:07 -0700456size_t display_count = ARRAY_SIZE(displays);
457
458static void setup_display(void)
459{
460 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
461 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
462 int reg;
463
464 enable_ipu_clock();
465 imx_setup_hdmi();
466 /* Turn on LDB0,IPU,IPU DI0 clocks */
467 reg = __raw_readl(&mxc_ccm->CCGR3);
468 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
469 writel(reg, &mxc_ccm->CCGR3);
470
471 /* set LDB0, LDB1 clk select to 011/011 */
472 reg = readl(&mxc_ccm->cs2cdr);
473 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
474 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
475 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
476 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
477 writel(reg, &mxc_ccm->cs2cdr);
478
479 reg = readl(&mxc_ccm->cscmr2);
480 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
481 writel(reg, &mxc_ccm->cscmr2);
482
483 reg = readl(&mxc_ccm->chsccdr);
484 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
485 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
486 writel(reg, &mxc_ccm->chsccdr);
487
488 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
489 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
490 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
491 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
492 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
493 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
494 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
495 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
496 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
497 writel(reg, &iomux->gpr[2]);
498
499 reg = readl(&iomux->gpr[3]);
500 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
501 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
502 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
503 writel(reg, &iomux->gpr[3]);
504
Tim Harveya67e07f2016-05-24 11:03:53 -0700505 /* LVDS Backlight GPIO on LVDS connector - output low */
Tim Harvey26993362014-08-07 22:35:49 -0700506 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
Tim Harveyfb64cc72014-04-25 15:39:07 -0700507 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
508}
509#endif /* CONFIG_VIDEO_IPUV3 */
510
Tim Harvey0dff16f2014-05-05 08:22:25 -0700511/* setup board specific PMIC */
512int power_init_board(void)
513{
Tim Harvey195bc972015-05-08 18:28:37 -0700514 setup_pmic();
Tim Harvey0dff16f2014-05-05 08:22:25 -0700515 return 0;
516}
517
Tim Harvey552c3582014-03-06 07:46:30 -0800518#if defined(CONFIG_CMD_PCI)
519int imx6_pcie_toggle_reset(void)
520{
521 if (board_type < GW_UNKNOWN) {
Tim Harvey02fb5922014-06-02 16:13:26 -0700522 uint pin = gpio_cfg[board_type].pcie_rst;
Tim Harveyf1f41db2015-05-08 18:28:28 -0700523 gpio_request(pin, "pci_rst#");
Tim Harvey02fb5922014-06-02 16:13:26 -0700524 gpio_direction_output(pin, 0);
Tim Harvey552c3582014-03-06 07:46:30 -0800525 mdelay(50);
Tim Harvey02fb5922014-06-02 16:13:26 -0700526 gpio_direction_output(pin, 1);
Tim Harvey552c3582014-03-06 07:46:30 -0800527 }
528 return 0;
529}
Tim Harvey33791d52014-08-07 22:49:57 -0700530
531/*
532 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
533 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
534 * properly and assert reset for 100ms.
535 */
Tim Harveybfb240a2016-06-17 06:10:41 -0700536#define MAX_PCI_DEVS 32
537struct pci_dev {
538 pci_dev_t devfn;
539 unsigned short vendor;
540 unsigned short device;
541 unsigned short class;
542 unsigned short busno; /* subbordinate busno */
543 struct pci_dev *ppar;
544};
545struct pci_dev pci_devs[MAX_PCI_DEVS];
546int pci_devno;
547int pci_bridgeno;
548
Tim Harvey33791d52014-08-07 22:49:57 -0700549void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
550 unsigned short vendor, unsigned short device,
551 unsigned short class)
552{
Tim Harveybfb240a2016-06-17 06:10:41 -0700553 int i;
Tim Harvey33791d52014-08-07 22:49:57 -0700554 u32 dw;
Tim Harveybfb240a2016-06-17 06:10:41 -0700555 struct pci_dev *pdev = &pci_devs[pci_devno++];
Tim Harvey33791d52014-08-07 22:49:57 -0700556
557 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
558 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
Tim Harveybfb240a2016-06-17 06:10:41 -0700559
560 /* store array of devs for later use in device-tree fixup */
561 pdev->devfn = dev;
562 pdev->vendor = vendor;
563 pdev->device = device;
564 pdev->class = class;
565 pdev->ppar = NULL;
566 if (class == PCI_CLASS_BRIDGE_PCI)
567 pdev->busno = ++pci_bridgeno;
568 else
569 pdev->busno = 0;
570
571 /* fixup RC - it should be 00:00.0 not 00:01.0 */
572 if (PCI_BUS(dev) == 0)
573 pdev->devfn = 0;
574
575 /* find dev's parent */
576 for (i = 0; i < pci_devno; i++) {
577 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
578 pdev->ppar = &pci_devs[i];
579 break;
580 }
581 }
582
583 /* assert downstream PERST# */
Tim Harvey33791d52014-08-07 22:49:57 -0700584 if (vendor == PCI_VENDOR_ID_PLX &&
585 (device & 0xfff0) == 0x8600 &&
586 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
587 debug("configuring PLX 860X downstream PERST#\n");
588 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
589 dw |= 0xaaa8; /* GPIO1-7 outputs */
590 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
591
592 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
593 dw |= 0xfe; /* GPIO1-7 output high */
594 pci_hose_write_config_dword(hose, dev, 0x644, dw);
595
596 mdelay(100);
597 }
598}
Tim Harvey552c3582014-03-06 07:46:30 -0800599#endif /* CONFIG_CMD_PCI */
600
601#ifdef CONFIG_SERIAL_TAG
602/*
603 * called when setting up ATAGS before booting kernel
604 * populate serialnum from the following (in order of priority):
605 * serial# env var
606 * eeprom
607 */
608void get_board_serial(struct tag_serialnr *serialnr)
609{
Simon Glass64b723f2017-08-03 12:22:12 -0600610 char *serial = env_get("serial#");
Tim Harvey552c3582014-03-06 07:46:30 -0800611
612 if (serial) {
613 serialnr->high = 0;
614 serialnr->low = simple_strtoul(serial, NULL, 10);
615 } else if (ventana_info.model[0]) {
616 serialnr->high = 0;
617 serialnr->low = ventana_info.serial;
618 } else {
619 serialnr->high = 0;
620 serialnr->low = 0;
621 }
622}
623#endif
624
625/*
626 * Board Support
627 */
628
629int board_early_init_f(void)
630{
631 setup_iomux_uart();
Tim Harveyf1f41db2015-05-08 18:28:28 -0700632
Tim Harveyfb64cc72014-04-25 15:39:07 -0700633#if defined(CONFIG_VIDEO_IPUV3)
634 setup_display();
635#endif
Tim Harvey552c3582014-03-06 07:46:30 -0800636 return 0;
637}
638
639int dram_init(void)
640{
Tim Harveybfa2dae2014-06-02 16:13:27 -0700641 gd->ram_size = imx_ddr_size();
Tim Harvey552c3582014-03-06 07:46:30 -0800642 return 0;
643}
644
645int board_init(void)
646{
Fabio Estevamceb74c42014-07-09 17:59:54 -0300647 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
Tim Harvey552c3582014-03-06 07:46:30 -0800648
649 clrsetbits_le32(&iomuxc_regs->gpr[1],
650 IOMUXC_GPR1_OTG_ID_MASK,
651 IOMUXC_GPR1_OTG_ID_GPIO1);
652
653 /* address of linux boot parameters */
654 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
655
Tim Harveyba9f2342019-02-04 13:10:52 -0800656 /* read Gateworks EEPROM into global struct (used later) */
657 setup_ventana_i2c(0);
658 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
659
Tim Harvey552c3582014-03-06 07:46:30 -0800660#ifdef CONFIG_CMD_NAND
Tim Harveyba9f2342019-02-04 13:10:52 -0800661 if (gpio_cfg[board_type].nand)
662 setup_gpmi_nand();
Tim Harvey552c3582014-03-06 07:46:30 -0800663#endif
664#ifdef CONFIG_MXC_SPI
665 setup_spi();
666#endif
Tim Harveyd04dc812019-02-04 13:10:49 -0800667 setup_ventana_i2c(1);
668 setup_ventana_i2c(2);
Tim Harvey552c3582014-03-06 07:46:30 -0800669
Simon Glassab3055a2017-06-14 21:28:25 -0600670#ifdef CONFIG_SATA
Tim Harvey552c3582014-03-06 07:46:30 -0800671 setup_sata();
672#endif
Tim Harvey552c3582014-03-06 07:46:30 -0800673
Tim Harvey0cee2242015-05-08 18:28:35 -0700674 setup_iomux_gpio(board_type, &ventana_info);
Tim Harvey552c3582014-03-06 07:46:30 -0800675
676 return 0;
677}
678
Tim Harvey948202c2021-03-01 14:33:32 -0800679int board_fit_config_name_match(const char *name)
680{
681 static char init;
682 const char *dtb;
683 char buf[32];
684 int i = 0;
685
686 do {
687 dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
688 if (dtb && !strcmp(dtb, name)) {
689 if (!init++)
690 printf("DTB: %s\n", name);
691 return 0;
692 }
693 } while (dtb);
694
695 return -1;
696}
697
Tim Harvey552c3582014-03-06 07:46:30 -0800698#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
699/*
700 * called during late init (after relocation and after board_init())
701 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
702 * EEPROM read.
703 */
704int checkboard(void)
705{
706 struct ventana_board_info *info = &ventana_info;
707 unsigned char buf[4];
708 const char *p;
709 int quiet; /* Quiet or minimal output mode */
710
711 quiet = 0;
Simon Glass64b723f2017-08-03 12:22:12 -0600712 p = env_get("quiet");
Tim Harvey552c3582014-03-06 07:46:30 -0800713 if (p)
714 quiet = simple_strtol(p, NULL, 10);
715 else
Simon Glass6a38e412017-08-03 12:22:09 -0600716 env_set("quiet", "0");
Tim Harvey552c3582014-03-06 07:46:30 -0800717
718 puts("\nGateworks Corporation Copyright 2014\n");
719 if (info->model[0]) {
720 printf("Model: %s\n", info->model);
721 printf("MFGDate: %02x-%02x-%02x%02x\n",
722 info->mfgdate[0], info->mfgdate[1],
723 info->mfgdate[2], info->mfgdate[3]);
724 printf("Serial:%d\n", info->serial);
725 } else {
726 puts("Invalid EEPROM - board will not function fully\n");
727 }
728 if (quiet)
729 return 0;
730
731 /* Display GSC firmware revision/CRC/status */
Tim Harvey92e3d842015-04-08 12:54:59 -0700732 gsc_info(0);
733
Tim Harvey552c3582014-03-06 07:46:30 -0800734 /* Display RTC */
735 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
736 printf("RTC: %d\n",
737 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
738 }
739
740 return 0;
741}
742#endif
743
744#ifdef CONFIG_CMD_BMODE
745/*
746 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
747 * see Table 8-11 and Table 5-9
748 * BOOT_CFG1[7] = 1 (boot from NAND)
749 * BOOT_CFG1[5] = 0 - raw NAND
750 * BOOT_CFG1[4] = 0 - default pad settings
751 * BOOT_CFG1[3:2] = 00 - devices = 1
752 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
753 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
754 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
755 * BOOT_CFG2[0] = 0 - Reset time 12ms
756 */
757static const struct boot_mode board_boot_modes[] = {
758 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
759 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
Tim Harvey659441b2017-03-17 07:31:02 -0700760 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
Tim Harveya2d24c92019-02-04 13:10:50 -0800761 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
Tim Harvey552c3582014-03-06 07:46:30 -0800762 { NULL, 0 },
763};
764#endif
765
766/* late init */
767int misc_init_r(void)
768{
769 struct ventana_board_info *info = &ventana_info;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700770 char buf[256];
771 int i;
Tim Harvey552c3582014-03-06 07:46:30 -0800772
773 /* set env vars based on EEPROM data */
774 if (ventana_info.model[0]) {
775 char str[16], fdt[36];
776 char *p;
777 const char *cputype = "";
Tim Harvey552c3582014-03-06 07:46:30 -0800778
779 /*
780 * FDT name will be prefixed with CPU type. Three versions
781 * will be created each increasingly generic and bootloader
782 * env scripts will try loading each from most specific to
783 * least.
784 */
Tim Harveybfa2dae2014-06-02 16:13:27 -0700785 if (is_cpu_type(MXC_CPU_MX6Q) ||
786 is_cpu_type(MXC_CPU_MX6D))
Tim Harvey552c3582014-03-06 07:46:30 -0800787 cputype = "imx6q";
Tim Harveybfa2dae2014-06-02 16:13:27 -0700788 else if (is_cpu_type(MXC_CPU_MX6DL) ||
789 is_cpu_type(MXC_CPU_MX6SOLO))
Tim Harvey552c3582014-03-06 07:46:30 -0800790 cputype = "imx6dl";
Simon Glass6a38e412017-08-03 12:22:09 -0600791 env_set("soctype", cputype);
Tim Harvey06d87432014-08-07 22:35:41 -0700792 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
Simon Glass6a38e412017-08-03 12:22:09 -0600793 env_set("flash_layout", "large");
Tim Harvey06d87432014-08-07 22:35:41 -0700794 else
Simon Glass6a38e412017-08-03 12:22:09 -0600795 env_set("flash_layout", "normal");
Tim Harvey552c3582014-03-06 07:46:30 -0800796 memset(str, 0, sizeof(str));
797 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
798 str[i] = tolower(info->model[i]);
Simon Glass6a38e412017-08-03 12:22:09 -0600799 env_set("model", str);
Simon Glass64b723f2017-08-03 12:22:12 -0600800 if (!env_get("fdt_file")) {
Tim Harvey552c3582014-03-06 07:46:30 -0800801 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600802 env_set("fdt_file", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800803 }
804 p = strchr(str, '-');
805 if (p) {
806 *p++ = 0;
807
Simon Glass6a38e412017-08-03 12:22:09 -0600808 env_set("model_base", str);
Tim Harveyf6db79a2015-05-26 11:04:56 -0700809 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600810 env_set("fdt_file1", fdt);
Tim Harvey892068c2016-05-24 11:03:58 -0700811 if (board_type != GW551x &&
812 board_type != GW552x &&
Tim Harvey659441b2017-03-17 07:31:02 -0700813 board_type != GW553x &&
814 board_type != GW560x)
Tim Harvey50581832014-08-20 23:35:14 -0700815 str[4] = 'x';
Tim Harvey552c3582014-03-06 07:46:30 -0800816 str[5] = 'x';
817 str[6] = 0;
Tim Harveyf6db79a2015-05-26 11:04:56 -0700818 sprintf(fdt, "%s-%s.dtb", cputype, str);
Simon Glass6a38e412017-08-03 12:22:09 -0600819 env_set("fdt_file2", fdt);
Tim Harvey552c3582014-03-06 07:46:30 -0800820 }
821
822 /* initialize env from EEPROM */
823 if (test_bit(EECONFIG_ETH0, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600824 !env_get("ethaddr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600825 eth_env_set_enetaddr("ethaddr", info->mac0);
Tim Harvey552c3582014-03-06 07:46:30 -0800826 }
827 if (test_bit(EECONFIG_ETH1, info->config) &&
Simon Glass64b723f2017-08-03 12:22:12 -0600828 !env_get("eth1addr")) {
Simon Glass8551d552017-08-03 12:22:11 -0600829 eth_env_set_enetaddr("eth1addr", info->mac1);
Tim Harvey552c3582014-03-06 07:46:30 -0800830 }
831
832 /* board serial-number */
833 sprintf(str, "%6d", info->serial);
Simon Glass6a38e412017-08-03 12:22:09 -0600834 env_set("serial#", str);
Tim Harvey27770822015-04-08 12:54:51 -0700835
836 /* memory MB */
837 sprintf(str, "%d", (int) (gd->ram_size >> 20));
Simon Glass6a38e412017-08-03 12:22:09 -0600838 env_set("mem_mb", str);
Tim Harvey552c3582014-03-06 07:46:30 -0800839 }
840
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700841 /* Set a non-initialized hwconfig based on board configuration */
Simon Glass64b723f2017-08-03 12:22:12 -0600842 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
Tim Harveyfd6f2392017-03-13 08:51:06 -0700843 buf[0] = 0;
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700844 if (gpio_cfg[board_type].rs232_en)
845 strcat(buf, "rs232;");
846 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
847 char buf1[32];
848 sprintf(buf1, "dio%d:mode=gpio;", i);
849 if (strlen(buf) + strlen(buf1) < sizeof(buf))
850 strcat(buf, buf1);
851 }
Simon Glass6a38e412017-08-03 12:22:09 -0600852 env_set("hwconfig", buf);
Tim Harvey71dbb2c2016-07-15 07:14:25 -0700853 }
Tim Harvey552c3582014-03-06 07:46:30 -0800854
Tim Harvey0cee2242015-05-08 18:28:35 -0700855 /* setup baseboard specific GPIO based on board and env */
856 setup_board_gpio(board_type, info);
Tim Harvey552c3582014-03-06 07:46:30 -0800857
858#ifdef CONFIG_CMD_BMODE
859 add_board_boot_modes(board_boot_modes);
860#endif
861
Tim Harvey40feabb2015-05-08 18:28:36 -0700862 /* disable boot watchdog */
863 gsc_boot_wd_disable();
Tim Harvey552c3582014-03-06 07:46:30 -0800864
865 return 0;
866}
867
Robert P. J. Day3c757002016-05-19 15:23:12 -0400868#ifdef CONFIG_OF_BOARD_SETUP
Tim Harvey552c3582014-03-06 07:46:30 -0800869
Tim Harveycf20e552015-04-08 12:55:01 -0700870static int ft_sethdmiinfmt(void *blob, char *mode)
871{
872 int off;
873
874 if (!mode)
875 return -EINVAL;
876
877 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
878 if (off < 0)
879 return off;
880
881 if (0 == strcasecmp(mode, "yuv422bt656")) {
882 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
883 0x00, 0x00, 0x00 };
884 mode = "422_ccir";
885 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
886 fdt_setprop_u32(blob, off, "vidout_trc", 1);
887 fdt_setprop_u32(blob, off, "vidout_blc", 1);
888 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
889 printf(" set HDMI input mode to %s\n", mode);
890 } else if (0 == strcasecmp(mode, "yuv422smp")) {
891 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
892 0x82, 0x81, 0x00 };
893 mode = "422_smp";
894 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
895 fdt_setprop_u32(blob, off, "vidout_trc", 0);
896 fdt_setprop_u32(blob, off, "vidout_blc", 0);
897 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
898 printf(" set HDMI input mode to %s\n", mode);
899 } else {
900 return -EINVAL;
901 }
902
903 return 0;
904}
905
Tim Harveybfb240a2016-06-17 06:10:41 -0700906#if defined(CONFIG_CMD_PCI)
907#define PCI_ID(x) ( \
908 (PCI_BUS(x->devfn)<<16)| \
909 (PCI_DEV(x->devfn)<<11)| \
910 (PCI_FUNC(x->devfn)<<8) \
911 )
Tim Harveybfb240a2016-06-17 06:10:41 -0700912int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
913{
914 uint32_t reg[5];
915 char node[32];
916 int np;
917
918 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
919 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
920
921 np = fdt_subnode_offset(blob, par, node);
922 if (np >= 0)
923 return np;
924 np = fdt_add_subnode(blob, par, node);
925 if (np < 0) {
926 printf(" %s failed: no space\n", __func__);
927 return np;
928 }
929
930 memset(reg, 0, sizeof(reg));
931 reg[0] = cpu_to_fdt32(PCI_ID(dev));
932 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
933
934 return np;
935}
936
937/* build a path of nested PCI devs for all bridges passed through */
938int fdt_add_pci_path(void *blob, struct pci_dev *dev)
939{
940 struct pci_dev *bridges[MAX_PCI_DEVS];
941 int k, np;
942
943 /* build list of parents */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800944 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700945 if (np < 0)
946 return np;
947
948 k = 0;
949 while (dev) {
950 bridges[k++] = dev;
951 dev = dev->ppar;
952 };
953
954 /* now add them the to DT in reverse order */
955 while (k--) {
956 np = fdt_add_pci_node(blob, np, bridges[k]);
957 if (np < 0)
958 break;
959 }
960
961 return np;
962}
963
964/*
965 * The GW16082 has a hardware errata errata such that it's
966 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
967 * of this normal PCI interrupt swizzling will not work so we will
968 * provide an irq-map via device-tree.
969 */
970int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
971{
972 int len;
973 int host;
974 uint32_t imap_new[8*4*4];
975 const uint32_t *imap;
976 uint32_t irq[4];
977 uint32_t reg[4];
978 int i;
979
980 /* build irq-map based on host controllers map */
Tim Harvey984aa0d2019-02-04 13:11:00 -0800981 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
Tim Harveybfb240a2016-06-17 06:10:41 -0700982 if (host < 0) {
983 printf(" %s failed: missing host\n", __func__);
984 return host;
985 }
986
987 /* use interrupt data from root complex's node */
988 imap = fdt_getprop(blob, host, "interrupt-map", &len);
989 if (!imap || len != 128) {
990 printf(" %s failed: invalid interrupt-map\n",
991 __func__);
992 return -FDT_ERR_NOTFOUND;
993 }
994
995 /* obtain irq's of host controller in pin order */
996 for (i = 0; i < 4; i++)
997 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
998
999 /*
1000 * determine number of swizzles necessary:
1001 * For each bridge we pass through we need to swizzle
1002 * the number of the slot we are on.
1003 */
1004 struct pci_dev *d;
1005 int b;
1006 b = 0;
1007 d = dev->ppar;
1008 while(d && d->ppar) {
1009 b += PCI_DEV(d->devfn);
1010 d = d->ppar;
1011 }
1012
1013 /* create new irq mappings for slots12-15
1014 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
1015 * J3 AD28 12 INTD INTA
1016 * J4 AD29 13 INTC INTD
1017 * J5 AD30 14 INTB INTC
1018 * J2 AD31 15 INTA INTB
1019 */
1020 for (i = 0; i < 4; i++) {
1021 /* addr matches bus:dev:func */
1022 u32 addr = dev->busno << 16 | (12+i) << 11;
1023
1024 /* default cells from root complex */
1025 memcpy(&imap_new[i*32], imap, 128);
1026 /* first cell is PCI device address (BDF) */
1027 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1028 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1029 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1030 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1031 /* third cell is pin */
1032 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1033 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1034 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1035 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1036 /* sixth cell is relative interrupt */
1037 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1038 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1039 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1040 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1041 }
1042 fdt_setprop(blob, np, "interrupt-map", imap_new,
1043 sizeof(imap_new));
1044 reg[0] = cpu_to_fdt32(0xfff00);
1045 reg[1] = 0;
1046 reg[2] = 0;
1047 reg[3] = cpu_to_fdt32(0x7);
1048 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1049 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1050 fdt_setprop_string(blob, np, "device_type", "pci");
1051 fdt_setprop_cell(blob, np, "#address-cells", 3);
1052 fdt_setprop_cell(blob, np, "#size-cells", 2);
1053 printf(" Added custom interrupt-map for GW16082\n");
1054
1055 return 0;
1056}
1057
Tim Harvey77b82a12016-06-17 06:10:42 -07001058/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1059int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1060{
1061 char *tmp, *end;
1062 char mac[16];
1063 unsigned char mac_addr[6];
1064 int j;
1065
1066 sprintf(mac, "eth1addr");
Simon Glass64b723f2017-08-03 12:22:12 -06001067 tmp = env_get(mac);
Tim Harvey77b82a12016-06-17 06:10:42 -07001068 if (tmp) {
1069 for (j = 0; j < 6; j++) {
1070 mac_addr[j] = tmp ?
1071 simple_strtoul(tmp, &end,16) : 0;
1072 if (tmp)
1073 tmp = (*end) ? end+1 : end;
1074 }
1075 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1076 sizeof(mac_addr));
1077 printf(" Added mac addr for eth1\n");
1078 return 0;
1079 }
1080
1081 return -1;
1082}
1083
Tim Harveybfb240a2016-06-17 06:10:41 -07001084/*
1085 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1086 * we will walk the PCI bus and add bridge nodes up to the device receiving
1087 * the fixup.
1088 */
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001089void ft_board_pci_fixup(void *blob, struct bd_info *bd)
Tim Harveybfb240a2016-06-17 06:10:41 -07001090{
1091 int i, np;
1092 struct pci_dev *dev;
1093
1094 for (i = 0; i < pci_devno; i++) {
1095 dev = &pci_devs[i];
1096
1097 /*
1098 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1099 * an EEPROM at i2c1-0x50.
1100 */
1101 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1102 (dev->device == 0x8240) &&
1103 (i2c_set_bus_num(1) == 0) &&
1104 (i2c_probe(0x50) == 0))
1105 {
1106 np = fdt_add_pci_path(blob, dev);
1107 if (np > 0)
1108 fdt_fixup_gw16082(blob, np, dev);
1109 }
Tim Harvey77b82a12016-06-17 06:10:42 -07001110
1111 /* ethernet1 mac address */
1112 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1113 (dev->device == 0x4380))
1114 {
1115 np = fdt_add_pci_path(blob, dev);
1116 if (np > 0)
1117 fdt_fixup_sky2(blob, np, dev);
1118 }
Tim Harveybfb240a2016-06-17 06:10:41 -07001119 }
1120}
1121#endif /* if defined(CONFIG_CMD_PCI) */
Tim Harvey147b5762016-05-24 11:03:59 -07001122
Tim Harvey984aa0d2019-02-04 13:11:00 -08001123void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
Tim Harveyfcabb0b2017-05-15 10:05:07 -07001124{
Tim Harvey984aa0d2019-02-04 13:11:00 -08001125 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1126
1127 if (off) {
1128 fdt_delprop(blob, off, "ext-reset-output");
1129 fdt_delprop(blob, off, "fsl,ext-reset-output");
1130 }
Tim Harveyfcabb0b2017-05-15 10:05:07 -07001131}
1132
Tim Harvey552c3582014-03-06 07:46:30 -08001133/*
1134 * called prior to booting kernel or by 'fdt boardsetup' command
1135 *
1136 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1137 * - mtd partitions based on mtdparts/mtdids env
1138 * - system-serial (board serial num from EEPROM)
1139 * - board (full model from EEPROM)
1140 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1141 */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001142#define WDOG1_ADDR 0x20bc000
1143#define WDOG2_ADDR 0x20c0000
1144#define GPIO3_ADDR 0x20a4000
1145#define USDHC3_ADDR 0x2198000
1146#define PWM0_ADDR 0x2080000
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001147int ft_board_setup(void *blob, struct bd_info *bd)
Tim Harvey552c3582014-03-06 07:46:30 -08001148{
Tim Harvey552c3582014-03-06 07:46:30 -08001149 struct ventana_board_info *info = &ventana_info;
Tim Harvey0da2c522014-08-07 22:35:45 -07001150 struct ventana_eeprom_config *cfg;
Masahiro Yamada20ead6f2018-07-19 16:28:23 +09001151 static const struct node_info nodes[] = {
Tim Harvey552c3582014-03-06 07:46:30 -08001152 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1153 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1154 };
Simon Glass64b723f2017-08-03 12:22:12 -06001155 const char *model = env_get("model");
1156 const char *display = env_get("display");
Tim Harvey16e0eae2015-04-08 12:54:44 -07001157 int i;
1158 char rev = 0;
1159
1160 /* determine board revision */
1161 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1162 if (ventana_info.model[i] >= 'A') {
1163 rev = ventana_info.model[i];
1164 break;
1165 }
1166 }
Tim Harvey552c3582014-03-06 07:46:30 -08001167
Simon Glass64b723f2017-08-03 12:22:12 -06001168 if (env_get("fdt_noauto")) {
Tim Harvey552c3582014-03-06 07:46:30 -08001169 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001170 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001171 }
1172
Tim Harveyc9e43e02015-05-26 11:04:58 -07001173 if (test_bit(EECONFIG_NAND, info->config)) {
1174 /* Update partition nodes using info from mtdparts env var */
1175 puts(" Updating MTD partitions...\n");
1176 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1177 }
Tim Harvey552c3582014-03-06 07:46:30 -08001178
Tim Harveye4af5d32015-04-08 12:54:58 -07001179 /* Update display timings from display env var */
1180 if (display) {
1181 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1182 display) >= 0)
1183 printf(" Set display timings for %s...\n", display);
1184 }
1185
Tim Harvey552c3582014-03-06 07:46:30 -08001186 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1187
1188 /* board serial number */
Simon Glass64b723f2017-08-03 12:22:12 -06001189 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1190 strlen(env_get("serial#")) + 1);
Tim Harvey552c3582014-03-06 07:46:30 -08001191
1192 /* board (model contains model from device-tree) */
1193 fdt_setprop(blob, 0, "board", info->model,
1194 strlen((const char *)info->model) + 1);
1195
Tim Harveycf20e552015-04-08 12:55:01 -07001196 /* set desired digital video capture format */
Simon Glass64b723f2017-08-03 12:22:12 -06001197 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
Tim Harveycf20e552015-04-08 12:55:01 -07001198
Tim Harvey552c3582014-03-06 07:46:30 -08001199 /*
Tim Harveya1d32222016-07-15 07:16:28 -07001200 * Board model specific fixups
Tim Harvey865dc9c2015-04-08 12:54:56 -07001201 */
Tim Harveya1d32222016-07-15 07:16:28 -07001202 switch (board_type) {
1203 case GW51xx:
1204 /*
1205 * disable wdog node for GW51xx-A/B to work around
1206 * errata causing wdog timer to be unreliable.
1207 */
1208 if (rev >= 'A' && rev < 'C') {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001209 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1210 WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001211 if (i)
1212 fdt_status_disabled(blob, i);
1213 }
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001214
1215 /* GW51xx-E adds WDOG1_B external reset */
1216 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001217 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001218 break;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001219
Tim Harveya1d32222016-07-15 07:16:28 -07001220 case GW52xx:
1221 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1222 if (info->model[4] == '2') {
1223 u32 handle = 0;
1224 u32 *range = NULL;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001225
Tim Harveya1d32222016-07-15 07:16:28 -07001226 i = fdt_node_offset_by_compatible(blob, -1,
1227 "fsl,imx6q-pcie");
Pushpal Sidhud1100562015-04-08 12:55:00 -07001228 if (i)
Tim Harveya1d32222016-07-15 07:16:28 -07001229 range = (u32 *)fdt_getprop(blob, i,
1230 "reset-gpio", NULL);
1231
1232 if (range) {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001233 i = fdt_node_offset_by_compat_reg(blob,
1234 "fsl,imx6q-gpio", GPIO3_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001235 if (i)
1236 handle = fdt_get_phandle(blob, i);
1237 if (handle) {
1238 range[0] = cpu_to_fdt32(handle);
1239 range[1] = cpu_to_fdt32(23);
1240 }
Pushpal Sidhud1100562015-04-08 12:55:00 -07001241 }
Tim Harveya1d32222016-07-15 07:16:28 -07001242
1243 /* these have broken usd_vsel */
1244 if (strstr((const char *)info->model, "SP318-B") ||
1245 strstr((const char *)info->model, "SP331-B"))
1246 gpio_cfg[board_type].usd_vsel = 0;
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001247
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001248 /* GW522x-B adds WDOG1_B external reset */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001249 if (rev < 'B')
1250 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Pushpal Sidhud1100562015-04-08 12:55:00 -07001251 }
Tim Harveydc5996a2017-05-15 10:05:06 -07001252
1253 /* GW520x-E adds WDOG1_B external reset */
1254 else if (info->model[4] == '0' && rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001255 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001256 break;
Tim Harvey147b5762016-05-24 11:03:59 -07001257
Tim Harveya1d32222016-07-15 07:16:28 -07001258 case GW53xx:
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001259 /* GW53xx-E adds WDOG1_B external reset */
1260 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001261 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001262 break;
Pushpal Sidhud1100562015-04-08 12:55:00 -07001263
Tim Harveya1d32222016-07-15 07:16:28 -07001264 case GW54xx:
1265 /*
1266 * disable serial2 node for GW54xx for compatibility with older
1267 * 3.10.x kernel that improperly had this node enabled in the DT
1268 */
Tim Harvey984aa0d2019-02-04 13:11:00 -08001269 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1270 0);
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001271
1272 /* GW54xx-E adds WDOG2_B external reset */
1273 if (rev < 'E')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001274 ft_board_wdog_fixup(blob, WDOG2_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001275 break;
1276
1277 case GW551x:
1278 /*
1279 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1280 * causing non functional digital video in (it is not hooked up)
1281 */
1282 if (rev == 'A') {
1283 u32 *range = NULL;
1284 int len;
1285 const u32 *handle = NULL;
1286
1287 i = fdt_node_offset_by_compatible(blob, -1,
1288 "fsl,imx-tda1997x-video");
1289 if (i)
1290 handle = fdt_getprop(blob, i, "pinctrl-0",
1291 NULL);
1292 if (handle)
1293 i = fdt_node_offset_by_phandle(blob,
1294 fdt32_to_cpu(*handle));
1295 if (i)
1296 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1297 &len);
1298 if (range) {
1299 len /= sizeof(u32);
1300 for (i = 0; i < len; i += 6) {
1301 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1302 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1303 /* mux PAD_CSI0_DATA_EN to GPIO */
1304 if (is_cpu_type(MXC_CPU_MX6Q) &&
1305 mux_reg == 0x260 &&
1306 conf_reg == 0x630)
1307 range[i+3] = cpu_to_fdt32(0x5);
1308 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1309 mux_reg == 0x08c &&
1310 conf_reg == 0x3a0)
1311 range[i+3] = cpu_to_fdt32(0x5);
1312 }
1313 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1314 len);
Tim Harvey6944ccf2015-04-08 12:54:53 -07001315 }
Tim Harveydc8b5e62015-04-08 12:55:02 -07001316
Tim Harveya1d32222016-07-15 07:16:28 -07001317 /* set BT656 video format */
1318 ft_sethdmiinfmt(blob, "yuv422bt656");
1319 }
Tim Harvey8d76d0d2016-07-15 07:16:29 -07001320
1321 /* GW551x-C adds WDOG1_B external reset */
1322 if (rev < 'C')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001323 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harveya1d32222016-07-15 07:16:28 -07001324 break;
Tim Harvey5852a332019-02-04 13:10:58 -08001325 case GW5901:
1326 case GW5902:
1327 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1328 if (rev < 'B')
Tim Harvey984aa0d2019-02-04 13:11:00 -08001329 ft_board_wdog_fixup(blob, WDOG1_ADDR);
Tim Harvey5852a332019-02-04 13:10:58 -08001330 break;
Tim Harvey6944ccf2015-04-08 12:54:53 -07001331 }
1332
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001333 /* Configure DIO */
Tim Harvey41595b52016-07-15 07:14:23 -07001334 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001335 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1336 char arg[10];
1337
1338 sprintf(arg, "dio%d", i);
1339 if (!hwconfig(arg))
1340 continue;
1341 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1342 {
Tim Harvey984aa0d2019-02-04 13:11:00 -08001343 phys_addr_t addr;
1344 int off;
1345
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001346 printf(" Enabling pwm%d for DIO%d\n",
1347 cfg->pwm_param, i);
Tim Harvey984aa0d2019-02-04 13:11:00 -08001348 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1349 off = fdt_node_offset_by_compat_reg(blob,
1350 "fsl,imx6q-pwm",
1351 addr);
1352 if (off)
1353 fdt_status_okay(blob, off);
Tim Harvey8d2d8df2016-05-24 11:03:55 -07001354 }
1355 }
1356
Tim Harvey147b5762016-05-24 11:03:59 -07001357 /* remove no-1-8-v if UHS-I support is present */
1358 if (gpio_cfg[board_type].usd_vsel) {
1359 debug("Enabling UHS-I support\n");
Tim Harvey984aa0d2019-02-04 13:11:00 -08001360 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1361 USDHC3_ADDR);
1362 if (i)
1363 fdt_delprop(blob, i, "no-1-8-v");
Tim Harvey147b5762016-05-24 11:03:59 -07001364 }
1365
Tim Harveybfb240a2016-06-17 06:10:41 -07001366#if defined(CONFIG_CMD_PCI)
Simon Glass64b723f2017-08-03 12:22:12 -06001367 if (!env_get("nopcifixup"))
Tim Harveybfb240a2016-06-17 06:10:41 -07001368 ft_board_pci_fixup(blob, bd);
1369#endif
1370
Tim Harvey6944ccf2015-04-08 12:54:53 -07001371 /*
Tim Harvey552c3582014-03-06 07:46:30 -08001372 * Peripheral Config:
1373 * remove nodes by alias path if EEPROM config tells us the
1374 * peripheral is not loaded on the board.
1375 */
Simon Glass64b723f2017-08-03 12:22:12 -06001376 if (env_get("fdt_noconfig")) {
Tim Harvey0da2c522014-08-07 22:35:45 -07001377 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
Simon Glass2aec3cc2014-10-23 18:58:47 -06001378 return 0;
Tim Harvey0da2c522014-08-07 22:35:45 -07001379 }
1380 cfg = econfig;
1381 while (cfg->name) {
1382 if (!test_bit(cfg->bit, info->config)) {
1383 fdt_del_node_and_alias(blob, cfg->dtalias ?
1384 cfg->dtalias : cfg->name);
1385 }
1386 cfg++;
Tim Harvey552c3582014-03-06 07:46:30 -08001387 }
Simon Glass2aec3cc2014-10-23 18:58:47 -06001388
1389 return 0;
Tim Harvey552c3582014-03-06 07:46:30 -08001390}
Robert P. J. Day3c757002016-05-19 15:23:12 -04001391#endif /* CONFIG_OF_BOARD_SETUP */
Tim Harvey552c3582014-03-06 07:46:30 -08001392
Simon Glassb75b15b2020-12-03 16:55:23 -07001393static struct mxc_serial_plat ventana_mxc_serial_plat = {
Tim Harvey67ed7922015-05-08 18:28:29 -07001394 .reg = (struct mxc_uart *)UART2_BASE,
1395};
1396
Simon Glass1d8364a2020-12-28 20:34:54 -07001397U_BOOT_DRVINFO(ventana_serial) = {
Tim Harvey67ed7922015-05-08 18:28:29 -07001398 .name = "serial_mxc",
Simon Glass71fa5b42020-12-03 16:55:18 -07001399 .plat = &ventana_mxc_serial_plat,
Tim Harvey67ed7922015-05-08 18:28:29 -07001400};