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git01.mediatek.com / filogic / uboot / 03f27e531ef215a517cda92b2883db606bda13ec / . / board / freescale / mx7ulp_evk / plugin.S
blob: 2cc93dbdd57c629f76a1092bc1af9b01c98ae99d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Ye Li79d3f922019-05-15 09:57:01 +0000[diff] [blame]4 * Copyright 2019 NXP
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]5 */
6
7#include <config.h>
8
9.macro imx7ulp_ddr_freq_decrease
10 ldr r2, =0x403f0000
11 ldr r3, =0x00000000
12 str r3, [r2, #0xdc]
13
14 ldr r2, =0x403e0000
15 ldr r3, =0x01000020
16 str r3, [r2, #0x40]
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]17 ldr r3, =0x01000000
18 str r3, [r2, #0x500]
Ye Li8fb27922019-05-15 09:56:51 +0000[diff] [blame]19
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]20 ldr r3, =0x80808080
21 str r3, [r2, #0x50c]
Ye Li15c80932019-05-15 09:56:59 +0000[diff] [blame]22 ldr r3, =0x00160002
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]23 str r3, [r2, #0x508]
Ye Li79d3f922019-05-15 09:57:01 +0000[diff] [blame]24 ldr r3, =0x00000001
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]25 str r3, [r2, #0x510]
Ye Li79d3f922019-05-15 09:57:01 +0000[diff] [blame]26 ldr r3, =0x00000014
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]27 str r3, [r2, #0x514]
28 ldr r3, =0x00000001
29 str r3, [r2, #0x500]
30
31 ldr r3, =0x01000000
32wait1:
33 ldr r4, [r2, #0x500]
34 and r4, r3
35 cmp r4, r3
36 bne wait1
37
Ye Li79d3f922019-05-15 09:57:01 +0000[diff] [blame]38 ldr r3, =0x8080801B
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]39 str r3, [r2, #0x50c]
40
41 ldr r3, =0x00000040
42wait2:
43 ldr r4, [r2, #0x50c]
44 and r4, r3
45 cmp r4, r3
46 bne wait2
47
48 ldr r3, =0x00000001
49 str r3, [r2, #0x30]
50 ldr r3, =0x11000020
51 str r3, [r2, #0x40]
52
53 ldr r2, =0x403f0000
54 ldr r3, =0x42000000
55 str r3, [r2, #0xdc]
56
57.endm
58
59.macro imx7ulp_evk_ddr_setting
60
61 imx7ulp_ddr_freq_decrease
62
63 /* Enable MMDC PCC clock */
64 ldr r2, =0x40b30000
65 ldr r3, =0x40000000
66 str r3, [r2, #0xac]
67
68 /* Configure DDR pad */
69 ldr r0, =0x40ad0000
70 ldr r1, =0x00040000
71 str r1, [r0, #0x128]
72 ldr r1, =0x0
73 str r1, [r0, #0xf8]
74 ldr r1, =0x00000180
75 str r1, [r0, #0xd8]
76 ldr r1, =0x00000180
77 str r1, [r0, #0x108]
78 ldr r1, =0x00000180
79 str r1, [r0, #0x104]
80 ldr r1, =0x00010000
81 str r1, [r0, #0x124]
82 ldr r1, =0x0000018C
83 str r1, [r0, #0x80]
84 ldr r1, =0x0000018C
85 str r1, [r0, #0x84]
86 ldr r1, =0x0000018C
87 str r1, [r0, #0x88]
88 ldr r1, =0x0000018C
89 str r1, [r0, #0x8c]
90
91 ldr r1, =0x00010000
92 str r1, [r0, #0x120]
93 ldr r1, =0x00000180
94 str r1, [r0, #0x10c]
95 ldr r1, =0x00000180
96 str r1, [r0, #0x110]
97 ldr r1, =0x00000180
98 str r1, [r0, #0x114]
99 ldr r1, =0x00000180
100 str r1, [r0, #0x118]
101 ldr r1, =0x00000180
102 str r1, [r0, #0x90]
103 ldr r1, =0x00000180
104 str r1, [r0, #0x94]
105 ldr r1, =0x00000180
106 str r1, [r0, #0x98]
107 ldr r1, =0x00000180
108 str r1, [r0, #0x9c]
109 ldr r1, =0x00040000
110 str r1, [r0, #0xe0]
111 ldr r1, =0x00040000
112 str r1, [r0, #0xe4]
113
114 ldr r0, =0x40ab0000
115 ldr r1, =0x00008000
116 str r1, [r0, #0x1c]
117 ldr r1, =0xA1390003
118 str r1, [r0, #0x800]
119 ldr r1, =0x0D3900A0
120 str r1, [r0, #0x85c]
121 ldr r1, =0x00400000
122 str r1, [r0, #0x890]
123
124 ldr r1, =0x40404040
125 str r1, [r0, #0x848]
126 ldr r1, =0x40404040
127 str r1, [r0, #0x850]
128 ldr r1, =0x33333333
129 str r1, [r0, #0x81c]
130 ldr r1, =0x33333333
131 str r1, [r0, #0x820]
132 ldr r1, =0x33333333
133 str r1, [r0, #0x824]
134 ldr r1, =0x33333333
135 str r1, [r0, #0x828]
136
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]137 ldr r1, =0x24922492
138 str r1, [r0, #0x8c0]
139 ldr r1, =0x00000800
140 str r1, [r0, #0x8b8]
141
142 ldr r1, =0x00020052
143 str r1, [r0, #0x4]
144 ldr r1, =0x292C42F3
145 str r1, [r0, #0xc]
146 ldr r1, =0x00100A22
147 str r1, [r0, #0x10]
148 ldr r1, =0x00120556
149 str r1, [r0, #0x38]
150 ldr r1, =0x00C700DB
151 str r1, [r0, #0x14]
152 ldr r1, =0x00211718
153 str r1, [r0, #0x18]
154
155 ldr r1, =0x0F9F26D2
156 str r1, [r0, #0x2c]
157 ldr r1, =0x009F0E10
158 str r1, [r0, #0x30]
159 ldr r1, =0x0000003F
160 str r1, [r0, #0x40]
161 ldr r1, =0xC3190000
162 str r1, [r0, #0x0]
163
Ye Li2ed2ecc2019-05-15 09:56:53 +0000[diff] [blame]164 ldr r1, =0x00008010
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]165 str r1, [r0, #0x1c]
Ye Li2ed2ecc2019-05-15 09:56:53 +0000[diff] [blame]166 ldr r1, =0x00008018
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]167 str r1, [r0, #0x1c]
168 ldr r1, =0x003F8030
169 str r1, [r0, #0x1c]
170 ldr r1, =0x003F8038
171 str r1, [r0, #0x1c]
172 ldr r1, =0xFF0A8030
173 str r1, [r0, #0x1c]
174 ldr r1, =0xFF0A8038
175 str r1, [r0, #0x1c]
176 ldr r1, =0x04028030
177 str r1, [r0, #0x1c]
178 ldr r1, =0x04028038
179 str r1, [r0, #0x1c]
180 ldr r1, =0x83018030
181 str r1, [r0, #0x1c]
182 ldr r1, =0x83018038
183 str r1, [r0, #0x1c]
184 ldr r1, =0x01038030
185 str r1, [r0, #0x1c]
186 ldr r1, =0x01038038
187 str r1, [r0, #0x1c]
188
189 ldr r1, =0x20000000
190 str r1, [r0, #0x83c]
191
192 ldr r1, =0x00001800
193 str r1, [r0, #0x20]
194 ldr r1, =0xA1310000
195 str r1, [r0, #0x800]
196 ldr r1, =0x00020052
197 str r1, [r0, #0x4]
198 ldr r1, =0x00011006
199 str r1, [r0, #0x404]
200 ldr r1, =0x00000000
201 str r1, [r0, #0x1c]
202
203.endm
204
205.macro imx7ulp_clock_gating
206.endm
207
208.macro imx7ulp_qos_setting
209.endm
210
211.macro imx7ulp_ddr_setting
212 imx7ulp_evk_ddr_setting
213.endm
214
215/* include the common plugin code here */
216#include <asm/arch/mx7ulp_plugin.S>