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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / board / freescale / mx7ulp_evk / plugin.S
blob: 082b2beaa3c78e451151d885999360d474232c02 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]4 */
5
6#include <config.h>
7
8.macro imx7ulp_ddr_freq_decrease
9 ldr r2, =0x403f0000
10 ldr r3, =0x00000000
11 str r3, [r2, #0xdc]
12
13 ldr r2, =0x403e0000
14 ldr r3, =0x01000020
15 str r3, [r2, #0x40]
16 ldr r3, =0x01000000
17 str r3, [r2, #0x500]
18 ldr r3, =0x80808080
19 str r3, [r2, #0x50c]
20 ldr r3, =0x00140000
21 str r3, [r2, #0x508]
22 ldr r3, =0x00000004
23 str r3, [r2, #0x510]
24 ldr r3, =0x00000002
25 str r3, [r2, #0x514]
26 ldr r3, =0x00000001
27 str r3, [r2, #0x500]
28
29 ldr r3, =0x01000000
30wait1:
31 ldr r4, [r2, #0x500]
32 and r4, r3
33 cmp r4, r3
34 bne wait1
35
36 ldr r3, =0x8080801E
37 str r3, [r2, #0x50c]
38
39 ldr r3, =0x00000040
40wait2:
41 ldr r4, [r2, #0x50c]
42 and r4, r3
43 cmp r4, r3
44 bne wait2
45
46 ldr r3, =0x00000001
47 str r3, [r2, #0x30]
48 ldr r3, =0x11000020
49 str r3, [r2, #0x40]
50
51 ldr r2, =0x403f0000
52 ldr r3, =0x42000000
53 str r3, [r2, #0xdc]
54
55.endm
56
57.macro imx7ulp_evk_ddr_setting
58
59 imx7ulp_ddr_freq_decrease
60
61 /* Enable MMDC PCC clock */
62 ldr r2, =0x40b30000
63 ldr r3, =0x40000000
64 str r3, [r2, #0xac]
65
66 /* Configure DDR pad */
67 ldr r0, =0x40ad0000
68 ldr r1, =0x00040000
69 str r1, [r0, #0x128]
70 ldr r1, =0x0
71 str r1, [r0, #0xf8]
72 ldr r1, =0x00000180
73 str r1, [r0, #0xd8]
74 ldr r1, =0x00000180
75 str r1, [r0, #0x108]
76 ldr r1, =0x00000180
77 str r1, [r0, #0x104]
78 ldr r1, =0x00010000
79 str r1, [r0, #0x124]
80 ldr r1, =0x0000018C
81 str r1, [r0, #0x80]
82 ldr r1, =0x0000018C
83 str r1, [r0, #0x84]
84 ldr r1, =0x0000018C
85 str r1, [r0, #0x88]
86 ldr r1, =0x0000018C
87 str r1, [r0, #0x8c]
88
89 ldr r1, =0x00010000
90 str r1, [r0, #0x120]
91 ldr r1, =0x00000180
92 str r1, [r0, #0x10c]
93 ldr r1, =0x00000180
94 str r1, [r0, #0x110]
95 ldr r1, =0x00000180
96 str r1, [r0, #0x114]
97 ldr r1, =0x00000180
98 str r1, [r0, #0x118]
99 ldr r1, =0x00000180
100 str r1, [r0, #0x90]
101 ldr r1, =0x00000180
102 str r1, [r0, #0x94]
103 ldr r1, =0x00000180
104 str r1, [r0, #0x98]
105 ldr r1, =0x00000180
106 str r1, [r0, #0x9c]
107 ldr r1, =0x00040000
108 str r1, [r0, #0xe0]
109 ldr r1, =0x00040000
110 str r1, [r0, #0xe4]
111
112 ldr r0, =0x40ab0000
113 ldr r1, =0x00008000
114 str r1, [r0, #0x1c]
115 ldr r1, =0xA1390003
116 str r1, [r0, #0x800]
117 ldr r1, =0x0D3900A0
118 str r1, [r0, #0x85c]
119 ldr r1, =0x00400000
120 str r1, [r0, #0x890]
121
122 ldr r1, =0x40404040
123 str r1, [r0, #0x848]
124 ldr r1, =0x40404040
125 str r1, [r0, #0x850]
126 ldr r1, =0x33333333
127 str r1, [r0, #0x81c]
128 ldr r1, =0x33333333
129 str r1, [r0, #0x820]
130 ldr r1, =0x33333333
131 str r1, [r0, #0x824]
132 ldr r1, =0x33333333
133 str r1, [r0, #0x828]
134
135 ldr r1, =0xf3333333
136 str r1, [r0, #0x82c]
137 ldr r1, =0xf3333333
138 str r1, [r0, #0x830]
139 ldr r1, =0xf3333333
140 str r1, [r0, #0x834]
141 ldr r1, =0xf3333333
142 str r1, [r0, #0x838]
143
144 ldr r1, =0x24922492
145 str r1, [r0, #0x8c0]
146 ldr r1, =0x00000800
147 str r1, [r0, #0x8b8]
148
149 ldr r1, =0x00020052
150 str r1, [r0, #0x4]
151 ldr r1, =0x292C42F3
152 str r1, [r0, #0xc]
153 ldr r1, =0x00100A22
154 str r1, [r0, #0x10]
155 ldr r1, =0x00120556
156 str r1, [r0, #0x38]
157 ldr r1, =0x00C700DB
158 str r1, [r0, #0x14]
159 ldr r1, =0x00211718
160 str r1, [r0, #0x18]
161
162 ldr r1, =0x0F9F26D2
163 str r1, [r0, #0x2c]
164 ldr r1, =0x009F0E10
165 str r1, [r0, #0x30]
166 ldr r1, =0x0000003F
167 str r1, [r0, #0x40]
168 ldr r1, =0xC3190000
169 str r1, [r0, #0x0]
170
171 ldr r1, =0x00008050
172 str r1, [r0, #0x1c]
173 ldr r1, =0x00008058
174 str r1, [r0, #0x1c]
175 ldr r1, =0x003F8030
176 str r1, [r0, #0x1c]
177 ldr r1, =0x003F8038
178 str r1, [r0, #0x1c]
179 ldr r1, =0xFF0A8030
180 str r1, [r0, #0x1c]
181 ldr r1, =0xFF0A8038
182 str r1, [r0, #0x1c]
183 ldr r1, =0x04028030
184 str r1, [r0, #0x1c]
185 ldr r1, =0x04028038
186 str r1, [r0, #0x1c]
187 ldr r1, =0x83018030
188 str r1, [r0, #0x1c]
189 ldr r1, =0x83018038
190 str r1, [r0, #0x1c]
191 ldr r1, =0x01038030
192 str r1, [r0, #0x1c]
193 ldr r1, =0x01038038
194 str r1, [r0, #0x1c]
195
196 ldr r1, =0x20000000
197 str r1, [r0, #0x83c]
198
199 ldr r1, =0x00001800
200 str r1, [r0, #0x20]
201 ldr r1, =0xA1310000
202 str r1, [r0, #0x800]
203 ldr r1, =0x00020052
204 str r1, [r0, #0x4]
205 ldr r1, =0x00011006
206 str r1, [r0, #0x404]
207 ldr r1, =0x00000000
208 str r1, [r0, #0x1c]
209
210.endm
211
212.macro imx7ulp_clock_gating
213.endm
214
215.macro imx7ulp_qos_setting
216.endm
217
218.macro imx7ulp_ddr_setting
219 imx7ulp_evk_ddr_setting
220.endm
221
222/* include the common plugin code here */
223#include <asm/arch/mx7ulp_plugin.S>