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git01.mediatek.com / filogic / uboot / 15c80933f5d5355f12512d1b4fdacf9d22940e1b / . / board / freescale / mx7ulp_evk / plugin.S
blob: 55dfecc751220e3a171f74e837e77cc5366c2dac [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]4 */
5
6#include <config.h>
7
8.macro imx7ulp_ddr_freq_decrease
9 ldr r2, =0x403f0000
10 ldr r3, =0x00000000
11 str r3, [r2, #0xdc]
12
13 ldr r2, =0x403e0000
14 ldr r3, =0x01000020
15 str r3, [r2, #0x40]
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]16 ldr r3, =0x01000000
17 str r3, [r2, #0x500]
Ye Li8fb27922019-05-15 09:56:51 +0000[diff] [blame]18
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]19 ldr r3, =0x80808080
20 str r3, [r2, #0x50c]
Ye Li15c80932019-05-15 09:56:59 +0000[diff] [blame^]21 ldr r3, =0x00160002
Ye Li87cff102019-05-15 09:56:56 +0000[diff] [blame]22 str r3, [r2, #0x508]
23 ldr r3, =0x00000002
24 str r3, [r2, #0x510]
25 ldr r3, =0x00000005
26 str r3, [r2, #0x514]
27 ldr r3, =0x00000001
28 str r3, [r2, #0x500]
29
30 ldr r3, =0x01000000
31wait1:
32 ldr r4, [r2, #0x500]
33 and r4, r3
34 cmp r4, r3
35 bne wait1
36
37 ldr r3, =0x80808020
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]38 str r3, [r2, #0x50c]
39
40 ldr r3, =0x00000040
41wait2:
42 ldr r4, [r2, #0x50c]
43 and r4, r3
44 cmp r4, r3
45 bne wait2
46
47 ldr r3, =0x00000001
48 str r3, [r2, #0x30]
49 ldr r3, =0x11000020
50 str r3, [r2, #0x40]
51
52 ldr r2, =0x403f0000
53 ldr r3, =0x42000000
54 str r3, [r2, #0xdc]
55
56.endm
57
58.macro imx7ulp_evk_ddr_setting
59
60 imx7ulp_ddr_freq_decrease
61
62 /* Enable MMDC PCC clock */
63 ldr r2, =0x40b30000
64 ldr r3, =0x40000000
65 str r3, [r2, #0xac]
66
67 /* Configure DDR pad */
68 ldr r0, =0x40ad0000
69 ldr r1, =0x00040000
70 str r1, [r0, #0x128]
71 ldr r1, =0x0
72 str r1, [r0, #0xf8]
73 ldr r1, =0x00000180
74 str r1, [r0, #0xd8]
75 ldr r1, =0x00000180
76 str r1, [r0, #0x108]
77 ldr r1, =0x00000180
78 str r1, [r0, #0x104]
79 ldr r1, =0x00010000
80 str r1, [r0, #0x124]
81 ldr r1, =0x0000018C
82 str r1, [r0, #0x80]
83 ldr r1, =0x0000018C
84 str r1, [r0, #0x84]
85 ldr r1, =0x0000018C
86 str r1, [r0, #0x88]
87 ldr r1, =0x0000018C
88 str r1, [r0, #0x8c]
89
90 ldr r1, =0x00010000
91 str r1, [r0, #0x120]
92 ldr r1, =0x00000180
93 str r1, [r0, #0x10c]
94 ldr r1, =0x00000180
95 str r1, [r0, #0x110]
96 ldr r1, =0x00000180
97 str r1, [r0, #0x114]
98 ldr r1, =0x00000180
99 str r1, [r0, #0x118]
100 ldr r1, =0x00000180
101 str r1, [r0, #0x90]
102 ldr r1, =0x00000180
103 str r1, [r0, #0x94]
104 ldr r1, =0x00000180
105 str r1, [r0, #0x98]
106 ldr r1, =0x00000180
107 str r1, [r0, #0x9c]
108 ldr r1, =0x00040000
109 str r1, [r0, #0xe0]
110 ldr r1, =0x00040000
111 str r1, [r0, #0xe4]
112
113 ldr r0, =0x40ab0000
114 ldr r1, =0x00008000
115 str r1, [r0, #0x1c]
116 ldr r1, =0xA1390003
117 str r1, [r0, #0x800]
118 ldr r1, =0x0D3900A0
119 str r1, [r0, #0x85c]
120 ldr r1, =0x00400000
121 str r1, [r0, #0x890]
122
123 ldr r1, =0x40404040
124 str r1, [r0, #0x848]
125 ldr r1, =0x40404040
126 str r1, [r0, #0x850]
127 ldr r1, =0x33333333
128 str r1, [r0, #0x81c]
129 ldr r1, =0x33333333
130 str r1, [r0, #0x820]
131 ldr r1, =0x33333333
132 str r1, [r0, #0x824]
133 ldr r1, =0x33333333
134 str r1, [r0, #0x828]
135
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]136 ldr r1, =0x24922492
137 str r1, [r0, #0x8c0]
138 ldr r1, =0x00000800
139 str r1, [r0, #0x8b8]
140
141 ldr r1, =0x00020052
142 str r1, [r0, #0x4]
143 ldr r1, =0x292C42F3
144 str r1, [r0, #0xc]
145 ldr r1, =0x00100A22
146 str r1, [r0, #0x10]
147 ldr r1, =0x00120556
148 str r1, [r0, #0x38]
149 ldr r1, =0x00C700DB
150 str r1, [r0, #0x14]
151 ldr r1, =0x00211718
152 str r1, [r0, #0x18]
153
154 ldr r1, =0x0F9F26D2
155 str r1, [r0, #0x2c]
156 ldr r1, =0x009F0E10
157 str r1, [r0, #0x30]
158 ldr r1, =0x0000003F
159 str r1, [r0, #0x40]
160 ldr r1, =0xC3190000
161 str r1, [r0, #0x0]
162
Ye Li2ed2ecc2019-05-15 09:56:53 +0000[diff] [blame]163 ldr r1, =0x00008010
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]164 str r1, [r0, #0x1c]
Ye Li2ed2ecc2019-05-15 09:56:53 +0000[diff] [blame]165 ldr r1, =0x00008018
Peng Fanf7765d72017-02-22 16:21:56 +0800[diff] [blame]166 str r1, [r0, #0x1c]
167 ldr r1, =0x003F8030
168 str r1, [r0, #0x1c]
169 ldr r1, =0x003F8038
170 str r1, [r0, #0x1c]
171 ldr r1, =0xFF0A8030
172 str r1, [r0, #0x1c]
173 ldr r1, =0xFF0A8038
174 str r1, [r0, #0x1c]
175 ldr r1, =0x04028030
176 str r1, [r0, #0x1c]
177 ldr r1, =0x04028038
178 str r1, [r0, #0x1c]
179 ldr r1, =0x83018030
180 str r1, [r0, #0x1c]
181 ldr r1, =0x83018038
182 str r1, [r0, #0x1c]
183 ldr r1, =0x01038030
184 str r1, [r0, #0x1c]
185 ldr r1, =0x01038038
186 str r1, [r0, #0x1c]
187
188 ldr r1, =0x20000000
189 str r1, [r0, #0x83c]
190
191 ldr r1, =0x00001800
192 str r1, [r0, #0x20]
193 ldr r1, =0xA1310000
194 str r1, [r0, #0x800]
195 ldr r1, =0x00020052
196 str r1, [r0, #0x4]
197 ldr r1, =0x00011006
198 str r1, [r0, #0x404]
199 ldr r1, =0x00000000
200 str r1, [r0, #0x1c]
201
202.endm
203
204.macro imx7ulp_clock_gating
205.endm
206
207.macro imx7ulp_qos_setting
208.endm
209
210.macro imx7ulp_ddr_setting
211 imx7ulp_evk_ddr_setting
212.endm
213
214/* include the common plugin code here */
215#include <asm/arch/mx7ulp_plugin.S>