| commit | 15c80933f5d5355f12512d1b4fdacf9d22940e1b | [log] [tgz] |
|---|---|---|
| author | Ye Li <ye.li@nxp.com> | Wed May 15 09:56:59 2019 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Fri Jul 19 20:14:50 2019 +0200 |
| tree | 2427c80f845acaaaca1c198f46f06fa63c89a0c2 | |
| parent | 87cff10f328303c3868c3c3f73a5f64b053fea72 [diff] |
mx7ulp: Select the SCG1 APLL PFD as a system clock source Due to the APLL out glitch issue, the APLLCFG PLLS bit must be set to select SCG1 APLL PFD for generating system clock to align with the design. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>