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git01.mediatek.com / filogic / uboot / 035939ee7119fc39c2e1cbaab44e1502fd37d504 / . / arch / m68k / cpu / mcf5445x / start.S
blob: 7007d78c83faafd5fc9f87e581036587bef6636a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]6 * Copyright 2010-2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]8 */
9
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]10#include <common.h>
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]11#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]12#include <config.h>
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]13#include <timestamp.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]14#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]15#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]16
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]17#define _START _start
18#define _FAULT _fault
19
20#define SAVE_ALL \
21 move.w #0x2700,%sr; /* disable intrs */ \
22 subl #60,%sp; /* space for 15 regs */ \
23 moveml %d0-%d7/%a0-%a6,%sp@;
24
25#define RESTORE_ALL \
26 moveml %sp@,%d0-%d7/%a0-%a6; \
27 addl #60,%sp; /* space for 15 regs */ \
28 rte;
29
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]30#if defined(CONFIG_SERIAL_BOOT)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]31#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
32 CONFIG_SYS_INIT_RAM_ADDR)
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]33#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]34#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
35 CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]36#endif
37
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]38.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]39
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]40/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]41 * Vector table. This is used for initial platform startup.
42 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]43 */
44_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]45#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]46
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]47INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]48#ifdef CONFIG_CF_SBF
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]49INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]50#endif
51#ifdef CONFIG_SYS_NAND_BOOT
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]52INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]53#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]54
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]55#else
56
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]57INITSP: .long 0 /* Initial SP */
58INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]59
60#endif
61
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]62vector02_0F:
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]65
66/* Reserved */
67vector10_17:
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]70vector18_1F:
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]72
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]73#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]74
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]75/* TRAP #0 - #15 */
76vector20_2F:
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79
80/* Reserved */
81vector30_3F:
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85vector64_127:
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94
95vector128_191:
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104
105vector192_255:
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]114#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]115
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]116#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]117 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
118asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]119 .long 0x00000000 /* checksum, not yet implemented */
120 .long 0x00040000 /* image length */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]121 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]122
123asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]124 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]125
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]126#ifdef CONFIG_SYS_NAND_BOOT
127 /* for assembly stack */
128 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
129 movec %d0, %RAMBAR1
130
131 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]132 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]133#endif
134
135#ifdef CONFIG_CF_SBF
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]136 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
137 movec %d0, %VBR
138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]139 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]140 movec %d0, %RAMBAR1
141
142 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]143 move.l #0, %d0
144 move.l #(ICACHE_STATUS), %a1 /* icache */
145 move.l #(DCACHE_STATUS), %a2 /* dcache */
146 move.l %d0, (%a1)
147 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]148
149 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]150 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]151 movec %d0, %CACR /* Invalidate cache */
152 move.l #0, %d0
153 movec %d0, %ACR0
154 movec %d0, %ACR1
155 movec %d0, %ACR2
156 movec %d0, %ACR3
157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]158 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]159 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]160
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]161#ifdef CONFIG_SYS_CS0_BASE
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]162 /* Must disable global address */
163 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]164 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]165 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]167 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]168 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]169#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]170#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]171
172#ifdef CONFIG_MCF5441x
173 /* TC: enable all peripherals,
174 in the future only enable certain peripherals */
175 move.l #0xFC04002D, %a1
176
177#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]178 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]179#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]180#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]181
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]182 /* mandatory board level ddr-sdram init,
183 * for both 5441x and 5445x
184 */
185 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]186
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]187#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]188 /*
189 * DSPI Initialization
190 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
191 * a1 - dspi status
192 * a2 - dtfr
193 * a3 - drfr
194 * a4 - Dst addr
195 */
196 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]197asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]198#ifdef CONFIG_MCF5441x
199 move.l #0xEC09404E, %a1
200 move.l #0xEC09404F, %a2
201 move.b #0xFF, (%a1)
202 move.b #0x80, (%a2)
203#endif
204
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]205 /* Configure DSPI module */
206 move.l #0xFC05C000, %a0
207 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
208
209 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]210#ifdef CONFIG_MCF5441x
211 move.l #0x3E000016, (%a0)
212#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]213
214 move.l #0xFC05C034, %a2 /* dtfr */
215 move.l #0xFC05C03B, %a3 /* drfr */
216
217 move.l #(ASM_SBF_IMG_HDR + 4), %a1
218 move.l (%a1)+, %d5
219 move.l (%a1), %a4
220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]221 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
222 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]223
224 move.l #0xFC05C02C, %a1 /* dspi status */
225
226 /* Issue commands and address */
227 move.l #0x8002000B, %d2 /* Fast Read Cmd */
228 jsr asm_dspi_wr_status
229 jsr asm_dspi_rd_status
230
231 move.l #0x80020000, %d2 /* Address byte 2 */
232 jsr asm_dspi_wr_status
233 jsr asm_dspi_rd_status
234
235 move.l #0x80020000, %d2 /* Address byte 1 */
236 jsr asm_dspi_wr_status
237 jsr asm_dspi_rd_status
238
239 move.l #0x80020000, %d2 /* Address byte 0 */
240 jsr asm_dspi_wr_status
241 jsr asm_dspi_rd_status
242
243 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
244 jsr asm_dspi_wr_status
245 jsr asm_dspi_rd_status
246
247 /* Transfer serial boot header to sram */
248asm_dspi_rd_loop1:
249 move.l #0x80020000, %d2
250 jsr asm_dspi_wr_status
251 jsr asm_dspi_rd_status
252
253 move.b %d1, (%a0) /* read, copy to dst */
254
255 add.l #1, %a0 /* inc dst by 1 */
256 sub.l #1, %d4 /* dec cnt by 1 */
257 bne asm_dspi_rd_loop1
258
259 /* Transfer u-boot from serial flash to memory */
260asm_dspi_rd_loop2:
261 move.l #0x80020000, %d2
262 jsr asm_dspi_wr_status
263 jsr asm_dspi_rd_status
264
265 move.b %d1, (%a4) /* read, copy to dst */
266
267 add.l #1, %a4 /* inc dst by 1 */
268 sub.l #1, %d5 /* dec cnt by 1 */
269 bne asm_dspi_rd_loop2
270
271 move.l #0x00020000, %d2 /* Terminate */
272 jsr asm_dspi_wr_status
273 jsr asm_dspi_rd_status
274
275 /* jump to memory and execute */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]276 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]277 jmp (%a0)
278
279asm_dspi_wr_status:
280 move.l (%a1), %d0 /* status */
281 and.l #0x0000F000, %d0
282 cmp.l #0x00003000, %d0
283 bgt asm_dspi_wr_status
284
285 move.l %d2, (%a2)
286 rts
287
288asm_dspi_rd_status:
289 move.l (%a1), %d0 /* status */
290 and.l #0x000000F0, %d0
291 lsr.l #4, %d0
292 cmp.l #0, %d0
293 beq asm_dspi_rd_status
294
295 move.b (%a3), %d1
296 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]297#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]298
299#ifdef CONFIG_SYS_NAND_BOOT
300 /* copy 4 boot pages to dram as soon as possible */
301 /* each page is 996 bytes (1056 total with 60 ECC bytes */
302 move.l #0x00000000, %a1 /* src */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]303 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]304 move.l #0x3E0, %d0 /* sz in long */
305
306asm_boot_nand_copy:
307 move.l (%a1)+, (%a2)+
308 subq.l #1, %d0
309 bne asm_boot_nand_copy
310
311 /* jump to memory and execute */
312 move.l #(asm_nand_init), %a0
313 jmp (%a0)
314
315asm_nand_init:
316 /* exit nand boot-mode */
317 move.l #0xFC0FFF30, %a1
318 or.l #0x00000040, %d1
319 move.l %d1, (%a1)
320
321 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]322 move.l #0, %d0
323 move.l #(CACR_STATUS), %a1 /* CACR */
324 move.l #(ICACHE_STATUS), %a2 /* icache */
325 move.l #(DCACHE_STATUS), %a3 /* dcache */
326 move.l %d0, (%a1)
327 move.l %d0, (%a2)
328 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]329
330 /* invalidate and disable cache */
331 move.l #0x01004100, %d0 /* Invalidate cache cmd */
332 movec %d0, %CACR /* Invalidate cache */
333 move.l #0, %d0
334 movec %d0, %ACR0
335 movec %d0, %ACR1
336 movec %d0, %ACR2
337 movec %d0, %ACR3
338
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]339#ifdef CONFIG_SYS_CS0_BASE
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]340 /* Must disable global address */
341 move.l #0xFC008000, %a1
342 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
343 move.l #0xFC008008, %a1
344 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
345 move.l #0xFC008004, %a1
346 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]347#endif
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]348
349 /* NAND port configuration */
350 move.l #0xEC094048, %a1
351 move.b #0xFD, (%a1)+
352 move.b #0x5F, (%a1)+
353 move.b #0x04, (%a1)+
354
355 /* reset nand */
356 move.l #0xFC0FFF38, %a1 /* isr */
357 move.l #0x000e0000, (%a1)
358 move.l #0xFC0FFF08, %a2
359 move.l #0x00000000, (%a2)+ /* car */
360 move.l #0x11000000, (%a2)+ /* rar */
361 move.l #0x00000000, (%a2)+ /* rpt */
362 move.l #0x00000000, (%a2)+ /* rai */
363 move.l #0xFC0FFF2c, %a2 /* cfg */
364 move.l #0x00000000, (%a2)+ /* secsz */
365 move.l #0x000e0681, (%a2)+
366 move.l #0xFC0FFF04, %a2 /* cmd2 */
367 move.l #0xFF404001, (%a2)
368 move.l #0x000e0000, (%a1)
369
370 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]371 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]372
373 /* setup nand */
374 move.l #0xFC0FFF00, %a1
375 move.l #0x30700000, (%a1)+ /* cmd1 */
376 move.l #0x007EF000, (%a1)+ /* cmd2 */
377
378 move.l #0xFC0FFF2C, %a1
379 move.l #0x00000841, (%a1)+ /* secsz */
380 move.l #0x000e0681, (%a1)+ /* cfg */
381
382 move.l #100, %d4 /* 100 pages ~200KB */
383 move.l #4, %d2 /* start at 4 */
384 move.l #0xFC0FFF04, %a0 /* cmd2 */
385 move.l #0xFC0FFF0C, %a1 /* rar */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]386 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]387
388asm_nand_read:
389 move.l #0x11000000, %d0 /* rar */
390 or.l %d2, %d0
391 move.l %d0, (%a1)
392 add.l #1, %d2
393
394 move.l (%a0), %d0 /* cmd2 */
395 or.l #1, %d0
396 move.l %d0, (%a0)
397
398 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]399 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]400
401asm_nand_chk_status:
402 move.l #0xFC0FFF38, %a4 /* isr */
403 move.l (%a4), %d0
404 and.l #0x40000000, %d0
405 tst.l %d0
406 beq asm_nand_chk_status
407
408 move.l #0xFC0FFF38, %a4 /* isr */
409 move.l (%a4), %d0
410 or.l #0x000E0000, %d0
411 move.l %d0, (%a4)
412
413 move.l #0x200, %d3
414 move.l #0xFC0FC000, %a3 /* buf 1 */
415asm_nand_copy:
416 move.l (%a3)+, (%a2)+
417 subq.l #1, %d3
418 bgt asm_nand_copy
419
420 subq.l #1, %d4
421 bgt asm_nand_read
422
423 /* jump to memory and execute */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]424 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]425 jmp (%a0)
426
427#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]428
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]429.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]430asm_delay:
431 nop
432 subq.l #1, %d1
433 bne asm_delay
434 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]435#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]436
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]437.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]438 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]439.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]440_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]441#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]442 nop
443 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]444 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]445
446 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]447 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]448 movec %d0, %VBR
449
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]450 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]451 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]452
453 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]454 move.l #0, %d0
455 move.l #(ICACHE_STATUS), %a1 /* icache */
456 move.l #(DCACHE_STATUS), %a2 /* dcache */
457 move.l %d0, (%a1)
458 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]459
460 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]461 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]462 movec %d0, %CACR /* Invalidate cache */
463 move.l #0, %d0
464 movec %d0, %ACR0
465 movec %d0, %ACR1
466 movec %d0, %ACR2
467 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]468#else
469 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
470 movec %d0, %RAMBAR1
471#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]472
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]473 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]474 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]475
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]476 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]477 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]478
479 /*
480 * if configured, malloc_f arena will be reserved first,
481 * then (and always) gd struct space will be reserved
482 */
483 move.l %sp, -(%sp)
484 move.l #board_init_f_alloc_reserve, %a1
485 jsr (%a1)
486
487 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]488 move.l %d0, %sp
489 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]490
491 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]492 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]493 move.l #board_init_f_init_reserve, %a1
494 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]495
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]496 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]497 move.l #cpu_init_f, %a1
498 jsr (%a1)
499
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]500 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]501 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]502 move.l #board_init_f, %a1
503 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]504
505 /* board_init_f() does not return */
506
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]507/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]508
509/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]510 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]511 *
512 * This "function" does not return, instead it continues in RAM
513 * after relocating the monitor code.
514 *
515 * r3 = dest
516 * r4 = src
517 * r5 = length in bytes
518 * r6 = cachelinesize
519 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]520.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]521relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]522 link.w %a6,#0
523 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]524
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]525 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
526 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]527
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]528 move.l #CONFIG_SYS_MONITOR_BASE, %a1
529 move.l #__init_end, %a2
530 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]531
532 /* copy the code to RAM */
5331:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]534 move.l (%a1)+, (%a3)+
535 cmp.l %a1,%a2
536 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]537
538/*
539 * We are done. Do not return, instead branch to second part of board
540 * initialization, now running from RAM.
541 */
542 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]543 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]544 jmp (%a1)
545
546in_ram:
547
548clear_bss:
549 /*
550 * Now clear BSS segment
551 */
552 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]553 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]554 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]555 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5566:
557 clr.l (%a1)+
558 cmp.l %a1,%d1
559 bgt.s 6b
560
561 /*
562 * fix got table in RAM
563 */
564 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]565 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]566 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]567
568 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]569 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]570
5717:
572 move.l (%a1),%d1
573 sub.l #_start,%d1
574 add.l %a0,%d1
575 move.l %d1,(%a1)+
576 cmp.l %a2, %a1
577 bne 7b
578
579 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]580 move.l %a0, %a1
581 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]582
583 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]584 move.l %a0,-(%sp) /* dest_addr */
585 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]586 jsr (%a1)
587
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]588/******************************************************************************/
589
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]590/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]591.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]592_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]593 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]594
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]595.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]596_exc_handler:
597 SAVE_ALL
598 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]599 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]600 addql #4,%sp
601 RESTORE_ALL
602
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]603.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]604_int_handler:
605 SAVE_ALL
606 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]607 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]608 addql #4,%sp
609 RESTORE_ALL
610
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]611/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]612
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]613.globl version_string
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]614version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]615.ascii U_BOOT_VERSION_STRING, "\0"
616.align 4