Merge patch series "Add Android 14 bootflow support for AM62X and AM62P board"
Guillaume La Roque <glaroque@baylibre.com> says:
Ths patchset add support of Android 14 with boot image version 4
for :
- AM62X-SK EVM: https://www.ti.com/tool/SK-AM62B
- BeaglePlay: https://beagleplay.org/
- AM62PX-SK EVM: https://www.ti.com/tool/SK-AM62P-LP
Android Images use to test this series are on the Official TI website:
- AM62x/BeaglePlay: https://www.ti.com/tool/PROCESSOR-SDK-AM62X
- AM62PX: https://www.ti.com/tool/PROCESSOR-SDK-AM62P
diff --git a/Kconfig b/Kconfig
index 82df59f..ab46b27 100644
--- a/Kconfig
+++ b/Kconfig
@@ -1,6 +1,6 @@
#
# For a description of the syntax of this configuration file,
-# see the file Documentation/kbuild/kconfig-language.txt in the
+# see the file Documentation/kbuild/kconfig-language.rst in the
# Linux kernel source tree.
#
mainmenu "U-Boot $(UBOOTVERSION) Configuration"
@@ -209,6 +209,7 @@
config NR_DRAM_BANKS
int "Number of DRAM banks"
default 1 if ARCH_SUNXI || ARCH_OWL
+ default 2 if OMAP34XX
default 4
help
This defines the number of DRAM banks.
@@ -236,6 +237,7 @@
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
+ default y if OMAP34XX || AM33XX || AM43XX || DRA7XX
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
@@ -249,6 +251,10 @@
config CUSTOM_SYS_INIT_SP_ADDR
hex "Static location for the initial stack pointer"
depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
+ default 0x4020ff00 if OMAP34XX
+ default 0x4030ff00 if AM33XX
+ default 0x4033ff00 if AM43XX
+ default 0x4037ff00 if DRA7XX
default TEXT_BASE if TFABOOT
config SYS_MALLOC_F
@@ -615,6 +621,7 @@
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
+ default 262144 if OMAP34XX
default 786432 if ARCH_SUNXI
default 0
help
diff --git a/MAINTAINERS b/MAINTAINERS
index 2050ae2..7ab39d9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -617,6 +617,7 @@
L: u-boot-qcom@groups.io
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git
+F: configs/qcm6490_defconfig
F: drivers/*/*/pm8???-*
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
@@ -1711,6 +1712,19 @@
S: Maintained
F: drivers/ufs/
+UPL
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-dm.git
+F: boot/upl*
+F: cmd/upl.c
+F: common/spl/spl_upl.c
+F: doc/usage/upl.rst
+F: doc/usage/cmd/upl.rst
+F: include/upl.h
+F: test/boot/upl.c
+F: test/py/tests/test_upl.py
+
USB
M: Marek Vasut <marex@denx.de>
S: Maintained
diff --git a/Makefile b/Makefile
index f90e48f..8711831 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc6
NAME =
# *DOCUMENTATION*
@@ -1473,8 +1473,10 @@
u-boot-lzma.img: u-boot.bin.lzma FORCE
$(call if_changed,mkimage)
+fit_image := $(if $(CONFIG_SANDBOX_VPL),u-boot,u-boot-nodtb.bin)
+
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
- $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+ $(if $(CONFIG_SPL_LOAD_FIT),$(fit_image) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
diff --git a/README b/README
index b76449b..4be1e8c 100644
--- a/README
+++ b/README
@@ -771,21 +771,8 @@
CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
- CFG_SYS_I2C_DIRECT_BUS
- define this, if you don't use i2c muxes on your hardware.
- if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
- omit this define.
-
- CFG_SYS_I2C_MAX_HOPS
- define how many muxes are maximal consecutively connected
- on one i2c bus. If you not use i2c muxes, omit this
- define.
-
CFG_SYS_I2C_BUSES
- hold a list of buses you want to use, only used if
- CFG_SYS_I2C_DIRECT_BUS is not defined, for example
- a board with CFG_SYS_I2C_MAX_HOPS = 1 and
- CFG_SYS_NUM_I2C_BUSES = 9:
+ hold a list of buses you want to use
CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
@@ -883,13 +870,6 @@
You should define these to the GPIO value as given directly to
the generic GPIO functions.
- CFG_I2C_MULTI_BUS
-
- This option allows the use of multiple I2C buses, each of which
- must have a controller. At any point in time, only one bus is
- active. To switch to a different bus, use the 'i2c dev' command.
- Note that bus numbering is zero-based.
-
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
@@ -900,11 +880,6 @@
will skip addresses 0x50 and 0x68 on a board with one I2C bus
- CFG_SYS_RTC_BUS_NUM
-
- If defined, then this indicates the I2C bus number for the RTC.
- If not defined, then U-Boot assumes that RTC is on I2C bus 0.
-
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 22e7488..5169fc6 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -10,7 +10,6 @@
#include <linux/compiler.h>
#include <linux/kernel.h>
#include <linux/log2.h>
-#include <lmb.h>
#include <asm/arcregs.h>
#include <asm/arc-bcr.h>
#include <asm/cache.h>
@@ -820,16 +819,3 @@
__ic_entire_invalidate();
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba0359f..656f588 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -802,7 +802,7 @@
bool "TI OMAP2+"
select CPU_V7A
select GPIO_EXTRA_HEADER
- select SPL_BOARD_INIT if SPL
+ select SPL_SOC_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
imply TI_SYSC if DM && OF_CONTROL
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 76a69d7..dd74832 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -117,7 +117,7 @@
gd->bd = &bdata;
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
#endif
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c3f8dac..631d9ef 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -339,6 +339,31 @@
}
}
+void mmu_map_region(phys_addr_t addr, u64 size, bool emergency)
+{
+ u64 va_bits;
+ int level = 0;
+ u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
+
+ attrs |= PTE_TYPE_BLOCK | PTE_BLOCK_AF;
+
+ get_tcr(NULL, &va_bits);
+ if (va_bits < 39)
+ level = 1;
+
+ if (emergency)
+ map_range(addr, addr, size, level,
+ (u64 *)gd->arch.tlb_emerg, attrs);
+
+ /* Switch pagetables while we update the primary one */
+ __asm_switch_ttbr(gd->arch.tlb_emerg);
+
+ map_range(addr, addr, size, level,
+ (u64 *)gd->arch.tlb_addr, attrs);
+
+ __asm_switch_ttbr(gd->arch.tlb_addr);
+}
+
static void add_map(struct mm_region *map)
{
u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2d931c2..b3fe3f3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -262,11 +262,6 @@
zynqmp-m-a2197-02-revA.dtb \
zynqmp-m-a2197-03-revA.dtb \
zynqmp-p-a2197-00-revA.dtb \
- zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo \
- zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo \
- zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo \
- zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo \
- zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
@@ -281,22 +276,10 @@
zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
- zynqmp-sc-vek280-revA.dtbo \
- zynqmp-sc-vek280-revB.dtbo \
- zynqmp-sc-vhk158-revA.dtbo \
- zynqmp-sc-vpk120-revB.dtbo \
- zynqmp-sc-vpk180-revA.dtbo \
- zynqmp-sc-vpk180-revB.dtbo \
- zynqmp-sc-vn-p-b2197-00-revA.dtbo \
zynqmp-sm-k24-revA.dtb \
zynqmp-smk-k24-revA.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
- zynqmp-sck-kd-g-revA.dtbo \
- zynqmp-sck-kr-g-revA.dtbo \
- zynqmp-sck-kr-g-revB.dtbo \
- zynqmp-sck-kv-g-revA.dtbo \
- zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-vpk120-revA.dtb \
zynqmp-vp-x-a2785-00-revA.dtb \
@@ -324,6 +307,67 @@
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+
+zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
+zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
+zynqmp-p-a2197-00-revA-x-prc-03-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-03-revA.dtbo
+zynqmp-p-a2197-00-revA-x-prc-04-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-04-revA.dtbo
+zynqmp-p-a2197-00-revA-x-prc-05-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-05-revA.dtbo
+
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-01-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb
+
+zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo
+zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo
+zynqmp-sc-vhk158-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vhk158-revA.dtbo
+zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo
+zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo
+zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo
+zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo
+
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vhk158-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb
+
+zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
+zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
+zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+
+zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
+zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
+zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+
+zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
+zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo
+zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo
+zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
+
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
versal-mini-emmc0.dtb \
@@ -812,6 +856,7 @@
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
+ imx6q-lxr.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
@@ -950,13 +995,6 @@
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach.dtb
-dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \
- keystone-k2l-evm.dtb \
- keystone-k2e-evm.dtb \
- keystone-k2g-evm.dtb \
- keystone-k2g-generic.dtb \
- keystone-k2g-ice.dtb
-
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
@@ -994,14 +1032,8 @@
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
at91sam9g25-gardena-smart-gateway.dtb
-dtb-$(CONFIG_TARGET_ETHERNUT5) += ethernut5.dtb
-
dtb-$(CONFIG_TARGET_USB_A9263) += usb_a9263.dtb
-dtb-$(CONFIG_TARGET_OMAP3_EVM) += \
- omap3-evm-37xx.dtb \
- omap3-evm.dtb
-
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
diff --git a/arch/arm/dts/at91sam9xe.dtsi b/arch/arm/dts/at91sam9xe.dtsi
deleted file mode 100644
index 0278f63..0000000
--- a/arch/arm/dts/at91sam9xe.dtsi
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
- *
- * Copyright (C) 2015 Atmel,
- * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "at91sam9260.dtsi"
-
-/ {
- model = "Atmel AT91SAM9XE family SoC";
- compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
-
- sram0: sram@002ff000 {
- status = "disabled";
- };
-
- sram1: sram@00300000 {
- compatible = "mmio-sram";
- reg = <0x00300000 0x4000>;
- };
-};
diff --git a/arch/arm/dts/ethernut5.dts b/arch/arm/dts/ethernut5.dts
deleted file mode 100644
index 5c24dea..0000000
--- a/arch/arm/dts/ethernut5.dts
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * ethernut5.dts - Device Tree file for Ethernut 5 board
- *
- * Copyright (C) 2012 egnite GmbH <info@egnite.de>
- *
- * Licensed under GPLv2.
- */
-/dts-v1/;
-#include "at91sam9xe.dtsi"
-
-/ {
- model = "Ethernut 5";
- compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
-
- chosen {
- bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
- };
-
- memory {
- reg = <0x20000000 0x08000000>;
- };
-
- clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
- main_xtal {
- clock-frequency = <18432000>;
- };
- };
-
- ahb {
- apb {
- dbgu: serial@fffff200 {
- status = "okay";
- };
-
- usart0: serial@fffb0000 {
- status = "okay";
- };
-
- usart1: serial@fffb4000 {
- status = "okay";
- };
-
- macb0: ethernet@fffc4000 {
- phy-mode = "rmii";
- status = "okay";
- };
-
- usb1: gadget@fffa4000 {
- atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
- };
-
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- status = "okay";
-
- gpios = <0
- &pioC 14 GPIO_ACTIVE_HIGH
- 0
- >;
-
- root@0 {
- label = "root";
- reg = <0x0 0x08000000>;
- };
-
- data@20000 {
- label = "data";
- reg = <0x08000000 0x38000000>;
- };
- };
-
- usb0: ohci@00500000 {
- num-ports = <2>;
- status = "okay";
- };
- };
-
- i2c-gpio-0 {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- pcf8563@50 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-};
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
index 65a5fcd..40289c8 100644
--- a/arch/arm/dts/exynos4210-origen.dts
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -25,8 +25,7 @@
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 05989ee..88e9c0e 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -240,15 +240,13 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 2 0>;
status = "okay";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpx3 4 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 610a8ad..c87b92b 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -235,15 +235,13 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 2 0>;
status = "okay";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpx3 4 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index ce08e8d..346e0f5 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -234,20 +234,19 @@
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-inverted;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
&mshc_0 {
- samsung,bus-width = <8>;
- samsung,timing = <2 1 0>;
- samsung,removable = <0>;
- fifoth_val = <0x203f0040>;
- bus_hz = <400000000>;
- div = <0x3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <0>;
+ samsung,dw-mshc-sdr-timing = <2 1>;
+ non-removable;
+ fifo-depth = <0x80>;
+ clock-frequency = <400000000>;
index = <4>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index c4db137..2b71d32 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -108,8 +108,7 @@
};
sdhci@12510000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@@ -431,26 +430,23 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
&mshc_0 {
- samsung,bus-width = <8>;
- samsung,timing = <2 1 0>;
- samsung,removable = <0>;
- fifoth_val = <0x203f0040>;
- bus_hz = <400000000>;
- div = <0x3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <0>;
+ samsung,dw-mshc-sdr-timing = <2 1>;
+ non-removable;
+ clock-frequency = <400000000>;
index = <4>;
fifo-depth = <0x80>;
status = "okay";
diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts
index 60309c6..4c894f1 100644
--- a/arch/arm/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
@@ -27,8 +27,9 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
};
mmc@12210000 {
@@ -36,8 +37,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts
index afe0cca..f9f54cb 100644
--- a/arch/arm/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/dts/exynos5250-smdk5250.dts
@@ -145,9 +145,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
@@ -155,9 +156,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index e41f2d3..ab7b521 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -301,9 +301,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
@@ -311,9 +312,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 77e7a6b..9c47883 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -103,9 +103,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts
index 7a5da67..6ba1306 100644
--- a/arch/arm/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/dts/exynos5420-smdk5420.dts
@@ -106,9 +106,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
samsung,pre-init;
};
@@ -117,9 +118,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
index 9d055d0..ef25cf7 100644
--- a/arch/arm/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -280,11 +280,11 @@
};
mmc@12200000 {
- fifoth_val = <0x201f0020>;
+ fifo-depth = <0x40>;
};
mmc@12220000 {
- fifoth_val = <0x201f0020>;
+ fifo-depth = <0x40>;
};
emmc-reset {
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 221da8b..5915ed6 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -119,9 +119,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
samsung,pre-init;
};
@@ -130,9 +131,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts
new file mode 100644
index 0000000..ae4f8ee
--- /dev/null
+++ b/arch/arm/dts/imx6q-lxr.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2024 Comvetia AG
+
+/dts-v1/;
+#include "imx6q-phytec-pfla02.dtsi"
+
+/ {
+ model = "COMVETIA QSoIP LXR-2";
+ compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ spi {
+ compatible = "spi-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi_gpio>;
+ sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga@0 {
+ compatible = "altr,fpga-passive-serial";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fpga>;
+ nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&fec {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&usdhc3 {
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fpga: fpgagrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
+ MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_spi_gpio: spigpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
+ MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 0000000..500944b
--- /dev/null
+++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
+
+/ {
+ model = "Phytec phyFLEX-i.MX6 Quad";
+ compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
index 78457ef..c8c0fc1 100644
--- a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
@@ -10,6 +10,22 @@
};
};
+&aips2 {
+ bootph-all;
+};
+
+&pinctrl_uart2 {
+ bootph-all;
+};
+
+&soc {
+ bootph-all;
+};
+
+&uart2 {
+ bootph-all;
+};
+
&wdog1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
new file mode 100644
index 0000000..c0c47ad
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -0,0 +1,467 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Phytec phyFLEX-i.MX6 Quad";
+ compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 15 0>;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_vbus>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 0 0>;
+ enable-active-high;
+ };
+
+ gpio_leds: leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ label = "phyflex:green";
+ gpios = <&gpio1 30 0>;
+ };
+
+ led_red: led-red {
+ label = "phyflex:red";
+ gpios = <&gpio2 31 0>;
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "disabled";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+
+ som_flash: flash@0 {
+ compatible = "m25p80", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-handle = <ðphy>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <10>; /* in msecs */
+ phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ phy-supply = <&vdd_eth_io_reg>;
+ status = "disabled";
+
+ fec_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ txc-skew-ps = <1680>;
+ rxc-skew-ps = <1860>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ som_eeprom: eeprom@50 {
+ compatible = "catalyst,24c32", "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+
+ pmic@58 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ regulators {
+ vddcore_reg: bcore1 {
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vddsoc_reg: bcore2 {
+ regulator-min-microvolt = <730000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vdd_ddr3_reg: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_reg: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_buckmem_reg: bmem {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_reg: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vdd_eth_io_reg: ldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_mx6_snvs_reg: ldo5 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_pmic_io_reg: ldo6 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_sd0_reg: ldo9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_sd1_reg: ldo10 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_mx6_high_reg: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ };
+
+ da9063_rtc: rtc {
+ compatible = "dlg,da9063-rtc";
+ };
+
+ da9063_wdog: watchdog {
+ compatible = "dlg,da9063-watchdog";
+ };
+
+ onkey {
+ compatible = "dlg,da9063-onkey";
+ status = "disabled";
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <100000>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+};
+
+&iomuxc {
+ imx6q-phytec-pfla02 {
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1_vbus: usbh1vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_cdwp: usdhc3cdwp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
+ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+ >;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+};
+
+®_arm {
+ vin-supply = <&vddcore_reg>;
+};
+
+®_pu {
+ vin-supply = <&vddsoc_reg>;
+};
+
+®_soc {
+ vin-supply = <&vddsoc_reg>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "disabled";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "disabled";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&vdd_sd1_reg>;
+ status = "disabled";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3
+ &pinctrl_usdhc3_cdwp>;
+ cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&vdd_sd0_reg>;
+ status = "disabled";
+};
+
+&wdog1 {
+ /*
+ * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
+ * used for reboot, does not reset all external PMIC voltages on reset.
+ */
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts
deleted file mode 100644
index f16c830..0000000
--- a/arch/arm/dts/imx6sl-evk.dts
+++ /dev/null
@@ -1,658 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-//Copyright (C) 2013 Freescale Semiconductor, Inc.
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "imx6sl.dtsi"
-
-/ {
- model = "Freescale i.MX6 SoloLite EVK Board";
- compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x40000000>;
- };
-
- backlight_display: backlight_display {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_led>;
-
- user {
- label = "debug";
- gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
-
- reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&swbst_reg>;
- };
-
- reg_aud3v: regulator-aud3v {
- compatible = "regulator-fixed";
- regulator-name = "wm8962-supply-3v15";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
- regulator-boot-on;
- };
-
- reg_aud4v: regulator-aud4v {
- compatible = "regulator-fixed";
- regulator-name = "wm8962-supply-4v2";
- regulator-min-microvolt = <4325000>;
- regulator-max-microvolt = <4325000>;
- regulator-boot-on;
- };
-
- reg_lcd_3v3: regulator-lcd-3v3 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
- regulator-name = "lcd-3v3";
- gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_lcd_5v: regulator-lcd-5v {
- compatible = "regulator-fixed";
- regulator-name = "lcd-5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- sound {
- compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hp>;
- model = "wm8962-audio";
- ssi-controller = <&ssi2>;
- audio-codec = <&codec>;
- audio-routing =
- "Headphone Jack", "HPOUTL",
- "Headphone Jack", "HPOUTR",
- "Ext Spk", "SPKOUTL",
- "Ext Spk", "SPKOUTR",
- "AMIC", "MICBIAS",
- "IN3R", "AMIC";
- mux-int-port = <2>;
- mux-ext-port = <3>;
- hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
- };
-
- panel {
- compatible = "sii,43wvf1g";
- backlight = <&backlight_display>;
- dvdd-supply = <®_lcd_3v3>;
- avdd-supply = <®_lcd_5v>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
-
-&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux3>;
- status = "okay";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p32", "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&fec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
- phy-mode = "rmii";
- status = "okay";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic: pfuze100@8 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1875000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- regulator-always-on;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- codec: wm8962@1a {
- compatible = "wlf,wm8962";
- reg = <0x1a>;
- clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
- DCVDD-supply = <&vgen3_reg>;
- DBVDD-supply = <®_aud3v>;
- AVDD-supply = <&vgen3_reg>;
- CPVDD-supply = <&vgen3_reg>;
- MICVDD-supply = <®_aud3v>;
- PLLVDD-supply = <&vgen3_reg>;
- SPKVDD1-supply = <®_aud4v>;
- SPKVDD2-supply = <®_aud4v>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- imx6sl-evk {
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
- MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
- MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
- MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
- MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
- MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
- MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
- MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
- >;
- };
-
- pinctrl_audmux3: audmux3grp {
- fsl,pins = <
- MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
- MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
- MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
- MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
- MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
- >;
- };
-
- pinctrl_fec_sleep: fecgrp-sleep {
- fsl,pins = <
- MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
- MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
- MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
- MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
- MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
- MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
- MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
- MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
- >;
- };
-
- pinctrl_hp: hpgrp {
- fsl,pins = <
- MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
- >;
- };
-
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_kpp: kppgrp {
- fsl,pins = <
- MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
- MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
- MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
- MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
- MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
- MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
- >;
- };
-
- pinctrl_lcd: lcdgrp {
- fsl,pins = <
- MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
- MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
- MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
- MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
- MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
- MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
- MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
- MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
- MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
- MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
- MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
- MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
- MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
- MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
- MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
- MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
- MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
- MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
- MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
- MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
- MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
- MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
- MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
- MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
- MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
- MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
- MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
- MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
- >;
- };
-
- pinctrl_led: ledgrp {
- fsl,pins = <
- MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
- >;
- };
-
- pinctrl_pwm1: pwmgrp {
- fsl,pins = <
- MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
- >;
- };
-
- pinctrl_reg_lcd_3v3: reglcd3v3grp {
- fsl,pins = <
- MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
- >;
- };
- };
-};
-
-&kpp {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_kpp>;
- linux,keymap = <
- MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
- MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
- MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
- MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
- MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
- MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
- MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
- MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
- >;
- status = "okay";
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcd>;
- status = "okay";
-
- port {
- display_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pwm1 {
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1>;
- status = "okay";
-};
-
-®_vdd1p1 {
- vin-supply = <&sw2_reg>;
-};
-
-®_vdd2p5 {
- vin-supply = <&sw2_reg>;
-};
-
-&snvs_poweroff {
- status = "okay";
-};
-
-&ssi2 {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&usbotg1 {
- vbus-supply = <®_usb_otg1_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- vbus-supply = <®_usb_otg2_vbus>;
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx6sl-pinfunc.h b/arch/arm/dts/imx6sl-pinfunc.h
deleted file mode 100644
index bcf1606..0000000
--- a/arch/arm/dts/imx6sl-pinfunc.h
+++ /dev/null
@@ -1,1073 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DTS_IMX6SL_PINFUNC_H
-#define __DTS_IMX6SL_PINFUNC_H
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
-#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
-#define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
-#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
-#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
-#define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
-#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x050 0x2a8 0x80c 0x2 0x0
-#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0
-#define MX6SL_PAD_AUD_RXC__I2C3_SDA 0x050 0x2a8 0x730 0x4 0x0
-#define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 0x050 0x2a8 0x6c4 0x6 0x0
-#define MX6SL_PAD_AUD_RXD__AUD3_RXD 0x054 0x2ac 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI 0x054 0x2ac 0x6bc 0x1 0x0
-#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA 0x054 0x2ac 0x814 0x2 0x0
-#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA 0x054 0x2ac 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0
-#define MX6SL_PAD_AUD_RXD__SD1_LCTL 0x054 0x2ac 0x000 0x4 0x0
-#define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS 0x058 0x2b0 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_RXFS__I2C1_SCL 0x058 0x2b0 0x71c 0x1 0x0
-#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA 0x058 0x2b0 0x80c 0x2 0x1
-#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA 0x058 0x2b0 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0
-#define MX6SL_PAD_AUD_RXFS__I2C3_SCL 0x058 0x2b0 0x72c 0x4 0x0
-#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 0x058 0x2b0 0x6c0 0x6 0x0
-#define MX6SL_PAD_AUD_TXC__AUD3_TXC 0x05c 0x2b4 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO 0x05c 0x2b4 0x6b8 0x1 0x0
-#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA 0x05c 0x2b4 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA 0x05c 0x2b4 0x814 0x2 0x1
-#define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0
-#define MX6SL_PAD_AUD_TXC__SD2_LCTL 0x05c 0x2b4 0x000 0x4 0x0
-#define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_TXD__AUD3_TXD 0x060 0x2b8 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK 0x060 0x2b8 0x6b0 0x1 0x0
-#define MX6SL_PAD_AUD_TXD__UART4_CTS_B 0x060 0x2b8 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_TXD__UART4_RTS_B 0x060 0x2b8 0x810 0x2 0x0
-#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0
-#define MX6SL_PAD_AUD_TXD__SD4_LCTL 0x060 0x2b8 0x000 0x4 0x0
-#define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0
-#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x064 0x2bc 0x000 0x0 0x0
-#define MX6SL_PAD_AUD_TXFS__PWM3_OUT 0x064 0x2bc 0x000 0x1 0x0
-#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B 0x064 0x2bc 0x810 0x2 0x1
-#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B 0x064 0x2bc 0x000 0x2 0x0
-#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0
-#define MX6SL_PAD_AUD_TXFS__SD3_LCTL 0x064 0x2bc 0x000 0x4 0x0
-#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x068 0x358 0x684 0x0 0x0
-#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS 0x068 0x358 0x5f8 0x1 0x0
-#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x068 0x358 0x818 0x2 0x0
-#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B 0x068 0x358 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0
-#define MX6SL_PAD_ECSPI1_MISO__SD2_WP 0x068 0x358 0x834 0x4 0x0
-#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x06c 0x35c 0x688 0x0 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC 0x06c 0x35c 0x5f4 0x1 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x06c 0x35c 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA 0x06c 0x35c 0x81c 0x2 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x06c 0x35c 0x000 0x4 0x0
-#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x070 0x360 0x67c 0x0 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD 0x070 0x360 0x5e8 0x1 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x070 0x360 0x81c 0x2 0x1
-#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA 0x070 0x360 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET 0x070 0x360 0x000 0x4 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0
-#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x074 0x364 0x68c 0x0 0x0
-#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD 0x074 0x364 0x5e4 0x1 0x0
-#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x074 0x364 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B 0x074 0x364 0x818 0x2 0x1
-#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1 0x074 0x364 0x000 0x3 0x0
-#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B 0x074 0x364 0x830 0x4 0x0
-#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x074 0x364 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x074 0x364 0x000 0x6 0x0
-#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x078 0x368 0x6a0 0x0 0x0
-#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x078 0x368 0x000 0x1 0x0
-#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B 0x078 0x368 0x808 0x2 0x0
-#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B 0x078 0x368 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK 0x078 0x368 0x000 0x3 0x0
-#define MX6SL_PAD_ECSPI2_MISO__SD1_WP 0x078 0x368 0x82c 0x4 0x0
-#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x078 0x368 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x078 0x368 0x824 0x6 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x07c 0x36c 0x6a4 0x0 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x07c 0x36c 0x000 0x1 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA 0x07c 0x36c 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA 0x07c 0x36c 0x80c 0x2 0x2
-#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x07c 0x36c 0x670 0x3 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x07c 0x36c 0x000 0x4 0x0
-#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x07c 0x36c 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x080 0x370 0x69c 0x0 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x080 0x370 0x7f4 0x1 0x1
-#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA 0x080 0x370 0x80c 0x2 0x3
-#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA 0x080 0x370 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x080 0x370 0x674 0x3 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET 0x080 0x370 0x000 0x4 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x080 0x370 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1
-#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x084 0x374 0x6a8 0x0 0x0
-#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x084 0x374 0x698 0x1 0x0
-#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B 0x084 0x374 0x000 0x2 0x0
-#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B 0x084 0x374 0x808 0x2 0x1
-#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC 0x084 0x374 0x678 0x3 0x0
-#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B 0x084 0x374 0x828 0x4 0x0
-#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x084 0x374 0x000 0x5 0x0
-#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x084 0x374 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x088 0x378 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_BDR0__SD4_CLK 0x088 0x378 0x850 0x1 0x0
-#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B 0x088 0x378 0x808 0x2 0x2
-#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B 0x088 0x378 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26 0x088 0x378 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_BDR0__SPDC_RL 0x088 0x378 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05 0x088 0x378 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7 0x088 0x378 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1 0x08c 0x37c 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_BDR1__SD4_CMD 0x08c 0x37c 0x858 0x1 0x0
-#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B 0x08c 0x37c 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B 0x08c 0x37c 0x808 0x2 0x3
-#define MX6SL_PAD_EPDC_BDR1__EIM_CRE 0x08c 0x37c 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_BDR1__SPDC_UD 0x08c 0x37c 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06 0x08c 0x37c 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8 0x08c 0x37c 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x090 0x380 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI 0x090 0x380 0x6d8 0x1 0x0
-#define MX6SL_PAD_EPDC_D0__LCD_DATA24 0x090 0x380 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D0__CSI_DATA00 0x090 0x380 0x630 0x3 0x0
-#define MX6SL_PAD_EPDC_D0__SPDC_DATA00 0x090 0x380 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D0__GPIO1_IO07 0x090 0x380 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x094 0x384 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO 0x094 0x384 0x6d4 0x1 0x0
-#define MX6SL_PAD_EPDC_D1__LCD_DATA25 0x094 0x384 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D1__CSI_DATA01 0x094 0x384 0x634 0x3 0x0
-#define MX6SL_PAD_EPDC_D1__SPDC_DATA01 0x094 0x384 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D1__GPIO1_IO08 0x094 0x384 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x098 0x388 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 0x098 0x388 0x6c0 0x1 0x1
-#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2 0x098 0x388 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D10__EIM_ADDR18 0x098 0x388 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D10__SPDC_DATA10 0x098 0x388 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D10__GPIO1_IO17 0x098 0x388 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D10__SD4_WP 0x098 0x388 0x87c 0x6 0x0
-#define MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x09c 0x38c 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK 0x09c 0x38c 0x6b0 0x1 0x1
-#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3 0x09c 0x38c 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D11__EIM_ADDR19 0x09c 0x38c 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D11__SPDC_DATA11 0x09c 0x38c 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D11__GPIO1_IO18 0x09c 0x38c 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D11__SD4_CD_B 0x09c 0x38c 0x854 0x6 0x0
-#define MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x0a0 0x390 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x0a0 0x390 0x804 0x1 0x0
-#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA 0x0a0 0x390 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM 0x0a0 0x390 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D12__EIM_ADDR20 0x0a0 0x390 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D12__SPDC_DATA12 0x0a0 0x390 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D12__GPIO1_IO19 0x0a0 0x390 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 0x0a0 0x390 0x6c4 0x6 0x1
-#define MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x0a4 0x394 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x0a4 0x394 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA 0x0a4 0x394 0x804 0x1 0x1
-#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ 0x0a4 0x394 0x6e8 0x2 0x0
-#define MX6SL_PAD_EPDC_D13__EIM_ADDR21 0x0a4 0x394 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D13__SPDC_DATA13 0x0a4 0x394 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D13__GPIO1_IO20 0x0a4 0x394 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 0x0a4 0x394 0x6c8 0x6 0x0
-#define MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x0a8 0x398 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x0a8 0x398 0x800 0x1 0x0
-#define MX6SL_PAD_EPDC_D14__UART2_CTS_B 0x0a8 0x398 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT 0x0a8 0x398 0x6ec 0x2 0x0
-#define MX6SL_PAD_EPDC_D14__EIM_ADDR22 0x0a8 0x398 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D14__SPDC_DATA14 0x0a8 0x398 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D14__GPIO1_IO21 0x0a8 0x398 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 0x0a8 0x398 0x6cc 0x6 0x0
-#define MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x0ac 0x39c 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x0ac 0x39c 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D15__UART2_RTS_B 0x0ac 0x39c 0x800 0x1 0x1
-#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE 0x0ac 0x39c 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D15__EIM_ADDR23 0x0ac 0x39c 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D15__SPDC_DATA15 0x0ac 0x39c 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D15__GPIO1_IO22 0x0ac 0x39c 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY 0x0ac 0x39c 0x6b4 0x6 0x1
-#define MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x0b0 0x3a0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 0x0b0 0x3a0 0x6dc 0x1 0x0
-#define MX6SL_PAD_EPDC_D2__LCD_DATA26 0x0b0 0x3a0 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D2__CSI_DATA02 0x0b0 0x3a0 0x638 0x3 0x0
-#define MX6SL_PAD_EPDC_D2__SPDC_DATA02 0x0b0 0x3a0 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D2__GPIO1_IO09 0x0b0 0x3a0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x0b4 0x3a4 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK 0x0b4 0x3a4 0x6d0 0x1 0x0
-#define MX6SL_PAD_EPDC_D3__LCD_DATA27 0x0b4 0x3a4 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D3__CSI_DATA03 0x0b4 0x3a4 0x63c 0x3 0x0
-#define MX6SL_PAD_EPDC_D3__SPDC_DATA03 0x0b4 0x3a4 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D3__GPIO1_IO10 0x0b4 0x3a4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x0b8 0x3a8 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 0x0b8 0x3a8 0x6e0 0x1 0x0
-#define MX6SL_PAD_EPDC_D4__LCD_DATA28 0x0b8 0x3a8 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D4__CSI_DATA04 0x0b8 0x3a8 0x640 0x3 0x0
-#define MX6SL_PAD_EPDC_D4__SPDC_DATA04 0x0b8 0x3a8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D4__GPIO1_IO11 0x0b8 0x3a8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x0bc 0x3ac 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 0x0bc 0x3ac 0x6e4 0x1 0x0
-#define MX6SL_PAD_EPDC_D5__LCD_DATA29 0x0bc 0x3ac 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D5__CSI_DATA05 0x0bc 0x3ac 0x644 0x3 0x0
-#define MX6SL_PAD_EPDC_D5__SPDC_DATA05 0x0bc 0x3ac 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D5__GPIO1_IO12 0x0bc 0x3ac 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x0c0 0x3b0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 0x0c0 0x3b0 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D6__LCD_DATA30 0x0c0 0x3b0 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D6__CSI_DATA06 0x0c0 0x3b0 0x648 0x3 0x0
-#define MX6SL_PAD_EPDC_D6__SPDC_DATA06 0x0c0 0x3b0 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D6__GPIO1_IO13 0x0c0 0x3b0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x0c4 0x3b4 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY 0x0c4 0x3b4 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_D7__LCD_DATA31 0x0c4 0x3b4 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D7__CSI_DATA07 0x0c4 0x3b4 0x64c 0x3 0x0
-#define MX6SL_PAD_EPDC_D7__SPDC_DATA07 0x0c4 0x3b4 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D7__GPIO1_IO14 0x0c4 0x3b4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x0c8 0x3b8 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI 0x0c8 0x3b8 0x6bc 0x1 0x1
-#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0 0x0c8 0x3b8 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D8__EIM_ADDR16 0x0c8 0x3b8 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D8__SPDC_DATA08 0x0c8 0x3b8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D8__GPIO1_IO15 0x0c8 0x3b8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D8__SD4_RESET 0x0c8 0x3b8 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x0cc 0x3bc 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO 0x0cc 0x3bc 0x6b8 0x1 0x1
-#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1 0x0cc 0x3bc 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_D9__EIM_ADDR17 0x0cc 0x3bc 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_D9__SPDC_DATA09 0x0cc 0x3bc 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_D9__GPIO1_IO16 0x0cc 0x3bc 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_D9__SD4_VSELECT 0x0cc 0x3bc 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0d0 0x3c0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x0d0 0x3c0 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR 0x0d0 0x3c0 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x0d0 0x3c0 0x674 0x3 0x1
-#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL 0x0d0 0x3c0 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31 0x0d0 0x3c0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET 0x0d0 0x3c0 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x0d4 0x3c4 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 0x0d4 0x3c4 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER 0x0d4 0x3c4 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x0d4 0x3c4 0x670 0x3 0x1
-#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL 0x0d4 0x3c4 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00 0x0d4 0x3c4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT 0x0d4 0x3c4 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x0d8 0x3c8 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY 0x0d8 0x3c8 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR 0x0d8 0x3c8 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x0d8 0x3c8 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL 0x0d8 0x3c8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01 0x0d8 0x3c8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_GDRL__SD2_WP 0x0d8 0x3c8 0x834 0x6 0x1
-#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x0dc 0x3cc 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT 0x0dc 0x3cc 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR 0x0dc 0x3cc 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x0dc 0x3cc 0x678 0x3 0x1
-#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL 0x0dc 0x3cc 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02 0x0dc 0x3cc 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B 0x0dc 0x3cc 0x830 0x6 0x1
-#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM 0x0e0 0x3d0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 0x0e0 0x3d0 0x85c 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20 0x0e0 0x3d0 0x7c8 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK 0x0e0 0x3d0 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x0e0 0x3d0 0x5dc 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11 0x0e0 0x3d0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET 0x0e0 0x3d0 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0 0x0e4 0x3d4 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC 0x0e4 0x3d4 0x604 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16 0x0e4 0x3d4 0x7b8 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW 0x0e4 0x3d4 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL 0x0e4 0x3d4 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x0e4 0x3d4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET 0x0e4 0x3d4 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1 0x0e8 0x3d8 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS 0x0e8 0x3d8 0x610 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17 0x0e8 0x3d8 0x7bc 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B 0x0e8 0x3d8 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL 0x0e8 0x3d8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x0e8 0x3d8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT 0x0e8 0x3d8 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2 0x0ec 0x3dc 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD 0x0ec 0x3dc 0x600 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18 0x0ec 0x3dc 0x7c0 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B 0x0ec 0x3dc 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL 0x0ec 0x3dc 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x0ec 0x3dc 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP 0x0ec 0x3dc 0x87c 0x6 0x1
-#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3 0x0f0 0x3e0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC 0x0f0 0x3e0 0x60c 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19 0x0f0 0x3e0 0x7c4 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B 0x0f0 0x3e0 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL 0x0f0 0x3e0 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x0f0 0x3e0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B 0x0f0 0x3e0 0x854 0x6 0x1
-#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ 0x0f4 0x3e4 0x6e8 0x0 0x1
-#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 0x0f4 0x3e4 0x860 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21 0x0f4 0x3e4 0x7cc 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN 0x0f4 0x3e4 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID 0x0f4 0x3e4 0x5e0 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x0f4 0x3e4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT 0x0f4 0x3e4 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT 0x0f8 0x3e8 0x6ec 0x0 0x1
-#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 0x0f8 0x3e8 0x864 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22 0x0f8 0x3e8 0x7d0 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B 0x0f8 0x3e8 0x884 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI 0x0f8 0x3e8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x0f8 0x3e8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP 0x0f8 0x3e8 0x84c 0x6 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE 0x0fc 0x3ec 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 0x0fc 0x3ec 0x868 0x1 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23 0x0fc 0x3ec 0x7d4 0x2 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B 0x0fc 0x3ec 0x880 0x3 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO 0x0fc 0x3ec 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x0fc 0x3ec 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B 0x0fc 0x3ec 0x838 0x6 0x0
-#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100 0x3f0 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x100 0x3f0 0x6ac 0x1 0x0
-#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT 0x100 0x3f0 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B 0x100 0x3f0 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR 0x100 0x3f0 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27 0x100 0x3f0 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x104 0x3f4 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B 0x104 0x3f4 0x000 0x1 0x0
-#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT 0x104 0x3f4 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B 0x104 0x3f4 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER 0x104 0x3f4 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28 0x104 0x3f4 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x108 0x3f8 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x108 0x3f8 0x72c 0x1 0x1
-#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT 0x108 0x3f8 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B 0x108 0x3f8 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR 0x108 0x3f8 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x108 0x3f8 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x10c 0x3fc 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x10c 0x3fc 0x730 0x1 0x1
-#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT 0x10c 0x3fc 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B 0x10c 0x3fc 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR 0x10c 0x3fc 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30 0x10c 0x3fc 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x110 0x400 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x110 0x400 0x6a4 0x1 0x1
-#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL 0x110 0x400 0x724 0x2 0x0
-#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110 0x400 0x650 0x3 0x0
-#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL 0x110 0x400 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23 0x110 0x400 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x114 0x404 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO 0x114 0x404 0x6a0 0x1 0x1
-#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA 0x114 0x404 0x728 0x2 0x0
-#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x114 0x404 0x654 0x3 0x0
-#define MX6SL_PAD_EPDC_SDLE__SPDC_LD 0x114 0x404 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24 0x114 0x404 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x118 0x408 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 0x118 0x408 0x6a8 0x1 0x1
-#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR 0x118 0x408 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10 0x118 0x408 0x658 0x3 0x0
-#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL 0x118 0x408 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x118 0x408 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x11c 0x40c 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x11c 0x40c 0x69c 0x1 0x1
-#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x11c 0x40c 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11 0x11c 0x40c 0x65c 0x3 0x0
-#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR 0x11c 0x40c 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x11c 0x40c 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x120 0x410 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS 0x120 0x410 0x608 0x1 0x0
-#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA 0x120 0x410 0x80c 0x2 0x4
-#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA 0x120 0x410 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24 0x120 0x410 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0 0x120 0x410 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x120 0x410 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x120 0x410 0x000 0x6 0x0
-#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x124 0x414 0x000 0x0 0x0
-#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD 0x124 0x414 0x5fc 0x1 0x0
-#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA 0x124 0x414 0x000 0x2 0x0
-#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA 0x124 0x414 0x80c 0x2 0x5
-#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25 0x124 0x414 0x000 0x3 0x0
-#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1 0x124 0x414 0x000 0x4 0x0
-#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04 0x124 0x414 0x000 0x5 0x0
-#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x124 0x414 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1
-#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1
-#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0
-#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1
-#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0
-#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_MDC__FEC_MDC 0x12c 0x41c 0x000 0x0 0x0
-#define MX6SL_PAD_FEC_MDC__SD4_DATA4 0x12c 0x41c 0x86c 0x1 0x0
-#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT 0x12c 0x41c 0x000 0x2 0x0
-#define MX6SL_PAD_FEC_MDC__SD1_RESET 0x12c 0x41c 0x000 0x3 0x0
-#define MX6SL_PAD_FEC_MDC__SD3_RESET 0x12c 0x41c 0x000 0x4 0x0
-#define MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x12c 0x41c 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_MDC__ARM_TRACE29 0x12c 0x41c 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x130 0x420 0x6f4 0x0 0x1
-#define MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130 0x420 0x850 0x1 0x1
-#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS 0x130 0x420 0x620 0x2 0x0
-#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 0x130 0x420 0x6dc 0x3 0x1
-#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1 0x130 0x420 0x710 0x4 0x0
-#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x130 0x420 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26 0x130 0x420 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x134 0x424 0x000 0x0 0x0
-#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x134 0x424 0x000 0x1 0x0
-#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B 0x134 0x424 0x000 0x2 0x0
-#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT 0x134 0x424 0x000 0x3 0x0
-#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY 0x134 0x424 0x62c 0x4 0x0
-#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x134 0x424 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK 0x134 0x424 0x7f4 0x6 0x2
-#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER 0x138 0x428 0x708 0x0 0x1
-#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x138 0x428 0x85c 0x1 0x1
-#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD 0x138 0x428 0x614 0x2 0x0
-#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI 0x138 0x428 0x6d8 0x3 0x1
-#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1 0x138 0x428 0x000 0x4 0x0
-#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x138 0x428 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25 0x138 0x428 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x13c 0x42c 0x6f8 0x0 0x0
-#define MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x13c 0x42c 0x870 0x1 0x0
-#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x13c 0x42c 0x5dc 0x2 0x1
-#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT 0x13c 0x42c 0x000 0x3 0x0
-#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT 0x13c 0x42c 0x000 0x4 0x0
-#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x13c 0x42c 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24 0x13c 0x42c 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x140 0x430 0x6fc 0x0 0x1
-#define MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x140 0x430 0x864 0x1 0x1
-#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS 0x140 0x430 0x628 0x2 0x0
-#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 0x140 0x430 0x6e0 0x3 0x1
-#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3 0x140 0x430 0x000 0x4 0x0
-#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x140 0x430 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_RXD1__FEC_COL 0x140 0x430 0x6f0 0x6 0x0
-#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK 0x144 0x434 0x70c 0x0 0x1
-#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x144 0x434 0x858 0x1 0x1
-#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC 0x144 0x434 0x61c 0x2 0x0
-#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK 0x144 0x434 0x6d0 0x3 0x1
-#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2 0x144 0x434 0x714 0x4 0x0
-#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x144 0x434 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27 0x144 0x434 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x148 0x438 0x000 0x0 0x0
-#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x148 0x438 0x874 0x1 0x0
-#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN 0x148 0x438 0x7f0 0x2 0x0
-#define MX6SL_PAD_FEC_TX_EN__SD1_WP 0x148 0x438 0x82c 0x3 0x1
-#define MX6SL_PAD_FEC_TX_EN__SD3_WP 0x148 0x438 0x84c 0x4 0x1
-#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x148 0x438 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28 0x148 0x438 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x14c 0x43c 0x000 0x0 0x0
-#define MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x14c 0x43c 0x868 0x1 0x1
-#define MX6SL_PAD_FEC_TXD0__AUD6_TXD 0x14c 0x43c 0x618 0x2 0x0
-#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 0x14c 0x43c 0x6e4 0x3 0x1
-#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN 0x14c 0x43c 0x718 0x4 0x0
-#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x14c 0x43c 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30 0x14c 0x43c 0x000 0x6 0x0
-#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x150 0x440 0x000 0x0 0x0
-#define MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x150 0x440 0x878 0x1 0x0
-#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT 0x150 0x440 0x000 0x2 0x0
-#define MX6SL_PAD_FEC_TXD1__SD1_CD_B 0x150 0x440 0x828 0x3 0x1
-#define MX6SL_PAD_FEC_TXD1__SD3_CD_B 0x150 0x440 0x838 0x4 0x1
-#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x150 0x440 0x000 0x5 0x0
-#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK 0x150 0x440 0x700 0x6 0x0
-#define MX6SL_PAD_HSIC_DAT__USB_H_DATA 0x154 0x444 0x000 0x0 0x0
-#define MX6SL_PAD_HSIC_DAT__I2C1_SCL 0x154 0x444 0x71c 0x1 0x1
-#define MX6SL_PAD_HSIC_DAT__PWM1_OUT 0x154 0x444 0x000 0x2 0x0
-#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M 0x154 0x444 0x000 0x3 0x0
-#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19 0x154 0x444 0x000 0x5 0x0
-#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE 0x158 0x448 0x000 0x0 0x0
-#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA 0x158 0x448 0x720 0x1 0x1
-#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT 0x158 0x448 0x000 0x2 0x0
-#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0
-#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x158 0x448 0x000 0x5 0x0
-#define MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x15c 0x44c 0x71c 0x0 0x2
-#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B 0x15c 0x44c 0x7f8 0x1 0x0
-#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B 0x15c 0x44c 0x000 0x1 0x0
-#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 0x15c 0x44c 0x6c8 0x2 0x1
-#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0 0x15c 0x44c 0x6f8 0x3 0x1
-#define MX6SL_PAD_I2C1_SCL__SD3_RESET 0x15c 0x44c 0x000 0x4 0x0
-#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x15c 0x44c 0x000 0x5 0x0
-#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 0x15c 0x44c 0x690 0x6 0x0
-#define MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x160 0x450 0x720 0x0 0x2
-#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B 0x160 0x450 0x000 0x1 0x0
-#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B 0x160 0x450 0x7f8 0x1 0x1
-#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 0x160 0x450 0x6cc 0x2 0x1
-#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN 0x160 0x450 0x000 0x3 0x0
-#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT 0x160 0x450 0x000 0x4 0x0
-#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x160 0x450 0x000 0x5 0x0
-#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 0x160 0x450 0x694 0x6 0x0
-#define MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x164 0x454 0x724 0x0 0x1
-#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS 0x164 0x454 0x5f0 0x1 0x0
-#define MX6SL_PAD_I2C2_SCL__SPDIF_IN 0x164 0x454 0x7f0 0x2 0x1
-#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1 0x164 0x454 0x000 0x3 0x0
-#define MX6SL_PAD_I2C2_SCL__SD3_WP 0x164 0x454 0x84c 0x4 0x2
-#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x164 0x454 0x000 0x5 0x0
-#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY 0x164 0x454 0x680 0x6 0x0
-#define MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x168 0x458 0x728 0x0 0x1
-#define MX6SL_PAD_I2C2_SDA__AUD4_RXC 0x168 0x458 0x5ec 0x1 0x0
-#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT 0x168 0x458 0x000 0x2 0x0
-#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT 0x168 0x458 0x000 0x3 0x0
-#define MX6SL_PAD_I2C2_SDA__SD3_CD_B 0x168 0x458 0x838 0x4 0x2
-#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x168 0x458 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL0__KEY_COL0 0x16c 0x474 0x734 0x0 0x0
-#define MX6SL_PAD_KEY_COL0__I2C2_SCL 0x16c 0x474 0x724 0x1 0x2
-#define MX6SL_PAD_KEY_COL0__LCD_DATA00 0x16c 0x474 0x778 0x2 0x0
-#define MX6SL_PAD_KEY_COL0__EIM_AD00 0x16c 0x474 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL0__SD1_CD_B 0x16c 0x474 0x828 0x4 0x2
-#define MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x16c 0x474 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL1__KEY_COL1 0x170 0x478 0x738 0x0 0x0
-#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI 0x170 0x478 0x6d8 0x1 0x2
-#define MX6SL_PAD_KEY_COL1__LCD_DATA02 0x170 0x478 0x780 0x2 0x0
-#define MX6SL_PAD_KEY_COL1__EIM_AD02 0x170 0x478 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL1__SD3_DATA4 0x170 0x478 0x83c 0x4 0x0
-#define MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x170 0x478 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL2__KEY_COL2 0x174 0x47c 0x73c 0x0 0x0
-#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 0x174 0x47c 0x6dc 0x1 0x2
-#define MX6SL_PAD_KEY_COL2__LCD_DATA04 0x174 0x47c 0x788 0x2 0x0
-#define MX6SL_PAD_KEY_COL2__EIM_AD04 0x174 0x47c 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL2__SD3_DATA6 0x174 0x47c 0x844 0x4 0x0
-#define MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x174 0x47c 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL3__KEY_COL3 0x178 0x480 0x740 0x0 0x0
-#define MX6SL_PAD_KEY_COL3__AUD6_RXFS 0x178 0x480 0x620 0x1 0x1
-#define MX6SL_PAD_KEY_COL3__LCD_DATA06 0x178 0x480 0x790 0x2 0x0
-#define MX6SL_PAD_KEY_COL3__EIM_AD06 0x178 0x480 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL3__SD4_DATA6 0x178 0x480 0x874 0x4 0x1
-#define MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x178 0x480 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL3__SD1_RESET 0x178 0x480 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_COL4__KEY_COL4 0x17c 0x484 0x744 0x0 0x0
-#define MX6SL_PAD_KEY_COL4__AUD6_RXD 0x17c 0x484 0x614 0x1 0x1
-#define MX6SL_PAD_KEY_COL4__LCD_DATA08 0x17c 0x484 0x798 0x2 0x0
-#define MX6SL_PAD_KEY_COL4__EIM_AD08 0x17c 0x484 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL4__SD4_CLK 0x17c 0x484 0x850 0x4 0x2
-#define MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17c 0x484 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR 0x17c 0x484 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_COL5__KEY_COL5 0x180 0x488 0x748 0x0 0x0
-#define MX6SL_PAD_KEY_COL5__AUD6_TXFS 0x180 0x488 0x628 0x1 0x1
-#define MX6SL_PAD_KEY_COL5__LCD_DATA10 0x180 0x488 0x7a0 0x2 0x0
-#define MX6SL_PAD_KEY_COL5__EIM_AD10 0x180 0x488 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL5__SD4_DATA0 0x180 0x488 0x85c 0x4 0x2
-#define MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x180 0x488 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR 0x180 0x488 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_COL6__KEY_COL6 0x184 0x48c 0x74c 0x0 0x0
-#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x184 0x48c 0x814 0x1 0x2
-#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA 0x184 0x48c 0x000 0x1 0x0
-#define MX6SL_PAD_KEY_COL6__LCD_DATA12 0x184 0x48c 0x7a8 0x2 0x0
-#define MX6SL_PAD_KEY_COL6__EIM_AD12 0x184 0x48c 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL6__SD4_DATA2 0x184 0x48c 0x864 0x4 0x2
-#define MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x184 0x48c 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL6__SD3_RESET 0x184 0x48c 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_COL7__KEY_COL7 0x188 0x490 0x750 0x0 0x0
-#define MX6SL_PAD_KEY_COL7__UART4_RTS_B 0x188 0x490 0x810 0x1 0x2
-#define MX6SL_PAD_KEY_COL7__UART4_CTS_B 0x188 0x490 0x000 0x1 0x0
-#define MX6SL_PAD_KEY_COL7__LCD_DATA14 0x188 0x490 0x7b0 0x2 0x0
-#define MX6SL_PAD_KEY_COL7__EIM_AD14 0x188 0x490 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_COL7__SD4_DATA4 0x188 0x490 0x86c 0x4 0x1
-#define MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x188 0x490 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_COL7__SD1_WP 0x188 0x490 0x82c 0x6 0x2
-#define MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x18c 0x494 0x754 0x0 0x0
-#define MX6SL_PAD_KEY_ROW0__I2C2_SDA 0x18c 0x494 0x728 0x1 0x2
-#define MX6SL_PAD_KEY_ROW0__LCD_DATA01 0x18c 0x494 0x77c 0x2 0x0
-#define MX6SL_PAD_KEY_ROW0__EIM_AD01 0x18c 0x494 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW0__SD1_WP 0x18c 0x494 0x82c 0x4 0x3
-#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x18c 0x494 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x190 0x498 0x758 0x0 0x0
-#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO 0x190 0x498 0x6d4 0x1 0x2
-#define MX6SL_PAD_KEY_ROW1__LCD_DATA03 0x190 0x498 0x784 0x2 0x0
-#define MX6SL_PAD_KEY_ROW1__EIM_AD03 0x190 0x498 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW1__SD3_DATA5 0x190 0x498 0x840 0x4 0x0
-#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x190 0x498 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x194 0x49c 0x75c 0x0 0x0
-#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK 0x194 0x49c 0x6d0 0x1 0x2
-#define MX6SL_PAD_KEY_ROW2__LCD_DATA05 0x194 0x49c 0x78c 0x2 0x0
-#define MX6SL_PAD_KEY_ROW2__EIM_AD05 0x194 0x49c 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW2__SD3_DATA7 0x194 0x49c 0x848 0x4 0x0
-#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x194 0x49c 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW3__KEY_ROW3 0x198 0x4a0 0x760 0x0 0x0
-#define MX6SL_PAD_KEY_ROW3__AUD6_RXC 0x198 0x4a0 0x61c 0x1 0x1
-#define MX6SL_PAD_KEY_ROW3__LCD_DATA07 0x198 0x4a0 0x794 0x2 0x0
-#define MX6SL_PAD_KEY_ROW3__EIM_AD07 0x198 0x4a0 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW3__SD4_DATA7 0x198 0x4a0 0x878 0x4 0x1
-#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31 0x198 0x4a0 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT 0x198 0x4a0 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_ROW4__KEY_ROW4 0x19c 0x4a4 0x764 0x0 0x0
-#define MX6SL_PAD_KEY_ROW4__AUD6_TXC 0x19c 0x4a4 0x624 0x1 0x1
-#define MX6SL_PAD_KEY_ROW4__LCD_DATA09 0x19c 0x4a4 0x79c 0x2 0x0
-#define MX6SL_PAD_KEY_ROW4__EIM_AD09 0x19c 0x4a4 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW4__SD4_CMD 0x19c 0x4a4 0x858 0x4 0x2
-#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01 0x19c 0x4a4 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC 0x19c 0x4a4 0x824 0x6 0x1
-#define MX6SL_PAD_KEY_ROW5__KEY_ROW5 0x1a0 0x4a8 0x768 0x0 0x0
-#define MX6SL_PAD_KEY_ROW5__AUD6_TXD 0x1a0 0x4a8 0x618 0x1 0x1
-#define MX6SL_PAD_KEY_ROW5__LCD_DATA11 0x1a0 0x4a8 0x7a4 0x2 0x0
-#define MX6SL_PAD_KEY_ROW5__EIM_AD11 0x1a0 0x4a8 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW5__SD4_DATA1 0x1a0 0x4a8 0x860 0x4 0x2
-#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x1a0 0x4a8 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2
-#define MX6SL_PAD_KEY_ROW6__KEY_ROW6 0x1a4 0x4ac 0x76c 0x0 0x0
-#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1a4 0x4ac 0x000 0x1 0x0
-#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA 0x1a4 0x4ac 0x814 0x1 0x3
-#define MX6SL_PAD_KEY_ROW6__LCD_DATA13 0x1a4 0x4ac 0x7ac 0x2 0x0
-#define MX6SL_PAD_KEY_ROW6__EIM_AD13 0x1a4 0x4ac 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW6__SD4_DATA3 0x1a4 0x4ac 0x868 0x4 0x2
-#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x1a4 0x4ac 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT 0x1a4 0x4ac 0x000 0x6 0x0
-#define MX6SL_PAD_KEY_ROW7__KEY_ROW7 0x1a8 0x4b0 0x770 0x0 0x0
-#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B 0x1a8 0x4b0 0x000 0x1 0x0
-#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B 0x1a8 0x4b0 0x810 0x1 0x3
-#define MX6SL_PAD_KEY_ROW7__LCD_DATA15 0x1a8 0x4b0 0x7b4 0x2 0x0
-#define MX6SL_PAD_KEY_ROW7__EIM_AD15 0x1a8 0x4b0 0x000 0x3 0x0
-#define MX6SL_PAD_KEY_ROW7__SD4_DATA5 0x1a8 0x4b0 0x870 0x4 0x1
-#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x1a8 0x4b0 0x000 0x5 0x0
-#define MX6SL_PAD_KEY_ROW7__SD1_CD_B 0x1a8 0x4b0 0x828 0x6 0x3
-#define MX6SL_PAD_LCD_CLK__LCD_CLK 0x1ac 0x4b4 0x000 0x0 0x0
-#define MX6SL_PAD_LCD_CLK__SD4_DATA4 0x1ac 0x4b4 0x86c 0x1 0x2
-#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN 0x1ac 0x4b4 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_CLK__EIM_RW 0x1ac 0x4b4 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_CLK__PWM4_OUT 0x1ac 0x4b4 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x1ac 0x4b4 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0 0x4b8 0x778 0x0 0x1
-#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI 0x1b0 0x4b8 0x688 0x1 0x1
-#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID 0x1b0 0x4b8 0x5e0 0x2 0x1
-#define MX6SL_PAD_LCD_DAT0__PWM1_OUT 0x1b0 0x4b8 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B 0x1b0 0x4b8 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x1b0 0x4b8 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00 0x1b0 0x4b8 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00 0x1b0 0x4b8 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b4 0x4bc 0x77c 0x0 0x1
-#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO 0x1b4 0x4bc 0x684 0x1 0x1
-#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x1b4 0x4bc 0x5dc 0x2 0x2
-#define MX6SL_PAD_LCD_DAT1__PWM2_OUT 0x1b4 0x4bc 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS 0x1b4 0x4bc 0x5f0 0x4 0x1
-#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x1b4 0x4bc 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01 0x1b4 0x4bc 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01 0x1b4 0x4bc 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b8 0x4c0 0x7a0 0x0 0x1
-#define MX6SL_PAD_LCD_DAT10__KEY_COL1 0x1b8 0x4c0 0x738 0x1 0x1
-#define MX6SL_PAD_LCD_DAT10__CSI_DATA07 0x1b8 0x4c0 0x64c 0x2 0x1
-#define MX6SL_PAD_LCD_DAT10__EIM_DATA04 0x1b8 0x4c0 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO 0x1b8 0x4c0 0x6a0 0x4 0x2
-#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x1b8 0x4c0 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10 0x1b8 0x4c0 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10 0x1b8 0x4c0 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1bc 0x4c4 0x7a4 0x0 0x1
-#define MX6SL_PAD_LCD_DAT11__KEY_ROW1 0x1bc 0x4c4 0x758 0x1 0x1
-#define MX6SL_PAD_LCD_DAT11__CSI_DATA06 0x1bc 0x4c4 0x648 0x2 0x1
-#define MX6SL_PAD_LCD_DAT11__EIM_DATA05 0x1bc 0x4c4 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 0x1bc 0x4c4 0x6ac 0x4 0x1
-#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x1bc 0x4c4 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11 0x1bc 0x4c4 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11 0x1bc 0x4c4 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1c0 0x4c8 0x7a8 0x0 0x1
-#define MX6SL_PAD_LCD_DAT12__KEY_COL2 0x1c0 0x4c8 0x73c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT12__CSI_DATA05 0x1c0 0x4c8 0x644 0x2 0x1
-#define MX6SL_PAD_LCD_DAT12__EIM_DATA06 0x1c0 0x4c8 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B 0x1c0 0x4c8 0x818 0x4 0x2
-#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B 0x1c0 0x4c8 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x1c0 0x4c8 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12 0x1c0 0x4c8 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12 0x1c0 0x4c8 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1c4 0x4cc 0x7ac 0x0 0x1
-#define MX6SL_PAD_LCD_DAT13__KEY_ROW2 0x1c4 0x4cc 0x75c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT13__CSI_DATA04 0x1c4 0x4cc 0x640 0x2 0x1
-#define MX6SL_PAD_LCD_DAT13__EIM_DATA07 0x1c4 0x4cc 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B 0x1c4 0x4cc 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B 0x1c4 0x4cc 0x818 0x4 0x3
-#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x1c4 0x4cc 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13 0x1c4 0x4cc 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13 0x1c4 0x4cc 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1c8 0x4d0 0x7b0 0x0 0x1
-#define MX6SL_PAD_LCD_DAT14__KEY_COL3 0x1c8 0x4d0 0x740 0x1 0x1
-#define MX6SL_PAD_LCD_DAT14__CSI_DATA03 0x1c8 0x4d0 0x63c 0x2 0x1
-#define MX6SL_PAD_LCD_DAT14__EIM_DATA08 0x1c8 0x4d0 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA 0x1c8 0x4d0 0x81c 0x4 0x2
-#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA 0x1c8 0x4d0 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x1c8 0x4d0 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14 0x1c8 0x4d0 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14 0x1c8 0x4d0 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1cc 0x4d4 0x7b4 0x0 0x1
-#define MX6SL_PAD_LCD_DAT15__KEY_ROW3 0x1cc 0x4d4 0x760 0x1 0x1
-#define MX6SL_PAD_LCD_DAT15__CSI_DATA02 0x1cc 0x4d4 0x638 0x2 0x1
-#define MX6SL_PAD_LCD_DAT15__EIM_DATA09 0x1cc 0x4d4 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA 0x1cc 0x4d4 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA 0x1cc 0x4d4 0x81c 0x4 0x3
-#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x1cc 0x4d4 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15 0x1cc 0x4d4 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15 0x1cc 0x4d4 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1d0 0x4d8 0x7b8 0x0 0x1
-#define MX6SL_PAD_LCD_DAT16__KEY_COL4 0x1d0 0x4d8 0x744 0x1 0x1
-#define MX6SL_PAD_LCD_DAT16__CSI_DATA01 0x1d0 0x4d8 0x634 0x2 0x1
-#define MX6SL_PAD_LCD_DAT16__EIM_DATA10 0x1d0 0x4d8 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT16__I2C2_SCL 0x1d0 0x4d8 0x724 0x4 0x3
-#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x1d0 0x4d8 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16 0x1d0 0x4d8 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24 0x1d0 0x4d8 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1d4 0x4dc 0x7bc 0x0 0x1
-#define MX6SL_PAD_LCD_DAT17__KEY_ROW4 0x1d4 0x4dc 0x764 0x1 0x1
-#define MX6SL_PAD_LCD_DAT17__CSI_DATA00 0x1d4 0x4dc 0x630 0x2 0x1
-#define MX6SL_PAD_LCD_DAT17__EIM_DATA11 0x1d4 0x4dc 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT17__I2C2_SDA 0x1d4 0x4dc 0x728 0x4 0x3
-#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x1d4 0x4dc 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17 0x1d4 0x4dc 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25 0x1d4 0x4dc 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1d8 0x4e0 0x7c0 0x0 0x1
-#define MX6SL_PAD_LCD_DAT18__KEY_COL5 0x1d8 0x4e0 0x748 0x1 0x1
-#define MX6SL_PAD_LCD_DAT18__CSI_DATA15 0x1d8 0x4e0 0x66c 0x2 0x0
-#define MX6SL_PAD_LCD_DAT18__EIM_DATA12 0x1d8 0x4e0 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1 0x1d8 0x4e0 0x710 0x4 0x1
-#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x1d8 0x4e0 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18 0x1d8 0x4e0 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26 0x1d8 0x4e0 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1dc 0x4e4 0x7c4 0x0 0x1
-#define MX6SL_PAD_LCD_DAT19__KEY_ROW5 0x1dc 0x4e4 0x768 0x1 0x1
-#define MX6SL_PAD_LCD_DAT19__CSI_DATA14 0x1dc 0x4e4 0x668 0x2 0x0
-#define MX6SL_PAD_LCD_DAT19__EIM_DATA13 0x1dc 0x4e4 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2 0x1dc 0x4e4 0x714 0x4 0x1
-#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x1dc 0x4e4 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19 0x1dc 0x4e4 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27 0x1dc 0x4e4 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1e0 0x4e8 0x780 0x0 0x1
-#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 0x1e0 0x4e8 0x68c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT 0x1e0 0x4e8 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_DAT2__PWM3_OUT 0x1e0 0x4e8 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT2__AUD4_RXC 0x1e0 0x4e8 0x5ec 0x4 0x1
-#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x1e0 0x4e8 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02 0x1e0 0x4e8 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02 0x1e0 0x4e8 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1e4 0x4ec 0x7c8 0x0 0x1
-#define MX6SL_PAD_LCD_DAT20__KEY_COL6 0x1e4 0x4ec 0x74c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT20__CSI_DATA13 0x1e4 0x4ec 0x664 0x2 0x0
-#define MX6SL_PAD_LCD_DAT20__EIM_DATA14 0x1e4 0x4ec 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1 0x1e4 0x4ec 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x1e4 0x4ec 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20 0x1e4 0x4ec 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28 0x1e4 0x4ec 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1e8 0x4f0 0x7cc 0x0 0x1
-#define MX6SL_PAD_LCD_DAT21__KEY_ROW6 0x1e8 0x4f0 0x76c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT21__CSI_DATA12 0x1e8 0x4f0 0x660 0x2 0x0
-#define MX6SL_PAD_LCD_DAT21__EIM_DATA15 0x1e8 0x4f0 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2 0x1e8 0x4f0 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x1e8 0x4f0 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21 0x1e8 0x4f0 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29 0x1e8 0x4f0 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1ec 0x4f4 0x7d0 0x0 0x1
-#define MX6SL_PAD_LCD_DAT22__KEY_COL7 0x1ec 0x4f4 0x750 0x1 0x1
-#define MX6SL_PAD_LCD_DAT22__CSI_DATA11 0x1ec 0x4f4 0x65c 0x2 0x1
-#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B 0x1ec 0x4f4 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3 0x1ec 0x4f4 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x1ec 0x4f4 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22 0x1ec 0x4f4 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30 0x1ec 0x4f4 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1f0 0x4f8 0x7d4 0x0 0x1
-#define MX6SL_PAD_LCD_DAT23__KEY_ROW7 0x1f0 0x4f8 0x770 0x1 0x1
-#define MX6SL_PAD_LCD_DAT23__CSI_DATA10 0x1f0 0x4f8 0x658 0x2 0x1
-#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B 0x1f0 0x4f8 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN 0x1f0 0x4f8 0x718 0x4 0x1
-#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x1f0 0x4f8 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23 0x1f0 0x4f8 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31 0x1f0 0x4f8 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1f4 0x4fc 0x784 0x0 0x1
-#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK 0x1f4 0x4fc 0x67c 0x1 0x1
-#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B 0x1f4 0x4fc 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_DAT3__PWM4_OUT 0x1f4 0x4fc 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT3__AUD4_RXD 0x1f4 0x4fc 0x5e4 0x4 0x1
-#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x1f4 0x4fc 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03 0x1f4 0x4fc 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03 0x1f4 0x4fc 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1f8 0x500 0x788 0x0 0x1
-#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 0x1f8 0x500 0x690 0x1 0x1
-#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC 0x1f8 0x500 0x678 0x2 0x2
-#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB 0x1f8 0x500 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT4__AUD4_TXC 0x1f8 0x500 0x5f4 0x4 0x1
-#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x1f8 0x500 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04 0x1f8 0x500 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04 0x1f8 0x500 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1fc 0x504 0x78c 0x0 0x1
-#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 0x1fc 0x504 0x694 0x1 0x1
-#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC 0x1fc 0x504 0x670 0x2 0x2
-#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B 0x1fc 0x504 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS 0x1fc 0x504 0x5f8 0x4 0x1
-#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x1fc 0x504 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05 0x1fc 0x504 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05 0x1fc 0x504 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x200 0x508 0x790 0x0 0x1
-#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 0x200 0x508 0x698 0x1 0x1
-#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK 0x200 0x508 0x674 0x2 0x2
-#define MX6SL_PAD_LCD_DAT6__EIM_DATA00 0x200 0x508 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT6__AUD4_TXD 0x200 0x508 0x5e8 0x4 0x1
-#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x200 0x508 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06 0x200 0x508 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06 0x200 0x508 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x204 0x50c 0x794 0x0 0x1
-#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY 0x204 0x50c 0x680 0x1 0x1
-#define MX6SL_PAD_LCD_DAT7__CSI_MCLK 0x204 0x50c 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_DAT7__EIM_DATA01 0x204 0x50c 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT 0x204 0x50c 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x204 0x50c 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07 0x204 0x50c 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07 0x204 0x50c 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x208 0x510 0x798 0x0 0x1
-#define MX6SL_PAD_LCD_DAT8__KEY_COL0 0x208 0x510 0x734 0x1 0x1
-#define MX6SL_PAD_LCD_DAT8__CSI_DATA09 0x208 0x510 0x654 0x2 0x1
-#define MX6SL_PAD_LCD_DAT8__EIM_DATA02 0x208 0x510 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK 0x208 0x510 0x69c 0x4 0x2
-#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x208 0x510 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08 0x208 0x510 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08 0x208 0x510 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x20c 0x514 0x79c 0x0 0x1
-#define MX6SL_PAD_LCD_DAT9__KEY_ROW0 0x20c 0x514 0x754 0x1 0x1
-#define MX6SL_PAD_LCD_DAT9__CSI_DATA08 0x20c 0x514 0x650 0x2 0x1
-#define MX6SL_PAD_LCD_DAT9__EIM_DATA03 0x20c 0x514 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI 0x20c 0x514 0x6a4 0x4 0x2
-#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x20c 0x514 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09 0x20c 0x514 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09 0x20c 0x514 0x000 0x7 0x0
-#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x210 0x518 0x000 0x0 0x0
-#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5 0x210 0x518 0x870 0x1 0x2
-#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E 0x210 0x518 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B 0x210 0x518 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA 0x210 0x518 0x804 0x4 0x2
-#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA 0x210 0x518 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x210 0x518 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x214 0x51c 0x774 0x0 0x0
-#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6 0x214 0x51c 0x874 0x1 0x2
-#define MX6SL_PAD_LCD_HSYNC__LCD_CS 0x214 0x51c 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B 0x214 0x51c 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA 0x214 0x51c 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA 0x214 0x51c 0x804 0x4 0x3
-#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x214 0x51c 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x214 0x51c 0x000 0x6 0x0
-#define MX6SL_PAD_LCD_RESET__LCD_RESET 0x218 0x520 0x000 0x0 0x0
-#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B 0x218 0x520 0x880 0x1 0x1
-#define MX6SL_PAD_LCD_RESET__LCD_BUSY 0x218 0x520 0x774 0x2 0x1
-#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B 0x218 0x520 0x884 0x3 0x1
-#define MX6SL_PAD_LCD_RESET__UART2_CTS_B 0x218 0x520 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_RESET__UART2_RTS_B 0x218 0x520 0x800 0x4 0x2
-#define MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x218 0x520 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY 0x218 0x520 0x62c 0x6 0x1
-#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x21c 0x524 0x000 0x0 0x0
-#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7 0x21c 0x524 0x878 0x1 0x2
-#define MX6SL_PAD_LCD_VSYNC__LCD_RS 0x21c 0x524 0x000 0x2 0x0
-#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B 0x21c 0x524 0x000 0x3 0x0
-#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B 0x21c 0x524 0x800 0x4 0x3
-#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B 0x21c 0x524 0x000 0x4 0x0
-#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x21c 0x524 0x000 0x5 0x0
-#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x21c 0x524 0x000 0x6 0x0
-#define MX6SL_PAD_PWM1__PWM1_OUT 0x220 0x528 0x000 0x0 0x0
-#define MX6SL_PAD_PWM1__CCM_CLKO 0x220 0x528 0x000 0x1 0x0
-#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT 0x220 0x528 0x000 0x2 0x0
-#define MX6SL_PAD_PWM1__FEC_REF_OUT 0x220 0x528 0x000 0x3 0x0
-#define MX6SL_PAD_PWM1__CSI_MCLK 0x220 0x528 0x000 0x4 0x0
-#define MX6SL_PAD_PWM1__GPIO3_IO23 0x220 0x528 0x000 0x5 0x0
-#define MX6SL_PAD_PWM1__EPIT1_OUT 0x220 0x528 0x000 0x6 0x0
-#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0
-#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x224 0x52c 0x72c 0x1 0x2
-#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT 0x224 0x52c 0x000 0x2 0x0
-#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID 0x224 0x52c 0x5e0 0x3 0x2
-#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x224 0x52c 0x62c 0x4 0x2
-#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21 0x224 0x52c 0x000 0x5 0x0
-#define MX6SL_PAD_REF_CLK_24M__SD3_WP 0x224 0x52c 0x84c 0x6 0x3
-#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0
-#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x228 0x530 0x730 0x1 0x2
-#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT 0x228 0x530 0x000 0x2 0x0
-#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x228 0x530 0x5dc 0x3 0x3
-#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL 0x228 0x530 0x000 0x4 0x0
-#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x228 0x530 0x000 0x5 0x0
-#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B 0x228 0x530 0x838 0x6 0x3
-#define MX6SL_PAD_SD1_CLK__SD1_CLK 0x22c 0x534 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_CLK__FEC_MDIO 0x22c 0x534 0x6f4 0x1 0x2
-#define MX6SL_PAD_SD1_CLK__KEY_COL0 0x22c 0x534 0x734 0x2 0x2
-#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4 0x22c 0x534 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x22c 0x534 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_CMD__SD1_CMD 0x230 0x538 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK 0x230 0x538 0x70c 0x1 0x2
-#define MX6SL_PAD_SD1_CMD__KEY_ROW0 0x230 0x538 0x754 0x2 0x2
-#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5 0x230 0x538 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_CMD__GPIO5_IO14 0x230 0x538 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x234 0x53c 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER 0x234 0x53c 0x708 0x1 0x2
-#define MX6SL_PAD_SD1_DAT0__KEY_COL1 0x234 0x53c 0x738 0x2 0x2
-#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6 0x234 0x53c 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x234 0x53c 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x238 0x540 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV 0x238 0x540 0x704 0x1 0x2
-#define MX6SL_PAD_SD1_DAT1__KEY_ROW1 0x238 0x540 0x758 0x2 0x2
-#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7 0x238 0x540 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x238 0x540 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x23c 0x544 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1 0x23c 0x544 0x6fc 0x1 0x2
-#define MX6SL_PAD_SD1_DAT2__KEY_COL2 0x23c 0x544 0x73c 0x2 0x2
-#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8 0x23c 0x544 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x23c 0x544 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x240 0x548 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0 0x240 0x548 0x000 0x1 0x0
-#define MX6SL_PAD_SD1_DAT3__KEY_ROW2 0x240 0x548 0x75c 0x2 0x2
-#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9 0x240 0x548 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x240 0x548 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x244 0x54c 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT4__FEC_MDC 0x244 0x54c 0x000 0x1 0x0
-#define MX6SL_PAD_SD1_DAT4__KEY_COL3 0x244 0x54c 0x740 0x2 0x2
-#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N 0x244 0x54c 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x244 0x54c 0x814 0x4 0x4
-#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x244 0x54c 0x000 0x4 0x0
-#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x244 0x54c 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2
-#define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2
-#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0
-#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5
-#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x24c 0x554 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN 0x24c 0x554 0x000 0x1 0x0
-#define MX6SL_PAD_SD1_DAT6__KEY_COL4 0x24c 0x554 0x744 0x2 0x2
-#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ 0x24c 0x554 0x000 0x3 0x0
-#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x24c 0x554 0x810 0x4 0x4
-#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x24c 0x554 0x000 0x4 0x0
-#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x24c 0x554 0x000 0x5 0x0
-#define MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x250 0x558 0x000 0x0 0x0
-#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1 0x250 0x558 0x000 0x1 0x0
-#define MX6SL_PAD_SD1_DAT7__KEY_ROW4 0x250 0x558 0x764 0x2 0x2
-#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY 0x250 0x558 0x62c 0x3 0x3
-#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x250 0x558 0x000 0x4 0x0
-#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x250 0x558 0x810 0x4 0x5
-#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x250 0x558 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_CLK__SD2_CLK 0x254 0x55c 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_CLK__AUD4_RXFS 0x254 0x55c 0x5f0 0x1 0x2
-#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK 0x254 0x55c 0x6b0 0x2 0x2
-#define MX6SL_PAD_SD2_CLK__CSI_DATA00 0x254 0x55c 0x630 0x3 0x2
-#define MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x254 0x55c 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_CMD__SD2_CMD 0x258 0x560 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_CMD__AUD4_RXC 0x258 0x560 0x5ec 0x1 0x2
-#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 0x258 0x560 0x6c0 0x2 0x2
-#define MX6SL_PAD_SD2_CMD__CSI_DATA01 0x258 0x560 0x634 0x3 0x2
-#define MX6SL_PAD_SD2_CMD__EPIT1_OUT 0x258 0x560 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x258 0x560 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x25c 0x564 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT0__AUD4_RXD 0x25c 0x564 0x5e4 0x1 0x2
-#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI 0x25c 0x564 0x6bc 0x2 0x2
-#define MX6SL_PAD_SD2_DAT0__CSI_DATA02 0x25c 0x564 0x638 0x3 0x2
-#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B 0x25c 0x564 0x818 0x4 0x4
-#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B 0x25c 0x564 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x25c 0x564 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x260 0x568 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT1__AUD4_TXC 0x260 0x568 0x5f4 0x1 0x2
-#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO 0x260 0x568 0x6b8 0x2 0x2
-#define MX6SL_PAD_SD2_DAT1__CSI_DATA03 0x260 0x568 0x63c 0x3 0x2
-#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B 0x260 0x568 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B 0x260 0x568 0x818 0x4 0x5
-#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x260 0x568 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x264 0x56c 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS 0x264 0x56c 0x5f8 0x1 0x2
-#define MX6SL_PAD_SD2_DAT2__FEC_COL 0x264 0x56c 0x6f0 0x2 0x1
-#define MX6SL_PAD_SD2_DAT2__CSI_DATA04 0x264 0x56c 0x640 0x3 0x2
-#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA 0x264 0x56c 0x81c 0x4 0x4
-#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA 0x264 0x56c 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x264 0x56c 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x268 0x570 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT3__AUD4_TXD 0x268 0x570 0x5e8 0x1 0x2
-#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK 0x268 0x570 0x700 0x2 0x1
-#define MX6SL_PAD_SD2_DAT3__CSI_DATA05 0x268 0x570 0x644 0x3 0x2
-#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA 0x268 0x570 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA 0x268 0x570 0x81c 0x4 0x5
-#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x268 0x570 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x26c 0x574 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT4__SD3_DATA4 0x26c 0x574 0x83c 0x1 0x1
-#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA 0x26c 0x574 0x804 0x2 0x4
-#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA 0x26c 0x574 0x000 0x2 0x0
-#define MX6SL_PAD_SD2_DAT4__CSI_DATA06 0x26c 0x574 0x648 0x3 0x2
-#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x26c 0x574 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x26c 0x574 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x270 0x578 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT5__SD3_DATA5 0x270 0x578 0x840 0x1 0x1
-#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA 0x270 0x578 0x000 0x2 0x0
-#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA 0x270 0x578 0x804 0x2 0x5
-#define MX6SL_PAD_SD2_DAT5__CSI_DATA07 0x270 0x578 0x64c 0x3 0x2
-#define MX6SL_PAD_SD2_DAT5__SPDIF_IN 0x270 0x578 0x7f0 0x4 0x2
-#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31 0x270 0x578 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x274 0x57c 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT6__SD3_DATA6 0x274 0x57c 0x844 0x1 0x1
-#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B 0x274 0x57c 0x800 0x2 0x4
-#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B 0x274 0x57c 0x000 0x2 0x0
-#define MX6SL_PAD_SD2_DAT6__CSI_DATA08 0x274 0x57c 0x650 0x3 0x2
-#define MX6SL_PAD_SD2_DAT6__SD2_WP 0x274 0x57c 0x834 0x4 0x2
-#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x274 0x57c 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x278 0x580 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_DAT7__SD3_DATA7 0x278 0x580 0x848 0x1 0x1
-#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B 0x278 0x580 0x000 0x2 0x0
-#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B 0x278 0x580 0x800 0x2 0x5
-#define MX6SL_PAD_SD2_DAT7__CSI_DATA09 0x278 0x580 0x654 0x3 0x2
-#define MX6SL_PAD_SD2_DAT7__SD2_CD_B 0x278 0x580 0x830 0x4 0x2
-#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x278 0x580 0x000 0x5 0x0
-#define MX6SL_PAD_SD2_RST__SD2_RESET 0x27c 0x584 0x000 0x0 0x0
-#define MX6SL_PAD_SD2_RST__FEC_REF_OUT 0x27c 0x584 0x000 0x1 0x0
-#define MX6SL_PAD_SD2_RST__WDOG2_B 0x27c 0x584 0x000 0x2 0x0
-#define MX6SL_PAD_SD2_RST__SPDIF_OUT 0x27c 0x584 0x000 0x3 0x0
-#define MX6SL_PAD_SD2_RST__CSI_MCLK 0x27c 0x584 0x000 0x4 0x0
-#define MX6SL_PAD_SD2_RST__GPIO4_IO27 0x27c 0x584 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_CLK__SD3_CLK 0x280 0x588 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_CLK__AUD5_RXFS 0x280 0x588 0x608 0x1 0x1
-#define MX6SL_PAD_SD3_CLK__KEY_COL5 0x280 0x588 0x748 0x2 0x2
-#define MX6SL_PAD_SD3_CLK__CSI_DATA10 0x280 0x588 0x658 0x3 0x2
-#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x280 0x588 0x000 0x4 0x0
-#define MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x280 0x588 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR 0x280 0x588 0x000 0x6 0x0
-#define MX6SL_PAD_SD3_CMD__SD3_CMD 0x284 0x58c 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_CMD__AUD5_RXC 0x284 0x58c 0x604 0x1 0x1
-#define MX6SL_PAD_SD3_CMD__KEY_ROW5 0x284 0x58c 0x768 0x2 0x2
-#define MX6SL_PAD_SD3_CMD__CSI_DATA11 0x284 0x58c 0x65c 0x3 0x2
-#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID 0x284 0x58c 0x5e0 0x4 0x3
-#define MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x284 0x58c 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR 0x284 0x58c 0x000 0x6 0x0
-#define MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x288 0x590 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_DAT0__AUD5_RXD 0x288 0x590 0x5fc 0x1 0x1
-#define MX6SL_PAD_SD3_DAT0__KEY_COL6 0x288 0x590 0x74c 0x2 0x2
-#define MX6SL_PAD_SD3_DAT0__CSI_DATA12 0x288 0x590 0x660 0x3 0x1
-#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x288 0x590 0x5dc 0x4 0x4
-#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x288 0x590 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x28c 0x594 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_DAT1__AUD5_TXC 0x28c 0x594 0x60c 0x1 0x1
-#define MX6SL_PAD_SD3_DAT1__KEY_ROW6 0x28c 0x594 0x76c 0x2 0x2
-#define MX6SL_PAD_SD3_DAT1__CSI_DATA13 0x28c 0x594 0x664 0x3 0x1
-#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT 0x28c 0x594 0x000 0x4 0x0
-#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x28c 0x594 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B 0x28c 0x594 0x000 0x6 0x0
-#define MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x290 0x598 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS 0x290 0x598 0x610 0x1 0x1
-#define MX6SL_PAD_SD3_DAT2__KEY_COL7 0x290 0x598 0x750 0x2 0x2
-#define MX6SL_PAD_SD3_DAT2__CSI_DATA14 0x290 0x598 0x668 0x3 0x1
-#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT 0x290 0x598 0x000 0x4 0x0
-#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x290 0x598 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3
-#define MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x294 0x59c 0x000 0x0 0x0
-#define MX6SL_PAD_SD3_DAT3__AUD5_TXD 0x294 0x59c 0x600 0x1 0x1
-#define MX6SL_PAD_SD3_DAT3__KEY_ROW7 0x294 0x59c 0x770 0x2 0x2
-#define MX6SL_PAD_SD3_DAT3__CSI_DATA15 0x294 0x59c 0x66c 0x3 0x1
-#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT 0x294 0x59c 0x000 0x4 0x0
-#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x294 0x59c 0x000 0x5 0x0
-#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC 0x294 0x59c 0x824 0x6 0x2
-#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x298 0x5a0 0x7fc 0x0 0x0
-#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x298 0x5a0 0x000 0x0 0x0
-#define MX6SL_PAD_UART1_RXD__PWM1_OUT 0x298 0x5a0 0x000 0x1 0x0
-#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA 0x298 0x5a0 0x814 0x2 0x6
-#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA 0x298 0x5a0 0x000 0x2 0x0
-#define MX6SL_PAD_UART1_RXD__FEC_COL 0x298 0x5a0 0x6f0 0x3 0x2
-#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA 0x298 0x5a0 0x81c 0x4 0x6
-#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA 0x298 0x5a0 0x000 0x4 0x0
-#define MX6SL_PAD_UART1_RXD__GPIO3_IO16 0x298 0x5a0 0x000 0x5 0x0
-#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x29c 0x5a4 0x000 0x0 0x0
-#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA 0x29c 0x5a4 0x7fc 0x0 0x1
-#define MX6SL_PAD_UART1_TXD__PWM2_OUT 0x29c 0x5a4 0x000 0x1 0x0
-#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA 0x29c 0x5a4 0x000 0x2 0x0
-#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA 0x29c 0x5a4 0x814 0x2 0x7
-#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK 0x29c 0x5a4 0x700 0x3 0x2
-#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA 0x29c 0x5a4 0x000 0x4 0x0
-#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA 0x29c 0x5a4 0x81c 0x4 0x7
-#define MX6SL_PAD_UART1_TXD__GPIO3_IO17 0x29c 0x5a4 0x000 0x5 0x0
-#define MX6SL_PAD_UART1_TXD__UART5_DCD_B 0x29c 0x5a4 0x000 0x7 0x0
-#define MX6SL_PAD_WDOG_B__WDOG1_B 0x2a0 0x5a8 0x000 0x0 0x0
-#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x2a0 0x5a8 0x000 0x1 0x0
-#define MX6SL_PAD_WDOG_B__UART5_RI_B 0x2a0 0x5a8 0x000 0x2 0x0
-#define MX6SL_PAD_WDOG_B__GPIO3_IO18 0x2a0 0x5a8 0x000 0x5 0x0
-
-#endif /* __DTS_IMX6SL_PINFUNC_H */
diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi
deleted file mode 100644
index 271f4b9..0000000
--- a/arch/arm/dts/imx6sl.dtsi
+++ /dev/null
@@ -1,1005 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2013 Freescale Semiconductor, Inc.
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6sl-pinfunc.h"
-#include <dt-bindings/clock/imx6sl-clock.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- /*
- * The decompressor and also some bootloaders rely on a
- * pre-existing /chosen node to be available to insert the
- * command line and merge other ATAGS info.
- */
- chosen {};
-
- aliases {
- ethernet0 = &fec;
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- mmc0 = &usdhc1;
- mmc1 = &usdhc2;
- mmc2 = &usdhc3;
- mmc3 = &usdhc4;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- spi0 = &ecspi1;
- spi1 = &ecspi2;
- spi2 = &ecspi3;
- spi3 = &ecspi4;
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- usb2 = &usbh;
- usbphy0 = &usbphy1;
- usbphy1 = &usbphy2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&L2>;
- operating-points =
- /* kHz uV */
- <996000 1275000>,
- <792000 1175000>,
- <396000 975000>;
- fsl,soc-operating-points =
- /* ARM kHz SOC-PU uV */
- <996000 1225000>,
- <792000 1175000>,
- <396000 1175000>;
- clock-latency = <61036>; /* two CLK32 periods */
- #cooling-cells = <2>;
- clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
- <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
- <&clks IMX6SL_CLK_PLL1_SYS>;
- clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
- arm-supply = <®_arm>;
- pu-supply = <®_pu>;
- soc-supply = <®_soc>;
- nvmem-cells = <&cpu_speed_grade>;
- nvmem-cell-names = "speed_grade";
- };
- };
-
- clocks {
- ckil {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
- osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupt-parent = <&gpc>;
- interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- usbphynop1: usbphynop1 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gpc>;
- ranges;
-
- ocram: sram@900000 {
- compatible = "mmio-sram";
- reg = <0x00900000 0x20000>;
- clocks = <&clks IMX6SL_CLK_OCRAM>;
- };
-
- intc: interrupt-controller@a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
- L2: cache-controller@a02000 {
- compatible = "arm,pl310-cache";
- reg = <0x00a02000 0x1000>;
- interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
- cache-unified;
- cache-level = <2>;
- arm,tag-latency = <4 2 3>;
- arm,data-latency = <4 2 3>;
- };
-
- aips1: bus@2000000 {
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x02000000 0x100000>;
- ranges;
-
- spba: spba-bus@2000000 {
- compatible = "fsl,spba-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x02000000 0x40000>;
- ranges;
-
- spdif: spdif@2004000 {
- compatible = "fsl,imx6sl-spdif",
- "fsl,imx35-spdif";
- reg = <0x02004000 0x4000>;
- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 14 18 0>,
- <&sdma 15 18 0>;
- dma-names = "rx", "tx";
- clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
- <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
- <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
- <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
- <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
- clock-names = "core", "rxtx0",
- "rxtx1", "rxtx2",
- "rxtx3", "rxtx4",
- "rxtx5", "rxtx6",
- "rxtx7", "spba";
- status = "disabled";
- };
-
- ecspi1: spi@2008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
- reg = <0x02008000 0x4000>;
- interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_ECSPI1>,
- <&clks IMX6SL_CLK_ECSPI1>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi2: spi@200c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
- reg = <0x0200c000 0x4000>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_ECSPI2>,
- <&clks IMX6SL_CLK_ECSPI2>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi3: spi@2010000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
- reg = <0x02010000 0x4000>;
- interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_ECSPI3>,
- <&clks IMX6SL_CLK_ECSPI3>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi4: spi@2014000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
- reg = <0x02014000 0x4000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_ECSPI4>,
- <&clks IMX6SL_CLK_ECSPI4>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart5: serial@2018000 {
- compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
- reg = <0x02018000 0x4000>;
- interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_UART>,
- <&clks IMX6SL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart1: serial@2020000 {
- compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
- reg = <0x02020000 0x4000>;
- interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_UART>,
- <&clks IMX6SL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart2: serial@2024000 {
- compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
- reg = <0x02024000 0x4000>;
- interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_UART>,
- <&clks IMX6SL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- ssi1: ssi@2028000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx6sl-ssi",
- "fsl,imx51-ssi";
- reg = <0x02028000 0x4000>;
- interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
- <&clks IMX6SL_CLK_SSI1>;
- clock-names = "ipg", "baud";
- dmas = <&sdma 37 1 0>,
- <&sdma 38 1 0>;
- dma-names = "rx", "tx";
- fsl,fifo-depth = <15>;
- status = "disabled";
- };
-
- ssi2: ssi@202c000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx6sl-ssi",
- "fsl,imx51-ssi";
- reg = <0x0202c000 0x4000>;
- interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
- <&clks IMX6SL_CLK_SSI2>;
- clock-names = "ipg", "baud";
- dmas = <&sdma 41 1 0>,
- <&sdma 42 1 0>;
- dma-names = "rx", "tx";
- fsl,fifo-depth = <15>;
- status = "disabled";
- };
-
- ssi3: ssi@2030000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx6sl-ssi",
- "fsl,imx51-ssi";
- reg = <0x02030000 0x4000>;
- interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
- <&clks IMX6SL_CLK_SSI3>;
- clock-names = "ipg", "baud";
- dmas = <&sdma 45 1 0>,
- <&sdma 46 1 0>;
- dma-names = "rx", "tx";
- fsl,fifo-depth = <15>;
- status = "disabled";
- };
-
- uart3: serial@2034000 {
- compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
- reg = <0x02034000 0x4000>;
- interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_UART>,
- <&clks IMX6SL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart4: serial@2038000 {
- compatible = "fsl,imx6sl-uart",
- "fsl,imx6q-uart", "fsl,imx21-uart";
- reg = <0x02038000 0x4000>;
- interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_UART>,
- <&clks IMX6SL_CLK_UART_SERIAL>;
- clock-names = "ipg", "per";
- dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
- };
-
- pwm1: pwm@2080000 {
- #pwm-cells = <3>;
- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
- reg = <0x02080000 0x4000>;
- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PERCLK>,
- <&clks IMX6SL_CLK_PWM1>;
- clock-names = "ipg", "per";
- };
-
- pwm2: pwm@2084000 {
- #pwm-cells = <3>;
- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
- reg = <0x02084000 0x4000>;
- interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PERCLK>,
- <&clks IMX6SL_CLK_PWM2>;
- clock-names = "ipg", "per";
- };
-
- pwm3: pwm@2088000 {
- #pwm-cells = <3>;
- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
- reg = <0x02088000 0x4000>;
- interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PERCLK>,
- <&clks IMX6SL_CLK_PWM3>;
- clock-names = "ipg", "per";
- };
-
- pwm4: pwm@208c000 {
- #pwm-cells = <3>;
- compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
- reg = <0x0208c000 0x4000>;
- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_PERCLK>,
- <&clks IMX6SL_CLK_PWM4>;
- clock-names = "ipg", "per";
- };
-
- gpt: timer@2098000 {
- compatible = "fsl,imx6sl-gpt";
- reg = <0x02098000 0x4000>;
- interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_GPT>,
- <&clks IMX6SL_CLK_GPT_SERIAL>;
- clock-names = "ipg", "per";
- };
-
- gpio1: gpio@209c000 {
- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
- reg = <0x0209c000 0x4000>;
- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
- <0 67 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
- <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
- <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
- <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
- <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
- <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
- };
-
- gpio2: gpio@20a0000 {
- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
- reg = <0x020a0000 0x4000>;
- interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
- <0 69 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
- <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
- <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
- <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
- <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
- <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
- <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
- };
-
- gpio3: gpio@20a4000 {
- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
- reg = <0x020a4000 0x4000>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
- <0 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
- <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
- <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
- <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
- <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
- <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
- <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
- <&iomuxc 31 102 1>;
- };
-
- gpio4: gpio@20a8000 {
- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
- reg = <0x020a8000 0x4000>;
- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
- <0 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
- <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
- <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
- <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
- <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
- <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
- <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
- <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
- <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
- <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
- <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
- <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
- <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
- <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
- <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
- };
-
- gpio5: gpio@20ac000 {
- compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
- reg = <0x020ac000 0x4000>;
- interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
- <0 75 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
- <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
- <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
- <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
- <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
- <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
- <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
- <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
- <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
- <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
- <&iomuxc 21 161 1>;
- };
-
- kpp: keypad@20b8000 {
- compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
- reg = <0x020b8000 0x4000>;
- interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_IPG>;
- status = "disabled";
- };
-
- wdog1: watchdog@20bc000 {
- compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
- reg = <0x020bc000 0x4000>;
- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_IPG>;
- };
-
- wdog2: watchdog@20c0000 {
- compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
- reg = <0x020c0000 0x4000>;
- interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_IPG>;
- status = "disabled";
- };
-
- clks: clock-controller@20c4000 {
- compatible = "fsl,imx6sl-ccm";
- reg = <0x020c4000 0x4000>;
- interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
- <0 88 IRQ_TYPE_LEVEL_HIGH>;
- #clock-cells = <1>;
- };
-
- anatop: anatop@20c8000 {
- compatible = "fsl,imx6sl-anatop",
- "fsl,imx6q-anatop",
- "syscon", "simple-mfd";
- reg = <0x020c8000 0x1000>;
- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
- <0 54 IRQ_TYPE_LEVEL_HIGH>,
- <0 127 IRQ_TYPE_LEVEL_HIGH>;
-
- reg_vdd1p1: regulator-1p1 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd1p1";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- anatop-reg-offset = <0x110>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <4>;
- anatop-min-voltage = <800000>;
- anatop-max-voltage = <1375000>;
- anatop-enable-bit = <0>;
- };
-
- reg_vdd3p0: regulator-3p0 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd3p0";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <3150000>;
- regulator-always-on;
- anatop-reg-offset = <0x120>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <0>;
- anatop-min-voltage = <2625000>;
- anatop-max-voltage = <3400000>;
- anatop-enable-bit = <0>;
- };
-
- reg_vdd2p5: regulator-2p5 {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vdd2p5";
- regulator-min-microvolt = <2250000>;
- regulator-max-microvolt = <2750000>;
- regulator-always-on;
- anatop-reg-offset = <0x130>;
- anatop-vol-bit-shift = <8>;
- anatop-vol-bit-width = <5>;
- anatop-min-bit-val = <0>;
- anatop-min-voltage = <2100000>;
- anatop-max-voltage = <2850000>;
- anatop-enable-bit = <0>;
- };
-
- reg_arm: regulator-vddcore {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddarm";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <0>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <24>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
-
- reg_pu: regulator-vddpu {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddpu";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <9>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <26>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
-
- reg_soc: regulator-vddsoc {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddsoc";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <18>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <28>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1450000>;
- };
-
- tempmon: tempmon {
- compatible = "fsl,imx6q-tempmon";
- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gpc>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
- };
- };
-
- usbphy1: usbphy@20c9000 {
- compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
- reg = <0x020c9000 0x1000>;
- interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USBPHY1>;
- fsl,anatop = <&anatop>;
- };
-
- usbphy2: usbphy@20ca000 {
- compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
- reg = <0x020ca000 0x1000>;
- interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USBPHY2>;
- fsl,anatop = <&anatop>;
- };
-
- snvs: snvs@20cc000 {
- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
- reg = <0x020cc000 0x4000>;
-
- snvs_rtc: snvs-rtc-lp {
- compatible = "fsl,sec-v4.0-mon-rtc-lp";
- regmap = <&snvs>;
- offset = <0x34>;
- interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
- <0 20 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- snvs_poweroff: snvs-poweroff {
- compatible = "syscon-poweroff";
- regmap = <&snvs>;
- offset = <0x38>;
- value = <0x60>;
- mask = <0x60>;
- status = "disabled";
- };
- };
-
- epit1: epit@20d0000 {
- reg = <0x020d0000 0x4000>;
- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- epit2: epit@20d4000 {
- reg = <0x020d4000 0x4000>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- src: reset-controller@20d8000 {
- compatible = "fsl,imx6sl-src", "fsl,imx51-src";
- reg = <0x020d8000 0x4000>;
- interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
- <0 96 IRQ_TYPE_LEVEL_HIGH>;
- #reset-cells = <1>;
- };
-
- gpc: gpc@20dc000 {
- compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
- reg = <0x020dc000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&intc>;
- clocks = <&clks IMX6SL_CLK_IPG>;
- clock-names = "ipg";
-
- pgc {
- #address-cells = <1>;
- #size-cells = <0>;
-
- power-domain@0 {
- reg = <0>;
- #power-domain-cells = <0>;
- };
-
- pd_pu: power-domain@1 {
- reg = <1>;
- #power-domain-cells = <0>;
- power-supply = <®_pu>;
- clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
- <&clks IMX6SL_CLK_GPU2D_PODF>;
- };
-
- pd_disp: power-domain@2 {
- reg = <2>;
- #power-domain-cells = <0>;
- clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
- <&clks IMX6SL_CLK_LCDIF_PIX>,
- <&clks IMX6SL_CLK_EPDC_AXI>,
- <&clks IMX6SL_CLK_EPDC_PIX>,
- <&clks IMX6SL_CLK_PXP_AXI>;
- };
- };
- };
-
- gpr: iomuxc-gpr@20e0000 {
- compatible = "fsl,imx6sl-iomuxc-gpr",
- "fsl,imx6q-iomuxc-gpr", "syscon";
- reg = <0x020e0000 0x38>;
- };
-
- iomuxc: pinctrl@20e0000 {
- compatible = "fsl,imx6sl-iomuxc";
- reg = <0x020e0000 0x4000>;
- };
-
- csi: csi@20e4000 {
- reg = <0x020e4000 0x4000>;
- interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- spdc: spdc@20e8000 {
- reg = <0x020e8000 0x4000>;
- interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sdma: sdma@20ec000 {
- compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
- reg = <0x020ec000 0x4000>;
- interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SDMA>,
- <&clks IMX6SL_CLK_AHB>;
- clock-names = "ipg", "ahb";
- #dma-cells = <3>;
- /* imx6sl reuses imx6q sdma firmware */
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
- };
-
- pxp: pxp@20f0000 {
- reg = <0x020f0000 0x4000>;
- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- epdc: epdc@20f4000 {
- reg = <0x020f4000 0x4000>;
- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- lcdif: lcdif@20f8000 {
- compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
- reg = <0x020f8000 0x4000>;
- interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
- <&clks IMX6SL_CLK_LCDIF_AXI>,
- <&clks IMX6SL_CLK_DUMMY>;
- clock-names = "pix", "axi", "disp_axi";
- status = "disabled";
- power-domains = <&pd_disp>;
- };
-
- dcp: crypto@20fc000 {
- compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
- reg = <0x020fc000 0x4000>;
- interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
- <0 100 IRQ_TYPE_LEVEL_HIGH>,
- <0 101 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- aips2: bus@2100000 {
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x02100000 0x100000>;
- ranges;
-
- usbotg1: usb@2184000 {
- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
- reg = <0x02184000 0x200>;
- interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USBOH3>;
- fsl,usbphy = <&usbphy1>;
- fsl,usbmisc = <&usbmisc 0>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x10>;
- rx-burst-size-dword = <0x10>;
- status = "disabled";
- };
-
- usbotg2: usb@2184200 {
- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
- reg = <0x02184200 0x200>;
- interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USBOH3>;
- fsl,usbphy = <&usbphy2>;
- fsl,usbmisc = <&usbmisc 1>;
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x10>;
- rx-burst-size-dword = <0x10>;
- status = "disabled";
- };
-
- usbh: usb@2184400 {
- compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
- reg = <0x02184400 0x200>;
- interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USBOH3>;
- fsl,usbphy = <&usbphynop1>;
- phy_type = "hsic";
- fsl,usbmisc = <&usbmisc 2>;
- dr_mode = "host";
- ahb-burst-config = <0x0>;
- tx-burst-size-dword = <0x10>;
- rx-burst-size-dword = <0x10>;
- status = "disabled";
- };
-
- usbmisc: usbmisc@2184800 {
- #index-cells = <1>;
- compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
- reg = <0x02184800 0x200>;
- clocks = <&clks IMX6SL_CLK_USBOH3>;
- };
-
- fec: ethernet@2188000 {
- compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
- reg = <0x02188000 0x4000>;
- interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_ENET>,
- <&clks IMX6SL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb";
- status = "disabled";
- };
-
- usdhc1: mmc@2190000 {
- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
- reg = <0x02190000 0x4000>;
- interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USDHC1>,
- <&clks IMX6SL_CLK_USDHC1>,
- <&clks IMX6SL_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc2: mmc@2194000 {
- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
- reg = <0x02194000 0x4000>;
- interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USDHC2>,
- <&clks IMX6SL_CLK_USDHC2>,
- <&clks IMX6SL_CLK_USDHC2>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc3: mmc@2198000 {
- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
- reg = <0x02198000 0x4000>;
- interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USDHC3>,
- <&clks IMX6SL_CLK_USDHC3>,
- <&clks IMX6SL_CLK_USDHC3>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc4: mmc@219c000 {
- compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
- reg = <0x0219c000 0x4000>;
- interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_USDHC4>,
- <&clks IMX6SL_CLK_USDHC4>,
- <&clks IMX6SL_CLK_USDHC4>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- status = "disabled";
- };
-
- i2c1: i2c@21a0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
- reg = <0x021a0000 0x4000>;
- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_I2C1>;
- status = "disabled";
- };
-
- i2c2: i2c@21a4000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
- reg = <0x021a4000 0x4000>;
- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_I2C2>;
- status = "disabled";
- };
-
- i2c3: i2c@21a8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
- reg = <0x021a8000 0x4000>;
- interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_I2C3>;
- status = "disabled";
- };
-
- memory-controller@21b0000 {
- compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
- reg = <0x021b0000 0x4000>;
- clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
- };
-
- rngb: rngb@21b4000 {
- compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
- reg = <0x021b4000 0x4000>;
- interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_DUMMY>;
- };
-
- weim: weim@21b8000 {
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0x021b8000 0x4000>;
- interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
- fsl,weim-cs-gpr = <&gpr>;
- status = "disabled";
- };
-
- ocotp: efuse@21bc000 {
- compatible = "fsl,imx6sl-ocotp", "syscon";
- reg = <0x021bc000 0x4000>;
- clocks = <&clks IMX6SL_CLK_OCOTP>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpu_speed_grade: speed-grade@10 {
- reg = <0x10 4>;
- };
-
- tempmon_calib: calib@38 {
- reg = <0x38 4>;
- };
-
- tempmon_temp_grade: temp-grade@20 {
- reg = <0x20 4>;
- };
- };
-
- audmux: audmux@21d8000 {
- compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
- reg = <0x021d8000 0x4000>;
- status = "disabled";
- };
- };
-
- gpu_2d: gpu@2200000 {
- compatible = "vivante,gc";
- reg = <0x02200000 0x4000>;
- interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
- <&clks IMX6SL_CLK_GPU2D_OVG>;
- clock-names = "bus", "core";
- power-domains = <&pd_pu>;
- };
-
- gpu_vg: gpu@2204000 {
- compatible = "vivante,gc";
- reg = <0x02204000 0x4000>;
- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
- <&clks IMX6SL_CLK_GPU2D_OVG>;
- clock-names = "bus", "core";
- power-domains = <&pd_pu>;
- };
- };
-};
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index c02e11d..d31bc82 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -122,6 +122,7 @@
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
+ filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index 732191f..6875c6d 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -193,6 +193,7 @@
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
+ filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index f2655a4..56749cc 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -148,6 +148,7 @@
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
+ filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index e1cd6f8..d7a83a7 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -106,11 +106,14 @@
binman_imx_fit: fit {
description = "Configuration to load ATF before U-Boot";
+ filename = "u-boot.itb";
#ifndef CONFIG_IMX_HAB
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
#endif
#address-cells = <1>;
+ offset = <0x57c00>;
+
images {
uboot {
arch = "arm64";
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 6b9f40e..0912b95 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -83,3 +83,8 @@
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
+
+&main_pktdma {
+ ti,sci = <&dm_tifs>;
+ bootph-all;
+};
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
index f177f56..4d6aab5 100644
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -97,6 +97,12 @@
<0x0 0x58000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index fb7e2e5..94760c7 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -89,6 +89,12 @@
<0x0 0x50000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
index 884f442..27851b7 100644
--- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -64,6 +64,10 @@
bootph-all;
};
+&chipid {
+ bootph-all;
+};
+
&mcu_ringacc {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index c7e3443..ce55ea6 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -62,3 +62,9 @@
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 96a13b2..5470490 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -57,3 +57,9 @@
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index bef4573..d2c7522 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -97,6 +97,12 @@
<0x0 0x58000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
deleted file mode 100644
index 33742d8..0000000
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ /dev/null
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 clock tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mainmuxclk: mainmuxclk@2310108 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-mux-clock";
- clocks = <&mainpllclk>, <&refclksys>;
- reg = <0x02310108 4>;
- bit-shift = <23>;
- bit-mask = <1>;
- clock-output-names = "mainmuxclk";
- };
-
- chipclk1: chipclk1 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mainmuxclk>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "chipclk1";
- };
-
- chipclk1rstiso: chipclk1rstiso {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mainmuxclk>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso";
- };
-
- gemtraceclk: gemtraceclk@2310120 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-divider-clock";
- clocks = <&mainmuxclk>;
- reg = <0x02310120 4>;
- bit-shift = <0>;
- bit-mask = <8>;
- clock-output-names = "gemtraceclk";
- };
-
- chipstmxptclk: chipstmxptclk@2310164 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-divider-clock";
- clocks = <&mainmuxclk>;
- reg = <0x02310164 4>;
- bit-shift = <0>;
- bit-mask = <8>;
- clock-output-names = "chipstmxptclk";
- };
-
- chipclk12: chipclk12 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <2>;
- clock-mult = <1>;
- clock-output-names = "chipclk12";
- };
-
- chipclk13: chipclk13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "chipclk13";
- };
-
- paclk13: paclk13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&papllclk>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "paclk13";
- };
-
- chipclk14: chipclk14 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "chipclk14";
- };
-
- chipclk16: chipclk16 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <6>;
- clock-mult = <1>;
- clock-output-names = "chipclk16";
- };
-
- chipclk112: chipclk112 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <12>;
- clock-mult = <1>;
- clock-output-names = "chipclk112";
- };
-
- chipclk124: chipclk124 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <24>;
- clock-mult = <1>;
- clock-output-names = "chipclk114";
- };
-
- chipclk1rstiso13: chipclk1rstiso13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso13";
- };
-
- chipclk1rstiso14: chipclk1rstiso14 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso14";
- };
-
- chipclk1rstiso16: chipclk1rstiso16 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <6>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso16";
- };
-
- chipclk1rstiso112: chipclk1rstiso112 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <12>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso112";
- };
-
- clkmodrst0: clkmodrst0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "modrst0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
-
- clkusb: clkusb@2350008 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "usb";
- reg = <0x02350008 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkaemifspi: clkaemifspi@235000c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "aemif-spi";
- reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
-
- clkdebugsstrc: clkdebugsstrc@2350014 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "debugss-trc";
- reg = <0x02350014 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <1>;
- };
-
- clktetbtrc: clktetbtrc@2350018 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tetb-trc";
- reg = <0x02350018 0xb00>, <0x02350004 0x400>;
- reg-names = "control", "domain";
- domain-id = <1>;
- };
-
- clkpa: clkpa@235001c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&paclk13>;
- clock-output-names = "pa";
- reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clkcpgmac: clkcpgmac@2350020 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkpa>;
- clock-output-names = "cpgmac";
- reg = <0x02350020 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clksa: clksa@2350024 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkpa>;
- clock-output-names = "sa";
- reg = <0x02350024 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clkpcie: clkpcie@2350028 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie";
- reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
- reg-names = "control", "domain";
- domain-id = <3>;
- };
-
- clksr: clksr@2350034 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1rstiso112>;
- clock-output-names = "sr";
- reg = <0x02350034 0xb00>, <0x02350018 0x400>;
- reg-names = "control", "domain";
- domain-id = <6>;
- };
-
- clkgem0: clkgem0@235003c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem0";
- reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
- reg-names = "control", "domain";
- domain-id = <8>;
- };
-
- clkddr30: clkddr30@235005c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "ddr3-0";
- reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
- reg-names = "control", "domain";
- domain-id = <16>;
- };
-
- clkwdtimer0: clkwdtimer0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer1: clkwdtimer1@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer1";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer2: clkwdtimer2@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer2";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer3: clkwdtimer3@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer3";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clktimer15: clktimer15@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer15";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart0: clkuart0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart1: clkuart1@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart1";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkaemif: clkaemif@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkaemifspi>;
- clock-output-names = "aemif";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkusim: clkusim@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "usim";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clki2c: clki2c@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "i2c";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkspi: clkspi@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkaemifspi>;
- clock-output-names = "spi";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkgpio: clkgpio@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "gpio";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkkeymgr: clkkeymgr@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "keymgr";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
deleted file mode 100644
index 46f8ab3..0000000
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison SoC specific device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkusb1: clkusb1@2350004 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "usb1";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkhyperlink0: clkhyperlink0@2350030 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkpcie1: clkpcie1@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie1";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkxge: clkxge@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index 953c750..e77c53d 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -4,15 +4,23 @@
*/
/{
- soc {
- bootph-all;
- };
aliases {
usb0 = &usb;
usb1 = &usb1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = &uart0;
};
};
+&soc0 {
+ bootph-all;
+};
+
&i2c1 {
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
deleted file mode 100644
index bf88444..0000000
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison EVM device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2e.dtsi"
-
-/ {
- compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
- model = "Texas Instruments Keystone 2 Edison EVM";
-
- soc {
-
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
deleted file mode 100644
index dd61503..0000000
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ /dev/null
@@ -1,203 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Edison Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x24186000 0x100>,
- <0x24187000 0x2a0>,
- <0x24188000 0xb60>,
- <0x24186100 0x80>,
- <0x24189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@24000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x24000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-9";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- port-4 {
- slave-port = <4>;
- link-interface = <2>;
- };
- port-5 {
- slave-port = <5>;
- link-interface = <2>;
- };
- port-6 {
- slave-port = <6>;
- link-interface = <2>;
- };
- port-7 {
- slave-port = <7>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 00];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
deleted file mode 100644
index 449cddc..0000000
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison soc device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "keystone-k2e-clocks.dtsi"
-
- usb: usb@2680000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- usb@2690000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- usb1_phy: usb_phy@2620750 {
- compatible = "ti,keystone-usbphy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2620750 24>;
- status = "disabled";
- };
-
- usb1: usb@25000000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x25000000 0x10000>;
- clocks = <&clkusb1>;
- clock-names = "usb";
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
-
- usb@25010000 {
- compatible = "synopsys,dwc3";
- reg = <0x25010000 0x70000>;
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb1_phy>, <&usb1_phy>;
- };
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- pcie1: pcie@21020000 {
- compatible = "ti,keystone-pcie","snps,dw-pcie";
- clocks = <&clkpcie1>;
- clock-names = "pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
- ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
- 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
-
- status = "disabled";
- device_type = "pci";
- num-lanes = <2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
- <0 0 0 2 &pcie_intc1 1>, /* INT B */
- <0 0 0 3 &pcie_intc1 2>, /* INT C */
- <0 0 0 4 &pcie_intc1 3>; /* INT D */
-
- pcie_msi_intc1: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
- };
-
- pcie_intc1: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- mdio: mdio@24200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x24200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2e-netcp.dtsi"
- };
-};
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 72b67b2..19c78c9 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -4,20 +4,34 @@
*/
/{
- soc {
- bootph-all;
- };
aliases {
usb0 = &usb0;
usb1 = &usb1;
};
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+
+ pmmc@2900000 {
+ bootph-all;
+ compatible = "ti,power-processor";
+ reg = <0x02900000 0x40000>;
+ ti,lpsc_module = <1>;
+ };
};
&i2c0 {
+ status = "okay";
bootph-all;
};
&i2c1 {
+ status = "okay";
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
deleted file mode 100644
index 491fdc4..0000000
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G EVM
- *
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-
-/ {
- compatible = "ti,k2g-evm","ti,keystone";
- model = "Texas Instruments K2G General Purpose EVM";
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-&keystone_usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&keystone_usb1 {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&gbe0 {
- phy-handle = <ðphy0>;
-};
-
-&netcp {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- spi_nor: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&qspi {
- status = "okay";
-
- flash0: flash@0 {
- compatible = "s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- cdns,tshsl-ns = <392>;
- cdns,tsd2d-ns = <392>;
- cdns,tchsh-ns = <100>;
- cdns,tslch-ns = <100>;
- block-size = <18>;
-
- partition@0 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001C0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.file-system";
- reg = <0x009C0000 0x3640000>;
- };
- };
-};
-
-&mmc0 {
- status = "okay";
-};
-
-&mmc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
deleted file mode 100644
index 3634ed7..0000000
--- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/{
- soc {
- bootph-all;
- };
-};
-
-&i2c0 {
- bootph-all;
-};
-
-&i2c1 {
- bootph-all;
-};
diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts
deleted file mode 100644
index dc6c31a..0000000
--- a/arch/arm/dts/keystone-k2g-generic.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Device Tree Source for Generic 66AK2G0X EVM
- *
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-
-/ {
- compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
- model = "Texas Instruments 66AK2G02 Generic";
-
- chosen {
- stdout-path = &uart0;
- };
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
index 3634ed7..1527446 100644
--- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
@@ -4,15 +4,28 @@
*/
/{
- soc {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+
+ pmmc@2900000 {
bootph-all;
+ compatible = "ti,power-processor";
+ reg = <0x02900000 0x40000>;
+ ti,lpsc_module = <1>;
};
};
&i2c0 {
+ status = "okay";
bootph-all;
};
&i2c1 {
+ status = "okay";
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
deleted file mode 100644
index b898ae6..0000000
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G Industrial Communication Engine EVM
- *
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
- model = "Texas Instruments K2G Industrial Communication EVM";
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-};
-
-&mmc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-
- flash0: flash@0 {
- compatible = "s25fl256s1", "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- cdns,read-delay = <5>;
- cdns,tshsl-ns = <500>;
- cdns,tsd2d-ns = <500>;
- cdns,tchsh-ns = <119>;
- cdns,tslch-ns = <119>;
-
- partition@0 {
- label = "QSPI.u-boot";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001c0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x009c0000 0x0040000>;
- };
- partition@6 {
- label = "QSPI.file-system";
- reg = <0x00a00000 0x1600000>;
- };
- };
-};
-
-&qmss {
- status = "okay";
-};
-
-&knav_dmas {
- status = "okay";
-};
-
-&netcp {
- pinctrl-names = "default";
- //pinctrl-0 = <&emac_pins>;
- status = "okay";
-};
-
-&mdio {
- pinctrl-names = "default";
- //pinctrl-0 = <&mdio_pins>;
- status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- ti,min-output-impedance;
- ti,dp83867-rxctrl-strap-quirk;
- };
-};
-
-&gbe0 {
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
deleted file mode 100644
index 2afb488..0000000
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G Netcp driver
- *
- * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@4020000 {
- compatible = "ti,keystone-navigator-qmss-l";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- queue-range = <0 0x80>;
- linkram0 = <0x4020000 0x7ff>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x80>;
- reg = <0x4100000 0x800>,
- <0x4040000 0x100>,
- <0x4080000 0x800>,
- <0x40c0000 0x800>;
- reg-names = "peek", "config",
- "region", "push";
- };
-
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <77 8>;
- interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
- 0 311 0xf04 0 312 0xf04 0 313 0xf04
- 0 314 0xf04 0 315 0xf04>;
- qalloc-by-id;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <112 8>;
- };
- netcp-tx {
- qrange = <5 8>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <1023 128>; /* num_desc desc_size */
- link-index = <0x400>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x4010000 0x100>,
- <0x4011000 0x2a0>, /* 21 Tx channels */
- <0x4012000 0x400>, /* 32 Rx channels */
- <0x4010100 0x80>,
- <0x4013000 0x400>; /* 32 Rx flows */
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-
-};
-
-gbe_subsys: subsys@4200000 {
- compatible = "syscon";
- reg = <0x4200000 0x100>;
-};
-
-netcp: netcp@4000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "ethss_clk";
-
- /* NetCP address range */
- ranges = <0 0x4000000 0x1000000>;
-
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>;
- ti,navigator-dma-names = "netrx0", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 {
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-2";
- syscon-subsys = <&gbe_subsys>;
- reg = <0x200100 0xe00>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <5>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <5>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <512 12>;
- tx-pool = <511 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <77>;
- tx-completion-queue = <78>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
deleted file mode 100644
index 5c3ff12..0000000
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G SOC
- *
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "Texas Instruments K2G SoC";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- chosen { };
-
- aliases {
- serial0 = &uart0;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- spi4 = &qspi;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- gic: interrupt-controller@2561000 {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x0 0x02561000 0x0 0x1000>,
- <0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
- <0x0 0x02566000 0x0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,keystone","simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- uart0: serial@02530c00 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02530c00 0x100>;
- clock-names = "uart";
- interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
- };
-
- mdio: mdio@4200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "fck";
- reg = <0x04200f00 0x100>;
- status = "disabled";
- bus_freq = <2500000>;
- };
-
- qspi: qspi@2940000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02940000 0x1000>,
- <0x24000000 0x4000000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
- num-cs = <4>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x24000000>;
- status = "disabled";
- };
-
- #include "keystone-k2g-netcp.dtsi"
-
- pmmc: pmmc@2900000 {
- compatible = "ti,power-processor";
- reg = <0x02900000 0x40000>;
- ti,lpsc_module = <1>;
- };
-
- spi0: spi@21805400 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805400 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@21805800 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805800 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@21805c00 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805C00 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@21806000 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21806000 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- i2c0: i2c@2530000 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530000 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@2530400 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530400 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@2530800 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530800 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmc0: mmc@23000000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23000000 0x400>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
- bus-width = <4>;
- ti,needs-special-reset;
- no-1-8-v;
- max-frequency = <96000000>;
- status = "disabled";
- };
-
- mmc1: mmc@23100000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23100000 0x400>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
- bus-width = <8>;
- ti,needs-special-reset;
- ti,non-removable;
- max-frequency = <96000000>;
- status = "disabled";
- clock-names = "fck";
- };
-
- usb0_phy: usb-phy@0 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
- keystone_usb0: keystone-dwc3@2680000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2680000 0x10000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
- /*power-domains = <&k2g_pds 0x0016>;*/
-
- usb0: usb@2690000 {
- compatible = "snps,dwc3";
- reg = <0x2690000 0x10000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
- maximum-speed = "high-speed";
- dr_mode = "otg";
- /*usb-phy = <&usb0_phy>;*/
- status = "disabled";
- };
- };
-
- usb1_phy: usb-phy@1 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
- keystone_usb1: keystone-dwc3@2580000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2580000 0x10000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
- /*power-domains = <&k2g_pds 0x0017>;*/
-
- usb1: usb@2590000 {
- compatible = "snps,dwc3";
- reg = <0x2590000 0x10000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
- maximum-speed = "high-speed";
- dr_mode = "otg";
- /*usb-phy = <&usb1_phy>;*/
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
deleted file mode 100644
index 3ca4722..0000000
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ /dev/null
@@ -1,422 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking SoC clock nodes
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkarm>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- ddr3bpllclk: ddr3bpllclk@2620368 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3b>;
- clock-output-names = "ddr-3b-pll-clk";
- reg = <0x02620368 4>;
- reg-names = "control";
- };
-
- clktsip: clktsip@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "tsip";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clksrio: clksrio@235002c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1rstiso13>;
- clock-output-names = "srio";
- reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkhyperlink0: clkhyperlink0@2350030 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkgem1: clkgem1@2350040 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2@2350044 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3@2350048 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clkgem4: clkgem4@235004c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem4";
- reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
- reg-names = "control", "domain";
- domain-id = <12>;
- };
-
- clkgem5: clkgem5@2350050 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem5";
- reg = <0x02350050 0xb00>, <0x02350034 0x400>;
- reg-names = "control", "domain";
- domain-id = <13>;
- };
-
- clkgem6: clkgem6@2350054 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem6";
- reg = <0x02350054 0xb00>, <0x02350038 0x400>;
- reg-names = "control", "domain";
- domain-id = <14>;
- };
-
- clkgem7: clkgem7@2350058 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem7";
- reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
- reg-names = "control", "domain";
- domain-id = <15>;
- };
-
- clkddr31: clkddr31@2350060 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "ddr3-1";
- reg = <0x02350060 0xb00>, <0x02350040 0x400>;
- reg-names = "control", "domain";
- domain-id = <16>;
- };
-
- clktac: clktac@2350064 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac01: clkrac01@2350068 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-01";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac23: clkrac23@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-23";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0@2350070 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc1: clkfftc1@2350074 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc2: clkfftc2@2350078 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-2";
- reg = <0x02350078 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc3: clkfftc3@235007c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-3";
- reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc4: clkfftc4@2350080 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-4";
- reg = <0x02350080 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc5: clkfftc5@2350084 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-5";
- reg = <0x02350084 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkaif: clkaif@2350088 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "aif";
- reg = <0x02350088 0xb00>, <0x02350054 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0@235008c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1@2350090 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350090 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d2: clktcp3d2@2350094 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-2";
- reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clktcp3d3: clktcp3d3@2350098 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-3";
- reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0@235009c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1@23500a0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2@23500a4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3@23500a8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp4: clkvcp4@23500ac {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-4";
- reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp5: clkvcp5@23500b0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-5";
- reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp6: clkvcp6@23500b4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-6";
- reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp7: clkvcp7@23500b8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-7";
- reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkbcp: clkbcp@23500bc {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdxb: clkdxb@23500c0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dxb";
- reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkhyperlink1: clkhyperlink1@23500c4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-1";
- reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkxge: clkxge@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index 3e38f22..3b3d327 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -4,9 +4,19 @@
*/
/{
- soc {
- bootph-all;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
};
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
};
&i2c1 {
@@ -18,11 +28,9 @@
psc-domain = <2>;
};
-&usb {
- dwc3@2690000 {
- phys = <&usb_phy>;
- dr_mode = "host";
- snps,u2ss_inp3_quirk;
- status = "okay";
- };
+&usb0 {
+ phys = <&usb_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
};
diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
deleted file mode 100644
index 6222876..0000000
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking EVM device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2hk.dtsi"
-
-/ {
- compatible = "ti,k2hk-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkarm: refclkarm {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "refclk-arm";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
-
- refclkddr3b: refclkddr3b {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3b";
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led-debug-1-1 {
- label = "keystone:green:debug1";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
- };
-
- led-debug-1-2 {
- label = "keystone:red:debug1";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
- };
-
- led-debug-2 {
- label = "keystone:blue:debug2";
- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
- };
-
- led-debug-3 {
- label = "keystone:blue:debug3";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1fe80000>;
- };
- };
- };
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
deleted file mode 100644
index 3f8c4c2..0000000
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Hawking Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x4000>;
- linkram0 = <0x100000 0x8000>;
- linkram1 = <0x0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
-
- qmgr1 {
- managed-queues = <0x2000 0x2000>;
- reg = <0x2a60000 0x20000>,
- <0x2a06400 0x400>,
- <0x2a04000 0x1000>,
- <0x2a05000 0x1000>,
- <0x23aa0000 0x20000>,
- <0x2aa0000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
-
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <8704 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <8720 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <640 9>;
- qalloc-by-id;
- };
- netcpx-tx {
- qrange = <8752 8>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23aa0000 0x23ab0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x2004000 0x100>,
- <0x2004400 0x120>,
- <0x2004800 0x300>,
- <0x2004c00 0x120>,
- <0x2005000 0x400>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@2000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x2000000 0x100000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 22>,
- <&dma_gbe 23>,
- <&dma_gbe 8>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
- gbe@90000 { /* ETHSS */
- #address-cells = <1>;
- #size-cells = <1>;
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe";
- reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
- /* enable-ale; */
- tx-queue = <648>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8704>;
- tx-completion-queue = <8706>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8705>;
- tx-completion-queue = <8707>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 6f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
deleted file mode 100644
index e5ab1fb..0000000
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking soc specific device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "keystone-k2hk-clocks.dtsi"
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- dspgpio4: keystone_dsp_gpio@2620250 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x250>;
- };
-
- dspgpio5: keystone_dsp_gpio@2620254 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x254>;
- };
-
- dspgpio6: keystone_dsp_gpio@2620258 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x258>;
- };
-
- dspgpio7: keystone_dsp_gpio@262025c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x25c>;
- };
-
- mdio: mdio@02090300 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02090300 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2hk-netcp.dtsi"
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
deleted file mode 100644
index fcfc2fb..0000000
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ /dev/null
@@ -1,263 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 lamarr SoC clock nodes
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkdfeiqnsys: clkdfeiqnsys@2350004 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "dfe";
- reg-names = "control", "domain";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- domain-id = <0>;
- };
-
- clkpcie1: clkpcie1@235002c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie";
- reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkgem1: clkgem1@2350040 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2@2350044 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3@2350048 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clktac: clktac@2350064 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac: clkrac@2350068 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkdfepd0: clkdfepd0@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd0";
- reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0@2350070 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkosr: clkosr@2350088 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "osr";
- reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0@235008c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1@2350094 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350094 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0@235009c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1@23500a0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2@23500a4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3@23500a8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkbcp: clkbcp@23500bc {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdfepd1: clkdfepd1@23500c0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd1";
- reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkfftc1: clkfftc1@23500c4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkiqnail: clkiqnail@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "iqn-ail";
- reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-
- clkuart2: clkuart2@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart2";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart3: clkuart3@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart3";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
index f1aed14..d9dee80 100644
--- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -3,16 +3,30 @@
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
+/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+};
+
&usb_phy {
#phy-cells = <0>;
psc-domain = <2>;
};
-&usb {
- dwc3@2690000 {
- phys = <&usb_phy>;
- dr_mode = "host";
- snps,u2ss_inp3_quirk;
- status = "okay";
- };
+&usb0 {
+ phys = <&usb_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
};
diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
deleted file mode 100644
index 9d2b454..0000000
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Lamarr EVM device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2l.dtsi"
-
-/ {
- compatible = "ti,k2l-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Lamarr EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x7FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status ="okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
deleted file mode 100644
index 2caa058..0000000
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ /dev/null
@@ -1,187 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Lamarr Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x26186000 0x100>,
- <0x26187000 0x2a0>,
- <0x26188000 0xb60>,
- <0x26186100 0x80>,
- <0x26189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@26000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x26000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-5";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 7f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
deleted file mode 100644
index c8893e2..0000000
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Lamarr SoC specific device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
- };
-
- soc {
- /include/ "keystone-k2l-clocks.dtsi"
-
- uart2: serial@2348400 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348400 0x100>;
- clocks = <&clkuart2>;
- interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
- };
-
- uart3: serial@2348800 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348800 0x100>;
- clocks = <&clkuart3>;
- interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- mdio: mdio@26200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x26200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2l-netcp.dtsi"
- };
-};
-
-&spi0 {
- ti,davinci-spi-num-cs = <5>;
-};
-
-&spi1 {
- ti,davinci-spi-num-cs = <3>;
-};
-
-&spi2 {
- ti,davinci-spi-num-cs = <5>;
- /* Pin muxed. Enabled and configured by Bootloader */
- status = "disabled";
-};
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
deleted file mode 100644
index 1538cce..0000000
--- a/arch/arm/dts/keystone.dtsi
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "skeleton.dtsi"
-
-/ {
- model = "Texas Instruments Keystone 2 SoC";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- gic: interrupt-controller {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x02561000 0x1000>,
- <0x02562000 0x2000>,
- <0x02564000 0x1000>,
- <0x02566000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts =
- <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,keystone","simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- pllctrl: pll-controller@02310000 {
- compatible = "ti,keystone-pllctrl", "syscon";
- reg = <0x02310000 0x200>;
- };
-
- devctrl: device-state-control@02620000 {
- compatible = "ti,keystone-devctrl", "syscon";
- reg = <0x02620000 0x1000>;
- };
-
- rstctrl: reset-controller {
- compatible = "ti,keystone-reset";
- ti,syscon-pll = <&pllctrl 0xe4>;
- ti,syscon-dev = <&devctrl 0x328>;
- ti,wdt-list = <0>;
- };
-
- /include/ "keystone-clocks.dtsi"
-
- uart0: serial@2530c00 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02530c00 0x100>;
- clocks = <&clkuart0>;
- interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
- };
-
- uart1: serial@2531000 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02531000 0x100>;
- clocks = <&clkuart1>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
- };
-
- i2c0: i2c@2530000 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530000 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@2530400 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530400 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@2530800 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530800 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi@21000400 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000400 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@21000600 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000600 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi2: spi@21000800 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000800 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb_phy: usb_phy@2620738 {
- compatible = "ti,keystone-usbphy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2620738 24>;
- status = "disabled";
- };
-
- usb: usb@2680000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2680000 0x10000>;
- clocks = <&clkusb>;
- clock-names = "usb";
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
-
- usb@2690000 {
- compatible = "synopsys,dwc3";
- reg = <0x2690000 0x70000>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb_phy>, <&usb_phy>;
- };
- };
-
- wdt: wdt@22f0080 {
- compatible = "ti,keystone-wdt","ti,davinci-wdt";
- reg = <0x022f0080 0x80>;
- clocks = <&clkwdtimer0>;
- };
-
- clock_event: timer@22f0000 {
- compatible = "ti,keystone-timer";
- reg = <0x022f0000 0x80>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clktimer15>;
- };
-
- gpio0: gpio@260bf00 {
- compatible = "ti,keystone-gpio";
- reg = <0x0260bf00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- /* HW Interrupts mapped to GPIO pins */
- interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkgpio>;
- clock-names = "gpio";
- ti,ngpio = <32>;
- ti,davinci-gpio-unbanked = <32>;
- };
-
- aemif: aemif@21000A00 {
- compatible = "ti,keystone-aemif", "ti,davinci-aemif";
- #address-cells = <2>;
- #size-cells = <1>;
- clocks = <&clkaemif>;
- clock-names = "aemif";
- clock-ranges;
-
- reg = <0x21000A00 0x00000100>;
- ranges = <0 0 0x30000000 0x10000000
- 1 0 0x21000A00 0x00000100>;
- };
-
- kirq0: keystone_irq@26202a0 {
- compatible = "ti,keystone-irq";
- interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- ti,syscon-dev = <&devctrl 0x2a0>;
- };
-
- pcie0: pcie@21800000 {
- compatible = "ti,keystone-pcie", "snps,dw-pcie";
- clocks = <&clkpcie>;
- clock-names = "pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
- ranges = <0x81000000 0 0 0x23250000 0 0x4000
- 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
-
- status = "disabled";
- device_type = "pci";
- num-lanes = <2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
- <0 0 0 2 &pcie_intc0 1>, /* INT B */
- <0 0 0 3 &pcie_intc0 2>, /* INT C */
- <0 0 0 4 &pcie_intc0 3>; /* INT D */
-
- pcie_msi_intc0: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
- };
-
- pcie_intc0: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 7aaa777..a9991a1 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -98,14 +98,6 @@
bootph-all;
};
- infracfg_ao: infracfg_ao@10001000 {
- compatible = "mediatek,mt7981-infracfg_ao";
- reg = <0x10001000 0x80>;
- clock-parent = <&infracfg>;
- #clock-cells = <1>;
- bootph-all;
- };
-
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg";
reg = <0x10001000 0x30>;
@@ -140,14 +132,13 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_PWM>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>,
- /* FIXME */
- <&infracfg_ao CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
@@ -158,8 +149,8 @@
<0x10217080 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
- <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -170,11 +161,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -184,11 +175,11 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -197,11 +188,11 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -211,14 +202,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+ <&topckgen CLK_TOP_CB_M_D8>;
status = "disabled";
};
@@ -244,14 +235,14 @@
};
sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
reg = <0x10060000 0x1000>;
pn_swap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
reg = <0x10070000 0x1000>;
#clock-cells = <1>;
};
@@ -265,13 +256,13 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -280,19 +271,26 @@
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_SPI1_CK>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ clock-names = "spi-clk", "sel-clk";
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI2_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -302,13 +300,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_400M>,
- <&topckgen CK_TOP_EMMC_208M>,
- <&infracfg_ao CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
- <&topckgen CK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
- <&topckgen CK_TOP_CB_M_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_400M>,
+ <&topckgen CLK_TOP_EMMC_208M>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
+ <&topckgen CLK_TOP_EMMC_208M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
+ <&topckgen CLK_TOP_CB_M_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 30b5a89..f871f23 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -78,7 +78,7 @@
compatible = "mediatek,mt7986-timer";
reg = <0x10008000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&topckgen CLK_TOP_F26M_SEL>;
clock-names = "gpt-clk";
bootph-all;
};
@@ -115,13 +115,6 @@
#clock-cells = <1>;
};
- infracfg_ao: infracfg_ao@10001000 {
- compatible = "mediatek,mt7986-infracfg_ao";
- reg = <0x10001000 0x68>;
- clock-parent = <&infracfg>;
- #clock-cells = <1>;
- };
-
infracfg: infracfg@10001040 {
compatible = "mediatek,mt7986-infracfg";
reg = <0x10001000 0x1000>;
@@ -154,18 +147,18 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_PWM>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
- <&infracfg CK_INFRA_PWM_BSEL>,
- <&infracfg CK_INFRA_PWM1_SEL>,
- <&infracfg CK_INFRA_PWM2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
- <&infracfg CK_INFRA_PWM>,
- <&infracfg CK_INFRA_PWM>,
- <&infracfg CK_INFRA_PWM>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_SEL>,
+ <&infracfg CLK_INFRA_PWM2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
bootph-all;
@@ -175,11 +168,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -189,9 +182,9 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -200,9 +193,9 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -212,14 +205,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -258,12 +251,12 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -281,13 +274,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_416M>,
- <&topckgen CK_TOP_EMMC_250M>,
- <&infracfg_ao CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
- <&topckgen CK_TOP_EMMC_250M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
- <&topckgen CK_TOP_NET1_D5_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>;
+ assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
+ <&topckgen CLK_TOP_NET1PLL_D5_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 5c0c5bc..e120e50 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -97,13 +97,6 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
- compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- clock-parent = <&infracfg_ao>;
- #clock-cells = <1>;
- };
-
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7988-fixed-plls", "syscon";
reg = <0 0x1001e000 0 0x1000>;
@@ -251,7 +244,7 @@
#clock-cells = <1>;
};
- infracfg_ao: infracfg@10001000 {
+ infracfg: infracfg@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
clock-parent = <&topckgen>;
@@ -262,11 +255,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O0>;
+ clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -274,11 +267,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O1>;
+ clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -286,11 +279,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O2>;
+ clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -301,8 +294,8 @@
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -316,8 +309,8 @@
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -331,8 +324,8 @@
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -343,16 +336,16 @@
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
- clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4","pwm5","pwm6","pwm7","pwm8";
status = "disabled";
@@ -365,14 +358,14 @@
<0 0x11002000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_SPINFI>,
- <&infracfg_ao CK_INFRA_NFI>,
- <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI>,
+ <&infracfg CLK_INFRA_NFI>,
+ <&infracfg CLK_INFRA_66M_NFI_HCK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -408,10 +401,10 @@
"mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
- <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
- <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
- <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
clock-names = "source", "hclk", "source_cg", "axi_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi b/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi
new file mode 100644
index 0000000..0abe8b0
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845-yosemite4-pincfg.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/ {
+ pinctrl: pinctrl@f0800000 {
+ gpio234_pins: gpio234-pins {
+ pins = "GPIO234/PWM10/SMB20_SCL";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio61_pins: gpio61-pins {
+ pins = "GPIO61/SI1_nDTR_BOUT";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio46_pins: gpio46-pins {
+ pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio54_pins: gpio54-pins {
+ pins = "GPIO54/SI2_nDSR/BU4_TXD";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio55_pins: gpio55-pins {
+ pins = "GPIO55/SI2_RI2/BU4_RXD";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio121_pins: gpio121-pins {
+ pins = "GPIO121/SMB2C_SCL";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio108_pins: gpio108-pins {
+ pins = "GPIO108/SG1_MDC";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio109_pins: gpio109-pins {
+ pins = "GPIO109/SG1_MDIO";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio183_pins: gpio183-pins {
+ pins = "GPIO183/SPI3_SEL";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio184_pins: gpio184-pins {
+ pins = "GPIO184/SPI3_D0/STRAP13";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio189_pins: gpio189-pins {
+ pins = "GPIO189/SPI3_D3/SPI3_nCS3";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio92_pins: gpio92-pins {
+ pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio35_pins: gpio35-pins {
+ pins = "GPI35/MCBPCK";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio36_pins: gpio36-pins {
+ pins = "GPI36/SYSBPCK";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio62_pins: gpio62-pins {
+ pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio45_pins: gpio45-pins {
+ pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio83_pins: gpio83-pins {
+ pins = "GPIO83/PWM3";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio144_pins: gpio144-pins {
+ pins = "GPIO144/PWM4";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio145_pins: gpio145-pins {
+ pins = "GPIO145/PWM5";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio146_pins: gpio146-pins {
+ pins = "GPIO146/PWM6";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio159_pins: gpio159-pins {
+ pins = "GPIO159/MMC_DT3";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio127_pins: gpio127-pins {
+ pins = "GPIO127/SMB1B_SCL/CP1_GPIO0";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ gpio15_pins: gpio15-pins {
+ pins = "GPIO15/GSPI_CS/SMB5C_SDA";
+ bias-disable;
+ input-enable;
+ event-clear;
+ persist-enable;
+ };
+ };
+};
diff --git a/arch/arm/dts/nuvoton-npcm845-yosemite4.dts b/arch/arm/dts/nuvoton-npcm845-yosemite4.dts
new file mode 100644
index 0000000..1a5d503
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845-yosemite4.dts
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2024 Nuvoton Technology
+
+/dts-v1/;
+
+#include <dt-bindings/phy/nuvoton,npcm-usbphy.h>
+#include "nuvoton-npcm845.dtsi"
+#include "nuvoton-npcm845-yosemite4-pincfg.dtsi"
+
+/ {
+ model = "Nuvoton npcm845 yosemite4";
+ compatible = "nuvoton,npcm845";
+
+ aliases {
+ serial0 = &serial0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ ethernet3 = &gmac3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
+ spi0 = &fiu0;
+ spi1 = &fiu1;
+ spi3 = &fiu3;
+ spi4 = &fiux;
+ spi5 = &pspi;
+ usb0 = &udc0;
+ usb1 = &ehci1;
+ usb2 = &udc8;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ tpm@0 {
+ compatible = "microsoft,ftpm";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ vsbr2: vsbr2 {
+ compatible = "regulator-npcm845";
+ regulator-name = "vr2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vsbv8: vsbv8 {
+ compatible = "regulator-npcm845";
+ regulator-name = "v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vsbv5: vsbv5 {
+ compatible = "regulator-npcm845";
+ regulator-name = "v5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&fiu0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0cs1_pins>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ spi_flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&fiu1 {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&fiu3 {
+ pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+ status = "okay";
+ vqspi-supply = <&vsbv5>;
+ vqspi-microvolt = <3300000>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
+
+&fiux {
+ nuvoton,spix-mode;
+ status = "okay";
+};
+
+&pspi {
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usbphy3 {
+ status = "okay";
+};
+
+&udc0 {
+ status = "okay";
+ phys = <&usbphy1 NPCM_UDC0_7>;
+};
+
+&ehci1 {
+ status = "okay";
+ phys = <&usbphy2 NPCM_USBH1>;
+};
+
+&udc8 {
+ status = "okay";
+ phys = <&usbphy3 NPCM_UDC8>;
+};
+
+&rng {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&sha {
+ status = "okay";
+};
+
+&otp {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &spix_pins
+ &r1_pins
+ &r1en_pins
+ &r1oen_pins
+ &r2_pins
+ &r2en_pins
+ &r2oen_pins
+ &gpio234_pins
+ &gpio61_pins
+ &gpio46_pins
+ &gpio54_pins
+ &gpio55_pins
+ &gpio121_pins
+ &gpio108_pins
+ &gpio109_pins
+ &gpio183_pins
+ &gpio184_pins
+ &gpio189_pins
+ &gpio92_pins
+ &gpio35_pins
+ &gpio36_pins
+ &gpio62_pins
+ &gpio45_pins
+ &gpio83_pins
+ &gpio144_pins
+ &gpio145_pins
+ &gpio146_pins
+ &gpio159_pins
+ &gpio127_pins
+ &gpio15_pins
+ >;
+};
diff --git a/arch/arm/dts/omap3-evm-37xx.dts b/arch/arm/dts/omap3-evm-37xx.dts
deleted file mode 100644
index abd403c..0000000
--- a/arch/arm/dts/omap3-evm-37xx.dts
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-#include "omap3-evm-common.dtsi"
-#include "omap3-evm-processor-common.dtsi"
-
-/ {
- model = "TI OMAP37XX EVM (TMDSEVM3730)";
- compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
-};
-
-&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_2_pins>;
-
- ehci_phy_pins: pinmux_ehci_phy_pins {
- pinctrl-single,pins = <
-
- /* EHCI PHY reset GPIO etk_d7.gpio_21 */
- OMAP3630_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
-
- /* EHCI VBUS etk_d8.gpio_22 */
- OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
- >;
- };
-
- /* Used by OHCI and EHCI. OHCI won't work without external phy */
- hsusb2_2_pins: pinmux_hsusb2_2_pins {
- pinctrl-single,pins = <
-
- /* etk_d10.hsusb2_clk */
- OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
-
- /* etk_d11.hsusb2_stp */
- OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
-
- /* etk_d12.hsusb2_dir */
- OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d13.hsusb2_nxt */
- OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d14.hsusb2_data0 */
- OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d15.hsusb2_data1 */
- OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
- >;
- };
-};
-
-&gpmc {
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "hynix,h8kds0un0mer-4em";
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- ti,nand-ecc-opt = "bch8";
-
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "X-Loader";
- reg = <0 0x80000>;
- };
- partition@80000 {
- label = "U-Boot";
- reg = <0x80000 0x1c0000>;
- };
- partition@1c0000 {
- label = "Environment";
- reg = <0x240000 0x40000>;
- };
- partition@280000 {
- label = "Kernel";
- reg = <0x280000 0x500000>;
- };
- partition@780000 {
- label = "Filesystem";
- reg = <0x780000 0x1f880000>;
- };
- };
-};
diff --git a/arch/arm/dts/omap3-evm-common.dtsi b/arch/arm/dts/omap3-evm-common.dtsi
deleted file mode 100644
index 17c89df..0000000
--- a/arch/arm/dts/omap3-evm-common.dtsi
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common support for omap3 EVM boards
- */
-
-#include <dt-bindings/input/input.h>
-#include "omap-gpmc-smsc911x.dtsi"
-
-/ {
- cpus {
- cpu@0 {
- cpu0-supply = <&vcc>;
- };
- };
-
- /* HS USB Port 2 Power */
- hsusb2_power: hsusb2_power_reg {
- compatible = "regulator-fixed";
- regulator-name = "hsusb2_vbus";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; /* gpio_22 */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-
- /* HS USB Host PHY on PORT 2 */
- hsusb2_phy: hsusb2_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
- vcc-supply = <&hsusb2_power>;
- #phy-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
- ledb {
- label = "omap3evm::ledb";
- gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
- linux,default-trigger = "default-on";
- };
- };
-
- wl12xx_vmmc: wl12xx_vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio150 */
- startup-delay-us = <70000>;
- enable-active-high;
- vin-supply = <&vmmc2>;
- };
-};
-
-&i2c1 {
- clock-frequency = <2600000>;
-
- twl: twl@48 {
- reg = <0x48>;
- interrupts = <7>; /* SYS_NIRQ cascaded to intc */
- interrupt-parent = <&intc>;
- };
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-#include "omap3-panel-sharp-ls037v7dw01.dtsi"
-
-&backlight0 {
- gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;
-};
-
-&twl {
- twl_power: power {
- compatible = "ti,twl4030-power-omap3-evm", "ti,twl4030-power-idle";
- ti,use_poweroff;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
-};
-
-&i2c3 {
- clock-frequency = <400000>;
-
- /*
- * TVP5146 Video decoder-in for analog input support.
- */
- tvp5146@5c {
- compatible = "ti,tvp5146m2";
- reg = <0x5c>;
- };
-};
-
-&lcd_3v3 {
- gpio = <&gpio5 25 GPIO_ACTIVE_LOW>; /* gpio153 */
-};
-
-&lcd0 {
- enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */
- reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */
- mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */
- &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
- &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */
-};
-
-&mcspi1 {
- tsc2046@0 {
- interrupt-parent = <&gpio6>;
- interrupts = <15 0>; /* gpio175 */
- pendown-gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&mmc1 {
- interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
- vmmc-supply = <&vmmc1>;
- vqmmc-supply = <&vsim>;
- bus-width = <8>;
-};
-
-&mmc2 {
- interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
- vmmc-supply = <&wl12xx_vmmc>;
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1271";
- reg = <2>;
- /* gpio_149 with uart1_rts pad as wakeirq */
- interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
- <&omap3_pmx_core 0x14e>;
- interrupt-names = "irq", "wakeup";
- ref-clock-frequency = <38400000>;
- };
-};
-
-&twl_gpio {
- ti,use-leds;
-};
-
-&twl_keypad {
- linux,keymap = <
- MATRIX_KEY(2, 2, KEY_1)
- MATRIX_KEY(1, 1, KEY_2)
- MATRIX_KEY(0, 0, KEY_3)
- MATRIX_KEY(3, 2, KEY_4)
- MATRIX_KEY(2, 1, KEY_5)
- MATRIX_KEY(1, 0, KEY_6)
- MATRIX_KEY(1, 3, KEY_7)
- MATRIX_KEY(3, 1, KEY_8)
- MATRIX_KEY(2, 0, KEY_9)
- MATRIX_KEY(2, 3, KEY_KPASTERISK)
- MATRIX_KEY(0, 2, KEY_0)
- MATRIX_KEY(3, 0, KEY_KPDOT)
- /* s4 not wired */
- MATRIX_KEY(1, 2, KEY_BACKSPACE)
- MATRIX_KEY(0, 1, KEY_ENTER)
- >;
-};
-
-&usbhshost {
- port2-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <0 &hsusb2_phy>;
-};
-
-&usb_otg_hs {
- interface-type = <0>;
- usb-phy = <&usb2_phy>;
- phys = <&usb2_phy>;
- phy-names = "usb2-phy";
- mode = <3>;
- power = <50>;
-};
-
-&gpmc {
- ethernet@gpmc {
- interrupt-parent = <&gpio6>;
- interrupts = <16 8>;
- reg = <5 0 0xff>;
- };
-};
-
-&vaux2 {
- regulator-name = "usb_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
-};
diff --git a/arch/arm/dts/omap3-evm-processor-common.dtsi b/arch/arm/dts/omap3-evm-processor-common.dtsi
deleted file mode 100644
index e6ba30a..0000000
--- a/arch/arm/dts/omap3-evm-processor-common.dtsi
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Common support for omap3 EVM 35xx/37xx processor modules
- */
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256 MB */
- };
-
- wl12xx_vmmc: wl12xx_vmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&wl12xx_gpio>;
- };
-};
-
-&dss {
- vdds_dsi-supply = <&vpll2>;
- vdda_video-supply = <&lcd_3v3>;
- pinctrl-names = "default";
- pinctrl-0 = <
- &dss_dpi_pins1
- &dss_dpi_pins2
- >;
-};
-
-&hsusb2_phy {
- pinctrl-names = "default";
- pinctrl-0 = <&ehci_phy_pins>;
-};
-
-&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>;
-
- dss_dpi_pins1: pinmux_dss_dpi_pins2 {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
- OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
- OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
- OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
-
- OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
- OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
- OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
- OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
- OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
- OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
- OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
- OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
- OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
- OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
- OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
- OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
-
- OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
- OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
- OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
- OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
- OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
- OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
- OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
- OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
- OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
- OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
- OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
- OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
- OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
- OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
- OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
- >;
- };
-
- /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */
- mmc2_pins: pinmux_mmc2_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
- OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
- OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
- OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
- OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
- OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
- OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */
- OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */
- OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */
- OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
- OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
- >;
- };
-
- /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */
- on_board_gpio_61: pinmux_ehci_port_select_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4)
- >;
- };
-
- /* Used by OHCI and EHCI. OHCI won't work without external phy */
- hsusb2_pins: pinmux_hsusb2_pins {
- pinctrl-single,pins = <
-
- /* mcspi1_cs3.hsusb2_data2 */
- OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* mcspi2_clk.hsusb2_data7 */
- OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* mcspi2_simo.hsusb2_data4 */
- OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* mcspi2_somi.hsusb2_data5 */
- OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* mcspi2_cs0.hsusb2_data6 */
- OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* mcspi2_cs1.hsusb2_data3 */
- OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)
- >;
- };
-
- /*
- * Note that gpio_150 pulled high with internal pull to prevent wlcore
- * reset on return from off mode in idle.
- */
- wl12xx_gpio: pinmux_wl12xx_gpio {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */
- OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */
- >;
- };
-
- smsc911x_pins: pinmux_smsc911x_pins {
- pinctrl-single,pins = <
- OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
- >;
- };
-};
-
-&omap3_pmx_wkup {
- dss_dpi_pins2: pinmux_dss_dpi_pins1 {
- pinctrl-single,pins = <
- OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
- OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
- OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
- OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
- OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
- OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
- >;
- };
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
-};
-
-&mmc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins>;
-};
-
-&mmc3 {
- status = "disabled";
-};
-
-&uart1 {
- interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
-};
-
-&uart2 {
- interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
-};
-
-&uart3 {
- interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-/*
- * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface
- * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
- */
-&gpio2 {
- en-usb2-port-hog {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
- output-low;
- line-name = "enable usb2 port";
- };
-};
-
-/* T2_GPIO_2 low to route GPIO_61 to on-board devices */
-&twl_gpio {
- en_on_board_gpio_61 {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "en_hsusb2_clk";
- };
-};
-
-&gpmc {
- ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
- <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */
-
- ethernet@gpmc {
- pinctrl-names = "default";
- pinctrl-0 = <&smsc911x_pins>;
- };
-};
diff --git a/arch/arm/dts/omap3-evm.dts b/arch/arm/dts/omap3-evm.dts
deleted file mode 100644
index f95eea6..0000000
--- a/arch/arm/dts/omap3-evm.dts
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap34xx.dtsi"
-#include "omap3-evm-common.dtsi"
-#include "omap3-evm-processor-common.dtsi"
-
-/ {
- model = "TI OMAP35XX EVM (TMDSEVM3530)";
- compatible = "ti,omap3-evm", "ti,omap3430", "ti,omap3";
-};
-
-&omap3_pmx_core2 {
- pinctrl-names = "default";
- pinctrl-0 = <&hsusb2_2_pins>;
-
- ehci_phy_pins: pinmux_ehci_phy_pins {
- pinctrl-single,pins = <
-
- /* EHCI PHY reset GPIO etk_d7.gpio_21 */
- OMAP3430_CORE2_IOPAD(0x25ea, PIN_OUTPUT | MUX_MODE4)
-
- /* EHCI VBUS etk_d8.gpio_22 */
- OMAP3430_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4)
- >;
- };
-
- /* Used by OHCI and EHCI. OHCI won't work without external phy */
- hsusb2_2_pins: pinmux_hsusb2_2_pins {
- pinctrl-single,pins = <
-
- /* etk_d10.hsusb2_clk */
- OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)
-
- /* etk_d11.hsusb2_stp */
- OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)
-
- /* etk_d12.hsusb2_dir */
- OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d13.hsusb2_nxt */
- OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d14.hsusb2_data0 */
- OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)
-
- /* etk_d15.hsusb2_data1 */
- OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)
- >;
- };
-};
-
-&gpmc {
- nand@0,0 {
- compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
- interrupt-parent = <&gpmc>;
- interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
- <1 IRQ_TYPE_NONE>; /* termcount */
- linux,mtd-name = "micron,mt29f2g16abdhc";
- nand-bus-width = <16>;
- gpmc,device-width = <2>;
- ti,nand-ecc-opt = "bch8";
-
- gpmc,sync-clk-ps = <0>;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
- gpmc,wr-access-ns = <40>;
- gpmc,wr-data-mux-bus-ns = <0>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi
deleted file mode 100644
index 2dbb687..0000000
--- a/arch/arm/dts/omap3-panel-sharp-ls037v7dw01.dtsi
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common file for omap dpi panels with QVGA and reset pins
- *
- * Note that the board specifc DTS file needs to specify
- * at minimum the GPIO enable-gpios for display, and
- * gpios for gpio-backlight.
- */
-
-/ {
- aliases {
- display0 = &lcd0;
- };
-
- backlight0: backlight {
- compatible = "gpio-backlight";
- default-on;
- };
-
- /* 3.3V GPIO controlled regulator for LCD_ENVDD */
- lcd_3v3: regulator-lcd-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "lcd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- startup-delay-us = <70000>;
- };
-
- lcd0: display {
- compatible = "sharp,ls037v7dw01";
- label = "lcd";
- power-supply = <&lcd_3v3>;
- envdd-supply = <&lcd_3v3>;
-
- port {
- lcd_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
- };
-};
-
-/* Needed to power the DPI pins */
-&vpll2 {
- regulator-always-on;
-};
-
-&dss {
- status = "okay";
- port {
- dpi_out: endpoint {
- remote-endpoint = <&lcd_in>;
- data-lines = <18>;
- };
- };
-};
-
-&mcspi1 {
- tsc2046@0 {
- reg = <0>; /* CS0 */
- compatible = "ti,tsc2046";
- spi-max-frequency = <1000000>;
- vcc-supply = <&lcd_3v3>;
- ti,x-min = /bits/ 16 <0>;
- ti,x-max = /bits/ 16 <8000>;
- ti,y-min = /bits/ 16 <0>;
- ti,y-max = /bits/ 16 <4800>;
- ti,x-plate-ohms = /bits/ 16 <40>;
- ti,pressure-max = /bits/ 16 <255>;
- ti,swap-xy;
- wakeup-source;
- };
-};
diff --git a/arch/arm/dts/omap3-sniper-u-boot.dtsi b/arch/arm/dts/omap3-sniper-u-boot.dtsi
new file mode 100644
index 0000000..d467f53
--- /dev/null
+++ b/arch/arm/dts/omap3-sniper-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#include "omap3-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+};
diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi
new file mode 100644
index 0000000..fbe7259
--- /dev/null
+++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Linaro Ltd.
+ */
+/ {
+ /* When running as the primary bootloader there is no prior
+ * stage to populate the memory layout for us. We *should*
+ * have two nodes here, but ABL does NOT like that.
+ * sooo we're stuck with this.
+ */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x3A800000>,
+ <0 0xC0000000 0 0x01800000>,
+ <0 0xC3400000 0 0x3CC00000>,
+ <1 0x00000000 1 0x00000000>;
+ };
+};
+
+&usb_1_dwc3 {
+ dr_mode = "host";
+ /delete-property/ usb-role-switch;
+};
+
+// RAM Entry 0 : Base 0x0080000000 Size 0x003A800000
+// RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000
+// RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000
+// RAM Entry 3 : Base 0x0100000000 Size 0x0100000000
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index cc8beca..f60eba5 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -8,7 +8,6 @@
#include "r8a779x-u-boot.dtsi"
&rpc {
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
bank-width = <2>;
num-cs = <1>;
};
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
index a102639..c3704d7 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -13,29 +13,9 @@
};
};
-&pfc {
- qspi0_pins: qspi0 {
- groups = "qspi0_ctrl", "qspi0_data4";
- function = "qspi0";
- };
-};
-
&rpc {
- pinctrl-0 = <&qspi0_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
- spi-max-frequency = <40000000>;
- status = "disabled";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "s25fs512s", "jedec,spi-nor";
- reg = <0>;
+ flash@0 {
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
- spi-max-frequency = <40000000>;
};
};
diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts
index 60b1c0e..b98ed16 100644
--- a/arch/arm/dts/versal-mini-emmc0.dts
+++ b/arch/arm/dts/versal-mini-emmc0.dts
@@ -28,7 +28,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts
index 751cc38..e6a5c2b 100644
--- a/arch/arm/dts/versal-mini-emmc1.dts
+++ b/arch/arm/dts/versal-mini-emmc1.dts
@@ -28,7 +28,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 8735292..9ca0cf3 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -28,7 +28,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
index 9347ea3..57427e0 100644
--- a/arch/arm/dts/versal-mini-qspi.dtsi
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -28,7 +28,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 18f627f..f1fb159 100644
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -31,7 +31,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index a5c8a08..8e60d17 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -31,7 +31,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi
index 2e4afaf..3b7e6c7 100644
--- a/arch/arm/dts/zynq-cse-qspi.dtsi
+++ b/arch/arm/dts/zynq-cse-qspi.dtsi
@@ -32,7 +32,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 2076271..293d8e9 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -87,7 +87,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
- is-internal-pcspma;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -118,7 +117,7 @@
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 0b97fa3..4e0587f 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -155,7 +155,6 @@
phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
- is-internal-pcspma;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index 36a0db4..c439f77 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -80,7 +80,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii";
- is-internal-pcspma;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -112,7 +111,7 @@
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
- "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 - 89 */
"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
"SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 83b8a98..d6cd193 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -101,7 +101,7 @@
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
- status = "disable";
+ status = "disabled";
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
@@ -140,9 +140,9 @@
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
- "", "", "", "", "", /* 78 - 79 */
+ "", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
@@ -300,7 +300,7 @@
i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
#address-cells = <1>;
#size-cells = <0>;
- /* reg = <3>; */
+ reg = <3>;
};
i2c@4 { /* LP_I2C_SM */
#address-cells = <1>;
@@ -365,25 +365,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index dd37b72..902fdd4 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -97,7 +97,7 @@
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
- status = "disable";
+ status = "disabled";
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
@@ -135,9 +135,9 @@
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
- "", "", "", "", "", /* 78 - 79 */
+ "", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
@@ -288,7 +288,7 @@
i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
#address-cells = <1>;
#size-cells = <0>;
- /* reg = <3>; */
+ reg = <3>;
};
i2c@4 { /* LP_I2C_SM */
#address-cells = <1>;
@@ -367,25 +367,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 811ceba..f3994bc 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -97,7 +97,7 @@
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
- status = "disable";
+ status = "disabled";
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
@@ -135,9 +135,9 @@
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
- "", "", "", "", "", /* 78 - 79 */
+ "", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
@@ -292,7 +292,7 @@
i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
#address-cells = <1>;
#size-cells = <0>;
- /* reg = <3>; */
+ reg = <3>;
};
i2c@4 { /* LP_I2C_SM */
#address-cells = <1>;
@@ -361,25 +361,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 7823c58..cf22197 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,13 +41,13 @@
clock-frequency = <200000000>;
};
- amba: amba {
+ amba: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- sdhci0: sdhci@ff160000 {
+ sdhci0: mmc@ff160000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 2f6ba95..4c9f56a 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,13 +41,13 @@
clock-frequency = <200000000>;
};
- amba: amba {
+ amba: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- sdhci1: sdhci@ff170000 {
+ sdhci1: mmc@ff170000 {
bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index e08a784..5e21351 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -35,7 +35,7 @@
bootph-all;
};
- amba: amba {
+ amba: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index e35317f..917603d 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -36,7 +36,13 @@
bootph-all;
};
- amba: amba {
+ misc_clk: misc-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ amba: axi {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
@@ -52,19 +58,13 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- misc_clk: misc-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- };
};
};
&qspi {
status = "okay";
flash0: flash@0 {
- compatible = "n25q512a11", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
index 197dc25..82cc383 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-01-revA.dtso
@@ -33,25 +33,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
index 8eb6e40..11b1544 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-02-revA.dtso
@@ -33,25 +33,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
index af7a3ce..9b4c8b3 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-03-revA.dtso
@@ -33,25 +33,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
index 29a6c2a..1b1bb36 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-04-revA.dtso
@@ -33,25 +33,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
index 6ddf18c..8c16286 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA-x-prc-05-revA.dtso
@@ -33,25 +33,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 5a60b86..ae52e8e 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -90,7 +90,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
- is-internal-pcspma;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -121,7 +120,7 @@
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
- "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 - 89 */
"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
"SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
@@ -427,25 +426,25 @@
#gpio-cells = <2>;
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "sw4_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "sw4_2";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "sw4_3";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index c1d713b..1fcb5bf 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -104,7 +104,7 @@
"", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
index 5333767..620afba 100644
--- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
@@ -115,25 +115,25 @@
#gpio-cells = <2>;
gpio-line-names = "xprc_sw_1", "xprc_sw_2", "xprc_sw_3", "xprc_sw_4",
"", "", "", "";
- gtr-sel0 {
+ gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
input; /* FIXME add meaning */
line-name = "xprc_sw_1";
};
- gtr-sel1 {
+ gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
input; /* FIXME add meaning */
line-name = "xprc_sw_1";
};
- gtr-sel2 {
+ gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
input; /* FIXME add meaning */
line-name = "xprc_sw_1";
};
- gtr-sel3 {
+ gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
input; /* FIXME add meaning */
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
index 1862593..ba54845 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -16,6 +16,12 @@
&{/} {
compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
"xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+
+ vc7_xin: vc7-xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <50000000>;
+ };
};
&i2c0 {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
index ce7c5eb..6349a0e 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
@@ -195,7 +195,6 @@
phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
- is-internal-pcspma;
assigned-clock-rates = <250000000>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 0a0cbd2..b0d737d 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -216,7 +216,6 @@
phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
- is-internal-pcspma;
assigned-clock-rates = <250000000>;
};
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index b626d1a..7849f8c 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -117,7 +117,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
- is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
mdio: mdio {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index e063288..4768fac 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -118,7 +118,6 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
- is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
mdio: mdio {
#address-cells = <1>;
diff --git a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
index a9b5826..f1ec314 100644
--- a/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
+++ b/arch/arm/dts/zynqmp-zcu106-rev1.0.dts
@@ -11,6 +11,6 @@
/ {
model = "ZynqMP ZCU106 Rev1.0";
- compatible = "xlnx,zynqmp-zcu106-rev1.0", "xlnx,zynqmp-zcu106-revA",
+ compatible = "xlnx,zynqmp-zcu106-rev1.0",
"xlnx,zynqmp-zcu106", "xlnx,zynqmp";
};
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 787cf0d..3a1580d 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -494,7 +494,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- sc18is603@2f { /* sc18is602 - u93 */
+ sc18is603: spi@2f { /* sc18is602 - u93 */
compatible = "nxp,sc18is603";
reg = <0x2f>;
/* 4 gpios for CS not handled by driver */
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index 4060dc3..ed83ba3 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -43,6 +43,7 @@
&gem1 {
status = "okay";
+ phy-mode = "rgmii-id";
mdio {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index a113e47..88536e9 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -68,7 +68,7 @@
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
- ina226-vccint-io-bram-ps {
+ ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
@@ -205,7 +205,7 @@
"ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 4d7d5d2..29087aa 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -68,7 +68,7 @@
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
- ina226-vccint-io-bram-ps {
+ ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
@@ -211,7 +211,7 @@
"ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index def3b53..2928ebe 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -71,7 +71,7 @@
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
- ina226-vccint-io-bram-ps {
+ ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index 41f9a23..1a99d1e 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -71,7 +71,7 @@
compatible = "iio-hwmon";
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
};
- ina226-vccint-io-bram-ps {
+ ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 513cdac..7abcd1c 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -37,7 +37,6 @@
#ifdef CONFIG_NOR_BOOT
void enable_norboot_pin_mux(void);
#endif
-void am33xx_spl_board_init(void);
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
int am335x_get_mpu_vdd(int sil_rev, int frequency);
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index cbd2717..b0468a1 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -68,6 +68,8 @@
#define MXC_CPU_IMX9321 0xC6 /* dummy ID */
#define MXC_CPU_IMX9312 0xC7 /* dummy ID */
#define MXC_CPU_IMX9311 0xC8 /* dummy ID */
+#define MXC_CPU_IMX9302 0xC9 /* dummy ID */
+#define MXC_CPU_IMX9301 0xCA /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index 1ce6ac4..76f1211 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -211,7 +211,8 @@
u32 div;
};
-int clock_init(void);
+int clock_init_early(void);
+int clock_init_late(void);
u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void);
void init_uart_clk(u32 index);
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 76d241e..ef9538b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -25,6 +25,7 @@
#define ANATOP_BASE_ADDR 0x44480000UL
#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
+#define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x44210000
#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000
#define SRC_IPS_BASE_ADDR (0x44460000)
@@ -38,6 +39,7 @@
#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x80000000UL)
@@ -48,8 +50,16 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
+#define TRDC_AON_BASE (0x44270000UL)
+#define TRDC_WAKEUP_BASE (0x42460000UL)
+#define TRDC_MEGA_BASE (0x42810000UL)
+#define TRDC_NIC_BASE (0x49010000UL)
+
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
+#define NUM_WORDS_PER_BANK 8
+#define HW_CFG1 19
+#define HW_CFG2 20
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 2f7a129..e4bf6a6 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -8,7 +8,18 @@
#include <asm/mach-imx/sys_proto.h>
+enum imx9_soc_voltage_mode {
+ VOLT_LOW_DRIVE = 0,
+ VOLT_NOMINAL_DRIVE,
+ VOLT_OVER_DRIVE,
+};
+
void soc_power_init(void);
bool m33_is_rom_kicked(void);
int m33_prepare(void);
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
+
+#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
+
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h
index 77b5422..b5fc738 100644
--- a/arch/arm/include/asm/arch-rockchip/timer.h
+++ b/arch/arm/include/asm/arch-rockchip/timer.h
@@ -15,4 +15,7 @@
u32 timer_int_status;
};
+/** rockchip_stimer_init() - Set up the timer ready for use */
+void rockchip_stimer_init(void);
+
#endif
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index a29b849..d4ac567 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -26,6 +26,7 @@
#define ELE_GET_EVENTS_REQ (0xA2)
#define ELE_COMMIT_REQ (0xA8)
#define ELE_START_RNG (0xA3)
+#define ELE_CMD_DERIVE_KEY (0xA9)
#define ELE_GENERATE_DEK_BLOB (0xAF)
#define ELE_ENABLE_PATCH_REQ (0xC3)
#define ELE_RELEASE_RDC_REQ (0xC4)
@@ -143,6 +144,7 @@
int ele_release_caam(u32 core_did, u32 *response);
int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ele_derive_huk(u8 *key, size_t key_size, u8 *ctx, size_t seed_size);
int ele_commit(u16 fuse_id, u32 *response, u32 *info_type);
int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size);
int ele_dump_buffer(u32 *buffer, u32 buffer_length);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 31ae179..31ace97 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -85,7 +85,8 @@
#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
- is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+ is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311) || \
+ is_cpu_type(MXC_CPU_IMX9302) || is_cpu_type(MXC_CPU_IMX9301))
#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
@@ -93,6 +94,8 @@
#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
+#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
@@ -275,4 +278,7 @@
enum boot_device get_boot_device(void);
+int disable_cpu_nodes(void *blob, const char * const *nodes_path,
+ u32 num_disabled_cores, u32 max_cores);
+int fixup_thermal_trips(void *blob, const char *name);
#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 7e30cac..2237d7d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -277,6 +277,16 @@
void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+
+/**
+ * mmu_map_region() - map a region of previously unmapped memory.
+ * Will be mapped MT_NORMAL & PTE_BLOCK_INNER_SHARE.
+ *
+ * @start: Start address of the region
+ * @size: Size of the region
+ * @emerg: Also map the region in the emergency table
+ */
+void mmu_map_region(phys_addr_t start, u64 size, bool emerg);
void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
/*
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 7c49462..c7fff01 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -58,7 +58,7 @@
printf("Board Type = %ld\n", gd->board_type);
#endif
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
- printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
+ printf("Early malloc usage: %x / %x\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
}
diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
index ea1b937..2b21ec0 100644
--- a/arch/arm/lib/stack.c
+++ b/arch/arm/lib/stack.c
@@ -11,7 +11,6 @@
* Marius Groeger <mgroeger@sysgo.de>
*/
#include <init.h>
-#include <lmb.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,16 +32,3 @@
return 0;
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 16384);
-}
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 8bace30..0b6d290 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -773,23 +773,20 @@
int board_late_init(void)
{
- struct lmb lmb;
u32 status = 0;
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
/* somewhat based on the Linux Kernel boot requirements:
* align by 2M and maximal FDT size 2M
*/
- status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
- status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
- status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
- status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
+ status |= env_set_hex("loadaddr", lmb_alloc(SZ_1G, SZ_2M));
+ status |= env_set_hex("fdt_addr_r", lmb_alloc(SZ_2M, SZ_2M));
+ status |= env_set_hex("kernel_addr_r", lmb_alloc(SZ_128M, SZ_2M));
+ status |= env_set_hex("ramdisk_addr_r", lmb_alloc(SZ_1G, SZ_2M));
status |= env_set_hex("kernel_comp_addr_r",
- lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
+ lmb_alloc(KERNEL_COMP_SIZE, SZ_2M));
status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
- status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
- status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
+ status |= env_set_hex("scriptaddr", lmb_alloc(SZ_4M, SZ_2M));
+ status |= env_set_hex("pxefile_addr_r", lmb_alloc(SZ_4M, SZ_2M));
if (status)
log_warning("late_init: Failed to set run time variables\n");
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 8a8ac53..7c4ccc4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -11,10 +11,6 @@
bool
select CPU_ARM926EJS
-config AT91SAM9XE
- bool
- select CPU_ARM926EJS
-
config AT91SAM9261
bool
select CPU_ARM926EJS
@@ -75,10 +71,6 @@
select AT91SAM9260
select BOARD_EARLY_INIT_F
-config TARGET_ETHERNUT5
- bool "Ethernut5 board"
- select AT91SAM9XE
-
config TARGET_GURNARD
bool "Support gurnard"
select AT91SAM9G45
@@ -340,21 +332,6 @@
config SYS_SOC
default "at91"
-config AT91_EFLASH
- bool "Support AT91 flash driver"
- depends on AT91SAM9XE
- select USE_SYS_MAX_FLASH_BANKS
- help
- Enable the driver for the embedded flash used in the Atmel
- AT91SAM9XE devices.
-
-config EFLASH_PROTSECTORS
- int "Number of flash sectors to protect from erasing"
- depends on AT91_EFLASH
- help
- If non-zero, this will be the number of sectors of the flash to disallow
- U-Boot to ease, starting from the beginning of flash.
-
config AT91_GPIO_PULLUP
bool "Keep pullups on peripheral pins"
depends on CPU_ARM926EJS
@@ -389,7 +366,6 @@
source "board/bluewater/gurnard/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/conclusive/kstr-sama5d27/Kconfig"
-source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/gardena/smart-gateway-at91sam/Kconfig"
source "board/l+g/vinco/Kconfig"
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile
index 902dd3a..a891686 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -5,7 +5,6 @@
obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o
obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o
obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
@@ -15,7 +14,6 @@
obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
-obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-y += clock.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)SYSRESET
diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c
deleted file mode 100644
index bb66700..0000000
--- a/arch/arm/mach-at91/arm926ejs/eflash.c
+++ /dev/null
@@ -1,255 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- */
-
-/*
- * this driver supports the enhanced embedded flash in the Atmel
- * AT91SAM9XE devices with the following geometry:
- *
- * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages)
- * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages)
- * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
- * (the exact geometry is read from the flash at runtime, so any
- * future devices should already be covered)
- *
- * Regions can be write/erase protected.
- * Whole (!) pages can be individually written with erase on the fly.
- * Writing partial pages will corrupt the rest of the page.
- *
- * The flash is presented to u-boot with each region being a sector,
- * having the following effects:
- * Each sector can be hardware protected (protect on/off).
- * Each page in a sector can be rewritten anytime.
- * Since pages are erased when written, the "erase" does nothing.
- * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
- * by u-Boot commands.
- *
- * Note: Redundant environment will not work in this flash since
- * it does use partial page writes. Make sure the environment spans
- * whole pages!
- */
-
-/*
- * optional TODOs (nice to have features):
- *
- * make the driver coexist with other NOR flash drivers
- * (use an index into flash_info[], requires work
- * in those other drivers, too)
- * Make the erase command fill the sectors with 0xff
- * (if the flashes grow larger in the future and
- * someone puts a jffs2 into them)
- * do a read-modify-write for partially programmed pages
- */
-#include <display_options.h>
-#include <flash.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_eefc.h>
-#include <asm/arch/at91_dbu.h>
-
-/* checks to detect configuration errors */
-#if CONFIG_SYS_MAX_FLASH_BANKS!=1
-#error eflash: this driver can only handle 1 bank
-#endif
-
-/* global structure */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static u32 pagesize;
-
-unsigned long flash_init(void)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU;
- u32 id, size, nplanes, planesize, nlocks;
- u32 addr, i, tmp=0;
-
- debug("eflash: init\n");
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
-
- /* check if its an AT91ARM9XE SoC */
- if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) {
- puts("eflash: not an AT91SAM9XE\n");
- return 0;
- }
-
- /* now query the eflash for its structure */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- id = readl(&eefc->frr); /* word 0 */
- size = readl(&eefc->frr); /* word 1 */
- pagesize = readl(&eefc->frr); /* word 2 */
- nplanes = readl(&eefc->frr); /* word 3 */
- planesize = readl(&eefc->frr); /* word 4 */
- debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n",
- id, size, pagesize, nplanes, planesize);
- for (i=1; i<nplanes; i++) {
- tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */
- };
- nlocks = readl(&eefc->frr); /* word 4+nplanes */
- debug("nlocks=%u\n", nlocks);
- /* since we are going to use the lock regions as sectors, check count */
- if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("eflash: number of lock regions(%u) "\
- "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n",
- nlocks);
- nlocks = CONFIG_SYS_MAX_FLASH_SECT;
- }
- flash_info[0].size = size;
- flash_info[0].sector_count = nlocks;
- flash_info[0].flash_id = id;
-
- addr = ATMEL_BASE_FLASH;
- for (i=0; i<nlocks; i++) {
- tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */
- flash_info[0].start[i] = addr;
- flash_info[0].protect[i] = 0;
- addr += tmp;
- };
-
- /* now read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<flash_info[0].sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
-#if CONFIG_VAL(EFLASH_PROTSECTORS)
- if (i < CONFIG_EFLASH_PROTSECTORS)
- flash_info[0].protect[i] = 1;
-#endif
- }
-
- return size;
-}
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
-
- puts("AT91SAM9XE embedded flash\n Size: ");
- print_size(info->size, " in ");
- printf("%d Sectors\n", info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize;
- u32 i, tmp=0;
-
- debug("protect sector=%ld prot=%d\n", sector, prot);
-
-#if CONFIG_VAL(EFLASH_PROTSECTORS)
- if (sector < CONFIG_EFLASH_PROTSECTORS) {
- if (!prot) {
- printf("eflash: sector %lu cannot be unprotected\n",
- sector);
- }
- return 1; /* return anyway, caller does not care for result */
- }
-#endif
- if (prot) {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- } else {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- }
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* now re-read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<info->sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- info->protect[i] = (tmp >> (i%32)) & 1;
- }
- return 0;
-}
-
-static u32 erase_write_page (u32 pagenum)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
-
- debug("erase+write page=%u\n", pagenum);
-
- /* give erase and write page command */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* return status */
- return readl(&eefc->fsr)
- & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE);
-}
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- debug("erase first=%d last=%d\n", s_first, s_last);
- puts("this flash does not need and support erasing!\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- u32 pagenum;
- u32 *src32, *dst32;
- u32 i;
-
- debug("write src=%08lx addr=%08lx cnt=%lx\n",
- (ulong)src, addr, cnt);
-
- /* REQUIRE addr to be on a page start, abort if not */
- if (addr % pagesize) {
- printf ("eflash: start %08lx is not on page start\n"\
- " write aborted\n", addr);
- return 1;
- }
-
- /* now start copying data */
- pagenum = (addr-ATMEL_BASE_FLASH)/pagesize;
- src32 = (u32 *) src;
- dst32 = (u32 *) addr;
- while (cnt > 0) {
- i = pagesize / 4;
- /* fill page buffer */
- while (i--)
- *dst32++ = *src32++;
- /* write page */
- if (erase_write_page(pagenum))
- return 1;
- pagenum++;
- if (cnt > pagesize)
- cnt -= pagesize;
- else
- cnt = 0;
- }
- return 0;
-}
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h
index 683e539..8fec346 100644
--- a/arch/arm/mach-at91/include/mach/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -28,7 +28,7 @@
void at91_mck_init(u32 mckr);
void at91_mck_init_down(u32 mckr);
void at91_pmc_init(void);
-void mem_init(void);
+void at91_mem_init(void);
void at91_phy_reset(void);
void at91_sdram_hw_init(void);
void at91_mck_init(u32 mckr);
diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h
deleted file mode 100644
index 91bb686..0000000
--- a/arch/arm/mach-at91/include/mach/at91_dbu.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Debug Unit
- * Based on AT91SAM9XE datasheet
- */
-
-#ifndef AT91_DBU_H
-#define AT91_DBU_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_dbu {
- u32 cr; /* Control Register WO */
- u32 mr; /* Mode Register RW */
- u32 ier; /* Interrupt Enable Register WO */
- u32 idr; /* Interrupt Disable Register WO */
- u32 imr; /* Interrupt Mask Register RO */
- u32 sr; /* Status Register RO */
- u32 rhr; /* Receive Holding Register RO */
- u32 thr; /* Transmit Holding Register WO */
- u32 brgr; /* Baud Rate Generator Register RW */
- u32 res1[7];/* 0x0024 - 0x003C Reserved */
- u32 cidr; /* Chip ID Register RO */
- u32 exid; /* Chip ID Extension Register RO */
- u32 fnr; /* Force NTRST Register RW */
-} at91_dbu_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_DBU_CID_ARCH_MASK 0x0ff00000
-#define AT91_DBU_CID_ARCH_9xx 0x01900000
-#define AT91_DBU_CID_ARCH_9XExx 0x02900000
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_eefc.h b/arch/arm/mach-at91/include/mach/at91_eefc.h
deleted file mode 100644
index e7bb2bf..0000000
--- a/arch/arm/mach-at91/include/mach/at91_eefc.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Enhanced Embedded Flash Controller
- * Based on AT91SAM9XE datasheet
- */
-
-#ifndef AT91_EEFC_H
-#define AT91_EEFC_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct at91_eefc {
- u32 fmr; /* Flash Mode Register RW */
- u32 fcr; /* Flash Command Register WO */
- u32 fsr; /* Flash Status Register RO */
- u32 frr; /* Flash Result Register RO */
-} at91_eefc_t;
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_EEFC_FMR_FWS_MASK 0x00000f00
-#define AT91_EEFC_FMR_FRDY_BIT 0x00000001
-
-#define AT91_EEFC_FCR_KEY 0x5a000000
-#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00
-#define AT91_EEFC_FCR_FARG_SHIFT 8
-#define AT91_EEFC_FCR_FCMD_GETD 0x0
-#define AT91_EEFC_FCR_FCMD_WP 0x1
-#define AT91_EEFC_FCR_FCMD_WPL 0x2
-#define AT91_EEFC_FCR_FCMD_EWP 0x3
-#define AT91_EEFC_FCR_FCMD_EWPL 0x4
-#define AT91_EEFC_FCR_FCMD_EA 0x5
-#define AT91_EEFC_FCR_FCMD_SLB 0x8
-#define AT91_EEFC_FCR_FCMD_CLB 0x9
-#define AT91_EEFC_FCR_FCMD_GLB 0xA
-#define AT91_EEFC_FCR_FCMD_SGPB 0xB
-#define AT91_EEFC_FCR_FCMD_CGPB 0xC
-#define AT91_EEFC_FCR_FCMD_GGPB 0xD
-
-#define AT91_EEFC_FSR_FRDY 1
-#define AT91_EEFC_FSR_FCMDE 2
-#define AT91_EEFC_FSR_FLOCKE 4
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 103db26..bdd46ee 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -7,7 +7,7 @@
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* Definitions for the SoCs:
- * AT91SAM9260, AT91SAM9G20, AT91SAM9XE
+ * AT91SAM9260, AT91SAM9G20
*
* Note that those SoCs are mostly software and pin compatible,
* therefore this file applies to all of them. Differences between
@@ -142,15 +142,7 @@
/*
* SoC specific defines
*/
-#if defined(CONFIG_AT91SAM9XE)
-# define ATMEL_CPU_NAME "AT91SAM9XE"
-# define ATMEL_ID_TWI1 25 /* TWI 1 */
-# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */
-# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */
-# define ATMEL_BASE_TWI1 0xfffd8000
-# define ATMEL_BASE_EEFC 0xfffffa00
-# define ATMEL_BASE_GPBR 0xfffffd60
-#elif defined(CONFIG_AT91SAM9260)
+#if defined(CONFIG_AT91SAM9260)
# define ATMEL_CPU_NAME "AT91SAM9260"
# define ATMEL_ID_USART5 25 /* USART 5 */
# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 0a16c8f..988ef49 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -9,8 +9,7 @@
#if defined(CONFIG_AT91RM9200)
# include <asm/arch/at91rm9200.h>
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \
- defined(CONFIG_AT91SAM9XE)
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
# include <asm/arch/at91sam9260.h>
#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
# include <asm/arch/at91sam9261.h>
diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c
index cde1700..0d1233c 100644
--- a/arch/arm/mach-at91/spl_at91.c
+++ b/arch/arm/mach-at91/spl_at91.c
@@ -142,7 +142,7 @@
preloader_console_init();
#endif
- mem_init();
+ at91_mem_init();
at91_spl_board_init();
}
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 62a7df8..7bfbadf 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -134,7 +134,7 @@
board_early_init_f();
- mem_init();
+ at91_mem_init();
ret = spl_init();
if (ret) {
diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h
index 59c28ed..75d8498 100644
--- a/arch/arm/mach-exynos/include/mach/dwmmc.h
+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h
@@ -4,24 +4,34 @@
* Jaehoon Chung <jh80.chung@samsung.com>
*/
-#define DWMCI_CLKSEL 0x09C
-#define DWMCI_SET_SAMPLE_CLK(x) (x)
-#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
-#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+#ifndef __ASM_ARM_ARCH_DWMMC_H
+#define __ASM_ARM_ARCH_DWMMC_H
-#define EMMCP_MPSBEGIN0 0x1200
-#define EMMCP_SEND0 0x1204
-#define EMMCP_CTRL0 0x120C
+#include <linux/bitops.h>
-#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
-#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
-#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
-#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
-#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
-#define MPSCTRL_ECB_MODE (0x1<<2)
-#define MPSCTRL_ENCRYPTION (0x1<<1)
-#define MPSCTRL_VALID (0x1<<0)
+#define DWMCI_CLKSEL 0x09c
+#define DWMCI_CLKSEL64 0x0a8
+#define DWMCI_SET_SAMPLE_CLK(x) (x)
+#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+
+/* Protector Register */
+#define DWMCI_EMMCP_BASE 0x1000
+#define EMMCP_MPSBEGIN0 (DWMCI_EMMCP_BASE + 0x0200)
+#define EMMCP_SEND0 (DWMCI_EMMCP_BASE + 0x0204)
+#define EMMCP_CTRL0 (DWMCI_EMMCP_BASE + 0x020c)
+
+#define MPSCTRL_SECURE_READ_BIT BIT(7)
+#define MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define MPSCTRL_NON_SECURE_READ_BIT BIT(5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
+#define MPSCTRL_USE_FUSE_KEY BIT(3)
+#define MPSCTRL_ECB_MODE BIT(2)
+#define MPSCTRL_ENCRYPTION BIT(1)
+#define MPSCTRL_VALID BIT(0)
/* CLKSEL Register */
#define DWMCI_DIVRATIO_BIT 24
#define DWMCI_DIVRATIO_MASK 0x7
+
+#endif /* __ASM_ARM_ARCH_DWMMC_H */
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index bd5a064..219d7fb 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -312,7 +312,7 @@
memzero((void *)gd, sizeof(gd_t));
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
}
void board_init_f(unsigned long bootflag)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c34bc25..134e420 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,8 @@
config MACH_IMX
bool
+if MACH_IMX
+
config HAS_CAAM
bool
@@ -200,3 +202,5 @@
config IOMUX_SHARE_CONF_REG
bool
+
+endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5262dca..f8903af 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -21,6 +21,12 @@
obj-y += cpu.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += fdt.o
+endif
+endif
+
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index c13d9f0e..647daeb 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -624,6 +624,31 @@
return CMD_RET_SUCCESS;
}
+static int do_ahab_derive(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong key;
+ size_t key_size;
+ char seed[] = "_ELE_AHAB_SEED_";
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ key = hextoul(argv[1], NULL);
+ key_size = simple_strtoul(argv[2], NULL, 10);
+ if (key_size != 16 && key_size != 32) {
+ printf("key size can only be 16 or 32\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (ele_derive_huk((u8 *)key, key_size, seed, sizeof(seed))) {
+ printf("Error in AHAB derive\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -680,6 +705,12 @@
"addr - Return lifecycle message block signed by OEM SRK\n"
);
+U_BOOT_CMD(ahab_derive, CONFIG_SYS_MAXARGS, 3, do_ahab_derive,
+ "Derive the hardware unique key",
+ "addr [16|32]\n"
+ "Store at addr the derivation of the HUK on 16 or 32 bytes.\n"
+);
+
U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
"commit into the fuses any new SRK revocation and FW version information\n"
"that have been found into the NXP (ELE FW) and OEM containers",
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
new file mode 100644
index 0000000..ac782e3
--- /dev/null
+++ b/arch/arm/mach-imx/fdt.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/arch/sys_proto.h>
+
+static void disable_thermal_cpu_nodes(void *blob, u32 num_disabled_cores, u32 max_cores)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/cpu-thermal/cooling-maps/map0"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 num_le32 = max_cores * 3;
+ u32 *cooling_dev = (u32 *)malloc(num_le32 * sizeof(__le32));
+
+ if (!cooling_dev) {
+ printf("failed to alloc cooling dev\n");
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ nodeoff = fdt_path_offset(blob, thermal_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device",
+ cooling_dev, num_le32);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != num_le32)
+ printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+ sizeof(__le32) * (num_le32 - num_disabled_cores * 3));
+ if (ret < 0) {
+ printf("Warning: %s, cooling-device setprop failed %d\n",
+ thermal_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, cooling-device prop\n", thermal_path[i]);
+ }
+
+ free(cooling_dev);
+}
+
+int disable_cpu_nodes(void *blob, const char * const *nodes_path, u32 num_disabled_cores,
+ u32 max_cores)
+{
+ u32 i = 0;
+ int rc;
+ int nodeoff;
+
+ if (max_cores == 0 || (num_disabled_cores > (max_cores - 1)))
+ return -EINVAL;
+
+ i = max_cores - num_disabled_cores;
+
+ for (; i < max_cores; i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ debug("Found %s node\n", nodes_path[i]);
+
+ rc = fdt_del_node(blob, nodeoff);
+ if (rc < 0) {
+ printf("Unable to delete node %s, err=%s\n",
+ nodes_path[i], fdt_strerror(rc));
+ } else {
+ printf("Delete node %s\n", nodes_path[i]);
+ }
+ }
+
+ disable_thermal_cpu_nodes(blob, num_disabled_cores, max_cores);
+
+ return 0;
+}
+
+int fixup_thermal_trips(void *blob, const char *name)
+{
+ int minc, maxc;
+ int node, trip;
+
+ node = fdt_path_offset(blob, "/thermal-zones");
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, name);
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, "trips");
+ if (node < 0)
+ return node;
+
+ get_cpu_temp_grade(&minc, &maxc);
+
+ fdt_for_each_subnode(trip, blob, node) {
+ const char *type;
+ int temp, ret;
+
+ type = fdt_getprop(blob, trip, "type", NULL);
+ if (!type)
+ continue;
+
+ temp = 0;
+ if (!strcmp(type, "critical"))
+ temp = 1000 * (maxc - 5);
+ else if (!strcmp(type, "passive"))
+ temp = 1000 * (maxc - 10);
+ if (temp) {
+ ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index e2388e3..2afe9d3 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -205,7 +205,7 @@
} else {
u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 1 || part == 2) {
+ if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
offset = CONTAINER_HDR_MMCSD_OFFSET;
else
@@ -294,15 +294,15 @@
int part;
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 1 || part == 2) {
+ if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) {
unsigned long sec_set_off = 0;
bool sec_boot = false;
sec_boot = check_secondary_cnt_set(&sec_set_off);
if (sec_boot)
- part = (part == 1) ? 2 : 1;
- } else if (part == 7) {
- part = 0;
+ part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1;
+ } else if (part == EMMC_BOOT_PART_USER) {
+ part = EMMC_HWPART_DEFAULT;
}
return part;
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index de630e9..d7fd102 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -181,10 +181,19 @@
}
#endif
-int intpll_configure(enum pll_clocks pll, ulong freq)
+__weak int board_imx_intpll_override(enum pll_clocks pll, ulong *freq)
+{
+ return 0;
+}
+
+static int intpll_configure(enum pll_clocks pll, ulong freq)
{
void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
u32 pll_div_ctl_val, pll_clke_masks;
+ int ret = board_imx_intpll_override(pll, &freq);
+
+ if (ret)
+ return ret;
switch (pll) {
case ANATOP_SYSTEM_PLL1:
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index be38ca5..46974bf 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -32,6 +32,7 @@
#include <imx_sip.h>
#include <linux/bitops.h>
#include <linux/bitfield.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -206,6 +207,14 @@
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
+ /* Deactivate the data cache, possibly enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
@@ -587,12 +596,50 @@
}
}
+/*
+ * Place early TLB into the .data section so that it will not
+ * get cleared, use 16 kiB alignment.
+ */
+#define EARLY_TLB_SIZE SZ_64K
+u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+/*
+ * Initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+static void early_enable_caches(void)
+{
+ phys_size_t sdram_size;
+ int entry, ret;
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return;
+
+ if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ /* Use maximum available DRAM size in first bank. */
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return;
+
+ entry = imx8m_find_dram_entry_in_mem_map();
+ imx8m_mem_map[entry].size = max(sdram_size, (phys_size_t)0xc0000000);
+
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+
+ /* Enable MMU (default configuration) */
+ dcache_enable();
+}
+
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
+ early_enable_caches();
#endif
/*
@@ -735,6 +782,7 @@
#endif
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
@@ -769,6 +817,7 @@
return raw_sect;
}
+#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
#endif
bool is_usb_boot(void)
@@ -1135,117 +1184,6 @@
return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
}
-static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const thermal_path[] = {
- "/thermal-zones/cpu-thermal/cooling-maps/map0"
- };
-
- int nodeoff, cnt, i, ret, j;
- u32 cooling_dev[12];
-
- for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
- nodeoff = fdt_path_offset(blob, thermal_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
- if (cnt < 0)
- continue;
-
- if (cnt != 12)
- printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
-
- for (j = 0; j < cnt; j++)
- cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
-
- ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
- sizeof(u32) * (12 - disabled_cores * 3));
- if (ret < 0) {
- printf("Warning: %s, cooling-device setprop failed %d\n",
- thermal_path[i], ret);
- continue;
- }
-
- printf("Update node %s, cooling-device prop\n", thermal_path[i]);
- }
-}
-
-static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const pmu_path[] = {
- "/pmu"
- };
-
- int nodeoff, cnt, i, ret, j;
- u32 irq_affinity[4];
-
- for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
- nodeoff = fdt_path_offset(blob, pmu_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
- irq_affinity, 4);
- if (cnt < 0)
- continue;
-
- if (cnt != 4)
- printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
-
- for (j = 0; j < cnt; j++)
- irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
-
- ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
- sizeof(u32) * (4 - disabled_cores));
- if (ret < 0) {
- printf("Warning: %s, interrupt-affinity setprop failed %d\n",
- pmu_path[i], ret);
- continue;
- }
-
- printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
- }
-}
-
-static int disable_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const nodes_path[] = {
- "/cpus/cpu@1",
- "/cpus/cpu@2",
- "/cpus/cpu@3",
- };
- u32 i = 0;
- int rc;
- int nodeoff;
-
- if (disabled_cores > 3)
- return -EINVAL;
-
- i = 3 - disabled_cores;
-
- for (; i < 3; i++) {
- nodeoff = fdt_path_offset(blob, nodes_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- debug("Found %s node\n", nodes_path[i]);
-
- rc = fdt_del_node(blob, nodeoff);
- if (rc < 0) {
- printf("Unable to delete node %s, err=%s\n",
- nodes_path[i], fdt_strerror(rc));
- } else {
- printf("Delete node %s\n", nodes_path[i]);
- }
- }
-
- disable_thermal_cpu_nodes(blob, disabled_cores);
- disable_pmu_cpu_nodes(blob, disabled_cores);
-
- return 0;
-}
-
static int cleanup_nodes_for_efi(void *blob)
{
static const char * const path[][2] = {
@@ -1277,48 +1215,6 @@
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node) {
- const char *type;
- int temp, ret;
-
- type = fdt_getprop(blob, trip, "type", NULL);
- if (!type)
- continue;
-
- temp = 0;
- if (!strcmp(type, "critical"))
- temp = 1000 * maxc;
- else if (!strcmp(type, "passive"))
- temp = 1000 * (maxc - 10);
- if (temp) {
- ret = fdt_setprop_u32(blob, trip, "temperature", temp);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
#define OPTEE_SHM_SIZE 0x00400000
static int ft_add_optee_node(void *fdt, struct bd_info *bd)
{
@@ -1397,6 +1293,13 @@
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ static const char * const nodes_path[] = {
+ "/cpus/cpu@0",
+ "/cpus/cpu@1",
+ "/cpus/cpu@2",
+ "/cpus/cpu@3",
+ };
+
#ifdef CONFIG_IMX8MQ
int i = 0;
int rc;
@@ -1440,13 +1343,6 @@
/* Disable the CPU idle for A0 chip since the HW does not support it */
if (is_soc_rev(CHIP_REV_1_0)) {
- static const char * const nodes_path[] = {
- "/cpus/cpu@0",
- "/cpus/cpu@1",
- "/cpus/cpu@2",
- "/cpus/cpu@3",
- };
-
for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
nodeoff = fdt_path_offset(blob, nodes_path[i]);
if (nodeoff < 0)
@@ -1478,16 +1374,16 @@
}
if (is_imx8md())
- disable_cpu_nodes(blob, 2);
+ disable_cpu_nodes(blob, nodes_path, 2, 4);
#elif defined(CONFIG_IMX8MM)
if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
disable_vpu_nodes(blob);
if (is_imx8mmd() || is_imx8mmdl())
- disable_cpu_nodes(blob, 2);
+ disable_cpu_nodes(blob, nodes_path, 2, 4);
else if (is_imx8mms() || is_imx8mmsl())
- disable_cpu_nodes(blob, 3);
+ disable_cpu_nodes(blob, nodes_path, 3, 4);
#elif defined(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
@@ -1504,9 +1400,9 @@
#endif
if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
- disable_cpu_nodes(blob, 2);
+ disable_cpu_nodes(blob, nodes_path, 2, 4);
else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
- disable_cpu_nodes(blob, 3);
+ disable_cpu_nodes(blob, nodes_path, 3, 4);
#elif defined(CONFIG_IMX8MP)
if (is_imx8mpul()) {
@@ -1533,7 +1429,7 @@
disable_dsp_nodes(blob);
if (is_imx8mpd())
- disable_cpu_nodes(blob, 2);
+ disable_cpu_nodes(blob, nodes_path, 2, 4);
#endif
cleanup_nodes_for_efi(blob);
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index e892da8..4d32c28 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,11 +5,6 @@
help
This option enables the support for AHAB secure boot.
-config IMX9_LOW_DRIVE_MODE
- bool "Configure to i.MX9 low drive mode"
- help
- This option enables the settings for iMX9 low drive mode.
-
config IMX9
bool
select BINMAN
@@ -30,6 +25,7 @@
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
+ select OF_BOARD_FIXUP
select IMX93
imply OF_UPSTREAM
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 0abf457..12685f9 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -41,6 +41,7 @@
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
+ FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
};
/* return in khz */
@@ -603,7 +604,7 @@
{
u32 div;
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
div = 3; /* 266.67 Mhz */
else
div = 2; /* 400 Mhz */
@@ -700,8 +701,7 @@
#endif
-#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
-struct imx_clk_setting imx_clk_settings[] = {
+struct imx_clk_setting imx_clk_ld_settings[] = {
/* Set A55 clk to 500M */
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 200M */
@@ -728,7 +728,7 @@
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#else
+
struct imx_clk_setting imx_clk_settings[] = {
/*
* Set A55 clk to 500M. This clock root is normally used as intermediate
@@ -762,9 +762,18 @@
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#endif
+
+void bus_clock_init_low_drive(void)
+{
+ int i;
-int clock_init(void)
+ for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
+ ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+ imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+ }
+}
+
+void bus_clock_init(void)
{
int i;
@@ -772,9 +781,11 @@
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src, imx_clk_settings[i].div);
}
+}
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
- set_arm_clk(MHZ(900));
+int clock_init_early(void)
+{
+ int i;
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
@@ -792,6 +803,19 @@
return 0;
}
+/* Set bus and A55 core clock per voltage mode */
+int clock_init_late(void)
+{
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
+ set_arm_core_max_clk();
+ } else {
+ bus_clock_init();
+ }
+
+ return 0;
+}
+
int set_clk_eqos(enum enet_freq type)
{
u32 eqos_post_div;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 3220822..04b2120 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -96,10 +96,16 @@
*/
u32 get_cpu_speed_grade_hz(void)
{
- u32 speed, max_speed;
+ int ret;
+ u32 bank, word, speed, max_speed;
u32 val;
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
- fuse_read(2, 3, &val);
val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
speed = MHZ(2300) - val * MHZ(100);
@@ -122,9 +128,15 @@
*/
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
- u32 val;
+ int ret;
+ u32 bank, word, val;
- fuse_read(2, 3, &val);
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
val = FIELD_GET(MARKETING_GRADING_MASK, val);
if (minc && maxc) {
@@ -160,13 +172,29 @@
static u32 get_cpu_variant_type(u32 type)
{
- /* word 19 */
- u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
- u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+ u32 bank, word, val, val2;
+ int ret;
+
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ bank = HW_CFG2 / NUM_WORDS_PER_BANK;
+ word = HW_CFG2 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val2);
+ if (ret)
+ val2 = 0; /* If read fuse failed, return as blank fuse */
+
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+ /* Low performance 93 part */
+ if (((val >> 6) & 0x3F) == 0xE && npu_disable)
+ return core1_disable ? MXC_CPU_IMX9301 : MXC_CPU_IMX9302;
+
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9322;
@@ -216,15 +244,9 @@
void init_wdog(void)
{
- u32 src_val;
-
disable_wdog((void __iomem *)WDG3_BASE_ADDR);
disable_wdog((void __iomem *)WDG4_BASE_ADDR);
disable_wdog((void __iomem *)WDG5_BASE_ADDR);
-
- src_val = readl(0x54460018); /* reset mask */
- src_val &= ~0x1c;
- writel(src_val, 0x54460018);
}
static struct mm_region imx93_mem_map[] = {
@@ -480,12 +502,21 @@
if (ret)
goto err;
- mac[0] = val[1] >> 24;
- mac[1] = val[1] >> 16;
- mac[2] = val[0] >> 24;
- mac[3] = val[0] >> 16;
- mac[4] = val[0] >> 8;
- mac[5] = val[0];
+ if (is_imx93() && is_soc_rev(CHIP_REV_1_0)) {
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ } else {
+ mac[0] = val[0] >> 24;
+ mac[1] = val[0] >> 16;
+ mac[2] = val[0] >> 8;
+ mac[3] = val[0];
+ mac[4] = val[1] >> 24;
+ mac[5] = val[1] >> 16;
+ }
}
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
@@ -507,64 +538,152 @@
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
+void build_info(void)
{
- int minc, maxc;
- int node, trip;
+ u32 fw_version, sha1, res, status;
+ int ret;
+
+ printf("\nBuildInfo:\n");
+
+ ret = ele_get_fw_status(&status, &res);
+ if (ret) {
+ printf(" - ELE firmware status failed %d, 0x%x\n", ret, res);
+ } else if ((status & 0xff) == 1) {
+ ret = ele_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf(" - ELE firmware version failed %d, 0x%x\n", ret, res);
+ } else {
+ printf(" - ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff0000)) >> 16,
+ (fw_version & (0x0000fff0)) >> 4,
+ (fw_version & (0x0000000f)), sha1);
+ ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
+ }
+ } else {
+ printf(" - ELE firmware not included\n");
+ }
+ puts("\n");
+}
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
+int arch_misc_init(void)
+{
+ build_info();
+ return 0;
+}
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
+struct low_drive_freq_entry {
+ const char *node_path;
+ u32 clk;
+ u32 new_rate;
+};
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
+static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 new_rate)
+{
+#define MAX_ASSIGNED_CLKS 8
+ int cnt, j;
+ u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/
- get_cpu_temp_grade(&minc, &maxc);
+ cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates",
+ assignedclks, MAX_ASSIGNED_CLKS);
+ if (cnt > 0) {
+ if (cnt <= clk_index)
+ return -ENOENT;
- fdt_for_each_subnode(trip, blob, node) {
- const char *type;
- int temp, ret;
+ if (assignedclks[clk_index] <= new_rate)
+ return 0;
- type = fdt_getprop(blob, trip, "type", NULL);
- if (!type)
- continue;
+ assignedclks[clk_index] = new_rate;
+ for (j = 0; j < cnt; j++)
+ assignedclks[j] = cpu_to_fdt32(assignedclks[j]);
- temp = 0;
- if (!strcmp(type, "critical"))
- temp = 1000 * (maxc - 5);
- else if (!strcmp(type, "passive"))
- temp = 1000 * (maxc - 10);
- if (temp) {
- ret = fdt_setprop_u32(blob, trip, "temperature", temp);
- if (ret)
- return ret;
+ return fdt_setprop(fdt, node_off, "assigned-clock-rates", &assignedclks,
+ cnt * sizeof(u32));
+ }
+
+ return -ENOENT;
+}
+
+static int low_drive_freq_update(void *blob)
+{
+ int nodeoff, ret;
+ int i;
+
+ /* Update kernel dtb clocks for low drive mode */
+ struct low_drive_freq_entry table[] = {
+ {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667},
+ {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667},
+ {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667},
+ };
+
+ for (i = 0; i < ARRAY_SIZE(table); i++) {
+ nodeoff = fdt_path_offset(blob, table[i].node_path);
+ if (nodeoff >= 0) {
+ ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk,
+ table[i].new_rate);
+ if (!ret)
+ printf("%s freq updated\n", table[i].node_path);
}
}
return 0;
}
+#ifdef CONFIG_OF_BOARD_FIXUP
+#ifndef CONFIG_SPL_BUILD
+int board_fix_fdt(void *fdt)
+{
+ /* Update dtb clocks for low drive mode */
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ int nodeoff;
+ int i;
+
+ struct low_drive_freq_entry table[] = {
+ {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667},
+ {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667},
+ {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667},
+ };
+
+ for (i = 0; i < ARRAY_SIZE(table); i++) {
+ nodeoff = fdt_path_offset(fdt, table[i].node_path);
+ if (nodeoff >= 0)
+ low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk,
+ table[i].new_rate);
+ }
+ }
+
+ return 0;
+}
+#endif
+#endif
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ static const char * const nodes_path[] = {
+ "/cpus/cpu@0",
+ "/cpus/cpu@100",
+ };
+
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311() || is_imx9301())
+ disable_cpu_nodes(blob, nodes_path, 1, 2);
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ low_drive_freq_update(blob);
+
return 0;
}
#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
void get_board_serial(struct tag_serialnr *serialnr)
{
- printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
- gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]);
+ printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]),
+ __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]),
+ __be32_to_cpu(gd->arch.uid[3]));
- serialnr->low = gd->arch.uid[0];
- serialnr->high = gd->arch.uid[3];
+ serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
+ serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
}
#endif
@@ -586,7 +705,7 @@
/* Disable wdog */
init_wdog();
- clock_init();
+ clock_init_early();
trdc_early_init();
@@ -752,7 +871,7 @@
/* power on */
clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
val = readl(&mix_regs->func_stat);
- while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
val = readl(&mix_regs->func_stat);
return 0;
@@ -792,7 +911,7 @@
(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
- u32 val;
+ u32 val, i;
if (m33_is_rom_kicked())
return -EPERM;
@@ -817,6 +936,18 @@
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+ /* OSCCA enabled, reconfigure TRDC for TCM access, otherwise ECC init will raise error */
+ val = readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28);
+ if (val & BIT(0)) {
+ trdc_mbc_set_control(0x44270000, 1, 0, 0x6600);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x44270000, 1, 3, 0, i, true, 0);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x44270000, 1, 3, 1, i, true, 0);
+ }
+
/* Clear M33 TCM for ECC */
memset((void *)(ulong)0x201e0000, 0, 0x40000);
@@ -864,3 +995,22 @@
return 0;
}
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void)
+{
+ u32 speed = get_cpu_speed_grade_hz();
+ enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
+
+ if (is_imx93()) {
+ if (speed == 1700000000)
+ voltage = VOLT_OVER_DRIVE;
+ else if (speed == 1400000000)
+ voltage = VOLT_NOMINAL_DRIVE;
+ else if (speed == 900000000 || speed == 800000000)
+ voltage = VOLT_LOW_DRIVE;
+ else
+ printf("Unexpected A55 freq %u, default to OD\n", speed);
+ }
+
+ return voltage;
+}
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index 8cdb284..ef0f8b5 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -4,12 +4,13 @@
*/
#include <log.h>
+#include <div64.h>
+#include <hang.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <div64.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
@@ -18,6 +19,26 @@
#define MRC_MAX_NUM 2
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF)
+
+enum {
+ /* Order following ELE API Spec, not change */
+ TRDC_A,
+ TRDC_W,
+ TRDC_M,
+ TRDC_N,
+};
+
+/* Just make it easier to know what the parameter is */
+#define MBC(X) (X)
+#define MRC(X) (X)
+#define GLOBAL_ID(X) (X)
+#define MEM(X) (X)
+#define DOM(X) (X)
+/*
+ *0|SPR|SPW|SPX,0|SUR|SUW|SWX, 0|NPR|NPW|NPX, 0|NUR|NUW|NUX
+ */
+#define PERM(X) (X)
struct mbc_mem_dom {
u32 mem_glbcfg[4];
@@ -134,6 +155,22 @@
return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
}
+static u32 trdc_mbc_blk_num(ulong trdc_reg, u32 mbc_x, u32 mem_x)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 glbcfg;
+
+ if (mbc_base == 0)
+ return 0;
+
+ /* only first dom has the glbcfg */
+ mbc_dom = &mbc_base->mem_dom[0];
+ glbcfg = readl((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]);
+
+ return MBC_BLK_NUM(glbcfg);
+}
+
int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
@@ -363,69 +400,87 @@
void trdc_early_init(void)
{
int ret = 0, i;
+ u32 blks;
- ret |= release_rdc(0);
- ret |= release_rdc(2);
- ret |= release_rdc(1);
- ret |= release_rdc(3);
+ ret |= release_rdc(TRDC_A);
+ ret |= release_rdc(TRDC_M);
+ ret |= release_rdc(TRDC_W);
+ ret |= release_rdc(TRDC_N);
- if (!ret) {
- /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
- trdc_mbc_set_control(0x49010000, 3, 0, 0x7700);
+ if (ret) {
+ hang();
+ return;
+ }
+
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0);
+ blks = trdc_mbc_blk_num(TRDC_NIC_BASE, MBC(3), MEM(0));
+ for (i = 0; i < blks; i++) {
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(1), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(1), i,
+ true, GLOBAL_ID(0));
}
}
void trdc_init(void)
{
/* TRDC mega */
- if (trdc_mrc_enabled(0x49010000)) {
+ if (trdc_mrc_enabled(TRDC_NIC_BASE)) {
/* DDR */
- trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
+ trdc_mrc_set_control(TRDC_NIC_BASE, MRC(0), GLOBAL_ID(0), PERM(0x7777));
/* ELE */
- trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(0), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* MTR */
- trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(1), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* M33 */
- trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(2), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* A55*/
- trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(3), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* For USDHC1 to DDR, USDHC1 is default force to non-secure */
- trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(5), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* For USDHC2 to DDR, USDHC2 is default force to non-secure */
- trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(6), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* eDMA */
- trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(7), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/*CoreSight, TestPort*/
- trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(8), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/* DAP */
- trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(9), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/*SoC masters */
- trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(10), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
/*USB*/
- trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(11), 0x80000000,
+ 0xFFFFFFFF, false, GLOBAL_ID(0));
}
}
@@ -504,78 +559,78 @@
printf("TRDC AONMIX MBC\n");
- trdc_mbc_control_dump(0x44270000, 0, 0);
- trdc_mbc_control_dump(0x44270000, 1, 0);
+ trdc_mbc_control_dump(TRDC_AON_BASE, MBC(0), GLOBAL_ID(0));
+ trdc_mbc_control_dump(TRDC_AON_BASE, MBC(1), GLOBAL_ID(0));
for (i = 0; i < 11; i++)
- trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_AON_BASE, MBC(0), DOM(3), MEM(0), i);
for (i = 0; i < 1; i++)
- trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_AON_BASE, MBC(0), DOM(3), MEM(1), i);
for (i = 0; i < 4; i++)
- trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_AON_BASE, MBC(1), DOM(3), MEM(0), i);
for (i = 0; i < 4; i++)
- trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_AON_BASE, MBC(1), DOM(3), MEM(1), i);
printf("TRDC WAKEUP MBC\n");
- trdc_mbc_control_dump(0x42460000, 0, 0);
- trdc_mbc_control_dump(0x42460000, 1, 0);
+ trdc_mbc_control_dump(TRDC_WAKEUP_BASE, MBC(0), GLOBAL_ID(0));
+ trdc_mbc_control_dump(TRDC_WAKEUP_BASE, MBC(1), GLOBAL_ID(0));
for (i = 0; i < 15; i++)
- trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, MBC(0), DOM(3), MEM(0), i);
- trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0);
- trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, MBC(0), DOM(3), MEM(1), 0);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, 0, 3, 2, 0);
for (i = 0; i < 2; i++)
- trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, MBC(1), DOM(3), MEM(0), i);
- trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0);
- trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0);
- trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, MBC(1), DOM(3), MEM(1), 0);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, 1, 3, 2, 0);
+ trdc_mbc_mem_dump(TRDC_WAKEUP_BASE, MBC(1), DOM(3), MEM(3), 0);
printf("TRDC NICMIX MBC\n");
- trdc_mbc_control_dump(0x49010000, 0, 0);
- trdc_mbc_control_dump(0x49010000, 1, 0);
- trdc_mbc_control_dump(0x49010000, 2, 0);
- trdc_mbc_control_dump(0x49010000, 3, 0);
+ trdc_mbc_control_dump(TRDC_NIC_BASE, MBC(0), GLOBAL_ID(0));
+ trdc_mbc_control_dump(TRDC_NIC_BASE, MBC(1), GLOBAL_ID(0));
+ trdc_mbc_control_dump(TRDC_NIC_BASE, MBC(2), GLOBAL_ID(0));
+ trdc_mbc_control_dump(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0));
for (i = 0; i < 7; i++)
- trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(0), DOM(3), MEM(0), i);
for (i = 0; i < 2; i++)
- trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(0), DOM(3), MEM(1), i);
for (i = 0; i < 5; i++)
- trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(0), DOM(3), MEM(2), i);
for (i = 0; i < 6; i++)
- trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(0), DOM(3), MEM(3), i);
for (i = 0; i < 1; i++)
- trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(1), DOM(3), MEM(0), i);
for (i = 0; i < 1; i++)
- trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(1), DOM(3), MEM(1), i);
for (i = 0; i < 3; i++)
- trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(1), DOM(3), MEM(2), i);
for (i = 0; i < 3; i++)
- trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(1), DOM(3), MEM(3), i);
for (i = 0; i < 2; i++)
- trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(2), DOM(3), MEM(0), i);
for (i = 0; i < 2; i++)
- trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(2), DOM(3), MEM(1), i);
for (i = 0; i < 5; i++)
- trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i);
for (i = 0; i < 5; i++)
- trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i);
+ trdc_mbc_mem_dump(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(1), i);
}
#endif
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index bee9d5f..1f8022e 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -393,6 +393,7 @@
bool "mx6slevk"
depends on MX6SL
select SUPPORT_SPL
+ imply OF_UPSTREAM
config TARGET_MX6SLLEVK
bool "mx6sll evk"
@@ -540,6 +541,16 @@
select BOARD_LATE_INIT
select MX6UL_LITESOM
+config TARGET_LXR2
+ bool "Comvetia i.MX6Q LXR2"
+ depends on MX6Q
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_PCM058
bool "Phytec PCM058 i.MX6 Quad"
depends on MX6Q
@@ -695,6 +706,7 @@
source "board/bsh/imx6ulz_smm_m2/Kconfig"
source "board/bticino/mamoj/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
+source "board/comvetia/lxr2/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/engicam/imx6q/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 3a3e01f..2c0c77e 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -585,6 +585,10 @@
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ {"ecspi3:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0a)},
+ {"ecspi3:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x1a)},
+ {"ecspi3:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x2a)},
+ {"ecspi3:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x3a)},
/* 4 bit bus width */
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 9a86f5c..3982f4c 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -33,8 +33,17 @@
ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
- return image_offset +
- (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000);
+ u32 sector = 0;
+
+ /*
+ * Some boards use this value even though MMC is not enabled in SPL, for
+ * example imx8mn_bsh_smm_s2
+ */
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+#endif
+
+ return image_offset + sector * 512 - 0x8000;
}
static int is_boot_from_stream_device(u32 boot)
@@ -99,18 +108,13 @@
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) {
struct spl_load_info load;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, pagesize);
- load.read = spl_romapi_read_seekable;
+ spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize);
return spl_load_simple_fit(spl_image, &load, offset, header);
} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, pagesize);
- load.read = spl_romapi_read_seekable;
-
+ spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize);
ret = spl_load_imx_container(spl_image, &load, offset);
} else {
/* TODO */
@@ -332,10 +336,7 @@
ss.end = p;
ss.pagesize = pagesize;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, 1);
- load.read = spl_romapi_read_stream;
- load.priv = &ss;
+ spl_load_init(&load, spl_romapi_read_stream, &ss, 1);
return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr);
}
diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index 72a752d..595fc39 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -282,6 +282,15 @@
}
spl_enable_cache();
+ if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
+ spl_boot_device() == BOOT_DEVICE_ETHERNET) {
+ struct udevice *cpswdev;
+
+ if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
+ &cpswdev))
+ printf("Failed to probe am65_cpsw_nuss driver\n");
+ }
+
fixup_a53_cpu_freq_by_speed_grade();
}
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index eaa7d36..df48ec8 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -104,7 +104,7 @@
gd->cur_serial_dev = dev;
gd->flags |= GD_FLG_SERIAL_READY;
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
return 0;
}
diff --git a/arch/arm/mach-k3/r5/sysfw-loader.c b/arch/arm/mach-k3/r5/sysfw-loader.c
index 94d051b..188731e 100644
--- a/arch/arm/mach-k3/r5/sysfw-loader.c
+++ b/arch/arm/mach-k3/r5/sysfw-loader.c
@@ -451,7 +451,7 @@
* the case when continuing to boot serially from the same
* UART that the ROM loaded the initial bootloader from.
*/
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
early_console_init();
#endif
ret = spl_ymodem_load_image(&spl_image, &bootdev);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 4a83287..c1a1a33 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -149,6 +149,7 @@
select SPL_SYS_MALLOC_SIMPLE
select SYS_I2C_MVTWSI
select ATSHA204A
+ select I2C_EEPROM
select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
config TARGET_TURRIS_MOX
diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig
index 542f480..c2bef89 100644
--- a/arch/arm/mach-octeontx/Kconfig
+++ b/arch/arm/mach-octeontx/Kconfig
@@ -13,7 +13,6 @@
endchoice
config SYS_SOC
- string
default "octeontx"
endif
diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig
index f6158df..c6a477b 100644
--- a/arch/arm/mach-octeontx2/Kconfig
+++ b/arch/arm/mach-octeontx2/Kconfig
@@ -13,7 +13,6 @@
endchoice
config SYS_SOC
- string
default "octeontx2"
endif
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 84a60de..abdc1e4 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -337,14 +337,6 @@
return 0;
}
-/*
- * This function is the place to do per-board things such as ramp up the
- * MPU clock frequency.
- */
-__weak void am33xx_spl_board_init(void)
-{
-}
-
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
static void rtc32k_enable(void)
{
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index e1ea351..649bc07 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -269,7 +269,7 @@
debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
}
-void spl_board_init(void)
+void spl_soc_init(void)
{
/* Prepare console output */
preloader_console_init();
@@ -286,9 +286,6 @@
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
#endif
-#ifdef CONFIG_AM33XX
- am33xx_spl_board_init();
-#endif
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
spl_boot_ipu();
diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c
index 7348e92..1e30a06 100644
--- a/arch/arm/mach-omap2/omap3/emac.c
+++ b/arch/arm/mach-omap2/omap3/emac.c
@@ -9,6 +9,7 @@
#include <net.h>
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
+#include <netdev.h>
/*
* Initializes on-chip ethernet controllers.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdae..3b13891 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -8,9 +8,9 @@
# inaccessible/protected memory (and the bootrom-helper assumes that
# the stack-pointer is valid before switching to the U-Boot stack).
obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
+obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 8a57b82..3fadf7e 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -25,7 +25,7 @@
#include <part.h>
#include <ram.h>
#include <syscon.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <u-boot/crc.h>
#include <u-boot/sha256.h>
#include <asm/cache.h>
@@ -202,14 +202,6 @@
int board_init(void)
{
- int ret;
-
-#ifdef CONFIG_DM_REGULATOR
- ret = regulators_enable_boot_on(false);
- if (ret)
- debug("%s: Cannot enable boot on regulator\n", __func__);
-#endif
-
return 0;
}
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 3ce7e79..f4d29bb 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -13,6 +13,7 @@
#include <ram.h>
#include <spl.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/timer.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
@@ -79,33 +80,6 @@
return MMCSD_MODE_RAW;
}
-#define TIMER_LOAD_COUNT_L 0x00
-#define TIMER_LOAD_COUNT_H 0x04
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_EN 0x1
-#define TIMER_FMODE BIT(0)
-#define TIMER_RMODE BIT(1)
-
-__weak void rockchip_stimer_init(void)
-{
-#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
- /* If Timer already enabled, don't re-init it */
- u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
- if (reg & TIMER_EN)
- return;
-#ifndef CONFIG_ARM64
- asm volatile("mcr p15, 0, %0, c14, c0, 0"
- : : "r"(CONFIG_COUNTER_FREQUENCY));
-#endif
- writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
- writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
- TIMER_CONTROL_REG);
-#endif
-}
-
__weak int board_early_init_f(void)
{
return 0;
diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c
new file mode 100644
index 0000000..b29f334
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl_common.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE BIT(0)
+#define TIMER_RMODE BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+ if (reg & TIMER_EN)
+ return;
+
+#ifndef CONFIG_ARM64
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(CONFIG_COUNTER_FREQUENCY));
+#endif
+
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+#endif
+}
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 597a5ca..bbb9329 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -14,41 +14,13 @@
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/timer.h>
#include <linux/bitops.h>
#if CONFIG_IS_ENABLED(BANNER_PRINT)
#include <timestamp.h>
#endif
-#define TIMER_LOAD_COUNT_L 0x00
-#define TIMER_LOAD_COUNT_H 0x04
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_EN 0x1
-#define TIMER_FMODE BIT(0)
-#define TIMER_RMODE BIT(1)
-
-__weak void rockchip_stimer_init(void)
-{
-#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
- /* If Timer already enabled, don't re-init it */
- u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
- if (reg & TIMER_EN)
- return;
-
-#ifndef CONFIG_ARM64
- asm volatile("mcr p15, 0, %0, c14, c0, 0"
- : : "r"(CONFIG_COUNTER_FREQUENCY));
-#endif
-
- writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
- writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
- TIMER_CONTROL_REG);
-#endif
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index b439a19..2ab2ceb 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -18,6 +18,7 @@
#include <dm/read.h>
#include <power/regulator.h>
#include <env.h>
+#include <fdt_support.h>
#include <init.h>
#include <linux/arm-smccc.h>
#include <linux/bug.h>
@@ -37,9 +38,18 @@
struct mm_region *mem_map = rbx_mem_map;
+static struct {
+ phys_addr_t start;
+ phys_size_t size;
+} prevbl_ddr_banks[CONFIG_NR_DRAM_BANKS] __section(".data") = { 0 };
+
int dram_init(void)
{
- return fdtdec_setup_mem_size_base();
+ /*
+ * gd->ram_base / ram_size have been setup already
+ * in qcom_parse_memory().
+ */
+ return 0;
}
static int ddr_bank_cmp(const void *v1, const void *v2)
@@ -57,21 +67,69 @@
return (res1->start >> 24) - (res2->start >> 24);
}
+/* This has to be done post-relocation since gd->bd isn't preserved */
+static void qcom_configure_bi_dram(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start;
+ gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size;
+ }
+}
+
int dram_init_banksize(void)
{
- int ret;
+ qcom_configure_bi_dram();
- ret = fdtdec_setup_memory_banksize();
- if (ret < 0)
- return ret;
+ return 0;
+}
- if (CONFIG_NR_DRAM_BANKS < 2)
- return 0;
+static void qcom_parse_memory(void)
+{
+ ofnode node;
+ const fdt64_t *memory;
+ int memsize;
+ phys_addr_t ram_end = 0;
+ int i, j, banks;
+
+ node = ofnode_path("/memory");
+ if (!ofnode_valid(node)) {
+ log_err("No memory node found in device tree!\n");
+ return;
+ }
+ memory = ofnode_read_prop(node, "reg", &memsize);
+ if (!memory) {
+ log_err("No memory configuration was provided by the previous bootloader!\n");
+ return;
+ }
+
+ banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
+
+ if (memsize / sizeof(u64) > CONFIG_NR_DRAM_BANKS * 2)
+ log_err("Provided more than the max of %d memory banks\n", CONFIG_NR_DRAM_BANKS);
+
+ if (banks > CONFIG_NR_DRAM_BANKS)
+ log_err("Provided more memory banks than we can handle\n");
+
+ for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
+ prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
+ prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
+ /* SM8650 boards sometimes have empty regions! */
+ if (!prevbl_ddr_banks[j].size) {
+ j--;
+ continue;
+ }
+ ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size);
+ }
/* Sort our RAM banks -_- */
- qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
+ qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp);
- return 0;
+ gd->ram_base = prevbl_ddr_banks[0].start;
+ gd->ram_size = ram_end - gd->ram_base;
+ debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n",
+ gd->ram_base, gd->ram_size, ram_end);
}
static void show_psci_version(void)
@@ -85,26 +143,43 @@
PSCI_VERSION_MINOR(res.a0));
}
+/* We support booting U-Boot with an internal DT when running as a first-stage bootloader
+ * or for supporting quirky devices where it's easier to leave the downstream DT in place
+ * to improve ABL compatibility. Otherwise, we use the DT provided by ABL.
+ */
void *board_fdt_blob_setup(int *err)
{
- phys_addr_t fdt;
- /* Return DTB pointer passed by ABL */
+ struct fdt_header *fdt;
+ bool internal_valid, external_valid;
+
*err = 0;
- fdt = get_prev_bl_fdt_addr();
+ fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
+ external_valid = fdt && !fdt_check_header(fdt);
+ internal_valid = !fdt_check_header(gd->fdt_blob);
/*
- * If we bail then the board will simply not boot, instead let's
- * try and use the FDT built into U-Boot if there is one...
- * This avoids having a hard dependency on the previous stage bootloader
+ * There is no point returning an error here, U-Boot can't do anything useful in this situation.
+ * Bail out while we can still print a useful error message.
*/
+ if (!internal_valid && !external_valid)
+ panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
+ (phys_addr_t)fdt);
- if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) ||
- fdt_check_header((void *)fdt))) {
- debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
- return (void *)gd->fdt_blob;
+ if (internal_valid) {
+ debug("Using built in FDT\n");
+ } else {
+ debug("Using external FDT\n");
+ /* So we can use it before returning */
+ gd->fdt_blob = fdt;
}
- return (void *)fdt;
+ /*
+ * Parse the /memory node while we're here,
+ * this makes it easy to do other things early.
+ */
+ qcom_parse_memory();
+
+ return (void *)gd->fdt_blob;
}
void reset_cpu(void)
@@ -162,13 +237,72 @@
int board_init(void)
{
- regulators_enable_boot_on(false);
show_psci_version();
qcom_of_fixup_nodes();
qcom_board_init();
return 0;
}
+/**
+ * out_len includes the trailing null space
+ */
+static int get_cmdline_option(const char *cmdline, const char *key, char *out, int out_len)
+{
+ const char *p, *p_end;
+ int len;
+
+ p = strstr(cmdline, key);
+ if (!p)
+ return -ENOENT;
+
+ p += strlen(key);
+ p_end = strstr(p, " ");
+ if (!p_end)
+ return -ENOENT;
+
+ len = p_end - p;
+ if (len > out_len)
+ len = out_len;
+
+ strncpy(out, p, len);
+ out[len] = '\0';
+
+ return 0;
+}
+
+/* The bootargs are populated by the previous stage bootloader */
+static const char *get_cmdline(void)
+{
+ ofnode node;
+ static const char *cmdline = NULL;
+
+ if (cmdline)
+ return cmdline;
+
+ node = ofnode_path("/chosen");
+ if (!ofnode_valid(node))
+ return NULL;
+
+ cmdline = ofnode_read_string(node, "bootargs");
+
+ return cmdline;
+}
+
+void qcom_set_serialno(void)
+{
+ const char *cmdline = get_cmdline();
+ char serial[32];
+
+ if (!cmdline) {
+ log_debug("Failed to get bootargs\n");
+ return;
+ }
+
+ get_cmdline_option(cmdline, "androidboot.serialno=", serial, sizeof(serial));
+ if (serial[0] != '\0')
+ env_set("serial#", serial);
+}
+
/* Sets up the "board", and "soc" environment variables as well as constructing the devicetree
* path, with a few quirks to handle non-standard dtb filenames. This is not meant to be a
* comprehensive solution to automatically picking the DTB, but aims to be correct for the
@@ -267,6 +401,8 @@
snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
env_get("soc"), env_get("board"));
env_set("fdtfile", dt_path);
+
+ qcom_set_serialno();
}
void __weak qcom_late_init(void)
@@ -274,29 +410,41 @@
}
#define KERNEL_COMP_SIZE SZ_64M
+#ifdef CONFIG_FASTBOOT_BUF_SIZE
+#define FASTBOOT_BUF_SIZE CONFIG_FASTBOOT_BUF_SIZE
+#else
+#define FASTBOOT_BUF_SIZE 0
+#endif
-#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
+#define addr_alloc(size) lmb_alloc(size, SZ_2M)
/* Stolen from arch/arm/mach-apple/board.c */
int board_late_init(void)
{
- struct lmb lmb;
u32 status = 0;
-
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+ phys_addr_t addr;
+ struct fdt_header *fdt_blob = (struct fdt_header *)gd->fdt_blob;
/* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */
- status |= env_set_hex("kernel_addr_r", addr_alloc(&lmb, SZ_128M));
- status |= env_set_hex("ramdisk_addr_r", addr_alloc(&lmb, SZ_128M));
- status |= env_set_hex("kernel_comp_addr_r", addr_alloc(&lmb, KERNEL_COMP_SIZE));
+ addr = addr_alloc(SZ_128M);
+ status |= env_set_hex("kernel_addr_r", addr);
+ status |= env_set_hex("loadaddr", addr);
+ status |= env_set_hex("ramdisk_addr_r", addr_alloc(SZ_128M));
+ status |= env_set_hex("kernel_comp_addr_r", addr_alloc(KERNEL_COMP_SIZE));
status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
- status |= env_set_hex("scriptaddr", addr_alloc(&lmb, SZ_4M));
- status |= env_set_hex("pxefile_addr_r", addr_alloc(&lmb, SZ_4M));
- status |= env_set_hex("fdt_addr_r", addr_alloc(&lmb, SZ_2M));
+ if (IS_ENABLED(CONFIG_FASTBOOT))
+ status |= env_set_hex("fastboot_addr_r", addr_alloc(FASTBOOT_BUF_SIZE));
+ status |= env_set_hex("scriptaddr", addr_alloc(SZ_4M));
+ status |= env_set_hex("pxefile_addr_r", addr_alloc(SZ_4M));
+ addr = addr_alloc(SZ_2M);
+ status |= env_set_hex("fdt_addr_r", addr);
if (status)
log_warning("%s: Failed to set run time variables\n", __func__);
+ /* By default copy U-Boots FDT, it will be used as a fallback */
+ memcpy((void *)addr, (void *)gd->fdt_blob, fdt32_to_cpu(fdt_blob->totalsize));
+
configure_env();
qcom_late_init();
@@ -342,7 +490,7 @@
u64 get_page_table_size(void)
{
- return SZ_64K;
+ return SZ_1M;
}
static int fdt_cmp_res(const void *v1, const void *v2)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 6024959..1987853 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -14,9 +14,26 @@
#include <ram.h>
#include <asm/global_data.h>
#include <asm/system.h>
+#include <mach/stm32mp.h>
DECLARE_GLOBAL_DATA_PTR;
+int optee_get_reserved_memory(u32 *start, u32 *size)
+{
+ fdt_addr_t fdt_mem_size;
+ fdt_addr_t fdt_start;
+ ofnode node;
+
+ node = ofnode_path("/reserved-memory/optee");
+ if (!ofnode_valid(node))
+ return -ENOENT;
+
+ fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
+ *start = fdt_start;
+ *size = fdt_mem_size;
+ return (fdt_start < 0) ? fdt_start : 0;
+}
+
int dram_init(void)
{
struct ram_info ram;
@@ -45,9 +62,10 @@
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
+ int ret;
phys_size_t size;
phys_addr_t reg;
- struct lmb lmb;
+ u32 optee_start, optee_size;
if (!total_size)
return gd->ram_top;
@@ -57,17 +75,10 @@
* if the effective available memory is bigger
*/
gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
-
- /* found enough not-reserved memory to relocated U-Boot */
- lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
- boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
- /* add 8M for reserved memory for display, fdt, gd,... */
- size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
- reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
+ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
- if (!reg)
- reg = gd->ram_top - size;
+ ret = optee_get_reserved_memory(&optee_start, &optee_size);
+ reg = (!ret ? optee_start : gd->ram_top) - size;
/* before relocation, mark the U-Boot memory as cacheable by default */
if (!(gd->flags & GD_FLG_RELOC))
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp.h b/arch/arm/mach-stm32mp/include/mach/stm32mp.h
new file mode 100644
index 0000000..506a425
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/stm32mp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __MACH_STM32MP_H_
+#define __MACH_STM32MP_H_
+
+int optee_get_reserved_memory(u32 *start, u32 *size);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 478c3ef..64480da 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -30,8 +30,6 @@
*/
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
-struct lmb lmb;
-
u32 get_bootmode(void)
{
/* read bootmode from TAMP backup register */
@@ -80,7 +78,7 @@
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++) {
option = DCACHE_DEFAULT_OPTION;
- if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
+ if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
option = 0; /* INVALID ENTRY in TLB */
set_section_dcache(i, option);
}
@@ -143,9 +141,6 @@
void enable_caches(void)
{
- /* parse device tree when data cache is still activated */
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
/* I-cache is already enabled in start.S: icache_enable() not needed */
/* deactivate the data cache, early enabled in arch_cpu_init() */
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c
index bfbf420..a02a898 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
@@ -393,8 +393,7 @@
asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start));
for (;;) {
tmp = readl(reg);
- tmp &= mask;
- if ((tmp & val) == val)
+ if ((tmp & mask) == val)
return 0;
asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end));
if ((end - start) > delay)
diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c
index 6eae5c2..9c4fafb 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/spl.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c
@@ -18,6 +18,7 @@
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <mach/tzc.h>
+#include <mach/stm32mp.h>
#include <linux/libfdt.h>
u32 spl_boot_device(void)
@@ -110,22 +111,6 @@
return ram.size;
}
-static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
-{
- fdt_addr_t fdt_mem_size;
- fdt_addr_t fdt_start;
- ofnode node;
-
- node = ofnode_path("/reserved-memory/optee");
- if (!ofnode_valid(node))
- return -ENOENT;
-
- fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
- *start = fdt_start;
- *size = fdt_mem_size;
- return (fdt_start < 0) ? fdt_start : 0;
-}
-
#define CFG_SHMEM_SIZE 0x200000
#define STM32_TZC_NSID_ALL 0xffff
#define STM32_TZC_FILTER_ALL 3
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
index f096fe5..ca202be 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
@@ -148,8 +148,8 @@
*/
clrsetbits_le32(TAMP_SMCR,
TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
- FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
- FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
+ FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) |
+ FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F));
/* GPIOZ: deactivate the security */
writel(BIT(0), RCC_MP_AHB5ENSETR);
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 046e9fb..2b64ddc 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -399,7 +399,7 @@
return false;
/* Partition 0 is the user data partition, bootpart must be 1 or 2. */
- if (bootpart != 1 && bootpart != 2)
+ if (bootpart != EMMC_BOOT_PART_BOOT1 && bootpart != EMMC_BOOT_PART_BOOT2)
return false;
/* Failure to switch to the boot partition is fatal. */
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index d7abdc2..5f72e80 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -390,8 +390,7 @@
struct spl_load_info load;
debug("Found FIT image\n");
- spl_set_bl_len(&load, 1);
- load.read = spi_load_read;
+ spl_load_init(&load, spi_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load,
load_offset, header);
} else {
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 479137e..5c58386 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -187,9 +187,6 @@
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
- /* Set up boot-on regulators */
- regulators_enable_boot_on(_DEBUG);
-
return nvidia_board_init();
}
@@ -423,10 +420,6 @@
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
-#ifdef CONFIG_PCI
- gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
-#endif
-
#ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = 0x100000000;
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index c12543d..e2342b2 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -189,10 +189,6 @@
gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
}
-#ifdef CONFIG_PCI
- gd->pci_ram_top = ram_top;
-#endif
-
return 0;
}
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 8cb6494..49e449e 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -42,6 +42,8 @@
#define CRLAPB_DBG_LPD_CTRL_SETUP_CLK 0x01002002
#define CRLAPB_RST_LPD_DBG_RESET 0
+#define CRL_APB_SOFT_RESET_CTRL_MASK 0x10
+
struct crlapb_regs {
u32 reserved0[36];
u32 cpu_r5_ctrl; /* 0x90 */
@@ -51,7 +53,9 @@
u32 timestamp_ref_ctrl; /* 0x128 */
u32 reserved3[53];
u32 boot_mode; /* 0x200 */
- u32 reserved4_0[7];
+ u32 reserved4_0[5];
+ u32 soft_reset; /* 0x218 */
+ u32 reserved4_10;
u32 reset_reason; /* 0x220 */
u32 reserved4_1[6];
u32 rst_lpd_top; /* 0x23C */
@@ -63,6 +67,8 @@
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
+#define ZYNQMP_IOU_SECURE_SLCR 0xFF240000
+
#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@@ -126,6 +132,9 @@
#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
+#define ZYNQMP_CCI_REG_CCI_MISC_CTRL 0xFD5E0040
+#define ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN BIT(1)
+
#define ZYNQMP_APU_BASEADDR 0xFD5C0000
struct apu_regs {
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index bf39c54..3b4d9c6 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -340,6 +340,30 @@
return CMD_RET_SUCCESS;
}
+static int do_zynqmp_reboot(struct cmd_tbl *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ u32 multiboot;
+ int ret;
+
+ if (argc != cmdtp->maxargs)
+ return CMD_RET_USAGE;
+
+ multiboot = hextoul(argv[2], NULL);
+
+ ret = zynqmp_mmio_write(0xFFCA0010, 0xfff, multiboot);
+ if (ret != 0) {
+ printf("Failed: mmio write\n");
+ return ret;
+ }
+
+ /* issue soft reset */
+ writel(CRL_APB_SOFT_RESET_CTRL_MASK, &crlapb_base->soft_reset);
+
+ /* never get here */
+ return CMD_RET_SUCCESS;
+}
+
static struct cmd_tbl cmd_zynqmp_sub[] = {
U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
@@ -348,6 +372,7 @@
U_BOOT_CMD_MKENT(aes, 9, 0, do_zynqmp_aes, "", ""),
U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""),
U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""),
+ U_BOOT_CMD_MKENT(reboot, 3, 0, do_zynqmp_reboot, "", ""),
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""),
#endif
@@ -387,6 +412,7 @@
" long at address $src. Optional key_addr\n"
" can be specified if user key needs to\n"
" be used for decryption\n"
+ "zynqmp reboot multiboot - soft reboot to multiboot offset\n"
"zynqmp mmio_read address - read from address\n"
"zynqmp mmio_write address mask value - write value after masking to\n"
" address\n"
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index b811ac3..3fbd6a5 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -92,7 +92,7 @@
strmhz(buf3, gd->arch.flb_clk));
#ifdef CONFIG_PCI
printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->pci_clk),
+ strmhz(buf1, gd->arch.pci_clk),
strmhz(buf2, gd->arch.inp_clk),
strmhz(buf3, gd->arch.vco_clk));
#else
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index 93efc72..4ac8869 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -26,6 +26,8 @@
#if defined(CONFIG_FSL_ESDHC)
unsigned long sdhc_per_clk;
#endif
+ /** @pci_clk: PCI clock rate in Hz */
+ unsigned long pci_clk;
};
#include <asm-generic/global_data.h>
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index cf6ae5a..891e94b 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -22,7 +22,7 @@
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
if (IS_ENABLED(CONFIG_PCI))
- bd->bi_pcifreq = gd->pci_clk;
+ bd->bi_pcifreq = gd->arch.pci_clk;
#if defined(CONFIG_EXTRA_CLOCK)
bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c
index f2d02e4..3dcff80 100644
--- a/arch/m68k/lib/bootm.c
+++ b/arch/m68k/lib/bootm.c
@@ -9,7 +9,6 @@
#include <command.h>
#include <env.h>
#include <image.h>
-#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
#include <u-boot/zlib.h>
@@ -27,21 +26,14 @@
#define LINUX_MAX_ENVS 256
#define LINUX_MAX_ARGS 256
-static ulong get_sp (void);
static void set_clocks_in_mhz (struct bd_info *kbd);
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 1024);
-}
-
int do_bootm_linux(int flag, struct bootm_info *bmi)
{
struct bootm_headers *images = bmi->images;
int ret;
struct bd_info *kbd;
void (*kernel) (struct bd_info *, ulong, ulong, ulong, ulong);
- struct lmb *lmb = &images->lmb;
/*
* allow the PREP bootm subcommand, it is required for bootm to work
@@ -53,7 +45,7 @@
return 1;
/* allocate space for kernel copy of board info */
- ret = boot_get_kbd (lmb, &kbd);
+ ret = boot_get_kbd(&kbd);
if (ret) {
puts("ERROR with allocation of kernel bd\n");
goto error;
@@ -89,16 +81,6 @@
return 1;
}
-static ulong get_sp (void)
-{
- ulong sp;
-
- asm("movel %%a7, %%d0\n"
- "movel %%d0, %0\n": "=d"(sp): :"%d0");
-
- return sp;
-}
-
static void set_clocks_in_mhz (struct bd_info *kbd)
{
char *s;
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index cbe9d85..4879a41 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -15,7 +15,6 @@
#include <fdt_support.h>
#include <hang.h>
#include <image.h>
-#include <lmb.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -24,19 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("addik %0, r1, 0" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
-
static void boot_jump_linux(struct bootm_headers *images, int flag)
{
void (*thekernel)(char *cmdline, ulong rd, ulong dt);
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index adb6b6c..8719510 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -9,7 +9,6 @@
#include <env.h>
#include <image.h>
#include <fdt_support.h>
-#include <lmb.h>
#include <log.h>
#include <asm/addrspace.h>
#include <asm/global_data.h>
@@ -28,20 +27,6 @@
static char *linux_env_p;
static int linux_env_idx;
-static ulong arch_get_sp(void)
-{
- ulong ret;
-
- __asm__ __volatile__("move %0, $sp" : "=r"(ret) : );
-
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, arch_get_sp(), gd->ram_top, 4096);
-}
-
static void linux_cmdline_init(void)
{
linux_argc = 1;
@@ -225,9 +210,8 @@
}
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
- boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
- return boot_relocate_fdt(&images->lmb, &images->ft_addr,
- &images->ft_len);
+ boot_fdt_add_mem_rsv_regions(images->ft_addr);
+ return boot_relocate_fdt(&images->ft_addr, &images->ft_len);
#else
return 0;
#endif
@@ -248,7 +232,7 @@
images->initrd_start = virt_to_phys((void *)images->initrd_start);
images->initrd_end = virt_to_phys((void *)images->initrd_end);
- return image_setup_libfdt(images, images->ft_addr, &images->lmb);
+ return image_setup_libfdt(images, images->ft_addr, true);
}
static void boot_prep_linux(struct bootm_headers *images)
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index bdaa683..231a21c 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -327,8 +327,8 @@
{
ar934x_update_clock();
printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
- printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
- printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
+ printf("Memory: %8d MHz\n", gd->mem_clk / 1000000);
+ printf("AHB: %8d MHz\n", gd->bus_clk / 1000000);
return 0;
}
diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig
index 624039d..5d2186b 100644
--- a/arch/mips/mach-octeon/Kconfig
+++ b/arch/mips/mach-octeon/Kconfig
@@ -2,7 +2,6 @@
depends on ARCH_OCTEON
config SYS_SOC
- string
default "octeon"
config OCTEON_CN7XXX
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index c7744e8..c771da6 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -67,7 +67,7 @@
gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
- debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+ debug("%s: cpu: %lu, bus: %u\n", __func__, gd->cpu_clk, gd->bus_clk);
return 0;
}
diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c
index c74fe9d..15ce292 100644
--- a/arch/mips/mach-octeon/octeon_fdt.c
+++ b/arch/mips/mach-octeon/octeon_fdt.c
@@ -687,13 +687,6 @@
while (node_offset > 0 &&
!(found = !fdt_node_check_compatible(fdt, node_offset, compat))) {
node_offset = fdt_parent_offset(fdt, node_offset);
-#ifdef CONFIG_OCTEON_I2C_FDT
- bus = i2c_get_bus_num_fdt(node_offset);
- if (bus >= 0) {
- debug("%s: Found bus 0x%x\n", __func__, bus);
- return bus;
- }
-#endif
}
if (!found) {
printf("Error: node %d in device tree is not a child of the I2C bus\n",
diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c
index ce939ff..7131983 100644
--- a/arch/nios2/lib/bootm.c
+++ b/arch/nios2/lib/bootm.c
@@ -64,16 +64,3 @@
return 1;
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 6f378c4..aef1123 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -45,7 +45,7 @@
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
- tmp[0] = cpu_to_be32(gd->pci_clk);
+ tmp[0] = cpu_to_be32(gd->arch.pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
@@ -60,7 +60,7 @@
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
- tmp[0] = cpu_to_be32(gd->pci_clk);
+ tmp[0] = cpu_to_be32(gd->arch.pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 7246496..0185ab5 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -456,7 +456,7 @@
#if defined(CONFIG_ARCH_MPC837X)
gd->arch.sata_clk = sata_clk;
#endif
- gd->pci_clk = pci_sync_in;
+ gd->arch.pci_clk = pci_sync_in;
gd->cpu_clk = gd->arch.core_clk;
gd->bus_clk = gd->arch.csb_clk;
return 0;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a7b805b..739d14f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -940,22 +940,6 @@
return 0;
}
-#ifdef CONFIG_ARCH_MISC_INIT
-int arch_misc_init(void)
-{
- if (IS_ENABLED(CONFIG_FSL_CAAM)) {
- struct udevice *dev;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
- if (ret)
- printf("Failed to initialize caam_jr: %d\n", ret);
- }
-
- return 0;
-}
-#endif
-
void arch_preboot_os(void)
{
u32 msr;
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 03f801e..bed465c 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -408,11 +408,11 @@
}
#endif
-void cpu_mp_lmb_reserve(struct lmb *lmb)
+void cpu_mp_lmb_reserve(void)
{
u32 bootpg = determine_mp_bootpg(NULL);
- lmb_reserve(lmb, bootpg, 4096);
+ lmb_reserve(bootpg, 4096);
}
void setup_mp(void)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index a9efbbd..cc2ce61 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -87,6 +87,8 @@
#if defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
+ /** @pci_clk: PCI clock rate in Hz */
+ unsigned long pci_clk;
};
#include <asm-generic/global_data.h>
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index 8dacd27..b3f59be 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -6,10 +6,8 @@
#ifndef _ASM_MP_H_
#define _ASM_MP_H_
-#include <lmb.h>
-
void setup_mp(void);
-void cpu_mp_lmb_reserve(struct lmb *lmb);
+void cpu_mp_lmb_reserve(void);
u32 determine_mp_bootpg(unsigned int *pagesize);
int is_core_disabled(int nr);
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index bb819dc..ecc2aba 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -39,6 +39,7 @@
obj-y += extable.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
+obj-y += misc.o
obj-y += stack.o
obj-y += time.o
obj-y += traps.o
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 61e0872..dc44bf3 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -12,7 +12,6 @@
#include <cpu_func.h>
#include <env.h>
#include <init.h>
-#include <lmb.h>
#include <log.h>
#include <watchdog.h>
#include <command.h>
@@ -37,14 +36,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static ulong get_sp (void);
extern void ft_fixup_num_cores(void *blob);
static void set_clocks_in_mhz (struct bd_info *kbd);
-#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE
-#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
-#endif
-
static void boot_jump_linux(struct bootm_headers *images)
{
void (*kernel)(struct bd_info *, ulong r4, ulong r5, ulong r6,
@@ -116,41 +110,6 @@
return;
}
-void arch_lmb_reserve(struct lmb *lmb)
-{
- phys_size_t bootm_size;
- ulong size, bootmap_base;
-
- bootmap_base = env_get_bootm_low();
- bootm_size = env_get_bootm_size();
-
-#ifdef DEBUG
- if (((u64)bootmap_base + bootm_size) >
- (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size))
- puts("WARNING: bootm_low + bootm_size exceed total memory\n");
- if ((bootmap_base + bootm_size) > get_effective_memsize())
- puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");
-#endif
-
- size = min(bootm_size, get_effective_memsize());
- size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE);
-
- if (size < bootm_size) {
- ulong base = bootmap_base + size;
- printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n",
- size, (unsigned long long)bootm_size);
- lmb_reserve(lmb, base, bootm_size - size);
- }
-
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-
-#ifdef CONFIG_MP
- cpu_mp_lmb_reserve(lmb);
-#endif
-
- return;
-}
-
static void boot_prep_linux(struct bootm_headers *images)
{
#ifdef CONFIG_MP
@@ -166,7 +125,6 @@
static int boot_cmdline_linux(struct bootm_headers *images)
{
ulong of_size = images->ft_len;
- struct lmb *lmb = &images->lmb;
ulong *cmd_start = &images->cmdline_start;
ulong *cmd_end = &images->cmdline_end;
@@ -174,7 +132,7 @@
if (!of_size) {
/* allocate space and init command line */
- ret = boot_get_cmdline (lmb, cmd_start, cmd_end);
+ ret = boot_get_cmdline(cmd_start, cmd_end);
if (ret) {
puts("ERROR with allocation of cmdline\n");
return ret;
@@ -187,14 +145,13 @@
static int boot_bd_t_linux(struct bootm_headers *images)
{
ulong of_size = images->ft_len;
- struct lmb *lmb = &images->lmb;
struct bd_info **kbd = &images->kbd;
int ret = 0;
if (!of_size) {
/* allocate space for kernel copy of board info */
- ret = boot_get_kbd (lmb, kbd);
+ ret = boot_get_kbd(kbd);
if (ret) {
puts("ERROR with allocation of kernel bd\n");
return ret;
@@ -252,14 +209,6 @@
return 0;
}
-static ulong get_sp (void)
-{
- ulong sp;
-
- asm( "mr %0,1": "=r"(sp) : );
- return sp;
-}
-
static void set_clocks_in_mhz (struct bd_info *kbd)
{
char *s;
diff --git a/arch/powerpc/lib/misc.c b/arch/powerpc/lib/misc.c
new file mode 100644
index 0000000..4cd23b3
--- /dev/null
+++ b/arch/powerpc/lib/misc.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <image.h>
+#include <init.h>
+#include <lmb.h>
+
+#include <asm/mp.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+#ifndef CFG_SYS_LINUX_LOWMEM_MAX_SIZE
+#define CFG_SYS_LINUX_LOWMEM_MAX_SIZE (768 * 1024 * 1024)
+#endif
+
+int arch_misc_init(void)
+{
+ if (CONFIG_IS_ENABLED(CMD_BOOTM)) {
+ phys_size_t bootm_size;
+ ulong size, bootmap_base;
+
+ bootmap_base = env_get_bootm_low();
+ bootm_size = env_get_bootm_size();
+
+#ifdef DEBUG
+ if (((u64)bootmap_base + bootm_size) >
+ (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size))
+ puts("WARNING: bootm_low + bootm_size exceed total memory\n");
+ if ((bootmap_base + bootm_size) > get_effective_memsize())
+ puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");
+#endif
+
+ size = min(bootm_size, get_effective_memsize());
+ size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE);
+
+ if (size < bootm_size) {
+ ulong base = bootmap_base + size;
+
+ printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n",
+ size, (unsigned long long)bootm_size);
+ lmb_reserve(base, bootm_size - size);
+ }
+
+#ifdef CONFIG_MP
+ cpu_mp_lmb_reserve();
+#endif
+ }
+
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize caam_jr: %d\n", ret);
+ }
+
+ return 0;
+}
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016..fa37102 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -46,6 +46,9 @@
config TARGET_XILINX_MBV
bool "Support AMD/Xilinx MicroBlaze V"
+config TARGET_ASPEED_AST2700_IBEX
+ bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -81,6 +84,7 @@
# board-specific options below
source "board/andestech/ae350/Kconfig"
+source "board/aspeed/ibex_ast2700/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -97,6 +101,7 @@
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
+source "arch/riscv/cpu/ast2700/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
@@ -133,6 +138,7 @@
config SPL_FRAMEPOINTER
bool "Build SPL with frame pointer for stack unwinding"
+ depends on SPL
help
Choose this option to use the frame pointer so the stack can be
unwound if needed. This is useful for tracing where faults came
@@ -308,7 +314,10 @@
endmenu
config RISCV_ISA_A
- def_bool y
+ bool "Standard extension for Atomic Instructions"
+ default y
+ help
+ Adds "A" to the ISA string passed to the compiler.
config DMA_ADDR_T_64BIT
bool
@@ -437,7 +446,20 @@
If disable this, it will send IPI by CPUs node numbers of device tree.
config SHOW_REGS
+ default y
bool "Show registers on unhandled exception"
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ main U-Boot.
+
+config SPL_SHOW_REGS
+ bool "In SPL show registers on unhandled exception"
+ depends on SPL
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ SPL.
config RISCV_PRIV_1_9
bool "Use version 1.9 of the RISC-V priviledged specification"
@@ -450,7 +472,7 @@
memory is configured was also changed.
config STACK_SIZE_SHIFT
- int
+ int "Stack size shift"
default 14
config OF_BOARD_FIXUP
diff --git a/arch/riscv/cpu/ast2700/Kconfig b/arch/riscv/cpu/ast2700/Kconfig
new file mode 100644
index 0000000..b16f0fc
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/Kconfig
@@ -0,0 +1,6 @@
+config RISCV_AST2700
+ bool
+ imply CPU
+ imply CPU_RISCV
+ help
+ Run U-Boot on AST2700 with IBex RISC-V CPU integrated.
diff --git a/arch/riscv/cpu/ast2700/Makefile b/arch/riscv/cpu/ast2700/Makefile
new file mode 100644
index 0000000..1f843c7
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/Makefile
@@ -0,0 +1 @@
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/ast2700/cpu.c b/arch/riscv/cpu/ast2700/cpu.c
new file mode 100644
index 0000000..c154054
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2024, Aspeed Technology Inc.
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index d1113a5..9070946 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -44,8 +44,6 @@
__binman_sym_end = .;
} > .spl_mem
- . = ALIGN(8);
-
_end = .;
_image_binary_end = .;
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 17cda48..c4c4405 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -11,6 +11,7 @@
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/ast2700-ibex.dts b/arch/riscv/dts/ast2700-ibex.dts
new file mode 100644
index 0000000..f7a05e5
--- /dev/null
+++ b/arch/riscv/dts/ast2700-ibex.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "ast2700.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart12;
+ tick-timer = &ast_ibex_timer;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart12 {
+ status = "okay";
+ clock-frequency = <1846153>;
+};
diff --git a/arch/riscv/dts/ast2700-u-boot.dtsi b/arch/riscv/dts/ast2700-u-boot.dtsi
new file mode 100644
index 0000000..ddc08a4
--- /dev/null
+++ b/arch/riscv/dts/ast2700-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ cpus {
+ bootph-all;
+ };
+
+ memory@80000000 {
+ bootph-all;
+ };
+
+ soc0: soc@12000000 {
+ bootph-all;
+
+ sdrammc: sdrammc@12c00000 {
+ bootph-all;
+ };
+
+ syscon0: syscon@12c02000 {
+ bootph-all;
+ };
+ };
+
+ soc1: soc@14000000 {
+ bootph-all;
+
+ syscon1: syscon@14c02000 {
+ bootph-all;
+ };
+
+ uart12: serial@14c33b00 {
+ bootph-all;
+ };
+
+ ast_ibex_timer: timer {
+ bootph-all;
+ };
+ };
+
+};
diff --git a/arch/riscv/dts/ast2700.dtsi b/arch/riscv/dts/ast2700.dtsi
new file mode 100644
index 0000000..9b482df
--- /dev/null
+++ b/arch/riscv/dts/ast2700.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ model = "Aspeed AST2700 Ibex BootMCU";
+ compatible = "aspeed,ast2700-ibex";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "lowrisc,ibex";
+ device_type = "cpu";
+ reg = <0>;
+ comptaible = "riscv";
+ riscv,isa = "rv32imc";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ soc0: soc@12000000 {
+ compatible = "aspeed,soc1","simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdrammc: sdrammc@12c00000 {
+ compatible = "aspeed,ast2700-sdrammc";
+ reg = <0x12c00000 0x3000>, <0x13000000 0x1000>;
+ aspeed,scu0 = <&syscon0>;
+ aspeed,scu1 = <&syscon1>;
+ };
+
+ syscon0: syscon@12c02000 {
+ compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+ reg = <0x12c02000 0x1000>;
+ ranges = <0 0x12c02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ soc1: soc@14000000 {
+ compatible = "aspeed,soc1","simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon1: syscon@14c02000 {
+ compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+ reg = <0x14c02000 0x1000>;
+ ranges = <0 0x14c02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ uart12: serial@14c33b00 {
+ compatible = "ns16550a";
+ reg = <0x14c33b00 0x20>;
+ reg-shift = <2>;
+ no-loopback-test;
+ clock-frequency = <1846153>;
+ status = "disabled";
+ };
+
+ ast_ibex_timer: timer {
+ compatible = "aspeed,ast2700-ibex-timer";
+ clock-frequency = <200000000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 4b01434..8a7386b 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,cv1800.h>
/ {
#address-cells = <1>;
@@ -45,13 +46,6 @@
#clock-cells = <0>;
};
- sdhci_clk: sdhci-clock {
- compatible = "fixed-clock";
- clock-frequency = <375000000>;
- clock-output-names = "sdhci_clk";
- #clock-cells = <0>;
- };
-
eth_csrclk: eth-csrclk {
compatible = "fixed-clock";
clock-frequency = <250000000>;
@@ -66,13 +60,6 @@
#clock-cells = <0x0>;
};
- spif_clk: spi-flash-clock {
- compatible = "fixed-clock";
- clock-frequency = <300000000>;
- clock-output-names = "spif_clk";
- #clock-cells = <0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -163,8 +150,8 @@
compatible = "sophgo,cv1800b-dwmac";
reg = <0x04070000 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <ð_csrclk>, <ð_ptpclk>;
- clock-names = "stmmaceth", "ptp_ref";
+ clocks = <&clk CLK_ETH0_500M>, <&clk CLK_AXI4_ETH0>;
+ clock-names = "stmmaceth", "pclk";
status = "disabled";
};
@@ -172,7 +159,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -182,7 +170,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -192,7 +181,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -202,7 +192,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -212,7 +203,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -222,8 +214,8 @@
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
- clock-names = "core";
+ clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>;
+ clock-names = "core", "bus";
status = "disabled";
};
@@ -232,7 +224,7 @@
reg = <0x10000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&spif_clk>;
+ clocks = <&clk CLK_AHB_SF>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
diff --git a/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h
new file mode 100644
index 0000000..fbbcdb2
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#ifndef __ASM_AST2700_FMC_HDR_H__
+#define __ASM_AST2700_FMC_HDR_H__
+
+#include <linux/types.h>
+
+#define HDR_MAGIC 0x48545341 /* ASTH */
+#define HDR_PB_MAX 30
+
+enum prebuilt_type {
+ PBT_END_MARK = 0x0,
+
+ PBT_DDR4_PMU_TRAIN_IMEM,
+ PBT_DDR4_PMU_TRAIN_DMEM,
+ PBT_DDR4_2D_PMU_TRAIN_IMEM,
+ PBT_DDR4_2D_PMU_TRAIN_DMEM,
+ PBT_DDR5_PMU_TRAIN_IMEM,
+ PBT_DDR5_PMU_TRAIN_DMEM,
+ PBT_DP_FW,
+ PBT_UEFI_X64_AST2700,
+
+ PBT_NUM
+};
+
+struct fmc_hdr_preamble {
+ uint32_t magic;
+ uint32_t version;
+};
+
+struct fmc_hdr_body {
+ uint32_t fmc_size;
+ union {
+ struct {
+ uint32_t type;
+ uint32_t size;
+ } pbs[0];
+ uint32_t raz[29];
+ };
+};
+
+struct fmc_hdr {
+ struct fmc_hdr_preamble preamble;
+ struct fmc_hdr_body body;
+} __packed;
+
+int fmc_hdr_get_prebuilt(uint32_t type, uint32_t *ofst, uint32_t *size);
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/scu.h b/arch/riscv/include/asm/arch-ast2700/scu.h
new file mode 100644
index 0000000..1aa7d38
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/scu.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SCU_H__
+#define __ASM_AST2700_SCU_H__
+
+/* SCU0: CPU-die SCU */
+#define SCU0_HWSTRAP 0x010
+#define SCU0_HWSTRAP_DIS_RVAS BIT(30)
+#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25)
+#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22)
+#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21)
+#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20)
+#define SCU0_HWSTRAP_VGA_CC BIT(18)
+#define SCU0_HWSTRAP_EN_OPROM BIT(17)
+#define SCU0_HWSTRAP_DISARMICE BIT(16)
+#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9)
+#define SCU0_HWSTRAP_DISDEBUG BIT(8)
+#define SCU0_HWSTRAP_HCLKHPLL BIT(7)
+#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5)
+#define SCU0_HWSTRAP_CPUHPLL BIT(4)
+#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2)
+#define SCU0_HWSTRAP_BOOTSPI BIT(1)
+#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0)
+#define SCU0_DBGCTL 0x0c8
+#define SCU0_DBGCTL_MASK GENMASK(14, 0)
+#define SCU0_DBGCTL_UARTDBG BIT(1)
+#define SCU0_RSTCTL1 0x200
+#define SCU0_RSTCTL1_EMMC BIT(17)
+#define SCU0_RSTCTL1_HACE BIT(4)
+#define SCU0_RSTCTL1_CLR 0x204
+#define SCU0_RSTCTL1_CLR_EMMC BIT(17)
+#define SCU0_RSTCTL1_CLR_HACE BIT(4)
+#define SCU0_CLKGATE1 0x240
+#define SCU0_CLKGATE1_EMMC BIT(27)
+#define SCU0_CLKGATE1_HACE BIT(13)
+#define SCU0_CLKGATE1_DDRPHY BIT(11)
+#define SCU0_CLKGATE1_CLR 0x244
+#define SCU0_CLKGATE1_CLR_EMMC BIT(27)
+#define SCU0_CLKGATE1_CLR_HACE BIT(13)
+#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11)
+#define SCU0_VGA0_SCRATCH 0x900
+#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6)
+#define SCU0_PCI_MISC70 0xa70
+#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3)
+#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2)
+#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0)
+#define SCU0_PCI_MISC80 0xa80
+#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3)
+#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2)
+#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0)
+#define SCU0_PCI_MISCF0 0xaf0
+#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3)
+#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2)
+#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0)
+#define SCU0_WPROT1 0xe04
+#define SCU0_WPROT1_0C8 BIT(18)
+
+/* SCU1: IO-die SCU */
+#define SCU1_REVISION 0x000
+#define SCU1_REVISION_HWID GENMASK(23, 16)
+#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8)
+#define SCU1_HWSTRAP1 0x010
+#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30)
+#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28)
+#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26)
+#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27))
+#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27)
+#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26)
+#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25)
+#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24)
+#define SCU1_HWSTRAP1_BOOT_UFS BIT(23)
+#define SCU1_HWSTRAP1_DIS_ROM BIT(22)
+#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20)
+#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19)
+#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18)
+#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17)
+#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16)
+#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14)
+#define SCU1_HWSTRAP1_ACPI_1 BIT(13)
+#define SCU1_HWSTRAP1_ACPI_0 BIT(12)
+#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11)
+#define SCU1_HWSTRAP1_DDR4 BIT(10)
+#define SCU1_HWSTRAP1_LOW_SECURE BIT(8)
+#define SCU1_HWSTRAP1_EN_EMCS BIT(7)
+#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6)
+#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5)
+#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4)
+#define SCU1_HWSTRAP1_LTPI0_EN BIT(3)
+#define SCU1_HWSTRAP1_LTPI_IDX BIT(2)
+#define SCU1_HWSTRAP1_LTPI1_EN BIT(1)
+#define SCU1_HWSTRAP1_LTPI_MODE BIT(0)
+#define SCU1_HWSTRAP2 0x030
+#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29)
+#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28)
+#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27)
+#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25)
+#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23)
+#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19)
+#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17)
+#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16)
+#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13)
+#define SCU1_HWSTRAP2_DIS_REC BIT(12)
+#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11)
+#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2)
+#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1)
+#define SCU1_HWSTRAP2_ABR BIT(0)
+#define SCU1_RSTLOG0 0x050
+#define SCU1_RSTLOG0_BMC_CPU BIT(12)
+#define SCU1_RSTLOG0_ABR BIT(2)
+#define SCU1_RSTLOG0_EXTRSTN BIT(1)
+#define SCU1_RSTLOG0_SRST BIT(0)
+#define SCU1_MISC1 0x0c0
+#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22)
+#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20)
+#define SCU1_DBGCTL 0x0c8
+#define SCU1_DBGCTL_MASK GENMASK(7, 0)
+#define SCU1_DBGCTL_UARTDBG BIT(6)
+#define SCU1_RNG_DATA 0x0f4
+#define SCU1_RSTCTL1 0x200
+#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x))
+#define SCU1_RSTCTL1_CLR 0x204
+#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x))
+#define SCU1_RSTCTL2 0x220
+#define SCU1_RSTCTL2_LTPI1 BIT(22)
+#define SCU1_RSTCTL2_LTPI0 BIT(20)
+#define SCU1_RSTCTL2_I2C BIT(15)
+#define SCU1_RSTCTL2_CPTRA BIT(9)
+#define SCU1_RSTCTL2_CLR 0x224
+#define SCU1_RSTCTL2_CLR_I2C BIT(15)
+#define SCU1_RSTCTL2_CLR_CPTRA BIT(9)
+#define SCU1_CLKGATE1 0x240
+#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x))
+#define SCU1_CLKGATE1_I2C BIT(15)
+#define SCU1_CLKGATE1_CLR 0x244
+#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x))
+#define SCU1_CLKGATE1_CLR_I2C BIT(15)
+#define SCU1_CLKGATE2 0x260
+#define SCU1_CLKGATE2_LTPI1_TX BIT(19)
+#define SCU1_CLKGATE2_LTPI_AHB BIT(10)
+#define SCU1_CLKGATE2_LTPI0_TX BIT(9)
+#define SCU1_CLKGATE2_CLR 0x264
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/sdram.h b/arch/riscv/include/asm/arch-ast2700/sdram.h
new file mode 100644
index 0000000..daf48dd
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/sdram.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SDRAM_H__
+#define __ASM_AST2700_SDRAM_H__
+
+struct sdrammc_regs {
+ u32 prot_key;
+ u32 intr_status;
+ u32 intr_clear;
+ u32 intr_mask;
+ u32 mcfg;
+ u32 mctl;
+ u32 msts;
+ u32 error_status;
+ u32 actime1;
+ u32 actime2;
+ u32 actime3;
+ u32 actime4;
+ u32 actime5;
+ u32 actime6;
+ u32 actime7;
+ u32 dfi_timing;
+ u32 dcfg;
+ u32 dctl;
+ u32 mrctl;
+ u32 mrwr;
+ u32 mrrd;
+ u32 mr01;
+ u32 mr23;
+ u32 mr45;
+ u32 mr67;
+ u32 refctl;
+ u32 refmng_ctl;
+ u32 refsts;
+ u32 zqctl;
+ u32 ecc_addr_range;
+ u32 ecc_failure_status;
+ u32 ecc_failure_addr;
+ u32 ecc_test_control;
+ u32 ecc_test_status;
+ u32 arbctl;
+ u32 enccfg;
+ u32 protect_lock_set;
+ u32 protect_lock_status;
+ u32 protect_lock_reset;
+ u32 enc_min_addr;
+ u32 enc_max_addr;
+ u32 enc_key[4];
+ u32 enc_iv[3];
+ u32 bistcfg;
+ u32 bist_addr;
+ u32 bist_size;
+ u32 bist_patt;
+ u32 bist_res;
+ u32 bist_fail_addr;
+ u32 bist_fail_data[4];
+ u32 reserved2[2];
+ u32 debug_control;
+ u32 debug_status;
+ u32 phy_intf_status;
+ u32 testcfg;
+ u32 gfmcfg;
+ u32 gfm0ctl;
+ u32 gfm1ctl;
+ u32 reserved3[0xf8];
+};
+
+#define DRAMC_UNLK_KEY 0x1688a8a8
+
+/* offset 0x04 */
+#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16)
+#define DRAMC_IRQSTA_PHY_ERR BIT(15)
+#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12)
+#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11)
+#define DRAMC_IRQSTA_REF_DONE BIT(10)
+#define DRAMC_IRQSTA_ZQ_DONE BIT(9)
+#define DRAMC_IRQSTA_BIST_DONE BIT(8)
+#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5)
+#define DRAMC_IRQSTA_ECC_ERR BIT(4)
+#define DRAMC_IRQSTA_PROT_ERR BIT(3)
+#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2)
+#define DRAMC_IRQSTA_MR_DONE BIT(1)
+#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0)
+
+/* offset 0x14 */
+#define DRAMC_MCTL_WB_SOFT_RESET BIT(24)
+#define DRAMC_MCTL_PHY_CLK_DIS BIT(18)
+#define DRAMC_MCTL_PHY_RESET BIT(17)
+#define DRAMC_MCTL_PHY_POWER_ON BIT(16)
+#define DRAMC_MCTL_FREQ_CHG_START BIT(3)
+#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2)
+#define DRAMC_MCTL_SELF_REF_START BIT(1)
+#define DRAMC_MCTL_PHY_INIT_START BIT(0)
+
+/* offset 0x40 */
+#define DRAMC_DFICFG_WD_POL BIT(18)
+#define DRAMC_DFICFG_CKE_OUT BIT(17)
+#define DRAMC_DFICFG_RESET BIT(16)
+
+/* offset 0x48 */
+#define DRAMC_MRCTL_ERR_STATUS BIT(31)
+#define DRAMC_MRCTL_READY_STATUS BIT(30)
+#define DRAMC_MRCTL_MR_ADDR BIT(8)
+#define DRAMC_MRCTL_CMD_DLL_RST BIT(7)
+#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6)
+#define DRAMC_MRCTL_CMD_TYPE BIT(2)
+#define DRAMC_MRCTL_CMD_WR_CTL BIT(1)
+#define DRAMC_MRCTL_CMD_START BIT(0)
+
+/* offset 0xC0 */
+#define DRAMC_BISTRES_RUNNING BIT(10)
+#define DRAMC_BISTRES_FAIL BIT(9)
+#define DRAMC_BISTRES_DONE BIT(8)
+#define DRAMC_BISTCFG_INIT_MODE BIT(7)
+#define DRAMC_BISTCFG_PMODE GENMASK(6, 4)
+#define DRAMC_BISTCFG_BMODE GENMASK(3, 2)
+#define DRAMC_BISTCFG_ENABLE BIT(1)
+#define DRAMC_BISTCFG_START BIT(0)
+#define BIST_PMODE_CRC (3)
+#define BIST_BMODE_RW_SWITCH (3)
+
+/* DRAMC048 MR Control Register */
+#define MR_TYPE_SHIFT 2
+#define MR_RW (0 << MR_TYPE_SHIFT)
+#define MR_MPC BIT(2)
+#define MR_VREFCS (2 << MR_TYPE_SHIFT)
+#define MR_VREFCA (3 << MR_TYPE_SHIFT)
+#define MR_ADDRESS_SHIFT 8
+#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL)
+#define MR_NUM_SHIFT 4
+#define MR_NUM(n) ((n) << MR_NUM_SHIFT)
+#define MR_DLL_RESET BIT(7)
+#define MR_1T_MODE BIT(16)
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/sli.h b/arch/riscv/include/asm/arch-ast2700/sli.h
new file mode 100644
index 0000000..42f0f9a
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/sli.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SLI_H__
+#define __ASM_AST2700_SLI_H__
+
+#define SLI_CPU_ADRBASE 0x12c17000
+#define SLI_IOD_ADRBASE 0x14c1e000
+#define SLIM_CPU_BASE (SLI_CPU_ADRBASE + 0x000)
+#define SLIH_CPU_BASE (SLI_CPU_ADRBASE + 0x200)
+#define SLIV_CPU_BASE (SLI_CPU_ADRBASE + 0x400)
+#define SLIM_IOD_BASE (SLI_IOD_ADRBASE + 0x000)
+#define SLIH_IOD_BASE (SLI_IOD_ADRBASE + 0x200)
+#define SLIV_IOD_BASE (SLI_IOD_ADRBASE + 0x400)
+
+#define SLI_CTRL_I 0x00
+#define SLIV_RAW_MODE BIT(15)
+#define SLI_TX_MODE BIT(14)
+#define SLI_RX_PHY_LAH_SEL_REV BIT(13)
+#define SLI_RX_PHY_LAH_SEL_NEG BIT(12)
+#define SLI_AUTO_SEND_TRN_OFF BIT(8)
+#define SLI_CLEAR_BUS BIT(6)
+#define SLI_TRANS_EN BIT(5)
+#define SLI_CLEAR_RX BIT(2)
+#define SLI_CLEAR_TX BIT(1)
+#define SLI_RESET_TRIGGER BIT(0)
+#define SLI_CTRL_II 0x04
+#define SLI_CTRL_III 0x08
+#define SLI_CLK_SEL GENMASK(31, 28)
+#define SLI_CLK_500M 0x6
+#define SLI_CLK_200M 0x3
+#define SLI_PHYCLK_SEL GENMASK(27, 24)
+#define SLI_PHYCLK_25M 0x0
+#define SLI_PHYCLK_800M 0x1
+#define SLI_PHYCLK_400M 0x2
+#define SLI_PHYCLK_200M 0x3
+#define SLI_PHYCLK_788M 0x5
+#define SLI_PHYCLK_500M 0x6
+#define SLI_PHYCLK_250M 0x7
+#define SLIH_PAD_DLY_TX1 GENMASK(23, 18)
+#define SLIH_PAD_DLY_TX0 GENMASK(17, 12)
+#define SLIH_PAD_DLY_RX1 GENMASK(11, 6)
+#define SLIH_PAD_DLY_RX0 GENMASK(5, 0)
+#define SLIM_PAD_DLY_RX3 GENMASK(23, 18)
+#define SLIM_PAD_DLY_RX2 GENMASK(17, 12)
+#define SLIM_PAD_DLY_RX1 GENMASK(11, 6)
+#define SLIM_PAD_DLY_RX0 GENMASK(5, 0)
+#define SLI_CTRL_IV 0x0c
+#define SLIM_PAD_DLY_TX3 GENMASK(23, 18)
+#define SLIM_PAD_DLY_TX2 GENMASK(17, 12)
+#define SLIM_PAD_DLY_TX1 GENMASK(11, 6)
+#define SLIM_PAD_DLY_TX0 GENMASK(5, 0)
+#define SLI_INTR_EN 0x10
+#define SLI_INTR_STATUS 0x14
+#define SLI_INTR_RX_SYNC BIT(15)
+#define SLI_INTR_RX_ERR BIT(13)
+#define SLI_INTR_RX_NACK BIT(12)
+#define SLI_INTR_RX_TRAIN_PKT BIT(10)
+#define SLI_INTR_RX_DISCONN BIT(6)
+#define SLI_INTR_TX_SUSPEND BIT(4)
+#define SLI_INTR_TX_TRAIN BIT(3)
+#define SLI_INTR_TX_IDLE BIT(2)
+#define SLI_INTR_RX_SUSPEND BIT(1)
+#define SLI_INTR_RX_IDLE BIT(0)
+#define SLI_INTR_RX_ERRORS \
+ (SLI_INTR_RX_ERR | SLI_INTR_RX_NACK | SLI_INTR_RX_DISCONN)
+
+#define SLIM_MARB_FUNC_I 0x60
+#define SLIM_SLI_MARB_RR BIT(0)
+
+#define SLI_TARGET_PHYCLK SLI_PHYCLK_400M
+#define SLIH_DEFAULT_DELAY 11
+#if (SLI_TARGET_PHYCLK == SLI_PHYCLK_800M) || (SLI_TARGET_PHYCLK == SLI_PHYCLK_788M)
+#define SLIM_DEFAULT_DELAY 5
+#define SLIM_LAH_CONFIG 1
+#else
+#define SLIM_DEFAULT_DELAY 12
+#define SLIM_LAH_CONFIG 0
+#endif
+#endif
+int sli_init(void);
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 35f1368..2f2994c 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -138,6 +138,43 @@
return k;
}
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
+ unsigned long result = offset & ~(BITS_PER_LONG - 1);
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= (BITS_PER_LONG - 1);
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (BITS_PER_LONG - offset);
+ if (size < BITS_PER_LONG)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= BITS_PER_LONG;
+ result += BITS_PER_LONG;
+ }
+ while (size & ~(BITS_PER_LONG - 1)) {
+ tmp = *(p++);
+ if (~tmp)
+ goto found_middle;
+ result += BITS_PER_LONG;
+ size -= BITS_PER_LONG;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
@@ -158,6 +195,9 @@
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
#define test_and_set_bit __test_and_set_bit
#define test_and_clear_bit __test_and_clear_bit
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 13cbaab..8250297 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -133,16 +133,3 @@
{
return do_bootm_linux(flag, bmi);
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mv %0, sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index f9a1428..714cc92 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -34,9 +34,8 @@
efi_print_image_infos((void *)epc);
}
-static void show_regs(struct pt_regs *regs)
+static void __maybe_unused show_regs(struct pt_regs *regs)
{
-#ifdef CONFIG_SHOW_REGS
printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
regs->sp, regs->gp, regs->tp);
printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
@@ -57,7 +56,6 @@
regs->s10, regs->s11, regs->t3);
printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
regs->t4, regs->t5, regs->t6);
-#endif
}
static void __maybe_unused show_backtrace(struct pt_regs *regs)
@@ -157,7 +155,8 @@
printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
epc - gd->reloc_off, regs->ra - gd->reloc_off);
- show_regs(regs);
+ if (CONFIG_IS_ENABLED(SHOW_REGS))
+ show_regs(regs);
if (CONFIG_IS_ENABLED(FRAMEPOINTER))
show_backtrace(regs);
show_code(epc);
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 0ed85b3..51ce40e 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -109,8 +109,9 @@
state = state_get_current();
list_for_each_entry(mentry, &state->mapmem_head, sibling_node) {
if (mentry->tag == paddr) {
- debug("%s: Used map from %lx to %p\n", __func__,
- (ulong)paddr, mentry->ptr);
+ log_debug("Used map from %lx to %p\n", (ulong)paddr,
+ mentry->ptr);
+ mentry->refcnt++;
return mentry->ptr;
}
}
@@ -130,11 +131,12 @@
list_for_each_entry(mentry, &state->mapmem_head, sibling_node) {
if (mentry->ptr == ptr) {
- debug("%s: Used map from %p to %lx\n", __func__, ptr,
- mentry->tag);
+ log_debug("Used map from %p to %lx\n", ptr,
+ mentry->tag);
return mentry;
}
}
+
return NULL;
}
@@ -156,7 +158,7 @@
__func__, ptr, (ulong)gd->ram_size);
os_abort();
}
- debug("%s: Used map from %p to %lx\n", __func__, ptr, mentry->tag);
+ log_debug("Used map from %p to %lx\n", ptr, mentry->tag);
return mentry->tag;
}
@@ -174,6 +176,7 @@
__func__, (uint)paddr, len, plen);
}
map_len = len;
+ log_debug("pci map %lx -> %p\n", (ulong)paddr, ptr);
return ptr;
}
#endif
@@ -183,12 +186,30 @@
void unmap_physmem(const void *ptr, unsigned long flags)
{
+ struct sandbox_mapmem_entry *mentry;
+
#ifdef CONFIG_PCI
if (map_dev) {
pci_unmap_physmem(ptr, map_len, map_dev);
map_dev = NULL;
}
#endif
+
+ /* If it is in emulated RAM, we didn't create a tag, so nothing to do */
+ if (is_in_sandbox_mem(ptr))
+ return;
+
+ mentry = find_tag(ptr);
+ if (mentry) {
+ if (!--mentry->refcnt) {
+ list_del(&mentry->sibling_node);
+ log_debug("Removed map from %p to %lx\n", ptr,
+ (ulong)mentry->tag);
+ free(mentry);
+ }
+ } else {
+ log_warning("Address not mapped: %p\n", ptr);
+ }
}
phys_addr_t map_to_sysmem(const void *ptr)
@@ -217,11 +238,14 @@
}
mentry->tag = state->next_tag++;
mentry->ptr = (void *)ptr;
+ mentry->refcnt = 0;
list_add_tail(&mentry->sibling_node, &state->mapmem_head);
- debug("%s: Added map from %p to %lx\n", __func__, ptr,
- (ulong)mentry->tag);
+ log_debug("Added map from %p to %lx\n", ptr,
+ (ulong)mentry->tag);
}
+ mentry->refcnt++;
+
/*
* Return the tag as the address to use. A later call to map_sysmem()
* will return ptr
@@ -340,6 +364,8 @@
int err;
int fd;
+ if (gd->fdt_blob)
+ return (void *)gd->fdt_blob;
blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
*ret = 0;
if (!state->fdt_fname) {
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 46ff305..f5c9a8a 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -47,12 +47,24 @@
ssize_t os_read(int fd, void *buf, size_t count)
{
- return read(fd, buf, count);
+ ssize_t ret;
+
+ ret = read(fd, buf, count);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
ssize_t os_write(int fd, const void *buf, size_t count)
{
- return write(fd, buf, count);
+ ssize_t ret;
+
+ ret = write(fd, buf, count);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
int os_printf(const char *fmt, ...)
@@ -69,6 +81,8 @@
off_t os_lseek(int fd, off_t offset, int whence)
{
+ off_t ret;
+
if (whence == OS_SEEK_SET)
whence = SEEK_SET;
else if (whence == OS_SEEK_CUR)
@@ -77,7 +91,11 @@
whence = SEEK_END;
else
os_exit(1);
- return lseek(fd, offset, whence);
+ ret = lseek(fd, offset, whence);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
int os_open(const char *pathname, int os_flags)
@@ -808,7 +826,7 @@
* @count: Number of arguments in @add_args
* Return: 0 if OK, -ENOMEM if out of memory
*/
-static int add_args(char ***argvp, char *add_args[], int count)
+static int add_args(char ***argvp, const char *add_args[], int count)
{
char **argv, **ap;
int argc;
@@ -859,7 +877,7 @@
struct sandbox_state *state = state_get_current();
char mem_fname[30];
int fd, err;
- char *extra_args[5];
+ const char *extra_args[5];
char **argv = state->argv;
int argc;
#ifdef DEBUG
@@ -964,7 +982,7 @@
p = strstr(fname, subdir);
if (p) {
if (*next_prefix)
- /* e.g. ".../tpl/u-boot-spl" to "../spl/u-boot-spl" */
+ /* e.g. ".../tpl/u-boot-spl" to ".../spl/u-boot-spl" */
memcpy(p + 1, next_prefix, strlen(next_prefix));
else
/* e.g. ".../spl/u-boot" to ".../u-boot" */
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 9ad9da6..1c33a52 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -3,13 +3,18 @@
* Copyright (c) 2016 Google, Inc
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <dm.h>
#include <hang.h>
#include <handoff.h>
+#include <image.h>
#include <init.h>
#include <log.h>
+#include <mapmem.h>
#include <os.h>
#include <spl.h>
+#include <upl.h>
#include <asm/global_data.h>
#include <asm/spl.h>
#include <asm/state.h>
@@ -51,7 +56,8 @@
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_VBE;
- spl_boot_list[1] = BOOT_DEVICE_BOARD;
+ spl_boot_list[1] = BOOT_DEVICE_UPL;
+ spl_boot_list[2] = BOOT_DEVICE_BOARD;
}
static int spl_board_load_file(struct spl_image_info *spl_image,
@@ -121,6 +127,15 @@
}
SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image);
+int dram_init_banksize(void)
+{
+ /* These are necessary so TFTP can use LMBs to check its load address */
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+
+ return 0;
+}
+
void spl_board_init(void)
{
struct sandbox_state *state = state_get_current();
@@ -128,10 +143,6 @@
if (!CONFIG_IS_ENABLED(UNIT_TEST))
return;
- /* These are necessary so TFTP can use LMBs to check its load address */
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = get_effective_memsize();
-
if (state->run_unittests) {
struct unit_test *tests = UNIT_TEST_ALL_START();
const int count = UNIT_TEST_ALL_COUNT();
@@ -179,3 +190,114 @@
return 0;
}
+
+/* Context used to hold file descriptor */
+struct load_ctx {
+ int fd;
+};
+
+static ulong read_fit_image(struct spl_load_info *load, ulong offset,
+ ulong size, void *buf)
+{
+ struct load_ctx *load_ctx = load->priv;
+ off_t ret;
+ ssize_t res;
+
+ ret = os_lseek(load_ctx->fd, offset, OS_SEEK_SET);
+ if (ret < 0) {
+ printf("Failed to seek to %zx, got %zx\n", offset, ret);
+ return log_msg_ret("lse", ret);
+ }
+
+ res = os_read(load_ctx->fd, buf, size);
+ if (res < 0) {
+ printf("Failed to read %lx bytes, got %ld\n", size, res);
+ return log_msg_ret("osr", res);
+ }
+
+ return size;
+}
+
+int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image)
+{
+ struct legacy_img_hdr *header;
+ struct load_ctx load_ctx;
+ struct spl_load_info load;
+ int ret;
+ int fd;
+
+ spl_load_init(&load, read_fit_image, &load_ctx,
+ IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) ? 512 : 1);
+
+ ret = sandbox_find_next_phase(fname, maxlen, true);
+ if (ret) {
+ printf("%s not found, error %d\n", fname, ret);
+ return log_msg_ret("nph", ret);
+ }
+
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+
+ log_debug("reading from %s\n", fname);
+ fd = os_open(fname, OS_O_RDONLY);
+ if (fd < 0) {
+ printf("Failed to open '%s'\n", fname);
+ return log_msg_ret("ope", -errno);
+ }
+ ret = os_read(fd, header, sizeof(*header));
+ if (ret != sizeof(*header)) {
+ printf("Failed to read %lx bytes, got %d\n", sizeof(*header),
+ ret);
+ return log_msg_ret("rea", ret);
+ }
+ load_ctx.fd = fd;
+
+ load.priv = &load_ctx;
+
+ ret = spl_load_simple_fit(image, &load, 0, header);
+ if (ret)
+ return log_msg_ret("slf", ret);
+
+ return 0;
+}
+
+static int upl_load_from_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ long long size;
+ char *fname;
+ int ret, fd;
+ ulong addr;
+
+ if (!CONFIG_IS_ENABLED(UPL_OUT))
+ return -ENOTSUPP;
+
+ spl_upl_init();
+ fname = os_malloc(256);
+
+ ret = sandbox_spl_load_fit(fname, 256, spl_image);
+ if (ret)
+ return log_msg_ret("fit", ret);
+ spl_image->flags = SPL_SANDBOXF_ARG_IS_BUF;
+ spl_image->arg = map_sysmem(spl_image->load_addr, 0);
+ /* size is set by load_simple_fit(), offset is left as 0 */
+
+ /* now read the whole FIT into memory */
+ fd = os_open(fname, OS_O_RDONLY);
+ if (fd < 0)
+ return log_msg_ret("op2", -ENOENT);
+ if (os_get_filesize(fname, &size))
+ return log_msg_ret("fis", -ENOENT);
+
+ /* place it after the loaded image, allowing plenty of space */
+ addr = ALIGN(spl_image->load_addr + size, 0x1000);
+ log_debug("Loading whole FIT to %lx\n", addr);
+ if (os_read(fd, map_sysmem(addr, 0), size) != size)
+ return log_msg_ret("rea", -EIO);
+ os_close(fd);
+
+ /* tell UPL where it is */
+ upl_set_fit_addr(addr);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("upl", 4, BOOT_DEVICE_UPL, upl_load_from_image);
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index dce8041..9ad5d46 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -431,6 +431,14 @@
}
SANDBOX_CMDLINE_OPT(autoboot_keyed, 0, "Allow keyed autoboot");
+static int sandbox_cmdline_cb_upl(struct sandbox_state *state, const char *arg)
+{
+ state->upl = true;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT(upl, 0, "Enable Universal Payload (UPL)");
+
static void setup_ram_buf(struct sandbox_state *state)
{
/* Zero the RAM buffer if we didn't read it, to keep valgrind happy */
@@ -483,6 +491,9 @@
text_base = os_find_text_base();
+ memset(&data, '\0', sizeof(data));
+ gd = &data;
+
/*
* This must be the first invocation of os_malloc() to have
* state->ram_buf in the low 4 GiB.
@@ -501,8 +512,6 @@
os_exit(1);
memcpy(os_argv, argv, size);
- memset(&data, '\0', sizeof(data));
- gd = &data;
gd->arch.text_base = text_base;
state = state_get_current();
@@ -539,6 +548,9 @@
goto err;
}
+ if (state->upl)
+ gd->flags |= GD_FLG_UPL;
+
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
gd->malloc_base = CFG_MALLOC_F_ADDR;
#endif
@@ -557,7 +569,7 @@
log_debug("debug: %s\n", __func__);
/* Do pre- and post-relocation init */
- board_init_f(0);
+ board_init_f(gd->flags);
board_init_r(gd->new_gd, 0);
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index a9ca79e..49236db 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -373,12 +373,13 @@
memset(state->spi, '\0', sizeof(state->spi));
/*
- * Set up the memory tag list. Use the top of emulated SDRAM for the
- * first tag number, since that address offset is outside the legal
- * range, and can be assumed to be a tag.
+ * Set up the memory tag list. We could use the top of emulated SDRAM
+ * for the first tag number, since that address offset is outside the
+ * legal SDRAM range, but PCI can have address there. So use a very
+ * large address instead
*/
INIT_LIST_HEAD(&state->mapmem_head);
- state->next_tag = state->ram_size;
+ state->next_tag = 0xff000000;
}
bool autoboot_keyed(void)
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index c93ce71..8a115c5 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -231,23 +231,25 @@
};
pinctrl {
+ bootph-some-ram;
compatible = "sandbox,pinctrl";
status = "okay";
pinctrl_i2c0: i2c0 {
- groups = "i2c";
- function = "i2c";
+ groups = "I2C_UART";
+ function = "I2C";
bias-pull-up;
};
pinctrl_serial0: uart0 {
- groups = "serial_a";
- function = "serial";
+ bootph-some-ram;
+ groups = "I2C_UART";
+ function = "UART";
};
pinctrl_onewire0: onewire0 {
- groups = "w1";
- function = "w1";
+ pins = "P8";
+ function = "ONEWIRE";
bias-pull-up;
};
};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 5fb5eac..8412506 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -78,7 +78,7 @@
event_log: tcg_event_log {
no-map;
- reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
+ reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
};
};
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index 4fab24c..d824b21 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -6,6 +6,8 @@
#ifndef __asm_spl_h
#define __asm_spl_h
+struct spl_image_info;
+
enum {
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
@@ -16,6 +18,7 @@
BOOT_DEVICE_NOR,
BOOT_DEVICE_SPI,
BOOT_DEVICE_NAND,
+ BOOT_DEVICE_UPL,
};
/**
@@ -31,4 +34,16 @@
*/
int sandbox_find_next_phase(char *fname, int maxlen, bool use_img);
+/**
+ * sandbox_spl_load_fit() - Load the next phase from a FIT
+ *
+ * Loads a FIT containing the next phase and sets it up for booting
+ *
+ * @fname: Returns filename loaded
+ * @maxlen: Maximum length for @fname including \0
+ * @image: Place to put SPL-image information
+ * Return: 0 if OK, -ve on error
+ */
+int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image);
+
#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index c84a1f7..e7dc017 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -53,10 +53,13 @@
* be returned, just as it would for a normal sandbox address.
*
* @tag: Address tag (a value which U-Boot uses to refer to the address)
+ * @refcnt: Number of references to this tag
* @ptr: Associated pointer for that tag
+ * @sibling_node: Next node
*/
struct sandbox_mapmem_entry {
ulong tag;
+ uint refcnt;
void *ptr;
struct list_head sibling_node;
};
@@ -97,6 +100,7 @@
bool autoboot_keyed; /* Use keyed-autoboot feature */
bool disable_eth; /* Disable Ethernet devices */
bool disable_sf_bootdevs; /* Don't bind SPI flash bootdevs */
+ bool upl; /* Enable Universal Payload (UPL) */
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 17159f8..0e8d19c 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -49,6 +49,10 @@
#define PCI_EA_BAR2_MAGIC 0x72727272
#define PCI_EA_BAR4_MAGIC 0x74747474
+/* Used by the sandbox iommu driver */
+#define SANDBOX_IOMMU_DVA_ADDR 0x89abc000
+#define SANDBOX_IOMMU_PAGE_SIZE SZ_4K
+
enum {
SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
};
diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c
index 6040eac..5eff7c7 100644
--- a/arch/sandbox/lib/pci_io.c
+++ b/arch/sandbox/lib/pci_io.c
@@ -8,6 +8,8 @@
* IO space access commands.
*/
+#define LOG_CATEGORY UCLASS_PCI
+
#include <command.h>
#include <dm.h>
#include <log.h>
@@ -31,10 +33,11 @@
if (ret)
continue;
*devp = dev;
+ log_debug("addr=%lx, dev=%s\n", (ulong)paddr, dev->name);
return 0;
}
- debug("%s: failed: addr=%pap\n", __func__, &paddr);
+ log_debug("%s: failed: addr=%pap\n", __func__, &paddr);
return -ENOSYS;
}
@@ -66,7 +69,7 @@
}
}
- debug("%s: failed: addr=%x\n", __func__, addr);
+ log_debug("%s: failed: addr=%x\n", __func__, addr);
return -ENOSYS;
}
@@ -87,7 +90,7 @@
}
}
- debug("%s: failed: addr=%x, value=%lx\n", __func__, addr, value);
+ log_debug("%s: failed: addr=%x, value=%lx\n", __func__, addr, value);
return -ENOSYS;
}
diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c
index e298d76..bb0f59e 100644
--- a/arch/sh/lib/bootm.c
+++ b/arch/sh/lib/bootm.c
@@ -101,16 +101,3 @@
/* does not return */
return 1;
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov r15, %0" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index db2727d..934e98a 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -412,12 +412,6 @@
return 32;
}
-/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
-static void setup_pci_ram_top(void)
-{
- gd_set_pci_ram_top(0x80000000U);
-}
-
static void setup_mtrr(void)
{
u64 mtrr_cap;
@@ -469,7 +463,6 @@
setup_cpu_features();
setup_identity();
setup_mtrr();
- setup_pci_ram_top();
/* Set up the i8254 timer if required */
if (IS_ENABLED(CONFIG_I8254_TIMER))
@@ -483,7 +476,6 @@
long addr;
setup_identity();
- setup_pci_ram_top();
addr = locate_coreboot_table();
if (addr >= 0) {
gd->arch.coreboot_table = addr;
diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c
index 48b2ef2..5aad2ae 100644
--- a/arch/x86/cpu/intel_common/cpu_from_spl.c
+++ b/arch/x86/cpu/intel_common/cpu_from_spl.c
@@ -24,9 +24,7 @@
int ret;
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
- struct spl_handoff *ho = gd->spl_handoff;
-
- gd->arch.hob_list = ho->arch.hob_list;
+ gd->arch.hob_list = handoff_get();
#endif
ret = x86_cpu_reinit_f();
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index d71ab0a..05691a3 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -55,7 +55,6 @@
static int ivybridge_cpu_init(void)
{
- struct pci_controller *hose;
struct udevice *bus, *dev;
int ret;
@@ -65,10 +64,6 @@
if (ret)
return ret;
post_code(0x72);
- hose = dev_get_uclass_priv(bus);
-
- /* TODO(sjg@chromium.org): Get rid of gd->hose */
- gd->hose = hose;
ret = uclass_first_device_err(UCLASS_LPC, &dev);
if (ret)
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index aa1f47d..e2e1849 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -164,12 +164,12 @@
{
while (atomic_read(b) == 0)
asm("pause");
- mfence();
+ mb();
}
static inline void release_barrier(atomic_t *b)
{
- mfence();
+ mb();
atomic_set(b, 1);
}
@@ -631,7 +631,7 @@
if (cur_cpu != i)
store_callback(&ap_callbacks[i], callback);
}
- mfence();
+ mb();
/* Wait for all the APs to signal back that call has been accepted. */
start = get_timer(0);
@@ -656,7 +656,7 @@
} while (cpus_accepted != num_aps);
/* Make sure we can see any data written by the APs */
- mfence();
+ mb();
return 0;
}
@@ -692,7 +692,7 @@
/* Copy to local variable before using the value */
memcpy(&lcb, cb, sizeof(lcb));
- mfence();
+ mb();
if (lcb.logical_cpu_number == MP_SELECT_ALL ||
lcb.logical_cpu_number == MP_SELECT_APS ||
dev_seq(cpu) == lcb.logical_cpu_number)
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 073f80b..87e0c6f 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -185,11 +185,6 @@
}
#endif
-static inline void mfence(void)
-{
- __asm__ __volatile__("mfence" : : : "memory");
-}
-
/**
* cpu_enable_paging_pae() - Enable PAE-paging
*
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index c6d90eb..1390193 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -240,6 +240,7 @@
* have some advantages to use them instead of the simple one here.
*/
#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define mb() __asm__ __volatile__ ("mfence" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index dbcea7f..e1ed9bc 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -20,11 +20,12 @@
#if defined(__x86_64__)
typedef unsigned long __kernel_size_t;
typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
#else
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
-#endif
typedef int __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 2c889bc..55f5818 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -253,21 +253,3 @@
return boot_jump_linux(images);
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
-#if CONFIG_IS_ENABLED(X86_64)
- asm("mov %%rsp, %0" : "=r"(ret) : );
-#else
- asm("mov %%esp, %0" : "=r"(ret) : );
-#endif
-
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 5f77012..ad25020 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -103,7 +103,6 @@
* For IGD, it seems to be always on BAR2.
*/
vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
- gd->fb_base = vesa->phys_base_ptr;
ret = vesa_setup_video_priv(vesa, vesa->phys_base_ptr, uc_priv, plat);
if (ret)
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index 83c6d7b..a50dc98 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -59,7 +59,7 @@
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = gd->spl_handoff;
+ struct spl_handoff *ho = handoff_get();
if (!ho) {
log_debug("No SPL handoff found\n");
@@ -82,7 +82,7 @@
return gd->ram_size;
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = gd->spl_handoff;
+ struct spl_handoff *ho = handoff_get();
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 70eebb4..3876c3f 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -2,7 +2,6 @@
depends on XTENSA
config SYS_ARCH
- string
default "xtensa"
config SYS_CPU
diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c
index 1de06b7..2958f20 100644
--- a/arch/xtensa/lib/bootm.c
+++ b/arch/xtensa/lib/bootm.c
@@ -197,16 +197,3 @@
return 1;
}
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("mov %0, a1" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index 192a2fa..80e0ca8 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c
@@ -79,7 +79,7 @@
#define OSC (V_OSCK/1000000)
static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int rc;
diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c
index 2d3f593..bfb6adf 100644
--- a/board/BuR/brsmarc1/board.c
+++ b/board/BuR/brsmarc1/board.c
@@ -72,7 +72,7 @@
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c
index b9b595c..510d2af 100644
--- a/board/BuR/brxre1/board.c
+++ b/board/BuR/brxre1/board.c
@@ -79,7 +79,7 @@
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int rc;
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 2f29d26..eb88ee7 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -23,6 +23,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <fdt_support.h>
#include <hexdump.h>
+#include <i2c_eeprom.h>
#include <time.h>
#include <turris-omnia-mcu-interface.h>
#include <linux/bitops.h>
@@ -46,6 +47,9 @@
#define OMNIA_I2C_EEPROM_CHIP_LEN 2
#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
+#define OMNIA_RESET_TO_LOWER_DDR_SPEED 9
+#define OMNIA_LOWER_DDR_SPEED "1333H"
+
#define A385_SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260)
#define A385_SYS_RSTOUT_MASK_WD BIT(10)
@@ -205,6 +209,20 @@
return ~bitrev32(crc);
}
+static int omnia_mcu_get_reset(void)
+{
+ u8 reset_status;
+ int ret;
+
+ ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, reset status unknown!\n", ret);
+ return ret;
+ }
+
+ return reset_status;
+}
+
/* Can only be called after relocation, since it needs cleared BSS */
static int omnia_mcu_board_info(char *serial, u8 *mac, char *version)
{
@@ -462,20 +480,27 @@
return true;
}
+static struct udevice *omnia_get_eeprom(void)
+{
+ return omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
+ OMNIA_I2C_EEPROM_CHIP_LEN);
+}
+
static bool omnia_read_eeprom(struct omnia_eeprom *oep)
{
- struct udevice *chip;
+ struct udevice *eeprom = omnia_get_eeprom();
int ret;
- chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
- OMNIA_I2C_EEPROM_CHIP_LEN);
-
- if (!chip)
+ if (!eeprom)
return false;
- ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ ret = dm_i2c_read(eeprom, 0, (void *)oep, sizeof(*oep));
+ else
+ ret = i2c_eeprom_read(eeprom, 0, (void *)oep, sizeof(*oep));
+
if (ret) {
- printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
+ printf("cannot read EEPROM: %d\n", ret);
return false;
}
@@ -497,6 +522,35 @@
return true;
}
+static void omnia_eeprom_set_lower_ddr_speed(void)
+{
+ struct udevice *eeprom = omnia_get_eeprom();
+ struct omnia_eeprom oep;
+ int ret;
+
+ if (!eeprom || !omnia_read_eeprom(&oep))
+ return;
+
+ puts("Setting DDR speed to " OMNIA_LOWER_DDR_SPEED " in EEPROM as requested by reset button... ");
+
+ /* check if already set */
+ if (!strncmp(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed)) &&
+ (oep.old_ddr_training == 0 || oep.old_ddr_training == 0xff)) {
+ puts("was already set\n");
+ return;
+ }
+
+ strncpy(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed));
+ oep.old_ddr_training = 0xff;
+ oep.crc2 = crc32(0, (const void *)&oep, offsetof(struct omnia_eeprom, crc2));
+
+ ret = i2c_eeprom_write(eeprom, 0, (const void *)&oep, sizeof(oep));
+ if (ret)
+ printf("cannot write EEPROM: %d\n", ret);
+ else
+ puts("done\n");
+}
+
int omnia_get_ram_size_gb(void)
{
static int ram_size;
@@ -526,6 +580,13 @@
{
struct omnia_eeprom oep;
+ /*
+ * If lower DDR speed is requested by reset button, we can't use old DDR
+ * training algorithm.
+ */
+ if (omnia_mcu_get_reset() == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ return false;
+
if (!omnia_read_eeprom(&oep))
return false;
@@ -706,13 +767,19 @@
const struct omnia_ddr_speed *setting;
const char *speed;
static bool done;
+ int reset_status;
if (done)
return;
done = true;
+ reset_status = omnia_mcu_get_reset();
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ speed = OMNIA_LOWER_DDR_SPEED;
+ else
+ speed = omnia_get_ddr_speed();
+
- speed = omnia_get_ddr_speed();
if (!speed)
return;
@@ -729,7 +796,10 @@
if (params->speed_bin_index == setting->speed_bin)
return;
- printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ printf("Fixing up DDR3 speed to %s as requested by reset button\n", speed);
+ else
+ printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
params->speed_bin_index = setting->speed_bin;
params->memory_freq = setting->freq;
@@ -766,8 +836,7 @@
static void handle_reset_button(void)
{
const char * const vars[1] = { "bootcmd_rescue", };
- int ret;
- u8 reset_status;
+ int reset_status;
/*
* Ensure that bootcmd_rescue has always stock value, so that running
@@ -776,12 +845,12 @@
*/
env_set_default_vars(1, (char * const *)vars, 0);
- ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
- if (ret) {
- printf("omnia_mcu_read failed: %i, reset status unknown!\n",
- ret);
+ reset_status = omnia_mcu_get_reset();
+ if (reset_status < 0)
return;
- }
+
+ if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
+ return omnia_eeprom_set_lower_ddr_speed();
env_set_ulong("omnia_reset", reset_status);
diff --git a/board/Marvell/octeon_ebb7304/Kconfig b/board/Marvell/octeon_ebb7304/Kconfig
index b3244f7..c8dd026 100644
--- a/board/Marvell/octeon_ebb7304/Kconfig
+++ b/board/Marvell/octeon_ebb7304/Kconfig
@@ -1,11 +1,9 @@
if TARGET_OCTEON_EBB7304
config SYS_BOARD
- string
default "octeon_ebb7304"
config SYS_VENDOR
- string
default "Marvell"
config SYS_CONFIG_NAME
diff --git a/board/Marvell/octeon_nic23/Kconfig b/board/Marvell/octeon_nic23/Kconfig
index 468bbb7..ad8d508 100644
--- a/board/Marvell/octeon_nic23/Kconfig
+++ b/board/Marvell/octeon_nic23/Kconfig
@@ -1,11 +1,9 @@
if TARGET_OCTEON_NIC23
config SYS_BOARD
- string
default "octeon_nic23"
config SYS_VENDOR
- string
default "Marvell"
config SYS_CONFIG_NAME
diff --git a/board/Marvell/octeontx/Kconfig b/board/Marvell/octeontx/Kconfig
index 45d1159..bdedd24 100644
--- a/board/Marvell/octeontx/Kconfig
+++ b/board/Marvell/octeontx/Kconfig
@@ -1,11 +1,9 @@
if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX
config SYS_VENDOR
- string
default "Marvell"
config SYS_BOARD
- string
default "octeontx"
config SYS_CONFIG_NAME
diff --git a/board/Marvell/octeontx2/Kconfig b/board/Marvell/octeontx2/Kconfig
index 99291d7..8664b3e 100644
--- a/board/Marvell/octeontx2/Kconfig
+++ b/board/Marvell/octeontx2/Kconfig
@@ -1,11 +1,9 @@
if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX
config SYS_VENDOR
- string
default "Marvell"
config SYS_BOARD
- string
default "octeontx2"
config SYS_CONFIG_NAME
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
index 3d20cfb..3ffe15d 100644
--- a/board/Marvell/octeontx2_cn913x/board.c
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -23,11 +23,6 @@
int board_early_init_r(void)
{
- if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
- /* Check if any existing regulator should be turned down */
- regulators_enable_boot_off(false);
- }
-
return 0;
}
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index cc3a662..b9f4700 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -189,7 +189,7 @@
return 0;
}
-#ifdef CONFIG_SPL_MMC
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define UBOOT_RAW_SECTOR_OFFSET 0x40
unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sector)
@@ -203,4 +203,4 @@
return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
}
}
-#endif /* CONFIG_SPL_MMC */
+#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR */
diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c
index 8f3f204..f941207 100644
--- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c
+++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c
@@ -16,7 +16,5 @@
int board_init(void)
{
- regulators_enable_boot_on(_DEBUG);
-
return 0;
}
diff --git a/board/aspeed/ibex_ast2700/Kconfig b/board/aspeed/ibex_ast2700/Kconfig
new file mode 100644
index 0000000..469cea5
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_ASPEED_AST2700_IBEX
+
+config SYS_BOARD
+ default "ibex_ast2700"
+
+config SYS_VENDOR
+ default "aspeed"
+
+config SYS_CPU
+ default "ast2700"
+
+config SYS_CONFIG_NAME
+ default "ibex_ast2700"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select RISCV_AST2700
+ select SUPPORT_SPL
+ imply SPL_DRIVERS_MISC
+
+endif
diff --git a/board/aspeed/ibex_ast2700/MAINTAINERS b/board/aspeed/ibex_ast2700/MAINTAINERS
new file mode 100644
index 0000000..777f582
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/MAINTAINERS
@@ -0,0 +1,7 @@
+AST2700 using Ibex RISC-V Core as the boot MCU
+M: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
+S: Maintained
+F: arch/riscv/include/asm/arch-ast2700/
+F: board/aspeed/ibex_ast2700/
+F: configs/ibex-ast2700_defconfig
+F: include/configs/ibex_ast2700.h
diff --git a/board/aspeed/ibex_ast2700/Makefile b/board/aspeed/ibex_ast2700/Makefile
new file mode 100644
index 0000000..3d8eea9
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/Makefile
@@ -0,0 +1,3 @@
+obj-y += ibex_ast2700.o
+obj-y += fmc_hdr.o
+obj-y += sli.o
diff --git a/board/aspeed/ibex_ast2700/fmc_hdr.c b/board/aspeed/ibex_ast2700/fmc_hdr.c
new file mode 100644
index 0000000..2068a90
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/fmc_hdr.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+
+#include <asm/arch/fmc_hdr.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+#include <errno.h>
+#include <spl.h>
+#include <string.h>
+
+int fmc_hdr_get_prebuilt(uint32_t type, uint32_t *ofst, uint32_t *size)
+{
+ struct fmc_hdr_preamble *preamble;
+ struct fmc_hdr_body *body;
+ struct fmc_hdr *hdr;
+ uint32_t t, s, o;
+ int i;
+
+ if (type >= PBT_NUM)
+ return -EINVAL;
+
+ if (!ofst || !size)
+ return -EINVAL;
+
+ hdr = (struct fmc_hdr *)(_start - sizeof(*hdr));
+ preamble = &hdr->preamble;
+ body = &hdr->body;
+
+ if (preamble->magic != HDR_MAGIC)
+ return -EIO;
+
+ for (i = 0, o = sizeof(*hdr) + body->fmc_size; i < HDR_PB_MAX; ++i) {
+ t = body->pbs[i].type;
+ s = body->pbs[i].size;
+
+ /* skip if unrecognized, yet */
+ if (t >= PBT_NUM) {
+ o += s;
+ continue;
+ }
+
+ /* prebuilt end mark */
+ if (t == 0 && s == 0)
+ break;
+
+ /* return the prebuilt info if found */
+ if (t == type) {
+ *ofst = o;
+ *size = s;
+
+ goto found;
+ }
+
+ /* update offset for next prebuilt */
+ o += s;
+ }
+
+ return -ENODATA;
+
+found:
+ return 0;
+}
diff --git a/board/aspeed/ibex_ast2700/ibex_ast2700.c b/board/aspeed/ibex_ast2700/ibex_ast2700.c
new file mode 100644
index 0000000..e697f9b
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/ibex_ast2700.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <asm/io.h>
+#include <asm/arch/sli.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+ struct udevice *dev;
+ struct ram_info ram;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("cannot get DRAM driver\n");
+ return ret;
+ }
+
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ printf("cannot get DRAM information\n");
+ return ret;
+ }
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+int spl_board_init_f(void)
+{
+ sli_init();
+
+ dram_init();
+
+ return 0;
+}
+
+struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+ return (struct legacy_img_hdr *)CONFIG_SYS_LOAD_ADDR;
+}
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return (void *)spl_get_load_buffer(sectors, bl_len);
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_RAM;
+}
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int i = 0;
+ int ret;
+
+ /*
+ * Loop over all MISC uclass drivers to call the comphy code
+ * and init all CP110 devices enabled in the DT
+ */
+ while (1) {
+ /* Call the comphy code via the MISC uclass driver */
+ ret = uclass_get_device(UCLASS_MISC, i++, &dev);
+
+ /* We're done, once no further CP110 device is found */
+ if (ret)
+ break;
+ }
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
diff --git a/board/aspeed/ibex_ast2700/sli.c b/board/aspeed/ibex_ast2700/sli.c
new file mode 100644
index 0000000..7868111
--- /dev/null
+++ b/board/aspeed/ibex_ast2700/sli.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#include <asm/io.h>
+#include <asm/arch/sli.h>
+#include <asm/arch/scu.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+#define SLI_POLL_TIMEOUT_US 100
+
+static void sli_clear_interrupt_status(uint32_t base)
+{
+ writel(-1, (void *)base + SLI_INTR_STATUS);
+}
+
+static int sli_wait(uint32_t base, uint32_t mask)
+{
+ uint32_t value;
+
+ sli_clear_interrupt_status(base);
+
+ do {
+ value = readl((void *)base + SLI_INTR_STATUS);
+ if (value & SLI_INTR_RX_ERRORS)
+ return -1;
+ } while ((value & mask) != mask);
+
+ return 0;
+}
+
+static int sli_wait_suspend(uint32_t base)
+{
+ return sli_wait(base, SLI_INTR_TX_SUSPEND | SLI_INTR_RX_SUSPEND);
+}
+
+/*
+ * CPU die --- downstream pads ---> I/O die
+ * CPU die <--- upstream pads ----- I/O die
+ *
+ * US/DS PAD[3:0] : SLIM[3:0]
+ * US/DS PAD[5:4] : SLIH[1:0]
+ * US/DS PAD[7:6] : SLIV[1:0]
+ */
+int sli_init(void)
+{
+ uint32_t value;
+
+ /* The following training sequence is designed for AST2700A0 */
+ value = FIELD_GET(SCU1_REVISION_HWID, readl(SCU1_REVISION));
+ if (value)
+ return 0;
+
+ /* Return if SLI had been calibrated */
+ value = readl((void *)SLIH_IOD_BASE + SLI_CTRL_III);
+ value = FIELD_GET(SLI_CLK_SEL, value);
+ if (value) {
+ debug("SLI has been initialized\n");
+ return 0;
+ }
+
+ /* 25MHz PAD delay for AST2700A0 */
+ value = SLI_RX_PHY_LAH_SEL_NEG | SLI_TRANS_EN | SLI_CLEAR_BUS;
+ writel(value, (void *)SLIH_IOD_BASE + SLI_CTRL_I);
+ writel(value, (void *)SLIM_IOD_BASE + SLI_CTRL_I);
+ writel(value | SLIV_RAW_MODE, (void *)SLIV_IOD_BASE + SLI_CTRL_I);
+ sli_wait_suspend(SLIH_IOD_BASE);
+ sli_wait_suspend(SLIH_CPU_BASE);
+
+ return 0;
+}
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 3bd94d0..af486e9 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -125,7 +125,7 @@
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index afc0c05..6f9abcb 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -167,7 +167,7 @@
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index e5688c6..f52b9a9 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -181,7 +181,7 @@
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
index 36995a9..cb3cd7a 100644
--- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
+++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c
@@ -146,7 +146,7 @@
(8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index c775d59..15cbd0d 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -208,7 +208,7 @@
ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c
index 986da01..6f0d578 100644
--- a/board/atmel/sama5d2_icp/sama5d2_icp.c
+++ b/board/atmel/sama5d2_icp/sama5d2_icp.c
@@ -180,7 +180,7 @@
(7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index c8a8eb4..d104736 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -146,7 +146,7 @@
7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 54cc3c4..f98322f 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -175,7 +175,7 @@
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index f2e1242..28079a8 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -241,7 +241,7 @@
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 09ca16c..f9112fc 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -184,7 +184,7 @@
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 1f8b85f..0bdc6ad 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -169,7 +169,7 @@
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 41d7567..33ba7a7 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -75,7 +75,7 @@
const struct dpll_params dpll_ddr = {
400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int mpu_vdd;
int usb_cur_lim;
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index ab68874..1f9dc2d 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -34,6 +34,7 @@
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <i2c_eeprom.h>
#include <miiphy.h>
#include <cpsw.h>
#include <linux/delay.h>
@@ -51,21 +52,21 @@
/*
* Read header information from EEPROM into global structure.
*/
-#define EEPROM_ADDR 0x50
static int read_eeprom(void)
{
+ struct udevice *dev;
+ int ret;
+
/* Check if baseboard eeprom is available */
- if (i2c_probe(EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -ENODEV;
+ ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+ if (ret) {
+ puts("Could not find EEPROM.\n");
+ return ret;
}
- /* read the eeprom using i2c */
- if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
- puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
+ ret = i2c_eeprom_read(dev, 0, (uint8_t *)&header, sizeof(header));
+ if (ret)
+ return ret;
if (header.magic != HDR_MAGIC) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
@@ -310,7 +311,7 @@
const struct dpll_params dpll_mpu_shc_opp100 = {
99, MPUPLL_N, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int sil_rev;
int mpu_vdd;
@@ -445,7 +446,6 @@
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("EEPROM Content Invalid.\n");
diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig
index a64961e..9d3a7aa 100644
--- a/board/cadence/xtfpga/Kconfig
+++ b/board/cadence/xtfpga/Kconfig
@@ -17,11 +17,9 @@
endchoice
config SYS_BOARD
- string
default "xtfpga"
config SYS_VENDOR
- string
default "cadence"
config SYS_CONFIG_NAME
diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig
index 3d4b260..1add150 100644
--- a/board/cavium/thunderx/Kconfig
+++ b/board/cavium/thunderx/Kconfig
@@ -1,15 +1,12 @@
if TARGET_THUNDERX_88XX
config SYS_CPU
- string
default "armv8"
config SYS_BOARD
- string
default "thunderx"
config SYS_VENDOR
- string
default "cavium"
config SYS_CONFIG_NAME
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 616842e..7d81036 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -11,7 +11,7 @@
#include <irq_func.h>
#include <stdio.h>
#include <time.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <vsprintf.h>
#include <linux/delay.h>
#include <linux/string.h>
@@ -135,22 +135,22 @@
{
ulong result;
int iflag, cflag, prot, sect;
- int rc = ERR_OK;
+ int rc = FL_ERR_OK;
int chip1;
ulong start;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
+ return FL_ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last)) {
- return ERR_INVAL;
+ return FL_ERR_INVAL;
}
if ((info->flash_id & FLASH_VENDMASK) !=
(AMD_MANUFACT & FLASH_VENDMASK)) {
- return ERR_UNKNOWN_FLASH_VENDOR;
+ return FL_ERR_UNKNOWN_FLASH_VENDOR;
}
prot = 0;
@@ -160,7 +160,7 @@
}
}
if (prot)
- return ERR_PROTECTED;
+ return FL_ERR_PROTECTED;
/*
* Disable interrupts which might cause a timeout
@@ -217,11 +217,11 @@
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
if (chip1 == ERR) {
- rc = ERR_PROG_ERROR;
+ rc = FL_ERR_PROG_ERROR;
goto outahere;
}
if (chip1 == TMO) {
- rc = ERR_TIMEOUT;
+ rc = FL_ERR_TIMEOUT;
goto outahere;
}
@@ -252,7 +252,7 @@
{
volatile u16 *addr = (volatile u16 *) dest;
ulong result;
- int rc = ERR_OK;
+ int rc = FL_ERR_OK;
int cflag, iflag;
int chip1;
ulong start;
@@ -262,7 +262,7 @@
*/
result = *addr;
if ((result & data) != data)
- return ERR_NOT_ERASED;
+ return FL_ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
@@ -302,7 +302,7 @@
*addr = CMD_READ_ARRAY;
if (chip1 == ERR || *addr != data)
- rc = ERR_PROG_ERROR;
+ rc = FL_ERR_PROG_ERROR;
if (iflag)
enable_interrupts();
@@ -320,13 +320,13 @@
if (addr & 1) {
printf ("unaligned destination not supported\n");
- return ERR_ALIGN;
+ return FL_ERR_ALIGN;
}
#if 0
if (cnt & 1) {
printf ("odd transfer sizes not supported\n");
- return ERR_ALIGN;
+ return FL_ERR_ALIGN;
}
#endif
@@ -364,5 +364,5 @@
cnt -= 1;
}
- return ERR_OK;
+ return FL_ERR_OK;
}
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index c6d33c3..40047cf 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -14,6 +14,7 @@
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
+#include <i2c.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <net.h>
@@ -256,7 +257,7 @@
{
int ret;
- ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
+ ret = setup_i2c(busnum, I2C_SPEED_STANDARD_RATE, 0x7f, pads);
if (ret)
printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
index 1815819..983991e 100644
--- a/board/compulab/cm_t43/cm_t43.c
+++ b/board/compulab/cm_t43/cm_t43.c
@@ -48,8 +48,6 @@
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- i2c_probe(TPS65218_CHIP_PM);
return 0;
}
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 7c8226e..c7b2237 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -4,6 +4,12 @@
#
# Author: Igor Grinberg <grinberg@compulab.co.il>
+CL_EEPROM=y
+
+ifdef CONFIG_TARGET_TRIMSLICE
+CL_EEPROM=
+endif
+
obj-y += common.o
-obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o
+obj-$(CL_EEPROM) += eeprom.o
obj-$(CONFIG_SMC911X) += omap3_smc911x.o
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index efdaf34..1b12d09 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -34,19 +34,15 @@
static int cl_eeprom_read(uint offset, uchar *buf, int len)
{
+ struct udevice *eeprom;
int res;
- unsigned int current_i2c_bus = i2c_get_bus_num();
- res = i2c_set_bus_num(cl_eeprom_bus);
- if (res < 0)
+ res = i2c_get_chip_for_busnum(cl_eeprom_bus, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &eeprom);
+ if (res)
return res;
- res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
-
- i2c_set_bus_num(current_i2c_bus);
-
- return res;
+ return dm_i2c_read(eeprom, offset, (uint8_t *)buf, len);
}
static int cl_eeprom_setup(uint eeprom_bus)
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
index 9bd7604..0a44926 100644
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -10,7 +10,7 @@
#define _EEPROM_
#include <errno.h>
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
+#if !CONFIG_IS_ENABLED(TARGET_TRIMSLICE)
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
u32 cl_eeprom_get_board_rev(uint eeprom_bus);
int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
diff --git a/board/comvetia/lxr2/Kconfig b/board/comvetia/lxr2/Kconfig
new file mode 100644
index 0000000..93c7f49
--- /dev/null
+++ b/board/comvetia/lxr2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LXR2
+
+config SYS_BOARD
+ default "lxr2"
+
+config SYS_VENDOR
+ default "comvetia"
+
+config SYS_CONFIG_NAME
+ default "lxr2"
+
+endif
diff --git a/board/comvetia/lxr2/MAINTAINERS b/board/comvetia/lxr2/MAINTAINERS
new file mode 100644
index 0000000..25db90b
--- /dev/null
+++ b/board/comvetia/lxr2/MAINTAINERS
@@ -0,0 +1,6 @@
+COMVETIA LXR2
+M: Fabio Estevam <festevam@denx.de>
+S: Maintained
+F: board/comvetia/lxr2/
+F: include/configs/lxr2.h
+F: configs/lxr2_defconfig
diff --git a/board/comvetia/lxr2/Makefile b/board/comvetia/lxr2/Makefile
new file mode 100644
index 0000000..86b9284
--- /dev/null
+++ b/board/comvetia/lxr2/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := lxr2.o
diff --git a/board/comvetia/lxr2/lxr2.c b/board/comvetia/lxr2/lxr2.c
new file mode 100644
index 0000000..1732635
--- /dev/null
+++ b/board/comvetia/lxr2/lxr2.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
+// Copyright (C) 2024 Fabio Estevam <festevam@denx.de>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+
+#include <asm/mach-imx/spi.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
+#include <linux/delay.h>
+
+#include <image.h>
+#include <init.h>
+#include <serial.h>
+#include <spl.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <fsl_esdhc_imx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+static const iomux_v3_cfg_t uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ return IMX_GPIO_NR(4, 24);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_gpmi_nand();
+
+ return 0;
+}
+
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ * BOOT_CFG1[7] = 1 (boot from NAND)
+ * BOOT_CFG1[5] = 0 - raw NAND
+ * BOOT_CFG1[4] = 0 - default pad settings
+ * BOOT_CFG1[3:2] = 00 - devices = 1
+ * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ * BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+ /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+ {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
+ {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {NULL, 0},
+};
+
+int board_late_init(void)
+{
+ add_board_boot_modes(board_boot_modes);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
+static void phyflex_err006282_workaround(void)
+{
+ /*
+ * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
+ * to the CMIC. If this pin isn't toggled within 10s the boards
+ * reset. The pin is unconnected on older boards, so we do not
+ * need a check for older boards before applying this fixup.
+ */
+
+ gpio_request(MX6_PHYFLEX_ERR006282, "errata_gpio");
+ gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
+ mdelay(2);
+ gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
+ mdelay(2);
+ gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
+
+ imx_iomux_v3_setup_pad(MX6_PAD_SD4_DAT3__GPIO2_IO11);
+
+ gpio_direction_input(MX6_PHYFLEX_ERR006282);
+}
+
+static const iomux_v3_cfg_t gpios_pads[] = {
+ MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpios(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
+}
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdclk_1 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_reset = 0x00000030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000030,
+ .dram_sdodt0 = 0x00000030,
+ .dram_sdodt1 = 0x00000030,
+
+ .dram_sdqs0 = 0x00000028,
+ .dram_sdqs1 = 0x00000028,
+ .dram_sdqs2 = 0x00000028,
+ .dram_sdqs3 = 0x00000028,
+ .dram_sdqs4 = 0x00000028,
+ .dram_sdqs5 = 0x00000028,
+ .dram_sdqs6 = 0x00000028,
+ .dram_sdqs7 = 0x00000028,
+ .dram_dqm0 = 0x00000028,
+ .dram_dqm1 = 0x00000028,
+ .dram_dqm2 = 0x00000028,
+ .dram_dqm3 = 0x00000028,
+ .dram_dqm4 = 0x00000028,
+ .dram_dqm5 = 0x00000028,
+ .dram_dqm6 = 0x00000028,
+ .dram_dqm7 = 0x00000028,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_ddr_type = 0x000C0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x30,
+ .grp_ctlds = 0x30,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000028,
+ .grp_b1ds = 0x00000028,
+ .grp_b2ds = 0x00000028,
+ .grp_b3ds = 0x00000028,
+ .grp_b4ds = 0x00000028,
+ .grp_b5ds = 0x00000028,
+ .grp_b6ds = 0x00000028,
+ .grp_b7ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00170018,
+ .p0_mpwldectrl1 = 0x003B0039,
+ .p1_mpwldectrl0 = 0x00350048,
+ .p1_mpwldectrl1 = 0x00410052,
+ .p0_mpdgctrl0 = 0x03600374,
+ .p0_mpdgctrl1 = 0x03680360,
+ .p1_mpdgctrl0 = 0x0370037C,
+ .p1_mpdgctrl1 = 0x03700350,
+ .p0_mprddlctl = 0x3A363234,
+ .p1_mprddlctl = 0x3634363C,
+ .p0_mpwrdlctl = 0x38383E3C,
+ .p1_mpwrdlctl = 0x422A483C,
+};
+
+/* MT41K64M16JT-125 (1Gb density) */
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 1600,
+ .density = 1,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+ .SRT = 1,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ .dsize = 2,
+ .cs_density = 6,
+ .ncs = 2,
+ .cs1_mirror = 1,
+ .rtt_wr = 1,
+ .rtt_nom = 1,
+ .walat = 1,
+ .ralat = 5,
+ .mif3_mode = 3,
+ .bi_on = 1,
+ .sde_to_rst = 0x10,
+ .rst_to_cke = 0x23,
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 1,
+ .refr = 7,
+ };
+
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+static const iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ switch (spl_boot_list[0]) {
+ case BOOT_DEVICE_SPI:
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ break;
+ case BOOT_DEVICE_MMC1:
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+ spl_boot_list[2] = BOOT_DEVICE_UART;
+ break;
+ default:
+ printf("Boot device %x\n", spl_boot_list[0]);
+ }
+}
+
+static const iomux_v3_cfg_t ecspi3_pads[] = {
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+
+ enable_spi_clk(true, 2);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup clock gating */
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* setup AXI */
+ gpr_init();
+
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ setup_spi();
+
+ setup_gpios();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ phyflex_err006282_workaround();
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/comvetia/lxr2/lxr2.env b/board/comvetia/lxr2/lxr2.env
new file mode 100644
index 0000000..ec21380
--- /dev/null
+++ b/board/comvetia/lxr2/lxr2.env
@@ -0,0 +1,34 @@
+addcons=setenv bootargs ${bootargs} console=${console},${baudrate}
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off
+addmisc=setenv bootargs ${bootargs} ${miscargs}
+addmtd=run mtdnand;run mtdspi;setenv bootargs ${bootargs} ${mtdparts}
+altbootcmd=run swupdate
+bootcmd=run nandboot;run swupdate
+bootcount=2
+bootlimit=3
+console=ttymxc3
+cpu=armv7
+ethprime=FEC
+fdt_addr_r=0x18000000
+fitfile=fitImage
+flash-all-from-sd-card=env default -f -a;load mmc 0:1 10000000 u-boot.scr;source 10000000;saveenv
+initrd_high=0xffffffff
+kernel_addr_r=0x12000000
+loadaddr=0x12000000
+miscargs=panic=1
+mmcargs=setenv bootargs root=${mmcroot} rw rootwait
+mmcboot=if run mmcload;then run mmcargs addcons addmisc;bootm;fi
+mmcload=mmc rescan;load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage
+mmcpart=1
+mmcroot=/dev/mmcblk0p1
+mtdnand=setenv mtdparts mtdparts=gpmi-nand:40m(Kernels),860m(root),-(nand)
+mtdspi=setenv mtdparts ${mtdparts}';spi2.0:1024k(bootloader),64k(env1),64k(env2),-(rescue)'
+nanboot_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};run nandargs addip addcons addmtd addmisc;bootm
+nandargs=setenv bootargs ubi.mtd=1 root=ubi0:rootfs${ubiroot} rootfstype=ubifs
+nandboot=run mtdnand;ubi part Kernels;ubi readvol ${kernel_addr_r} kernel${ubiroot};run nandargs addip addcons addmtd addmisc;bootm ${kernel_addr_r}
+net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};tftp ${fdt_addr_r} ${board_name}/${fdt_file};run nfsargs addip addcons addmtd addmisc;bootm ${kernel_addr_r} - ${fdt_addr_r}
+net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};run nfsargs addip addcons addmtd addmisc;bootm ${kernel_addr_r}
+netmask=255.255.255.0
+nfsargs=setenv bootargs root=/dev/nfs nfsroot=${serverip}:${nfsroot},v3 panic=1
+swupdate=setenv bootargs root=/dev/ram;run addip addcons addmtd addmisc;sf probe;sf read ${kernel_addr_r} 120000 600000;sf read 14000000 730000 800000;bootm ${kernel_addr_r} 14000000
+ubiroot=1
diff --git a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c
index 64282ae..3775013 100644
--- a/board/conclusive/kstr-sama5d27/kstr-sama5d27.c
+++ b/board/conclusive/kstr-sama5d27/kstr-sama5d27.c
@@ -182,7 +182,7 @@
(8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c
index c193589..f81b727 100644
--- a/board/data_modul/imx8mp_edm_sbc/spl.c
+++ b/board/data_modul/imx8mp_edm_sbc/spl.c
@@ -100,7 +100,10 @@
if (boot_dev_spl == MMC3_BOOT) /* eMMC */
return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1; /* SD */
+ if (boot_dev_spl == SD2_BOOT) /* SD */
+ return BOOT_DEVICE_MMC1;
+
+ return BOOT_DEVICE_BOOTROM; /* USB SDPS */
}
void board_boot_order(u32 *spl_boot_list)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index c8dd30d..f2b14bf 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -30,6 +30,7 @@
#include <fuse.h>
#include <i2c_eeprom.h>
#include <mmc.h>
+#include <power/regulator.h>
#include <usb.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index c635735..78aae41 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -14,6 +14,7 @@
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
+#include <power/regulator.h>
#include "lpddr4_timing.h"
#include "../common/dh_common.h"
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 4f4f537..24c5f37 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -622,8 +622,6 @@
static void board_init_regulator(void)
{
board_init_regulator_av96();
-
- regulators_enable_boot_on(_DEBUG);
}
#else
static inline int board_get_regulator_buck3_nvm_uv_av96(int *uv)
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 2ad256f..00f9a5e 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -56,10 +56,10 @@
* boot device save register
* -------------------------
* The boot device can be quired by 'spl_boot_device()' in
- * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
+ * 'spl_board_init'. However it can't be saved in the u-boot
* environment here. In turn 'spl_boot_device' can't be called in
* 'board_late_init' which allows writing to u-boot environment.
- * To get the boot device from 'am33xx_spl_board_init' to
+ * To get the boot device from 'spl_board_init' to
* 'board_late_init' we therefore use a scratch register from the RTC.
*/
#define CFG_SYS_RTC_SCRATCH0 0x60
@@ -192,7 +192,7 @@
const struct dpll_params dpll_ddr_bone_black = {
400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig
deleted file mode 100644
index 5a6c1c5..0000000
--- a/board/egnite/ethernut5/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ETHERNUT5
-
-config SYS_BOARD
- default "ethernut5"
-
-config SYS_VENDOR
- default "egnite"
-
-config SYS_CONFIG_NAME
- default "ethernut5"
-
-endif
diff --git a/board/egnite/ethernut5/MAINTAINERS b/board/egnite/ethernut5/MAINTAINERS
deleted file mode 100644
index a4ad913..0000000
--- a/board/egnite/ethernut5/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ETHERNUT5 BOARD
-M: egnite GmbH <info@egnite.de>
-S: Maintained
-F: board/egnite/ethernut5/
-F: include/configs/ethernut5.h
-F: configs/ethernut5_defconfig
diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile
deleted file mode 100644
index 580f440..0000000
--- a/board/egnite/ethernut5/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2010
-# egnite GmbH
-
-obj-y += ethernut5.o
-obj-y += ethernut5_pwrman.o
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
deleted file mode 100644
index 64e341c3..0000000
--- a/board/egnite/ethernut5/ethernut5.c
+++ /dev/null
@@ -1,198 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * egnite GmbH <info@egnite.de>
- *
- * (C) Copyright 2010
- * Ole Reinhardt <ole.reinhardt@thermotemp.de>
- */
-
-/*
- * Ethernut 5 general board support
- *
- * Ethernut is an open source hardware and software project for
- * embedded Ethernet devices. Hardware layouts and CAD files are
- * freely available under BSD-like license.
- *
- * Ethernut 5 is the first member of the Ethernut board family
- * with U-Boot and Linux support. This implementation is based
- * on the original work done by Ole Reinhardt, but heavily modified
- * to support additional features and the latest board revision 5.0F.
- *
- * Main board components are by default:
- *
- * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
- * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
- * 512 MBytes Micron MT29F4G08ABADA NAND Flash
- * 4 MBytes Atmel AT45DB321D DataFlash
- * SMSC LAN8710 Ethernet PHY
- * Atmel ATmega168 MCU used for power management
- * Linear Technology LTC4411 PoE controller
- *
- * U-Boot relevant board interfaces are:
- *
- * 100 Mbit Ethernet with IEEE 802.3af PoE
- * RS-232 serial port
- * USB host and device
- * MMC/SD-Card slot
- * Expansion port with I2C, SPI and more...
- *
- * Typically the U-Boot image is loaded from serial DataFlash into
- * SDRAM by the samboot boot loader, which is located in internal
- * NOR Flash and provides all essential initializations like CPU
- * and peripheral clocks and, of course, the SDRAM configuration.
- *
- * For testing purposes it is also possibly to directly transfer
- * the image into SDRAM via JTAG. A tested configuration exists
- * for the Turtelizer 2 hardware dongle and the OpenOCD software.
- * In this case the latter will do the basic hardware configuration
- * via its reset-init script.
- *
- * For additional information visit the project home page at
- * http://www.ethernut.de/
- */
-
-#include <config.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <atmel_mci.h>
-#include <asm/global_data.h>
-
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#include "ethernut5_pwrman.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This is called last during early initialization. Most of the basic
- * hardware interfaces are up and running.
- *
- * The SDRAM hardware has been configured by the first stage boot loader.
- * We only need to announce its size, using u-boot's memory check.
- */
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(
- (void *)CFG_SYS_SDRAM_BASE,
- CFG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-#ifdef CONFIG_CMD_NAND
-static void ethernut5_nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Assign CS3 to NAND/SmartMedia Interface */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
-
-#ifdef CFG_SYS_NAND_READY_PIN
- /* Ready pin is optional. */
- at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1);
-#endif
- gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1);
-}
-#endif
-
-/*
- * This is called first during late initialization.
- */
-int board_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
-
- /* Set adress of boot parameters. */
- gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
- /* Initialize UARTs and power management. */
- ethernut5_power_init();
-#ifdef CONFIG_CMD_NAND
- ethernut5_nand_hw_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MACB
-/*
- * This is optionally called last during late initialization.
- */
-int board_eth_init(struct bd_info *bis)
-{
- const char *devname;
- unsigned short mode;
-
- at91_periph_clk_enable(ATMEL_ID_EMAC0);
-
- /* Need to reset PHY via power management. */
- ethernut5_phy_reset();
- /* Set peripheral pins. */
- at91_macb_hw_init();
- /* Basic EMAC initialization. */
- if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CFG_PHY_ID))
- return -1;
- /*
- * Early board revisions have a pull-down at the PHY's MODE0
- * strap pin, which forces the PHY into power down. Here we
- * switch to all-capable mode.
- */
- devname = miiphy_get_current_dev();
- if (miiphy_read(devname, 0, 18, &mode) == 0) {
- /* Set mode[2:0] to 0b111. */
- mode |= 0x00E0;
- miiphy_write(devname, 0, 18, mode);
- /* Soft reset overrides strap pins. */
- miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
- }
- /* Sync environment with network devices, needed for nfsroot. */
- return eth_init();
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(struct bd_info *bd)
-{
- at91_periph_clk_enable(ATMEL_ID_MCI);
-
- /* Initialize MCI hardware. */
- at91_mci_hw_init();
- /* Register the device. */
- return atmel_mci_init((void *)ATMEL_BASE_MCI);
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN);
-}
-#endif
diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c
deleted file mode 100644
index 42e1914..0000000
--- a/board/egnite/ethernut5/ethernut5_pwrman.c
+++ /dev/null
@@ -1,323 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011
- * egnite GmbH <info@egnite.de>
- */
-
-/*
- * Ethernut 5 power management support
- *
- * This board may be supplied via USB, IEEE 802.3af PoE or an
- * auxiliary DC input. An on-board ATmega168 microcontroller,
- * the so called power management controller or PMC, is used
- * to select the supply source and to switch on and off certain
- * energy consuming board components. This allows to reduce the
- * total stand-by consumption to less than 70mW.
- *
- * The main CPU communicates with the PMC via I2C. When
- * CONFIG_CMD_BSP is defined in the board configuration file,
- * then the board specific command 'pwrman' becomes available,
- * which allows to manually deal with the PMC.
- *
- * Two distinct registers are provided by the PMC for enabling
- * and disabling specific features. This avoids the often seen
- * read-modify-write cycle or shadow register requirement.
- * Additional registers are available to query the board
- * status and temperature, the auxiliary voltage and to control
- * the green user LED that is integrated in the reset switch.
- *
- * Note, that the AVR firmware of the PMC is released under BSDL.
- *
- * For additional information visit the project home page at
- * http://www.ethernut.de/
- */
-#include <command.h>
-#include <vsprintf.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#include "ethernut5_pwrman.h"
-
-/* PMC firmware version */
-static int pwrman_major;
-static int pwrman_minor;
-
-/*
- * Enable Ethernut 5 power management.
- *
- * This function must be called during board initialization.
- * While we are using u-boot's I2C subsystem, it may be required
- * to enable the serial port before calling this function,
- * in particular when debugging is enabled.
- *
- * If board specific commands are not available, we will activate
- * all board components.
- */
-void ethernut5_power_init(void)
-{
- pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS);
- pwrman_major = pwrman_minor >> 4;
- pwrman_minor &= 15;
-
-#ifndef CONFIG_CMD_BSP
- /* Do not modify anything, if we do not have a known version. */
- if (pwrman_major == 2) {
- /* Without board specific commands we enable all features. */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST);
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
- }
-#endif
-}
-
-/*
- * Reset Ethernet PHY.
- *
- * This function allows the re-configure the PHY after
- * changing its strap pins.
- */
-void ethernut5_phy_reset(void)
-{
- /* Do not modify anything, if we do not have a known version. */
- if (pwrman_major != 2)
- return;
-
- /*
- * Make sure that the Ethernet clock is enabled and the PHY reset
- * is disabled for at least 100 us.
- */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK);
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
- udelay(100);
-
- /*
- * LAN8710 strap pins are
- * PA14 => PHY MODE0
- * PA15 => PHY MODE1
- * PA17 => PHY MODE2 => 111b all capable
- * PA18 => PHY ADDR0 => 0b
- */
- at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
- at91_set_pio_input(AT91_PIO_PORTA, 15, 1);
- at91_set_pio_input(AT91_PIO_PORTA, 17, 1);
- at91_set_pio_input(AT91_PIO_PORTA, 18, 0);
-
- /* Activate PHY reset for 100 us. */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST);
- udelay(100);
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
-
- at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
-}
-
-/*
- * Output the firmware version we got during initialization.
- */
-void ethernut5_print_version(void)
-{
- printf("%u.%u\n", pwrman_major, pwrman_minor);
-}
-
-/*
- * All code below this point is optional and implements
- * the 'pwrman' command.
- */
-#ifdef CONFIG_CMD_BSP
-
-/* Human readable names of PMC features */
-char *pwrman_feat[8] = {
- "board", "vbin", "vbout", "mmc",
- "rs232", "ethclk", "ethrst", "wakeup"
-};
-
-/*
- * Print all feature names, that have its related flags enabled.
- */
-static void print_flagged_features(u8 flags)
-{
- int i;
-
- for (i = 0; i < 8; i++) {
- if (flags & (1 << i))
- printf("%s ", pwrman_feat[i]);
- }
-}
-
-/*
- * Return flags of a given list of feature names.
- *
- * The function stops at the first unknown list entry and
- * returns the number of detected names as a function result.
- */
-static int feature_flags(char * const names[], int num, u8 *flags)
-{
- int i, j;
-
- *flags = 0;
- for (i = 0; i < num; i++) {
- for (j = 0; j < 8; j++) {
- if (strcmp(pwrman_feat[j], names[i]) == 0) {
- *flags |= 1 << j;
- break;
- }
- }
- if (j > 7)
- break;
- }
- return i;
-}
-
-void ethernut5_print_power(void)
-{
- u8 flags;
- int i;
-
- flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA);
- for (i = 0; i < 2; i++) {
- if (flags) {
- print_flagged_features(flags);
- printf("%s\n", i ? "off" : "on");
- }
- flags = ~flags;
- }
-}
-
-void ethernut5_print_celsius(void)
-{
- int val;
-
- /* Read ADC value from LM50 and return Celsius degrees. */
- val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP);
- val *= 5000; /* 100mV/degree with 5V reference */
- val += 128; /* 8 bit resolution */
- val /= 256;
- val -= 450; /* Celsius offset, still x10 */
- /* Output full degrees. */
- printf("%d\n", (val + 5) / 10);
-}
-
-void ethernut5_print_voltage(void)
-{
- int val;
-
- /* Read ADC value from divider and return voltage. */
- val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX);
- /* Resistors are 100k and 12.1k */
- val += 5;
- val *= 180948;
- val /= 100000;
- val++;
- /* Calculation was done in 0.1V units. */
- printf("%d\n", (val + 5) / 10);
-}
-
-/*
- * Process the board specific 'pwrman' command.
- */
-int do_pwrman(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- u8 val;
- int i;
-
- if (argc == 1) {
- ethernut5_print_power();
- } else if (argc == 2 && strcmp(argv[1], "reset") == 0) {
- at91_set_pio_output(AT91_PIO_PORTB, 8, 1);
- udelay(100);
- at91_set_pio_output(AT91_PIO_PORTB, 8, 0);
- udelay(100000);
- } else if (argc == 2 && strcmp(argv[1], "temp") == 0) {
- ethernut5_print_celsius();
- } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) {
- ethernut5_print_voltage();
- } else if (argc == 2 && strcmp(argv[1], "version") == 0) {
- ethernut5_print_version();
- } else if (strcmp(argv[1], "led") == 0) {
- /* Control the green status LED. Blink frequency unit
- ** is 0.1s, very roughly. */
- if (argc == 2) {
- /* No more arguments, output current settings. */
- val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL);
- printf("led %u %u\n", val >> 4, val & 15);
- } else {
- /* First argument specifies the on-time. */
- val = (u8) simple_strtoul(argv[2], NULL, 0);
- val <<= 4;
- if (argc > 3) {
- /* Second argument specifies the off-time. */
- val |= (u8) (simple_strtoul(argv[3], NULL, 0)
- & 15);
- }
- /* Update the LED control register. */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val);
- }
- } else {
- /* We expect a list of features followed an optional status. */
- argc--;
- i = feature_flags(&argv[1], argc, &val);
- if (argc == i) {
- /* We got a list only, print status. */
- val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA);
- if (val) {
- if (i > 1)
- print_flagged_features(val);
- printf("active\n");
- } else {
- printf("inactive\n");
- }
- } else {
- /* More arguments. */
- if (i == 0) {
- /* No given feature, use despensibles. */
- val = PWRMAN_DISPENSIBLE;
- }
- if (strcmp(argv[i + 1], "on") == 0) {
- /* Enable features. */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA,
- val);
- } else if (strcmp(argv[i + 1], "off") == 0) {
- /* Disable features. */
- i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS,
- val);
- } else {
- printf("Bad parameter %s\n", argv[i + 1]);
- return 1;
- }
- }
- }
- return 0;
-}
-
-U_BOOT_CMD(
- pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman,
- "power management",
- "- print settings\n"
- "pwrman feature ...\n"
- " - print status\n"
- "pwrman [feature ...] on|off\n"
- " - enable/disable specified or all dispensible features\n"
- "pwrman led [on-time [off-time]]\n"
- " - print or set led blink timer\n"
- "pwrman temp\n"
- " - print board temperature (Celsius)\n"
- "pwrman vaux\n"
- " - print auxiliary input voltage\n"
- "pwrman reset\n"
- " - reset power management controller\n"
- "pwrman version\n"
- " - print firmware version\n"
- "\n"
- " features, (*)=dispensible:\n"
- " board - 1.8V and 3.3V supply\n"
- " vbin - supply via USB device connector\n"
- " vbout - USB host connector supply(*)\n"
- " mmc - MMC slot supply(*)\n"
- " rs232 - RS232 driver\n"
- " ethclk - Ethernet PHY clock(*)\n"
- " ethrst - Ethernet PHY reset\n"
- " wakeup - RTC alarm"
-);
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h
deleted file mode 100644
index 103f558..0000000
--- a/board/egnite/ethernut5/ethernut5_pwrman.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * egnite GmbH <info@egnite.de>
- */
-
-/*
- * Ethernut 5 power management support
- *
- * For additional information visit the project home page at
- * http://www.ethernut.de/
- */
-
-/* I2C address of the PMC */
-#define PWRMAN_I2C_ADDR 0x22
-
-/* PMC registers */
-#define PWRMAN_REG_VERS 0 /* Version register */
-#define PWRMAN_REG_STA 1 /* Feature status register */
-#define PWRMAN_REG_ENA 2 /* Feature enable register */
-#define PWRMAN_REG_DIS 3 /* Feature disable register */
-#define PWRMAN_REG_TEMP 4 /* Board temperature */
-#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */
-#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */
-
-/* Feature flags used in status, enable and disable registers */
-#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */
-#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */
-#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */
-#define PWRMAN_MMC 0x08 /* Memory card supply */
-#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */
-#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */
-#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */
-#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */
-
-/* Features, which are not essential to keep u-boot alive */
-#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK)
-
-/* Enable Ethernut 5 power management. */
-extern void ethernut5_power_init(void);
-
-/* Reset Ethernet PHY. */
-extern void ethernut5_phy_reset(void);
-
-extern void ethernut5_print_version(void);
-
-#ifdef CONFIG_CMD_BSP
-extern void ethernut5_print_power(void);
-extern void ethernut5_print_celsius(void);
-extern void ethernut5_print_voltage(void);
-#endif
diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c
index bc2af66..56557d5 100644
--- a/board/engicam/stm32mp1/stm32mp1.c
+++ b/board/engicam/stm32mp1/stm32mp1.c
@@ -37,9 +37,6 @@
/* board dependent setup after realloc */
int board_init(void)
{
- if (IS_ENABLED(CONFIG_DM_REGULATOR))
- regulators_enable_boot_on(_DEBUG);
-
return 0;
}
diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile
index 17956d2..ede8d20 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,9 +8,5 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-ifdef CONFIG_IMX9_LOW_DRIVE_MODE
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o
-else
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
-endif
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o
endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
new file mode 100644
index 0000000..f4e910b
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ff},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x0051E1E6},
+ {0x4e300124, 0x0E3A0000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30900000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x11281109},
+ {0x4e300304, 0x00AA140A},
+ {0x4e300308, 0x063C071E},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010A1000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x9492AA58},
+ {0x4e30010C, 0x00310113},
+ {0x4e300124, 0x071E0000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30200000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x0000000A},
+ {0x4e300254, 0x00510051},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x5ff},
+ {0x1015f, 0x5ff},
+ {0x1105f, 0x5ff},
+ {0x1115f, 0x5ff},
+ {0x11005f, 0x5ff},
+ {0x11015f, 0x5ff},
+ {0x11105f, 0x5ff},
+ {0x11115f, 0x5ff},
+ {0x21005f, 0x5ff},
+ {0x21015f, 0x5ff},
+ {0x21105f, 0x5ff},
+ {0x21115f, 0x5ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0xb},
+ {0x1200c5, 0x3},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x1},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe00},
+ {0x10149, 0xe00},
+ {0x11049, 0xe00},
+ {0x11149, 0xe00},
+ {0x110049, 0xe00},
+ {0x110149, 0xe00},
+ {0x111049, 0xe00},
+ {0x111149, 0xe00},
+ {0x210049, 0xe00},
+ {0x210149, 0xe00},
+ {0x211049, 0xe00},
+ {0x211149, 0xe00},
+ {0x43, 0x60},
+ {0x1043, 0x60},
+ {0x2043, 0x60},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x2009b, 0x2},
+ {0x20008, 0x1d3},
+ {0x120008, 0xe9},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x41},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
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+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x321b},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x321b},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x3a4},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3209},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3209},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1100},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1100},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3209},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3209},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x321b},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x321b},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x20d},
+ {0x2000c, 0x74},
+ {0x2000d, 0x48e},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x107},
+ {0x12000c, 0x3a},
+ {0x12000d, 0x246},
+ {0x12000e, 0x21},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 1866mts 1D */
+ .drate = 1866,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 933mts 1D */
+ .drate = 933,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 1866mts 2D */
+ .drate = 1866,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1866mts = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 1866, 933, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
deleted file mode 100644
index f080322..0000000
--- a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
+++ /dev/null
@@ -1,1496 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2022 NXP
- *
- * Generated code from IMX_DDR_tool
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- */
-
-#include <linux/kernel.h>
-#include <asm/arch/ddr.h>
-
-struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
- { 0x4e300110, 0x44140001 },
- { 0x4e301000, 0x0 },
- { 0x4e300000, 0x8000ff },
- { 0x4e300008, 0x0 },
- { 0x4e300080, 0x80000512 },
- { 0x4e300084, 0x0 },
- { 0x4e300114, 0x2 },
- { 0x4e300260, 0x0 },
- { 0x4e30017c, 0x0 },
- { 0x4e300f04, 0x80 },
- { 0x4e300104, 0xaa77000e },
- { 0x4e300108, 0x1816b1aa },
- { 0x4e30010c, 0x5101e6 },
- { 0x4e300100, 0x12552100 },
- { 0x4e300160, 0x9002 },
- { 0x4e30016c, 0x30900000 },
- { 0x4e300250, 0x14 },
- { 0x4e300254, 0xaa00aa },
- { 0x4e300258, 0x8 },
- { 0x4e30025c, 0x400 },
- { 0x4e300300, 0x11281109 },
- { 0x4e300304, 0xaa110a },
- { 0x4e300308, 0x620071e },
- { 0x4e300170, 0x8a0a0508 },
- { 0x4e300124, 0xe3c0000 },
- { 0x4e300804, 0x1f1f1f1f },
- { 0x4e301240, 0x0 },
- { 0x4e301244, 0x0 },
- { 0x4e301248, 0x0 },
- { 0x4e30124c, 0x0 },
- { 0x4e301250, 0x0 },
- { 0x4e301254, 0x0 },
- { 0x4e301258, 0x0 },
- { 0x4e30125c, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-struct dram_cfg_param ddr_ddrphy_cfg[] = {
- { 0x100a0, 0x4 },
- { 0x100a1, 0x5 },
- { 0x100a2, 0x6 },
- { 0x100a3, 0x7 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x1 },
- { 0x100a6, 0x2 },
- { 0x100a7, 0x3 },
- { 0x110a0, 0x3 },
- { 0x110a1, 0x2 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x1 },
- { 0x110a4, 0x7 },
- { 0x110a5, 0x6 },
- { 0x110a6, 0x4 },
- { 0x110a7, 0x5 },
- { 0x1005f, 0x5ff },
- { 0x1015f, 0x5ff },
- { 0x1105f, 0x5ff },
- { 0x1115f, 0x5ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x200c5, 0xb },
- { 0x2002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x20024, 0x1e3 },
- { 0x2003a, 0x2 },
- { 0x2007d, 0x212 },
- { 0x2007c, 0x61 },
- { 0x20056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x10049, 0xe00 },
- { 0x10149, 0xe00 },
- { 0x11049, 0xe00 },
- { 0x11149, 0xe00 },
- { 0x43, 0x60 },
- { 0x1043, 0x60 },
- { 0x2043, 0x60 },
- { 0x20018, 0x1 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x2009b, 0x2 },
- { 0x20008, 0x1d3 },
- { 0x20088, 0x9 },
- { 0x200b2, 0x10c },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x200fa, 0x2 },
- { 0x20019, 0x1 },
- { 0x200f0, 0x0 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x4444 },
- { 0x200f3, 0x8888 },
- { 0x200f4, 0x5555 },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x20021, 0x0 },
- { 0x2002c, 0x0 },
-};
-
-/* ddr phy trained csr */
-struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
- { 0x200b2, 0x0 },
- { 0x1200b2, 0x0 },
- { 0x2200b2, 0x0 },
- { 0x200cb, 0x0 },
- { 0x10043, 0x0 },
- { 0x110043, 0x0 },
- { 0x210043, 0x0 },
- { 0x10143, 0x0 },
- { 0x110143, 0x0 },
- { 0x210143, 0x0 },
- { 0x11043, 0x0 },
- { 0x111043, 0x0 },
- { 0x211043, 0x0 },
- { 0x11143, 0x0 },
- { 0x111143, 0x0 },
- { 0x211143, 0x0 },
- { 0x12043, 0x0 },
- { 0x112043, 0x0 },
- { 0x212043, 0x0 },
- { 0x12143, 0x0 },
- { 0x112143, 0x0 },
- { 0x212143, 0x0 },
- { 0x13043, 0x0 },
- { 0x113043, 0x0 },
- { 0x213043, 0x0 },
- { 0x13143, 0x0 },
- { 0x113143, 0x0 },
- { 0x213143, 0x0 },
- { 0x80, 0x0 },
- { 0x100080, 0x0 },
- { 0x200080, 0x0 },
- { 0x1080, 0x0 },
- { 0x101080, 0x0 },
- { 0x201080, 0x0 },
- { 0x2080, 0x0 },
- { 0x102080, 0x0 },
- { 0x202080, 0x0 },
- { 0x3080, 0x0 },
- { 0x103080, 0x0 },
- { 0x203080, 0x0 },
- { 0x4080, 0x0 },
- { 0x104080, 0x0 },
- { 0x204080, 0x0 },
- { 0x5080, 0x0 },
- { 0x105080, 0x0 },
- { 0x205080, 0x0 },
- { 0x6080, 0x0 },
- { 0x106080, 0x0 },
- { 0x206080, 0x0 },
- { 0x7080, 0x0 },
- { 0x107080, 0x0 },
- { 0x207080, 0x0 },
- { 0x8080, 0x0 },
- { 0x108080, 0x0 },
- { 0x208080, 0x0 },
- { 0x9080, 0x0 },
- { 0x109080, 0x0 },
- { 0x209080, 0x0 },
- { 0x10080, 0x0 },
- { 0x110080, 0x0 },
- { 0x210080, 0x0 },
- { 0x10180, 0x0 },
- { 0x110180, 0x0 },
- { 0x210180, 0x0 },
- { 0x11080, 0x0 },
- { 0x111080, 0x0 },
- { 0x211080, 0x0 },
- { 0x11180, 0x0 },
- { 0x111180, 0x0 },
- { 0x211180, 0x0 },
- { 0x12080, 0x0 },
- { 0x112080, 0x0 },
- { 0x212080, 0x0 },
- { 0x12180, 0x0 },
- { 0x112180, 0x0 },
- { 0x212180, 0x0 },
- { 0x13080, 0x0 },
- { 0x113080, 0x0 },
- { 0x213080, 0x0 },
- { 0x13180, 0x0 },
- { 0x113180, 0x0 },
- { 0x213180, 0x0 },
- { 0x10081, 0x0 },
- { 0x110081, 0x0 },
- { 0x210081, 0x0 },
- { 0x10181, 0x0 },
- { 0x110181, 0x0 },
- { 0x210181, 0x0 },
- { 0x11081, 0x0 },
- { 0x111081, 0x0 },
- { 0x211081, 0x0 },
- { 0x11181, 0x0 },
- { 0x111181, 0x0 },
- { 0x211181, 0x0 },
- { 0x12081, 0x0 },
- { 0x112081, 0x0 },
- { 0x212081, 0x0 },
- { 0x12181, 0x0 },
- { 0x112181, 0x0 },
- { 0x212181, 0x0 },
- { 0x13081, 0x0 },
- { 0x113081, 0x0 },
- { 0x213081, 0x0 },
- { 0x13181, 0x0 },
- { 0x113181, 0x0 },
- { 0x213181, 0x0 },
- { 0x100d0, 0x0 },
- { 0x1100d0, 0x0 },
- { 0x2100d0, 0x0 },
- { 0x101d0, 0x0 },
- { 0x1101d0, 0x0 },
- { 0x2101d0, 0x0 },
- { 0x110d0, 0x0 },
- { 0x1110d0, 0x0 },
- { 0x2110d0, 0x0 },
- { 0x111d0, 0x0 },
- { 0x1111d0, 0x0 },
- { 0x2111d0, 0x0 },
- { 0x120d0, 0x0 },
- { 0x1120d0, 0x0 },
- { 0x2120d0, 0x0 },
- { 0x121d0, 0x0 },
- { 0x1121d0, 0x0 },
- { 0x2121d0, 0x0 },
- { 0x130d0, 0x0 },
- { 0x1130d0, 0x0 },
- { 0x2130d0, 0x0 },
- { 0x131d0, 0x0 },
- { 0x1131d0, 0x0 },
- { 0x2131d0, 0x0 },
- { 0x100d1, 0x0 },
- { 0x1100d1, 0x0 },
- { 0x2100d1, 0x0 },
- { 0x101d1, 0x0 },
- { 0x1101d1, 0x0 },
- { 0x2101d1, 0x0 },
- { 0x110d1, 0x0 },
- { 0x1110d1, 0x0 },
- { 0x2110d1, 0x0 },
- { 0x111d1, 0x0 },
- { 0x1111d1, 0x0 },
- { 0x2111d1, 0x0 },
- { 0x120d1, 0x0 },
- { 0x1120d1, 0x0 },
- { 0x2120d1, 0x0 },
- { 0x121d1, 0x0 },
- { 0x1121d1, 0x0 },
- { 0x2121d1, 0x0 },
- { 0x130d1, 0x0 },
- { 0x1130d1, 0x0 },
- { 0x2130d1, 0x0 },
- { 0x131d1, 0x0 },
- { 0x1131d1, 0x0 },
- { 0x2131d1, 0x0 },
- { 0x10068, 0x0 },
- { 0x10168, 0x0 },
- { 0x10268, 0x0 },
- { 0x10368, 0x0 },
- { 0x10468, 0x0 },
- { 0x10568, 0x0 },
- { 0x10668, 0x0 },
- { 0x10768, 0x0 },
- { 0x10868, 0x0 },
- { 0x11068, 0x0 },
- { 0x11168, 0x0 },
- { 0x11268, 0x0 },
- { 0x11368, 0x0 },
- { 0x11468, 0x0 },
- { 0x11568, 0x0 },
- { 0x11668, 0x0 },
- { 0x11768, 0x0 },
- { 0x11868, 0x0 },
- { 0x12068, 0x0 },
- { 0x12168, 0x0 },
- { 0x12268, 0x0 },
- { 0x12368, 0x0 },
- { 0x12468, 0x0 },
- { 0x12568, 0x0 },
- { 0x12668, 0x0 },
- { 0x12768, 0x0 },
- { 0x12868, 0x0 },
- { 0x13068, 0x0 },
- { 0x13168, 0x0 },
- { 0x13268, 0x0 },
- { 0x13368, 0x0 },
- { 0x13468, 0x0 },
- { 0x13568, 0x0 },
- { 0x13668, 0x0 },
- { 0x13768, 0x0 },
- { 0x13868, 0x0 },
- { 0x10069, 0x0 },
- { 0x10169, 0x0 },
- { 0x10269, 0x0 },
- { 0x10369, 0x0 },
- { 0x10469, 0x0 },
- { 0x10569, 0x0 },
- { 0x10669, 0x0 },
- { 0x10769, 0x0 },
- { 0x10869, 0x0 },
- { 0x11069, 0x0 },
- { 0x11169, 0x0 },
- { 0x11269, 0x0 },
- { 0x11369, 0x0 },
- { 0x11469, 0x0 },
- { 0x11569, 0x0 },
- { 0x11669, 0x0 },
- { 0x11769, 0x0 },
- { 0x11869, 0x0 },
- { 0x12069, 0x0 },
- { 0x12169, 0x0 },
- { 0x12269, 0x0 },
- { 0x12369, 0x0 },
- { 0x12469, 0x0 },
- { 0x12569, 0x0 },
- { 0x12669, 0x0 },
- { 0x12769, 0x0 },
- { 0x12869, 0x0 },
- { 0x13069, 0x0 },
- { 0x13169, 0x0 },
- { 0x13269, 0x0 },
- { 0x13369, 0x0 },
- { 0x13469, 0x0 },
- { 0x13569, 0x0 },
- { 0x13669, 0x0 },
- { 0x13769, 0x0 },
- { 0x13869, 0x0 },
- { 0x1008c, 0x0 },
- { 0x11008c, 0x0 },
- { 0x21008c, 0x0 },
- { 0x1018c, 0x0 },
- { 0x11018c, 0x0 },
- { 0x21018c, 0x0 },
- { 0x1108c, 0x0 },
- { 0x11108c, 0x0 },
- { 0x21108c, 0x0 },
- { 0x1118c, 0x0 },
- { 0x11118c, 0x0 },
- { 0x21118c, 0x0 },
- { 0x1208c, 0x0 },
- { 0x11208c, 0x0 },
- { 0x21208c, 0x0 },
- { 0x1218c, 0x0 },
- { 0x11218c, 0x0 },
- { 0x21218c, 0x0 },
- { 0x1308c, 0x0 },
- { 0x11308c, 0x0 },
- { 0x21308c, 0x0 },
- { 0x1318c, 0x0 },
- { 0x11318c, 0x0 },
- { 0x21318c, 0x0 },
- { 0x1008d, 0x0 },
- { 0x11008d, 0x0 },
- { 0x21008d, 0x0 },
- { 0x1018d, 0x0 },
- { 0x11018d, 0x0 },
- { 0x21018d, 0x0 },
- { 0x1108d, 0x0 },
- { 0x11108d, 0x0 },
- { 0x21108d, 0x0 },
- { 0x1118d, 0x0 },
- { 0x11118d, 0x0 },
- { 0x21118d, 0x0 },
- { 0x1208d, 0x0 },
- { 0x11208d, 0x0 },
- { 0x21208d, 0x0 },
- { 0x1218d, 0x0 },
- { 0x11218d, 0x0 },
- { 0x21218d, 0x0 },
- { 0x1308d, 0x0 },
- { 0x11308d, 0x0 },
- { 0x21308d, 0x0 },
- { 0x1318d, 0x0 },
- { 0x11318d, 0x0 },
- { 0x21318d, 0x0 },
- { 0x100c0, 0x0 },
- { 0x1100c0, 0x0 },
- { 0x2100c0, 0x0 },
- { 0x101c0, 0x0 },
- { 0x1101c0, 0x0 },
- { 0x2101c0, 0x0 },
- { 0x102c0, 0x0 },
- { 0x1102c0, 0x0 },
- { 0x2102c0, 0x0 },
- { 0x103c0, 0x0 },
- { 0x1103c0, 0x0 },
- { 0x2103c0, 0x0 },
- { 0x104c0, 0x0 },
- { 0x1104c0, 0x0 },
- { 0x2104c0, 0x0 },
- { 0x105c0, 0x0 },
- { 0x1105c0, 0x0 },
- { 0x2105c0, 0x0 },
- { 0x106c0, 0x0 },
- { 0x1106c0, 0x0 },
- { 0x2106c0, 0x0 },
- { 0x107c0, 0x0 },
- { 0x1107c0, 0x0 },
- { 0x2107c0, 0x0 },
- { 0x108c0, 0x0 },
- { 0x1108c0, 0x0 },
- { 0x2108c0, 0x0 },
- { 0x110c0, 0x0 },
- { 0x1110c0, 0x0 },
- { 0x2110c0, 0x0 },
- { 0x111c0, 0x0 },
- { 0x1111c0, 0x0 },
- { 0x2111c0, 0x0 },
- { 0x112c0, 0x0 },
- { 0x1112c0, 0x0 },
- { 0x2112c0, 0x0 },
- { 0x113c0, 0x0 },
- { 0x1113c0, 0x0 },
- { 0x2113c0, 0x0 },
- { 0x114c0, 0x0 },
- { 0x1114c0, 0x0 },
- { 0x2114c0, 0x0 },
- { 0x115c0, 0x0 },
- { 0x1115c0, 0x0 },
- { 0x2115c0, 0x0 },
- { 0x116c0, 0x0 },
- { 0x1116c0, 0x0 },
- { 0x2116c0, 0x0 },
- { 0x117c0, 0x0 },
- { 0x1117c0, 0x0 },
- { 0x2117c0, 0x0 },
- { 0x118c0, 0x0 },
- { 0x1118c0, 0x0 },
- { 0x2118c0, 0x0 },
- { 0x120c0, 0x0 },
- { 0x1120c0, 0x0 },
- { 0x2120c0, 0x0 },
- { 0x121c0, 0x0 },
- { 0x1121c0, 0x0 },
- { 0x2121c0, 0x0 },
- { 0x122c0, 0x0 },
- { 0x1122c0, 0x0 },
- { 0x2122c0, 0x0 },
- { 0x123c0, 0x0 },
- { 0x1123c0, 0x0 },
- { 0x2123c0, 0x0 },
- { 0x124c0, 0x0 },
- { 0x1124c0, 0x0 },
- { 0x2124c0, 0x0 },
- { 0x125c0, 0x0 },
- { 0x1125c0, 0x0 },
- { 0x2125c0, 0x0 },
- { 0x126c0, 0x0 },
- { 0x1126c0, 0x0 },
- { 0x2126c0, 0x0 },
- { 0x127c0, 0x0 },
- { 0x1127c0, 0x0 },
- { 0x2127c0, 0x0 },
- { 0x128c0, 0x0 },
- { 0x1128c0, 0x0 },
- { 0x2128c0, 0x0 },
- { 0x130c0, 0x0 },
- { 0x1130c0, 0x0 },
- { 0x2130c0, 0x0 },
- { 0x131c0, 0x0 },
- { 0x1131c0, 0x0 },
- { 0x2131c0, 0x0 },
- { 0x132c0, 0x0 },
- { 0x1132c0, 0x0 },
- { 0x2132c0, 0x0 },
- { 0x133c0, 0x0 },
- { 0x1133c0, 0x0 },
- { 0x2133c0, 0x0 },
- { 0x134c0, 0x0 },
- { 0x1134c0, 0x0 },
- { 0x2134c0, 0x0 },
- { 0x135c0, 0x0 },
- { 0x1135c0, 0x0 },
- { 0x2135c0, 0x0 },
- { 0x136c0, 0x0 },
- { 0x1136c0, 0x0 },
- { 0x2136c0, 0x0 },
- { 0x137c0, 0x0 },
- { 0x1137c0, 0x0 },
- { 0x2137c0, 0x0 },
- { 0x138c0, 0x0 },
- { 0x1138c0, 0x0 },
- { 0x2138c0, 0x0 },
- { 0x100c1, 0x0 },
- { 0x1100c1, 0x0 },
- { 0x2100c1, 0x0 },
- { 0x101c1, 0x0 },
- { 0x1101c1, 0x0 },
- { 0x2101c1, 0x0 },
- { 0x102c1, 0x0 },
- { 0x1102c1, 0x0 },
- { 0x2102c1, 0x0 },
- { 0x103c1, 0x0 },
- { 0x1103c1, 0x0 },
- { 0x2103c1, 0x0 },
- { 0x104c1, 0x0 },
- { 0x1104c1, 0x0 },
- { 0x2104c1, 0x0 },
- { 0x105c1, 0x0 },
- { 0x1105c1, 0x0 },
- { 0x2105c1, 0x0 },
- { 0x106c1, 0x0 },
- { 0x1106c1, 0x0 },
- { 0x2106c1, 0x0 },
- { 0x107c1, 0x0 },
- { 0x1107c1, 0x0 },
- { 0x2107c1, 0x0 },
- { 0x108c1, 0x0 },
- { 0x1108c1, 0x0 },
- { 0x2108c1, 0x0 },
- { 0x110c1, 0x0 },
- { 0x1110c1, 0x0 },
- { 0x2110c1, 0x0 },
- { 0x111c1, 0x0 },
- { 0x1111c1, 0x0 },
- { 0x2111c1, 0x0 },
- { 0x112c1, 0x0 },
- { 0x1112c1, 0x0 },
- { 0x2112c1, 0x0 },
- { 0x113c1, 0x0 },
- { 0x1113c1, 0x0 },
- { 0x2113c1, 0x0 },
- { 0x114c1, 0x0 },
- { 0x1114c1, 0x0 },
- { 0x2114c1, 0x0 },
- { 0x115c1, 0x0 },
- { 0x1115c1, 0x0 },
- { 0x2115c1, 0x0 },
- { 0x116c1, 0x0 },
- { 0x1116c1, 0x0 },
- { 0x2116c1, 0x0 },
- { 0x117c1, 0x0 },
- { 0x1117c1, 0x0 },
- { 0x2117c1, 0x0 },
- { 0x118c1, 0x0 },
- { 0x1118c1, 0x0 },
- { 0x2118c1, 0x0 },
- { 0x120c1, 0x0 },
- { 0x1120c1, 0x0 },
- { 0x2120c1, 0x0 },
- { 0x121c1, 0x0 },
- { 0x1121c1, 0x0 },
- { 0x2121c1, 0x0 },
- { 0x122c1, 0x0 },
- { 0x1122c1, 0x0 },
- { 0x2122c1, 0x0 },
- { 0x123c1, 0x0 },
- { 0x1123c1, 0x0 },
- { 0x2123c1, 0x0 },
- { 0x124c1, 0x0 },
- { 0x1124c1, 0x0 },
- { 0x2124c1, 0x0 },
- { 0x125c1, 0x0 },
- { 0x1125c1, 0x0 },
- { 0x2125c1, 0x0 },
- { 0x126c1, 0x0 },
- { 0x1126c1, 0x0 },
- { 0x2126c1, 0x0 },
- { 0x127c1, 0x0 },
- { 0x1127c1, 0x0 },
- { 0x2127c1, 0x0 },
- { 0x128c1, 0x0 },
- { 0x1128c1, 0x0 },
- { 0x2128c1, 0x0 },
- { 0x130c1, 0x0 },
- { 0x1130c1, 0x0 },
- { 0x2130c1, 0x0 },
- { 0x131c1, 0x0 },
- { 0x1131c1, 0x0 },
- { 0x2131c1, 0x0 },
- { 0x132c1, 0x0 },
- { 0x1132c1, 0x0 },
- { 0x2132c1, 0x0 },
- { 0x133c1, 0x0 },
- { 0x1133c1, 0x0 },
- { 0x2133c1, 0x0 },
- { 0x134c1, 0x0 },
- { 0x1134c1, 0x0 },
- { 0x2134c1, 0x0 },
- { 0x135c1, 0x0 },
- { 0x1135c1, 0x0 },
- { 0x2135c1, 0x0 },
- { 0x136c1, 0x0 },
- { 0x1136c1, 0x0 },
- { 0x2136c1, 0x0 },
- { 0x137c1, 0x0 },
- { 0x1137c1, 0x0 },
- { 0x2137c1, 0x0 },
- { 0x138c1, 0x0 },
- { 0x1138c1, 0x0 },
- { 0x2138c1, 0x0 },
- { 0x10020, 0x0 },
- { 0x110020, 0x0 },
- { 0x210020, 0x0 },
- { 0x11020, 0x0 },
- { 0x111020, 0x0 },
- { 0x211020, 0x0 },
- { 0x12020, 0x0 },
- { 0x112020, 0x0 },
- { 0x212020, 0x0 },
- { 0x13020, 0x0 },
- { 0x113020, 0x0 },
- { 0x213020, 0x0 },
- { 0x20072, 0x0 },
- { 0x20073, 0x0 },
- { 0x20074, 0x0 },
- { 0x100aa, 0x0 },
- { 0x110aa, 0x0 },
- { 0x120aa, 0x0 },
- { 0x130aa, 0x0 },
- { 0x20010, 0x0 },
- { 0x120010, 0x0 },
- { 0x220010, 0x0 },
- { 0x20011, 0x0 },
- { 0x120011, 0x0 },
- { 0x220011, 0x0 },
- { 0x100ae, 0x0 },
- { 0x1100ae, 0x0 },
- { 0x2100ae, 0x0 },
- { 0x100af, 0x0 },
- { 0x1100af, 0x0 },
- { 0x2100af, 0x0 },
- { 0x110ae, 0x0 },
- { 0x1110ae, 0x0 },
- { 0x2110ae, 0x0 },
- { 0x110af, 0x0 },
- { 0x1110af, 0x0 },
- { 0x2110af, 0x0 },
- { 0x120ae, 0x0 },
- { 0x1120ae, 0x0 },
- { 0x2120ae, 0x0 },
- { 0x120af, 0x0 },
- { 0x1120af, 0x0 },
- { 0x2120af, 0x0 },
- { 0x130ae, 0x0 },
- { 0x1130ae, 0x0 },
- { 0x2130ae, 0x0 },
- { 0x130af, 0x0 },
- { 0x1130af, 0x0 },
- { 0x2130af, 0x0 },
- { 0x20020, 0x0 },
- { 0x120020, 0x0 },
- { 0x220020, 0x0 },
- { 0x100a0, 0x0 },
- { 0x100a1, 0x0 },
- { 0x100a2, 0x0 },
- { 0x100a3, 0x0 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x0 },
- { 0x100a6, 0x0 },
- { 0x100a7, 0x0 },
- { 0x110a0, 0x0 },
- { 0x110a1, 0x0 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x0 },
- { 0x110a4, 0x0 },
- { 0x110a5, 0x0 },
- { 0x110a6, 0x0 },
- { 0x110a7, 0x0 },
- { 0x120a0, 0x0 },
- { 0x120a1, 0x0 },
- { 0x120a2, 0x0 },
- { 0x120a3, 0x0 },
- { 0x120a4, 0x0 },
- { 0x120a5, 0x0 },
- { 0x120a6, 0x0 },
- { 0x120a7, 0x0 },
- { 0x130a0, 0x0 },
- { 0x130a1, 0x0 },
- { 0x130a2, 0x0 },
- { 0x130a3, 0x0 },
- { 0x130a4, 0x0 },
- { 0x130a5, 0x0 },
- { 0x130a6, 0x0 },
- { 0x130a7, 0x0 },
- { 0x2007c, 0x0 },
- { 0x12007c, 0x0 },
- { 0x22007c, 0x0 },
- { 0x2007d, 0x0 },
- { 0x12007d, 0x0 },
- { 0x22007d, 0x0 },
- { 0x400fd, 0x0 },
- { 0x400c0, 0x0 },
- { 0x90201, 0x0 },
- { 0x190201, 0x0 },
- { 0x290201, 0x0 },
- { 0x90202, 0x0 },
- { 0x190202, 0x0 },
- { 0x290202, 0x0 },
- { 0x90203, 0x0 },
- { 0x190203, 0x0 },
- { 0x290203, 0x0 },
- { 0x90204, 0x0 },
- { 0x190204, 0x0 },
- { 0x290204, 0x0 },
- { 0x90205, 0x0 },
- { 0x190205, 0x0 },
- { 0x290205, 0x0 },
- { 0x90206, 0x0 },
- { 0x190206, 0x0 },
- { 0x290206, 0x0 },
- { 0x90207, 0x0 },
- { 0x190207, 0x0 },
- { 0x290207, 0x0 },
- { 0x90208, 0x0 },
- { 0x190208, 0x0 },
- { 0x290208, 0x0 },
- { 0x10062, 0x0 },
- { 0x10162, 0x0 },
- { 0x10262, 0x0 },
- { 0x10362, 0x0 },
- { 0x10462, 0x0 },
- { 0x10562, 0x0 },
- { 0x10662, 0x0 },
- { 0x10762, 0x0 },
- { 0x10862, 0x0 },
- { 0x11062, 0x0 },
- { 0x11162, 0x0 },
- { 0x11262, 0x0 },
- { 0x11362, 0x0 },
- { 0x11462, 0x0 },
- { 0x11562, 0x0 },
- { 0x11662, 0x0 },
- { 0x11762, 0x0 },
- { 0x11862, 0x0 },
- { 0x12062, 0x0 },
- { 0x12162, 0x0 },
- { 0x12262, 0x0 },
- { 0x12362, 0x0 },
- { 0x12462, 0x0 },
- { 0x12562, 0x0 },
- { 0x12662, 0x0 },
- { 0x12762, 0x0 },
- { 0x12862, 0x0 },
- { 0x13062, 0x0 },
- { 0x13162, 0x0 },
- { 0x13262, 0x0 },
- { 0x13362, 0x0 },
- { 0x13462, 0x0 },
- { 0x13562, 0x0 },
- { 0x13662, 0x0 },
- { 0x13762, 0x0 },
- { 0x13862, 0x0 },
- { 0x20077, 0x0 },
- { 0x10001, 0x0 },
- { 0x11001, 0x0 },
- { 0x12001, 0x0 },
- { 0x13001, 0x0 },
- { 0x10040, 0x0 },
- { 0x10140, 0x0 },
- { 0x10240, 0x0 },
- { 0x10340, 0x0 },
- { 0x10440, 0x0 },
- { 0x10540, 0x0 },
- { 0x10640, 0x0 },
- { 0x10740, 0x0 },
- { 0x10840, 0x0 },
- { 0x10030, 0x0 },
- { 0x10130, 0x0 },
- { 0x10230, 0x0 },
- { 0x10330, 0x0 },
- { 0x10430, 0x0 },
- { 0x10530, 0x0 },
- { 0x10630, 0x0 },
- { 0x10730, 0x0 },
- { 0x10830, 0x0 },
- { 0x11040, 0x0 },
- { 0x11140, 0x0 },
- { 0x11240, 0x0 },
- { 0x11340, 0x0 },
- { 0x11440, 0x0 },
- { 0x11540, 0x0 },
- { 0x11640, 0x0 },
- { 0x11740, 0x0 },
- { 0x11840, 0x0 },
- { 0x11030, 0x0 },
- { 0x11130, 0x0 },
- { 0x11230, 0x0 },
- { 0x11330, 0x0 },
- { 0x11430, 0x0 },
- { 0x11530, 0x0 },
- { 0x11630, 0x0 },
- { 0x11730, 0x0 },
- { 0x11830, 0x0 },
- { 0x12040, 0x0 },
- { 0x12140, 0x0 },
- { 0x12240, 0x0 },
- { 0x12340, 0x0 },
- { 0x12440, 0x0 },
- { 0x12540, 0x0 },
- { 0x12640, 0x0 },
- { 0x12740, 0x0 },
- { 0x12840, 0x0 },
- { 0x12030, 0x0 },
- { 0x12130, 0x0 },
- { 0x12230, 0x0 },
- { 0x12330, 0x0 },
- { 0x12430, 0x0 },
- { 0x12530, 0x0 },
- { 0x12630, 0x0 },
- { 0x12730, 0x0 },
- { 0x12830, 0x0 },
- { 0x13040, 0x0 },
- { 0x13140, 0x0 },
- { 0x13240, 0x0 },
- { 0x13340, 0x0 },
- { 0x13440, 0x0 },
- { 0x13540, 0x0 },
- { 0x13640, 0x0 },
- { 0x13740, 0x0 },
- { 0x13840, 0x0 },
- { 0x13030, 0x0 },
- { 0x13130, 0x0 },
- { 0x13230, 0x0 },
- { 0x13330, 0x0 },
- { 0x13430, 0x0 },
- { 0x13530, 0x0 },
- { 0x13630, 0x0 },
- { 0x13730, 0x0 },
- { 0x13830, 0x0 },
-};
-
-/* P0 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54003, 0x74a },
- { 0x54004, 0x4 },
- { 0x54006, 0x15 },
- { 0x54008, 0x131f },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x4 },
- { 0x5400c, 0x1 },
- { 0x5400d, 0x100 },
- { 0x5400f, 0x100 },
- { 0x54012, 0x110 },
- { 0x54019, 0x1bb4 },
- { 0x5401a, 0x32 },
- { 0x5401b, 0x1f46 },
- { 0x5401c, 0x1708 },
- { 0x5401e, 0x6 },
- { 0x5401f, 0x1bb4 },
- { 0x54020, 0x32 },
- { 0x54021, 0x1f46 },
- { 0x54022, 0x1708 },
- { 0x54024, 0x6 },
- { 0x54032, 0xb400 },
- { 0x54033, 0x321b },
- { 0x54034, 0x4600 },
- { 0x54035, 0x81f },
- { 0x54036, 0x17 },
- { 0x54037, 0x600 },
- { 0x54038, 0xb400 },
- { 0x54039, 0x321b },
- { 0x5403a, 0x4600 },
- { 0x5403b, 0x81f },
- { 0x5403c, 0x17 },
- { 0x5403d, 0x600 },
- { 0xd0000, 0x1 },
-};
-
-/* P0 2D message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
- { 0xd0000, 0x0 },
- { 0x54003, 0x74a },
- { 0x54004, 0x4 },
- { 0x54006, 0x15 },
- { 0x54008, 0x61 },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x4 },
- { 0x5400c, 0x1 },
- { 0x5400d, 0x100 },
- { 0x5400f, 0x100 },
- { 0x54010, 0x2080 },
- { 0x54012, 0x110 },
- { 0x54019, 0x1bb4 },
- { 0x5401a, 0x32 },
- { 0x5401b, 0x1f46 },
- { 0x5401c, 0x1708 },
- { 0x5401e, 0x6 },
- { 0x5401f, 0x1bb4 },
- { 0x54020, 0x32 },
- { 0x54021, 0x1f46 },
- { 0x54022, 0x1708 },
- { 0x54024, 0x6 },
- { 0x54032, 0xb400 },
- { 0x54033, 0x321b },
- { 0x54034, 0x4600 },
- { 0x54035, 0x81f },
- { 0x54036, 0x17 },
- { 0x54037, 0x600 },
- { 0x54038, 0xb400 },
- { 0x54039, 0x321b },
- { 0x5403a, 0x4600 },
- { 0x5403b, 0x81f },
- { 0x5403c, 0x17 },
- { 0x5403d, 0x600 },
- { 0xd0000, 0x1 },
-};
-
-/* DRAM PHY init engine image */
-struct dram_cfg_param ddr_phy_pie[] = {
- { 0xd0000, 0x0 },
- { 0x90000, 0x10 },
- { 0x90001, 0x400 },
- { 0x90002, 0x10e },
- { 0x90003, 0x0 },
- { 0x90004, 0x0 },
- { 0x90005, 0x8 },
- { 0x90029, 0xb },
- { 0x9002a, 0x480 },
- { 0x9002b, 0x109 },
- { 0x9002c, 0x8 },
- { 0x9002d, 0x448 },
- { 0x9002e, 0x139 },
- { 0x9002f, 0x8 },
- { 0x90030, 0x478 },
- { 0x90031, 0x109 },
- { 0x90032, 0x0 },
- { 0x90033, 0xe8 },
- { 0x90034, 0x109 },
- { 0x90035, 0x2 },
- { 0x90036, 0x10 },
- { 0x90037, 0x139 },
- { 0x90038, 0xb },
- { 0x90039, 0x7c0 },
- { 0x9003a, 0x139 },
- { 0x9003b, 0x44 },
- { 0x9003c, 0x633 },
- { 0x9003d, 0x159 },
- { 0x9003e, 0x14f },
- { 0x9003f, 0x630 },
- { 0x90040, 0x159 },
- { 0x90041, 0x47 },
- { 0x90042, 0x633 },
- { 0x90043, 0x149 },
- { 0x90044, 0x4f },
- { 0x90045, 0x633 },
- { 0x90046, 0x179 },
- { 0x90047, 0x8 },
- { 0x90048, 0xe0 },
- { 0x90049, 0x109 },
- { 0x9004a, 0x0 },
- { 0x9004b, 0x7c8 },
- { 0x9004c, 0x109 },
- { 0x9004d, 0x0 },
- { 0x9004e, 0x1 },
- { 0x9004f, 0x8 },
- { 0x90050, 0x30 },
- { 0x90051, 0x65a },
- { 0x90052, 0x9 },
- { 0x90053, 0x0 },
- { 0x90054, 0x45a },
- { 0x90055, 0x9 },
- { 0x90056, 0x0 },
- { 0x90057, 0x448 },
- { 0x90058, 0x109 },
- { 0x90059, 0x40 },
- { 0x9005a, 0x633 },
- { 0x9005b, 0x179 },
- { 0x9005c, 0x1 },
- { 0x9005d, 0x618 },
- { 0x9005e, 0x109 },
- { 0x9005f, 0x40c0 },
- { 0x90060, 0x633 },
- { 0x90061, 0x149 },
- { 0x90062, 0x8 },
- { 0x90063, 0x4 },
- { 0x90064, 0x48 },
- { 0x90065, 0x4040 },
- { 0x90066, 0x633 },
- { 0x90067, 0x149 },
- { 0x90068, 0x0 },
- { 0x90069, 0x4 },
- { 0x9006a, 0x48 },
- { 0x9006b, 0x40 },
- { 0x9006c, 0x633 },
- { 0x9006d, 0x149 },
- { 0x9006e, 0x0 },
- { 0x9006f, 0x658 },
- { 0x90070, 0x109 },
- { 0x90071, 0x10 },
- { 0x90072, 0x4 },
- { 0x90073, 0x18 },
- { 0x90074, 0x0 },
- { 0x90075, 0x4 },
- { 0x90076, 0x78 },
- { 0x90077, 0x549 },
- { 0x90078, 0x633 },
- { 0x90079, 0x159 },
- { 0x9007a, 0xd49 },
- { 0x9007b, 0x633 },
- { 0x9007c, 0x159 },
- { 0x9007d, 0x94a },
- { 0x9007e, 0x633 },
- { 0x9007f, 0x159 },
- { 0x90080, 0x441 },
- { 0x90081, 0x633 },
- { 0x90082, 0x149 },
- { 0x90083, 0x42 },
- { 0x90084, 0x633 },
- { 0x90085, 0x149 },
- { 0x90086, 0x1 },
- { 0x90087, 0x633 },
- { 0x90088, 0x149 },
- { 0x90089, 0x0 },
- { 0x9008a, 0xe0 },
- { 0x9008b, 0x109 },
- { 0x9008c, 0xa },
- { 0x9008d, 0x10 },
- { 0x9008e, 0x109 },
- { 0x9008f, 0x9 },
- { 0x90090, 0x3c0 },
- { 0x90091, 0x149 },
- { 0x90092, 0x9 },
- { 0x90093, 0x3c0 },
- { 0x90094, 0x159 },
- { 0x90095, 0x18 },
- { 0x90096, 0x10 },
- { 0x90097, 0x109 },
- { 0x90098, 0x0 },
- { 0x90099, 0x3c0 },
- { 0x9009a, 0x109 },
- { 0x9009b, 0x18 },
- { 0x9009c, 0x4 },
- { 0x9009d, 0x48 },
- { 0x9009e, 0x18 },
- { 0x9009f, 0x4 },
- { 0x900a0, 0x58 },
- { 0x900a1, 0xb },
- { 0x900a2, 0x10 },
- { 0x900a3, 0x109 },
- { 0x900a4, 0x1 },
- { 0x900a5, 0x10 },
- { 0x900a6, 0x109 },
- { 0x900a7, 0x5 },
- { 0x900a8, 0x7c0 },
- { 0x900a9, 0x109 },
- { 0x40000, 0x811 },
- { 0x40020, 0x880 },
- { 0x40040, 0x0 },
- { 0x40060, 0x0 },
- { 0x40001, 0x4008 },
- { 0x40021, 0x83 },
- { 0x40041, 0x4f },
- { 0x40061, 0x0 },
- { 0x40002, 0x4040 },
- { 0x40022, 0x83 },
- { 0x40042, 0x51 },
- { 0x40062, 0x0 },
- { 0x40003, 0x811 },
- { 0x40023, 0x880 },
- { 0x40043, 0x0 },
- { 0x40063, 0x0 },
- { 0x40004, 0x720 },
- { 0x40024, 0xf },
- { 0x40044, 0x1740 },
- { 0x40064, 0x0 },
- { 0x40005, 0x16 },
- { 0x40025, 0x83 },
- { 0x40045, 0x4b },
- { 0x40065, 0x0 },
- { 0x40006, 0x716 },
- { 0x40026, 0xf },
- { 0x40046, 0x2001 },
- { 0x40066, 0x0 },
- { 0x40007, 0x716 },
- { 0x40027, 0xf },
- { 0x40047, 0x2800 },
- { 0x40067, 0x0 },
- { 0x40008, 0x716 },
- { 0x40028, 0xf },
- { 0x40048, 0xf00 },
- { 0x40068, 0x0 },
- { 0x40009, 0x720 },
- { 0x40029, 0xf },
- { 0x40049, 0x1400 },
- { 0x40069, 0x0 },
- { 0x4000a, 0xe08 },
- { 0x4002a, 0xc15 },
- { 0x4004a, 0x0 },
- { 0x4006a, 0x0 },
- { 0x4000b, 0x625 },
- { 0x4002b, 0x15 },
- { 0x4004b, 0x0 },
- { 0x4006b, 0x0 },
- { 0x4000c, 0x4028 },
- { 0x4002c, 0x80 },
- { 0x4004c, 0x0 },
- { 0x4006c, 0x0 },
- { 0x4000d, 0xe08 },
- { 0x4002d, 0xc1a },
- { 0x4004d, 0x0 },
- { 0x4006d, 0x0 },
- { 0x4000e, 0x625 },
- { 0x4002e, 0x1a },
- { 0x4004e, 0x0 },
- { 0x4006e, 0x0 },
- { 0x4000f, 0x4040 },
- { 0x4002f, 0x80 },
- { 0x4004f, 0x0 },
- { 0x4006f, 0x0 },
- { 0x40010, 0x2604 },
- { 0x40030, 0x15 },
- { 0x40050, 0x0 },
- { 0x40070, 0x0 },
- { 0x40011, 0x708 },
- { 0x40031, 0x5 },
- { 0x40051, 0x0 },
- { 0x40071, 0x2002 },
- { 0x40012, 0x8 },
- { 0x40032, 0x80 },
- { 0x40052, 0x0 },
- { 0x40072, 0x0 },
- { 0x40013, 0x2604 },
- { 0x40033, 0x1a },
- { 0x40053, 0x0 },
- { 0x40073, 0x0 },
- { 0x40014, 0x708 },
- { 0x40034, 0xa },
- { 0x40054, 0x0 },
- { 0x40074, 0x2002 },
- { 0x40015, 0x4040 },
- { 0x40035, 0x80 },
- { 0x40055, 0x0 },
- { 0x40075, 0x0 },
- { 0x40016, 0x60a },
- { 0x40036, 0x15 },
- { 0x40056, 0x1200 },
- { 0x40076, 0x0 },
- { 0x40017, 0x61a },
- { 0x40037, 0x15 },
- { 0x40057, 0x1300 },
- { 0x40077, 0x0 },
- { 0x40018, 0x60a },
- { 0x40038, 0x1a },
- { 0x40058, 0x1200 },
- { 0x40078, 0x0 },
- { 0x40019, 0x642 },
- { 0x40039, 0x1a },
- { 0x40059, 0x1300 },
- { 0x40079, 0x0 },
- { 0x4001a, 0x4808 },
- { 0x4003a, 0x880 },
- { 0x4005a, 0x0 },
- { 0x4007a, 0x0 },
- { 0x900aa, 0x0 },
- { 0x900ab, 0x790 },
- { 0x900ac, 0x11a },
- { 0x900ad, 0x8 },
- { 0x900ae, 0x7aa },
- { 0x900af, 0x2a },
- { 0x900b0, 0x10 },
- { 0x900b1, 0x7b2 },
- { 0x900b2, 0x2a },
- { 0x900b3, 0x0 },
- { 0x900b4, 0x7c8 },
- { 0x900b5, 0x109 },
- { 0x900b6, 0x10 },
- { 0x900b7, 0x10 },
- { 0x900b8, 0x109 },
- { 0x900b9, 0x10 },
- { 0x900ba, 0x2a8 },
- { 0x900bb, 0x129 },
- { 0x900bc, 0x8 },
- { 0x900bd, 0x370 },
- { 0x900be, 0x129 },
- { 0x900bf, 0xa },
- { 0x900c0, 0x3c8 },
- { 0x900c1, 0x1a9 },
- { 0x900c2, 0xc },
- { 0x900c3, 0x408 },
- { 0x900c4, 0x199 },
- { 0x900c5, 0x14 },
- { 0x900c6, 0x790 },
- { 0x900c7, 0x11a },
- { 0x900c8, 0x8 },
- { 0x900c9, 0x4 },
- { 0x900ca, 0x18 },
- { 0x900cb, 0xe },
- { 0x900cc, 0x408 },
- { 0x900cd, 0x199 },
- { 0x900ce, 0x8 },
- { 0x900cf, 0x8568 },
- { 0x900d0, 0x108 },
- { 0x900d1, 0x18 },
- { 0x900d2, 0x790 },
- { 0x900d3, 0x16a },
- { 0x900d4, 0x8 },
- { 0x900d5, 0x1d8 },
- { 0x900d6, 0x169 },
- { 0x900d7, 0x10 },
- { 0x900d8, 0x8558 },
- { 0x900d9, 0x168 },
- { 0x900da, 0x1ff8 },
- { 0x900db, 0x85a8 },
- { 0x900dc, 0x1e8 },
- { 0x900dd, 0x50 },
- { 0x900de, 0x798 },
- { 0x900df, 0x16a },
- { 0x900e0, 0x60 },
- { 0x900e1, 0x7a0 },
- { 0x900e2, 0x16a },
- { 0x900e3, 0x8 },
- { 0x900e4, 0x8310 },
- { 0x900e5, 0x168 },
- { 0x900e6, 0x8 },
- { 0x900e7, 0xa310 },
- { 0x900e8, 0x168 },
- { 0x900e9, 0xa },
- { 0x900ea, 0x408 },
- { 0x900eb, 0x169 },
- { 0x900ec, 0x6e },
- { 0x900ed, 0x0 },
- { 0x900ee, 0x68 },
- { 0x900ef, 0x0 },
- { 0x900f0, 0x408 },
- { 0x900f1, 0x169 },
- { 0x900f2, 0x0 },
- { 0x900f3, 0x8310 },
- { 0x900f4, 0x168 },
- { 0x900f5, 0x0 },
- { 0x900f6, 0xa310 },
- { 0x900f7, 0x168 },
- { 0x900f8, 0x1ff8 },
- { 0x900f9, 0x85a8 },
- { 0x900fa, 0x1e8 },
- { 0x900fb, 0x68 },
- { 0x900fc, 0x798 },
- { 0x900fd, 0x16a },
- { 0x900fe, 0x78 },
- { 0x900ff, 0x7a0 },
- { 0x90100, 0x16a },
- { 0x90101, 0x68 },
- { 0x90102, 0x790 },
- { 0x90103, 0x16a },
- { 0x90104, 0x8 },
- { 0x90105, 0x8b10 },
- { 0x90106, 0x168 },
- { 0x90107, 0x8 },
- { 0x90108, 0xab10 },
- { 0x90109, 0x168 },
- { 0x9010a, 0xa },
- { 0x9010b, 0x408 },
- { 0x9010c, 0x169 },
- { 0x9010d, 0x58 },
- { 0x9010e, 0x0 },
- { 0x9010f, 0x68 },
- { 0x90110, 0x0 },
- { 0x90111, 0x408 },
- { 0x90112, 0x169 },
- { 0x90113, 0x0 },
- { 0x90114, 0x8b10 },
- { 0x90115, 0x168 },
- { 0x90116, 0x1 },
- { 0x90117, 0xab10 },
- { 0x90118, 0x168 },
- { 0x90119, 0x0 },
- { 0x9011a, 0x1d8 },
- { 0x9011b, 0x169 },
- { 0x9011c, 0x80 },
- { 0x9011d, 0x790 },
- { 0x9011e, 0x16a },
- { 0x9011f, 0x18 },
- { 0x90120, 0x7aa },
- { 0x90121, 0x6a },
- { 0x90122, 0xa },
- { 0x90123, 0x0 },
- { 0x90124, 0x1e9 },
- { 0x90125, 0x8 },
- { 0x90126, 0x8080 },
- { 0x90127, 0x108 },
- { 0x90128, 0xf },
- { 0x90129, 0x408 },
- { 0x9012a, 0x169 },
- { 0x9012b, 0xc },
- { 0x9012c, 0x0 },
- { 0x9012d, 0x68 },
- { 0x9012e, 0x9 },
- { 0x9012f, 0x0 },
- { 0x90130, 0x1a9 },
- { 0x90131, 0x0 },
- { 0x90132, 0x408 },
- { 0x90133, 0x169 },
- { 0x90134, 0x0 },
- { 0x90135, 0x8080 },
- { 0x90136, 0x108 },
- { 0x90137, 0x8 },
- { 0x90138, 0x7aa },
- { 0x90139, 0x6a },
- { 0x9013a, 0x0 },
- { 0x9013b, 0x8568 },
- { 0x9013c, 0x108 },
- { 0x9013d, 0xb7 },
- { 0x9013e, 0x790 },
- { 0x9013f, 0x16a },
- { 0x90140, 0x1f },
- { 0x90141, 0x0 },
- { 0x90142, 0x68 },
- { 0x90143, 0x8 },
- { 0x90144, 0x8558 },
- { 0x90145, 0x168 },
- { 0x90146, 0xf },
- { 0x90147, 0x408 },
- { 0x90148, 0x169 },
- { 0x90149, 0xd },
- { 0x9014a, 0x0 },
- { 0x9014b, 0x68 },
- { 0x9014c, 0x0 },
- { 0x9014d, 0x408 },
- { 0x9014e, 0x169 },
- { 0x9014f, 0x0 },
- { 0x90150, 0x8558 },
- { 0x90151, 0x168 },
- { 0x90152, 0x8 },
- { 0x90153, 0x3c8 },
- { 0x90154, 0x1a9 },
- { 0x90155, 0x3 },
- { 0x90156, 0x370 },
- { 0x90157, 0x129 },
- { 0x90158, 0x20 },
- { 0x90159, 0x2aa },
- { 0x9015a, 0x9 },
- { 0x9015b, 0x8 },
- { 0x9015c, 0xe8 },
- { 0x9015d, 0x109 },
- { 0x9015e, 0x0 },
- { 0x9015f, 0x8140 },
- { 0x90160, 0x10c },
- { 0x90161, 0x10 },
- { 0x90162, 0x8138 },
- { 0x90163, 0x104 },
- { 0x90164, 0x8 },
- { 0x90165, 0x448 },
- { 0x90166, 0x109 },
- { 0x90167, 0xf },
- { 0x90168, 0x7c0 },
- { 0x90169, 0x109 },
- { 0x9016a, 0x0 },
- { 0x9016b, 0xe8 },
- { 0x9016c, 0x109 },
- { 0x9016d, 0x47 },
- { 0x9016e, 0x630 },
- { 0x9016f, 0x109 },
- { 0x90170, 0x8 },
- { 0x90171, 0x618 },
- { 0x90172, 0x109 },
- { 0x90173, 0x8 },
- { 0x90174, 0xe0 },
- { 0x90175, 0x109 },
- { 0x90176, 0x0 },
- { 0x90177, 0x7c8 },
- { 0x90178, 0x109 },
- { 0x90179, 0x8 },
- { 0x9017a, 0x8140 },
- { 0x9017b, 0x10c },
- { 0x9017c, 0x0 },
- { 0x9017d, 0x478 },
- { 0x9017e, 0x109 },
- { 0x9017f, 0x0 },
- { 0x90180, 0x1 },
- { 0x90181, 0x8 },
- { 0x90182, 0x8 },
- { 0x90183, 0x4 },
- { 0x90184, 0x0 },
- { 0x90006, 0x8 },
- { 0x90007, 0x7c8 },
- { 0x90008, 0x109 },
- { 0x90009, 0x0 },
- { 0x9000a, 0x400 },
- { 0x9000b, 0x106 },
- { 0xd00e7, 0x400 },
- { 0x90017, 0x0 },
- { 0x9001f, 0x2b },
- { 0x90026, 0x69 },
- { 0x400d0, 0x0 },
- { 0x400d1, 0x101 },
- { 0x400d2, 0x105 },
- { 0x400d3, 0x107 },
- { 0x400d4, 0x10f },
- { 0x400d5, 0x202 },
- { 0x400d6, 0x20a },
- { 0x400d7, 0x20b },
- { 0x2003a, 0x2 },
- { 0x200be, 0x0 },
- { 0x2000b, 0x20c },
- { 0x2000c, 0x74 },
- { 0x2000d, 0x48e },
- { 0x2000e, 0x2c },
- { 0x9000c, 0x0 },
- { 0x9000d, 0x173 },
- { 0x9000e, 0x60 },
- { 0x9000f, 0x6110 },
- { 0x90010, 0x2152 },
- { 0x90011, 0xdfbd },
- { 0x90012, 0x2060 },
- { 0x90013, 0x6152 },
- { 0x20010, 0x5a },
- { 0x20011, 0x3 },
- { 0x40080, 0xe0 },
- { 0x40081, 0x12 },
- { 0x40082, 0xe0 },
- { 0x40083, 0x12 },
- { 0x40084, 0xe0 },
- { 0x40085, 0x12 },
- { 0x400fd, 0xf },
- { 0x400f1, 0xe },
- { 0x10011, 0x1 },
- { 0x10012, 0x1 },
- { 0x10013, 0x180 },
- { 0x10018, 0x1 },
- { 0x10002, 0x6209 },
- { 0x100b2, 0x1 },
- { 0x101b4, 0x1 },
- { 0x102b4, 0x1 },
- { 0x103b4, 0x1 },
- { 0x104b4, 0x1 },
- { 0x105b4, 0x1 },
- { 0x106b4, 0x1 },
- { 0x107b4, 0x1 },
- { 0x108b4, 0x1 },
- { 0x11011, 0x1 },
- { 0x11012, 0x1 },
- { 0x11013, 0x180 },
- { 0x11018, 0x1 },
- { 0x11002, 0x6209 },
- { 0x110b2, 0x1 },
- { 0x111b4, 0x1 },
- { 0x112b4, 0x1 },
- { 0x113b4, 0x1 },
- { 0x114b4, 0x1 },
- { 0x115b4, 0x1 },
- { 0x116b4, 0x1 },
- { 0x117b4, 0x1 },
- { 0x118b4, 0x1 },
- { 0x20089, 0x1 },
- { 0x20088, 0x19 },
- { 0xc0080, 0x0 },
- { 0xd0000, 0x1 }
-};
-
-struct dram_fsp_msg ddr_dram_fsp_msg[] = {
- {
- /* P0 1866mts 1D */
- .drate = 1866,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp0_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
- },
- {
- /* P0 1866mts 2D */
- .drate = 1866,
- .fw_type = FW_2D_IMAGE,
- .fsp_cfg = ddr_fsp0_2d_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
- },
-};
-
-/* ddr timing config params */
-struct dram_timing_info dram_timing = {
- .ddrc_cfg = ddr_ddrc_cfg,
- .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
- .ddrphy_cfg = ddr_ddrphy_cfg,
- .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
- .fsp_msg = ddr_dram_fsp_msg,
- .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
- .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
- .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
- .ddrphy_pie = ddr_phy_pie,
- .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 1866, },
-};
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index e580713..a214c04 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -52,9 +52,16 @@
puts("Normal Boot\n");
}
+extern struct dram_timing_info dram_timing_1866mts;
void spl_dram_init(void)
{
- ddr_init(&dram_timing);
+ struct dram_timing_info *ptiming = &dram_timing;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
+ ptiming = &dram_timing_1866mts;
+
+ printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+ ddr_init(ptiming);
}
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
@@ -62,6 +69,7 @@
{
struct udevice *dev;
int ret;
+ unsigned int val = 0, buck_val;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
@@ -77,20 +85,41 @@
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) {
- /* 0.75v for Low drive mode
- */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8v for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85v for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
} else {
- /* 0.9v for Over drive mode
- */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ buck_val = 0x14; /* 0.9v for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
}
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+ } else {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
+ /* Set VDDQ to 1.1V from buck2 */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
+ }
+
/* set standby voltage to 0.65v */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
@@ -123,9 +152,11 @@
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
+ clock_init_late();
+
power_init_board();
- if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
diff --git a/board/freescale/imxrt1020-evk/Kconfig b/board/freescale/imxrt1020-evk/Kconfig
index 3cb8fb1..6618a9b 100644
--- a/board/freescale/imxrt1020-evk/Kconfig
+++ b/board/freescale/imxrt1020-evk/Kconfig
@@ -1,15 +1,12 @@
if TARGET_IMXRT1020_EVK
config SYS_BOARD
- string
default "imxrt1020-evk"
config SYS_VENDOR
- string
default "freescale"
config SYS_SOC
- string
default "imxrt1020"
config SYS_CONFIG_NAME
diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig
index 068130b..04ade6e 100644
--- a/board/freescale/imxrt1050-evk/Kconfig
+++ b/board/freescale/imxrt1050-evk/Kconfig
@@ -1,15 +1,12 @@
if TARGET_IMXRT1050_EVK
config SYS_BOARD
- string
default "imxrt1050-evk"
config SYS_VENDOR
- string
default "freescale"
config SYS_SOC
- string
default "imxrt1050"
config SYS_CONFIG_NAME
diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig
index b433d6e..ad7cd4a 100644
--- a/board/freescale/imxrt1170-evk/Kconfig
+++ b/board/freescale/imxrt1170-evk/Kconfig
@@ -1,15 +1,12 @@
if TARGET_IMXRT1170_EVK
config SYS_BOARD
- string
default "imxrt1170-evk"
config SYS_VENDOR
- string
default "freescale"
config SYS_SOC
- string
default "imxrt1170"
config SYS_CONFIG_NAME
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 44d9782..7fc4fec 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -12,7 +12,7 @@
int board_eth_init(struct bd_info *bis)
{
-#ifdef CONFIG_PHY_AQUANTIA
+#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_SPL_BUILD)
/*
* Export functions to be used by AQ firmware
* upload application
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 334518a..ab5d2eb 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -72,7 +72,7 @@
}
}
- return ERR_OK;
+ return FL_ERR_OK;
}
void flash_print_info(flash_info_t * info)
@@ -369,9 +369,9 @@
}
if (cnt == 0)
- return ERR_OK;
+ return FL_ERR_OK;
- return ERR_OK;
+ return FL_ERR_OK;
}
/*-----------------------------------------------------------------------
diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c
index c8cbc5a..b32dfc6 100644
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c
@@ -11,6 +11,7 @@
#ifdef CONFIG_PWM_NX
#include <pwm.h>
#endif
+#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -492,12 +493,8 @@
ARRAY_SIZE(splash_locations));
}
- if (!err) {
- char addr[64];
-
- sprintf(addr, "0x%lx", gd->fb_base);
- env_set("fb_addr", addr);
- }
+ if (!err)
+ env_set_hex("fb_addr", video_get_fb());
return err;
}
diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c
index fb3ec48..db9ba88 100644
--- a/board/gardena/smart-gateway-at91sam/spl.c
+++ b/board/gardena/smart-gateway-at91sam/spl.c
@@ -110,7 +110,7 @@
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
diff --git a/board/gardena/smart-gateway-mt7688/board.c b/board/gardena/smart-gateway-mt7688/board.c
index c6b14be..eb7fcd6 100644
--- a/board/gardena/smart-gateway-mt7688/board.c
+++ b/board/gardena/smart-gateway-mt7688/board.c
@@ -16,7 +16,7 @@
#include <linux/delay.h>
#include <linux/stringify.h>
#include <u-boot/crc.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/ctype.h>
#include <linux/io.h>
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index e9cdede..002d7bb 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -366,8 +366,8 @@
{
if (!IS_SD(mmc)) {
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
- case 1:
- case 2:
+ case EMMC_BOOT_PART_BOOT1:
+ case EMMC_BOOT_PART_BOOT2:
if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
raw_sect -= 32 * 2;
break;
@@ -379,16 +379,24 @@
const char *spl_board_loader_name(u32 boot_device)
{
+ static char name[16];
+ struct mmc *mmc;
+
switch (boot_device) {
/* SDHC2 */
case BOOT_DEVICE_MMC1:
- return "eMMC";
+ mmc_init_device(0);
+ mmc = find_mmc_device(0);
+ mmc_init(mmc);
+ snprintf(name, sizeof(name), "eMMC %s", emmc_hwpart_names[EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)]);
+ return name;
/* SDHC3 */
case BOOT_DEVICE_MMC2:
- return "SD card";
- default:
- return NULL;
+ sprintf(name, "SD card");
+ return name;
}
+
+ return NULL;
}
void spl_board_init(void)
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index d4c2212..98b3362 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -157,20 +157,20 @@
int bootpart;
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
- case 1: /* boot0 */
- bootpart = 1;
+ case EMMC_BOOT_PART_BOOT1:
+ bootpart = EMMC_HWPART_BOOT1;
break;
- case 2: /* boot1 */
- bootpart = 2;
+ case EMMC_BOOT_PART_BOOT2:
+ bootpart = EMMC_HWPART_BOOT2;
break;
- case 7: /* user */
+ case EMMC_BOOT_PART_USER:
default:
- bootpart = 0;
+ bootpart = EMMC_HWPART_DEFAULT;
break;
}
/* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
- (bootpart == 1 || bootpart == 2))
+ (bootpart == EMMC_BOOT_PART_BOOT1 || bootpart == EMMC_BOOT_PART_BOOT2))
bootblk = 0;
env_set_hex("bootpart", bootpart);
env_set_hex("bootblk", bootblk);
@@ -201,10 +201,10 @@
{
if (!IS_SD(mmc)) {
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
- case 1:
- return 1;
- case 2:
- return 2;
+ case EMMC_BOOT_PART_BOOT1:
+ return EMMC_HWPART_BOOT1;
+ case EMMC_BOOT_PART_BOOT2:
+ return EMMC_HWPART_BOOT2;
}
}
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index bd8ce63..674f19b 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -57,10 +57,6 @@
if (ret)
return log_msg_ret("s33", ret);
- ret = regulators_enable_boot_on(false);
- if (ret)
- return log_msg_ret("boo", ret);
-
return 0;
}
#endif
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index 8313b37..e0eb8aa 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -80,7 +80,7 @@
enable_board_pin_mux();
}
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
chilisom_spl_board_init();
}
diff --git a/board/kontron/sl-mx6ul/Kconfig b/board/kontron/sl-mx6ul/Kconfig
index 782e099..7a4ffbe 100644
--- a/board/kontron/sl-mx6ul/Kconfig
+++ b/board/kontron/sl-mx6ul/Kconfig
@@ -1,11 +1,9 @@
if TARGET_KONTRON_MX6UL
config SYS_BOARD
- string
default "sl-mx6ul"
config SYS_VENDOR
- string
default "kontron"
config SYS_CONFIG_NAME
diff --git a/board/kontron/sl-mx8mm/Kconfig b/board/kontron/sl-mx8mm/Kconfig
index 1cfe9ee..1597bcf 100644
--- a/board/kontron/sl-mx8mm/Kconfig
+++ b/board/kontron/sl-mx8mm/Kconfig
@@ -1,11 +1,9 @@
if TARGET_KONTRON_MX8MM
config SYS_BOARD
- string
default "sl-mx8mm"
config SYS_VENDOR
- string
default "kontron"
config SYS_CONFIG_NAME
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 3220727..f65551e 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -137,23 +137,23 @@
int misc_init_r(void)
{
struct novena_eeprom_data data;
- uchar *datap = (uchar *)&data;
+ uint8_t *datap = (uint8_t *)&data;
const char *signature = "Novena";
+ struct udevice *eeprom;
int ret;
/* If 'ethaddr' is already set, do nothing. */
if (env_get("ethaddr"))
return 0;
- /* EEPROM is at bus 2. */
- ret = i2c_set_bus_num(2);
+ /* EEPROM is at bus 2, address 0x56 */
+ ret = i2c_get_chip_for_busnum(2, 0x56, 1, &eeprom);
if (ret) {
puts("Cannot select EEPROM I2C bus.\n");
return 0;
}
- /* EEPROM is at address 0x56. */
- ret = eeprom_read(0x56, 0, datap, sizeof(data));
+ ret = dm_i2c_read(eeprom, 0, datap, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
return 0;
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
index be5a737..67f9843 100644
--- a/board/kosagi/novena/video.c
+++ b/board/kosagi/novena/video.c
@@ -58,28 +58,29 @@
#define IT6521_RETRY_MAX 20
+static struct udevice *it6251_chip;
+static struct udevice *it6251_lvds;
+
static int it6251_is_stable(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
- const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
int status;
int clkcnt;
int rpclkcnt;
int refstate;
- rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
- ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+ rpclkcnt = (dm_i2c_reg_read(it6251_chip, 0x13) & 0xff) |
+ ((dm_i2c_reg_read(it6251_chip, 0x14) << 8) & 0x0f00);
debug("RPCLKCnt: %d\n", rpclkcnt);
- status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+ status = dm_i2c_reg_read(it6251_chip, IT6251_SYSTEM_STATUS);
debug("System status: 0x%02x\n", status);
- clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
- ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+ clkcnt = (dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+ ((dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_HIGH) << 8) &
0x0f00);
debug("Clock: 0x%02x\n", clkcnt);
- refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+ refstate = dm_i2c_reg_read(it6251_lvds, IT6251_REF_STATE);
debug("Ref Link State: 0x%02x\n", refstate);
if ((refstate & 0x1f) != 0)
@@ -97,16 +98,14 @@
static int it6251_ready(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
-
/* Test if the IT6251 came out of reset by reading ID regs. */
- if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_LOW) != 0x15)
return 0;
- if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_HIGH) != 0xca)
return 0;
- if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_LOW) != 0x51)
return 0;
- if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_HIGH) != 0x62)
return 0;
return 1;
@@ -114,116 +113,112 @@
static void it6251_program_regs(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
- const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
-
- i2c_reg_write(caddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x05, 0x00);
mdelay(1);
/* set LVDSRX address, and enable */
- i2c_reg_write(caddr, 0xfd, 0xbc);
- i2c_reg_write(caddr, 0xfe, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0xfd, 0xbc);
+ dm_i2c_reg_write(it6251_chip, 0xfe, 0x01);
/*
* LVDSRX
*/
/* This write always fails, because the chip goes into reset */
/* reset LVDSRX */
- i2c_reg_write(laddr, 0x05, 0xff);
- i2c_reg_write(laddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0xff);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
/* reset LVDSRX PLL */
- i2c_reg_write(laddr, 0x3b, 0x42);
- i2c_reg_write(laddr, 0x3b, 0x43);
+ dm_i2c_reg_write(it6251_lvds, 0x3b, 0x42);
+ dm_i2c_reg_write(it6251_lvds, 0x3b, 0x43);
/* something with SSC PLL */
- i2c_reg_write(laddr, 0x3c, 0x08);
+ dm_i2c_reg_write(it6251_lvds, 0x3c, 0x08);
/* don't swap links, but writing reserved registers */
- i2c_reg_write(laddr, 0x0b, 0x88);
+ dm_i2c_reg_write(it6251_lvds, 0x0b, 0x88);
/* JEIDA, 8-bit depth 0x11, orig 0x42 */
- i2c_reg_write(laddr, 0x2c, 0x01);
+ dm_i2c_reg_write(it6251_lvds, 0x2c, 0x01);
/* "reserved" */
- i2c_reg_write(laddr, 0x32, 0x04);
+ dm_i2c_reg_write(it6251_lvds, 0x32, 0x04);
/* "reserved" */
- i2c_reg_write(laddr, 0x35, 0xe0);
+ dm_i2c_reg_write(it6251_lvds, 0x35, 0xe0);
/* "reserved" + clock delay */
- i2c_reg_write(laddr, 0x2b, 0x24);
+ dm_i2c_reg_write(it6251_lvds, 0x2b, 0x24);
/* reset LVDSRX pix clock */
- i2c_reg_write(laddr, 0x05, 0x02);
- i2c_reg_write(laddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x02);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
/*
* DPTX
*/
/* set for two lane mode, normal op, no swapping, no downspread */
- i2c_reg_write(caddr, 0x16, 0x02);
+ dm_i2c_reg_write(it6251_chip, 0x16, 0x02);
/* some AUX channel EDID magic */
- i2c_reg_write(caddr, 0x23, 0x40);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
/* power down lanes 3-0 */
- i2c_reg_write(caddr, 0x5c, 0xf3);
+ dm_i2c_reg_write(it6251_chip, 0x5c, 0xf3);
/* enable DP scrambling, change EQ CR phase */
- i2c_reg_write(caddr, 0x5f, 0x06);
+ dm_i2c_reg_write(it6251_chip, 0x5f, 0x06);
/* color mode RGB, pclk/2 */
- i2c_reg_write(caddr, 0x60, 0x02);
+ dm_i2c_reg_write(it6251_chip, 0x60, 0x02);
/* dual pixel input mode, no EO swap, no RGB swap */
- i2c_reg_write(caddr, 0x61, 0x04);
+ dm_i2c_reg_write(it6251_chip, 0x61, 0x04);
/* M444B24 video format */
- i2c_reg_write(caddr, 0x62, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0x62, 0x01);
/* vesa range / not interlace / vsync high / hsync high */
- i2c_reg_write(caddr, 0xa0, 0x0F);
+ dm_i2c_reg_write(it6251_chip, 0xa0, 0x0F);
/* hpd event timer set to 1.6-ish ms */
- i2c_reg_write(caddr, 0xc9, 0xf5);
+ dm_i2c_reg_write(it6251_chip, 0xc9, 0xf5);
/* more reserved magic */
- i2c_reg_write(caddr, 0xca, 0x4d);
- i2c_reg_write(caddr, 0xcb, 0x37);
+ dm_i2c_reg_write(it6251_chip, 0xca, 0x4d);
+ dm_i2c_reg_write(it6251_chip, 0xcb, 0x37);
/* enhanced framing mode, auto video fifo reset, video mute disable */
- i2c_reg_write(caddr, 0xd3, 0x03);
+ dm_i2c_reg_write(it6251_chip, 0xd3, 0x03);
/* "vidstmp" and some reserved stuff */
- i2c_reg_write(caddr, 0xd4, 0x45);
+ dm_i2c_reg_write(it6251_chip, 0xd4, 0x45);
/* queue number -- reserved */
- i2c_reg_write(caddr, 0xe7, 0xa0);
+ dm_i2c_reg_write(it6251_chip, 0xe7, 0xa0);
/* info frame packets and reserved */
- i2c_reg_write(caddr, 0xe8, 0x33);
+ dm_i2c_reg_write(it6251_chip, 0xe8, 0x33);
/* more AVI stuff */
- i2c_reg_write(caddr, 0xec, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0xec, 0x00);
/* select PC master reg for aux channel? */
- i2c_reg_write(caddr, 0x23, 0x42);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x42);
/* send PC request commands */
- i2c_reg_write(caddr, 0x24, 0x00);
- i2c_reg_write(caddr, 0x25, 0x00);
- i2c_reg_write(caddr, 0x26, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x24, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x25, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x26, 0x00);
/* native aux read */
- i2c_reg_write(caddr, 0x2b, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x2b, 0x00);
/* back to internal */
- i2c_reg_write(caddr, 0x23, 0x40);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
/* voltage swing level 3 */
- i2c_reg_write(caddr, 0x19, 0xff);
+ dm_i2c_reg_write(it6251_chip, 0x19, 0xff);
/* pre-emphasis level 3 */
- i2c_reg_write(caddr, 0x1a, 0xff);
+ dm_i2c_reg_write(it6251_chip, 0x1a, 0xff);
/* start link training */
- i2c_reg_write(caddr, 0x17, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0x17, 0x01);
}
static int it6251_init(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
int reg;
int tries, retries = 0;
@@ -233,7 +228,7 @@
/* Wait for video stable. */
for (tries = 0; tries < 100; tries++) {
- reg = i2c_reg_read(caddr, 0x17);
+ reg = dm_i2c_reg_read(it6251_chip, 0x17);
/* Test Link CFG, STS, LCS read done. */
if ((reg & 0xe0) != 0xe0) {
/* Not yet, wait a bit more. */
@@ -285,10 +280,14 @@
enable_lvds(dev);
- ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
- if (ret) {
- puts("Cannot select IT6251 I2C bus.\n");
- return 0;
+ if (!it6251_chip) {
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_CHIPADDR,
+ 1, &it6251_chip);
+ if (ret) {
+ puts("Cannot select IT6251 I2C bus.\n");
+ return 0;
+ }
}
/* Wait up-to ~250 mS for the LVDS to come up. */
@@ -435,9 +434,20 @@
{
int ret;
+ if (!it6251_chip) {
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_CHIPADDR,
+ 1, &it6251_chip);
+ if (ret) {
+ puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ return;
+ }
+ }
+
- ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_LVDSADDR, 1, &it6251_lvds);
if (ret) {
- puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ puts("Cannot find IT6251 LVDS bus.\n");
return;
}
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 88d5d08..9d0959f 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -14,11 +14,9 @@
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
-#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
-#include <ns16550.h>
#include <twl4030.h>
#include "sniper.h"
@@ -30,18 +28,6 @@
.nand_string = "MMC"
};
-static const struct ns16550_plat serial_omap_plat = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DRVINFO(sniper_serial) = {
- .name = "ns16550_serial",
- .plat = &serial_omap_plat
-};
-
#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET)
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
@@ -77,6 +63,11 @@
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
timings->mr = MICRON_V_MR_165;
}
+
+void spl_board_init(void)
+{
+ twl4030_power_mmc_init(1);
+}
#endif
int board_init(void)
@@ -188,13 +179,3 @@
return omap_reboot_mode_store("b");
}
-
-int board_mmc_init(struct bd_info *bis)
-{
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(1);
-}
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index 1f51921..55e93a7 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -59,17 +59,21 @@
int dram_init_banksize(void)
{
+ phys_size_t ram_size = gd->ram_size;
gd->bd->bi_dram[0].start = 0;
- switch (gd->ram_size) {
+ #if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ram_size += CONFIG_SYS_MEM_TOP_HIDE;
+ #endif
+ switch (ram_size) {
case DRAM_512MB_ECC_SIZE:
case DRAM_512MB_SIZE:
case DRAM_1GB_ECC_SIZE:
case DRAM_1GB_SIZE:
case DRAM_2GB_ECC_SIZE:
case DRAM_2GB_SIZE:
- gd->bd->bi_dram[0].size = gd->ram_size;
+ gd->bd->bi_dram[0].size = ram_size;
gd->bd->bi_dram[1].start = 0;
gd->bd->bi_dram[1].size = 0;
break;
diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 42463ad..670c747 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -9,6 +9,7 @@
F: board/phytec/phycore_am62x/
F: configs/phycore_am62x_a53_defconfig
F: configs/phycore_am62x_r5_defconfig
+F: configs/phycore_am62x_r5_usbdfu_defconfig
F: include/configs/phycore_am62x.h
F: doc/board/phytec/phycore-am62x.rst
F: board/phytec/common/k3
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 046bbd2..711ca30 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -1,5 +1,7 @@
#include <env/ti/k3_dfu.env>
#include <env/phytec/k3_mmc.env>
+#include <env/phytec/k3_net.env>
+#include <env/phytec/k3_spi.env>
fdtaddr=0x88000000
loadaddr=0x82000000
@@ -15,3 +17,9 @@
mmcpart=1
console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x02800000
+
+get_cmd=tftp
+
+spi_fdt_addr=0x700000
+spi_image_addr=0x800000
+spi_ramdisk_addr=0x1e00000
diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env
index 18f0fa5..3032b51 100644
--- a/board/phytec/phycore_am64x/phycore_am64x.env
+++ b/board/phytec/phycore_am64x/phycore_am64x.env
@@ -1,4 +1,6 @@
#include <env/phytec/k3_mmc.env>
+#include <env/phytec/k3_net.env>
+#include <env/phytec/k3_spi.env>
fdtaddr=0x88000000
loadaddr=0x82000000
@@ -14,3 +16,9 @@
mmcpart=1
console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x02800000
+
+get_cmd=tftp
+
+spi_fdt_addr=0x700000
+spi_image_addr=0x800000
+spi_ramdisk_addr=0x1e00000
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index ef95136..bf2d5ce 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -10,10 +10,34 @@
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <init.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
#include <miiphy.h>
+#include <mtd_node.h>
+
+#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ u8 spi = phytec_get_imx8m_spi(NULL);
+ /* Do nothing if no SPI is populated */
+ if (!spi)
+ return 0;
+
+ static const struct node_info nodes[] = {
+ { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
+ };
+
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ return 0;
+}
+
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
@@ -27,6 +51,11 @@
int board_init(void)
{
+ int ret = phytec_eeprom_data_setup_fallback(NULL, 0,
+ EEPROM_ADDR, EEPROM_ADDR_FALLBACK);
+ if (ret)
+ printf("%s: EEPROM data init failed\n", __func__);
+
setup_fec();
return 0;
@@ -39,6 +68,11 @@
int board_late_init(void)
{
+ u8 spi = phytec_get_imx8m_spi(NULL);
+
+ if (spi != 0 && spi != PHYTEC_EEPROM_INVAL)
+ env_set("spiprobe", "sf probe");
+
switch (get_boot_device()) {
case SD2_BOOT:
env_set_ulong("mmcdev", 1);
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index f8f878e..2c12fc6 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -7,6 +7,7 @@
fi;
mmc dev ${mmcdev};
if mmc rescan; then
+ run spiprobe;
if test ${doraucboot} = 1; then
run raucinit;
fi;
@@ -27,10 +28,13 @@
fdtfile=CONFIG_DEFAULT_FDT_FILE
image=Image
ip_dyn=yes
+mtdparts=30bb0000.spi:3840k(u-boot),128k(env),128k(env_redund),-(none)
+mtdids=nor0=30bb0000.spi
+spiprobe=true
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
mmcargs=
- setenv bootargs console=${console}
+ setenv bootargs ${mcore_clk} console=${console}
root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
mmcautodetect=yes
mmcboot=
@@ -51,7 +55,7 @@
mmcpart=1
mmcroot=2
netargs=
- setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+ setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp
nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=
echo Booting from net ...;
@@ -74,4 +78,5 @@
echo WARN: Cannot load the DT;
fi;
nfsroot=/srv/nfs
+prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted
sd_dev=1
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 5efa38a..17a8736 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -130,7 +130,7 @@
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
- clock_init();
+ clock_init_late();
power_init_board();
diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c
index a3c4215..8ca8792 100644
--- a/board/purism/librem5/librem5.c
+++ b/board/purism/librem5/librem5.c
@@ -42,8 +42,8 @@
{
uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 7)
- part = 0;
+ if (part == EMMC_BOOT_PART_USER)
+ part = EMMC_HWPART_DEFAULT;
return part;
}
#endif
diff --git a/board/qualcomm/debug-sdm845.config b/board/qualcomm/debug-sdm845.config
new file mode 100644
index 0000000..31ad6d0
--- /dev/null
+++ b/board/qualcomm/debug-sdm845.config
@@ -0,0 +1,5 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0xa84000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=7372800
diff --git a/board/qualcomm/debug-sm6115.config b/board/qualcomm/debug-sm6115.config
new file mode 100644
index 0000000..131c6e2
--- /dev/null
+++ b/board/qualcomm/debug-sm6115.config
@@ -0,0 +1,5 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x4a90000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=14745600
diff --git a/board/qualcomm/debug-sm8250.config b/board/qualcomm/debug-sm8250.config
new file mode 100644
index 0000000..4d3cc4c
--- /dev/null
+++ b/board/qualcomm/debug-sm8250.config
@@ -0,0 +1,5 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0xa90000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=14745600
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 1de1bd6..8125f06 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -9,6 +9,7 @@
#include <config.h>
#include <init.h>
+#include <video.h>
#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
@@ -110,11 +111,12 @@
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
+ ulong fb_base = video_get_fb();
char *ss;
printf ("Board : Ronetix PM9263\n");
- switch (gd->fb_base) {
+ switch (fb_base) {
case PHYS_PSRAM:
ss = "(PSRAM)";
break;
@@ -127,7 +129,7 @@
ss = "";
break;
}
- printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+ printf("Video memory : 0x%08lX %s\n", fb_base, ss);
printf ("\n");
return 0;
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 56862bc..68edd1e 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -88,10 +88,6 @@
if (ret == -ENODEV)
return 0;
- ret = regulators_enable_boot_on(false);
- if (ret)
- return ret;
-
ret = exynos_set_regulator("vdd_mif", 1100000);
if (ret)
return ret;
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 8025965..d97945e 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -32,34 +32,18 @@
gd_t *gd;
#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
-/* GUIDs for capsule updatable firmware images */
-#define SANDBOX_UBOOT_IMAGE_GUID \
- EFI_GUID(0x09d7cf52, 0x0720, 0x4710, 0x91, 0xd1, \
- 0x08, 0x46, 0x9b, 0x7f, 0xe9, 0xc8)
-
-#define SANDBOX_UBOOT_ENV_IMAGE_GUID \
- EFI_GUID(0x5a7021f5, 0xfef2, 0x48b4, 0xaa, 0xba, \
- 0x83, 0x2e, 0x77, 0x74, 0x18, 0xc0)
-
-#define SANDBOX_FIT_IMAGE_GUID \
- EFI_GUID(0x3673b45d, 0x6a7c, 0x46f3, 0x9e, 0x60, \
- 0xad, 0xab, 0xb0, 0x3f, 0x79, 0x37)
-
struct efi_fw_image fw_images[] = {
#if defined(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)
{
- .image_type_id = SANDBOX_UBOOT_IMAGE_GUID,
.fw_name = u"SANDBOX-UBOOT",
.image_index = 1,
},
{
- .image_type_id = SANDBOX_UBOOT_ENV_IMAGE_GUID,
.fw_name = u"SANDBOX-UBOOT-ENV",
.image_index = 2,
},
#elif defined(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)
{
- .image_type_id = SANDBOX_FIT_IMAGE_GUID,
.fw_name = u"SANDBOX-FIT",
.image_index = 1,
},
diff --git a/board/sielaff/imx6dl-sielaff/Kconfig b/board/sielaff/imx6dl-sielaff/Kconfig
index 7876ab1..cad15ac 100644
--- a/board/sielaff/imx6dl-sielaff/Kconfig
+++ b/board/sielaff/imx6dl-sielaff/Kconfig
@@ -1,11 +1,9 @@
if TARGET_MX6S_SIELAFF
config SYS_BOARD
- string
default "imx6dl-sielaff"
config SYS_VENDOR
- string
default "sielaff"
config SYS_CONFIG_NAME
diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c
index 2a72760..e6537b0 100644
--- a/board/siemens/common/board_am335x.c
+++ b/board/siemens/common/board_am335x.c
@@ -36,7 +36,7 @@
/* enable early the console */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
siemens_ee_setup();
if (draco_read_eeprom() < 0)
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 7d73d1f..cd27fc1 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -187,7 +187,7 @@
2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
-void mem_init(void)
+void at91_mem_init(void)
{
struct atmel_mpddrc_config ddr2;
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index 946fbc3..e9e4bc3 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -238,7 +238,7 @@
| AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
| AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
-void mem_init(void)
+void at91_mem_init(void)
{
struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index bda12a9..3764ab4 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -177,7 +177,7 @@
sdramc_initialize(ATMEL_BASE_CS1, &setting);
}
-void mem_init(void)
+void at91_mem_init(void)
{
unsigned int ram_size = 0;
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 6e6e276..5e5a45e 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -15,7 +15,7 @@
#include <env.h>
#include <init.h>
#include <pci.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index a0dbf97..bd430cf 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -18,7 +18,6 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <env.h>
#include <linux/bitops.h>
@@ -27,7 +26,6 @@
#include <config.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
-#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
@@ -53,10 +51,6 @@
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
PAD_CTL_SRE_FAST)
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm)
-
#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
@@ -120,21 +114,6 @@
return ret;
}
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-
static struct pmic *pfuze_init(unsigned char i2cbus)
{
struct pmic *p;
@@ -400,10 +379,6 @@
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
return board_net_init();
}
diff --git a/board/st/stih410-b2260/Kconfig b/board/st/stih410-b2260/Kconfig
index 441a83c..2dd7411 100644
--- a/board/st/stih410-b2260/Kconfig
+++ b/board/st/stih410-b2260/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STIH410_B2260
config SYS_BOARD
- string
default "stih410-b2260"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stih410"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32f429-discovery/Kconfig b/board/st/stm32f429-discovery/Kconfig
index 3c93df2..cde6900 100644
--- a/board/st/stm32f429-discovery/Kconfig
+++ b/board/st/stm32f429-discovery/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32F429_DISCOVERY
config SYS_BOARD
- string
default "stm32f429-discovery"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32f4"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32f429-evaluation/Kconfig b/board/st/stm32f429-evaluation/Kconfig
index eaa40db..b168bf8 100644
--- a/board/st/stm32f429-evaluation/Kconfig
+++ b/board/st/stm32f429-evaluation/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32F429_EVALUATION
config SYS_BOARD
- string
default "stm32f429-evaluation"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32f4"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32f469-discovery/Kconfig b/board/st/stm32f469-discovery/Kconfig
index 622a8d8..688523b 100644
--- a/board/st/stm32f469-discovery/Kconfig
+++ b/board/st/stm32f469-discovery/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32F469_DISCOVERY
config SYS_BOARD
- string
default "stm32f469-discovery"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32f4"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig
index 86ace17..382b86e 100644
--- a/board/st/stm32f746-disco/Kconfig
+++ b/board/st/stm32f746-disco/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32F746_DISCO
config SYS_BOARD
- string
default "stm32f746-disco"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32f7"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32h743-disco/Kconfig b/board/st/stm32h743-disco/Kconfig
index bc116bc..0f0f56e 100644
--- a/board/st/stm32h743-disco/Kconfig
+++ b/board/st/stm32h743-disco/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32H743_DISCO
config SYS_BOARD
- string
default "stm32h743-disco"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32h7"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32h743-eval/Kconfig b/board/st/stm32h743-eval/Kconfig
index ff86de2..0fffa88 100644
--- a/board/st/stm32h743-eval/Kconfig
+++ b/board/st/stm32h743-eval/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32H743_EVAL
config SYS_BOARD
- string
default "stm32h743-eval"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32h7"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32h750-art-pi/Kconfig b/board/st/stm32h750-art-pi/Kconfig
index ab2d0f2..6bd6a13 100644
--- a/board/st/stm32h750-art-pi/Kconfig
+++ b/board/st/stm32h750-art-pi/Kconfig
@@ -1,15 +1,12 @@
if TARGET_STM32H750_ART_PI
config SYS_BOARD
- string
default "stm32h750-art-pi"
config SYS_VENDOR
- string
default "st"
config SYS_SOC
- string
default "stm32h7"
config SYS_CONFIG_NAME
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 97532a8..d5e5e77 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -665,8 +665,6 @@
if (board_is_stm32mp15x_dk2())
board_stm32mp15x_dk2_init();
- regulators_enable_boot_on(_DEBUG);
-
/*
* sysconf initialisation done only when U-Boot is running in secure
* done in TF-A for TFABOOT.
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index b794b73..f55c6b5 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -170,23 +170,32 @@
{
const char *compat;
const char *model;
+ int compat_size;
spl_fdt_fixup_mars(fdt);
if (!get_mmc_size_from_eeprom()) {
int offset;
+ static const char
+ compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110";
model = "Milk-V Mars CM Lite";
- compat = "milkv,mars-cm-lite\0starfive,jh7110";
+ compat = compat_cm_lite;
+ compat_size = sizeof(compat_cm_lite);
offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
/* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
} else {
+ static const char
+ compat_cm[] = "milkv,mars-cm\0starfive,jh7110";
+
model = "Milk-V Mars CM";
- compat = "milkv,mars-cm\0starfive,jh7110";
+ compat = compat_cm;
+ compat_size = sizeof(compat_cm);
}
- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"),
+ "compatible", compat, compat_size);
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
}
diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index 910feed..c9513dd 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -105,8 +105,8 @@
{
uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 7)
- part = 0;
+ if (part == EMMC_BOOT_PART_USER)
+ part = EMMC_HWPART_DEFAULT;
return part;
}
diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig
index e13ee8f..b5c81dd 100644
--- a/board/sysam/amcore/Kconfig
+++ b/board/sysam/amcore/Kconfig
@@ -1,15 +1,12 @@
if TARGET_AMCORE
config SYS_CPU
- string
default "mcf530x"
config SYS_BOARD
- string
default "amcore"
config SYS_VENDOR
- string
default "sysam"
config SYS_CONFIG_NAME
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 484b4e2..6c60c70 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -92,7 +92,7 @@
const struct dpll_params dpll_ddr_sl50 = {
400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int mpu_vdd;
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
index 562a5c6..d7dfeff 100644
--- a/board/ti/am62x/MAINTAINERS
+++ b/board/ti/am62x/MAINTAINERS
@@ -6,5 +6,7 @@
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
+F: configs/am62x_evm_r5_ethboot_defconfig
+F: configs/am62x_evm_a53_ethboot_defconfig
F: configs/am62x_lpsk_r5_defconfig
F: configs/am62x_lpsk_a53_defconfig
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 72d67d9..570bf2a 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -290,6 +290,14 @@
return 0;
}
+void reset_cpu(void)
+{
+ sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
+
+ do {
+ } while (1);
+}
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c
index 445ce98..40369f0 100644
--- a/board/tq/tqma6/tqma6.c
+++ b/board/tq/tqma6/tqma6.c
@@ -19,33 +19,15 @@
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/mach-imx/spi.h>
-#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
-#include <spi_flash.h>
#include "tqma6_bb.h"
DECLARE_GLOBAL_DATA_PTR;
-#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -55,114 +37,6 @@
static const uint16_t tqma6_emmc_dsr = 0x0100;
-#ifndef CONFIG_DM_MMC
-/* eMMC on USDHCI3 always present */
-static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
- NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
- /* eMMC reset */
- NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
-};
-
-/*
- * According to board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 eMMC (SD3) on TQMa6
- * mmc1 .. n optional slots used on baseboard
- */
-struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
- .esdhc_base = USDHC3_BASE_ADDR,
- .max_bus_width = 8,
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC3_BASE_ADDR)
- /* eMMC/uSDHC3 is always present */
- ret = 1;
- else
- ret = tqma6_bb_board_mmc_getcd(mmc);
-
- return ret;
-}
-
-int board_mmc_getwp(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC3_BASE_ADDR)
- /* eMMC/uSDHC3 is always present */
- ret = 0;
- else
- ret = tqma6_bb_board_mmc_getwp(mmc);
-
- return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
- ARRAY_SIZE(tqma6_usdhc3_pads));
- tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
- puts("Warning: failed to initialize eMMC dev\n");
- } else {
- struct mmc *mmc = find_mmc_device(0);
- if (mmc)
- mmc_set_dsr(mmc, tqma6_emmc_dsr);
- }
-
- tqma6_bb_board_mmc_init(bis);
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_DM_SPI
-static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
- /* SS1 */
- NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
-};
-
-#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
-
-static unsigned const tqma6_ecspi1_cs[] = {
- TQMA6_SF_CS_GPIO,
-};
-
-__weak void tqma6_iomuxc_spi(void)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
- gpio_direction_output(tqma6_ecspi1_cs[i], 1);
- imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
- ARRAY_SIZE(tqma6_ecspi1_pads));
-}
-
-#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return ((bus == CONFIG_SF_DEFAULT_BUS) &&
- (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
-}
-#endif
-#endif
int board_early_init_f(void)
{
diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c
index 877539e..b8f7659 100644
--- a/board/tq/tqma6/tqma6_mba6.c
+++ b/board/tq/tqma6/tqma6_mba6.c
@@ -31,28 +31,6 @@
#include "tqma6_bb.h"
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
#if defined(CONFIG_TQMA6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
@@ -89,17 +67,6 @@
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
}
-static iomux_v3_cfg_t const mba6_uart2_pads[] = {
- NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
-};
-
-static void mba6_setup_iomuxc_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
- ARRAY_SIZE(mba6_uart2_pads));
-}
-
int board_mmc_get_env_dev(int devno)
{
/*
@@ -159,8 +126,6 @@
int tqma6_bb_board_early_init_f(void)
{
- mba6_setup_iomuxc_uart();
-
return 0;
}
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index cea25f8..f54f183 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -177,7 +177,7 @@
const struct dpll_params dpll_ddr_baltos = {
400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int sil_rev, mpu_vdd;
int freq;
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 0b43407..5e5eb49 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -12,7 +12,6 @@
#include <image.h>
#include <init.h>
#include <jffs2/load_kernel.h>
-#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/sections.h>
@@ -31,7 +30,7 @@
#include <soc.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include "fru.h"
@@ -426,28 +425,25 @@
struct xilinx_board_description *desc;
phys_size_t bootm_size = gd->ram_top - gd->ram_base;
u64 bootscr_flash_offset, bootscr_flash_size;
+ ulong scriptaddr;
+ u64 bootscr_address;
+ u64 bootscr_offset;
- if (!IS_ENABLED(CONFIG_MICROBLAZE)) {
- ulong scriptaddr;
- u64 bootscr_address;
- u64 bootscr_offset;
-
- /* Fetch bootscr_address/bootscr_offset from DT and update */
- if (!ofnode_read_bootscript_address(&bootscr_address,
- &bootscr_offset)) {
- if (bootscr_offset)
- ret |= env_set_hex("scriptaddr",
- gd->ram_base +
- bootscr_offset);
- else
- ret |= env_set_hex("scriptaddr",
- bootscr_address);
- } else {
- /* Update scriptaddr(bootscr offset) from env */
- scriptaddr = env_get_hex("scriptaddr", 0);
+ /* Fetch bootscr_address/bootscr_offset from DT and update */
+ if (!ofnode_read_bootscript_address(&bootscr_address,
+ &bootscr_offset)) {
+ if (bootscr_offset)
ret |= env_set_hex("scriptaddr",
- gd->ram_base + scriptaddr);
- }
+ gd->ram_base +
+ bootscr_offset);
+ else
+ ret |= env_set_hex("scriptaddr",
+ bootscr_address);
+ } else {
+ /* Update scriptaddr(bootscr offset) from env */
+ scriptaddr = env_get_hex("scriptaddr", 0);
+ ret |= env_set_hex("scriptaddr",
+ gd->ram_base + scriptaddr);
}
if (!ofnode_read_bootscript_flash(&bootscr_flash_offset,
@@ -665,38 +661,6 @@
}
#endif
-#if defined(CONFIG_LMB)
-
-#ifndef MMU_SECTION_SIZE
-#define MMU_SECTION_SIZE (1 * 1024 * 1024)
-#endif
-
-phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
-{
- phys_size_t size;
- phys_addr_t reg;
- struct lmb lmb;
-
- if (!total_size)
- return gd->ram_top;
-
- if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
- panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
-
- /* found enough not-reserved memory to relocated U-Boot */
- lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, gd->ram_size);
- boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
- size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
- reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
-
- if (!reg)
- reg = gd->ram_top - size;
-
- return reg + size;
-}
-#endif
-
#ifdef CONFIG_OF_BOARD_SETUP
#define MAX_RAND_SIZE 8
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 1d67e3f..4d5913c 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -12,6 +12,7 @@
#include <env_internal.h>
#include <log.h>
#include <malloc.h>
+#include <spi.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/global_data.h>
@@ -196,7 +197,6 @@
int spi_get_env_dev(void)
{
struct udevice *dev;
- const char *mode = NULL;
int bootseq = -1;
switch (versal_net_get_bootmode()) {
@@ -207,7 +207,6 @@
debug("QSPI driver for QSPI device is not present\n");
break;
}
- mode = "xspi";
bootseq = dev_seq(dev);
break;
case QSPI_MODE_32BIT:
@@ -217,7 +216,6 @@
debug("QSPI driver for QSPI device is not present\n");
break;
}
- mode = "xspi";
bootseq = dev_seq(dev);
break;
case OSPI_MODE:
@@ -227,7 +225,6 @@
debug("OSPI driver for OSPI device is not present\n");
break;
}
- mode = "xspi";
bootseq = dev_seq(dev);
break;
default:
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index e6331c0..20a675c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -72,6 +72,14 @@
writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
+ /* Disable secure access for boot devices */
+ writel(0x04920492, ZYNQMP_IOU_SECURE_SLCR);
+ writel(0x00920492, ZYNQMP_IOU_SECURE_SLCR + 4);
+
+ /* Enable CCI PMU events */
+ writel(ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN,
+ ZYNQMP_CCI_REG_CCI_MISC_CTRL);
+
/* Delay is required for clocks to be propagated */
udelay(1000000);
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 49ef3e7..d0e431e 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -49,9 +49,19 @@
som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; fi;"
som_mmc_boot=setenv boot_targets mmc0 && run distro_bootcmd
+# To disable bootmenu set enable_bootmenu=0
+enable_bootmenu=1
+check_cc_for_default_boot=if test ${card1_name} = SCK-KV-G || test ${card1_name} = SCK-KR-G || test ${card1_name} = SCK-KD-G; then setenv bootmenu_default 1; else setenv bootmenu_default 0; fi
+som_bootmenu=if test ${enable_bootmenu} = 1; then run check_cc_for_default_boot; bootmenu; else run som_mmc_boot; fi
+
k26_starter=SMK-K26-XCL2G
k24_starter=SMK-K24-XCL2G
-bootcmd=setenv model $board_name && if setexpr model gsub .*$k24_starter* $k24_starter || setexpr model gsub .*$k26_starter* $k26_starter; then run som_cc_boot; else run som_mmc_boot; run som_cc_boot; fi
+bootcmd=setenv model $board_name; setexpr model gsub ".*${k24_starter}.*" starter; setexpr model gsub ".*${k26_starter}.*" starter; if test ${model} = "starter"; then run som_cc_boot; else run som_bootmenu; fi
+
+# Boot menu
+bootmenu_0=eMMC Boot=run som_mmc_boot
+bootmenu_1=SD Boot=run som_cc_boot
+bootmenu_delay=5
usb_hub_init=mw 1000 0056 && sleep 1 && i2c write 1000 2d aa 2 -s
diff --git a/boot/Kconfig b/boot/Kconfig
index 940389d..925afe0 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1,5 +1,7 @@
menu "Boot options"
+source "lib/efi_loader/Kconfig"
+
menu "Boot images"
config ANDROID_BOOT_IMAGE
@@ -745,6 +747,76 @@
This provides a way to try out standard boot on an existing boot flow.
It is not enabled by default to save space.
+config UPL
+ bool "upl - Universal Payload Specification"
+ imply CMD_UPL
+ imply UPL_READ
+ imply UPL_WRITE
+ imply SPL_UPL if SPL
+ help
+ Provides support for UPL payloads and handoff information. U-Boot
+ supports generating and accepting handoff information. The mkimage
+ tool will eventually support creating payloads.
+
+if UPL
+
+config UPL_READ
+ bool "upl - Support reading a Universal Payload handoff"
+ help
+ Provides support for decoding a UPL-format payload into a C structure
+ which can be used elsewhere in U-Boot. This is just the reading
+ implementation, useful for trying it out. See UPL_IN for how
+ to tell U-Boot to actually read it on startup and use it for memory
+ and device information, etc.
+
+config UPL_WRITE
+ bool "upl - Support writing a Universal Payload handoff"
+ help
+ Provides support for encoding a UPL-format payload from a C structure
+ so it can be passed to another program. This is just the writing
+ implementation, useful for trying it out. See SPL_UPL_OUT
+ for how to tell U-Boot SPL to actually write it before jumping to
+ the next phase.
+
+config UPL_IN
+ bool "upl - Read the UPL handoff on startup"
+ select UPL_READ
+ help
+ Read an SPL handoff when U-Boot starts and use it to provide
+ devices, memory layout, etc. required by U-Boot. This allows U-Boot
+ to function as a payload in the meaning of the specification.
+
+if SPL
+
+config SPL_UPL
+ bool "Write a UPL handoff in SPL"
+ imply SPL_UPL_OUT
+ help
+ This tells SPL to write a UPL handoff and pass it to the next phase
+ (e.g. to U-Boot or another program which SPL loads and runs). THis
+ provides information to help that program run correctly and
+ efficiently on the machine.
+
+config SPL_UPL_WRITE
+ bool # upl - Support writing a Universal Payload handoff in SPL
+ select SPL_BLOBLIST
+ help
+ Provides support for encoding a UPL-format payload from a C structure
+ so it can be passed to another program. This is just the writing
+ implementation, useful for trying it out.
+
+config SPL_UPL_OUT
+ bool "upl - Support writing a Universal Payload handoff in SPL"
+ select SPL_UPL_WRITE
+ help
+ Provides support for encoding a UPL-format payload and passing it to
+ the next firmware phase. This allows U-Boot SPL to function as
+ Platform Init in the meaning of the specification.
+
+endif # SPL
+
+endif # UPL
+
endif # BOOTSTD
config LEGACY_IMAGE_FORMAT
diff --git a/boot/Makefile b/boot/Makefile
index dff6f99..f4675d6 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -43,6 +43,10 @@
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_$(SPL_TPL_)FDT_SIMPLEFB) += fdt_simplefb.o
+obj-$(CONFIG_$(SPL_TPL_)UPL) += upl_common.o
+obj-$(CONFIG_$(SPL_TPL_)UPL_READ) += upl_read.o
+obj-$(CONFIG_$(SPL_TPL_)UPL_WRITE) += upl_write.o
+
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
diff --git a/boot/android_ab.c b/boot/android_ab.c
index 143f373..1196a18 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -139,8 +139,13 @@
{
ulong abc_offset, abc_blocks, ret;
- abc_offset = offset +
- offsetof(struct bootloader_message_ab, slot_suffix) /
+ if (offset % part_info->blksz) {
+ log_err("ANDROID: offset not block aligned\n");
+ return -EINVAL;
+ }
+
+ abc_offset = (offset +
+ offsetof(struct bootloader_message_ab, slot_suffix)) /
part_info->blksz;
abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control),
part_info->blksz);
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index 7c7bba0..807f8df 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -632,7 +632,7 @@
int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp)
{
- struct udevice *dev = *devp, *last_dev = NULL;
+ struct udevice *dev = *devp;
bool found;
int ret;
@@ -640,6 +640,7 @@
*devp = NULL;
log_debug("next prio %d: dev=%p/%s\n", iter->cur_prio, dev,
dev ? dev->name : "none");
+ found = false;
do {
/*
* Don't probe devices here since they may not be of the
@@ -682,23 +683,13 @@
}
} else {
ret = device_probe(dev);
- if (!ret)
- last_dev = dev;
- if (ret) {
- log_warning("Device '%s' failed to probe\n",
+ if (ret)
+ log_debug("Device '%s' failed to probe\n",
dev->name);
- if (last_dev == dev) {
- /*
- * We have already tried this device
- * and it failed to probe. Give up.
- */
- return log_msg_ret("probe", ret);
- }
- last_dev = dev;
- dev = NULL;
- }
+ else
+ found = true;
}
- } while (!dev);
+ } while (!found);
*devp = dev;
diff --git a/boot/bootm.c b/boot/bootm.c
index 480f8e6..16a43d5 100644
--- a/boot/bootm.c
+++ b/boot/bootm.c
@@ -239,30 +239,11 @@
return 0;
}
-#ifdef CONFIG_LMB
-static void boot_start_lmb(struct bootm_headers *images)
-{
- phys_addr_t mem_start;
- phys_size_t mem_size;
-
- mem_start = env_get_bootm_low();
- mem_size = env_get_bootm_size();
-
- lmb_init_and_reserve_range(&images->lmb, mem_start,
- mem_size, NULL);
-}
-#else
-#define lmb_reserve(lmb, base, size)
-static inline void boot_start_lmb(struct bootm_headers *images) { }
-#endif
-
static int bootm_start(void)
{
memset((void *)&images, 0, sizeof(images));
images.verify = env_get_yesno("verify");
- boot_start_lmb(&images);
-
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start");
images.state = BOOTM_STATE_START;
@@ -640,7 +621,7 @@
if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) {
ulong req_size = ALIGN(image_len * 4, SZ_1M);
- load = lmb_alloc(&images->lmb, req_size, SZ_2M);
+ load = lmb_alloc(req_size, SZ_2M);
if (!load)
return 1;
os.load = load;
@@ -703,7 +684,7 @@
/* Handle BOOTM_STATE_LOADOS */
if (relocated_addr != load) {
- printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n",
+ printf("Moving Image from 0x%lx to 0x%lx, end=0x%lx\n",
load, relocated_addr,
relocated_addr + image_size);
memmove((void *)relocated_addr, load_buf, image_size);
@@ -714,8 +695,9 @@
images->os.end = relocated_addr + image_size;
}
- lmb_reserve(&images->lmb, images->os.load, (load_end -
- images->os.load));
+ if (CONFIG_IS_ENABLED(LMB))
+ lmb_reserve(images->os.load, (load_end - images->os.load));
+
return 0;
}
@@ -1029,19 +1011,19 @@
if (!ret && (states & BOOTM_STATE_RAMDISK)) {
ulong rd_len = images->rd_end - images->rd_start;
- ret = boot_ramdisk_high(&images->lmb, images->rd_start,
- rd_len, &images->initrd_start, &images->initrd_end);
+ ret = boot_ramdisk_high(images->rd_start, rd_len,
+ &images->initrd_start,
+ &images->initrd_end);
if (!ret) {
env_set_hex("initrd_start", images->initrd_start);
env_set_hex("initrd_end", images->initrd_end);
}
}
#endif
-#if CONFIG_IS_ENABLED(OF_LIBFDT) && defined(CONFIG_LMB)
+#if CONFIG_IS_ENABLED(OF_LIBFDT) && CONFIG_IS_ENABLED(LMB)
if (!ret && (states & BOOTM_STATE_FDT)) {
- boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
- ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
- &images->ft_len);
+ boot_fdt_add_mem_rsv_regions(images->ft_addr);
+ ret = boot_relocate_fdt(&images->ft_addr, &images->ft_len);
}
#endif
diff --git a/boot/bootm_os.c b/boot/bootm_os.c
index 6a66217..e9522cd 100644
--- a/boot/bootm_os.c
+++ b/boot/bootm_os.c
@@ -260,12 +260,11 @@
char *bootline;
ulong of_size = images->ft_len;
char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = &images->lmb;
if (*of_flat_tree) {
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+ boot_fdt_add_mem_rsv_regions(*of_flat_tree);
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ ret = boot_relocate_fdt(of_flat_tree, &of_size);
if (ret)
return;
diff --git a/boot/image-board.c b/boot/image-board.c
index eca1b1d..1757e58 100644
--- a/boot/image-board.c
+++ b/boot/image-board.c
@@ -517,7 +517,6 @@
/**
* boot_ramdisk_high - relocate init ramdisk
- * @lmb: pointer to lmb handle, will be used for memory mgmt
* @rd_data: ramdisk data start address
* @rd_len: ramdisk data length
* @initrd_start: pointer to a ulong variable, will hold final init ramdisk
@@ -536,8 +535,8 @@
* 0 - success
* -1 - failure
*/
-int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
- ulong *initrd_start, ulong *initrd_end)
+int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start,
+ ulong *initrd_end)
{
char *s;
phys_addr_t initrd_high;
@@ -563,13 +562,14 @@
debug(" in-place initrd\n");
*initrd_start = rd_data;
*initrd_end = rd_data + rd_len;
- lmb_reserve(lmb, rd_data, rd_len);
+ lmb_reserve(rd_data, rd_len);
} else {
if (initrd_high)
- *initrd_start = (ulong)lmb_alloc_base(lmb,
- rd_len, 0x1000, initrd_high);
+ *initrd_start = (ulong)lmb_alloc_base(rd_len,
+ 0x1000,
+ initrd_high);
else
- *initrd_start = (ulong)lmb_alloc(lmb, rd_len,
+ *initrd_start = (ulong)lmb_alloc(rd_len,
0x1000);
if (*initrd_start == 0) {
@@ -802,7 +802,6 @@
/**
* boot_get_cmdline - allocate and initialize kernel cmdline
- * @lmb: pointer to lmb handle, will be used for memory mgmt
* @cmd_start: pointer to a ulong variable, will hold cmdline start
* @cmd_end: pointer to a ulong variable, will hold cmdline end
*
@@ -815,7 +814,7 @@
* 0 - success
* -1 - failure
*/
-int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end)
+int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end)
{
int barg;
char *cmdline;
@@ -829,7 +828,7 @@
return 0;
barg = IF_ENABLED_INT(CONFIG_SYS_BOOT_GET_CMDLINE, CONFIG_SYS_BARGSIZE);
- cmdline = (char *)(ulong)lmb_alloc_base(lmb, barg, 0xf,
+ cmdline = (char *)(ulong)lmb_alloc_base(barg, 0xf,
env_get_bootm_mapsize() + env_get_bootm_low());
if (!cmdline)
return -1;
@@ -850,7 +849,6 @@
/**
* boot_get_kbd - allocate and initialize kernel copy of board info
- * @lmb: pointer to lmb handle, will be used for memory mgmt
* @kbd: double pointer to board info data
*
* boot_get_kbd() allocates space for kernel copy of board info data below
@@ -861,10 +859,9 @@
* 0 - success
* -1 - failure
*/
-int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
+int boot_get_kbd(struct bd_info **kbd)
{
- *kbd = (struct bd_info *)(ulong)lmb_alloc_base(lmb,
- sizeof(struct bd_info),
+ *kbd = (struct bd_info *)(ulong)lmb_alloc_base(sizeof(struct bd_info),
0xf,
env_get_bootm_mapsize() +
env_get_bootm_low());
@@ -885,17 +882,16 @@
{
ulong of_size = images->ft_len;
char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = images_lmb(images);
int ret;
/* This function cannot be called without lmb support */
- if (!IS_ENABLED(CONFIG_LMB))
+ if (!CONFIG_IS_ENABLED(LMB))
return -EFAULT;
if (CONFIG_IS_ENABLED(OF_LIBFDT))
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+ boot_fdt_add_mem_rsv_regions(*of_flat_tree);
if (IS_ENABLED(CONFIG_SYS_BOOT_GET_CMDLINE)) {
- ret = boot_get_cmdline(lmb, &images->cmdline_start,
+ ret = boot_get_cmdline(&images->cmdline_start,
&images->cmdline_end);
if (ret) {
puts("ERROR with allocation of cmdline\n");
@@ -904,13 +900,13 @@
}
if (CONFIG_IS_ENABLED(OF_LIBFDT)) {
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ ret = boot_relocate_fdt(of_flat_tree, &of_size);
if (ret)
return ret;
}
if (CONFIG_IS_ENABLED(OF_LIBFDT) && of_size) {
- ret = image_setup_libfdt(images, *of_flat_tree, lmb);
+ ret = image_setup_libfdt(images, *of_flat_tree, true);
if (ret)
return ret;
}
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 8332792..8eda521 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -68,12 +68,11 @@
}
#endif
-static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr,
- uint64_t size, enum lmb_flags flags)
+static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags)
{
long ret;
- ret = lmb_reserve_flags(lmb, addr, size, flags);
+ ret = lmb_reserve_flags(addr, size, flags);
if (ret >= 0) {
debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
(unsigned long long)addr,
@@ -89,14 +88,13 @@
/**
* boot_fdt_add_mem_rsv_regions - Mark the memreserve and reserved-memory
* sections as unusable
- * @lmb: pointer to lmb handle, will be used for memory mgmt
* @fdt_blob: pointer to fdt blob base address
*
* Adds the and reserved-memorymemreserve regions in the dtb to the lmb block.
* Adding the memreserve regions prevents u-boot from using them to store the
* initrd or the fdt blob.
*/
-void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
+void boot_fdt_add_mem_rsv_regions(void *fdt_blob)
{
uint64_t addr, size;
int i, total, ret;
@@ -112,7 +110,7 @@
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- boot_fdt_reserve_region(lmb, addr, size, LMB_NONE);
+ boot_fdt_reserve_region(addr, size, LMB_NONE);
}
/* process reserved-memory */
@@ -130,7 +128,7 @@
flags = LMB_NOMAP;
addr = res.start;
size = res.end - res.start + 1;
- boot_fdt_reserve_region(lmb, addr, size, flags);
+ boot_fdt_reserve_region(addr, size, flags);
}
subnode = fdt_next_subnode(fdt_blob, subnode);
@@ -140,7 +138,6 @@
/**
* boot_relocate_fdt - relocate flat device tree
- * @lmb: pointer to lmb handle, will be used for memory mgmt
* @of_flat_tree: pointer to a char* variable, will hold fdt start address
* @of_size: pointer to a ulong variable, will hold fdt length
*
@@ -155,7 +152,7 @@
* 0 - success
* 1 - failure
*/
-int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size)
+int boot_relocate_fdt(char **of_flat_tree, ulong *of_size)
{
u64 start, size, usable, addr, low, mapsize;
void *fdt_blob = *of_flat_tree;
@@ -187,18 +184,17 @@
if (desired_addr == ~0UL) {
/* All ones means use fdt in place */
of_start = fdt_blob;
- lmb_reserve(lmb, map_to_sysmem(of_start), of_len);
+ lmb_reserve(map_to_sysmem(of_start), of_len);
disable_relocation = 1;
} else if (desired_addr) {
- addr = lmb_alloc_base(lmb, of_len, 0x1000,
- desired_addr);
+ addr = lmb_alloc_base(of_len, 0x1000, desired_addr);
of_start = map_sysmem(addr, of_len);
if (of_start == NULL) {
puts("Failed using fdt_high value for Device Tree");
goto error;
}
} else {
- addr = lmb_alloc(lmb, of_len, 0x1000);
+ addr = lmb_alloc(of_len, 0x1000);
of_start = map_sysmem(addr, of_len);
}
} else {
@@ -220,7 +216,7 @@
* for LMB allocation.
*/
usable = min(start + size, low + mapsize);
- addr = lmb_alloc_base(lmb, of_len, 0x1000, usable);
+ addr = lmb_alloc_base(of_len, 0x1000, usable);
of_start = map_sysmem(addr, of_len);
/* Allocation succeeded, use this block. */
if (of_start != NULL)
@@ -569,8 +565,7 @@
return 0;
}
-int image_setup_libfdt(struct bootm_headers *images, void *blob,
- struct lmb *lmb)
+int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb)
{
ulong *initrd_start = &images->initrd_start;
ulong *initrd_end = &images->initrd_end;
@@ -670,8 +665,8 @@
}
/* Delete the old LMB reservation */
- if (lmb)
- lmb_free(lmb, map_to_sysmem(blob), fdt_totalsize(blob));
+ if (CONFIG_IS_ENABLED(LMB) && lmb)
+ lmb_free(map_to_sysmem(blob), fdt_totalsize(blob));
ret = fdt_shrink_to_minimum(blob, 0);
if (ret < 0)
@@ -679,8 +674,8 @@
of_size = ret;
/* Create a new LMB reservation */
- if (lmb)
- lmb_reserve(lmb, map_to_sysmem(blob), of_size);
+ if (CONFIG_IS_ENABLED(LMB) && lmb)
+ lmb_reserve(map_to_sysmem(blob), of_size);
#if defined(CONFIG_ARCH_KEYSTONE)
if (IS_ENABLED(CONFIG_OF_BOARD_SETUP))
diff --git a/boot/image-fit.c b/boot/image-fit.c
index 9253f81..7d56f0b 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -36,6 +36,7 @@
#include <bootm.h>
#include <image.h>
#include <bootstage.h>
+#include <upl.h>
#include <u-boot/crc.h>
/*****************************************************************************/
@@ -2294,6 +2295,8 @@
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD);
+ upl_add_image(fit, noffset, load, len);
+
*datap = load;
*lenp = len;
if (fit_unamep)
diff --git a/boot/scene.c b/boot/scene.c
index ac976aa..270c9c6 100644
--- a/boot/scene.c
+++ b/boot/scene.c
@@ -79,13 +79,7 @@
int scene_obj_count(struct scene *scn)
{
- struct scene_obj *obj;
- int count = 0;
-
- list_for_each_entry(obj, &scn->obj_head, sibling)
- count++;
-
- return count;
+ return list_count_nodes(&scn->obj_head);
}
void *scene_obj_find(const struct scene *scn, uint id, enum scene_obj_t type)
diff --git a/boot/upl_common.c b/boot/upl_common.c
new file mode 100644
index 0000000..3924423
--- /dev/null
+++ b/boot/upl_common.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff command functions
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <string.h>
+#include <upl.h>
+
+/* Names of bootmodes */
+const char *const bootmode_names[UPLBM_COUNT] = {
+ [UPLBM_FULL] = "full",
+ [UPLBM_MINIMAL] = "minimal",
+ [UPLBM_FAST] = "fast",
+ [UPLBM_DIAG] = "diag",
+ [UPLBM_DEFAULT] = "default",
+ [UPLBM_S2] = "s2",
+ [UPLBM_S3] = "s3",
+ [UPLBM_S4] = "s4",
+ [UPLBM_S5] = "s5",
+ [UPLBM_FACTORY] = "factory",
+ [UPLBM_FLASH] = "flash",
+ [UPLBM_RECOVERY] = "recovery",
+};
+
+/* Names of memory usages */
+const char *const usage_names[UPLUS_COUNT] = {
+ [UPLUS_ACPI_RECLAIM] = "acpi-reclaim",
+ [UPLUS_ACPI_NVS] = "acpi-nvs",
+ [UPLUS_BOOT_CODE] = "boot-code",
+ [UPLUS_BOOT_DATA] = "boot-data",
+ [UPLUS_RUNTIME_CODE] = "runtime-code",
+ [UPLUS_RUNTIME_DATA] = "runtime-data",
+};
+
+/* Names of access types */
+const char *const access_types[UPLUS_COUNT] = {
+ [UPLAT_MMIO] = "mmio",
+ [UPLAT_IO] = "io",
+};
+
+/* Names of graphics formats */
+const char *const graphics_formats[UPLUS_COUNT] = {
+ [UPLGF_ARGB32] = "a8r8g8b8",
+ [UPLGF_ABGR32] = "a8b8g8r8",
+ [UPLGF_ABGR64] = "a16b16g16r16",
+};
+
+void upl_init(struct upl *upl)
+{
+ memset(upl, '\0', sizeof(struct upl));
+ alist_init_struct(&upl->image, struct upl_image);
+ alist_init_struct(&upl->mem, struct upl_mem);
+ alist_init_struct(&upl->memmap, struct upl_memmap);
+ alist_init_struct(&upl->memres, struct upl_memres);
+}
diff --git a/boot/upl_common.h b/boot/upl_common.h
new file mode 100644
index 0000000..cc517dc
--- /dev/null
+++ b/boot/upl_common.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UPL handoff command functions
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __UPL_COMMON_H
+#define __UPL_COMMON_H
+
+/* Names of bootmodes */
+extern const char *const bootmode_names[UPLBM_COUNT];
+
+/* Names of memory usages */
+extern const char *const usage_names[UPLUS_COUNT];
+
+/* Names of access types */
+extern const char *const access_types[UPLUS_COUNT];
+
+/* Names of graphics formats */
+extern const char *const graphics_formats[UPLUS_COUNT];
+
+#endif /* __UPL_COMMON_H */
diff --git a/boot/upl_read.c b/boot/upl_read.c
new file mode 100644
index 0000000..5063897
--- /dev/null
+++ b/boot/upl_read.c
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff parsing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <log.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include "upl_common.h"
+
+/**
+ * read_addr() - Read an address
+ *
+ * Reads an address in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @addr: Place to put the address
+ * Return: 0 if OK, -ve on error
+ */
+static int read_addr(const struct upl *upl, ofnode node, const char *prop,
+ ulong *addrp)
+{
+ int ret;
+
+ if (upl->addr_cells == 1) {
+ u32 val;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (!ret)
+ *addrp = val;
+ } else {
+ u64 val;
+
+ ret = ofnode_read_u64(node, prop, &val);
+ if (!ret)
+ *addrp = val;
+ }
+
+ return ret;
+}
+
+/**
+ * read_size() - Read a size
+ *
+ * Reads a size in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @addr: Place to put the size
+ * Return: 0 if OK, -ve on error
+ */
+static int read_size(const struct upl *upl, ofnode node, const char *prop,
+ ulong *sizep)
+{
+ int ret;
+
+ if (upl->size_cells == 1) {
+ u32 val;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (!ret)
+ *sizep = val;
+ } else {
+ u64 val;
+
+ ret = ofnode_read_u64(node, prop, &val);
+ if (!ret)
+ *sizep = val;
+ }
+
+ return ret;
+}
+
+/**
+ * ofnode_read_bitmask() - Read a bit mask from a string list
+ *
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @names: Array of names for each bit
+ * @count: Number of array entries
+ * @value: Returns resulting bit-mask value on success
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer, -EINVAL if no such property
+ */
+static int ofnode_read_bitmask(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint *valuep)
+{
+ const char **list;
+ const char **strp;
+ uint val;
+ uint bit;
+ int ret;
+
+ ret = ofnode_read_string_list(node, prop, &list);
+ if (ret < 0)
+ return log_msg_ret("rea", ret);
+
+ val = 0;
+ for (strp = list; *strp; strp++) {
+ const char *str = *strp;
+ bool found = false;
+
+ for (bit = 0; bit < count; bit++) {
+ if (!strcmp(str, names[bit])) {
+ found = true;
+ break;
+ }
+ }
+ if (found)
+ val |= BIT(bit);
+ else
+ log_warning("%s/%s: Invalid value '%s'\n",
+ ofnode_get_name(node), prop, str);
+ }
+ *valuep = val;
+
+ return 0;
+}
+
+/**
+ * ofnode_read_value() - Read a string value as an int using a lookup
+ *
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @names: Array of names for each int value
+ * @count: Number of array entries
+ * @valuep: Returns int value read
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOENT if the
+ * property does not exist
+ */
+static int ofnode_read_value(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint *valuep)
+{
+ const char *str;
+ int i;
+
+ str = ofnode_read_string(node, prop);
+ if (!str)
+ return log_msg_ret("rd", -ENOENT);
+
+ for (i = 0; i < count; i++) {
+ if (!strcmp(names[i], str)) {
+ *valuep = i;
+ return 0;
+ }
+ }
+
+ log_debug("Unnamed value '%s'\n", str);
+ return log_msg_ret("val", -EINVAL);
+}
+
+static int read_uint(ofnode node, const char *prop, uint *valp)
+{
+ u32 val;
+ int ret;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (ret)
+ return ret;
+ *valp = val;
+
+ return 0;
+}
+
+/**
+ * decode_root_props() - Decode root properties from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_root_props(struct upl *upl, ofnode node)
+{
+ int ret;
+
+ ret = read_uint(node, UPLP_ADDRESS_CELLS, &upl->addr_cells);
+ if (!ret)
+ ret = read_uint(node, UPLP_SIZE_CELLS, &upl->size_cells);
+ if (ret)
+ return log_msg_ret("cel", ret);
+
+ return 0;
+}
+
+/**
+ * decode_root_props() - Decode UPL parameters from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_params(struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret;
+
+ node = ofnode_find_subnode(options, UPLN_UPL_PARAMS);
+ if (!ofnode_valid(node))
+ return log_msg_ret("par", -EINVAL);
+ log_debug("decoding '%s'\n", ofnode_get_name(node));
+
+ ret = read_addr(upl, node, UPLP_SMBIOS, &upl->smbios);
+ if (ret)
+ return log_msg_ret("smb", ret);
+ ret = read_addr(upl, node, UPLP_ACPI, &upl->acpi);
+ if (ret)
+ return log_msg_ret("acp", ret);
+ ret = ofnode_read_bitmask(node, UPLP_BOOTMODE, bootmode_names,
+ UPLBM_COUNT, &upl->bootmode);
+ if (ret)
+ return log_msg_ret("boo", ret);
+ ret = read_uint(node, UPLP_ADDR_WIDTH, &upl->addr_width);
+ if (ret)
+ return log_msg_ret("add", ret);
+ ret = read_uint(node, UPLP_ACPI_NVS_SIZE, &upl->acpi_nvs_size);
+ if (ret)
+ return log_msg_ret("nvs", ret);
+
+ return 0;
+}
+
+/**
+ * decode_upl_images() - Decode /options/upl-image nodes
+ *
+ * @node: /options node in which to look for the node
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_images(struct upl *upl, ofnode options)
+{
+ ofnode node, images;
+ int ret;
+
+ images = ofnode_find_subnode(options, UPLN_UPL_IMAGE);
+ if (!ofnode_valid(images))
+ return log_msg_ret("img", -EINVAL);
+ log_debug("decoding '%s'\n", ofnode_get_name(images));
+
+ ret = read_addr(upl, images, UPLP_FIT, &upl->fit);
+ if (!ret)
+ ret = read_uint(images, UPLP_CONF_OFFSET, &upl->conf_offset);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ ofnode_for_each_subnode(node, images) {
+ struct upl_image img;
+
+ ret = read_addr(upl, node, UPLP_LOAD, &img.load);
+ if (!ret)
+ ret = read_size(upl, node, UPLP_SIZE, &img.size);
+ if (!ret)
+ ret = read_uint(node, UPLP_OFFSET, &img.offset);
+ img.description = ofnode_read_string(node, UPLP_DESCRIPTION);
+ if (!img.description)
+ return log_msg_ret("sim", ret);
+ if (!alist_add(&upl->image, img))
+ return log_msg_ret("img", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_addr_size() - Decide a set of addr/size pairs
+ *
+ * Each base/size value from the devicetree is written to the region list
+ *
+ * @upl: UPL state
+ * @buf: Bytes to decode
+ * @size: Number of bytes to decode
+ * @regions: List of regions to process (struct memregion)
+ * Returns: number of regions found, if OK, else -ve on error
+ */
+static int decode_addr_size(const struct upl *upl, const char *buf, int size,
+ struct alist *regions)
+{
+ const char *ptr, *end = buf + size;
+ int i;
+
+ alist_init_struct(regions, struct memregion);
+ ptr = buf;
+ for (i = 0; ptr < end; i++) {
+ struct memregion reg;
+
+ if (upl->addr_cells == 1)
+ reg.base = fdt32_to_cpu(*(u32 *)ptr);
+ else
+ reg.base = fdt64_to_cpu(*(u64 *)ptr);
+ ptr += upl->addr_cells * sizeof(u32);
+
+ if (upl->size_cells == 1)
+ reg.size = fdt32_to_cpu(*(u32 *)ptr);
+ else
+ reg.size = fdt64_to_cpu(*(u64 *)ptr);
+ ptr += upl->size_cells * sizeof(u32);
+ if (ptr > end)
+ return -ENOSPC;
+
+ if (!alist_add(regions, reg))
+ return log_msg_ret("reg", -ENOMEM);
+ }
+
+ return i;
+}
+
+/**
+ * node_matches_at() - Check if a node name matches "base@..."
+ *
+ * Return: true if the node name matches the base string followed by an @ sign;
+ * false otherwise
+ */
+static bool node_matches_at(ofnode node, const char *base)
+{
+ const char *name = ofnode_get_name(node);
+ int len = strlen(base);
+
+ return !strncmp(base, name, len) && name[len] == '@';
+}
+
+/**
+ * decode_upl_memory_node() - Decode a /memory node from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memory_node(struct upl *upl, ofnode node)
+{
+ struct upl_mem mem;
+ const char *buf;
+ int size, len;
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing '%s' property\n",
+ ofnode_get_name(node), UPLP_REG);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ len = decode_addr_size(upl, buf, size, &mem.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ mem.hotpluggable = ofnode_read_bool(node, UPLP_HOTPLUGGABLE);
+ if (!alist_add(&upl->mem, mem))
+ return log_msg_ret("mem", -ENOMEM);
+
+ return 0;
+}
+
+/**
+ * decode_upl_memmap() - Decode memory-map nodes from the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node containing the /memory-map nodes
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memmap(struct upl *upl, ofnode root)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, root) {
+ struct upl_memmap memmap;
+ int size, len, ret;
+ const char *buf;
+
+ memmap.name = ofnode_get_name(node);
+ memmap.usage = 0;
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing '%s' property\n",
+ ofnode_get_name(node), UPLP_REG);
+ continue;
+ }
+
+ len = decode_addr_size(upl, buf, size, &memmap.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ ret = ofnode_read_bitmask(node, UPLP_USAGE, usage_names,
+ UPLUS_COUNT, &memmap.usage);
+ if (ret && ret != -EINVAL) /* optional property */
+ return log_msg_ret("bit", ret);
+
+ if (!alist_add(&upl->memmap, memmap))
+ return log_msg_ret("mmp", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_upl_memres() - Decode reserved-memory nodes from the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node containing the reserved-memory nodes
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memres(struct upl *upl, ofnode root)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, root) {
+ struct upl_memres memres;
+ const char *buf;
+ int size, len;
+
+ log_debug("decoding '%s'\n", ofnode_get_name(node));
+ memres.name = ofnode_get_name(node);
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ continue;
+ }
+
+ len = decode_addr_size(upl, buf, size, &memres.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ memres.no_map = ofnode_read_bool(node, UPLP_NO_MAP);
+
+ if (!alist_add(&upl->memres, memres))
+ return log_msg_ret("mre", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_upl_serial() - Decode the serial node
+ *
+ * @upl: UPL state
+ * @root: Parent node contain node
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_serial(struct upl *upl, ofnode node)
+{
+ struct upl_serial *ser = &upl->serial;
+ const char *buf;
+ int len, size;
+ int ret;
+
+ ser->compatible = ofnode_read_string(node, UPLP_COMPATIBLE);
+ if (!ser->compatible) {
+ log_warning("Node '%s': Missing compatible string\n",
+ ofnode_get_name(node));
+ return log_msg_ret("com", -EINVAL);
+ }
+ ret = read_uint(node, UPLP_CLOCK_FREQUENCY, &ser->clock_frequency);
+ if (!ret)
+ ret = read_uint(node, UPLP_CURRENT_SPEED, &ser->current_speed);
+ if (ret)
+ return log_msg_ret("spe", ret);
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ return log_msg_ret("reg", -EINVAL);
+ }
+
+ len = decode_addr_size(upl, buf, sizeof(buf), &ser->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ /* set defaults */
+ ser->reg_io_shift = UPLD_REG_IO_SHIFT;
+ ser->reg_offset = UPLD_REG_OFFSET;
+ ser->reg_io_width = UPLD_REG_IO_WIDTH;
+ read_uint(node, UPLP_REG_IO_SHIFT, &ser->reg_io_shift);
+ read_uint(node, UPLP_REG_OFFSET, &ser->reg_offset);
+ read_uint(node, UPLP_REG_IO_WIDTH, &ser->reg_io_width);
+ read_addr(upl, node, UPLP_VIRTUAL_REG, &ser->virtual_reg);
+ ret = ofnode_read_value(node, UPLP_ACCESS_TYPE, access_types,
+ ARRAY_SIZE(access_types), &ser->access_type);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("ser", ret);
+
+ return 0;
+}
+
+/**
+ * decode_upl_graphics() - Decode graphics node
+ *
+ * @upl: UPL state
+ * @root: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_graphics(struct upl *upl, ofnode node)
+{
+ struct upl_graphics *gra = &upl->graphics;
+ const char *buf, *compat;
+ int len, size;
+ int ret;
+
+ compat = ofnode_read_string(node, UPLP_COMPATIBLE);
+ if (!compat) {
+ log_warning("Node '%s': Missing compatible string\n",
+ ofnode_get_name(node));
+ return log_msg_ret("com", -EINVAL);
+ }
+ if (strcmp(UPLC_GRAPHICS, compat)) {
+ log_warning("Node '%s': Ignoring compatible '%s'\n",
+ ofnode_get_name(node), compat);
+ return 0;
+ }
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ return log_msg_ret("reg", -EINVAL);
+ }
+
+ len = decode_addr_size(upl, buf, sizeof(buf), &gra->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = read_uint(node, UPLP_WIDTH, &gra->width);
+ if (!ret)
+ ret = read_uint(node, UPLP_HEIGHT, &gra->height);
+ if (!ret)
+ ret = read_uint(node, UPLP_STRIDE, &gra->stride);
+ if (!ret) {
+ ret = ofnode_read_value(node, UPLP_GRAPHICS_FORMAT,
+ graphics_formats,
+ ARRAY_SIZE(graphics_formats),
+ &gra->format);
+ }
+ if (ret)
+ return log_msg_ret("pro", ret);
+
+ return 0;
+}
+
+int upl_read_handoff(struct upl *upl, oftree tree)
+{
+ ofnode root, node;
+ int ret;
+
+ if (!oftree_valid(tree))
+ return log_msg_ret("tre", -EINVAL);
+
+ root = oftree_root(tree);
+
+ upl_init(upl);
+ ret = decode_root_props(upl, root);
+ if (ret)
+ return log_msg_ret("roo", ret);
+
+ ofnode_for_each_subnode(node, root) {
+ const char *name = ofnode_get_name(node);
+
+ log_debug("decoding '%s'\n", name);
+ if (!strcmp(UPLN_OPTIONS, name)) {
+ ret = decode_upl_params(upl, node);
+ if (ret)
+ return log_msg_ret("opt", ret);
+
+ ret = decode_upl_images(upl, node);
+ } else if (node_matches_at(node, UPLN_MEMORY)) {
+ ret = decode_upl_memory_node(upl, node);
+ } else if (!strcmp(UPLN_MEMORY_MAP, name)) {
+ ret = decode_upl_memmap(upl, node);
+ } else if (!strcmp(UPLN_MEMORY_RESERVED, name)) {
+ ret = decode_upl_memres(upl, node);
+ } else if (node_matches_at(node, UPLN_SERIAL)) {
+ ret = decode_upl_serial(upl, node);
+ } else if (node_matches_at(node, UPLN_GRAPHICS)) {
+ ret = decode_upl_graphics(upl, node);
+ } else {
+ log_debug("Unknown node '%s'\n", name);
+ ret = 0;
+ }
+ if (ret)
+ return log_msg_ret("err", ret);
+ }
+
+ return 0;
+}
diff --git a/boot/upl_write.c b/boot/upl_write.c
new file mode 100644
index 0000000..7d637c15
--- /dev/null
+++ b/boot/upl_write.c
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <log.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include "upl_common.h"
+
+/**
+ * write_addr() - Write an address
+ *
+ * Writes an address in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @addr: Address to write
+ * Return: 0 if OK, -ve on error
+ */
+static int write_addr(const struct upl *upl, ofnode node, const char *prop,
+ ulong addr)
+{
+ int ret;
+
+ if (upl->addr_cells == 1)
+ ret = ofnode_write_u32(node, prop, addr);
+ else
+ ret = ofnode_write_u64(node, prop, addr);
+
+ return ret;
+}
+
+/**
+ * write_size() - Write a size
+ *
+ * Writes a size in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @size: Size to write
+ * Return: 0 if OK, -ve on error
+ */
+static int write_size(const struct upl *upl, ofnode node, const char *prop,
+ ulong size)
+{
+ int ret;
+
+ if (upl->size_cells == 1)
+ ret = ofnode_write_u32(node, prop, size);
+ else
+ ret = ofnode_write_u64(node, prop, size);
+
+ return ret;
+}
+
+/**
+ * ofnode_write_bitmask() - Write a bit mask as a string list
+ *
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @names: Array of names for each bit
+ * @count: Number of array entries
+ * @value: Bit-mask value to write
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer
+ */
+static int ofnode_write_bitmask(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint value)
+{
+ char buf[128];
+ char *ptr, *end = buf + sizeof(buf);
+ uint bit;
+ int ret;
+
+ ptr = buf;
+ for (bit = 0; bit < count; bit++) {
+ if (value & BIT(bit)) {
+ const char *str = names[bit];
+ uint len;
+
+ if (!str) {
+ log_debug("Unnamed bit number %d\n", bit);
+ return log_msg_ret("bit", -EINVAL);
+ }
+ len = strlen(str) + 1;
+ if (ptr + len > end) {
+ log_debug("String array too long\n");
+ return log_msg_ret("bit", -ENOSPC);
+ }
+
+ memcpy(ptr, str, len);
+ ptr += len;
+ }
+ }
+
+ ret = ofnode_write_prop(node, prop, buf, ptr - buf, true);
+ if (ret)
+ return log_msg_ret("wri", ret);
+
+ return 0;
+}
+
+/**
+ * ofnode_write_value() - Write an int as a string value using a lookup
+ *
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @names: Array of names for each int value
+ * @count: Number of array entries
+ * @value: Int value to write
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer
+ */
+static int ofnode_write_value(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint value)
+{
+ const char *str;
+ int ret;
+
+ if (value >= count) {
+ log_debug("Value of range %d\n", value);
+ return log_msg_ret("val", -ERANGE);
+ }
+ str = names[value];
+ if (!str) {
+ log_debug("Unnamed value %d\n", value);
+ return log_msg_ret("val", -EINVAL);
+ }
+ ret = ofnode_write_string(node, prop, str);
+ if (ret)
+ return log_msg_ret("wri", ret);
+
+ return 0;
+}
+
+/**
+ * add_root_props() - Add root properties to the tree
+ *
+ * @node: Node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_root_props(const struct upl *upl, ofnode node)
+{
+ int ret;
+
+ ret = ofnode_write_u32(node, UPLP_ADDRESS_CELLS, upl->addr_cells);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_SIZE_CELLS, upl->size_cells);
+ if (ret)
+ return log_msg_ret("cel", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_params() - Add UPL parameters node
+ *
+ * @upl: UPL state
+ * @options: /options node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_params(const struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret;
+
+ ret = ofnode_add_subnode(options, UPLN_UPL_PARAMS, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ ret = write_addr(upl, node, UPLP_SMBIOS, upl->smbios);
+ if (!ret)
+ ret = write_addr(upl, node, UPLP_ACPI, upl->acpi);
+ if (!ret && upl->bootmode)
+ ret = ofnode_write_bitmask(node, UPLP_BOOTMODE, bootmode_names,
+ UPLBM_COUNT, upl->bootmode);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_ADDR_WIDTH, upl->addr_width);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_ACPI_NVS_SIZE,
+ upl->acpi_nvs_size);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_image() - Add /options/upl-image nodes and properties to the tree
+ *
+ * @upl: UPL state
+ * @node: /options node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_image(const struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret, i;
+
+ ret = ofnode_add_subnode(options, UPLN_UPL_IMAGE, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ if (upl->fit)
+ ret = ofnode_write_u32(node, UPLP_FIT, upl->fit);
+ if (!ret && upl->conf_offset)
+ ret = ofnode_write_u32(node, UPLP_CONF_OFFSET,
+ upl->conf_offset);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ for (i = 0; i < upl->image.count; i++) {
+ const struct upl_image *img = alist_get(&upl->image, i,
+ struct upl_image);
+ ofnode subnode;
+ char name[10];
+
+ snprintf(name, sizeof(name), UPLN_IMAGE "-%d", i + 1);
+ ret = ofnode_add_subnode(node, name, &subnode);
+ if (ret)
+ return log_msg_ret("sub", ret);
+
+ ret = write_addr(upl, subnode, UPLP_LOAD, img->load);
+ if (!ret)
+ ret = write_size(upl, subnode, UPLP_SIZE, img->size);
+ if (!ret && img->offset)
+ ret = ofnode_write_u32(subnode, UPLP_OFFSET,
+ img->offset);
+ ret = ofnode_write_string(subnode, UPLP_DESCRIPTION,
+ img->description);
+ if (ret)
+ return log_msg_ret("sim", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * buffer_addr_size() - Generate a set of addr/size pairs
+ *
+ * Each base/size value from each region is written to the buffer in a suitable
+ * format to be written to the devicetree
+ *
+ * @upl: UPL state
+ * @buf: Buffer to write to
+ * @size: Buffer size
+ * @num_regions: Number of regions to process
+ * @region: List of regions to process (struct memregion)
+ * Returns: Number of bytes written, or -ENOSPC if the buffer is too small
+ */
+static int buffer_addr_size(const struct upl *upl, char *buf, int size,
+ uint num_regions, const struct alist *region)
+{
+ char *ptr, *end = buf + size;
+ int i;
+
+ ptr = buf;
+ for (i = 0; i < num_regions; i++) {
+ const struct memregion *reg = alist_get(region, i,
+ struct memregion);
+
+ if (upl->addr_cells == 1)
+ *(u32 *)ptr = cpu_to_fdt32(reg->base);
+ else
+ *(u64 *)ptr = cpu_to_fdt64(reg->base);
+ ptr += upl->addr_cells * sizeof(u32);
+
+ if (upl->size_cells == 1)
+ *(u32 *)ptr = cpu_to_fdt32(reg->size);
+ else
+ *(u64 *)ptr = cpu_to_fdt64(reg->size);
+ ptr += upl->size_cells * sizeof(u32);
+ if (ptr > end)
+ return -ENOSPC;
+ }
+
+ return ptr - buf;
+}
+
+/**
+ * add_upl_memory() - Add /memory nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new /memory nodes
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memory(const struct upl *upl, ofnode root)
+{
+ int i;
+
+ for (i = 0; i < upl->mem.count; i++) {
+ const struct upl_mem *mem = alist_get(&upl->mem, i,
+ struct upl_mem);
+ char buf[mem->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!mem->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&mem->region, 0, struct memregion);
+ sprintf(name, UPLN_MEMORY "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("mem", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), mem->region.count,
+ &mem->region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && mem->hotpluggable)
+ ret = ofnode_write_bool(node, UPLP_HOTPLUGGABLE,
+ mem->hotpluggable);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_memmap() - Add memory-map nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new /memory-map node and its subnodes
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memmap(const struct upl *upl, ofnode root)
+{
+ ofnode mem_node;
+ int i, ret;
+
+ if (!upl->memmap.count)
+ return 0;
+ ret = ofnode_add_subnode(root, UPLN_MEMORY_MAP, &mem_node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ for (i = 0; i < upl->memmap.count; i++) {
+ const struct upl_memmap *memmap = alist_get(&upl->memmap, i,
+ struct upl_memmap);
+ char buf[memmap->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!memmap->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&memmap->region, 0, struct memregion);
+ sprintf(name, "%s@0x%lx", memmap->name, first->base);
+ ret = ofnode_add_subnode(mem_node, name, &node);
+ if (ret)
+ return log_msg_ret("memmap", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf),
+ memmap->region.count, &memmap->region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && memmap->usage)
+ ret = ofnode_write_bitmask(node, UPLP_USAGE,
+ usage_names,
+ UPLUS_COUNT, memmap->usage);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_memres() - Add /memory-reserved nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memres(const struct upl *upl, ofnode root,
+ bool skip_existing)
+{
+ ofnode mem_node;
+ int i, ret;
+
+ if (!upl->memmap.count)
+ return 0;
+ ret = ofnode_add_subnode(root, UPLN_MEMORY_RESERVED, &mem_node);
+ if (ret) {
+ if (skip_existing && ret == -EEXIST)
+ return 0;
+ return log_msg_ret("img", ret);
+ }
+
+ for (i = 0; i < upl->memres.count; i++) {
+ const struct upl_memres *memres = alist_get(&upl->memres, i,
+ struct upl_memres);
+ char buf[memres->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!memres->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&memres->region, 0, struct memregion);
+ sprintf(name, "%s@0x%lx", memres->name, first->base);
+ ret = ofnode_add_subnode(mem_node, name, &node);
+ if (ret)
+ return log_msg_ret("memres", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf),
+ memres->region.count, &memres->region);
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && memres->no_map)
+ ret = ofnode_write_bool(node, UPLP_NO_MAP,
+ memres->no_map);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_serial() - Add serial node
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_serial(const struct upl *upl, ofnode root,
+ bool skip_existing)
+{
+ const struct upl_serial *ser = &upl->serial;
+ const struct memregion *first;
+ char name[26];
+ ofnode node;
+ int ret;
+
+ if (!ser->compatible || skip_existing)
+ return 0;
+ if (!ser->reg.count)
+ return log_msg_ret("ser", -EINVAL);
+ first = alist_get(&ser->reg, 0, struct memregion);
+ sprintf(name, UPLN_SERIAL "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+ ret = ofnode_write_string(node, UPLP_COMPATIBLE, ser->compatible);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_CLOCK_FREQUENCY,
+ ser->clock_frequency);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_CURRENT_SPEED,
+ ser->current_speed);
+ if (!ret) {
+ char buf[16];
+ int len;
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), 1, &ser->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ }
+ if (!ret && ser->reg_io_shift != UPLD_REG_IO_SHIFT)
+ ret = ofnode_write_u32(node, UPLP_REG_IO_SHIFT,
+ ser->reg_io_shift);
+ if (!ret && ser->reg_offset != UPLD_REG_OFFSET)
+ ret = ofnode_write_u32(node, UPLP_REG_OFFSET, ser->reg_offset);
+ if (!ret && ser->reg_io_width != UPLD_REG_IO_WIDTH)
+ ret = ofnode_write_u32(node, UPLP_REG_IO_WIDTH,
+ ser->reg_io_width);
+ if (!ret && ser->virtual_reg)
+ ret = write_addr(upl, node, UPLP_VIRTUAL_REG, ser->virtual_reg);
+ if (!ret) {
+ ret = ofnode_write_value(node, UPLP_ACCESS_TYPE, access_types,
+ ARRAY_SIZE(access_types),
+ ser->access_type);
+ }
+ if (ret)
+ return log_msg_ret("ser", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_graphics() - Add graphics node
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_graphics(const struct upl *upl, ofnode root)
+{
+ const struct upl_graphics *gra = &upl->graphics;
+ const struct memregion *first;
+ char name[36];
+ ofnode node;
+ int ret;
+
+ if (!gra->reg.count)
+ return log_msg_ret("gra", -ENOENT);
+ first = alist_get(&gra->reg, 0, struct memregion);
+ sprintf(name, UPLN_GRAPHICS "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("gra", ret);
+
+ ret = ofnode_write_string(node, UPLP_COMPATIBLE, UPLC_GRAPHICS);
+ if (!ret) {
+ char buf[16];
+ int len;
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), 1, &gra->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ }
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_WIDTH, gra->width);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_HEIGHT, gra->height);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_STRIDE, gra->stride);
+ if (!ret) {
+ ret = ofnode_write_value(node, UPLP_GRAPHICS_FORMAT,
+ graphics_formats,
+ ARRAY_SIZE(graphics_formats),
+ gra->format);
+ }
+ if (ret)
+ return log_msg_ret("pro", ret);
+
+ return 0;
+}
+
+int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing)
+{
+ ofnode options;
+ int ret;
+
+ ret = add_root_props(upl, root);
+ if (ret)
+ return log_msg_ret("ad1", ret);
+ ret = ofnode_add_subnode(root, UPLN_OPTIONS, &options);
+ if (ret && ret != -EEXIST)
+ return log_msg_ret("opt", -EINVAL);
+
+ ret = add_upl_params(upl, options);
+ if (ret)
+ return log_msg_ret("ad1", ret);
+
+ ret = add_upl_image(upl, options);
+ if (ret)
+ return log_msg_ret("ad2", ret);
+
+ ret = add_upl_memory(upl, root);
+ if (ret)
+ return log_msg_ret("ad3", ret);
+
+ ret = add_upl_memmap(upl, root);
+ if (ret)
+ return log_msg_ret("ad4", ret);
+
+ ret = add_upl_memres(upl, root, skip_existing);
+ if (ret)
+ return log_msg_ret("ad5", ret);
+
+ ret = add_upl_serial(upl, root, skip_existing);
+ if (ret)
+ return log_msg_ret("ad6", ret);
+
+ ret = add_upl_graphics(upl, root);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("ad6", ret);
+
+ return 0;
+}
+
+int upl_create_handoff_tree(const struct upl *upl, oftree *treep)
+{
+ ofnode root;
+ oftree tree;
+ int ret;
+
+ ret = oftree_new(&tree);
+ if (ret)
+ return log_msg_ret("new", ret);
+
+ root = oftree_root(tree);
+ if (!ofnode_valid(root))
+ return log_msg_ret("roo", -EINVAL);
+
+ ret = upl_write_handoff(upl, root, false);
+ if (ret)
+ return log_msg_ret("wr", ret);
+
+ *treep = tree;
+
+ return 0;
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 978f44e..5ef3c8a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -388,6 +388,13 @@
help
Support reading NAND Seattle Image (SEAMA) images.
+config CMD_UPL
+ bool "upl - Universal Payload Specification"
+ help
+ Provides commands to deal with UPL payloads and handoff information.
+ U-Boot supports generating and accepting handoff information. The
+ mkimage tool will eventually support creating payloads.
+
config CMD_VBE
bool "vbe - Verified Boot for Embedded"
depends on BOOTMETH_VBE
@@ -1399,6 +1406,15 @@
Enable support for the "mmc swrite" command to write Android sparse
images to eMMC.
+config MMC_SPEED_MODE_SET
+ bool "set speed mode using mmc command"
+ help
+ Enable setting speed mode using mmc rescan and mmc dev commands.
+ The speed mode is provided as the last argument in these commands
+ and is indicated using the index from enum bus_mode in
+ include/mmc.h. A speed mode can be set only if it has already
+ been enabled in the device tree.
+
endif
config CMD_CLONE
@@ -1487,6 +1503,7 @@
config CMD_OSD
bool "osd"
+ depends on OSD
help
Enable the 'osd' command which allows to query information from and
write text data to a on-screen display (OSD) device; a virtual device
@@ -2003,6 +2020,7 @@
config CMD_WGET
bool "wget"
select PROT_TCP
+ default y if SANDBOX
help
wget is a simple command to download kernel, or other files,
from a http server over TCP.
@@ -2091,6 +2109,7 @@
config CMD_PXE
bool "pxe"
select PXE_UTILS
+ imply CMD_TFTPBOOT
help
Boot image via network using PXE protocol
@@ -2963,16 +2982,6 @@
help
UBIFS is a file system for flash devices which works on top of UBI.
-config MMC_SPEED_MODE_SET
- bool "set speed mode using mmc command"
- depends on CMD_MMC
- help
- Enable setting speed mode using mmc rescan and mmc dev commands.
- The speed mode is provided as the last argument in these commands
- and is indicated using the index from enum bus_mode in
- include/mmc.h. A speed mode can be set only if it has already
- been enabled in the device tree.
-
config CMD_MESON
bool "Amlogic Meson commands"
depends on ARCH_MESON
diff --git a/cmd/Makefile b/cmd/Makefile
index 87133cc..91227f1 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -189,6 +189,7 @@
obj-$(CONFIG_CMD_UNIVERSE) += universe.o
obj-$(CONFIG_CMD_UNLZ4) += unlz4.o
obj-$(CONFIG_CMD_UNZIP) += unzip.o
+obj-$(CONFIG_CMD_UPL) += upl.o
obj-$(CONFIG_CMD_VIRTIO) += virtio.o
obj-$(CONFIG_CMD_WDT) += wdt.o
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 437ac4e..f6e534d 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -154,18 +154,13 @@
if (IS_ENABLED(CONFIG_CMD_NET))
print_eth();
bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
- bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
- bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
if (IS_ENABLED(CONFIG_VIDEO))
show_video_info();
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
bdinfo_print_num_l("multi_dtb_fit", (ulong)gd->multi_dtb_fit);
#endif
if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) {
- struct lmb lmb;
-
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
- lmb_dump_all_force(&lmb);
+ lmb_dump_all_force();
if (IS_ENABLED(CONFIG_OF_REAL))
printf("devicetree = %s\n", fdtdec_get_srcname());
}
diff --git a/cmd/bind.c b/cmd/bind.c
index 3a59eef..c0d31f5 100644
--- a/cmd/bind.c
+++ b/cmd/bind.c
@@ -10,8 +10,8 @@
#include <dm/root.h>
#include <dm/uclass-internal.h>
-static int bind_by_class_index(const char *uclass, int index,
- const char *drv_name)
+static int bind_by_class_seq(const char *uclass, int seq,
+ const char *drv_name)
{
static enum uclass_id uclass_id;
struct udevice *dev;
@@ -31,9 +31,9 @@
return -EINVAL;
}
- ret = uclass_find_device(uclass_id, index, &parent);
+ ret = uclass_find_device_by_seq(uclass_id, seq, &parent);
if (!parent || ret) {
- printf("Cannot find device %d of class %s\n", index, uclass);
+ printf("Cannot find device %d of class %s\n", seq, uclass);
return ret;
}
@@ -47,7 +47,7 @@
return 0;
}
-static int find_dev(const char *uclass, int index, struct udevice **devp)
+static int find_dev(const char *uclass, int seq, struct udevice **devp)
{
static enum uclass_id uclass_id;
int rc;
@@ -58,21 +58,21 @@
return -EINVAL;
}
- rc = uclass_find_device(uclass_id, index, devp);
+ rc = uclass_find_device_by_seq(uclass_id, seq, devp);
if (!*devp || rc) {
- printf("Cannot find device %d of class %s\n", index, uclass);
+ printf("Cannot find device %d of class %s\n", seq, uclass);
return rc;
}
return 0;
}
-static int unbind_by_class_index(const char *uclass, int index)
+static int unbind_by_class_seq(const char *uclass, int seq)
{
int ret;
struct udevice *dev;
- ret = find_dev(uclass, index, &dev);
+ ret = find_dev(uclass, seq, &dev);
if (ret)
return ret;
@@ -91,8 +91,8 @@
return 0;
}
-static int unbind_child_by_class_index(const char *uclass, int index,
- const char *drv_name)
+static int unbind_child_by_class_seq(const char *uclass, int seq,
+ const char *drv_name)
{
struct udevice *parent;
int ret;
@@ -104,7 +104,7 @@
return -ENOENT;
}
- ret = find_dev(uclass, index, &parent);
+ ret = find_dev(uclass, seq, &parent);
if (ret)
return ret;
@@ -217,19 +217,19 @@
return CMD_RET_USAGE;
ret = unbind_by_node_path(argv[1]);
} else if (!by_node && bind) {
- int index = (argc > 2) ? dectoul(argv[2], NULL) : 0;
+ int seq = (argc > 2) ? dectoul(argv[2], NULL) : 0;
if (argc != 4)
return CMD_RET_USAGE;
- ret = bind_by_class_index(argv[1], index, argv[3]);
+ ret = bind_by_class_seq(argv[1], seq, argv[3]);
} else if (!by_node && !bind) {
- int index = (argc > 2) ? dectoul(argv[2], NULL) : 0;
+ int seq = (argc > 2) ? dectoul(argv[2], NULL) : 0;
if (argc == 3)
- ret = unbind_by_class_index(argv[1], index);
+ ret = unbind_by_class_seq(argv[1], seq);
else if (argc == 4)
- ret = unbind_child_by_class_index(argv[1], index,
- argv[3]);
+ ret = unbind_child_by_class_seq(argv[1], seq,
+ argv[3]);
else
return CMD_RET_USAGE;
}
@@ -244,17 +244,17 @@
bind, 4, 0, do_bind_unbind,
"Bind a device to a driver",
"<node path> <driver>\n"
- "bind <class> <index> <driver>\n"
+ "bind <class> <seq> <driver>\n"
"Use 'dm tree' to list all devices registered in the driver model,\n"
- "their path, class, index and current driver.\n"
+ "their path, class, sequence and current driver.\n"
);
U_BOOT_CMD(
unbind, 4, 0, do_bind_unbind,
"Unbind a device from a driver",
"<node path>\n"
- "unbind <class> <index>\n"
- "unbind <class> <index> <driver>\n"
+ "unbind <class> <seq>\n"
+ "unbind <class> <seq> <driver>\n"
"Use 'dm tree' to list all devices registered in the driver model,\n"
- "their path, class, index and current driver.\n"
+ "their path, class, sequence and current driver.\n"
);
diff --git a/cmd/booti.c b/cmd/booti.c
index 62b19e8..43e79e8 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -78,7 +78,7 @@
/* Handle BOOTM_STATE_LOADOS */
if (relocated_addr != ld) {
- printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n", ld,
+ printf("Moving Image from 0x%lx to 0x%lx, end=0x%lx\n", ld,
relocated_addr, relocated_addr + image_size);
memmove((void *)relocated_addr, (void *)ld, image_size);
}
@@ -87,7 +87,7 @@
images->os.start = relocated_addr;
images->os.end = relocated_addr + image_size;
- lmb_reserve(&images->lmb, images->ep, le32_to_cpu(image_size));
+ lmb_reserve(images->ep, le32_to_cpu(image_size));
/*
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
diff --git a/cmd/bootz.c b/cmd/bootz.c
index 55837a7..787203f 100644
--- a/cmd/bootz.c
+++ b/cmd/bootz.c
@@ -56,7 +56,7 @@
if (ret != 0)
return 1;
- lmb_reserve(&images->lmb, images->ep, zi_end - zi_start);
+ lmb_reserve(images->ep, zi_end - zi_start);
/*
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
diff --git a/cmd/date.c b/cmd/date.c
index 755adec..8614f02 100644
--- a/cmd/date.c
+++ b/cmd/date.c
@@ -31,7 +31,6 @@
int old_bus __maybe_unused;
/* switch to correct I2C bus */
-#ifdef CONFIG_DM_RTC
struct udevice *dev;
rcode = uclass_get_device_by_seq(UCLASS_RTC, 0, &dev);
@@ -42,35 +41,19 @@
return CMD_RET_FAILURE;
}
}
-#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM);
-#else
- old_bus = I2C_GET_BUS();
- I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM);
-#endif
switch (argc) {
case 2: /* set date & time */
if (strcmp(argv[1],"reset") == 0) {
puts ("Reset RTC...\n");
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_reset(dev);
if (!rcode)
rcode = dm_rtc_set(dev, &default_tm);
-#else
- rtc_reset();
- rcode = rtc_set(&default_tm);
-#endif
if (rcode)
puts("## Failed to set date after RTC reset\n");
} else {
/* initialize tm with current time */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
-#else
- rcode = rtc_get(&tm);
-#endif
if (!rcode) {
/* insert new date & time */
if (mk_date(argv[1], &tm) != 0) {
@@ -78,11 +61,7 @@
break;
}
/* and write to RTC */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_set(dev, &tm);
-#else
- rcode = rtc_set(&tm);
-#endif
if (rcode) {
printf("## Set date failed: err=%d\n",
rcode);
@@ -93,11 +72,7 @@
}
fallthrough;
case 1: /* get date & time */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
-#else
- rcode = rtc_get(&tm);
-#endif
if (rcode) {
puts("## Get date failed\n");
break;
@@ -114,13 +89,6 @@
rcode = CMD_RET_USAGE;
}
- /* switch back to original I2C bus */
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
- i2c_set_bus_num(old_bus);
-#elif !defined(CONFIG_DM_RTC)
- I2C_SET_BUS(old_bus);
-#endif
-
return rcode ? CMD_RET_FAILURE : 0;
}
diff --git a/cmd/efi.c b/cmd/efi.c
index 6bed2d7..687ccb5 100644
--- a/cmd/efi.c
+++ b/cmd/efi.c
@@ -11,7 +11,7 @@
#include <log.h>
#include <malloc.h>
#include <sort.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/cmd/efi_common.c b/cmd/efi_common.c
index c46764e..d2f2b59 100644
--- a/cmd/efi_common.c
+++ b/cmd/efi_common.c
@@ -8,7 +8,7 @@
#include <efi.h>
#include <efi_api.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
void efi_show_tables(struct efi_system_table *systab)
{
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 1a191eb..e040fe7 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -665,7 +665,7 @@
};
/**
- * create_lo_dp() - create a special device path for our Boot### option
+ * create_lo_dp_part() - create a special device path for our Boot### option
*
* @dev: device
* @part: disk partition
@@ -1127,7 +1127,7 @@
}
/**
- * show_efi_boot_dump() - dump all UEFI load options
+ * do_efi_boot_dump() - dump all UEFI load options
*
* @cmdtp: Command table
* @flag: Command flag
diff --git a/cmd/elf.c b/cmd/elf.c
index 673c6c3..f07e344 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -70,7 +70,7 @@
fdt_set_totalsize((void *)fdt_addr,
fdt_totalsize(fdt_addr) + CONFIG_SYS_FDT_PAD);
- if (image_setup_libfdt(&img, (void *)fdt_addr, NULL))
+ if (image_setup_libfdt(&img, (void *)fdt_addr, false))
return 1;
}
#endif
diff --git a/cmd/flash.c b/cmd/flash.c
index de0e04f..fd660ec 100644
--- a/cmd/flash.c
+++ b/cmd/flash.c
@@ -10,7 +10,7 @@
#include <command.h>
#include <log.h>
#include <vsprintf.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#if defined(CONFIG_CMD_MTDPARTS)
#include <jffs2/jffs2.h>
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 86b7701..27aea2d 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -19,7 +19,7 @@
#include <part_efi.h>
#include <part.h>
#include <exports.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/ctype.h>
#include <div64.h>
#include <memalign.h>
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 7dac0a9..7246c4f 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -1698,18 +1698,6 @@
for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) {
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- int j;
-
- for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
- if (i2c_bus[i].next_hop[j].chip == 0)
- break;
- printf("->%s@0x%2x:%d",
- i2c_bus[i].next_hop[j].mux.name,
- i2c_bus[i].next_hop[j].chip,
- i2c_bus[i].next_hop[j].channel);
- }
-#endif
printf("\n");
}
#endif
@@ -1734,17 +1722,6 @@
return -1;
}
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- int j;
- for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
- if (i2c_bus[i].next_hop[j].chip == 0)
- break;
- printf("->%s@0x%2x:%d",
- i2c_bus[i].next_hop[j].mux.name,
- i2c_bus[i].next_hop[j].chip,
- i2c_bus[i].next_hop[j].channel);
- }
-#endif
printf("\n");
#endif
}
diff --git a/cmd/led.c b/cmd/led.c
index 2f786f3..91fb856 100644
--- a/cmd/led.c
+++ b/cmd/led.c
@@ -118,7 +118,7 @@
return 0;
}
-#ifdef CONFIG_LED_BLINK
+#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK)
#define BLINK "|blink [blink-freq in ms]"
#else
#define BLINK ""
diff --git a/cmd/load.c b/cmd/load.c
index d773a25..20d8025 100644
--- a/cmd/load.c
+++ b/cmd/load.c
@@ -141,7 +141,6 @@
static ulong load_serial(long offset)
{
- struct lmb lmb;
char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */
char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */
int binlen; /* no. of data bytes in S-Rec. */
@@ -154,8 +153,6 @@
int line_count = 0;
long ret;
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
while (read_record(record, SREC_MAXRECLEN + 1) >= 0) {
type = srec_decode(record, &binlen, &addr, binbuf);
@@ -182,7 +179,7 @@
{
void *dst;
- ret = lmb_reserve(&lmb, store_addr, binlen);
+ ret = lmb_reserve(store_addr, binlen);
if (ret) {
printf("\nCannot overwrite reserved area (%08lx..%08lx)\n",
store_addr, store_addr + binlen);
@@ -191,7 +188,7 @@
dst = map_sysmem(store_addr, binlen);
memcpy(dst, binbuf, binlen);
unmap_sysmem(dst);
- lmb_free(&lmb, store_addr, binlen);
+ lmb_free(store_addr, binlen);
}
if ((store_addr) < start_addr)
start_addr = store_addr;
diff --git a/cmd/mem.c b/cmd/mem.c
index 2743480..4d6fde2 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -245,7 +245,7 @@
int size;
int rcode = 0;
const char *type;
- const void *buf1, *buf2, *base;
+ const void *buf1, *buf2, *base, *ptr1, *ptr2;
ulong word1, word2; /* 64-bit if MEM_SUPPORT_64BIT_DATA */
if (argc != 4)
@@ -270,22 +270,22 @@
bytes = size * count;
base = buf1 = map_sysmem(addr1, bytes);
buf2 = map_sysmem(addr2, bytes);
- for (ngood = 0; ngood < count; ++ngood) {
+ for (ngood = 0, ptr1 = buf1, ptr2 = buf2; ngood < count; ++ngood) {
if (size == 4) {
- word1 = *(u32 *)buf1;
- word2 = *(u32 *)buf2;
+ word1 = *(u32 *)ptr1;
+ word2 = *(u32 *)ptr2;
} else if (MEM_SUPPORT_64BIT_DATA && size == 8) {
- word1 = *(ulong *)buf1;
- word2 = *(ulong *)buf2;
+ word1 = *(ulong *)ptr1;
+ word2 = *(ulong *)ptr2;
} else if (size == 2) {
- word1 = *(u16 *)buf1;
- word2 = *(u16 *)buf2;
+ word1 = *(u16 *)ptr1;
+ word2 = *(u16 *)ptr2;
} else {
- word1 = *(u8 *)buf1;
- word2 = *(u8 *)buf2;
+ word1 = *(u8 *)ptr1;
+ word2 = *(u8 *)ptr2;
}
if (word1 != word2) {
- ulong offset = buf1 - base;
+ ulong offset = ptr1 - base;
printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n",
type, (ulong)(addr1 + offset), size, word1,
type, (ulong)(addr2 + offset), size, word2);
@@ -293,8 +293,8 @@
break;
}
- buf1 += size;
- buf2 += size;
+ ptr1 += size;
+ ptr2 += size;
/* reset watchdog from time to time */
if ((ngood % (64 << 10)) == 0)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 7244a90..fe7899e 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -8,12 +8,14 @@
#include <command.h>
#include <console.h>
#include <display_options.h>
+#include <mapmem.h>
#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <sparse_format.h>
#include <image-sparse.h>
#include <vsprintf.h>
+#include <linux/ctype.h>
static int curr_device = -1;
@@ -238,7 +240,7 @@
if (argc == 5)
key_addr = (void *)hextoul(argv[4], NULL);
- printf("\nMMC RPMB read: dev # %d, block # %d, count %d ... ",
+ printf("MMC RPMB read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
n = mmc_rpmb_read(mmc, addr, blk, cnt, key_addr);
@@ -265,7 +267,7 @@
cnt = hextoul(argv[3], NULL);
key_addr = (void *)hextoul(argv[4], NULL);
- printf("\nMMC RPMB write: dev # %d, block # %d, count %d ... ",
+ printf("MMC RPMB write: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
n = mmc_rpmb_write(mmc, addr, blk, cnt, key_addr);
@@ -349,12 +351,12 @@
{
struct mmc *mmc;
u32 blk, cnt, n;
- void *addr;
+ void *ptr;
if (argc != 4)
return CMD_RET_USAGE;
- addr = (void *)hextoul(argv[1], NULL);
+ ptr = map_sysmem(hextoul(argv[1], NULL), 0);
blk = hextoul(argv[2], NULL);
cnt = hextoul(argv[3], NULL);
@@ -362,11 +364,12 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC read: dev # %d, block # %d, count %d ... ",
+ printf("MMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
- n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ptr);
printf("%d blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR");
+ unmap_sysmem(ptr);
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
@@ -411,7 +414,7 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC Sparse write: dev # %d, block # %d ... ",
+ printf("MMC Sparse write: dev # %d, block # %d ... ",
curr_device, blk);
if (mmc_getwp(mmc) == 1) {
@@ -442,12 +445,12 @@
{
struct mmc *mmc;
u32 blk, cnt, n;
- void *addr;
+ void *ptr;
if (argc != 4)
return CMD_RET_USAGE;
- addr = (void *)hextoul(argv[1], NULL);
+ ptr = map_sysmem(hextoul(argv[1], NULL), 0);
blk = hextoul(argv[2], NULL);
cnt = hextoul(argv[3], NULL);
@@ -455,15 +458,16 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC write: dev # %d, block # %d, count %d ... ",
+ printf("MMC write: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
if (mmc_getwp(mmc) == 1) {
printf("Error: card is write protected!\n");
return CMD_RET_FAILURE;
}
- n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, ptr);
printf("%d blocks written: %s\n", n, (n == cnt) ? "OK" : "ERROR");
+ unmap_sysmem(ptr);
return (n == cnt) ? CMD_RET_SUCCESS : CMD_RET_FAILURE;
}
@@ -472,19 +476,27 @@
int argc, char *const argv[])
{
struct mmc *mmc;
+ struct disk_partition info;
u32 blk, cnt, n;
- if (argc != 3)
+ if (argc < 2 || argc > 3)
return CMD_RET_USAGE;
- blk = hextoul(argv[1], NULL);
- cnt = hextoul(argv[2], NULL);
-
mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
+
+ if (argc == 3) {
+ blk = hextoul(argv[1], NULL);
+ cnt = hextoul(argv[2], NULL);
+ } else if (part_get_info_by_name(mmc_get_blk_desc(mmc), argv[1], &info) >= 0) {
+ blk = info.start;
+ cnt = info.size;
+ } else {
+ return CMD_RET_FAILURE;
+ }
- printf("\nMMC erase: dev # %d, block # %d, count %d ... ",
+ printf("MMC erase: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
if (mmc_getwp(mmc) == 1) {
@@ -918,8 +930,9 @@
printf("EXT_CSD[179], PARTITION_CONFIG:\n"
"BOOT_ACK: 0x%x\n"
- "BOOT_PARTITION_ENABLE: 0x%x\n"
- "PARTITION_ACCESS: 0x%x\n", ack, part, access);
+ "BOOT_PARTITION_ENABLE: 0x%x (%s)\n"
+ "PARTITION_ACCESS: 0x%x (%s)\n", ack, part, emmc_boot_part_names[part],
+ access, emmc_hwpart_names[access]);
return CMD_RET_SUCCESS;
}
@@ -948,9 +961,26 @@
if (argc == 2 || argc == 3)
return mmc_partconf_print(mmc, cmd_arg2(argc, argv));
+ /* BOOT_ACK */
ack = dectoul(argv[2], NULL);
- part_num = dectoul(argv[3], NULL);
- access = dectoul(argv[4], NULL);
+ /* BOOT_PARTITION_ENABLE */
+ if (!isdigit(*argv[3])) {
+ for (part_num = ARRAY_SIZE(emmc_boot_part_names) - 1; part_num > 0; part_num--) {
+ if (!strcmp(argv[3], emmc_boot_part_names[part_num]))
+ break;
+ }
+ } else {
+ part_num = dectoul(argv[3], NULL);
+ }
+ /* PARTITION_ACCESS */
+ if (!isdigit(*argv[4])) {
+ for (access = ARRAY_SIZE(emmc_hwpart_names) - 1; access > 0; access--) {
+ if (!strcmp(argv[4], emmc_hwpart_names[access]))
+ break;
+ }
+ } else {
+ access = dectoul(argv[4], NULL);
+ }
/* acknowledge to be sent during boot operation */
ret = mmc_set_part_conf(mmc, ack, part_num, access);
@@ -1271,6 +1301,7 @@
"mmc swrite addr blk#\n"
#endif
"mmc erase blk# cnt\n"
+ "mmc erase partname\n"
"mmc rescan [mode]\n"
"mmc part - lists available partition on current mmc device\n"
"mmc dev [dev] [part] [mode] - show or set current mmc device [partition] and set mode\n"
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index e3f21dd..5e4ffc4 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -223,8 +223,8 @@
#endif
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 7)
- part = 0;
+ if (part == EMMC_BOOT_PART_USER)
+ part = EMMC_HWPART_DEFAULT;
#ifdef CONFIG_BLK
err = blk_dselect_hwpart(blk_desc, part);
diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c
index 64ae2ad..32b7d04 100644
--- a/cmd/nvedit_efi.c
+++ b/cmd/nvedit_efi.c
@@ -15,7 +15,7 @@
#include <malloc.h>
#include <mapmem.h>
#include <rtc.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/kernel.h>
/*
diff --git a/cmd/read.c b/cmd/read.c
index af54bd1..8e21f00 100644
--- a/cmd/read.c
+++ b/cmd/read.c
@@ -20,7 +20,7 @@
struct disk_partition part_info;
ulong offset, limit;
uint blk, cnt, res;
- void *addr;
+ void *ptr;
int part;
if (argc != 6) {
@@ -33,7 +33,7 @@
if (part < 0)
return 1;
- addr = map_sysmem(hextoul(argv[3], NULL), 0);
+ ptr = map_sysmem(hextoul(argv[3], NULL), 0);
blk = hextoul(argv[4], NULL);
cnt = hextoul(argv[5], NULL);
@@ -48,13 +48,15 @@
if (cnt + blk > limit) {
printf("%s out of range\n", cmdtp->name);
+ unmap_sysmem(ptr);
return 1;
}
if (IS_ENABLED(CONFIG_CMD_WRITE) && !strcmp(cmdtp->name, "write"))
- res = blk_dwrite(dev_desc, offset + blk, cnt, addr);
+ res = blk_dwrite(dev_desc, offset + blk, cnt, ptr);
else
- res = blk_dread(dev_desc, offset + blk, cnt, addr);
+ res = blk_dread(dev_desc, offset + blk, cnt, ptr);
+ unmap_sysmem(ptr);
if (res != cnt) {
printf("%s error\n", cmdtp->name);
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 2b58b1c..16e3353 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -36,6 +36,14 @@
return CMD_RET_SUCCESS;
}
+static int do_rdcycle(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ printf("cycle = 0x%lx\n", csr_read(CSR_CYCLE));
+
+ return CMD_RET_SUCCESS;
+}
+
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -62,6 +70,8 @@
"", ""),
U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16,
"", ""),
+ U_BOOT_CMD_MKENT(rdcycle, CONFIG_SYS_MAXARGS, 1, do_rdcycle,
+ "", ""),
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -74,7 +84,8 @@
" compressed - compressed instruction\n"
" ebreak - breakpoint\n"
" ialign16 - 16 bit aligned instruction\n"
- " undefined - illegal instruction\n"
- " unaligned - load address misaligned\n");
+ " rdcycle - read cycle CSR\n"
+ " unaligned - load address misaligned\n"
+ " undefined - illegal instruction\n");
#include <exception.h>
diff --git a/cmd/sb.c b/cmd/sb.c
index 1aa5921..db485fd 100644
--- a/cmd/sb.c
+++ b/cmd/sb.c
@@ -14,8 +14,10 @@
char *const argv[])
{
#if CONFIG_IS_ENABLED(HANDOFF)
- if (gd->spl_handoff)
- printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic);
+ struct spl_handoff *handoff = handoff_get();
+
+ if (handoff)
+ printf("SPL handoff magic %lx\n", handoff->arch.magic);
else
printf("SPL handoff info not received\n");
diff --git a/cmd/sf.c b/cmd/sf.c
index f43a2e0..08e364e 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -10,6 +10,7 @@
#include <div64.h>
#include <dm.h>
#include <log.h>
+#include <lmb.h>
#include <malloc.h>
#include <mapmem.h>
#include <spi.h>
@@ -317,6 +318,13 @@
strncmp(argv[0], "write", 5) == 0) {
int read;
+ if (CONFIG_IS_ENABLED(LMB)) {
+ if (lmb_read_check(addr, len)) {
+ printf("ERROR: trying to overwrite reserved memory...\n");
+ return CMD_RET_FAILURE;
+ }
+ }
+
read = strncmp(argv[0], "read", 4) == 0;
if (read)
ret = spi_flash_read(flash, offset, len, buf);
diff --git a/cmd/upl.c b/cmd/upl.c
new file mode 100644
index 0000000..c974588
--- /dev/null
+++ b/cmd/upl.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Commands for UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <abuf.h>
+#include <alist.h>
+#include <command.h>
+#include <display_options.h>
+#include <mapmem.h>
+#include <string.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int do_upl_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct upl *upl = gd_upl();
+
+ printf("UPL state: %sactive\n", upl ? "" : "in");
+ if (!upl)
+ return 0;
+ if (argc > 1 && !strcmp("-v", argv[1])) {
+ int i;
+
+ printf("fit %lx\n", upl->fit);
+ printf("conf_offset %x\n", upl->conf_offset);
+ for (i = 0; i < upl->image.count; i++) {
+ const struct upl_image *img =
+ alist_get(&upl->image, i, struct upl_image);
+
+ printf("image %d: load %lx size %lx offset %x: %s\n", i,
+ img->load, img->size, img->offset,
+ img->description);
+ }
+ }
+
+ return 0;
+}
+
+static int do_upl_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct upl s_upl, *upl = &s_upl;
+ struct unit_test_state uts;
+ struct abuf buf;
+ oftree tree;
+ ulong addr;
+ int ret;
+
+ upl_get_test_data(&uts, upl);
+
+ log_debug("Writing UPL\n");
+ ret = upl_create_handoff_tree(upl, &tree);
+ if (ret) {
+ log_err("Failed to write (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ log_debug("Flattening\n");
+ ret = oftree_to_fdt(tree, &buf);
+ if (ret) {
+ log_err("Failed to write (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ addr = map_to_sysmem(abuf_data(&buf));
+ printf("UPL handoff written to %lx size %lx\n", addr, abuf_size(&buf));
+ if (env_set_hex("upladdr", addr) ||
+ env_set_hex("uplsize", abuf_size(&buf))) {
+ printf("Cannot set env var\n");
+ return CMD_RET_FAILURE;
+ }
+
+ log_debug("done\n");
+
+ return 0;
+}
+
+static int do_upl_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct upl s_upl, *upl = &s_upl;
+ oftree tree;
+ ulong addr;
+ int ret;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ addr = hextoul(argv[1], NULL);
+
+ printf("Reading UPL at %lx\n", addr);
+ tree = oftree_from_fdt(map_sysmem(addr, 0));
+ ret = upl_read_handoff(upl, tree);
+ if (ret) {
+ log_err("Failed to read (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+U_BOOT_LONGHELP(upl,
+ "info [-v] - Check UPL status\n"
+ "upl read <addr> - Read handoff information\n"
+ "upl write - Write handoff information");
+
+U_BOOT_CMD_WITH_SUBCMDS(upl, "Universal Payload support", upl_help_text,
+ U_BOOT_SUBCMD_MKENT(info, 2, 1, do_upl_info),
+ U_BOOT_SUBCMD_MKENT(read, 2, 1, do_upl_read),
+ U_BOOT_SUBCMD_MKENT(write, 1, 1, do_upl_write));
diff --git a/cmd/usb.c b/cmd/usb.c
index 16c081b..13a2996 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -560,17 +560,6 @@
}
#endif /* CONFIG_USB_STORAGE */
-static int do_usb_stop_keyboard(int force)
-{
-#if !defined CONFIG_DM_USB && defined CONFIG_USB_KEYBOARD
- if (usb_kbd_deregister(force) != 0) {
- printf("USB not stopped: usbkbd still using USB\n");
- return 1;
- }
-#endif
- return 0;
-}
-
static void do_usb_start(void)
{
bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
@@ -583,11 +572,6 @@
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
# endif
-#ifndef CONFIG_DM_USB
-# ifdef CONFIG_USB_KEYBOARD
- drv_usb_kbd_init();
-# endif
-#endif /* !CONFIG_DM_USB */
}
#ifdef CONFIG_DM_USB
@@ -633,8 +617,6 @@
if (strncmp(argv[1], "reset", 5) == 0) {
printf("resetting USB...\n");
- if (do_usb_stop_keyboard(1) != 0)
- return 1;
usb_stop();
do_usb_start();
return 0;
@@ -642,8 +624,6 @@
if (strncmp(argv[1], "stop", 4) == 0) {
if (argc != 2)
console_assign(stdin, "serial");
- if (do_usb_stop_keyboard(0) != 0)
- return 1;
printf("stopping USB..\n");
usb_stop();
return 0;
diff --git a/cmd/x86/hob.c b/cmd/x86/hob.c
index 2dd3080..d3713ce 100644
--- a/cmd/x86/hob.c
+++ b/cmd/x86/hob.c
@@ -5,7 +5,7 @@
#include <command.h>
#include <efi.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/global_data.h>
#include <asm/hob.h>
#include <asm/fsp/fsp_hob.h>
diff --git a/common/Kconfig b/common/Kconfig
index 83c81ed..957de0c 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -934,6 +934,7 @@
config UPDATE_COMMON
bool
select DFU_WRITE_ALT
+ imply CMD_TFTPBOOT
config UPDATE_TFTP
bool "Auto-update using fitImage via TFTP"
@@ -986,7 +987,8 @@
help
If non-zero, a backup bootloader message starting at this offset in
the partition will tried in the event that the primary one (starting
- at offset 0) fails its checksum.
+ at offset 0) fails its checksum. The offset is in bytes and must be
+ multiple of the block size.
endmenu
diff --git a/common/board_f.c b/common/board_f.c
index 30d7fbf..154675d 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -40,6 +40,7 @@
#include <sysreset.h>
#include <timer.h>
#include <trace.h>
+#include <upl.h>
#include <video.h>
#include <watchdog.h>
#include <asm/cache.h>
@@ -304,17 +305,6 @@
return 0;
}
-static int setup_spl_handoff(void)
-{
-#if CONFIG_IS_ENABLED(HANDOFF)
- gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
- sizeof(struct spl_handoff));
- debug("Found SPL hand-off info %p\n", gd->spl_handoff);
-#endif
-
- return 0;
-}
-
__weak int arch_cpu_init(void)
{
return 0;
@@ -350,7 +340,7 @@
static int setup_dest_addr(void)
{
- debug("Monitor len: %08lX\n", gd->mon_len);
+ debug("Monitor len: %08x\n", gd->mon_len);
/*
* Ram is setup, size stored in gd !!
*/
@@ -487,7 +477,7 @@
gd->relocaddr &= ~(65536 - 1);
#endif
- debug("Reserving %ldk for U-Boot at: %08lx\n",
+ debug("Reserving %dk for U-Boot at: %08lx\n",
gd->mon_len >> 10, gd->relocaddr);
}
@@ -574,12 +564,15 @@
* section, then it will be relocated with other data.
*/
if (gd->fdt_blob) {
- gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
+ gd->boardf->fdt_size =
+ ALIGN(fdt_totalsize(gd->fdt_blob), 32);
- gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
- gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
+ gd->start_addr_sp = reserve_stack_aligned(
+ gd->boardf->fdt_size);
+ gd->boardf->new_fdt = map_sysmem(gd->start_addr_sp,
+ gd->boardf->fdt_size);
debug("Reserving %lu Bytes for FDT at: %08lx\n",
- gd->fdt_size, gd->start_addr_sp);
+ gd->boardf->fdt_size, gd->start_addr_sp);
}
}
@@ -592,7 +585,7 @@
int size = bootstage_get_size();
gd->start_addr_sp = reserve_stack_aligned(size);
- gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
+ gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size);
debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
gd->start_addr_sp);
#endif
@@ -623,8 +616,8 @@
/* Align to a 4KB boundary for easier reading of addresses */
gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
- gd->new_bloblist = map_sysmem(gd->start_addr_sp,
- CONFIG_BLOBLIST_SIZE_RELOC);
+ gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp,
+ CONFIG_BLOBLIST_SIZE_RELOC);
#endif
return 0;
@@ -667,10 +660,10 @@
static int reloc_fdt(void)
{
if (!IS_ENABLED(CONFIG_OF_EMBED)) {
- if (gd->new_fdt) {
- memcpy(gd->new_fdt, gd->fdt_blob,
+ if (gd->boardf->new_fdt) {
+ memcpy(gd->boardf->new_fdt, gd->fdt_blob,
fdt_totalsize(gd->fdt_blob));
- gd->fdt_blob = gd->new_fdt;
+ gd->fdt_blob = gd->boardf->new_fdt;
}
}
@@ -682,15 +675,8 @@
#ifdef CONFIG_BOOTSTAGE
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- if (gd->new_bootstage) {
- int size = bootstage_get_size();
-
- debug("Copying bootstage from %p to %p, size %x\n",
- gd->bootstage, gd->new_bootstage, size);
- memcpy(gd->new_bootstage, gd->bootstage, size);
- gd->bootstage = gd->new_bootstage;
- bootstage_relocate();
- }
+ if (gd->boardf->new_bootstage)
+ bootstage_relocate(gd->boardf->new_bootstage);
#endif
return 0;
@@ -707,10 +693,11 @@
debug("Not relocating bloblist\n");
return 0;
}
- if (gd->new_bloblist) {
+ if (gd->boardf->new_bloblist) {
debug("Copying bloblist from %p to %p, size %x\n",
- gd->bloblist, gd->new_bloblist, gd->bloblist->total_size);
- return bloblist_reloc(gd->new_bloblist,
+ gd->bloblist, gd->boardf->new_bloblist,
+ gd->bloblist->total_size);
+ return bloblist_reloc(gd->boardf->new_bloblist,
CONFIG_BLOBLIST_SIZE_RELOC);
}
#endif
@@ -856,6 +843,26 @@
__weak int clear_bss(void)
{
+ return 0;
+}
+
+static int initf_upl(void)
+{
+ struct upl *upl;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_UPL_IN) || !(gd->flags & GD_FLG_UPL))
+ return 0;
+
+ upl = malloc(sizeof(struct upl));
+ if (upl)
+ ret = upl_read_handoff(upl, oftree_default());
+ if (ret) {
+ printf("UPL handoff: read failure (err=%dE)\n", ret);
+ return ret;
+ }
+ gd_set_upl(upl);
+
return 0;
}
@@ -868,11 +875,11 @@
trace_early_init,
#endif
initf_malloc,
+ initf_upl,
log_init,
initf_bootstage, /* uses its own timer, so does not need DM */
event_init,
bloblist_maybe_init,
- setup_spl_handoff,
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
console_record_init,
#endif
@@ -1005,8 +1012,11 @@
void board_init_f(ulong boot_flags)
{
+ struct board_f boardf;
+
gd->flags = boot_flags;
- gd->have_console = 0;
+ gd->flags &= ~GD_FLG_HAVE_CONSOLE;
+ gd->boardf = &boardf;
if (initcall_run_list(init_sequence_f))
hang();
diff --git a/common/board_r.c b/common/board_r.c
index d4ba245..4faaa20 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -22,6 +22,7 @@
#include <hang.h>
#include <image.h>
#include <irq_func.h>
+#include <lmb.h>
#include <log.h>
#include <net.h>
#include <asm/cache.h>
@@ -192,7 +193,7 @@
ulong start;
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
- debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+ debug("Pre-reloc malloc() used %#x bytes (%d KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
/* The malloc area is immediately below the monitor copy in DRAM */
@@ -510,6 +511,14 @@
}
#endif
+static int initr_lmb(void)
+{
+ if (CONFIG_IS_ENABLED(LMB))
+ return lmb_init();
+ else
+ return 0;
+}
+
static int dm_announce(void)
{
int device_count;
@@ -521,6 +530,8 @@
uclass_count);
if (CONFIG_IS_ENABLED(OF_REAL))
printf(", devicetree: %s", fdtdec_get_srcname());
+ if (CONFIG_IS_ENABLED(UPL))
+ printf(", universal payload active");
printf("\n");
if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) &&
(gd->fdt_src == FDTSRC_SEPARATE ||
@@ -610,6 +621,7 @@
#ifdef CONFIG_CLOCKS
set_cpu_clk_info, /* Setup clock information */
#endif
+ initr_lmb,
#ifdef CONFIG_EFI_LOADER
efi_memory_init,
#endif
diff --git a/common/bootstage.c b/common/bootstage.c
index b6c268d..49acc90 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -54,12 +54,16 @@
u32 next_id; /* Next ID to use for bootstage */
};
-int bootstage_relocate(void)
+int bootstage_relocate(void *to)
{
- struct bootstage_data *data = gd->bootstage;
+ struct bootstage_data *data;
int i;
char *ptr;
+ debug("Copying bootstage from %p to %p\n", gd->bootstage, to);
+ memcpy(to, gd->bootstage, sizeof(struct bootstage_data));
+ data = gd->bootstage = to;
+
/* Figure out where to relocate the strings to */
ptr = (char *)(data + 1);
diff --git a/common/cli_hush_modern.c b/common/cli_hush_modern.c
index cd88c9d..deb61c3 100644
--- a/common/cli_hush_modern.c
+++ b/common/cli_hush_modern.c
@@ -25,7 +25,7 @@
/*
* BusyBox Version: UPDATE THIS WHEN PULLING NEW UPSTREAM REVISION!
*/
-#define BB_VER "1.35.0.git7d1c7d833785"
+#define BB_VER "1.37.0.git23da5c4b716b"
/*
* Define hush features by the names used upstream.
diff --git a/common/cli_hush_upstream.c b/common/cli_hush_upstream.c
index 7874b39..ab5aa5f 100644
--- a/common/cli_hush_upstream.c
+++ b/common/cli_hush_upstream.c
@@ -1651,12 +1651,22 @@
newfd = fcntl(fd, F_DUPFD_CLOEXEC, avoid_fd + 1);
if (newfd >= 0) {
if (F_DUPFD_CLOEXEC == F_DUPFD) /* if old libc (w/o F_DUPFD_CLOEXEC) */
- fcntl(newfd, F_SETFD, FD_CLOEXEC);
+ close_on_exec_on(newfd);
} else { /* newfd < 0 */
if (errno == EBUSY)
goto repeat;
if (errno == EINTR)
goto repeat;
+ if (errno != EBADF) {
+ /* "echo >&9999" gets EINVAL trying to save fd 1 to above 9999.
+ * We could try saving it _below_ 9999 instead (how?), but
+ * this probably means that dup2(9999,1) to effectuate >&9999
+ * would also not work: fd 9999 can't exist.
+ * (This differs from "echo >&99" where saving works, but
+ * subsequent dup2(99,1) fails if fd 99 is not open).
+ */
+ bb_perror_msg("fcntl(%d,F_DUPFD,%d)", fd, avoid_fd + 1);
+ }
}
return newfd;
}
@@ -1677,7 +1687,7 @@
xfunc_die();
}
if (F_DUPFD_CLOEXEC == F_DUPFD) /* if old libc (w/o F_DUPFD_CLOEXEC) */
- fcntl(newfd, F_SETFD, FD_CLOEXEC);
+ close_on_exec_on(newfd);
close(fd);
return newfd;
}
@@ -5851,6 +5861,15 @@
}
o_free_and_set_NULL(&ctx.word);
done_pipe(&ctx, PIPE_SEQ);
+
+ /* Do we sit inside of any if's, loops or case's? */
+ if (HAS_KEYWORDS
+ IF_HAS_KEYWORDS(&& (ctx.ctx_res_w != RES_NONE || ctx.old_flag != 0))
+ ) {
+ syntax_error_unterm_str("compound statement");
+ goto parse_error_exitcode1;
+ }
+
pi = ctx.list_head;
/* If we got nothing... */
/* (this makes bare "&" cmd a no-op.
@@ -5873,7 +5892,7 @@
// *heredoc_cnt_ptr = heredoc_cnt;
debug_leave();
debug_printf_heredoc("parse_stream return heredoc_cnt:%d\n", heredoc_cnt);
- debug_printf_parse("parse_stream return %p\n", pi);
+ debug_printf_parse("parse_stream return %p: EOF\n", pi);
return pi;
}
@@ -8384,10 +8403,16 @@
if (sq) for (; sq[i].orig_fd >= 0; i++) {
/* If we collide with an already moved fd... */
if (fd == sq[i].moved_to) {
- sq[i].moved_to = dup_CLOEXEC(sq[i].moved_to, avoid_fd);
- debug_printf_redir("redirect_fd %d: already busy, moving to %d\n", fd, sq[i].moved_to);
- if (sq[i].moved_to < 0) /* what? */
- xfunc_die();
+ moved_to = dup_CLOEXEC(sq[i].moved_to, avoid_fd);
+ debug_printf_redir("redirect_fd %d: already busy, moving to %d\n", fd, moved_to);
+ if (moved_to < 0) {
+ /* "echo 2>/dev/tty 10>&9999" testcase:
+ * We move fd 2 to 10, then discover we need to move fd 10
+ * (and not hit 9999) and the latter fails.
+ */
+ return NULL; /* fcntl failed */
+ }
+ sq[i].moved_to = moved_to;
return sq;
}
if (fd == sq[i].orig_fd) {
@@ -8401,7 +8426,7 @@
moved_to = dup_CLOEXEC(fd, avoid_fd);
debug_printf_redir("redirect_fd %d: previous fd is moved to %d (-1 if it was closed)\n", fd, moved_to);
if (moved_to < 0 && errno != EBADF)
- xfunc_die();
+ return NULL; /* fcntl failed (not because fd is closed) */
return append_squirrel(sq, i, fd, moved_to);
}
@@ -8434,6 +8459,8 @@
*/
static int save_fd_on_redirect(int fd, int avoid_fd, struct squirrel **sqp)
{
+ struct squirrel *new_squirrel;
+
if (avoid_fd < 9) /* the important case here is that it can be -1 */
avoid_fd = 9;
@@ -8497,7 +8524,10 @@
}
/* Check whether it collides with any open fds (e.g. stdio), save fds as needed */
- *sqp = add_squirrel(*sqp, fd, avoid_fd);
+ new_squirrel = add_squirrel(*sqp, fd, avoid_fd);
+ if (!new_squirrel)
+ return -1; /* redirect error */
+ *sqp = new_squirrel;
return 0; /* "we did not close fd" */
}
@@ -8568,8 +8598,11 @@
return 0;
}
-/* squirrel != NULL means we squirrel away copies of stdin, stdout,
- * and stderr if they are redirected. */
+/* sqp != NULL means we squirrel away copies of stdin, stdout,
+ * and stderr if they are redirected.
+ * If redirection fails, return 1. This will make caller
+ * skip command execution and restore already created redirect fds.
+ */
static int setup_redirects(struct command *prog, struct squirrel **sqp)
{
struct redir_struct *redir;
@@ -8580,7 +8613,8 @@
if (redir->rd_type == REDIRECT_HEREDOC2) {
/* "rd_fd<<HERE" case */
- save_fd_on_redirect(redir->rd_fd, /*avoid:*/ 0, sqp);
+ if (save_fd_on_redirect(redir->rd_fd, /*avoid:*/ 0, sqp) < 0)
+ return 1;
/* for REDIRECT_HEREDOC2, rd_filename holds _contents_
* of the heredoc */
debug_printf_redir("set heredoc '%s'\n",
@@ -8600,7 +8634,7 @@
* "cmd > <file" (2nd redirect starts too early)
*/
syntax_error("invalid redirect");
- continue;
+ return 1;
}
mode = redir_table[redir->rd_type].mode;
p = expand_string_to_string(redir->rd_filename,
@@ -8615,7 +8649,9 @@
*/
return 1;
}
- if (newfd == redir->rd_fd && sqp) {
+ if (newfd == redir->rd_fd && sqp
+ && sqp != ERR_PTR /* not a redirect in "exec" */
+ ) {
/* open() gave us precisely the fd we wanted.
* This means that this fd was not busy
* (not opened to anywhere).
@@ -8637,6 +8673,8 @@
/* if "N>&-": close redir->rd_fd (newfd is REDIRFD_CLOSE) */
closed = save_fd_on_redirect(redir->rd_fd, /*avoid:*/ newfd, sqp);
+ if (closed < 0)
+ return 1; /* error */
if (newfd == REDIRFD_CLOSE) {
/* "N>&-" means "close me" */
if (!closed) {
@@ -8650,13 +8688,16 @@
* and second redirect closes 3! Restore code then closes 3 again.
*/
} else {
- /* if newfd is a script fd or saved fd, simulate EBADF */
+ /* if newfd is a script fd or saved fd, do not allow to use it */
if (internally_opened_fd(newfd, sqp && sqp != ERR_PTR ? *sqp : NULL)) {
- //errno = EBADF;
- //bb_perror_msg_and_die("can't duplicate file descriptor");
- newfd = -1; /* same effect as code above */
+ bb_error_msg("fd#%d is not open", newfd);
+ return 1;
+ }
+ if (dup2(newfd, redir->rd_fd) < 0) {
+ /* "echo >&99" testcase */
+ bb_perror_msg("dup2(%d,%d)", newfd, redir->rd_fd);
+ return 1;
}
- xdup2(newfd, redir->rd_fd);
if (redir->rd_dup == REDIRFD_TO_FILE)
/* "rd_fd > FILE" */
close(newfd);
@@ -9731,6 +9772,7 @@
return rcode;
}
#endif
+#endif /* !__U_BOOT__ */
/* Start all the jobs, but don't wait for anything to finish.
* See checkjobs().
@@ -9758,6 +9800,38 @@
* backgrounded: cmd & { list } &
* subshell: ( list ) [&]
*/
+static void set_G_ifs(void)
+{
+ /* Testcase: set -- q w e; (IFS='' echo "$*"; IFS=''; echo "$*"); echo "$*"
+ * Result should be 3 lines: q w e, qwe, q w e
+ */
+ if (G.ifs_whitespace != G.ifs)
+ free(G.ifs_whitespace);
+ G.ifs = get_local_var_value("IFS");
+ if (G.ifs) {
+ char *p;
+ G.ifs_whitespace = (char*)G.ifs;
+ p = skip_whitespace(G.ifs);
+ if (*p) {
+ /* Not all $IFS is whitespace */
+ char *d;
+ int len = p - G.ifs;
+ p = skip_non_whitespace(p);
+ G.ifs_whitespace = xmalloc(len + strlen(p) + 1); /* can overestimate */
+ d = mempcpy(G.ifs_whitespace, G.ifs, len);
+ while (*p) {
+ if (isspace(*p))
+ *d++ = *p;
+ p++;
+ }
+ *d = '\0';
+ }
+ } else {
+ G.ifs = defifs;
+ G.ifs_whitespace = (char*)G.ifs;
+ }
+}
+#ifndef __U_BOOT__
#if !ENABLE_HUSH_MODE_X
#define redirect_and_varexp_helper(command, sqp, argv_expanded) \
redirect_and_varexp_helper(command, sqp)
@@ -9810,34 +9884,7 @@
debug_printf_exec("run_pipe start: members:%d\n", pi->num_cmds);
debug_enter();
- /* Testcase: set -- q w e; (IFS='' echo "$*"; IFS=''; echo "$*"); echo "$*"
- * Result should be 3 lines: q w e, qwe, q w e
- */
- if (G.ifs_whitespace != G.ifs)
- free(G.ifs_whitespace);
- G.ifs = get_local_var_value("IFS");
- if (G.ifs) {
- char *p;
- G.ifs_whitespace = (char*)G.ifs;
- p = skip_whitespace(G.ifs);
- if (*p) {
- /* Not all $IFS is whitespace */
- char *d;
- int len = p - G.ifs;
- p = skip_non_whitespace(p);
- G.ifs_whitespace = xmalloc(len + strlen(p) + 1); /* can overestimate */
- d = mempcpy(G.ifs_whitespace, G.ifs, len);
- while (*p) {
- if (isspace(*p))
- *d++ = *p;
- p++;
- }
- *d = '\0';
- }
- } else {
- G.ifs = defifs;
- G.ifs_whitespace = (char*)G.ifs;
- }
+ set_G_ifs();
#ifndef __U_BOOT__
IF_HUSH_JOB(pi->pgrp = -1;)
@@ -10362,6 +10409,8 @@
debug_enter();
#endif /* !__U_BOOT__ */
+ set_G_ifs();
+
#if ENABLE_HUSH_LOOPS
/* Check syntax for "for" */
{
@@ -11377,7 +11426,7 @@
G_interactive_fd = dup_CLOEXEC(STDIN_FILENO, 254);
if (G_interactive_fd < 0) {
/* try to dup to any fd */
- G_interactive_fd = dup(STDIN_FILENO);
+ G_interactive_fd = dup_CLOEXEC(STDIN_FILENO, -1);
if (G_interactive_fd < 0) {
/* give up */
G_interactive_fd = 0;
@@ -11387,8 +11436,6 @@
}
debug_printf("interactive_fd:%d\n", G_interactive_fd);
if (G_interactive_fd) {
- close_on_exec_on(G_interactive_fd);
-
if (G_saved_tty_pgrp) {
/* If we were run as 'hush &', sleep until we are
* in the foreground (tty pgrp == our pgrp).
@@ -11463,9 +11510,6 @@
G_interactive_fd = 0;
}
}
- if (G_interactive_fd) {
- close_on_exec_on(G_interactive_fd);
- }
install_special_sighandlers();
#else
/* We have interactiveness code disabled */
diff --git a/common/console.c b/common/console.c
index 63f7800..c9e206a 100644
--- a/common/console.c
+++ b/common/console.c
@@ -4,6 +4,8 @@
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*/
+#define LOG_CATEGORY LOGC_CONSOLE
+
#include <console.h>
#include <debug_uart.h>
#include <display_options.h>
@@ -189,6 +191,7 @@
/* Assign the new device (leaving the existing one started) */
stdio_devices[file] = dev;
+#ifndef CONFIG_SPL_BUILD
/*
* Update monitor functions
* (to use the console stuff by other applications)
@@ -206,7 +209,7 @@
break;
}
break;
-
+#endif
default: /* Invalid file ID */
error = -1;
}
@@ -586,7 +589,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return 0;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return 0;
ch = console_record_getc();
@@ -607,7 +610,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return 0;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return 0;
if (console_record_tstc())
@@ -715,7 +718,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return pre_console_putc(c);
if (gd->flags & GD_FLG_DEVINIT) {
@@ -759,7 +762,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return pre_console_puts(s);
if (gd->flags & GD_FLG_DEVINIT) {
@@ -793,7 +796,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return;
if (gd->flags & GD_FLG_DEVINIT) {
@@ -845,6 +848,8 @@
{
if (gd->flags & GD_FLG_RECORD_OVF)
return -ENOSPC;
+ if (console_record_isempty())
+ return -ENOENT;
return membuff_readline((struct membuff *)&gd->console_out, str,
maxlen, '\0', false);
@@ -872,7 +877,7 @@
static int ctrlc_was_pressed = 0;
int ctrlc(void)
{
- if (!ctrlc_disabled && gd->have_console) {
+ if (!ctrlc_disabled && (gd->flags & GD_FLG_HAVE_CONSOLE)) {
if (tstc()) {
switch (getchar()) {
case 0x03: /* ^C - Control C */
@@ -1011,7 +1016,7 @@
/* Called before relocation - use serial functions */
int console_init_f(void)
{
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
console_update_silent();
@@ -1239,3 +1244,37 @@
}
#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
+
+int console_remove_by_name(const char *name)
+{
+ int err = 0;
+
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
+ int fnum;
+
+ log_debug("removing console device %s\n", name);
+ for (fnum = 0; fnum < MAX_FILES; fnum++) {
+ struct stdio_dev **src, **dest;
+ int i;
+
+ log_debug("file %d: %d devices: ", fnum, cd_count[fnum]);
+ src = console_devices[fnum];
+ dest = src;
+ for (i = 0; i < cd_count[fnum]; i++, src++) {
+ struct stdio_dev *sdev = *src;
+ int ret = 0;
+
+ if (!strcmp(sdev->name, name))
+ ret = stdio_deregister_dev(sdev, true);
+ else
+ *dest++ = *src;
+ if (ret && !err)
+ err = ret;
+ }
+ cd_count[fnum] = dest - console_devices[fnum];
+ log_debug("now %d\n", cd_count[fnum]);
+ }
+#endif /* CONSOLE_MUX */
+
+ return err;
+}
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 62e8557..1ac7ce3 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -386,8 +386,8 @@
/* pad request bytes into a usable size */
#define request2size(req) \
- (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \
- (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \
+ ((((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \
+ (MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \
(((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK)))
/* Check if m has acceptable alignment */
@@ -581,6 +581,9 @@
ulong old = mem_malloc_brk;
ulong new = old + increment;
+ if ((new < mem_malloc_start) || (new > mem_malloc_end))
+ return (void *)MORECORE_FAILURE;
+
/*
* if we are giving memory back make sure we clear it out since
* we set MORECORE_CLEARS to 1
@@ -588,9 +591,6 @@
if (increment < 0)
memset((void *)new, 0, -increment);
- if ((new < mem_malloc_start) || (new > mem_malloc_end))
- return (void *)MORECORE_FAILURE;
-
mem_malloc_brk = new;
return (void *)old;
@@ -1274,7 +1274,8 @@
return NULL;
}
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
nb = request2size(bytes); /* padded request size; */
@@ -1687,7 +1688,8 @@
}
#endif
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc_impl(bytes);
@@ -1698,6 +1700,10 @@
panic("pre-reloc realloc() is not supported");
}
#endif
+ if (CONFIG_IS_ENABLED(UNIT_TEST) && malloc_testing) {
+ if (--malloc_max_allocs < 0)
+ return NULL;
+ }
newp = oldp = mem2chunk(oldmem);
newsize = oldsize = chunksize(oldp);
@@ -1907,7 +1913,8 @@
mchunkptr remainder; /* spare room at end to split off */
long remainder_size; /* its size */
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
diff --git a/common/flash.c b/common/flash.c
index 24ddc8b..fd1b4dd 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -8,7 +8,7 @@
#include <flash.h>
#include <log.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/string.h>
#include <mtd/cfi_flash.h>
@@ -110,13 +110,13 @@
* Make sure all target addresses are within Flash bounds,
* and no protected sectors are hit.
* Returns:
- * ERR_OK 0 - OK
- * ERR_TIMEOUT 1 - write timeout
- * ERR_NOT_ERASED 2 - Flash not erased
- * ERR_PROTECTED 4 - target range includes protected sectors
- * ERR_INVAL 8 - target address not in Flash memory
- * ERR_ALIGN 16 - target address not aligned on boundary
- * (only some targets require alignment)
+ * FL_ERR_OK 0 - OK
+ * FL_ERR_TIMEOUT 1 - write timeout
+ * FL_ERR_NOT_ERASED 2 - Flash not erased
+ * FL_ERR_PROTECTED 4 - target range includes protected sectors
+ * FL_ERR_INVAL 8 - target address not in Flash memory
+ * FL_ERR_ALIGN 16 - target address not aligned on boundary
+ * (only some targets require alignment)
*/
int
flash_write(char *src, ulong addr, ulong cnt)
@@ -131,11 +131,11 @@
__maybe_unused ulong cnt_orig = cnt;
if (cnt == 0) {
- return (ERR_OK);
+ return (FL_ERR_OK);
}
if (!info_first || !info_last) {
- return (ERR_INVAL);
+ return (FL_ERR_INVAL);
}
for (info = info_first; info <= info_last; ++info) {
@@ -146,7 +146,7 @@
if ((end >= info->start[i]) && (addr < e_addr) &&
(info->protect[i] != 0) ) {
- return (ERR_PROTECTED);
+ return (FL_ERR_PROTECTED);
}
}
}
@@ -169,11 +169,11 @@
#if defined(CONFIG_FLASH_VERIFY)
if (memcmp(src_orig, addr_orig, cnt_orig)) {
printf("\nVerify failed!\n");
- return ERR_PROG_ERROR;
+ return FL_ERR_PROG_ERROR;
}
#endif /* CONFIG_SYS_FLASH_VERIFY_AFTER_WRITE */
- return (ERR_OK);
+ return (FL_ERR_OK);
}
/*-----------------------------------------------------------------------
@@ -182,33 +182,33 @@
void flash_perror(int err)
{
switch (err) {
- case ERR_OK:
+ case FL_ERR_OK:
break;
- case ERR_TIMEOUT:
+ case FL_ERR_TIMEOUT:
puts ("Timeout writing to Flash\n");
break;
- case ERR_NOT_ERASED:
+ case FL_ERR_NOT_ERASED:
puts ("Flash not Erased\n");
break;
- case ERR_PROTECTED:
+ case FL_ERR_PROTECTED:
puts ("Can't write to protected Flash sectors\n");
break;
- case ERR_INVAL:
+ case FL_ERR_INVAL:
puts ("Outside available Flash\n");
break;
- case ERR_ALIGN:
+ case FL_ERR_ALIGN:
puts ("Start and/or end address not on sector boundary\n");
break;
- case ERR_UNKNOWN_FLASH_VENDOR:
+ case FL_ERR_UNKNOWN_FLASH_VENDOR:
puts ("Unknown Vendor of Flash\n");
break;
- case ERR_UNKNOWN_FLASH_TYPE:
+ case FL_ERR_UNKNOWN_FLASH_TYPE:
puts ("Unknown Type of Flash\n");
break;
- case ERR_PROG_ERROR:
+ case FL_ERR_PROG_ERROR:
puts ("General Flash Programming Error\n");
break;
- case ERR_ABORTED:
+ case FL_ERR_ABORTED:
puts("Flash Programming Aborted\n");
break;
default:
diff --git a/common/hwconfig.c b/common/hwconfig.c
index afaa6cb..25a8cd5 100644
--- a/common/hwconfig.c
+++ b/common/hwconfig.c
@@ -77,7 +77,13 @@
/* if we are passed a buffer use it, otherwise try the environment */
if (!env_hwconfig) {
- if (!(gd->flags & GD_FLG_ENV_READY) && gd->env_valid != ENV_VALID) {
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+ if (!(gd->flags & GD_FLG_ENV_READY) &&
+ gd->env_valid != ENV_VALID)
+#else
+ if (true)
+#endif
+ {
printf("WARNING: Calling __hwconfig without a buffer "
"and before environment is ready\n");
return NULL;
diff --git a/common/init/handoff.c b/common/init/handoff.c
index a7cd065..86c020e 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -5,6 +5,7 @@
* Copyright 2018 Google, Inc
*/
+#include <bloblist.h>
#include <handoff.h>
#include <asm/global_data.h>
@@ -38,3 +39,14 @@
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
}
+
+struct spl_handoff *handoff_get(void)
+{
+ struct spl_handoff *handoff;
+
+ handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
+ sizeof(struct spl_handoff));
+ debug("Found SPL hand-off info %p\n", handoff);
+
+ return handoff;
+}
diff --git a/common/log.c b/common/log.c
index dfee250..b83a661 100644
--- a/common/log.c
+++ b/common/log.c
@@ -31,6 +31,7 @@
"event",
"fs",
"expo",
+ "console",
};
_Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE,
diff --git a/common/log_console.c b/common/log_console.c
index c27101b..9376baa 100644
--- a/common/log_console.c
+++ b/common/log_console.c
@@ -38,10 +38,10 @@
printf("%d-", rec->line);
if (fmt & BIT(LOGF_FUNC)) {
if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) {
- printf("%s()", rec->func);
+ printf("%s()", rec->func ?: "?");
} else {
printf("%*s()", CONFIG_LOGF_FUNC_PAD,
- rec->func);
+ rec->func ?: "?");
}
}
}
diff --git a/common/log_syslog.c b/common/log_syslog.c
index d01bb74..0dcb5f7 100644
--- a/common/log_syslog.c
+++ b/common/log_syslog.c
@@ -88,7 +88,7 @@
if (fmt & BIT(LOGF_LINE))
append(&ptr, msg_end, "%d-", rec->line);
if (fmt & BIT(LOGF_FUNC))
- append(&ptr, msg_end, "%s()", rec->func);
+ append(&ptr, msg_end, "%s()", rec->func ?: "?");
if (fmt & BIT(LOGF_MSG))
append(&ptr, msg_end, "%s%s",
fmt != BIT(LOGF_MSG) ? " " : "", rec->msg);
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 4e6d795..5a8ec53 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -23,7 +23,7 @@
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
new_ptr = addr + bytes - gd->malloc_base;
- log_debug("size=%lx, ptr=%lx, limit=%lx: ", (ulong)bytes, new_ptr,
+ log_debug("size=%lx, ptr=%lx, limit=%x: ", (ulong)bytes, new_ptr,
gd->malloc_limit);
if (new_ptr > gd->malloc_limit) {
log_err("alloc space exhausted\n");
@@ -87,6 +87,6 @@
void malloc_simple_info(void)
{
- log_info("malloc_simple: %lx bytes used, %lx remain\n", gd->malloc_ptr,
+ log_info("malloc_simple: %x bytes used, %x remain\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr);
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c08ff06..137f94a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -78,6 +78,7 @@
hex "Maximum size of the SPL image, excluding BSS"
default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ default 0xec00 if OMAP34XX
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
@@ -261,6 +262,7 @@
config SPL_TEXT_BASE
hex "SPL Text Base"
+ default 0x40200000 if OMAP34XX
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
@@ -490,24 +492,45 @@
the board.
config SPL_SYS_MMCSD_RAW_MODE
- bool
- help
- Support booting from an MMC without a filesystem.
-
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- bool "MMC raw mode: by sector"
+ bool "Use raw reads to locate the next boot phase"
+ depends on SPL_DM_MMC || SPL_MMC
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
- select SPL_LOAD_BLOCK if SPL_MMC
- select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
+ help
+ Support booting from an MMC without a filesystem.
+
+if SPL_SYS_MMCSD_RAW_MODE
+
+choice
+ prompt "Method for locating next phase of boot (e.g. U-Boot)"
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ bool "MMC raw mode: by sector"
+ select SPL_LOAD_BLOCK
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ bool "MMC raw mode: by partition"
+ select SPL_LOAD_BLOCK
+ help
+ Use a partition for loading U-Boot when using MMC/SD in raw mode.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ bool "MMC raw mode: by partition type"
+ depends on DOS_PARTITION
+ help
+ Use partition type for specifying U-Boot partition on MMC/SD in
+ raw mode. U-Boot will be loaded from the first partition of this
+ type to be found.
+
+endchoice
+
config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
hex "Address on the MMC to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
@@ -538,13 +561,6 @@
If unsure, leave the default.
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- bool "MMC Raw mode: by partition"
- select SPL_LOAD_BLOCK if SPL_MMC
- select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
- help
- Use a partition for loading U-Boot when using MMC/SD in raw mode.
-
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
hex "Partition to use to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
@@ -553,14 +569,6 @@
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
- bool "MMC raw mode: by partition type"
- depends on DOS_PARTITION && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- help
- Use partition type for specifying U-Boot partition on MMC/SD in
- raw mode. U-Boot will be loaded from the first partition of this
- type to be found.
-
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
hex "Partition Type on the MMC to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
@@ -568,6 +576,8 @@
Partition Type on the MMC to load U-Boot from, when the MMC is being
used in raw mode.
+endif # SPL_SYS_MMCSD_RAW_MODE
+
config SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG
bool "Override eMMC EXT_CSC_PART_CONFIG by user defined partition"
depends on SUPPORT_EMMC_BOOT
@@ -1238,15 +1248,11 @@
the drivers in drivers/power/domain as part of a SPL build.
config SPL_RAM_SUPPORT
- bool "Support booting from RAM"
- default y if MICROBLAZE || ARCH_SOCFPGA || ARCH_TEGRA || ARCH_ZYNQ
- help
- Enable booting of an image in RAM. The image can be preloaded or
- it can be loaded by SPL directly into RAM (e.g. using USB).
+ bool
config SPL_RAM_DEVICE
bool "Support booting from preloaded image in RAM"
- depends on SPL_RAM_SUPPORT
+ select SPL_RAM_SUPPORT
default y if MICROBLAZE || ARCH_SOCFPGA || ARCH_TEGRA || ARCH_ZYNQ
help
Enable booting of an image already loaded in RAM. The image has to
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 4809f9c..137b184 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -37,3 +37,5 @@
obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o
endif
+
+obj-$(CONFIG_$(SPL_TPL_)UPL) += spl_upl.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7794ddc..c13b2b8 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -245,7 +245,6 @@
return map_sysmem(CONFIG_TEXT_BASE + offset, 0);
}
-#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
ulong u_boot_pos = spl_get_image_pos();
@@ -273,7 +272,6 @@
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
}
-#endif
__weak int spl_parse_board_header(struct spl_image_info *spl_image,
const struct spl_boot_device *bootdev,
@@ -308,8 +306,10 @@
ret = spl_parse_legacy_header(spl_image, header);
if (ret)
return ret;
- } else {
-#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
+ return 0;
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_PANIC_ON_RAW_IMAGE)) {
/*
* CONFIG_SPL_PANIC_ON_RAW_IMAGE is defined when the
* code which loads images in SPL cannot guarantee that
@@ -319,10 +319,9 @@
* is bad, and thus should be skipped silently.
*/
panic("** no mkimage signature but raw image not supported");
-#endif
+ }
-#if CONFIG_IS_ENABLED(OS_BOOT)
-#if defined(CMD_BOOTI)
+ if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTI)) {
ulong start, size;
if (!booti_setup((ulong)header, &start, &size, 0)) {
@@ -336,7 +335,7 @@
spl_image->load_addr, spl_image->size);
return 0;
}
-#elif defined(CMD_BOOTZ)
+ } else if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTZ)) {
ulong start, end;
if (!bootz_setup((ulong)header, &start, &end)) {
@@ -350,22 +349,21 @@
spl_image->load_addr, spl_image->size);
return 0;
}
-#endif
-#endif
+ }
- if (!spl_parse_board_header(spl_image, bootdev, (const void *)header, sizeof(*header)))
- return 0;
+ if (!spl_parse_board_header(spl_image, bootdev, (const void *)header,
+ sizeof(*header)))
+ return 0;
-#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT
+ if (IS_ENABLED(CONFIG_SPL_RAW_IMAGE_SUPPORT)) {
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
- header->ih_magic);
+ header->ih_magic);
spl_set_header_raw_uboot(spl_image);
-#else
+ } else {
/* RAW image not supported, proceed to other boot methods. */
debug("Raw boot image support not enabled, proceeding to other boot methods\n");
return -EINVAL;
-#endif
}
return 0;
@@ -713,16 +711,16 @@
if (CONFIG_IS_ENABLED(SOC_INIT))
spl_soc_init();
- if (CONFIG_IS_ENABLED(BOARD_INIT))
- spl_board_init();
-
if (IS_ENABLED(CONFIG_SPL_WATCHDOG) && CONFIG_IS_ENABLED(WDT))
initr_watchdog();
if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) ||
- IS_ENABLED(CONFIG_SPL_ATF))
+ IS_ENABLED(CONFIG_SPL_ATF) || IS_ENABLED(CONFIG_SPL_NET))
dram_init_banksize();
+ if (IS_ENABLED(CONFIG_SPL_LMB))
+ lmb_init();
+
if (CONFIG_IS_ENABLED(PCI) && !(gd->flags & GD_FLG_DM_DEAD)) {
ret = pci_init();
if (ret)
@@ -730,6 +728,9 @@
/* Don't fail. We still can try other boot methods. */
}
+ if (CONFIG_IS_ENABLED(BOARD_INIT))
+ spl_board_init();
+
bootcount_inc();
/* Dump driver model states to aid analysis */
@@ -784,7 +785,7 @@
}
if (CONFIG_IS_ENABLED(SYS_MALLOC_F) &&
!IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIZE))
- debug("SPL malloc() used 0x%lx bytes (%ld KB)\n",
+ debug("SPL malloc() used 0x%x bytes (%d KB)\n",
gd_malloc_ptr(), gd_malloc_ptr() / 1024);
bootstage_mark_name(get_bootstage_id(false), "end phase");
@@ -810,6 +811,14 @@
printf(SPL_TPL_PROMPT
"SPL hand-off write failed (err=%d)\n", ret);
}
+ if (CONFIG_IS_ENABLED(UPL_OUT) && (gd->flags & GD_FLG_UPL)) {
+ ret = spl_write_upl_handoff(&spl_image);
+ if (ret) {
+ printf(SPL_TPL_PROMPT
+ "UPL hand-off write failed (err=%d)\n", ret);
+ hang();
+ }
+ }
if (CONFIG_IS_ENABLED(BLOBLIST)) {
ret = bloblist_finish();
if (ret)
@@ -832,7 +841,7 @@
serial_init(); /* serial communications setup */
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
#if CONFIG_IS_ENABLED(BANNER_PRINT)
puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
@@ -895,7 +904,7 @@
#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
- debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n",
+ debug("SPL malloc() before relocation used 0x%x bytes (%d KB)\n",
gd->malloc_ptr, gd->malloc_ptr / 1024);
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
index bc551c5..bbf90a9 100644
--- a/common/spl/spl_blk_fs.c
+++ b/common/spl/spl_blk_fs.c
@@ -80,11 +80,8 @@
return ret;
}
- load.read = spl_fit_read;
- if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
- spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
- else
- spl_set_bl_len(&load, 1);
- load.priv = &dev;
+ spl_load_init(&load, spl_fit_read, &dev,
+ IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ?
+ ARCH_DMA_MINALIGN : 1);
return spl_load(spl_image, bootdev, &load, filesize, 0);
}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 76f49a5..c547882 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -51,8 +51,7 @@
goto end;
}
- spl_set_bl_len(&load, 1);
- load.read = spl_fit_read;
+ spl_load_init(&load, spl_fit_read, NULL, 1);
err = spl_load(spl_image, bootdev, &load, filelen, 0);
end:
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index bd8aab2..fce451b 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -83,12 +83,10 @@
size = 0;
}
- load.read = spl_fit_read;
- if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
- spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
- else
- spl_set_bl_len(&load, 1);
- load.priv = (void *)filename;
+ spl_load_init(&load, spl_fit_read, (void *)filename,
+ IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ?
+ ARCH_DMA_MINALIGN : 1);
+
err = spl_load(spl_image, bootdev, &load, size, 0);
end:
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 2a097f4..1ad5a69 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -12,6 +12,7 @@
#include <memalign.h>
#include <mapmem.h>
#include <spl.h>
+#include <upl.h>
#include <sysinfo.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -336,6 +337,8 @@
image_info->entry_point = FDT_ERROR;
}
+ upl_add_image(fit, node, load_addr, length);
+
return 0;
}
@@ -847,6 +850,8 @@
spl_image->entry_point = spl_image->load_addr;
spl_image->flags |= SPL_FIT_FOUND;
+ upl_set_fit_info(map_to_sysmem(ctx.fit), ctx.conf_node,
+ spl_image->entry_point);
return 0;
}
@@ -941,6 +946,10 @@
if (ret < 0)
return ret;
}
+ spl_image->flags |= SPL_FIT_FOUND;
+
+ upl_set_fit_info(map_to_sysmem(header), conf_noffset,
+ spl_image->entry_point);
return 0;
}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ccab0be..1337596 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -46,21 +46,17 @@
struct blk_desc *bd = mmc_get_blk_desc(mmc);
struct spl_load_info load;
- load.priv = bd;
- spl_set_bl_len(&load, bd->blksz);
- load.read = h_spl_load_read;
+ spl_load_init(&load, h_spl_load_read, bd, bd->blksz);
ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz);
if (ret) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_sector: mmc block read error\n");
-#endif
- return -1;
+ return ret;
}
return 0;
}
-static int spl_mmc_get_device_index(u32 boot_device)
+static int spl_mmc_get_device_index(uint boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
@@ -70,40 +66,30 @@
return 1;
}
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: unsupported mmc boot device.\n");
-#endif
return -ENODEV;
}
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev)
{
- int err, mmc_dev;
-
- mmc_dev = spl_mmc_get_device_index(boot_device);
- if (mmc_dev < 0)
- return mmc_dev;
+ int ret;
#if CONFIG_IS_ENABLED(DM_MMC)
- err = mmc_init_device(mmc_dev);
+ ret = mmc_init_device(mmc_dev);
#else
- err = mmc_initialize(NULL);
+ ret = mmc_initialize(NULL);
#endif /* DM_MMC */
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: could not initialize mmc. error: %d\n", err);
-#endif
- return err;
+ if (ret) {
+ printf("spl: could not initialize mmc. error: %d\n", ret);
+ return ret;
}
*mmcp = find_mmc_device(mmc_dev);
- err = *mmcp ? 0 : -ENODEV;
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ ret = *mmcp ? 0 : -ENODEV;
+ if (ret) {
printf("spl: could not find mmc device %d. error: %d\n",
- mmc_dev, err);
-#endif
- return err;
+ mmc_dev, ret);
+ return ret;
}
return 0;
@@ -116,14 +102,14 @@
unsigned long sector)
{
struct disk_partition info;
- int err;
+ int ret;
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
int type_part;
/* Only support MBR so DOS_ENTRY_NUMBERS */
for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
- err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
- if (err)
+ ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (ret)
continue;
if (info.sys_ind ==
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) {
@@ -133,12 +119,10 @@
}
#endif
- err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ ret = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
+ if (ret) {
puts("spl: partition error\n");
-#endif
- return -1;
+ return ret;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
@@ -164,10 +148,8 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
if (count != CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_os: mmc block read error\n");
-#endif
- return -1;
+ return -EIO;
}
#endif /* CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR */
@@ -205,7 +187,7 @@
struct mmc *mmc,
const char *filename)
{
- int err = -ENOSYS;
+ int ret = -ENOSYS;
__maybe_unused int partition = CONFIG_SYS_MMCSD_FS_BOOT_PARTITION;
@@ -214,8 +196,8 @@
struct disk_partition info;
debug("Checking for the first MBR bootable partition\n");
for (int type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
- err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
- if (err)
+ ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (ret)
continue;
debug("Partition %d is of type %d and bootable=%d\n", type_part, info.sys_ind, info.bootable);
if (info.bootable != 0) {
@@ -233,40 +215,40 @@
#ifdef CONFIG_SPL_FS_FAT
if (!spl_start_uboot()) {
- err = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- partition);
- if (!err)
- return err;
+ ret = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ partition);
+ if (!ret)
+ return 0;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ ret = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc),
partition,
filename);
- if (!err)
- return err;
+ if (!ret)
+ return ret;
#endif
#endif
#ifdef CONFIG_SPL_FS_EXT4
if (!spl_start_uboot()) {
- err = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- partition);
- if (!err)
- return err;
+ ret = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ partition);
+ if (!ret)
+ return 0;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ ret = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc),
partition,
filename);
- if (!err)
- return err;
+ if (!ret)
+ return 0;
#endif
#endif
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- err = -ENOENT;
+ ret = -ENOENT;
#endif
- return err;
+ return ret;
}
#endif
@@ -318,8 +300,8 @@
* which is the first physical partition (0).
*/
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
- if (part == 7)
- part = 0;
+ if (part == EMMC_BOOT_PART_USER)
+ part = EMMC_HWPART_DEFAULT;
#endif
return part;
}
@@ -354,87 +336,82 @@
unsigned long raw_sect)
{
u32 boot_mode;
- int err = 0;
+ int ret = 0;
__maybe_unused int part = 0;
int mmc_dev;
/* Perform peripheral init only once for an mmc device */
mmc_dev = spl_mmc_get_device_index(bootdev->boot_device);
if (!mmc || spl_mmc_get_mmc_devnum(mmc) != mmc_dev) {
- err = spl_mmc_find_device(&mmc, bootdev->boot_device);
- if (err)
- return err;
+ ret = spl_mmc_find_device(&mmc, mmc_dev);
+ if (ret)
+ return ret;
- err = mmc_init(mmc);
- if (err) {
+ ret = mmc_init(mmc);
+ if (ret) {
mmc = NULL;
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: mmc init failed with error: %d\n", err);
-#endif
- return err;
+ printf("spl: mmc init failed with error: %d\n", ret);
+ return ret;
}
}
boot_mode = spl_mmc_boot_mode(mmc, bootdev->boot_device);
- err = -EINVAL;
+ ret = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
part = spl_mmc_emmc_boot_partition(mmc);
if (CONFIG_IS_ENABLED(MMC_TINY))
- err = mmc_switch_part(mmc, part);
+ ret = mmc_switch_part(mmc, part);
else
- err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+ ret = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ if (ret) {
puts("spl: mmc partition switch failed\n");
-#endif
- return err;
+ return ret;
}
/* Fall through */
case MMCSD_MODE_RAW:
debug("spl: mmc boot mode: raw\n");
if (!spl_start_uboot()) {
- err = mmc_load_image_raw_os(spl_image, bootdev, mmc);
- if (!err)
- return err;
+ ret = mmc_load_image_raw_os(spl_image, bootdev, mmc);
+ if (!ret)
+ return 0;
}
raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- err = mmc_load_image_raw_partition(spl_image, bootdev,
+ ret = mmc_load_image_raw_partition(spl_image, bootdev,
mmc, raw_part,
raw_sect);
- if (!err)
- return err;
+ if (!ret)
+ return 0;
#endif
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- err = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
- raw_sect + spl_mmc_raw_uboot_offset(part));
- if (!err)
- return err;
+ ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
+ raw_sect +
+ spl_mmc_raw_uboot_offset(part));
+ if (!ret)
+ return 0;
#endif
/* If RAW mode fails, try FS mode. */
#ifdef CONFIG_SYS_MMCSD_FS_BOOT
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
- err = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename);
- if (!err)
- return err;
+ ret = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename);
+ if (!ret)
+ return 0;
break;
#endif
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
puts("spl: mmc: wrong boot mode\n");
-#endif
}
- return err;
+ return ret;
}
int spl_mmc_load_image(struct spl_image_info *spl_image,
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 5631fa6..22883f4 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -71,9 +71,7 @@
{
struct spl_load_info load;
- load.priv = &offset;
- spl_set_bl_len(&load, 1);
- load.read = spl_nand_read;
+ spl_load_init(&load, spl_nand_read, &offset, 1);
return spl_load(spl_image, bootdev, &load, 0, offset);
}
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index be7278b..2be7b73 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -47,8 +47,7 @@
return rv;
}
- spl_set_bl_len(&load, 1);
- load.read = spl_net_load_read;
+ spl_load_init(&load, spl_net_load_read, NULL, 1);
return spl_load(spl_image, bootdev, &load, 0, 0);
}
#endif
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index ed76b5e..1021d93 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -49,8 +49,7 @@
int ret;
debug("Found FIT\n");
- spl_set_bl_len(&load, 1);
- load.read = spl_nor_load_read;
+ spl_load_init(&load, spl_nor_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load,
CONFIG_SYS_OS_BASE,
@@ -93,8 +92,7 @@
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- spl_set_bl_len(&load, 1);
- load.read = spl_nor_load_read;
+ spl_load_init(&load, spl_nor_load_read, NULL, 1);
return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base());
}
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 5a23841..71b7a83 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -69,8 +69,7 @@
struct spl_load_info load;
debug("Found FIT\n");
- spl_set_bl_len(&load, 1);
- load.read = spl_ram_load_read;
+ spl_load_init(&load, spl_ram_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load, 0, header);
} else {
ulong u_boot_pos = spl_get_image_pos();
diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c
index 2047248..f36863f 100644
--- a/common/spl/spl_semihosting.c
+++ b/common/spl/spl_semihosting.c
@@ -43,9 +43,7 @@
}
len = ret;
- load.read = smh_fit_read;
- spl_set_bl_len(&load, 1);
- load.priv = &fd;
+ spl_load_init(&load, smh_fit_read, &fd, 1);
ret = spl_load(spl_image, bootdev, &load, len, 0);
if (ret)
log_debug("could not read %s: %d\n", filename, ret);
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 8ab4803..691a431 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -77,9 +77,7 @@
return -ENODEV;
}
- load.priv = flash;
- spl_set_bl_len(&load, 1);
- load.read = spl_spi_fit_read;
+ spl_load_init(&load, spl_spi_fit_read, flash, 1);
#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot()) {
diff --git a/common/spl/spl_upl.c b/common/spl/spl_upl.c
new file mode 100644
index 0000000..067d437
--- /dev/null
+++ b/common/spl/spl_upl.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff parsing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <alist.h>
+#include <bloblist.h>
+#include <dm.h>
+#include <image.h>
+#include <mapmem.h>
+#include <serial.h>
+#include <spl.h>
+#include <upl.h>
+#include <video.h>
+#include <asm/global_data.h>
+#include <dm/read.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct upl s_upl;
+
+void upl_set_fit_addr(ulong fit)
+{
+ struct upl *upl = &s_upl;
+
+ upl->fit = fit;
+}
+
+void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr)
+{
+ struct upl *upl = &s_upl;
+
+ upl->fit = fit;
+ upl->conf_offset = conf_offset;
+ log_debug("upl: add fit %lx conf %x\n", fit, conf_offset);
+}
+
+int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc)
+{
+ struct upl *upl = &s_upl;
+ struct upl_image img;
+
+ img.load = load_addr;
+ img.size = size;
+ img.offset = node;
+ img.description = desc;
+ if (!alist_add(&upl->image, img))
+ return -ENOMEM;
+ log_debug("upl: add image %s at %lx size %lx\n", desc, load_addr, size);
+
+ return 0;
+}
+
+static int write_serial(struct upl_serial *ser)
+{
+ struct udevice *dev = gd->cur_serial_dev;
+ struct serial_device_info info;
+ struct memregion region;
+ int ret;
+
+ if (!dev)
+ return log_msg_ret("ser", -ENOENT);
+ ret = serial_getinfo(dev, &info);
+ if (ret)
+ return log_msg_ret("inf", ret);
+
+ ser->compatible = ofnode_read_string(dev_ofnode(dev), "compatible");
+ ser->clock_frequency = info.clock;
+ ser->current_speed = gd->baudrate;
+ region.base = info.addr;
+ region.size = info.size;
+ alist_init_struct(&ser->reg, struct memregion);
+ if (!alist_add(&ser->reg, region))
+ return -ENOMEM;
+ ser->reg_io_shift = info.reg_shift;
+ ser->reg_offset = info.reg_offset;
+ ser->reg_io_width = info.reg_width;
+ ser->virtual_reg = 0;
+ ser->access_type = info.addr_space;
+
+ return 0;
+}
+
+static int write_graphics(struct upl_graphics *gra)
+{
+ struct video_uc_plat *plat;
+ struct video_priv *priv;
+ struct memregion region;
+ struct udevice *dev;
+
+ alist_init_struct(&gra->reg, struct memregion);
+ uclass_find_first_device(UCLASS_VIDEO, &dev);
+ if (!dev || !device_active(dev))
+ return log_msg_ret("vid", -ENOENT);
+
+ plat = dev_get_uclass_plat(dev);
+ region.base = plat->base;
+ region.size = plat->size;
+ if (!alist_add(&gra->reg, region))
+ return log_msg_ret("reg", -ENOMEM);
+
+ priv = dev_get_uclass_priv(dev);
+ gra->width = priv->xsize;
+ gra->height = priv->ysize;
+ gra->stride = priv->line_length; /* private field */
+ switch (priv->format) {
+ case VIDEO_RGBA8888:
+ case VIDEO_X8R8G8B8:
+ gra->format = UPLGF_ARGB32;
+ break;
+ case VIDEO_X8B8G8R8:
+ gra->format = UPLGF_ABGR32;
+ break;
+ case VIDEO_X2R10G10B10:
+ log_debug("device '%s': VIDEO_X2R10G10B10 not supported\n",
+ dev->name);
+ return log_msg_ret("for", -EPROTO);
+ case VIDEO_UNKNOWN:
+ log_debug("device '%s': Unknown video format\n", dev->name);
+ return log_msg_ret("for", -EPROTO);
+ }
+
+ return 0;
+}
+
+int spl_write_upl_handoff(struct spl_image_info *spl_image)
+{
+ struct upl *upl = &s_upl;
+ struct abuf buf;
+ ofnode root;
+ void *ptr;
+ int ret;
+
+ log_debug("UPL: Writing handoff - image_count=%d\n", upl->image.count);
+ upl->addr_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1;
+ upl->size_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1;
+ upl->bootmode = UPLBM_DEFAULT;
+ ret = write_serial(&upl->serial);
+ if (ret)
+ return log_msg_ret("ser", ret);
+ ret = write_graphics(&upl->graphics);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("gra", ret);
+
+ root = ofnode_root();
+ ret = upl_write_handoff(upl, root, true);
+ if (ret)
+ return log_msg_ret("wr", ret);
+
+ ret = oftree_to_fdt(oftree_default(), &buf);
+ if (ret)
+ return log_msg_ret("fdt", ret);
+ log_debug("FDT size %zx\n", abuf_size(&buf));
+
+ ptr = bloblist_add(BLOBLISTT_CONTROL_FDT, abuf_size(&buf), 0);
+ if (!ptr)
+ return log_msg_ret("blo", -ENOENT);
+ memcpy(ptr, abuf_data(&buf), abuf_size(&buf));
+
+ return 0;
+}
+
+void spl_upl_init(void)
+{
+ upl_init(&s_upl);
+}
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4c7222a..2be9571 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -132,11 +132,9 @@
struct ymodem_fit_info info;
debug("Found FIT\n");
- load.priv = (void *)&info;
- spl_set_bl_len(&load, 1);
+ spl_load_init(&load, ymodem_read_fit, (void *)&info, 1);
info.buf = buf;
info.image_read = BUF_SIZE;
- load.read = ymodem_read_fit;
ret = spl_load_simple_fit(spl_image, &load, 0, (void *)buf);
size = info.image_read;
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index f3b4a3c..bbfee23 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -137,6 +137,11 @@
/* The period of time between two calls of usb_kbd_testc(). */
static unsigned long kbd_testc_tms;
+int usb_kbd_remove_for_test(void)
+{
+ return console_remove_by_name(DEVNAME);
+}
+
/* Puts character in the queue and sets up the in and out pointer. */
static void usb_kbd_put_queue(struct usb_kbd_pdata *data, u8 c)
{
@@ -612,7 +617,7 @@
debug("USB KBD: register.\n");
memset(&usb_kbd_dev, 0, sizeof(struct stdio_dev));
strcpy(usb_kbd_dev.name, DEVNAME);
- usb_kbd_dev.flags = DEV_FLAGS_INPUT;
+ usb_kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_DM;
usb_kbd_dev.getc = usb_kbd_getc;
usb_kbd_dev.tstc = usb_kbd_testc;
usb_kbd_dev.priv = (void *)dev;
@@ -638,76 +643,11 @@
if (error)
return error;
}
-#endif
-
- return 0;
-}
-
-#if !CONFIG_IS_ENABLED(DM_USB)
-/* Search for keyboard and register it if found. */
-int drv_usb_kbd_init(void)
-{
- int error, i;
-
- debug("%s: Probing for keyboard\n", __func__);
- /* Scan all USB Devices */
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- struct usb_device *dev;
-
- /* Get USB device. */
- dev = usb_get_dev_index(i);
- if (!dev)
- break;
-
- if (dev->devnum == -1)
- continue;
-
- error = probe_usb_keyboard(dev);
- if (!error)
- return 1;
- if (error && error != -ENOENT)
- return error;
- }
-
- /* No USB Keyboard found */
- return -1;
-}
-
-/* Deregister the keyboard. */
-int usb_kbd_deregister(int force)
-{
-#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
- struct stdio_dev *dev;
- struct usb_device *usb_kbd_dev;
- struct usb_kbd_pdata *data;
-
- dev = stdio_get_by_name(DEVNAME);
- if (dev) {
- usb_kbd_dev = (struct usb_device *)dev->priv;
- data = usb_kbd_dev->privptr;
-#if CONFIG_IS_ENABLED(CONSOLE_MUX)
- if (iomux_replace_device(stdin, DEVNAME, force ? "nulldev" : ""))
- return 1;
-#endif
- if (stdio_deregister_dev(dev, force) != 0)
- return 1;
-#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
- destroy_int_queue(usb_kbd_dev, data->intq);
#endif
- free(data->new);
- free(data);
- }
return 0;
-#else
- return 1;
-#endif
}
-#endif
-
-#if CONFIG_IS_ENABLED(DM_USB)
-
static int usb_kbd_probe(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
@@ -788,5 +728,3 @@
};
U_BOOT_USB_DEVICE(usb_kbd, kbd_id_table);
-
-#endif
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 9eac43a..dd30e8d 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -139,7 +139,6 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig
index 5c15d51..b012b98 100644
--- a/configs/a3y17lte_defconfig
+++ b/configs/a3y17lte_defconfig
@@ -23,4 +23,3 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig
index 7c9b6b2..25a7d5b 100644
--- a/configs/a5y17lte_defconfig
+++ b/configs/a5y17lte_defconfig
@@ -23,4 +23,3 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig
index c7297f7..c87379a 100644
--- a/configs/a7y17lte_defconfig
+++ b/configs/a7y17lte_defconfig
@@ -23,4 +23,3 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index f8dfd1d..3fcebc6 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_BALTOS=y
@@ -19,6 +17,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index cabc181..5dd0b32 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -2,8 +2,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 8239f5f..a55aace 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -2,8 +2,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 7513854..6b36f6e 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x500000
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
@@ -31,10 +29,11 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_I2C=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 3694cc3..d780239 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL_TEXT_BASE=0x40300350
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index a99b7b4..bd97994 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL_TEXT_BASE=0x40301950
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index ddffd4f..1994388 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x18000
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_AM33XX=y
@@ -76,7 +74,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index febe5eb..d9acc81 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -4,8 +4,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x1200
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
@@ -24,9 +22,10 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}"
CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 47c08e5..72933ba 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -33,6 +31,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -66,10 +65,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index c7618c5..b8a3227 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -31,6 +29,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -64,10 +63,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 9342658..b25a4de 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -34,6 +32,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -67,10 +66,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 439f9b8..8486ccb 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -34,6 +32,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -66,10 +65,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 88122bd..7444e55 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
CONFIG_AM33XX=y
@@ -24,6 +22,7 @@
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ENV_SUPPORT=y
@@ -66,7 +65,7 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 3236f1d..4c1f664 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -5,15 +5,10 @@
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SOURCE_FILE="am3517evm"
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/am3517-evm"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2500
CONFIG_SPL=y
CONFIG_LTO=y
@@ -21,11 +16,10 @@
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
CONFIG_SYS_PBSIZE=1054
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index d73b1cb..0fc4c0f 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 89e2125..c538c1a 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x30000000
CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x110000
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 2ff0119..0fe5479 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 845b686..c4693bc 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -2,8 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index ff5073c..980ef13 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -4,8 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index 5ef59d8..75725e1 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -3,8 +3,6 @@
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x110000
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 7c3ceeb..587af53 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 1f7eca4..b790897 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 807e1d6..450751b 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 4a351cd..b905ff7 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -30,6 +30,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 44ccb6b..092d083 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 87005d0..9635beb 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index ace5569..4f7be44 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index 79c82d1..af54f96 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index d0cc4f5..ee4c43f 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index ca993b4..0b7ee94 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62x_evm_a53_ethboot_defconfig b/configs/am62x_evm_a53_ethboot_defconfig
new file mode 100644
index 0000000..9d3c6b8
--- /dev/null
+++ b/configs/am62x_evm_a53_ethboot_defconfig
@@ -0,0 +1,17 @@
+#include <configs/am62x_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_A53_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-sk"
+CONFIG_SPL_STACK_R_ADDR=0x83000000
+CONFIG_SPL_SIZE_LIMIT=0x80000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL"
+CONFIG_SPL_SYSCON=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 4b2e57b..78ed3f6 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/am62x_evm_r5_ethboot_defconfig b/configs/am62x_evm_r5_ethboot_defconfig
new file mode 100644
index 0000000..0d82374
--- /dev/null
+++ b/configs/am62x_evm_r5_ethboot_defconfig
@@ -0,0 +1,25 @@
+#include<configs/am62x_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_EVM=y
+CONFIG_DEFAULT_DEVICEC_TREE="k3-am625-r5-sk"
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_BSS_MAX_SIZE=0X3100
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot R5 SPL"
+CONFIG_CMD_DHCP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_DM_I2C=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 5b01002..e6e3e01 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 96475d4..1e83b7f 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -50,6 +50,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 925a88e..f22b9af 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 4fc9c39..1660bf9 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig
index c4bf771..78f6ffc 100644
--- a/configs/amd_versal2_virt_defconfig
+++ b/configs/amd_versal2_virt_defconfig
@@ -72,6 +72,7 @@
CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_CCF=y
CONFIG_CLK_SCMI=y
CONFIG_DFU_RAM=y
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index e9fb4c7..466147f 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_APALIS_IMX8=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95400000
CONFIG_SYS_MEMTEST_START=0x88000000
diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig
index 20d2cff..dca6e0c 100644
--- a/configs/apple_m1_defconfig
+++ b/configs/apple_m1_defconfig
@@ -26,4 +26,3 @@
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
# CONFIG_SMBIOS is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 08753ae..9983d3a 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -7,7 +7,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000
CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x3C0000
+CONFIG_ENV_OFFSET=0x7C0000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb"
@@ -17,7 +17,7 @@
CONFIG_SYS_SKIP_UART_INIT=y
CONFIG_TARGET_ARBEL_EVB=y
CONFIG_SYS_LOAD_ADDR=0x06208000
-CONFIG_ENV_ADDR=0x803C0000
+CONFIG_ENV_ADDR=0x807C0000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_BOOTM_LEN=0x1400000
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 0b2ee74..8947b76 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_DM_GPIO=y
@@ -39,6 +37,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 47b37bb..2f29cb3 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -34,7 +34,7 @@
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index f584b8d..a17afde 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
@@ -39,11 +37,12 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 6c27f07..fc801f2 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_DM_GPIO=y
@@ -35,6 +33,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 24dfdae..a9283ad 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index c574d93..8cb6b34 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x20000
CONFIG_DM_GPIO=y
@@ -24,6 +22,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
@@ -53,7 +52,7 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index e5d805d..93bf4f5 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 9bc5953..a1df1f8 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -37,7 +37,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 26fa05e..03520b6 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 5deb09b..607fd28 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 39f3384..90574d2 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -32,6 +32,7 @@
CONFIG_SPL_MAX_SIZE=0x2e00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c
CONFIG_SPL_MMC_TINY=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 386616c..81a39f7 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -80,7 +80,7 @@
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
CONFIG_LBA48=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_MXC_I2C3_SPEED=400000
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 32f126a..eabeee8 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -5,8 +5,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0xC0000
@@ -38,6 +36,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
@@ -72,7 +71,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SYS_RX_ETH_BUFFER=64
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index e76373e..d7b1b76 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -13,6 +13,8 @@
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_COLIBRI_IMX8X=y
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95c00000
CONFIG_SYS_MEMTEST_START=0x88000000
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 30d1a93..d10faa5 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -50,7 +50,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 62cbd02..7e59b6f 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -46,7 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig
index 4b9b073..4731e84 100644
--- a/configs/deneb_defconfig
+++ b/configs/deneb_defconfig
@@ -55,6 +55,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 7653fbb..33201ce 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -3,13 +3,8 @@
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="omap3-devkit8000"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_DEVKIT8000=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_BSS_START_ADDR=0x80000500
CONFIG_SPL=y
@@ -17,7 +12,6 @@
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 1d3336b..7463f4f 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -42,7 +42,7 @@
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SAVEENV=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 7c681f0..59d0c5d 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -39,7 +39,7 @@
CONFIG_SYS_PBSIZE=2084
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 0cea550..6264d9f 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 5f56b18..4e79297 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -3,9 +3,6 @@
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 5b67a0e..68d342b 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -3,9 +3,6 @@
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig
index ba3f381..78ee5c1 100644
--- a/configs/draco-etamin_defconfig
+++ b/configs/draco-etamin_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig
index 43d29f5..ea6518e 100644
--- a/configs/draco-rastaban_defconfig
+++ b/configs/draco-rastaban_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
@@ -35,7 +33,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig
index b457b22..4672d4b 100644
--- a/configs/draco-thuban_defconfig
+++ b/configs/draco-thuban_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
@@ -35,7 +33,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index 2949da2..e5d9099 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -9,12 +9,20 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ABOOTIMG=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
# CONFIG_NET is not set
CONFIG_CLK_EXYNOS850=y
-# CONFIG_MMC is not set
+CONFIG_MMC_DW=y
CONFIG_SOC_SAMSUNG=y
CONFIG_EXYNOS_PMU=y
CONFIG_EXYNOS_USI=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
deleted file mode 100644
index cc2f567..0000000
--- a/configs/ethernut5_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_AT91=y
-CONFIG_TEXT_BASE=0x27000000
-CONFIG_SYS_MALLOC_LEN=0x121000
-CONFIG_TARGET_ETHERNUT5=y
-CONFIG_AT91_EFLASH=y
-CONFIG_EFLASH_PROTSECTORS=1
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x21000
-CONFIG_ENV_OFFSET=0x3DE000
-CONFIG_ENV_SECT_SIZE=0x21000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="ethernut5"
-CONFIG_SYS_LOAD_ADDR=0x020000000
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mtdblock0 mtdparts=atmel_nand:-(root) rw rootfstype=jffs2"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="sf probe 0:0; sf read 0x22000000 0xc6000 0x294000; bootm 0x22000000"
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=281
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="U-Boot> "
-# CONFIG_CMD_BDI is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_RARP=y
-CONFIG_SYS_DISABLE_AUTOLOAD=y
-CONFIG_CMD_MII=y
-# CONFIG_CMD_MDIO is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_CDP=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_BSP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:-(root)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RETRY_COUNT=20
-CONFIG_CLK=y
-CONFIG_CLK_AT91=y
-CONFIG_AT91_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SLAVE=0
-CONFIG_GENERIC_ATMEL_MCI=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_SYS_MAX_FLASH_SECT=32
-CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_DATAFLASH=y
-CONFIG_MACB=y
-CONFIG_RMII=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_RTC_PCF8563=y
-CONFIG_DM_SERIAL=y
-CONFIG_ATMEL_USART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_JFFS2_NAND=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 3b9466c..42f116f 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -46,7 +46,7 @@
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
index c7390d1..774ab64 100644
--- a/configs/giedi_defconfig
+++ b/configs/giedi_defconfig
@@ -55,6 +55,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig
new file mode 100644
index 0000000..855615c
--- /dev/null
+++ b/configs/ibex-ast2700_defconfig
@@ -0,0 +1,94 @@
+CONFIG_RISCV=y
+CONFIG_SYS_DCACHE_OFF=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_TEXT_BASE=0x80000000
+CONFIG_SYS_MALLOC_LEN=0xf00
+CONFIG_SYS_MALLOC_F_LEN=0xf00
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x14bd7800
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DEFAULT_DEVICE_TREE="ast2700-ibex"
+CONFIG_SPL_TEXT_BASE=0x14bc0080
+CONFIG_DM_RESET=y
+CONFIG_SPL_BSS_START_ADDR=0x14bd7800
+CONFIG_SPL_BSS_MAX_SIZE=0x800
+CONFIG_SPL_SIZE_LIMIT=0x16000
+CONFIG_SPL=y
+CONFIG_SYS_MEM_TOP_HIDE=0x10000000
+CONFIG_SYS_LOAD_ADDR=0x83000000
+CONFIG_BUILD_TARGET=""
+CONFIG_TARGET_ASPEED_AST2700_IBEX=y
+# CONFIG_RISCV_ISA_F is not set
+# CONFIG_RISCV_ISA_A is not set
+# CONFIG_SPL_SMP is not set
+CONFIG_XIP=y
+CONFIG_SPL_XIP=y
+# CONFIG_AVAILABLE_HARTS is not set
+CONFIG_STACK_SIZE_SHIFT=11
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_STACK_SIZE=0x100000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x200c0000
+# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+# CONFIG_CONSOLE_FLUSH_SUPPORT is not set
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x16000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_BOOTM_LINUX is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DEVICE_TREE_INCLUDES="ast2700-u-boot.dtsi"
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_SYS_RX_ETH_BUFFER=2
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_DM_SEQ_ALIAS is not set
+# CONFIG_BLOCK_CACHE is not set
+# CONFIG_CPU is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+CONFIG_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_MTD is not set
+# CONFIG_POWER is not set
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_ASPEED_RAM=y
+# CONFIG_RAM_SIFIVE is not set
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_AST_IBEX_TIMER=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+# CONFIG_RSA is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 4738916..f1d9bb3 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -4,14 +4,9 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_ENV_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
@@ -22,7 +17,6 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 822a329..d147001 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -48,6 +48,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index 8d48d8c..aa1116a 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -29,6 +29,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 7203583..b893da6 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -30,7 +30,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index f5bb50c..0b7dd63 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index b36ad7c..9312e9f 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index d4e9d9f..f37297c 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index c85a141..950246e 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 5e6bbb3..8644177 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -52,6 +52,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 16ba7d4..6570c9f 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index e3dcbfe..7f0cb9a 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 0aca853..354a671 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index f26a879..34566d4 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -59,6 +59,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -105,6 +106,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 788770b..3fd2d9f 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -35,6 +35,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index a57dc47..96c0a46 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index e14dcdf..2fd319b 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index f4d999b..3633401 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -138,7 +139,6 @@
CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 1129d80..7a19315 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index f4af998..eebfb0d 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index cecde44..6acbb8a 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index b4351a3..29d7cda 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_DMA=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index 0faa337..151a9a5 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 82e3ce1..93380a0 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index 679ca71..5405f8f 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 218415f..0155cb2 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index b65fef0..d2925f2 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -133,7 +134,6 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 05f68c7..497a908 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 3c337d4..ba676c9 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index fe3e757..0e910e2 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -66,6 +66,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -112,6 +113,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index aa1de6d..c76ab23 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 79b3e96..f807b0c 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -64,6 +64,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 8ef8bf4..05895d6 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -66,6 +66,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index a2c0796..4b9ac30 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 5478936..7a7f390 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -53,6 +53,8 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 4b0b71d..75d110f 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index df93774..09a8841 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -138,7 +139,6 @@
CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 5eb96d3..ac45c3d 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 3c1701a..2a51681 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 3a3fb75..4c36827 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
index 1844e3c..2a951f1 100644
--- a/configs/imx8mq_reform2_defconfig
+++ b/configs/imx8mq_reform2_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index bf02d3e..a96fb31 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index d6b79f5..56cc834 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 0f0748b..c20b904 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x22040000
CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig
index e3eb002..6e9e9c5 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx93-phyboard-segin_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 6f083e0..198d43e 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig
deleted file mode 100644
index deed068..0000000
--- a/configs/imx93_11x11_evk_ld_defconfig
+++ /dev/null
@@ -1,126 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_IMX9=y
-CONFIG_TEXT_BASE=0x80200000
-CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x18000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x400000
-CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk"
-CONFIG_SPL_TEXT_BASE=0x2049A000
-CONFIG_IMX9_LOW_DRIVE_MODE=y
-CONFIG_TARGET_IMX93_11X11_EVK=y
-CONFIG_SYS_MONITOR_LEN=524288
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK=0x20519dd0
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2051a000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SPL=y
-CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
-CONFIG_SYS_LOAD_ADDR=0x80400000
-CONFIG_SYS_MEMTEST_START=0x80000000
-CONFIG_SYS_MEMTEST_END=0x90000000
-CONFIG_REMAKE_ELF=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
-CONFIG_SYS_CBSIZE=2048
-CONFIG_SYS_PBSIZE=2074
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x26000
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_BOOTROM_SUPPORT=y
-CONFIG_SPL_LOAD_IMX_CONTAINER=y
-CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
-CONFIG_SPL_I2C=y
-CONFIG_SPL_POWER=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SYS_PROMPT="u-boot=> "
-CONFIG_CMD_ERASEENV=y
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_RTC=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_GETTIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="eth0"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CPU=y
-CONFIG_CPU_IMX=y
-CONFIG_IMX_RGPIO2P=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_ES_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_FSL_USDHC=y
-CONFIG_PHY_ANEG_TIMEOUT=20000
-CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH_PHY=y
-CONFIG_PHY_GIGE=y
-CONFIG_DWC_ETH_QOS=y
-CONFIG_DWC_ETH_QOS_IMX=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_IMX93=y
-CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
-CONFIG_DM_SERIAL=y
-CONFIG_FSL_LPUART=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_CMD_POWEROFF=y
-CONFIG_SYSRESET_PSCI=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_TMU=y
-CONFIG_ULP_WATCHDOG=y
-CONFIG_WDT=y
-CONFIG_LZO=y
-CONFIG_BZIP2=y
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index 94ce213..14f220e 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 80c8769..72bbd72 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -31,6 +31,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 086fc47..fdbce8e 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -35,6 +35,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index 4b252cf..03543ed 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 83825da..fe0058a 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -31,6 +31,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 8654bf2..2a7a958 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index fcfa926..137ca3f 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index e023af2..774a9ef 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index 86c565a..ed75f7e 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig
index 314161b..ce96e49 100644
--- a/configs/j721e_beagleboneai64_r5_defconfig
+++ b/configs/j721e_beagleboneai64_r5_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index f993157..640c1be 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index f1c9bbd..3b4a7c3 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5800e4b..d78ebb5 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index d0af664..b6adb6a 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -50,6 +50,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 1675ced..9862022 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index 8ba3916..e574be9 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 520a53b..f022017 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 543b0a5..a116881 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 8d6cb24..f201a175 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm"
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc1223f4
@@ -99,3 +99,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index e3c0ae1..46501d5 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -73,3 +73,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 5d54d75..57a3d36 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -17,7 +17,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm"
CONFIG_SPL_TEXT_BASE=0xC0A0000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc0c23f4
@@ -57,7 +57,7 @@
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
+CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
@@ -109,3 +109,4 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 9adab3a..392ec5b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -14,7 +14,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -33,7 +33,7 @@
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
+CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
@@ -84,3 +84,4 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 4da75d1..2e29b2f 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm"
CONFIG_SPL_TEXT_BASE=0xC200000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc2223f4
@@ -100,3 +100,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 1a24d71..cf299f2 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -74,3 +74,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index c4534f0..0cadece 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm"
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc1223f4
@@ -100,3 +100,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index c874349..5496049 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm"
CONFIG_TIMESTAMP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
@@ -78,3 +78,4 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index 1b7d22b..d85a433 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index c213347..5223883 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index a1d5f89..c4493e5 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -51,6 +51,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900
CONFIG_SPL_MPC8XXX_INIT_DDR=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index 6999a68..248fc1f 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 2354f41..981093a 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 136ca9a..4fc0e66 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80200000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index befb4ae..72632b8 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -59,6 +59,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index db06a03..78dce4d 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -58,6 +58,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index e5d8eeb..0853bfb 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -52,6 +52,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index dc0e507..28434d8 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82104000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 9980d61..b4348f1 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -61,6 +61,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index ed92e34..8d2c391 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 06e4154..0066414 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -61,7 +61,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 0b54bc9..44a1459 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -43,7 +43,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index f1009e1..cbc8d6a 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -68,7 +68,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig
new file mode 100644
index 0000000..855366d
--- /dev/null
+++ b/configs/lxr2_defconfig
@@ -0,0 +1,118 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_LEN=0xa00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6Q=y
+CONFIG_TARGET_LXR2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-lxr"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SYS_MONITOR_LEN=409600
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SPL=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_ENV_OFFSET_REDUND=0x110000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_LTO=y
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=715766
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SYS_PBSIZE=532
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_FIT_IMAGE_TINY=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:40m(Kernels),860m(root),-(nand)"
+CONFIG_CMD_UBI=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ARP_TIMEOUT=200
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C4000
+CONFIG_SYS_BOOTCOUNT_BE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0xe00000
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SYSRESET_WATCHDOG_AUTO=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index ff371da..8ac29b9 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -27,7 +27,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 5b130bc..0a71013 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -29,7 +29,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index ce917a6..355292e 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -26,7 +26,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index de29a7a..ffd2771 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -28,7 +28,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
index d350ec1..1186763 100644
--- a/configs/milkv_duo_defconfig
+++ b/configs/milkv_duo_defconfig
@@ -1,6 +1,6 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x820000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000
@@ -26,6 +26,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_SOPHGO_CV1800B=y
CONFIG_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index 2e1d112..47ed5cf 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig
index 76ee2aa..d3e8339 100644
--- a/configs/mt7981_emmc_rfb_defconfig
+++ b/configs/mt7981_emmc_rfb_defconfig
@@ -62,4 +62,3 @@
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig
index 3989c79..4bc2173 100644
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -65,4 +65,3 @@
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig
index 9b33245..8721b40 100644
--- a/configs/mt7981_sd_rfb_defconfig
+++ b/configs/mt7981_sd_rfb_defconfig
@@ -62,4 +62,3 @@
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig
index 4d0cc85..15c31de 100644
--- a/configs/mt7986_rfb_defconfig
+++ b/configs/mt7986_rfb_defconfig
@@ -65,4 +65,3 @@
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig
index 3c296ab..56921f3 100644
--- a/configs/mt7986a_bpir3_emmc_defconfig
+++ b/configs/mt7986a_bpir3_emmc_defconfig
@@ -62,4 +62,3 @@
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig
index f644070..4ed06b7 100644
--- a/configs/mt7986a_bpir3_sd_defconfig
+++ b/configs/mt7986a_bpir3_sd_defconfig
@@ -62,4 +62,3 @@
CONFIG_FAT_WRITE=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
index d0ed2cc..f7ceace 100644
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -81,4 +81,3 @@
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig
index 5631eaa..808c8b9 100644
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -69,4 +69,3 @@
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 1fe68ef..dddb57e 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -32,7 +32,6 @@
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index e5178fb..5932a15 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -31,7 +31,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 9beb045..e927bb2 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -9,7 +9,7 @@
CONFIG_MX6SL=y
CONFIG_TARGET_MX6SLEVK=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6sl-evk"
# CONFIG_CMD_BMODE is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTCOMMAND=y
@@ -38,7 +38,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
@@ -63,9 +62,13 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_SYSRESET_WATCHDOG_AUTO=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
deleted file mode 100644
index 3491cbc..0000000
--- a/configs/mx6slevk_spinor_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MX6SL=y
-CONFIG_TARGET_MX6SLEVK=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
-# CONFIG_CMD_BMODE is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SPI_BOOT=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
-CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=32
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PFUZE100=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
deleted file mode 100644
index 9c92360..0000000
--- a/configs/mx6slevk_spl_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_MX6SL=y
-CONFIG_TARGET_MX6SLEVK=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
-CONFIG_SYS_PBSIZE=532
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
-CONFIG_SPL_I2C=y
-CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=32
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_SMSC=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_PFUZE100=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 322689e..dd3541b 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -67,7 +67,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_LBA48=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 23b2e50..29aa01f 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-35xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_ANDROID_BOOT_IMAGE=y
@@ -24,11 +19,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index a5f242f..4c60514 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-35xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_SYS_MONITOR_BASE=0x10000000
@@ -25,11 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 3c8d974..42c6aad 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -3,13 +3,8 @@
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
-CONFIG_SPL_TEXT_BASE=0x40200000
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-evm"
CONFIG_TARGET_OMAP3_EVM=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
@@ -18,7 +13,6 @@
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_SYS_PBSIZE=1053
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -48,10 +42,9 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FAT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index d081d4e..e3791da 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-37xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_ANDROID_BOOT_IMAGE=y
@@ -23,11 +18,10 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 68e89d2..e9291d5 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-37xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_SYS_MONITOR_BASE=0x10000000
@@ -25,11 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 7846981..a4e467f 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index ac638c4..d5056cc 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 98c6217..5813d10 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 6748e6f..61a3ead 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 63f8a80..b63a96f 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -6,8 +6,10 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_PHYTEC_SOM_DETECTION=y
+CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
@@ -24,12 +26,15 @@
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3e0000
+CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
@@ -44,11 +49,14 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_CRYPTO is not set
CONFIG_SPL_I2C=y
+CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
@@ -64,6 +72,8 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -77,10 +87,12 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
@@ -113,6 +125,17 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH_PHY=y
@@ -134,6 +157,9 @@
CONFIG_SPL_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 39161b7..67f89e0 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -12,7 +12,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
@@ -40,13 +40,14 @@
CONFIG_BOOTSTD_FULL=y
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
+CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_ENV_SUPPORT=y
@@ -92,7 +93,7 @@
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
@@ -151,7 +152,7 @@
CONFIG_USB_DWC3_AM62=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index b7d0273..7fc3abf 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_I2C=y
diff --git a/configs/phycore_am62x_r5_usbdfu_defconfig b/configs/phycore_am62x_r5_usbdfu_defconfig
new file mode 100644
index 0000000..ff17a29
--- /dev/null
+++ b/configs/phycore_am62x_r5_usbdfu_defconfig
@@ -0,0 +1,9 @@
+#include <configs/phycore_am62x_r5_defconfig>
+#include <configs/am62x_r5_usbdfu.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_PHYCORE_AM62X_R5=y
+
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 1af72e8..3bfe876 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -37,7 +37,8 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
-CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x180000
@@ -45,6 +46,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig
index a0d7824..72d10f7 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index cf91eb5..ef876ab 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index c2f8693..30946b8 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
diff --git a/configs/qcm6490_defconfig b/configs/qcm6490_defconfig
new file mode 100644
index 0000000..5ddc5ab
--- /dev/null
+++ b/configs/qcm6490_defconfig
@@ -0,0 +1,21 @@
+# Configuration for building U-Boot to be flashed
+# to the uefi partition of QCM6490 dev boards with
+# the "Linux Embedded" partition layout (which have
+# a dedicated "uefi" partition for edk2/U-Boot)
+
+#include "qcom_defconfig"
+
+# Otherwise buildman thinks this isn't an ARM platform
+CONFIG_ARM=y
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x994000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=14745600
+
+# Address where U-Boot will be loaded
+CONFIG_TEXT_BASE=0x9fc00000
+CONFIG_REMAKE_ELF=y
+
+CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs6490-rb3gen2"
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 8852e83..2a2253f 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -3,6 +3,7 @@
CONFIG_POSITION_INDEPENDENT=y
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_NR_DRAM_BANKS=24
CONFIG_DEFAULT_DEVICE_TREE="qcom/sdm845-db845c"
CONFIG_SYS_LOAD_ADDR=0xA0000000
CONFIG_BUTTON_CMD=y
@@ -44,6 +45,7 @@
CONFIG_CLK_QCOM_APQ8096=y
CONFIG_CLK_QCOM_QCM2290=y
CONFIG_CLK_QCOM_QCS404=y
+CONFIG_CLK_QCOM_SC7280=y
CONFIG_CLK_QCOM_SDM845=y
CONFIG_CLK_QCOM_SM6115=y
CONFIG_CLK_QCOM_SM8250=y
@@ -117,4 +119,3 @@
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_HEXDUMP=y
-CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 7e78f1d..2bcbdd6 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
@@ -90,7 +88,7 @@
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 89a5bcd..25213af 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -48,7 +48,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index a070445..5502858 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -48,7 +48,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 6b9fa27..98b931c 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -49,7 +49,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_AT91_MCK_BYPASS=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index dc5fcdb..a50fbce 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -16,6 +16,7 @@
CONFIG_FIT_CIPHER=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTMETH_ANDROID=y
+CONFIG_UPL=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_MEASURED_BOOT=y
CONFIG_BOOTSTAGE=y
@@ -39,6 +40,7 @@
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=6
+CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_STACKPROTECTOR=y
CONFIG_CMD_CPU=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index f372301..eb0f064 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x4000000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SPL_ENV_SUPPORT=y
@@ -285,3 +286,4 @@
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_SPL_LMB=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index f7b92dc..bc6a430 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -1,4 +1,4 @@
-CONFIG_TEXT_BASE=0x200000
+CONFIG_TEXT_BASE=0x400000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -253,3 +253,4 @@
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
+CONFIG_SPL_LMB=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 72483d8..96e9211 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -27,6 +27,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_UPL=y
+CONFIG_UPL_IN=y
+CONFIG_SPL_UPL_OUT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
@@ -35,6 +38,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BLOBLIST_SIZE=0x5000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 0243b15..bc4ff09 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -1,43 +1,33 @@
CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_SPL_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-sniper"
CONFIG_TARGET_SNIPER=y
-CONFIG_SPL_STACK=0x4020fffc
-CONFIG_SPL_BSS_START_ADDR=0x80000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};"
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=538
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_MAX_SIZE=0xec00
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SYS_PROMPT="sniper # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_CONS_INDEX=3
-CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index b8d9c84..a023e45 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -42,7 +42,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
CONFIG_SPL_MTD=y
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index caaabf3..9aa3560 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -103,6 +103,3 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_ERRNO_STR=y
-# CONFIG_LMB_USE_MAX_REGIONS is not set
-CONFIG_LMB_MEMORY_REGIONS=2
-CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 2e22bf8..806935f 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -190,6 +190,3 @@
CONFIG_WDT_STM32MP=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
-# CONFIG_LMB_USE_MAX_REGIONS is not set
-CONFIG_LMB_MEMORY_REGIONS=2
-CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig
index ffe7512..5f050ee 100644
--- a/configs/stm32mp15_defconfig
+++ b/configs/stm32mp15_defconfig
@@ -166,6 +166,3 @@
CONFIG_WDT_STM32MP=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
-# CONFIG_LMB_USE_MAX_REGIONS is not set
-CONFIG_LMB_MEMORY_REGIONS=2
-CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 74deaab..3c591d7 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -166,6 +166,3 @@
CONFIG_WDT_STM32MP=y
# CONFIG_BINMAN_FDT is not set
CONFIG_ERRNO_STR=y
-# CONFIG_LMB_USE_MAX_REGIONS is not set
-CONFIG_LMB_MEMORY_REGIONS=2
-CONFIG_LMB_RESERVED_REGIONS=16
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 87038cc..f5623a1 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -49,6 +49,3 @@
CONFIG_WDT_ARM_SMC=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_LMB_USE_MAX_REGIONS is not set
-CONFIG_LMB_MEMORY_REGIONS=2
-CONFIG_LMB_RESERVED_REGIONS=32
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index 49ff92f..db80e33 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -79,4 +79,3 @@
CONFIG_ZSTD=y
CONFIG_LIB_RATIONAL=y
# CONFIG_EFI_LOADER is not set
-# CONFIG_LMB_USE_MAX_REGIONS is not set
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index c8756a3..93f0bc5 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -92,7 +92,6 @@
CONFIG_AHCI_PCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_DM_PCA953X=y
-CONFIG_I2C_EEPROM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_DM_MTD=y
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index 25f5f5e..c5652e9 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -51,6 +51,7 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index e39ee2a..bd9ecd9 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index ef7f3b1..a7e969d 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -29,6 +29,7 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
@@ -47,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index fca91f7..15cfe2c 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -38,6 +38,7 @@
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
CONFIG_OF_SYSTEM_SETUP=y
@@ -60,6 +61,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index af889ec..7713454 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -47,7 +47,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VYBRID_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index c50afc4..2cef898 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -48,7 +48,7 @@
CONFIG_ENV_RANGE=0x80000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VYBRID_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index c39597c..e5c9c28 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -70,7 +70,7 @@
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_RPMB=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 4b73e15..e7da0de 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -47,7 +47,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 40a9b16..776af9a 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -73,6 +73,7 @@
CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_VERSAL=y
CONFIG_DFU_RAM=y
CONFIG_ARM_FFA_TRANSPORT=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index dc1754f..0d45914 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -72,6 +72,7 @@
CONFIG_IP_DEFRAG=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_CLK_VERSAL=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_RAM=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index f8b6a3f..b2921df 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -94,6 +94,7 @@
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
@@ -138,6 +139,7 @@
CONFIG_DM_ETH_PHY=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
+CONFIG_POWER_DOMAIN=y
CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_SPI=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 4c66c53..5a07edf 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -117,6 +117,7 @@
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 1133134..4912069 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -118,6 +118,7 @@
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index b1a03bd..580821a 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -15,7 +15,7 @@
#include <blk.h>
#include <log.h>
#include <part.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/unaligned.h>
diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions
index f4a9968..9ccb21c 100644
--- a/doc/I2C_Edge_Conditions
+++ b/doc/I2C_Edge_Conditions
@@ -31,12 +31,10 @@
!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
This reset edge condition could possibly be present in every I2C
-controller and device available. For boards where a I2C bus reset
-function can be implemented a i2c_init_board() function should be
-provided and enabled by #define'ing CONFIG_SYS_I2C_INIT_BOARD in your
-board's config file. Note that this is NOT necessary when using the
-bit-banging I2C driver (common/soft_i2c.c) as this already includes
-the I2C bus reset sequence.
+controller and device available.
+
+Note that this problem does not happen when using the bit-banging I2C driver
+(common/soft_i2c.c) as this already includes the I2C bus reset sequence.
Many thanks to Bill Hunter for finding this serious BUG.
diff --git a/doc/README.generic-board b/doc/README.generic-board
deleted file mode 100644
index bc35179..0000000
--- a/doc/README.generic-board
+++ /dev/null
@@ -1,135 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 Google, Inc
-# Simon Glass <sjg@chromium.org>
-
-Background
-----------
-
-U-Boot traditionally had a board.c file for each architecture. This introduced
-quite a lot of duplication, with each architecture tending to do
-initialisation slightly differently. To address this, a new 'generic board
-init' feature was introduced in March 2013 (further motivation is
-provided in the cover letter below).
-
-All boards and architectures have moved to this as of mid 2016.
-
-
-What has changed?
------------------
-
-The main change is that the arch/<arch>/lib/board.c file is removed in
-favour of common/board_f.c (for pre-relocation init) and common/board_r.c
-(for post-relocation init).
-
-Related to this, the global_data and bd_info structures now have a core set of
-fields which are common to all architectures. Architecture-specific fields
-have been moved to separate structures.
-
-
-Further Background
-------------------
-
-The full text of the original generic board series is reproduced below.
-
---8<-------------
-
-This series creates a generic board.c implementation which contains
-the essential functions of the major arch/xxx/lib/board.c files.
-
-What is the motivation for this change?
-
-1. There is a lot of repeated code in the board.c files. Any change to
-things like setting up the baud rate requires a change in 10 separate
-places.
-
-2. Since there are 10 separate files, adding a new feature which requires
-initialisation is painful since it must be independently added in 10
-places.
-
-3. As time goes by the architectures naturally diverge since there is limited
-pressure to compare features or even CONFIG options against similar things
-in other board.c files.
-
-4. New architectures must implement all the features all over again, and
-sometimes in subtle different ways. This places an unfair burden on getting
-a new architecture fully functional and running with U-Boot.
-
-5. While it is a bit of a tricky change, I believe it is worthwhile and
-achievable. There is no requirement that all code be common, only that
-the code that is common should be located in common/board.c rather than
-arch/xxx/lib/board.c.
-
-All the functions of board_init_f() and board_init_r() are broken into
-separate function calls so that they can easily be included or excluded
-for a particular architecture. It also makes it easier to adopt Graeme's
-initcall proposal when it is ready.
-
-http://lists.denx.de/pipermail/u-boot/2012-January/114499.html
-
-This series removes the dependency on generic relocation. So relocation
-happens as one big chunk and is still completely arch-specific. See the
-relocation series for a proposed solution to this for ARM:
-
-http://lists.denx.de/pipermail/u-boot/2011-December/112928.html
-
-or Graeme's recent x86 series v2:
-
-http://lists.denx.de/pipermail/u-boot/2012-January/114467.html
-
-Instead of moving over a whole architecture, this series takes the approach
-of simply enabling generic board support for an architecture. It is then up
-to each board to opt in by defining CONFIG_SYS_GENERIC_BOARD in the board
-config file. If this is not done, then the code will be generated as
-before. This allows both sets of code to co-exist until we are comfortable
-with the generic approach, and enough boards run.
-
-ARM is a relatively large board.c file and one which I can test, therefore
-I think it is a good target for this series. On the other hand, x86 is
-relatively small and simple, but different enough that it introduces a
-few issues to be solved. So I have chosen both ARM and x86 for this series.
-After a suggestion from Wolfgang I have added PPC also. This is the
-largest and most feature-full board, so hopefully we have all bases
-covered in this RFC.
-
-A generic global_data structure is also required. This might upset a few
-people. Here is my basic reasoning: most fields are the same, all
-architectures include and need it, most global_data.h files already have
-#ifdefs to select fields for a particular SOC, so it is hard to
-see why architecures are different in this area. We can perhaps add a
-way to put architecture-specific fields into a separate header file, but
-for now I have judged that to be counter-productive.
-
-Similarly we need a generic bd_info structure, since generic code will
-be accessing it. I have done this in the same way as global_data and the
-same comments apply.
-
-There was dicussion on the list about passing gd_t around as a parameter
-to pre-relocation init functions. I think this makes sense, but it can
-be done as a separate change, and this series does not require it.
-
-While this series needs to stand on its own (as with the link script
-cleanup series and the generic relocation series) the goal is the
-unification of the board init code. So I hope we can address issues with
-this in mind, rather than focusing too narrowly on particular ARM, x86 or
-PPC issues.
-
-I have run-tested ARM on Tegra Seaboard only. To try it out, define
-CONFIG_SYS_GENERIC_BOARD in your board file and rebuild. Most likely on
-x86 and PPC at least it will hang, but if you are lucky it will print
-something first :-)
-
-I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all
-ARM, PPC and x86 boards. There are a few failures due to errors in
-the board config, which I have sent patches for. The main issue is
-just the difference between __bss_end and __bss_end__.
-
-Note: the first group of commits are required for this series to build,
-but could be separated out if required. I have included them here for
-convenience.
-
-------------->8--
-
-Simon Glass, sjg@chromium.org
-March 2014
-Updated after final removal, May 2016
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 8474ece..de7eb38 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -82,9 +82,9 @@
Adopted toolchains
------------------
-Please check:
-https://www.denx.de/wiki/U-Boot/ColdFireNotes
-
+Currently the `kernel.org cross-development toolchains
+<https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/>`_ are
+used in the project CI builds.
ColdFire specific configuration options/settings
------------------------------------------------
diff --git a/doc/arch/mips.rst b/doc/arch/mips.rst
index b816608..aeb5824 100644
--- a/doc/arch/mips.rst
+++ b/doc/arch/mips.rst
@@ -8,9 +8,8 @@
Toolchains
----------
- * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
- * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
* `Buildroot <http://buildroot.uclibc.org/>`_
+ * `kernel.org cross-development toolchains <https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/>`_
Known Issues
------------
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 5f8db12..a8b0d7f 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -655,14 +655,17 @@
Sandbox has its own emulated memory starting at 0. Here are some of the things
that are mapped into that memory:
-======= ======================== ===============================
-Addr Config Usage
-======= ======================== ===============================
- 100 CONFIG_SYS_FDT_LOAD_ADDR Device tree
- b000 CONFIG_BLOBLIST_ADDR Blob list
- 10000 CFG_MALLOC_F_ADDR Early memory allocation
- f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer
- 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used
- as the SPL load buffer in spl_test_load().
- 200000 CONFIG_TEXT_BASE Load buffer for U-Boot (sandbox_spl only)
-======= ======================== ===============================
+======== ======================== ===============================
+Addr Config Usage
+======== ======================== ===============================
+ 100 CONFIG_SYS_FDT_LOAD_ADDR Device tree
+ b000 CONFIG_BLOBLIST_ADDR Blob list
+ 10000 CFG_MALLOC_F_ADDR Early memory allocation
+ f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer
+ 100000 TCG Event log TCG Event Log
+ 200000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used
+ 400000 CONFIG_TEXT_BASE Load buffer for U-Boot (sandbox_spl only)
+10000000 PCI address space (see test.dts)
+
+ff000000 Memory-mapping tags start here
+======== ======================== ===============================
diff --git a/doc/board/aspeed/ibex-ast2700.rst b/doc/board/aspeed/ibex-ast2700.rst
new file mode 100644
index 0000000..511bd08
--- /dev/null
+++ b/doc/board/aspeed/ibex-ast2700.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+IBex AST2700
+============
+
+AST2700 integrates an IBex RISC-V 32-bits CPU as the boot MCU to execute the
+first stage bootlaoder, namely SPL.
+
+Build
+-----
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make ibex-ast2700_defconfig` in u-boot root to build the image
+
+Running U-Boot SPL
+------------------
+
+The U-Boot SPL will boot in M mode and load the FIT image which includes
+the 2nd stage bootloaders executed by the main processor Cortex-A35.
+
+
+Burn U-Boot to SPI Flash
+------------------------
+
+Use SPI flash programmer (e.g. SF100) to program the u-book-spl.bin with the
+offset 0x80 bytes to the SPI flash beginning.
diff --git a/doc/board/aspeed/index.rst b/doc/board/aspeed/index.rst
new file mode 100644
index 0000000..d784c88
--- /dev/null
+++ b/doc/board/aspeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Aspeed
+======
+
+.. toctree::
+ :maxdepth: 2
+
+ ibex-ast2700
diff --git a/doc/board/atmel/at91ek.rst b/doc/board/atmel/at91ek.rst
index 6185b1d..a500b2f 100644
--- a/doc/board/atmel/at91ek.rst
+++ b/doc/board/atmel/at91ek.rst
@@ -6,8 +6,8 @@
Board mapping & boot media
--------------------------
-AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+AT91SAM9260EK & AT91SAM9G20EK
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Memory map::
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 417c128..3fb7c84 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -14,6 +14,7 @@
anbernic/index
apple/index
armltd/index
+ aspeed/index
asus/index
atmel/index
beacon/index
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 4955274..8c79699 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -7,5 +7,6 @@
:maxdepth: 2
dragonboard410c
+ rb3gen2
board
debugging
diff --git a/doc/board/qualcomm/rb3gen2.rst b/doc/board/qualcomm/rb3gen2.rst
new file mode 100644
index 0000000..4240606
--- /dev/null
+++ b/doc/board/qualcomm/rb3gen2.rst
@@ -0,0 +1,53 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Caleb Connolly <caleb.connolly@linaro.org>
+
+Qualcomm Robotics RB3 Gen 2
+===========================
+
+The RB3 Gen 2 is a development board based on the Qualcomm QCM6490 SoC (a derivative
+of SC7280). More information can be found on `Qualcomm's product page`_.
+
+U-Boot can be used as a replacement for Qualcomm's original EDK2 bootloader by
+flashing it directly to the uefi_a (or _b) partition.
+
+.. _Qualcomm's product page: https://www.qualcomm.com/developer/hardware/rb3-gen-2-development-kit
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``qcm6490``::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make qcm6490_defconfig
+ $ make -j8
+
+This will build ``u-boot.elf`` in the configured output directory.
+
+Although the RB3 Gen 2 does not have secure boot set up by default,
+the firmware still expects firmware ELF images to be "signed". The signature
+does not provide any security in this case, but it provides the firmware with
+some required metadata.
+
+To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_::
+
+ $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf
+
+Then install the resulting ``u-boot.mbn`` to the ``uefi_a`` partition
+on your device with ``fastboot flash uefi_a u-boot.mbn``.
+
+U-Boot should be running after a reboot (``fastboot reboot``).
+
+Note that fastboot is not yet supported in U-Boot on this board, as a result,
+to flash back the original firmware, or new versoins of the U-Boot, EDL mode
+must be used. This can be accessed by pressing the EDL mode button as described
+in the Qualcomm Linux documentation. A tool like bkerler's `edl`_ can be used
+for flashing with the firehose loader binary appropriate for the board.
+
+.. _qtestsign: https://github.com/msm8916-mainline/qtestsign
+.. _edl: https://github.com/bkerler/edl
+
+Usage
+-----
+
+The USB Type-A ports are connected via a PCIe USB hub, which is not supported yet.
+However, the Type-C port can be used with a powered USB dock to connect peripherals
+like a USB stick.
diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst
index 0cb9547..0a7b6fc 100644
--- a/doc/board/samsung/e850-96.rst
+++ b/doc/board/samsung/e850-96.rst
@@ -47,12 +47,13 @@
---------------
.. warning::
- At the moment both eMMC and USB features are not enabled in U-Boot. Flashing
+ At the moment USB is not enabled in U-Boot for this board. Although eMMC is
+ enabled, you won't be able to flash images over USB (fastboot). So flashing
U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can
be used then to perform USB boot and flash LittleKernel bootloader binary [7]_
to unbrick and revive the board. Flashing U-Boot binary might be helpful for
developers or anybody who want to check current state of U-Boot enablement on
- E850-96 (which is mostly serial console and related blocks).
+ E850-96 (which is mostly serial console, eMMC and related blocks).
Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain):
diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst
index 5ad4e59..77a7a4d 100644
--- a/doc/develop/commands.rst
+++ b/doc/develop/commands.rst
@@ -197,7 +197,6 @@
ctx.current = buf;
ut_assertok(acpi_fill_ssdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("dev 'acpi-test', type 1, size 2");
ut_assert_nextline("dev 'acpi-test2', type 1, size 2");
@@ -205,13 +204,11 @@
ctx.current = buf;
ut_assertok(acpi_inject_dsdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("dev 'acpi-test', type 2, size 2");
ut_assert_nextline("dev 'acpi-test2', type 2, size 2");
ut_assert_console_end();
- console_record_reset();
run_command("acpi items -d", 0);
ut_assert_nextline("dev 'acpi-test', type 2, size 2");
ut_assert_nextlines_are_dump(2);
@@ -223,4 +220,8 @@
return 0;
}
- DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
+
+Note that it is not necessary to call console_record_reset() unless you are
+trying to drop some unchecked output. Consider using ut_check_skip_to_line()
+instead.
diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst
index d143f27..2863154 100644
--- a/doc/develop/global_data.rst
+++ b/doc/develop/global_data.rst
@@ -51,6 +51,31 @@
whenever U-Boot is reentered. This is also relevant for the implementation of
function tracing. For setting the value of gd function set_gd() can be used.
+Guidelines
+----------
+
+The global_data structure is placed in some memory which is available very early
+after boot to allow for a minimum set of global variables during system
+initialisation (until the memory controller is set up and RAM can be used). It
+is the primary data structure passed from pre-relocation U-Boot to
+post-relocation, i.e. ``from board_init_f()`` ``to board_init_r()``.
+
+The global_data struct exists for the lifetime of U-Boot. Since the struct is
+used by all architectures, fields added should be useful for most architectures.
+Fields which are only needed on one or two architectures can be placed in the
+architecture-specific ``struct arch_global_data``.
+
+In any case the struct should be kept small, since it uses precious SRAM on
+many boards.
+
+SPL also uses global data, as well as U-Boot proper, so take care to avoid
+adding fields to SPL which are not actually used by SPL. You can create
+access functions or macros in the header file to avoid filling the C code with
+#ifdefs.
+
+A flags word is available, which provides a convenient means to track the state
+of various initialisation phases within U-Boot.
+
Global data structure
---------------------
diff --git a/doc/develop/historical/generic_board.rst b/doc/develop/historical/generic_board.rst
new file mode 100644
index 0000000..12550a1
--- /dev/null
+++ b/doc/develop/historical/generic_board.rst
@@ -0,0 +1,136 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2014 Google, Inc
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+
+Generic board
+-------------
+
+U-Boot traditionally had a board.c file for each architecture. This introduced
+quite a lot of duplication, with each architecture tending to do
+initialisation slightly differently. To address this, a new 'generic board
+init' feature was introduced in March 2013 (further motivation is
+provided in the cover letter below).
+
+All boards and architectures have moved to this as of mid 2016.
+
+
+What has changed?
+~~~~~~~~~~~~~~~~~
+
+The main change is that the arch/<arch>/lib/board.c file is removed in
+favour of common/board_f.c (for pre-relocation init) and common/board_r.c
+(for post-relocation init).
+
+Related to this, the global_data and bd_info structures now have a core set of
+fields which are common to all architectures. Architecture-specific fields
+have been moved to separate structures.
+
+
+Further Background
+~~~~~~~~~~~~~~~~~~
+
+The full text of the original generic board series is reproduced below.
+
+--8<-------------
+
+This series creates a generic board.c implementation which contains
+the essential functions of the major arch/xxx/lib/board.c files.
+
+What is the motivation for this change?
+
+1. There is a lot of repeated code in the board.c files. Any change to
+things like setting up the baud rate requires a change in 10 separate
+places.
+
+2. Since there are 10 separate files, adding a new feature which requires
+initialisation is painful since it must be independently added in 10
+places.
+
+3. As time goes by the architectures naturally diverge since there is limited
+pressure to compare features or even CONFIG options against similar things
+in other board.c files.
+
+4. New architectures must implement all the features all over again, and
+sometimes in subtle different ways. This places an unfair burden on getting
+a new architecture fully functional and running with U-Boot.
+
+5. While it is a bit of a tricky change, I believe it is worthwhile and
+achievable. There is no requirement that all code be common, only that
+the code that is common should be located in common/board.c rather than
+arch/xxx/lib/board.c.
+
+All the functions of board_init_f() and board_init_r() are broken into
+separate function calls so that they can easily be included or excluded
+for a particular architecture. It also makes it easier to adopt Graeme's
+initcall proposal when it is ready.
+
+http://lists.denx.de/pipermail/u-boot/2012-January/114499.html
+
+This series removes the dependency on generic relocation. So relocation
+happens as one big chunk and is still completely arch-specific. See the
+relocation series for a proposed solution to this for ARM:
+
+http://lists.denx.de/pipermail/u-boot/2011-December/112928.html
+
+or Graeme's recent x86 series v2:
+
+http://lists.denx.de/pipermail/u-boot/2012-January/114467.html
+
+Instead of moving over a whole architecture, this series takes the approach
+of simply enabling generic board support for an architecture. It is then up
+to each board to opt in by defining CONFIG_SYS_GENERIC_BOARD in the board
+config file. If this is not done, then the code will be generated as
+before. This allows both sets of code to co-exist until we are comfortable
+with the generic approach, and enough boards run.
+
+ARM is a relatively large board.c file and one which I can test, therefore
+I think it is a good target for this series. On the other hand, x86 is
+relatively small and simple, but different enough that it introduces a
+few issues to be solved. So I have chosen both ARM and x86 for this series.
+After a suggestion from Wolfgang I have added PPC also. This is the
+largest and most feature-full board, so hopefully we have all bases
+covered in this RFC.
+
+A generic global_data structure is also required. This might upset a few
+people. Here is my basic reasoning: most fields are the same, all
+architectures include and need it, most global_data.h files already have
+#ifdefs to select fields for a particular SOC, so it is hard to
+see why architecures are different in this area. We can perhaps add a
+way to put architecture-specific fields into a separate header file, but
+for now I have judged that to be counter-productive.
+
+Similarly we need a generic bd_info structure, since generic code will
+be accessing it. I have done this in the same way as global_data and the
+same comments apply.
+
+There was dicussion on the list about passing gd_t around as a parameter
+to pre-relocation init functions. I think this makes sense, but it can
+be done as a separate change, and this series does not require it.
+
+While this series needs to stand on its own (as with the link script
+cleanup series and the generic relocation series) the goal is the
+unification of the board init code. So I hope we can address issues with
+this in mind, rather than focusing too narrowly on particular ARM, x86 or
+PPC issues.
+
+I have run-tested ARM on Tegra Seaboard only. To try it out, define
+CONFIG_SYS_GENERIC_BOARD in your board file and rebuild. Most likely on
+x86 and PPC at least it will hang, but if you are lucky it will print
+something first :-)
+
+I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all
+ARM, PPC and x86 boards. There are a few failures due to errors in
+the board config, which I have sent patches for. The main issue is
+just the difference between __bss_end and __bss_end__.
+
+Note: the first group of commits are required for this series to build,
+but could be separated out if required. I have included them here for
+convenience.
+
+------------->8--
+
+Simon Glass, sjg@chromium.org
+March 2014
+
+Updated after final removal, May 2016
+
diff --git a/doc/develop/historical/index.rst b/doc/develop/historical/index.rst
new file mode 100644
index 0000000..e4462f5
--- /dev/null
+++ b/doc/develop/historical/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Historical Documents
+====================
+
+This section provides documentation about major changes in U-Boot over the
+years.
+
+.. toctree::
+ :maxdepth: 1
+
+ generic_board
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index c0107a7..0d0e60a 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -99,3 +99,11 @@
:maxdepth: 1
python_cq
+
+Historical documentation
+------------------------
+
+.. toctree::
+ :maxdepth: 2
+
+ historical/index
diff --git a/doc/develop/process.rst b/doc/develop/process.rst
index 0542b3f..0c6fb31 100644
--- a/doc/develop/process.rst
+++ b/doc/develop/process.rst
@@ -23,9 +23,8 @@
Phases of the Development Process
---------------------------------
-U-Boot development takes place in `Release Cycles
-<https://www.denx.de/wiki/U-Boot/ReleaseCycle>`_. A Release Cycle lasts
-normally for three months.
+U-Boot development takes place in a :doc:`release_cycle`. A Release Cycle
+lasts normally for three months.
The first three weeks of each Release Cycle are called *Merge Window*.
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 7286375..3cb63a0 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -73,11 +73,11 @@
* U-Boot v2024.10-rc3 was released on Mon 19 August 2024.
-.. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024.
+* U-Boot v2024.10-rc4 was released on Mon 02 September 2024.
-.. * U-Boot v2024.10-rc5 was released on Mon 16 September 2024.
+* U-Boot v2024.10-rc5 was released on Mon 16 September 2024.
-.. * U-Boot v2024.10-rc6 was released on Mon 30 September 2024.
+* U-Boot v2024.10-rc6 was released on Mon 30 September 2024.
Please note that the following dates are planned only and may be deviated from
as needed.
diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst
index 3f25b1d..e22b5e3 100644
--- a/doc/develop/sending_patches.rst
+++ b/doc/develop/sending_patches.rst
@@ -73,12 +73,13 @@
cover letter why they are ignored is desired.
* Send your patches as plain text messages: no HTML, no MIME, no links, no
- compression, no attachments. Just plain text. The best way the generate
- patches is by using the ``git format-patch`` command. Please use the
- ``master`` branch of the mainline U-Boot git repository
- (``https://source.denx.de/u-boot/u-boot.git``) as reference, unless (usually
- late in a release cycle) there has been an announcement to use the ``next``
- branch of this repository instead.
+ compression, no attachments. Just plain text. The best way to generate
+ patches is by using the ``git format-patch`` command. For a patch that is
+ fixing a bug or regression of some sort, please use the ``master`` branch of
+ the mainline U-Boot git repository located at
+ https://source.denx.de/u-boot/u-boot.git as reference. For new features, if
+ the ``next`` branch has been opened (which happens with the release of
+ ``-rc2``) that branch should be used, otherwise ``master`` is acceptable.
* Make sure that your mailer does not mangle the patch by automatic changes
like wrapping of longer lines etc.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 44b544f..a328ebf 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -81,7 +81,7 @@
perform some operations, with a 'checker' C unit test doing the checks
afterwards. This can be achieved with these steps:
-- Add the `UT_TESTF_MANUAL` flag to the checker test so that the `ut` command
+- Add the `UTF_MANUAL` flag to the checker test so that the `ut` command
does not run it by default
- Add a `_norun` suffix to the name so that pytest knows to skip it too
@@ -95,7 +95,7 @@
# Run the checker to make sure that everything worked
ut -f bootstd vbe_test_fixup_norun
-Note that apart from the `UT_TESTF_MANUAL` flag, the code in a 'manual' C test
+Note that apart from the `UTF_MANUAL` flag, the code in a 'manual' C test
is just like any other C test. It still uses ut_assert...() and other such
constructs, in this case to check that the expected things happened in the
Python test.
@@ -151,7 +151,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -167,7 +166,7 @@
return 0;
}
- MEM_TEST(mem_test_ms_b, UT_TESTF_CONSOLE_REC);
+ MEM_TEST(mem_test_ms_b, UTF_CONSOLE);
This runs the command directly in U-Boot, then checks the console output, also
directly in U-Boot. If run by itself this takes 100ms. For 1000 runs it takes
@@ -226,14 +225,17 @@
return 0;
}
- DM_TEST(dm_test_uclassname_what, UT_TESTF_SCAN_FDT);
+ DM_TEST(dm_test_uclassname_what, UTF_SCAN_FDT);
+
+Note that the convention is to NOT add a blank line before the macro, so that
+the function it relates to is more obvious.
Replace 'uclassname' with the name of your uclass, if applicable. Replace 'what'
with what you are testing.
The flags for DM_TEST() are defined in test/test.h and you typically want
-UT_TESTF_SCAN_FDT so that the devicetree is scanned and all devices are bound
-and ready for use. The DM_TEST macro adds UT_TESTF_DM automatically so that
+UTF_SCAN_FDT so that the devicetree is scanned and all devices are bound
+and ready for use. The DM_TEST macro adds UTF_DM automatically so that
the test runner knows it is a driver model test.
Driver model tests are special in that the entire driver model state is
@@ -263,7 +265,7 @@
return 0;
}
- MEM_TEST(mem_test_ms_new_thing, UT_TESTF_CONSOLE_REC);
+ MEM_TEST(mem_test_ms_new_thing, UTF_CONSOLE);
Note that the MEM_TEST() macros is defined at the top of the file.
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index d450b12..9448275 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -449,6 +449,33 @@
secure, assuming the firmware has been verified by a previous stage
boot loader.
+Dynamic Firmware Update GUIDs
+*****************************
+
+The image_type_id contains a GUID value which is specific to the image
+and board being updated, that is to say it should uniquely identify the
+board model (and revision if relevant) and image pair. Traditionally,
+these GUIDs are generated manually and hardcoded on a per-board basis,
+however this scheme makes it difficult to scale up to support many
+boards.
+
+To address this, v5 GUIDs can be used to generate board-specific GUIDs
+at runtime, based on the board's devicetree root compatible
+(e.g. "qcom,qrb5165-rb5").
+
+These strings are combined with the fw_image name to generate GUIDs for
+each image. Support for dynamic UUIDs can be enabled by generating a new
+namespace UUID and setting EFI_CAPSULE_NAMESPACE_GUID to it. Dynamic GUID
+generation is only enabled if the image_type_id property is unset for your
+firmware images, this is to avoid breaking existing boards with hardcoded
+GUIDs.
+
+The mkeficapsule tool can be used to determine the GUIDs for a particular
+board and image. It can be found in the tools directory.
+
+Firmware update images
+**********************
+
The firmware images structure defines the GUID values, image index
values and the name of the images that are to be updated through
the capsule update feature. These values are to be defined as part of
diff --git a/doc/develop/version.rst b/doc/develop/version.rst
index 5c9046a..de11836 100644
--- a/doc/develop/version.rst
+++ b/doc/develop/version.rst
@@ -9,7 +9,7 @@
weeks as the project heads to the next release. So 2020.10-rc1 was the first
release candidate (RC), tagged soon after 2020.07 was released.
-See https://www.denx.de/wiki/view/U-Boot/ReleaseCycle for full details.
+See :doc:`release_cycle` for full details.
Within the build system, various Makefile variables are created, making use of
VERSION, PATCHLEVEL and EXTRAVERSION defined at the top of 'Makefile'. There is
diff --git a/doc/device-tree-bindings/bootcount-syscon.txt b/doc/device-tree-bindings/bootcount-syscon.txt
index e124f7b..ea27b24 100644
--- a/doc/device-tree-bindings/bootcount-syscon.txt
+++ b/doc/device-tree-bindings/bootcount-syscon.txt
@@ -1,6 +1,6 @@
Bootcount Configuration
This is the implementation of the feature as described in
-https://www.denx.de/wiki/DULG/UBootBootCountLimit.
+https://docs.u-boot.org/en/latest/api/bootcount.html
Required Properties:
- compatible: must be "u-boot,bootcount-syscon".
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt
index 694d195..d90792b 100644
--- a/doc/device-tree-bindings/exynos/dwmmc.txt
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -12,7 +12,9 @@
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos-dwmmc: for exynos platforms
+ - samsung,exynos4412-dw-mshc: for Exynos4 platforms
+ - samsung,exynos-dwmmc: for Exynos5 platforms
+ - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block)
- reg: physical base address of the controller and length of memory mapped
region.
@@ -23,32 +25,38 @@
- #address-cells: should be 1.
- #size-cells: should be 0.
-- samsung,bus-width: The width of the bus used to interface the devices
+- bus-width: The width of the bus used to interface the devices
supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
. Typically the bus width is 4 or 8.
-- samsung,timing: The timing values to be written into the
- Drv/sample clock selection register of corresponding channel.
- . It is comprised of 3 values corresponding to the 3 fileds
- 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
- . SelClk_sample: Select sample clock among 8 shifted clocks.
- . SelClk_drv: Select drv clock among 8 shifted clocks.
- . DIVRATIO: Clock Divide ratio select.
- . The above 3 values are used by the clock phase shifter.
+- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu)
+ clock (0..7).
+- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode
+ operation.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
+- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode
+ operation. If missing, values from samsung,dw-mshc-sdr-timing are used.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
Example:
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <1>;
-}
+ bus-width = <8>;
+ non-removable;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+};
+
In the above example,
. The bus width is 8
- . Timing is comprised of 3 values as explained below
+ . Divider value for CLKSEL register is 3. The CIU clock rate will be
+ calculated as SDCLKIN / (3 + 1).
+ . SDR and DDR timings are comprised of 2 values as explained below
1 - SelClk_sample
3 - SelClk_drv
- 3 - DIVRATIO
- . The 'removable' flag indicates whether the the particilar device
+ . The 'non-removable' flag indicates whether the particular device
cannot be removed (always present) or it is a removable device.
- 1 - Indicates that the device is removable.
- 0 - Indicates that the device cannot be removed.
+ Flag is present - Indicates that the device cannot be removed.
+ Flag is not present - Indicates that the device is removable.
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
index bdf7e86..77b01b2 100644
--- a/doc/device-tree-bindings/spi/soft-spi.txt
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -8,14 +8,15 @@
Mandatory properties:
compatible: "spi-gpio"
-cs-gpios: GPIOs to use for SPI chip select (output)
+cs-gpios: GPIOs to use for SPI chip select (output), not required if num-chipselects = <0>
sck-gpios: GPIO to use for SPI clock (output)
And at least one of:
mosi-gpios: GPIO to use for SPI MOSI line (output)
miso-gpios: GPIO to use for SPI MISO line (input)
-Optional propertie:
+Optional properties:
spi-delay-us: Number of microseconds of delay between each CS transition
+num-chipselects: Number of chipselect lines
The GPIOs should be specified as required by the GPIO controller referenced.
The first cell holds the phandle of the controller and the second cell
diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
index c3d0f21..a726149 100644
--- a/doc/mkeficapsule.1
+++ b/doc/mkeficapsule.1
@@ -10,6 +10,9 @@
.B mkeficapsule
.RI [ options ] " " [ image-blob ] " " capsule-file
+.B mkeficapsule
+.RI guidgen " " [ GUID ] " " DTB " " IMAGE_NAME...
+
.SH "DESCRIPTION"
The
.B mkeficapsule
@@ -42,6 +45,10 @@
This type of image file can be generated by
.BR mkimage .
+mkeficapsule can also be used to simulate the dynamic GUID generation used to
+identify firmware images in capsule updates by providing the namespace guid, dtb
+for the board, and a list of firmware images.
+
.SH "OPTIONS"
.TP
@@ -117,6 +124,22 @@
.B "-d\fR,\fB --dump_sig"
Dump signature data into *.p7 file
+.SH "GUIDGEN OPTIONS"
+
+.TP
+.B "[GUID]"
+The namespace/salt GUID, by default this is EFI_CAPSULE_NAMESPACE_GUID.
+The format is:
+ xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+
+.TP
+.B DTB
+The device tree blob file for the board.
+
+.TP
+.B IMAGE_NAME...
+The names of the firmware images to generate GUIDs for.
+
.PP
.SH FILES
.TP
@@ -130,4 +153,4 @@
Written by AKASHI Takahiro <takahiro.akashi@linaro.org>
.SH HOMEPAGE
-http://www.denx.de/wiki/U-Boot/WebHome
+http://www.u-boot.org/
diff --git a/doc/usage/cmd/bind.rst b/doc/usage/cmd/bind.rst
index 2345778..67a0405 100644
--- a/doc/usage/cmd/bind.rst
+++ b/doc/usage/cmd/bind.rst
@@ -12,7 +12,7 @@
::
bind <node path> <driver>
- bind <class> <index> <driver>
+ bind <class> <seq> <driver>
Description
-----------
@@ -30,8 +30,8 @@
class
device class name
-index
- index of the parent device in the device class
+seq
+ sequence number of the parent device in the device class
driver
device driver name
@@ -46,7 +46,7 @@
.. code-block::
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
@@ -75,13 +75,13 @@
=> date
Cannot find RTC: err=-19
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
=> bind /pl031@9010000 rtc-pl031
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst
index 7651507..196b22d 100644
--- a/doc/usage/cmd/dm.rst
+++ b/doc/usage/cmd/dm.rst
@@ -112,9 +112,8 @@
uclass
Shows the name of the uclass for the device
-Index
- Shows the index number of the device, within the uclass. This shows the
- ordering within the uclass, but not the sequence number.
+Seq
+ Shows the sequence number of the device, within the uclass.
Probed
Shows `+` if the device is active
@@ -366,7 +365,7 @@
This example shows the abridged sandbox output::
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
demo 0 [ ] demo_shape_drv |-- demo_shape_drv
diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst
index 9629f97..b65d85b 100644
--- a/doc/usage/cmd/env.rst
+++ b/doc/usage/cmd/env.rst
@@ -79,7 +79,8 @@
environment to their default values.
var
- list of variable name.
+ list of variable names. If variable is not part of default
+ environment, it is deleted with a warning message on console.
\-a
all U-Boot environment.
\-f
@@ -309,6 +310,7 @@
Reset environment variable to default value, in memory::
=> env default bootcmd
+ => env default ipaddr serverip
=> env default -a
Save current environment in persistent storage::
diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst
index 5a64400..55391fd 100644
--- a/doc/usage/cmd/mmc.rst
+++ b/doc/usage/cmd/mmc.rst
@@ -15,6 +15,7 @@
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
+ mmc erase partname
mmc rescan [mode]
mmc part
mmc dev [dev] [part] [mode]
@@ -44,12 +45,15 @@
cnt
block count
-The 'mmc erase' command erases *cnt* blocks on the MMC device starting at block *blk#*.
+The 'mmc erase' command erases *cnt* blocks on the MMC device starting at block *blk#* or
+the entire partition specified by *partname*.
blk#
start block offset
cnt
block count
+ partname
+ partition name
The 'mmc rescan' command scans the available MMC device.
diff --git a/doc/usage/cmd/ums.rst b/doc/usage/cmd/ums.rst
index 9d379e3..e962227 100644
--- a/doc/usage/cmd/ums.rst
+++ b/doc/usage/cmd/ums.rst
@@ -48,7 +48,7 @@
-------------
The ums command is only available if CONFIG_CMD_USB_MASS_STORAGE=y
-and depends on CONFIG_USB_USB_GADGET and CONFIG_BLK.
+which depends on CONFIG_USB_GADGET_DOWNLOAD and CONFIG_BLK.
Return value
------------
diff --git a/doc/usage/cmd/unbind.rst b/doc/usage/cmd/unbind.rst
index 0309e90..1ae9c1b 100644
--- a/doc/usage/cmd/unbind.rst
+++ b/doc/usage/cmd/unbind.rst
@@ -12,8 +12,8 @@
::
unbind <node path>
- unbind <class> <index>
- unbind <class> <index> <driver>
+ unbind <class> <seq>
+ unbind <class> <seq> <driver>
Description
-----------
@@ -27,8 +27,8 @@
class
device class name
-index
- index of the device in the device class
+seq
+ sequence number of the device in the device class
driver
device driver name
@@ -43,7 +43,7 @@
.. code-block::
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
@@ -70,7 +70,7 @@
}
=> unbind /pl031@9010000
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
@@ -78,7 +78,7 @@
Cannot find a device with path /pl031@9010000
=> bind /pl031@9010000 rtc-pl031
=> dm tree
- Class Index Probed Driver Name
+ Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
...
diff --git a/doc/usage/cmd/upl.rst b/doc/usage/cmd/upl.rst
new file mode 100644
index 0000000..8d6ea5d
--- /dev/null
+++ b/doc/usage/cmd/upl.rst
@@ -0,0 +1,186 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+upl command
+===========
+
+Synopsis
+--------
+
+::
+
+ upl write
+ upl read <addr>
+ upl info [-v]
+
+Description
+-----------
+
+The *upl* command is used to test U-Boot's support for the Universal Payload
+Specification (UPL) firmware standard (see :doc:`../upl`). It allows creation of
+a fake handoff for use in testing.
+
+
+upl write
+~~~~~~~~~
+
+Write a fake UPL handoff structure. The `upladdr` environment variable is set to
+the address of this structure and `uplsize` is set to the size.
+
+
+upl read
+~~~~~~~~
+
+Read a UPL handoff structure into internal state. This allows testing that the
+handoff can be obtained.
+
+upl info
+~~~~~~~~
+
+Show basic information about usage of UPL:
+
+ UPL state
+ active or inactive (indicates whether U-Boot booted from UPL or not)
+
+ fit
+ Address of the FIT which was loaded
+
+ conf_offset 2a4
+ FIT offset of the chosen configuration
+
+For each image the following information is shown:
+
+ Image number
+ Images are numbered from 0
+
+ load
+ Address to which the image was loaded
+
+ size
+ Size of the loaded image
+
+ offset
+ FIT offset of the image
+
+ description
+ Description of the image
+
+
+Example
+-------
+
+This shows checking whether a UPL handoff was read at start-up::
+
+ => upl info
+ UPL state: active
+
+This shows how to use the command to write and display the handoff::
+
+ => upl write
+ UPL handoff written to bc8a5e0 size 662
+ => print upladdr
+ upladdr=bc8a5e0
+ => print uplsize
+ uplsize=662
+
+ > fdt addr ${upladdr}
+ Working FDT set to bc8a5e0
+ => fdt print
+ / {
+ #address-cells = <0x00000001>;
+ #size-cells = <0x00000001>;
+ options {
+ upl-params {
+ smbios = <0x00000123>;
+ acpi = <0x00000456>;
+ bootmode = "default", "s3";
+ addr-width = <0x0000002e>;
+ acpi-nvs-size = <0x00000100>;
+ };
+ upl-image {
+ fit = <0x00000789>;
+ conf-offset = <0x00000234>;
+ image-1 {
+ load = <0x00000001>;
+ size = <0x00000002>;
+ offset = <0x00000003>;
+ description = "U-Boot";
+ };
+ image-2 {
+ load = <0x00000004>;
+ size = <0x00000005>;
+ offset = <0x00000006>;
+ description = "ATF";
+ };
+ };
+ };
+ memory@0x10 {
+ reg = <0x00000010 0x00000020 0x00000030 0x00000040 0x00000050 0x00000060>;
+ };
+ memory@0x70 {
+ reg = <0x00000070 0x00000080>;
+ hotpluggable;
+ };
+ memory-map {
+ acpi@0x11 {
+ reg = <0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016 0x00000017 0x00000018 0x00000019 0x0000001a>;
+ usage = "acpi-reclaim";
+ };
+ u-boot@0x21 {
+ reg = <0x00000021 0x00000022>;
+ usage = "boot-data";
+ };
+ efi@0x23 {
+ reg = <0x00000023 0x00000024>;
+ usage = "runtime-code";
+ };
+ empty@0x25 {
+ reg = <0x00000025 0x00000026 0x00000027 0x00000028>;
+ };
+ acpi-things@0x2a {
+ reg = <0x0000002a 0x00000000>;
+ usage = "acpi-nvs", "runtime-code";
+ };
+ };
+ reserved-memory {
+ mmio@0x2b {
+ reg = <0x0000002b 0x0000002c>;
+ };
+ memory@0x2d {
+ reg = <0x0000002d 0x0000002e 0x0000002f 0x00000030>;
+ no-map;
+ };
+ };
+ serial@0xf1de0000 {
+ compatible = "ns16550a";
+ clock-frequency = <0x001c2000>;
+ current-speed = <0x0001c200>;
+ reg = <0xf1de0000 0x00000100>;
+ reg-io-shift = <0x00000002>;
+ reg-offset = <0x00000040>;
+ virtual-reg = <0x20000000>;
+ access-type = "mmio";
+ };
+ framebuffer@0xd0000000 {
+ compatible = "simple-framebuffer";
+ reg = <0xd0000000 0x10000000>;
+ width = <0x00000500>;
+ height = <0x00000500>;
+ stride = <0x00001400>;
+ format = "a8r8g8b8";
+ };
+ };
+ =>
+
+This showing reading the handoff into internal state::
+
+ => upl read bc8a5e0
+ Reading UPL at bc8a5e0
+ =>
+
+This shows getting basic information about UPL:
+
+ => upl info -v
+ UPL state: active
+ fit 1264000
+ conf_offset 2a4
+ image 0: load 200000 size 105f5c8 offset a4: U-Boot 2024.07-00770-g739ee12e8358 for sandbox board
diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst
index 45bc9ff..afeafa8 100644
--- a/doc/usage/cmd/ut.rst
+++ b/doc/usage/cmd/ut.rst
@@ -32,7 +32,7 @@
For a list of available test suites, type `ut` by itself.
-Each test is normally run once, although those marked with `UT_TESTF_DM` are
+Each test is normally run once, although those marked with `UTF_DM` are
run with livetree and flattree where possible. To run a test more than once,
use the `-r` flag.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 6a218c4..7056337 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -15,6 +15,7 @@
cmdline
semihosting
measured_boot
+ upl
Shell commands
--------------
@@ -115,6 +116,7 @@
cmd/tftpput
cmd/trace
cmd/true
+ cmd/upl
cmd/ums
cmd/unbind
cmd/ut
diff --git a/doc/usage/upl.rst b/doc/usage/upl.rst
new file mode 100644
index 0000000..3c4a10c
--- /dev/null
+++ b/doc/usage/upl.rst
@@ -0,0 +1,46 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Universal Payload
+-----------------
+
+`Universal Payload (UPL) <https://universalpayload.github.io/spec/index.html>`_
+is an Industry Standard for firmware components. UPL
+is designed to improve interoperability within the firmware industry, allowing
+mixing and matching of projects with less friction and fewer project-specific
+implementations. UPL is cross-platform, supporting ARM, x86 and RISC-V
+initially.
+
+UPL is defined in termns of two firmware components:
+
+`Platform Init`
+ Perhaps initial setup of the hardware and jumps to the payload.
+
+`Payload`
+ Selects the OS to boot
+
+In practice UPL can be used to handle any number of handoffs through the
+firmware startup process, with one program acting as platform init and another
+acting as the payload.
+
+UPL provides a standard for three main pieces:
+
+- file format for the payload, which may comprise multiple images to load
+- handoff format for the information the payload needs, such as serial port,
+ memory layout, etc.
+- machine state and register settings at the point of handoff
+
+See also the :doc:`cmd/upl`.
+
+UPL in U-Boot
+~~~~~~~~~~~~~
+
+U-Boot supports:
+
+- writing a UPL handoff (devicetree) in SPL
+- reading a UPL handoff in U-Boot proper
+- creating a FIT
+
+There are some new FIT features in UPL which are not yet supported in U-Boot.
+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+.. July 2024
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index a29d641..203f98e 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -6,6 +6,7 @@
#include <ahci.h>
#include <blk.h>
+#include <bootdev.h>
#include <cpu_func.h>
#include <dm.h>
#include <dwc_ahsata.h>
@@ -897,7 +898,11 @@
ret = blk_probe_or_unbind(dev);
if (ret < 0)
/* TODO: undo create */
- return ret;
+ return log_msg_ret("pro", ret);
+
+ ret = bootdev_setup_for_sibling_blk(blk, "sata_bootdev");
+ if (ret)
+ return log_msg_ret("bd", ret);
return 0;
}
diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c
index 84437d3..89cd516 100644
--- a/drivers/ata/sata.c
+++ b/drivers/ata/sata.c
@@ -9,9 +9,12 @@
* Dave Liu <daveliu@freescale.com>
*/
+#define LOG_CATEGORY UCLASS_AHCI
+
#include <ahci.h>
#include <blk.h>
#include <dm.h>
+#include <log.h>
#include <part.h>
#include <sata.h>
#include <dm/device-internal.h>
@@ -49,38 +52,39 @@
int sata_rescan(bool verbose)
{
+ struct uclass *uc;
+ struct udevice *dev; /* SATA controller */
int ret;
- struct udevice *dev;
if (verbose)
- printf("Removing devices on SATA bus...\n");
+ printf("scanning bus for devices...\n");
- blk_unbind_all(UCLASS_AHCI);
+ ret = uclass_get(UCLASS_AHCI, &uc);
+ if (ret)
+ return ret;
- ret = uclass_find_first_device(UCLASS_AHCI, &dev);
- if (ret || !dev) {
- printf("Cannot find SATA device (err=%d)\n", ret);
- return -ENOENT;
+ /* Remove all children of SATA devices (blk and bootdev) */
+ uclass_foreach_dev(dev, uc) {
+ log_debug("unbind %s\n", dev->name);
+ ret = device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
+ if (!ret)
+ ret = device_chld_unbind(dev, NULL);
+ if (ret && verbose) {
+ log_err("Unbinding from %s failed (%dE)\n",
+ dev->name, ret);
+ }
}
- ret = device_remove(dev, DM_REMOVE_NORMAL);
- if (ret) {
- printf("Cannot remove SATA device '%s' (err=%d)\n", dev->name, ret);
- return -ENOSYS;
- }
-
if (verbose)
printf("Rescanning SATA bus for devices...\n");
- ret = uclass_probe_all(UCLASS_AHCI);
-
- if (ret == -ENODEV) {
- if (verbose)
- printf("No SATA block device found\n");
- return 0;
+ uclass_foreach_dev_probe(UCLASS_AHCI, dev) {
+ ret = sata_scan(dev);
+ if (ret && verbose)
+ log_err("Scanning %s failed (%dE)\n", dev->name, ret);
}
- return ret;
+ return 0;
}
static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index ec34f1a..6c74d66 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -25,7 +25,7 @@
struct udevice *host_dev = dev_get_parent(dev);
struct host_sb_plat *plat = dev_get_plat(host_dev);
- if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
@@ -44,7 +44,7 @@
struct udevice *host_dev = dev_get_parent(dev);
struct host_sb_plat *plat = dev_get_plat(host_dev);
- if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 2105cea..fa6d8e7 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -6,14 +6,13 @@
bool "Enable support for checking boot count limit"
help
Enable checking for exceeding the boot count limit.
- More information: http://www.denx.de/wiki/DULG/UBootBootCountLimit
+ More information: https://docs.u-boot.org/en/latest/api/bootcount.html
if BOOTCOUNT_LIMIT
choice
prompt "Boot count device"
default BOOTCOUNT_AM33XX if AM33XX || SOC_DA8XX
- default BOOTCOUNT_AT91 if AT91SAM9XE
default BOOTCOUNT_GENERIC
config BOOTCOUNT_GENERIC
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9acbc47..d9d518d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -257,6 +257,7 @@
source "drivers/clk/owl/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sophgo/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/starfive/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 847b9b2..f9b90a3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -44,6 +44,7 @@
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
+obj-$(CONFIG_CLK_SOPHGO) += sophgo/
obj-$(CONFIG_CLK_SUNXI) += sunxi/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index a3cb109..537c696 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -81,7 +81,7 @@
{
if (post_divr_freq < MIN_POST_DIVR_FREQ ||
post_divr_freq > MAX_POST_DIVR_FREQ) {
- WARN(1, "%s: post-divider reference freq out of range: %lu",
+ WARN(1, "%s: post-divider reference freq out of range: %lu\n",
__func__, post_divr_freq);
return -ERANGE;
}
@@ -229,7 +229,7 @@
int range;
if (c->flags == 0) {
- WARN(1, "%s called with uninitialized PLL config", __func__);
+ WARN(1, "%s called with uninitialized PLL config\n", __func__);
return -EINVAL;
}
@@ -335,7 +335,7 @@
u64 n;
if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
- WARN(1, "external feedback mode not yet supported");
+ WARN(1, "external feedback mode not yet supported\n");
return ULONG_MAX;
}
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 2beb630..23b9787 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -66,6 +66,24 @@
21, 0x358, 1, 0x35c, 0),
};
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_APMIXED(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV, \
+ }
+
+static const struct mtk_gate apmixed_cgs[] = {
+ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, CLK_APMIXED_MAINPLL, 5),
+};
+
/* topckgen */
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -366,6 +384,20 @@
};
/* infracfg */
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
+
+static const struct mtk_parent infra_mux1_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ APMIXED_PARENT(CLK_APMIXED_MAINPLL),
+ APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN),
+ APMIXED_PARENT(CLK_APMIXED_MAINPLL),
+};
+
+static const struct mtk_composite infra_muxes[] = {
+ MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2),
+};
+
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
@@ -382,14 +414,26 @@
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
- GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+ GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
};
/* pericfg */
+static const int peribus_ck_parents[] = {
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL1_D4,
+};
+
+#define PERI_MUX(_id, _parents, _reg, _shift, _width) \
+ MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_composite peri_muxes[] = {
+ PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1),
+};
+
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
@@ -402,13 +446,17 @@
.sta_ofs = 0x1C,
};
-#define GATE_PERI0(_id, _parent, _shift) { \
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_PERI0(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
@@ -421,14 +469,14 @@
static const struct mtk_gate peri_cgs[] = {
/* PERI0 */
GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
- GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
- GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
- GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
- GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
- GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
- GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
- GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
- GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+ GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+ GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+ GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+ GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+ GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+ GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+ GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+ GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
@@ -436,12 +484,13 @@
GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+ GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21),
GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
- GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+ GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
@@ -550,12 +599,33 @@
GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
};
+static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
+ .xtal2_rate = 25 * MHZ,
+ .plls = apmixed_plls,
+ .gates_offs = CLK_APMIXED_MAIN_CORE_EN,
+ .gates = apmixed_cgs,
+};
+
+static const struct mtk_clk_tree mt7622_infra_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .muxes_offs = CLK_INFRA_MUX1_SEL,
+ .gates_offs = CLK_INFRA_DBGCLK_PD,
+ .muxes = infra_muxes,
+ .gates = infra_cgs,
+};
+
+static const struct mtk_clk_tree mt7622_peri_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .muxes_offs = CLK_PERIBUS_SEL,
+ .gates_offs = CLK_PERI_THERM_PD,
+ .muxes = peri_muxes,
+ .gates = peri_cgs,
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
- .xtal2_rate = 25 * MHZ,
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
- .plls = apmixed_plls,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
@@ -582,7 +652,7 @@
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
- ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
+ ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree);
if (ret)
return ret;
@@ -603,12 +673,12 @@
static int mt7622_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree);
}
static int mt7622_pericfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree);
}
static int mt7622_pciesys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 5072c99..d0b80f4 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -25,6 +25,22 @@
#define AXI_DIV_SEL(x) (x)
/* apmixedsys */
+static const int pll_id_offs_map[] = {
+ [CLK_APMIXED_ARMPLL] = 0,
+ [CLK_APMIXED_MAINPLL] = 1,
+ [CLK_APMIXED_UNIVPLL] = 2,
+ [CLK_APMIXED_MMPLL] = 3,
+ [CLK_APMIXED_MSDCPLL] = 4,
+ [CLK_APMIXED_TVDPLL] = 5,
+ [CLK_APMIXED_AUD1PLL] = 6,
+ [CLK_APMIXED_TRGPLL] = 7,
+ [CLK_APMIXED_ETHPLL] = 8,
+ [CLK_APMIXED_VDECPLL] = 9,
+ [CLK_APMIXED_HADDS2PLL] = 10,
+ [CLK_APMIXED_AUD2PLL] = 11,
+ [CLK_APMIXED_TVD2PLL] = 12,
+};
+
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
.id = _id, \
@@ -71,6 +87,176 @@
};
/* topckgen */
+
+/* Fixed CLK exposed upstream by the hdmi PHY driver */
+#define CLK_TOP_HDMITX_CLKDIG_CTS CLK_TOP_NR
+
+static const int top_id_offs_map[CLK_TOP_NR + 1] = {
+ /* Fixed CLK */
+ [CLK_TOP_DPI] = 0,
+ [CLK_TOP_DMPLL] = 1,
+ [CLK_TOP_VENCPLL] = 2,
+ [CLK_TOP_HDMI_0_PIX340M] = 3,
+ [CLK_TOP_HDMI_0_DEEP340M] = 4,
+ [CLK_TOP_HDMI_0_PLL340M] = 5,
+ [CLK_TOP_HADDS2_FB] = 6,
+ [CLK_TOP_WBG_DIG_416M] = 7,
+ [CLK_TOP_DSI0_LNTC_DSI] = 8,
+ [CLK_TOP_HDMI_SCL_RX] = 9,
+ [CLK_TOP_32K_EXTERNAL] = 10,
+ [CLK_TOP_HDMITX_CLKDIG_CTS] = 11,
+ [CLK_TOP_AUD_EXT1] = 12,
+ [CLK_TOP_AUD_EXT2] = 13,
+ [CLK_TOP_NFI1X_PAD] = 14,
+ /* Factor CLK */
+ [CLK_TOP_SYSPLL] = 15,
+ [CLK_TOP_SYSPLL_D2] = 16,
+ [CLK_TOP_SYSPLL_D3] = 17,
+ [CLK_TOP_SYSPLL_D5] = 18,
+ [CLK_TOP_SYSPLL_D7] = 19,
+ [CLK_TOP_SYSPLL1_D2] = 20,
+ [CLK_TOP_SYSPLL1_D4] = 21,
+ [CLK_TOP_SYSPLL1_D8] = 22,
+ [CLK_TOP_SYSPLL1_D16] = 23,
+ [CLK_TOP_SYSPLL2_D2] = 24,
+ [CLK_TOP_SYSPLL2_D4] = 25,
+ [CLK_TOP_SYSPLL2_D8] = 26,
+ [CLK_TOP_SYSPLL3_D2] = 27,
+ [CLK_TOP_SYSPLL3_D4] = 28,
+ [CLK_TOP_SYSPLL4_D2] = 29,
+ [CLK_TOP_SYSPLL4_D4] = 30,
+ [CLK_TOP_UNIVPLL] = 31,
+ [CLK_TOP_UNIVPLL_D2] = 32,
+ [CLK_TOP_UNIVPLL_D3] = 33,
+ [CLK_TOP_UNIVPLL_D5] = 34,
+ [CLK_TOP_UNIVPLL_D7] = 35,
+ [CLK_TOP_UNIVPLL_D26] = 36,
+ [CLK_TOP_UNIVPLL_D52] = 37,
+ [CLK_TOP_UNIVPLL_D108] = 38,
+ [CLK_TOP_USB_PHY48M] = 39,
+ [CLK_TOP_UNIVPLL1_D2] = 40,
+ [CLK_TOP_UNIVPLL1_D4] = 41,
+ [CLK_TOP_UNIVPLL1_D8] = 42,
+ [CLK_TOP_UNIVPLL2_D2] = 43,
+ [CLK_TOP_UNIVPLL2_D4] = 44,
+ [CLK_TOP_UNIVPLL2_D8] = 45,
+ [CLK_TOP_UNIVPLL2_D16] = 46,
+ [CLK_TOP_UNIVPLL2_D32] = 47,
+ [CLK_TOP_UNIVPLL3_D2] = 48,
+ [CLK_TOP_UNIVPLL3_D4] = 49,
+ [CLK_TOP_UNIVPLL3_D8] = 50,
+ [CLK_TOP_MSDCPLL] = 51,
+ [CLK_TOP_MSDCPLL_D2] = 52,
+ [CLK_TOP_MSDCPLL_D4] = 53,
+ [CLK_TOP_MSDCPLL_D8] = 54,
+ [CLK_TOP_MMPLL] = 55,
+ [CLK_TOP_MMPLL_D2] = 56,
+ [CLK_TOP_DMPLL_D2] = 57,
+ [CLK_TOP_DMPLL_D4] = 58,
+ [CLK_TOP_DMPLL_X2] = 59,
+ [CLK_TOP_TVDPLL] = 60,
+ [CLK_TOP_TVDPLL_D2] = 61,
+ [CLK_TOP_TVDPLL_D4] = 62,
+ [CLK_TOP_VDECPLL] = 63,
+ [CLK_TOP_TVD2PLL] = 64,
+ [CLK_TOP_TVD2PLL_D2] = 65,
+ [CLK_TOP_MIPIPLL] = 66,
+ [CLK_TOP_MIPIPLL_D2] = 67,
+ [CLK_TOP_MIPIPLL_D4] = 68,
+ [CLK_TOP_HDMIPLL] = 69,
+ [CLK_TOP_HDMIPLL_D2] = 70,
+ [CLK_TOP_HDMIPLL_D3] = 71,
+ [CLK_TOP_ARMPLL_1P3G] = 72,
+ [CLK_TOP_AUDPLL] = 73,
+ [CLK_TOP_AUDPLL_D4] = 74,
+ [CLK_TOP_AUDPLL_D8] = 75,
+ [CLK_TOP_AUDPLL_D16] = 76,
+ [CLK_TOP_AUDPLL_D24] = 77,
+ [CLK_TOP_AUD1PLL_98M] = 78,
+ [CLK_TOP_AUD2PLL_90M] = 79,
+ [CLK_TOP_HADDS2PLL_98M] = 80,
+ [CLK_TOP_HADDS2PLL_294M] = 81,
+ [CLK_TOP_ETHPLL_500M] = 82,
+ [CLK_TOP_CLK26M_D8] = 83,
+ [CLK_TOP_32K_INTERNAL] = 84,
+ [CLK_TOP_AXISEL_D4] = 85,
+ [CLK_TOP_8BDAC] = 86,
+ /* MUX CLK */
+ [CLK_TOP_AXI_SEL] = 87,
+ [CLK_TOP_MEM_SEL] = 88,
+ [CLK_TOP_DDRPHYCFG_SEL] = 89,
+ [CLK_TOP_MM_SEL] = 90,
+ [CLK_TOP_PWM_SEL] = 91,
+ [CLK_TOP_VDEC_SEL] = 92,
+ [CLK_TOP_MFG_SEL] = 93,
+ [CLK_TOP_CAMTG_SEL] = 94,
+ [CLK_TOP_UART_SEL] = 95,
+ [CLK_TOP_SPI0_SEL] = 96,
+ [CLK_TOP_USB20_SEL] = 97,
+ [CLK_TOP_MSDC30_0_SEL] = 98,
+ [CLK_TOP_MSDC30_1_SEL] = 99,
+ [CLK_TOP_MSDC30_2_SEL] = 100,
+ [CLK_TOP_AUDIO_SEL] = 101,
+ [CLK_TOP_AUDINTBUS_SEL] = 102,
+ [CLK_TOP_PMICSPI_SEL] = 103,
+ [CLK_TOP_SCP_SEL] = 104,
+ [CLK_TOP_DPI0_SEL] = 105,
+ [CLK_TOP_DPI1_SEL] = 106,
+ [CLK_TOP_TVE_SEL] = 107,
+ [CLK_TOP_HDMI_SEL] = 108,
+ [CLK_TOP_APLL_SEL] = 109,
+ [CLK_TOP_RTC_SEL] = 110,
+ [CLK_TOP_NFI2X_SEL] = 111,
+ [CLK_TOP_EMMC_HCLK_SEL] = 112,
+ [CLK_TOP_FLASH_SEL] = 113,
+ [CLK_TOP_DI_SEL] = 114,
+ [CLK_TOP_NR_SEL] = 115,
+ [CLK_TOP_OSD_SEL] = 116,
+ [CLK_TOP_HDMIRX_BIST_SEL] = 117,
+ [CLK_TOP_INTDIR_SEL] = 118,
+ [CLK_TOP_ASM_I_SEL] = 119,
+ [CLK_TOP_ASM_M_SEL] = 120,
+ [CLK_TOP_ASM_H_SEL] = 121,
+ [CLK_TOP_MS_CARD_SEL] = 122,
+ [CLK_TOP_ETHIF_SEL] = 123,
+ [CLK_TOP_HDMIRX26_24_SEL] = 124,
+ [CLK_TOP_MSDC30_3_SEL] = 125,
+ [CLK_TOP_CMSYS_SEL] = 126,
+ [CLK_TOP_SPI1_SEL] = 127,
+ [CLK_TOP_SPI2_SEL] = 128,
+ [CLK_TOP_8BDAC_SEL] = 129,
+ [CLK_TOP_AUD2DVD_SEL] = 130,
+ [CLK_TOP_PADMCLK_SEL] = 131,
+ [CLK_TOP_AUD_MUX1_SEL] = 132,
+ [CLK_TOP_AUD_MUX2_SEL] = 133,
+ [CLK_TOP_AUDPLL_MUX_SEL] = 134,
+ [CLK_TOP_AUD_K1_SRC_SEL] = 135,
+ [CLK_TOP_AUD_K2_SRC_SEL] = 136,
+ [CLK_TOP_AUD_K3_SRC_SEL] = 137,
+ [CLK_TOP_AUD_K4_SRC_SEL] = 138,
+ [CLK_TOP_AUD_K5_SRC_SEL] = 139,
+ [CLK_TOP_AUD_K6_SRC_SEL] = 140,
+ /* Misc CLK only used as parents */
+ [CLK_TOP_AUD_EXTCK1_DIV] = 141,
+ [CLK_TOP_AUD_EXTCK2_DIV] = 142,
+ [CLK_TOP_AUD_MUX1_DIV] = 143,
+ [CLK_TOP_AUD_MUX2_DIV] = 144,
+ [CLK_TOP_AUD_K1_SRC_DIV] = 145,
+ [CLK_TOP_AUD_K2_SRC_DIV] = 146,
+ [CLK_TOP_AUD_K3_SRC_DIV] = 147,
+ [CLK_TOP_AUD_K4_SRC_DIV] = 148,
+ [CLK_TOP_AUD_K5_SRC_DIV] = 149,
+ [CLK_TOP_AUD_K6_SRC_DIV] = 150,
+ [CLK_TOP_AUD_48K_TIMING] = 151,
+ [CLK_TOP_AUD_44K_TIMING] = 152,
+ [CLK_TOP_AUD_I2S1_MCLK] = 153,
+ [CLK_TOP_AUD_I2S2_MCLK] = 154,
+ [CLK_TOP_AUD_I2S3_MCLK] = 155,
+ [CLK_TOP_AUD_I2S4_MCLK] = 156,
+ [CLK_TOP_AUD_I2S5_MCLK] = 157,
+ [CLK_TOP_AUD_I2S6_MCLK] = 158,
+};
+
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -586,21 +772,26 @@
.sta_ofs = 0x48,
};
-#define GATE_INFRA(_id, _parent, _shift) { \
+#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &infra_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_INFRA(_id, _parent, _shift) \
+ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA_XTAL(_id, _parent, _shift) \
+ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
+
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
- GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
- GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
+ GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5),
+ GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6),
GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
@@ -616,6 +807,74 @@
};
/* pericfg */
+static const int peri_id_offs_map[] = {
+ /* MUX CLK */
+ [CLK_PERI_UART0_SEL] = 1,
+ [CLK_PERI_UART1_SEL] = 2,
+ [CLK_PERI_UART2_SEL] = 3,
+ [CLK_PERI_UART3_SEL] = 4,
+ /* GATE CLK */
+ [CLK_PERI_NFI] = 5,
+ [CLK_PERI_THERM] = 6,
+ [CLK_PERI_PWM1] = 7,
+ [CLK_PERI_PWM2] = 8,
+ [CLK_PERI_PWM3] = 9,
+ [CLK_PERI_PWM4] = 10,
+ [CLK_PERI_PWM5] = 11,
+ [CLK_PERI_PWM6] = 12,
+ [CLK_PERI_PWM7] = 13,
+ [CLK_PERI_PWM] = 14,
+ [CLK_PERI_USB0] = 15,
+ [CLK_PERI_USB1] = 16,
+ [CLK_PERI_AP_DMA] = 17,
+ [CLK_PERI_MSDC30_0] = 18,
+ [CLK_PERI_MSDC30_1] = 19,
+ [CLK_PERI_MSDC30_2] = 20,
+ [CLK_PERI_MSDC30_3] = 21,
+ [CLK_PERI_MSDC50_3] = 22,
+ [CLK_PERI_NLI] = 23,
+ [CLK_PERI_UART0] = 24,
+ [CLK_PERI_UART1] = 25,
+ [CLK_PERI_UART2] = 26,
+ [CLK_PERI_UART3] = 27,
+ [CLK_PERI_BTIF] = 28,
+ [CLK_PERI_I2C0] = 29,
+ [CLK_PERI_I2C1] = 30,
+ [CLK_PERI_I2C2] = 31,
+ [CLK_PERI_I2C3] = 32,
+ [CLK_PERI_AUXADC] = 33,
+ [CLK_PERI_SPI0] = 34,
+ [CLK_PERI_ETH] = 35,
+ [CLK_PERI_USB0_MCU] = 36,
+ [CLK_PERI_USB1_MCU] = 37,
+ [CLK_PERI_USB_SLV] = 38,
+ [CLK_PERI_GCPU] = 39,
+ [CLK_PERI_NFI_ECC] = 40,
+ [CLK_PERI_NFI_PAD] = 41,
+ [CLK_PERI_FLASH] = 42,
+ [CLK_PERI_HOST89_INT] = 43,
+ [CLK_PERI_HOST89_SPI] = 44,
+ [CLK_PERI_HOST89_DVD] = 45,
+ [CLK_PERI_SPI1] = 46,
+ [CLK_PERI_SPI2] = 47,
+ [CLK_PERI_FCI] = 48,
+};
+
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
+
+static const struct mtk_parent uart_ck_sel_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UART_SEL),
+};
+
+static const struct mtk_composite peri_muxes[] = {
+ MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1),
+ MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1),
+ MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1),
+ MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1),
+};
+
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
@@ -628,13 +887,17 @@
.sta_ofs = 0x1C,
};
-#define GATE_PERI0(_id, _parent, _shift) { \
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_PERI0(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
@@ -672,10 +935,10 @@
GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
- GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
- GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
+ GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27),
+ GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28),
GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
- GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
+ GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30),
GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
@@ -730,12 +993,17 @@
GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
};
-static const struct mtk_clk_tree mt7623_clk_tree = {
- .xtal_rate = 26 * MHZ,
+static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
.xtal2_rate = 26 * MHZ,
- .fdivs_offs = CLK_TOP_SYSPLL,
- .muxes_offs = CLK_TOP_AXI_SEL,
+ .id_offs_map = pll_id_offs_map,
.plls = apmixed_plls,
+};
+
+static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .id_offs_map = top_id_offs_map,
+ .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL],
+ .muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL],
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
@@ -760,7 +1028,7 @@
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
- ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
+ ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
if (ret)
return ret;
@@ -774,27 +1042,45 @@
static int mt7623_topckgen_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7623_clk_tree);
+ return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
}
+static const struct mtk_clk_tree mt7623_clk_gate_tree = {
+ /* Each CLK ID for gates clock starts at index 1 */
+ .gates_offs = 1,
+ .xtal_rate = 26 * MHZ,
+};
+
static int mt7623_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ infra_cgs);
}
+static const struct mtk_clk_tree mt7623_clk_peri_tree = {
+ .id_offs_map = peri_id_offs_map,
+ .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
+ .gates_offs = peri_id_offs_map[CLK_PERI_NFI],
+ .muxes = peri_muxes,
+ .gates = peri_cgs,
+ .xtal_rate = 26 * MHZ,
+};
+
static int mt7623_pericfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
}
static int mt7623_hifsys_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ hif_cgs);
}
static int mt7623_ethsys_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ eth_cgs);
}
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
@@ -889,7 +1175,7 @@
.of_match = mt7623_pericfg_compat,
.probe = mt7623_pericfg_probe,
.priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
+ .ops = &mtk_clk_infrasys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 13dc3df..9707391 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -29,204 +29,204 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk fixed_pll_clks[] = {
- FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+ PLL_FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", CLK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", CLK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", CLK_APMIXED_MMPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", CLK_APMIXED_MMPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", CLK_APMIXED_APLL2, 1,
1),
- PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+ PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", CLK_APMIXED_NET1PLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", CLK_APMIXED_NET2PLL, 1,
1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+ CLK_APMIXED_WEDMCUPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", CLK_APMIXED_SGMPLL, 1, 1),
+ TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2),
+ TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1,
1220),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_FAUD, "faud", CLK_TOP_AUD_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NFI1X, "nfi1x", CLK_TOP_NFI1X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CLK_TOP_CB_CKSQ_40M, 1,
1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
+ TOP_FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", CLK_TOP_SPINFI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPI, "spi", CLK_TOP_SPI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPIM_MST, "spim_mst", CLK_TOP_SPIM_MST_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_UART_BCK, "uart_bck", CLK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", CLK_TOP_PWM_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", CLK_TOP_I2C_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", CLK_TOP_PEXTP_TL_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", CLK_TOP_EMMC_208M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", CLK_TOP_EMMC_400M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", CLK_TOP_DRAMC_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", CLK_TOP_DRAMC_MD32_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
+ TOP_FACTOR(CLK_TOP_SYSAXI, "sysaxi", CLK_TOP_SYSAXI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SYSAPB, "sysapb", CLK_TOP_SYSAPB_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", CLK_TOP_ARM_DB_MAIN_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
+ TOP_FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", CLK_TOP_AP2CNN_HOST_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS, "netsys", CLK_TOP_NETSYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", CLK_TOP_NETSYS_500M_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+ CLK_TOP_NETSYS_MCU_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", CLK_TOP_NETSYS_2X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_325M, "sgm_325m", CLK_TOP_SGM_325M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_REG, "sgm_reg", CLK_TOP_SGM_REG_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_F26M, "csw_f26m", CLK_TOP_F26M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EIP97B, "eip97b", CLK_TOP_EIP97B_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", CLK_TOP_USB3_PHY_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD, "aud", CLK_TOP_FAUD, 1, 1),
+ TOP_FACTOR(CLK_TOP_A1SYS, "a1sys", CLK_TOP_A1SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD_L, "aud_l", CLK_TOP_AUD_L_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", CLK_TOP_U2U3_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", CLK_TOP_U2U3_SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", CLK_TOP_U2U3_XHCI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 1,
1),
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4,
+ CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6,
+ CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8,
+ CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 };
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4,
+ CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 };
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8,
+ CLK_TOP_M_D8_D2 };
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K };
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_RTC_32K };
+static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_RTC_32K };
static const int emmc_208m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
- CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_MM_D6
+ CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4,
+ CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_MM_D6
};
-static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
+static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2,
+ CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 };
-static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 };
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_WEDMCU_208M };
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
+static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 };
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 };
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D6 };
+static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_D6 };
-static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D4 };
+static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D8_D4 };
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
+static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 };
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5 };
+static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET1_D5 };
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M };
+static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M,
+ CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M };
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_800M,
+ CLK_TOP_CB_MM_720M };
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_SGM_325M };
+static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_SGM_325M };
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
+static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 };
-static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
- CK_TOP_NET1_D5_D2 };
+static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2,
+ CLK_TOP_NET1_D5_D2 };
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M };
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 };
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M,
+ CLK_TOP_M_D8_D2 };
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
- CK_TOP_M_D8_D2 };
+static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4,
+ CLK_TOP_M_D8_D2 };
-static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 };
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 };
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D3_D5 };
+static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_MM_D3_D5 };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -242,174 +242,150 @@
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite top_muxes[] = {
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
3, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
8, 3, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
23, 0x1c0, 2),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
24, 3, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
2, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
15, 0x1c0, 5),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
23, 0x1c0, 6),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
0x24, 0x28, 0, 3, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 8, 2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 16, 1, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 24, 1, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
0x38, 8, 1, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
0x38, 16, 1, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
+ TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
0x48, 8, 1, 15, 0x1c0, 17),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
0x54, 0x58, 0, 2, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
+ TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
0x54, 0x58, 8, 1, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
0x58, 16, 1, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
0x58, 24, 3, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
15, 0x1c0, 25),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
24, 2, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
0x78, 0, 2, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
+ TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
1, 15, 0x1c0, 29),
- TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 24, 1, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
};
/* INFRA FIXED DIV */
static const struct mtk_fixed_factor infra_fixed_divs[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
- TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
- INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
- 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M,
- 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
- CK_TOP_PEXTP_TL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", CLK_TOP_SYSAXI_SEL, 1, 2),
};
/* INFRASYS MUX PARENTS */
-static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
-static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
+static const struct mtk_parent infra_uart0_parents[] = {
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_UART_SEL)
+};
+
+static const struct mtk_parent infra_spi0_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPI_SEL)
+};
-static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
+static const struct mtk_parent infra_spi1_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPIM_MST_SEL)
+};
-static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM };
+static const struct mtk_parent infra_pwm1_parents[] = {
+ VOID_PARENT,
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
-static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM };
+static const struct mtk_parent infra_pwm_bsel_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ INFRA_PARENT(CLK_INFRA_66M_MCK),
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
-static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
- CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK};
+static const struct mtk_parent infra_pcie_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
+};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
{ \
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
- .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* INFRA MUX */
static const struct mtk_composite infra_muxes[] = {
- INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
0x10, 0, 1),
- INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
0x10, 1, 1),
- INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
0x10, 2, 1),
- INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
4, 1),
- INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
5, 1),
- INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
6, 1),
- INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
- 9, 2),
- INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
- 11, 2),
- INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
+ 9, 1),
+ INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
+ 11, 1),
+ INFRA_MUX(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10,
+ 15, 1),
+ INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
0x10, 13, 2),
- INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+ INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
0, 2),
};
@@ -431,92 +407,105 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
/* INFRA GATE */
-static const struct mtk_gate infracfg_ao_gates[] = {
- GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
- GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
- GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
- GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
- GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
- GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
- GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
- GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
- GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
- GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
- 11),
- GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
- 13),
- GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
- 14),
- GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
- GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
- GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
- GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
- GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
- GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
- GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
- GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
- GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
- GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6),
- GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
- 7),
- GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
- GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
+static const struct mtk_gate infracfg_gates[] = {
+ GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_66M_MCK, 0),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_66M_MCK, 1),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM3_CK, "infra_pwm3", CLK_INFRA_PWM3_SEL, 27),
+ GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI, 6),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI, 8),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS,
+ 11),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER,
+ 13),
+ GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
+ 14),
+ GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_66M_MCK, 15),
+ GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_66M_MCK, 16),
+ GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_66M_MCK, 24),
+ GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
+ GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2c0", CLK_TOP_I2C_BCK, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_CK, "infra_spi2", CLK_INFRA_SPI2_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CLK_INFRA_66M_MCK,
+ 7),
+ GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X, 8),
+ GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_BCK,
9),
- GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
- GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
- GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
- GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
- 13),
- GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
- 14),
- GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
- GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
- GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
- CK_INFRA_FMSDC_HCK_CK, 17),
- GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
- CK_INFRA_PERI_133M, 18),
- GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
- 19),
- GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20),
- GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
- GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
- 23),
- GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK,
- 25),
- GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
- GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
- 0),
- GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
- 1),
- GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
- 2),
- GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
- GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie",
- CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12),
- GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
- GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
+ GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_66M_MCK, 10),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_66M_MCK,
+ 13),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_66M_MCK,
+ 14),
+ GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_CB_RTC_32K, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_400M, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+ CLK_TOP_EMMC_208M, 17),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+ CLK_TOP_SYSAXI, 18),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_TOP_SYSAXI,
+ 19),
+ GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X,
+ 23),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CLK_TOP_SYSAXI,
+ 25),
+ GATE_INFRA1_INFRA(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CLK_INFRA_66M_MCK, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI,
+ 0),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_TOP_SYSAXI,
+ 1),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS,
+ 2),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_REF, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL, 12),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_CB_CKSQ_40M, 13),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI, 15),
};
static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
@@ -526,19 +515,22 @@
};
static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_M_416M,
- .muxes_offs = CK_TOP_NFI1X_SEL,
+ .fdivs_offs = CLK_TOP_CB_M_416M,
+ .muxes_offs = CLK_TOP_NFI1X_SEL,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
};
static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_UART0_SEL,
+ .fdivs_offs = CLK_INFRA_66M_MCK,
+ .muxes_offs = CLK_INFRA_UART0_SEL,
+ .gates_offs = CLK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
+ .gates = infracfg_gates,
+ .flags = CLK_INFRASYS,
};
static const struct udevice_id mt7981_fixed_pll_compat[] = {
@@ -592,20 +584,9 @@
{}
};
-static const struct udevice_id mt7981_infracfg_ao_compat[] = {
- { .compatible = "mediatek,mt7981-infracfg_ao" },
- {}
-};
-
static int mt7981_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
-}
-
-static int mt7981_infracfg_ao_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
- infracfg_ao_gates);
+ return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree);
}
U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -618,16 +599,74 @@
.flags = DM_FLAG_PRE_RELOC,
};
+/* sgmiisys */
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .set_ofs = 0xe4,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe4,
+};
+
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
- .name = "mt7981-clock-infracfg-ao",
+#define GATE_SGMII(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate sgmii0_cgs[] = {
+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM0_CK0_EN, "sgm0_ck0_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5),
+};
+
+static int mt7981_sgmii0sys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+ sgmii0_cgs);
+}
+
+static const struct udevice_id mt7981_sgmii0sys_compat[] = {
+ { .compatible = "mediatek,mt7981-sgmiisys_0", },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmii0sys) = {
+ .name = "mt7981-clock-sgmii0sys",
.id = UCLASS_CLK,
- .of_match = mt7981_infracfg_ao_compat,
- .probe = mt7981_infracfg_ao_probe,
+ .of_match = mt7981_sgmii0sys_compat,
+ .probe = mt7981_sgmii0sys_probe,
.priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct mtk_gate sgmii1_cgs[] = {
+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM1_CK1_EN, "sgm1_ck1_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5),
};
+static int mt7981_sgmii1sys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+ sgmii1_cgs);
+}
+
+static const struct udevice_id mt7981_sgmii1sys_compat[] = {
+ { .compatible = "mediatek,mt7981-sgmiisys_1", },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmii1sys) = {
+ .name = "mt7981-clock-sgmii1sys",
+ .id = UCLASS_CLK,
+ .of_match = mt7981_sgmii1sys_compat,
+ .probe = mt7981_sgmii1sys_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
/* ethsys */
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
@@ -643,10 +682,10 @@
}
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
- GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
- GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X, 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M, 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M, 8),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15),
};
static int mt7981_ethsys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index efc3d41..c5cc772 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -18,6 +18,11 @@
#define MT7986_CLK_PDN 0x250
#define MT7986_CLK_PDN_EN_WRITE BIT(31)
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
+
#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -29,177 +34,195 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk fixed_pll_clks[] = {
- FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
- PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
- 10),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
+ /* TOP Factors */
+ TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL,
1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
- 1),
+ /* Not defined upstream and not used */
+ /* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */
+ /* MPLL */
+ PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ /* MMPLL */
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30),
+ /* APLL2 */
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ /* NET1PLL */
+ PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ /* NET2PLL */
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ /* WEDMCUPLL */
+ PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1,
+ 10),
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
- CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
- CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int spinfi_parents[] = {
- CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
- CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
+static const struct mtk_parent spinfi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8),
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
- CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
+};
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+};
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
- CK_TOP_CB_RTC_32K };
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
+static const struct mtk_parent emmc_416m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL),
+};
-static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const struct mtk_parent f_26m_adc_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+};
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D4 };
+static const struct mtk_parent sysaxi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4),
+};
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
- CK_TOP_NET2_D4_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4_D2),
+};
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET2_D3_D2 };
+static const struct mtk_parent arm_db_main_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
+};
-static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
+static const struct mtk_parent arm_db_jtsel_parents[] = {
+ VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL),
+};
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
+};
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_WEDMCU_760M,
- CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_mcu_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
+ TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_WEDMCU_760M,
- CK_TOP_CB_MM_D2 };
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_325m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+};
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent sgm_reg_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+};
-static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D2 };
+static const struct mtk_parent conn_mcusys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
+static const struct mtk_parent eip_b_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+};
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent a_tuner_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const struct mtk_parent u2u3_sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+};
-static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_U2_PHYD_CK };
+static const struct mtk_parent da_u2_refsel_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD),
+};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -208,199 +231,167 @@
.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
.upd_shift = _upd, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
- .gate_shift = _gate, .parent = _parents, \
+ .gate_shift = _gate, .parent_flags = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
0x008, 0, 3, 7, 0x1C0, 0),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
0x008, 8, 3, 15, 0x1C0, 1),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
3, 23, 0x1C0, 2),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
0x008, 24, 3, 31, 0x1C0, 3),
/* CLK_CFG_1 */
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
0, 2, 7, 0x1C0, 4),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
2, 15, 0x1C0, 5),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
2, 23, 0x1C0, 6),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
/* CLK_CFG_2 */
- TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
0x024, 0x028, 0, 1, 7, 0x1C0, 8),
- TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
+ TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
0x024, 0x028, 8, 1, 15, 0x1C0, 9),
- TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
+ TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
0x024, 0x028, 16, 1, 23, 0x1C0, 10),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
0x028, 24, 1, 31, 0x1C0, 11),
/* CLK_CFG_3 */
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
0x038, 8, 2, 15, 0x1C0, 13),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
0x038, 16, 2, 23, 0x1C0, 14),
- TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
/* CLK_CFG_4 */
- TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
0x048, 8, 1, 15, 0x1C0, 17),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
/* CLK_CFG_5 */
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
0x054, 0x058, 0, 2, 7, 0x1C0, 20),
- TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
+ TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
0x054, 0x058, 8, 1, 15, 0x1C0, 21),
- TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
+ TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
0x054, 0x058, 16, 1, 23, 0x1C0, 22),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
- TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
+ TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
- TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
+ TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
0x068, 8, 1, 15, 0x1C0, 25),
- TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
+ TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
0x064, 0x068, 16, 1, 23, 0x1C0, 26),
- TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
+ TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
0x064, 0x068, 24, 1, 31, 0x1C0, 27),
/* CLK_CFG_7 */
- TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
+ TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
0x074, 0x078, 0, 1, 7, 0x1C0, 28),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
0x078, 8, 2, 15, 0x1C0, 29),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
0x074, 0x078, 16, 2, 23, 0x1C0, 30),
- TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
+ TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
0x078, 24, 1, 31, 0x1C4, 0),
/* CLK_CFG_8 */
- TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
+ TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
0x084, 0x088, 0, 1, 7, 0x1C4, 1),
- TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
+ TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
0x084, 0x088, 8, 1, 15, 0x1C4, 2),
- TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
+ TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
- TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
+ TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
/* CLK_CFG_9 */
- TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
+ TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
};
/* INFRA FIXED DIV */
static const struct mtk_fixed_factor infra_fixed_divs[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
- TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
- INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
- 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
- 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
- CK_TOP_PEXTP_TL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2),
};
/* INFRASYS MUX PARENTS */
-static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
-static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
-static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
+static const struct mtk_parent infra_uart0_parents[] = {
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_UART_SEL)
+};
+
+static const struct mtk_parent infra_spi0_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPI_SEL)
+};
-static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
- CK_INFRA_CK_F26M,
- CK_INFRA_66M_MCK, CK_INFRA_PWM };
+static const struct mtk_parent infra_spi1_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPINFI_SEL)
+};
-static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
- -1, CK_INFRA_PCIE_CK };
+static const struct mtk_parent infra_pwm_bsel_parents[] = {
+ TOP_PARENT(CLK_TOP_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ INFRA_PARENT(CLK_INFRA_SYSAXI_D2),
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
+
+static const struct mtk_parent infra_pcie_parents[] = {
+ TOP_PARENT(CLK_TOP_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
+};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
{ \
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
- .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* INFRA MUX */
static const struct mtk_composite infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
- INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
0x10, 0, 1),
- INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
0x10, 1, 1),
- INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
0x10, 2, 1),
- INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
4, 1),
- INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
5, 1),
- INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
0x10, 9, 2),
- INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
0x10, 11, 2),
- INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
0x10, 13, 2),
/* MODULE_CLK_SEL_1 */
- INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+ INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
0, 2),
};
@@ -422,113 +413,131 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
/* INFRA GATE */
-static const struct mtk_gate infracfg_ao_gates[] = {
+static const struct mtk_gate infracfg_gates[] = {
/* INFRA0 */
- GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
- GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
- GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
- GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
- GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
- GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
- GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
- GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
- GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
- GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
- GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
- 11),
- GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
- 13),
- GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
- 14),
- GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
- GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
- GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
- GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
- GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
+ GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+ GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6),
+ GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL,
+ 11),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL,
+ 13),
+ GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
+ 14),
+ GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15),
+ GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16),
+ GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24),
+ GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
/* INFRA1 */
- GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
- GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
- GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
- GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
- GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
- GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
- GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
- 9),
- GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
- GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
- GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
- GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
- 13),
- GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
- 14),
- GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
- GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
- GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
- CK_INFRA_FMSDC_HCK_CK, 17),
- GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
- CK_INFRA_PERI_133M, 18),
- GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
- 19),
- GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
- GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
- GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
- 23),
+ GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+ GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8),
+ GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL,
+ 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2,
+ 13),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2,
+ 14),
+ GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+ CLK_TOP_EMMC_250M_SEL, 17),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+ CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2,
+ 19),
+ GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL,
+ 23),
/* INFRA2 */
- GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
- 0),
- GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
- 1),
- GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
- 2),
- GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
- GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
- GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
- GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL,
+ 0),
+ GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2,
+ 1),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL,
+ 2),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15),
+ /* upstream linux unordered */
+ GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26),
};
static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
.fdivs_offs = CLK_APMIXED_NR_CLK,
.xtal_rate = 40 * MHZ,
.fclks = fixed_pll_clks,
+ .flags = CLK_APMIXED,
};
static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_M_416M,
- .muxes_offs = CK_TOP_NFI1X_SEL,
+ .fdivs_offs = CLK_TOP_XTAL_D2,
+ .muxes_offs = CLK_TOP_NFI1X_SEL,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
};
static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_UART0_SEL,
+ .fdivs_offs = CLK_INFRA_SYSAXI_D2,
+ .muxes_offs = CLK_INFRA_UART0_SEL,
+ .gates_offs = CLK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
+ .gates = infracfg_gates,
+ .flags = CLK_INFRASYS,
};
static const struct udevice_id mt7986_fixed_pll_compat[] = {
@@ -582,22 +591,11 @@
{}
};
-static const struct udevice_id mt7986_infracfg_ao_compat[] = {
- { .compatible = "mediatek,mt7986-infracfg_ao" },
- {}
-};
-
static int mt7986_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
+ return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree);
}
-static int mt7986_infracfg_ao_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
- infracfg_ao_gates);
-}
-
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7986-clock-infracfg",
.id = UCLASS_CLK,
@@ -608,16 +606,6 @@
.flags = DM_FLAG_PRE_RELOC,
};
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
- .name = "mt7986-clock-infracfg-ao",
- .id = UCLASS_CLK,
- .of_match = mt7986_infracfg_ao_compat,
- .probe = mt7986_infracfg_ao_probe,
- .priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-
/* ethsys */
static const struct mtk_gate_regs eth_cg_regs = {
.sta_ofs = 0x30,
@@ -631,11 +619,11 @@
}
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
- GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
- GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8),
+ GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7986_ethsys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 32b0451..8f4e8f4 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -35,225 +35,243 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
- FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
- FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
- FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
- FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+ FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
+ FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
+ FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
+ FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
};
+/* TOPCKGEN FIXED CLK */
+static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
+};
+
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
- XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
- PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
- 128),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
- CK_APMIXED_NETSYSPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
- 1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2),
+ TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
- CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
- 1, 1),
- TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
+ PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1,
+ 128),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8),
};
/* TOPCKGEN MUX PARENTS */
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2 };
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL),
+};
-static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const struct mtk_parent netsys_gsw_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_mcu_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
+static const struct mtk_parent eth_gmii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
};
-static const int eip197_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
+static const struct mtk_parent netsys_mcu_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL),
};
-static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D2 };
+static const struct mtk_parent eip197_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL),
+ APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent axi_infra_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+};
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
- CK_TOP_CB_MM_D4 };
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int emmc_400m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
- CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4),
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent emmc_400m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+ TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+};
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const struct mtk_parent spinfi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const struct mtk_parent pcie_mbist_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D3_D5 };
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const struct mtk_parent usb_frmcnt_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5),
+};
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
+static const struct mtk_parent aud_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+};
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+};
+
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const struct mtk_parent sspxtp_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent usxgmii_sbus_0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+};
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
+};
-static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET2_D4_D4 };
+static const struct mtk_parent eth_refck_50m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4),
+};
-static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D4 };
+static const struct mtk_parent eth_sys_200m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4),
+};
-static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
- CK_TOP_NET1_D8_D16 };
+static const struct mtk_parent eth_xgmii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D16),
+};
-static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_NET2_D2 };
+static const struct mtk_parent bus_tops_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET2PLL_D2),
+};
-static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M };
+static const struct mtk_parent npu_tops_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+};
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
+};
-static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D8 };
+static const struct mtk_parent da_xtp_glb_p0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8),
+};
-static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D4 };
+static const struct mtk_parent mcusys_backup_625m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+};
-static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
- CK_TOP_CB_NET1_D8 };
+static const struct mtk_parent macsec_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8),
+};
-static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D2 };
+static const struct mtk_parent netsys_tops_400m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
+};
-static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
+static const struct mtk_parent eth_mii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8),
+};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -262,278 +280,204 @@
.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
.upd_shift = _upd, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
- .gate_shift = _gate, .parent = _parents, \
+ .gate_shift = _gate, .parent_flags = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite topckgen_mtk_muxes[] = {
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
0, 2, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
0x4, 0x8, 16, 2, 23, 0x1c0, 2),
- TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
+ TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
+ TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
0x14, 0x18, 0, 1, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
- TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
- TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
+ TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
0x18, 24, 3, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
+ TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
0x24, 0x28, 0, 1, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
0x24, 0x28, 16, 2, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 24, 3, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
0x38, 8, 3, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
16, 3, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
0x38, 24, 3, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
7, 0x1c0, 16),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
15, 0x1c0, 17),
- TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+ TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
18),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
0x58, 24, 1, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 8, 1, 15, 0x1c0, 25),
- TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+ TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
+ TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
15, 0x1c0, 29),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
24, 2, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
0x88, 0, 1, 7, 0x1c4, 1),
- TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
0x88, 8, 1, 15, 0x1c4, 2),
- TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
0x88, 16, 1, 23, 0x1c4, 3),
- TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
- TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
- TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
8, 1, 15, 0x1c4, 6),
- TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
- TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
24, 1, 31, 0x1c4, 8),
- TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
- TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
- TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
0xa8, 24, 1, 31, 0x1c4, 12),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
0xb8, 0, 1, 7, 0x1c4, 13),
- TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+ TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
- TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+ TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
- TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+ TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
- TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
+ TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
- TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
- TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
24, 1, 31, 0x1c4, 20),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
- TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
- TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 16, 1, 23, 0x1c4, 23),
- TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 24, 1, 31, 0x1c4, 24),
- TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 0, 1, 7, 0x1c4, 25),
- TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 8, 1, 15, 0x1c4, 26),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
- TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
+ TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
1, 23, 0x1c8, 0),
- TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents,
0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
- TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
+ TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
0x108, 0, 1, 7, 0x1c8, 2),
- TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
- TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
+ TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
0x1c8, 4),
- TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
5),
- TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
+ TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
0x118, 0, 2, 7, 0x1c8, 6),
- TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
7),
- TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
8),
- TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
+ TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
- TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
+ TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
0x124, 0x128, 0, 1, 7, 0x1c8, 10),
- TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
+ TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel",
netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
-/* INFRA FIXED DIV */
-static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
- CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
- CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
- CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
- CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
- TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
- INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
- 1, 1),
- TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
- CK_TOP_EMMC_250M, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
- CK_TOP_USB_FRMCNT, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
- CK_TOP_USB_FRMCNT_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
- CK_TOP_USB_XHCI_P1, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
- CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
- CK_TOP_USB_SYS_P1, 1, 1),
-};
-
/* INFRASYS MUX PARENTS */
-static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O0 };
+static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O1 };
+static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O2 };
+static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
+static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL };
-static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
+static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL };
-static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
- CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
- CK_INFRA_PWM_O };
+static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL,
+ CLK_TOP_PWM_SEL };
static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P0
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P1
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P1_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P2
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P2_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P3
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P3_SEL
};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
@@ -542,51 +486,51 @@
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}
/* INFRA MUX */
static const struct mtk_composite infracfg_mtk_mux[] = {
- INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x10, 0, 1),
- INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x10, 1, 1),
- INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x10, 2, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x10, 4, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x10, 5, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x10, 6, 1),
- INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
+ INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
0x10, 14, 2),
- INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x10, 16, 2),
- INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x10, 18, 2),
- INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x10, 20, 2),
- INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x10, 22, 2),
- INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x10, 24, 2),
- INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x10, 26, 2),
- INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x10, 28, 2),
- INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x10, 30, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
"infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
"infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
"infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
"infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
};
@@ -615,218 +559,238 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA3(_id, _name, _parent, _shift) \
+#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
- GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
- CK_INFRA_66M_MCK, 0),
- GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
- CK_INFRA_66M_MCK, 1),
- GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
- CK_INFRA_PWM_SEL, 2),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
- CK_INFRA_PWM_CK1_SEL, 3),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
- CK_INFRA_PWM_CK2_SEL, 4),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
- CK_INFRA_PWM_CK3_SEL, 5),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
- CK_INFRA_PWM_CK4_SEL, 6),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
- CK_INFRA_PWM_CK5_SEL, 7),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
- CK_INFRA_PWM_CK6_SEL, 8),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
- CK_INFRA_PWM_CK7_SEL, 9),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
- CK_INFRA_PWM_CK8_SEL, 10),
- GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
- CK_INFRA_133M_MCK, 12),
- GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
- CK_INFRA_66M_PHCK, 13),
- GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
- GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
- GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
- 16),
- GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
- 18),
- GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
- 19),
- GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
- CK_INFRA_133M_MCK, 20),
- GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
- CK_INFRA_66M_MCK, 21),
- GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
- CK_INFRA_66M_MCK, 29),
- GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
- CK_INFRA_CK_F26M, 30),
- GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
- 31),
- GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
- CK_INFRA_CK_F26M, 0),
- GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
- GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_INFRA_66M_MCK, 3),
- GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_INFRA_66M_MCK, 4),
- GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_INFRA_66M_MCK, 5),
- GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
- CK_INFRA_MUX_UART0_SEL, 3),
- GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
- CK_INFRA_MUX_UART1_SEL, 4),
- GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
- CK_INFRA_MUX_UART2_SEL, 5),
- GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
- GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
- GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
- CK_INFRA_66M_MCK, 11),
- GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
- CK_INFRA_MUX_SPI0_SEL, 12),
- GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
- CK_INFRA_MUX_SPI1_SEL, 13),
- GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
- CK_INFRA_MUX_SPI2_SEL, 14),
- GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
- CK_INFRA_66M_MCK, 15),
- GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
- CK_INFRA_66M_MCK, 16),
- GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
- CK_INFRA_66M_MCK, 17),
- GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
- CK_INFRA_66M_MCK, 18),
- GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
- GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
- CK_INFRA_F26M_O1, 20),
- GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
- 21),
- GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
- 22),
- GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
- CK_INFRA_FMSDC2_HCK_OCC, 23),
- GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
- CK_INFRA_PERI_133M, 24),
- GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
- CK_INFRA_66M_PHCK, 25),
- GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
- CK_INFRA_133M_MCK, 26),
- GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
- 27),
- GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
- CK_INFRA_133M_MCK, 29),
- GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
- CK_INFRA_66M_PHCK, 31),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
- CK_INFRA_133M_PHCK, 0),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
- CK_INFRA_133M_PHCK, 1),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
- CK_INFRA_66M_PHCK, 2),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
- CK_INFRA_66M_PHCK, 3),
- GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
- GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
- CK_INFRA_USB_SYS_O_P1, 5),
- GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
- GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
- 7),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
- CK_INFRA_USB_FRMCNT_O, 8),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
- CK_INFRA_USB_FRMCNT_O_P1, 9),
- GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
- 10),
- GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
- CK_INFRA_USB_PIPE_O_P1, 11),
- GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
- 12),
- GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
- CK_INFRA_USB_UTMI_O_P1, 13),
- GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
- 14),
- GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
- CK_INFRA_USB_XHCI_O_P1, 15),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
- CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
- CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
- CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
- CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
- CK_INFRA_PCIE_PIPE_OCC_P0, 24),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
- CK_INFRA_PCIE_PIPE_OCC_P1, 25),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
- CK_INFRA_PCIE_PIPE_OCC_P2, 26),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
- CK_INFRA_PCIE_PIPE_OCC_P3, 27),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
- CK_INFRA_133M_PHCK, 28),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
- CK_INFRA_133M_PHCK, 29),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
- CK_INFRA_133M_PHCK, 30),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
- CK_INFRA_133M_PHCK, 31),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8),
+ GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+ CLK_INFRA_PWM_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+ CLK_INFRA_PWM_CK1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+ CLK_INFRA_PWM_CK2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+ CLK_INFRA_PWM_CK3_SEL, 5),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+ CLK_INFRA_PWM_CK4_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+ CLK_INFRA_PWM_CK5_SEL, 7),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+ CLK_INFRA_PWM_CK6_SEL, 8),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+ CLK_INFRA_PWM_CK7_SEL, 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+ CLK_INFRA_PWM_CK8_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+ CLK_TOP_SYSAXI_SEL, 12),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+ CLK_TOP_SYSAXI_SEL, 13),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL,
+ 16),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL,
+ 18),
+ GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL,
+ 19),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+ CLK_TOP_SYSAXI_SEL, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+ CLK_TOP_SYSAXI_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+ CLK_TOP_INFRA_F26M_SEL, 30),
+ /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL,
+ 31), */
+ GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+ CLK_TOP_INFRA_F26M_SEL, 0),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1),
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CLK_TOP_SYSAXI_SEL, 3), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CLK_TOP_SYSAXI_SEL, 4), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CLK_TOP_SYSAXI_SEL, 5), */
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+ CLK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+ CLK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+ CLK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9),
+ GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+ CLK_TOP_SYSAXI_SEL, 11),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CLK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CLK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+ CLK_INFRA_MUX_SPI2_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+ CLK_TOP_SYSAXI_SEL, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+ CLK_TOP_SYSAXI_SEL, 16),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+ CLK_TOP_SYSAXI_SEL, 17),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+ CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19),
+ GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CLK_TOP_INFRA_F26M_SEL, 20),
+ GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK,
+ 21),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL,
+ 22),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CLK_TOP_EMMC_250M_SEL, 23),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 24),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 25),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+ CLK_TOP_SYSAXI_SEL, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL,
+ 27),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 2),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+ CLK_TOP_USB_SYS_P1_SEL, 5),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
+ 7),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+ CLK_TOP_USB_FRMCNT_SEL, 8),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+ CLK_TOP_USB_FRMCNT_P1_SEL, 9),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
+ 10),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+ CLK_XTAL, 11),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
+ 12),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+ CLK_XTAL, 13),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL,
+ 14),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+ CLK_TOP_USB_XHCI_P1_SEL, 15),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+ CLK_XTAL, 24),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+ CLK_XTAL, 25),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+ CLK_XTAL, 26),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+ CLK_XTAL, 27),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+ CLK_TOP_SYSAXI_SEL, 28),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+ CLK_TOP_SYSAXI_SEL, 30),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+ CLK_TOP_SYSAXI_SEL, 31),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
+ .flags = CLK_APMIXED,
.xtal_rate = 40 * MHZ,
};
static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_CKSQ_40M,
- .muxes_offs = CK_TOP_NETSYS_SEL,
+ .fdivs_offs = CLK_TOP_XTAL_D2,
+ .muxes_offs = CLK_TOP_NETSYS_SEL,
+ .fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.xtal_rate = 40 * MHZ,
};
static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_MUX_UART0_SEL,
- .fdivs = infracfg_mtk_fixed_factor,
+ .muxes_offs = CLK_INFRA_MUX_UART0_SEL,
+ .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
+ .gates = infracfg_mtk_gates,
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
};
@@ -884,22 +848,11 @@
{}
};
-static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
- { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
- {}
-};
-
static int mt7988_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
+ return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree);
}
-static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
- infracfg_mtk_gates);
-}
-
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7988-clock-infracfg",
.id = UCLASS_CLK,
@@ -910,16 +863,6 @@
.flags = DM_FLAG_PRE_RELOC,
};
-U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
- .name = "mt7988-clock-infracfg_ao_cgs",
- .id = UCLASS_CLK,
- .of_match = mt7988_infracfg_ao_cgs_compat,
- .probe = mt7988_infracfg_ao_cgs_probe,
- .priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-
/* ETHDMA */
static const struct mtk_gate_regs ethdma_cg_regs = {
@@ -936,7 +879,7 @@
}
static const struct mtk_gate ethdma_mtk_gate[] = {
- GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
};
static int mt7988_ethdma_probe(struct udevice *dev)
@@ -991,10 +934,10 @@
}
static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_0_probe(struct udevice *dev)
@@ -1035,10 +978,10 @@
}
static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_1_probe(struct udevice *dev)
@@ -1079,12 +1022,12 @@
}
static const struct mtk_gate ethwarp_mtk_gate[] = {
- GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
- CK_TOP_NETSYS_WED_MCU, 13),
- GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
- CK_TOP_NETSYS_WED_MCU, 14),
- GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
- CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
+ CLK_TOP_NETSYS_MCU_SEL, 13),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
+ CLK_TOP_NETSYS_MCU_SEL, 14),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
+ CLK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7988_ethwarp_probe(struct udevice *dev)
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index a29ad0d..a43fff2 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -358,7 +358,7 @@
gd->mem_clk = priv->speed[MPC83XX_CLK_MEM];
if (mpc83xx_has_pci(type))
- gd->pci_clk = priv->speed[MPC83XX_CLK_PCI];
+ gd->arch.pci_clk = priv->speed[MPC83XX_CLK_PCI];
gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE];
gd->bus_clk = priv->speed[MPC83XX_CLK_CSB];
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 45d63c6..0d2c0ac 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -86,6 +86,14 @@
on the Snapdragon SM8650 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SC7280
+ bool "Qualcomm SC7280 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SC7280 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index dec20e4..e223c13 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o
obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index f6445c8..7aa6ca5 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -11,6 +11,7 @@
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
#define CFG_CLK_SRC_GPLL9 (2 << 8)
+#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
#define CFG_CLK_SRC_GPLL6 (4 << 8)
#define CFG_CLK_SRC_GPLL7 (3 << 8)
#define CFG_CLK_SRC_GPLL4 (5 << 8)
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
new file mode 100644
index 0000000..5d343f1
--- /dev/null
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm sc7280
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+
+#include "clock-qcom.h"
+
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+
+static ulong sc7280_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id < priv->data->num_clks)
+ debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
+
+ switch (clk->id) {
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
+ clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+ return rate;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+ 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
+ clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
+ return rate;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk sc7280_clks[] = {
+ GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1),
+ GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
+ GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
+ GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+};
+
+static int sc7280_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (priv->data->num_clks < clk->id) {
+ debug("%s: unknown clk id %lu\n", __func__, clk->id);
+ return 0;
+ }
+
+ debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name);
+
+ switch (clk->id) {
+ case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+ fallthrough;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+ break;
+ }
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map sc7280_gcc_resets[] = {
+ [GCC_PCIE_0_BCR] = { 0x6b000 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+ [GCC_PCIE_1_BCR] = { 0x8d000 },
+ [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_SDCC1_BCR] = { 0x75000 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+ [GCC_SDCC4_BCR] = { 0x16000 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB30_SEC_BCR] = { 0x9e000 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct qcom_power_map sc7280_gdscs[] = {
+ [GCC_UFS_PHY_GDSC] = { 0x77004 },
+ [GCC_USB30_PRIM_GDSC] = { 0xf004 },
+};
+
+static struct msm_clk_data qcs404_gcc_data = {
+ .resets = sc7280_gcc_resets,
+ .num_resets = ARRAY_SIZE(sc7280_gcc_resets),
+ .clks = sc7280_clks,
+ .num_clks = ARRAY_SIZE(sc7280_clks),
+
+ .power_domains = sc7280_gdscs,
+ .num_power_domains = ARRAY_SIZE(sc7280_gdscs),
+
+ .enable = sc7280_enable,
+ .set_rate = sc7280_set_rate,
+};
+
+static const struct udevice_id gcc_sc7280_of_match[] = {
+ {
+ .compatible = "qcom,gcc-sc7280",
+ .data = (ulong)&qcs404_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_sc7280) = {
+ .name = "gcc_sc7280",
+ .id = UCLASS_NOP,
+ .of_match = gcc_sc7280_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 24cefeb..8992404 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
+#include <handoff.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
@@ -1467,7 +1468,7 @@
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
- if (!(gd->spl_handoff))
+ if (!handoff_get())
init_clocks = true;
}
#endif
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index ceb2c6f..e55a26a 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -58,7 +58,7 @@
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu540[] = {
+static struct __prci_clock __prci_init_clocks_fu540[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -83,3 +83,8 @@
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
+
+const struct prci_clk_desc prci_clk_fu540 = {
+ .clks = __prci_init_clocks_fu540,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
+};
diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h
deleted file mode 100644
index 1133011..0000000
--- a/drivers/clk/sifive/fu540-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU540_PRCI_H
-#define __SIFIVE_CLK_FU540_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU540 4
-
-extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
-
-static const struct prci_clk_desc prci_clk_fu540 = {
- .clks = __prci_init_clocks_fu540,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
-};
-
-#endif /* __SIFIVE_CLK_FU540_PRCI_H */
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index 5edc864..4274b21 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -102,7 +102,7 @@
};
/* List of clock controls provided by the PRCI */
-struct __prci_clock __prci_init_clocks_fu740[] = {
+static struct __prci_clock __prci_init_clocks_fu740[] = {
[FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -156,3 +156,8 @@
.pwd = &__prci_pcieaux_data,
}
};
+
+const struct prci_clk_desc prci_clk_fu740 = {
+ .clks = __prci_init_clocks_fu740,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
+};
diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h
deleted file mode 100644
index b74f078..0000000
--- a/drivers/clk/sifive/fu740-prci.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- * Zong Li
- * Pragnesh Patel
- */
-
-#ifndef __SIFIVE_CLK_FU740_PRCI_H
-#define __SIFIVE_CLK_FU740_PRCI_H
-
-#include "sifive-prci.h"
-
-#define NUM_CLOCK_FU740 9
-
-extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
-
-static const struct prci_clk_desc prci_clk_fu740 = {
- .clks = __prci_init_clocks_fu740,
- .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
-};
-
-#endif /* __SIFIVE_CLK_FU740_PRCI_H */
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 5ea8606..aa26d3a 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -33,8 +33,7 @@
#include <linux/math64.h>
#include <dt-bindings/clock/sifive-fu740-prci.h>
-#include "fu540-prci.h"
-#include "fu740-prci.h"
+#include "sifive-prci.h"
/*
* Private functions
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 5ce33d6..b391698 100644
--- a/drivers/clk/sifive/sifive-prci.h
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -320,4 +320,8 @@
int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable);
+/* Clock driver data */
+extern const struct prci_clk_desc prci_clk_fu540;
+extern const struct prci_clk_desc prci_clk_fu740;
+
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
diff --git a/drivers/clk/sophgo/Kconfig b/drivers/clk/sophgo/Kconfig
new file mode 100644
index 0000000..59b5160
--- /dev/null
+++ b/drivers/clk/sophgo/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+config CLK_SOPHGO
+ bool
+
+config CLK_SOPHGO_CV1800B
+ bool "Sophgo CV1800B clock support"
+ depends on CLK
+ select CLK_CCF
+ select CLK_SOPHGO
+ help
+ This enables support clock driver for Sophgo CV1800B SoC.
diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile
new file mode 100644
index 0000000..caec762
--- /dev/null
+++ b/drivers/clk/sophgo/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+obj-y += clk-ip.o clk-pll.o
+obj-$(CONFIG_CLK_SOPHGO_CV1800B) += clk-cv1800b.o
diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h
new file mode 100644
index 0000000..95b82e9
--- /dev/null
+++ b/drivers/clk/sophgo/clk-common.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ *
+ */
+
+#ifndef __CLK_SOPHGO_COMMON_H__
+#define __CLK_SOPHGO_COMMON_H__
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#define CV1800B_CLK_OSC 1
+#define CV1800B_CLK_BYPASS 2
+#define CV1800B_CLK_ID_TRANSFORM(_id) ((_id) + 3)
+
+struct cv1800b_clk_regbit {
+ u32 offset;
+ u8 shift;
+};
+
+struct cv1800b_clk_regfield {
+ u32 offset;
+ u8 shift;
+ u8 width;
+};
+
+#define CV1800B_CLK_REGBIT(_offset, _shift) \
+ { \
+ .offset = _offset, \
+ .shift = _shift, \
+ }
+
+#define CV1800B_CLK_REGFIELD(_offset, _shift, _width) \
+ { \
+ .offset = _offset, \
+ .shift = _shift, \
+ .width = _width, \
+ }
+
+static inline u32 cv1800b_clk_getbit(void *base, struct cv1800b_clk_regbit *bit)
+{
+ return readl(base + bit->offset) & (BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit *bit)
+{
+ return setbits_le32(base + bit->offset, BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit *bit)
+{
+ return clrbits_le32(base + bit->offset, BIT(bit->shift));
+}
+
+static inline u32 cv1800b_clk_getfield(void *base,
+ struct cv1800b_clk_regfield *field)
+{
+ u32 mask = GENMASK(field->shift + field->width - 1, field->shift);
+
+ return (readl(base + field->offset) & mask) >> field->shift;
+}
+
+static inline void
+cv1800b_clk_setfield(void *base, struct cv1800b_clk_regfield *field, u32 val)
+{
+ u32 mask = GENMASK(field->shift + field->width - 1, field->shift);
+ u32 new_val = (readl(base + field->offset) & ~mask) |
+ ((val << field->shift) & mask);
+
+ return writel(new_val, base + field->offset);
+}
+
+#endif /* __CLK_SOPHGO_COMMON_H__ */
diff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c
new file mode 100644
index 0000000..d946ea5
--- /dev/null
+++ b/drivers/clk/sophgo/clk-cv1800b.c
@@ -0,0 +1,754 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/clk-provider.h>
+
+#include "clk-common.h"
+#include "clk-cv1800b.h"
+#include "clk-ip.h"
+#include "clk-pll.h"
+
+static const char *const clk_cam_parents[] = {
+ "clk_cam0pll",
+ "clk_cam0pll_d2",
+ "clk_cam0pll_d3",
+ "clk_mipimpll_d3"
+};
+
+static const char *const clk_tpu_parents[] = {
+ "clk_tpll",
+ "clk_a0pll",
+ "clk_mipimpll",
+ "clk_fpll"
+};
+
+static const char *const clk_axi4_parents[] = { "clk_fpll", "clk_disppll" };
+static const char *const clk_aud_parents[] = { "clk_a0pll", "clk_a24m" };
+static const char *const clk_cam0_200_parents[] = { "osc", "clk_disppll" };
+
+static const char *const clk_vip_sys_parents[] = {
+ "clk_mipimpll",
+ "clk_cam0pll",
+ "clk_disppll",
+ "clk_fpll"
+};
+
+static const char *const clk_axi_video_codec_parents[] = {
+ "clk_a0pll",
+ "clk_mipimpll",
+ "clk_cam1pll",
+ "clk_fpll"
+};
+
+static const char *const clk_vc_src0_parents[] = {
+ "clk_disppll",
+ "clk_mipimpll",
+ "clk_cam1pll",
+ "clk_fpll"
+};
+
+static const struct cv1800b_mmux_parent_info clk_c906_0_parents[] = {
+ { "clk_tpll", 0, 0 },
+ { "clk_a0pll", 0, 1 },
+ { "clk_mipimpll", 0, 2 },
+ { "clk_mpll", 0, 3 },
+ { "clk_fpll", 1, 0 },
+};
+
+static const struct cv1800b_mmux_parent_info clk_c906_1_parents[] = {
+ { "clk_tpll", 0, 0 },
+ { "clk_a0pll", 0, 1 },
+ { "clk_disppll", 0, 2 },
+ { "clk_mpll", 0, 3 },
+ { "clk_fpll", 1, 0 },
+};
+
+static const struct cv1800b_mmux_parent_info clk_a53_parents[] = {
+ { "clk_tpll", 0, 0 },
+ { "clk_a0pll", 0, 1 },
+ { "clk_mipimpll", 0, 2 },
+ { "clk_mpll", 0, 3 },
+ { "clk_fpll", 1, 0 },
+};
+
+static struct cv1800b_clk_gate cv1800b_gate_info[] = {
+ CV1800B_GATE(CLK_XTAL_AP, "clk_xtal_ap", "osc", REG_CLK_EN_0, 3, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_RTC_25M, "clk_rtc_25m", "osc", REG_CLK_EN_0, 8, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TEMPSEN, "clk_tempsen", "osc", REG_CLK_EN_0, 9, 0),
+ CV1800B_GATE(CLK_SARADC, "clk_saradc", "osc", REG_CLK_EN_0, 10, 0),
+ CV1800B_GATE(CLK_EFUSE, "clk_efuse", "osc", REG_CLK_EN_0, 11, 0),
+ CV1800B_GATE(CLK_APB_EFUSE, "clk_apb_efuse", "osc", REG_CLK_EN_0, 12, 0),
+ CV1800B_GATE(CLK_DEBUG, "clk_debug", "osc", REG_CLK_EN_0, 13, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_XTAL_MISC, "clk_xtal_misc", "osc", REG_CLK_EN_0, 14, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_APB_WDT, "clk_apb_wdt", "osc", REG_CLK_EN_1, 7, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_WGN, "clk_wgn", "osc", REG_CLK_EN_3, 22, 0),
+ CV1800B_GATE(CLK_WGN0, "clk_wgn0", "osc", REG_CLK_EN_3, 23, 0),
+ CV1800B_GATE(CLK_WGN1, "clk_wgn1", "osc", REG_CLK_EN_3, 24, 0),
+ CV1800B_GATE(CLK_WGN2, "clk_wgn2", "osc", REG_CLK_EN_3, 25, 0),
+ CV1800B_GATE(CLK_KEYSCAN, "clk_keyscan", "osc", REG_CLK_EN_3, 26, 0),
+ CV1800B_GATE(CLK_TPU_FAB, "clk_tpu_fab", "clk_mipimpll", REG_CLK_EN_0, 5, 0),
+ CV1800B_GATE(CLK_AHB_ROM, "clk_ahb_rom", "clk_axi4", REG_CLK_EN_0, 6, 0),
+ CV1800B_GATE(CLK_AXI4_EMMC, "clk_axi4_emmc", "clk_axi4", REG_CLK_EN_0, 15, 0),
+ CV1800B_GATE(CLK_AXI4_SD0, "clk_axi4_sd0", "clk_axi4", REG_CLK_EN_0, 18, 0),
+ CV1800B_GATE(CLK_AXI4_SD1, "clk_axi4_sd1", "clk_axi4", REG_CLK_EN_0, 21, 0),
+ CV1800B_GATE(CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4", REG_CLK_EN_0, 26, 0),
+ CV1800B_GATE(CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4", REG_CLK_EN_0, 28, 0),
+ CV1800B_GATE(CLK_AHB_SF, "clk_ahb_sf", "clk_axi4", REG_CLK_EN_1, 0, 0),
+ CV1800B_GATE(CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi4", REG_CLK_EN_1, 1, 0),
+ CV1800B_GATE(CLK_APB_I2C, "clk_apb_i2c", "clk_axi4", REG_CLK_EN_1, 6, 0),
+ CV1800B_GATE(CLK_APB_SPI0, "clk_apb_spi0", "clk_axi4", REG_CLK_EN_1, 9, 0),
+ CV1800B_GATE(CLK_APB_SPI1, "clk_apb_spi1", "clk_axi4", REG_CLK_EN_1, 10, 0),
+ CV1800B_GATE(CLK_APB_SPI2, "clk_apb_spi2", "clk_axi4", REG_CLK_EN_1, 11, 0),
+ CV1800B_GATE(CLK_APB_SPI3, "clk_apb_spi3", "clk_axi4", REG_CLK_EN_1, 12, 0),
+ CV1800B_GATE(CLK_APB_UART0, "clk_apb_uart0", "clk_axi4", REG_CLK_EN_1, 15, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_APB_UART1, "clk_apb_uart1", "clk_axi4", REG_CLK_EN_1, 17, 0),
+ CV1800B_GATE(CLK_APB_UART2, "clk_apb_uart2", "clk_axi4", REG_CLK_EN_1, 19, 0),
+ CV1800B_GATE(CLK_APB_UART3, "clk_apb_uart3", "clk_axi4", REG_CLK_EN_1, 21, 0),
+ CV1800B_GATE(CLK_APB_UART4, "clk_apb_uart4", "clk_axi4", REG_CLK_EN_1, 23, 0),
+ CV1800B_GATE(CLK_APB_I2S0, "clk_apb_i2s0", "clk_axi4", REG_CLK_EN_1, 24, 0),
+ CV1800B_GATE(CLK_APB_I2S1, "clk_apb_i2s1", "clk_axi4", REG_CLK_EN_1, 25, 0),
+ CV1800B_GATE(CLK_APB_I2S2, "clk_apb_i2s2", "clk_axi4", REG_CLK_EN_1, 26, 0),
+ CV1800B_GATE(CLK_APB_I2S3, "clk_apb_i2s3", "clk_axi4", REG_CLK_EN_1, 27, 0),
+ CV1800B_GATE(CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4", REG_CLK_EN_1, 28, 0),
+ CV1800B_GATE(CLK_APB_USB, "clk_apb_usb", "clk_axi4", REG_CLK_EN_1, 29, 0),
+ CV1800B_GATE(CLK_APB_I2C0, "clk_apb_i2c0", "clk_axi4", REG_CLK_EN_3, 17, 0),
+ CV1800B_GATE(CLK_APB_I2C1, "clk_apb_i2c1", "clk_axi4", REG_CLK_EN_3, 18, 0),
+ CV1800B_GATE(CLK_APB_I2C2, "clk_apb_i2c2", "clk_axi4", REG_CLK_EN_3, 19, 0),
+ CV1800B_GATE(CLK_APB_I2C3, "clk_apb_i2c3", "clk_axi4", REG_CLK_EN_3, 20, 0),
+ CV1800B_GATE(CLK_APB_I2C4, "clk_apb_i2c4", "clk_axi4", REG_CLK_EN_3, 21, 0),
+ CV1800B_GATE(CLK_AHB_SF1, "clk_ahb_sf1", "clk_axi4", REG_CLK_EN_3, 27, 0),
+ CV1800B_GATE(CLK_APB_AUDSRC, "clk_apb_audsrc", "clk_axi4", REG_CLK_EN_4, 2, 0),
+ CV1800B_GATE(CLK_DDR_AXI_REG, "clk_ddr_axi_reg", "clk_axi6", REG_CLK_EN_0, 7,
+ CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_APB_GPIO, "clk_apb_gpio", "clk_axi6", REG_CLK_EN_0, 29, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_axi6", REG_CLK_EN_0, 30,
+ CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6", REG_CLK_EN_2, 13, CLK_IGNORE_UNUSED),
+ CV1800B_GATE(CLK_APB_H264C, "clk_apb_h264c", "clk_axi6", REG_CLK_EN_2, 14, 0),
+ CV1800B_GATE(CLK_APB_H265C, "clk_apb_h265c", "clk_axi6", REG_CLK_EN_2, 15, 0),
+ CV1800B_GATE(CLK_PM, "clk_pm", "clk_axi6", REG_CLK_EN_3, 8, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_CFG_REG_VIP, "clk_cfg_reg_vip", "clk_axi6", REG_CLK_EN_3, 31, 0),
+ CV1800B_GATE(CLK_CFG_REG_VC, "clk_cfg_reg_vc", "clk_axi6", REG_CLK_EN_4, 0,
+ CLK_IGNORE_UNUSED),
+ CV1800B_GATE(CLK_PWM, "clk_pwm", "clk_pwm_src", REG_CLK_EN_1, 8, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_UART0, "clk_uart0", "clk_cam0_200", REG_CLK_EN_1, 14, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_UART1, "clk_uart1", "clk_cam0_200", REG_CLK_EN_1, 16, 0),
+ CV1800B_GATE(CLK_UART2, "clk_uart2", "clk_cam0_200", REG_CLK_EN_1, 18, 0),
+ CV1800B_GATE(CLK_UART3, "clk_uart3", "clk_cam0_200", REG_CLK_EN_1, 20, 0),
+ CV1800B_GATE(CLK_UART4, "clk_uart4", "clk_cam0_200", REG_CLK_EN_1, 22, 0),
+ CV1800B_GATE(CLK_H264C, "clk_h264c", "clk_axi_video_codec", REG_CLK_EN_2, 10, 0),
+ CV1800B_GATE(CLK_H265C, "clk_h265c", "clk_axi_video_codec", REG_CLK_EN_2, 11, 0),
+ CV1800B_GATE(CLK_JPEG, "clk_jpeg", "clk_axi_video_codec", REG_CLK_EN_2, 12,
+ CLK_IGNORE_UNUSED),
+ CV1800B_GATE(CLK_CSI_MAC0_VIP, "clk_csi_mac0_vip", "clk_axi_vip", REG_CLK_EN_2, 18, 0),
+ CV1800B_GATE(CLK_CSI_MAC1_VIP, "clk_csi_mac1_vip", "clk_axi_vip", REG_CLK_EN_2, 19, 0),
+ CV1800B_GATE(CLK_ISP_TOP_VIP, "clk_isp_top_vip", "clk_axi_vip", REG_CLK_EN_2, 20, 0),
+ CV1800B_GATE(CLK_IMG_D_VIP, "clk_img_d_vip", "clk_axi_vip", REG_CLK_EN_2, 21, 0),
+ CV1800B_GATE(CLK_IMG_V_VIP, "clk_img_v_vip", "clk_axi_vip", REG_CLK_EN_2, 22, 0),
+ CV1800B_GATE(CLK_SC_TOP_VIP, "clk_sc_top_vip", "clk_axi_vip", REG_CLK_EN_2, 23, 0),
+ CV1800B_GATE(CLK_SC_D_VIP, "clk_sc_d_vip", "clk_axi_vip", REG_CLK_EN_2, 24, 0),
+ CV1800B_GATE(CLK_SC_V1_VIP, "clk_sc_v1_vip", "clk_axi_vip", REG_CLK_EN_2, 25, 0),
+ CV1800B_GATE(CLK_SC_V2_VIP, "clk_sc_v2_vip", "clk_axi_vip", REG_CLK_EN_2, 26, 0),
+ CV1800B_GATE(CLK_SC_V3_VIP, "clk_sc_v3_vip", "clk_axi_vip", REG_CLK_EN_2, 27, 0),
+ CV1800B_GATE(CLK_DWA_VIP, "clk_dwa_vip", "clk_axi_vip", REG_CLK_EN_2, 28, 0),
+ CV1800B_GATE(CLK_BT_VIP, "clk_bt_vip", "clk_axi_vip", REG_CLK_EN_2, 29, 0),
+ CV1800B_GATE(CLK_DISP_VIP, "clk_disp_vip", "clk_axi_vip", REG_CLK_EN_2, 30, 0),
+ CV1800B_GATE(CLK_DSI_MAC_VIP, "clk_dsi_mac_vip", "clk_axi_vip", REG_CLK_EN_2, 31, 0),
+ CV1800B_GATE(CLK_LVDS0_VIP, "clk_lvds0_vip", "clk_axi_vip", REG_CLK_EN_3, 0, 0),
+ CV1800B_GATE(CLK_LVDS1_VIP, "clk_lvds1_vip", "clk_axi_vip", REG_CLK_EN_3, 1, 0),
+ CV1800B_GATE(CLK_CSI0_RX_VIP, "clk_csi0_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 2, 0),
+ CV1800B_GATE(CLK_CSI1_RX_VIP, "clk_csi1_rx_vip", "clk_axi_vip", REG_CLK_EN_3, 3, 0),
+ CV1800B_GATE(CLK_PAD_VI_VIP, "clk_pad_vi_vip", "clk_axi_vip", REG_CLK_EN_3, 4, 0),
+ CV1800B_GATE(CLK_PAD_VI1_VIP, "clk_pad_vi1_vip", "clk_axi_vip", REG_CLK_EN_3, 30, 0),
+ CV1800B_GATE(CLK_PAD_VI2_VIP, "clk_pad_vi2_vip", "clk_axi_vip", REG_CLK_EN_4, 7, 0),
+ CV1800B_GATE(CLK_CSI_BE_VIP, "clk_csi_be_vip", "clk_axi_vip", REG_CLK_EN_4, 8, 0),
+ CV1800B_GATE(CLK_VIP_IP0, "clk_vip_ip0", "clk_axi_vip", REG_CLK_EN_4, 9, 0),
+ CV1800B_GATE(CLK_VIP_IP1, "clk_vip_ip1", "clk_axi_vip", REG_CLK_EN_4, 10, 0),
+ CV1800B_GATE(CLK_VIP_IP2, "clk_vip_ip2", "clk_axi_vip", REG_CLK_EN_4, 11, 0),
+ CV1800B_GATE(CLK_VIP_IP3, "clk_vip_ip3", "clk_axi_vip", REG_CLK_EN_4, 12, 0),
+ CV1800B_GATE(CLK_IVE_VIP, "clk_ive_vip", "clk_axi_vip", REG_CLK_EN_4, 17, 0),
+ CV1800B_GATE(CLK_RAW_VIP, "clk_raw_vip", "clk_axi_vip", REG_CLK_EN_4, 18, 0),
+ CV1800B_GATE(CLK_OSDC_VIP, "clk_osdc_vip", "clk_axi_vip", REG_CLK_EN_4, 19, 0),
+ CV1800B_GATE(CLK_CSI_MAC2_VIP, "clk_csi_mac2_vip", "clk_axi_vip", REG_CLK_EN_4, 20, 0),
+ CV1800B_GATE(CLK_CAM0_VIP, "clk_cam0_vip", "clk_axi_vip", REG_CLK_EN_4, 21, 0),
+ CV1800B_GATE(CLK_TIMER0, "clk_timer0", "clk_xtal_misc", REG_CLK_EN_3, 9, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER1, "clk_timer1", "clk_xtal_misc", REG_CLK_EN_3, 10, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER2, "clk_timer2", "clk_xtal_misc", REG_CLK_EN_3, 11, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER3, "clk_timer3", "clk_xtal_misc", REG_CLK_EN_3, 12, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER4, "clk_timer4", "clk_xtal_misc", REG_CLK_EN_3, 13, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER5, "clk_timer5", "clk_xtal_misc", REG_CLK_EN_3, 14, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER6, "clk_timer6", "clk_xtal_misc", REG_CLK_EN_3, 15, CLK_IS_CRITICAL),
+ CV1800B_GATE(CLK_TIMER7, "clk_timer7", "clk_xtal_misc", REG_CLK_EN_3, 16, CLK_IS_CRITICAL),
+};
+
+struct cv1800b_clk_div cv1800b_div_info[] = {
+ CV1800B_DIV(CLK_1M, "clk_1m", "osc", REG_CLK_EN_3, 5,
+ REG_DIV_CLK_1M, 16, 6, 25, CLK_IS_CRITICAL),
+ CV1800B_DIV(CLK_EMMC_100K, "clk_emmc_100k", "clk_1m", REG_CLK_EN_0, 17,
+ REG_DIV_CLK_EMMC_100K, 16, 8, 10, 0),
+ CV1800B_DIV(CLK_SD0_100K, "clk_sd0_100k", "clk_1m", REG_CLK_EN_0, 20,
+ REG_DIV_CLK_SD0_100K, 16, 8, 10, 0),
+ CV1800B_DIV(CLK_SD1_100K, "clk_sd1_100k", "clk_1m", REG_CLK_EN_0, 23,
+ REG_DIV_CLK_SD1_100K, 16, 8, 10, 0),
+ CV1800B_DIV(CLK_GPIO_DB, "clk_gpio_db", "clk_1m", REG_CLK_EN_0, 31,
+ REG_DIV_CLK_GPIO_DB, 16, 16, 10, CLK_IS_CRITICAL)
+};
+
+struct cv1800b_clk_bypass_div cv1800b_bypass_div_info[] = {
+ CV1800B_BYPASS_DIV(CLK_AP_DEBUG, "clk_ap_debug", "clk_fpll", REG_CLK_EN_4, 5,
+ REG_DIV_CLK_AP_DEBUG, 16, 4, 5, REG_CLK_BYP_1, 4, CLK_IS_CRITICAL),
+ CV1800B_BYPASS_DIV(CLK_SRC_RTC_SYS_0, "clk_src_rtc_sys_0", "clk_fpll", REG_CLK_EN_4, 6,
+ REG_DIV_CLK_RTCSYS_SRC_0, 16, 4, 5, REG_CLK_BYP_1, 5, CLK_IS_CRITICAL),
+ CV1800B_BYPASS_DIV(CLK_CPU_GIC, "clk_cpu_gic", "clk_fpll", REG_CLK_EN_0, 2,
+ REG_DIV_CLK_CPU_GIC, 16, 4, 5, REG_CLK_BYP_0, 2, CLK_IS_CRITICAL),
+ CV1800B_BYPASS_DIV(CLK_ETH0_500M, "clk_eth0_500m", "clk_fpll", REG_CLK_EN_0, 25,
+ REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 9, 0),
+ CV1800B_BYPASS_DIV(CLK_ETH1_500M, "clk_eth1_500m", "clk_fpll", REG_CLK_EN_0, 27,
+ REG_DIV_CLK_GPIO_DB, 16, 4, 3, REG_CLK_BYP_0, 10, 0),
+ CV1800B_BYPASS_DIV(CLK_AXI6, "clk_axi6", "clk_fpll", REG_CLK_EN_2, 2, REG_DIV_CLK_AXI6, 16,
+ 4, 15, REG_CLK_BYP_0, 20, CLK_IS_CRITICAL),
+ CV1800B_BYPASS_DIV(CLK_SPI, "clk_spi", "clk_fpll", REG_CLK_EN_3, 6, REG_DIV_CLK_SPI, 16, 6,
+ 8, REG_CLK_BYP_0, 30, 0),
+ CV1800B_BYPASS_DIV(CLK_DISP_SRC_VIP, "clk_disp_src_vip", "clk_disppll", REG_CLK_EN_2, 7,
+ REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, REG_CLK_BYP_0, 25, 0),
+ CV1800B_BYPASS_DIV(CLK_CPU_AXI0, "clk_cpu_axi0", "clk_axi4", REG_CLK_EN_0, 1,
+ REG_DIV_CLK_CPU_AXI0, 16, 4, 3, REG_CLK_BYP_0, 1, CLK_IS_CRITICAL),
+ CV1800B_BYPASS_DIV(CLK_DSI_ESC, "clk_dsi_esc", "clk_axi6", REG_CLK_EN_2, 3,
+ REG_DIV_CLK_DSI_ESC, 16, 4, 5, REG_CLK_BYP_0, 21, 0),
+ CV1800B_BYPASS_DIV(CLK_I2C, "clk_i2c", "clk_axi6", REG_CLK_EN_3, 7, REG_DIV_CLK_I2C, 16, 4,
+ 1, REG_CLK_BYP_0, 31, 0),
+};
+
+struct cv1800b_clk_fixed_div cv1800b_fixed_div_info[] = {
+ CV1800B_FIXED_DIV(CLK_CAM0PLL_D2, "clk_cam0pll_d2", "clk_cam0pll",
+ REG_CAM0PLL_CLK_CSR, 1, 2,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+ CV1800B_FIXED_DIV(CLK_CAM0PLL_D3, "clk_cam0pll_d3", "clk_cam0pll",
+ REG_CAM0PLL_CLK_CSR, 2, 3,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+ CV1800B_FIXED_DIV(CLK_MIPIMPLL_D3, "clk_mipimpll_d3", "clk_mipimpll",
+ REG_MIPIMPLL_CLK_CSR, 2, 3,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
+ CV1800B_FIXED_DIV(CLK_USB_33K, "clk_usb_33k", "clk_1m",
+ REG_CLK_EN_1, 31, 3,
+ 0),
+};
+
+struct cv1800b_clk_bypass_fixed_div cv1800b_bypass_fixed_div_info[] = {
+ CV1800B_BYPASS_FIXED_DIV(CLK_USB_125M, "clk_usb_125m", "clk_fpll",
+ REG_CLK_EN_1, 30, 12,
+ REG_CLK_BYP_0, 17,
+ CLK_SET_RATE_PARENT),
+ CV1800B_BYPASS_FIXED_DIV(CLK_USB_12M, "clk_usb_12m", "clk_fpll",
+ REG_CLK_EN_2, 0, 125,
+ REG_CLK_BYP_0, 18,
+ CLK_SET_RATE_PARENT),
+ CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC1, "clk_vc_src1", "clk_fpll",
+ REG_CLK_EN_3, 28, 2,
+ REG_CLK_BYP_1, 0,
+ CLK_SET_RATE_PARENT),
+ CV1800B_BYPASS_FIXED_DIV(CLK_VC_SRC2, "clk_vc_src2", "clk_fpll",
+ REG_CLK_EN_4, 3, 3,
+ REG_CLK_BYP_1, 3,
+ CLK_SET_RATE_PARENT),
+};
+
+struct cv1800b_clk_mux cv1800b_mux_info[] = {
+ CV1800B_MUX(CLK_CAM0, "clk_cam0", clk_cam_parents,
+ REG_CLK_EN_2, 16,
+ REG_CLK_CAM0_SRC_DIV, 16, 6, 0,
+ REG_CLK_CAM0_SRC_DIV, 8, 2,
+ CLK_IGNORE_UNUSED),
+ CV1800B_MUX(CLK_CAM1, "clk_cam1", clk_cam_parents,
+ REG_CLK_EN_2, 17,
+ REG_CLK_CAM1_SRC_DIV, 16, 6, 0,
+ REG_CLK_CAM1_SRC_DIV, 8, 2,
+ CLK_IGNORE_UNUSED),
+};
+
+struct cv1800b_clk_bypass_mux cv1800b_bypass_mux_info[] = {
+ CV1800B_BYPASS_MUX(CLK_TPU, "clk_tpu", clk_tpu_parents,
+ REG_CLK_EN_0, 4,
+ REG_DIV_CLK_TPU, 16, 4, 3,
+ REG_DIV_CLK_TPU, 8, 2,
+ REG_CLK_BYP_0, 3,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_EMMC, "clk_emmc", clk_axi4_parents,
+ REG_CLK_EN_0, 16,
+ REG_DIV_CLK_EMMC, 16, 5, 15,
+ REG_DIV_CLK_EMMC, 8, 2,
+ REG_CLK_BYP_0, 5,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SD0, "clk_sd0", clk_axi4_parents,
+ REG_CLK_EN_0, 19,
+ REG_DIV_CLK_SD0, 16, 5, 15,
+ REG_DIV_CLK_SD0, 8, 2,
+ REG_CLK_BYP_0, 6,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SD1, "clk_sd1", clk_axi4_parents,
+ REG_CLK_EN_0, 22,
+ REG_DIV_CLK_SD1, 16, 5, 15,
+ REG_DIV_CLK_SD1, 8, 2,
+ REG_CLK_BYP_0, 7,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SPI_NAND, "clk_spi_nand", clk_axi4_parents,
+ REG_CLK_EN_0, 24,
+ REG_DIV_CLK_SPI_NAND, 16, 5, 8,
+ REG_DIV_CLK_SPI_NAND, 8, 2,
+ REG_CLK_BYP_0, 8,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_AXI4, "clk_axi4", clk_axi4_parents,
+ REG_CLK_EN_2, 1,
+ REG_DIV_CLK_AXI4, 16, 4, 5,
+ REG_DIV_CLK_AXI4, 8, 2,
+ REG_CLK_BYP_0, 19,
+ CLK_IS_CRITICAL),
+ CV1800B_BYPASS_MUX(CLK_PWM_SRC, "clk_pwm_src", clk_axi4_parents,
+ REG_CLK_EN_4, 4,
+ REG_DIV_CLK_PWM_SRC_0, 16, 6, 10,
+ REG_DIV_CLK_PWM_SRC_0, 8, 2,
+ REG_CLK_BYP_0, 15,
+ CLK_IS_CRITICAL),
+ CV1800B_BYPASS_MUX(CLK_AUDSRC, "clk_audsrc", clk_aud_parents,
+ REG_CLK_EN_4, 1,
+ REG_DIV_CLK_AUDSRC, 16, 8, 18,
+ REG_DIV_CLK_AUDSRC, 8, 2,
+ REG_CLK_BYP_1, 2,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SDMA_AUD0, "clk_sdma_aud0", clk_aud_parents,
+ REG_CLK_EN_1, 2,
+ REG_DIV_CLK_SDMA_AUD0, 16, 8, 18,
+ REG_DIV_CLK_SDMA_AUD0, 8, 2,
+ REG_CLK_BYP_0, 11,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SDMA_AUD1, "clk_sdma_aud1", clk_aud_parents,
+ REG_CLK_EN_1, 3,
+ REG_DIV_CLK_SDMA_AUD1, 16, 8, 18,
+ REG_DIV_CLK_SDMA_AUD1, 8, 2,
+ REG_CLK_BYP_0, 12,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SDMA_AUD2, "clk_sdma_aud2", clk_aud_parents,
+ REG_CLK_EN_1, 3,
+ REG_DIV_CLK_SDMA_AUD2, 16, 8, 18,
+ REG_DIV_CLK_SDMA_AUD2, 8, 2,
+ REG_CLK_BYP_0, 13,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SDMA_AUD3, "clk_sdma_aud3", clk_aud_parents,
+ REG_CLK_EN_1, 3,
+ REG_DIV_CLK_SDMA_AUD3, 16, 8, 18,
+ REG_DIV_CLK_SDMA_AUD3, 8, 2,
+ REG_CLK_BYP_0, 14,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_CAM0_200, "clk_cam0_200", clk_cam0_200_parents,
+ REG_CLK_EN_1, 13,
+ REG_DIV_CLK_CAM0_200, 16, 4, 1,
+ REG_DIV_CLK_CAM0_200, 8, 2,
+ REG_CLK_BYP_0, 16,
+ CLK_IS_CRITICAL),
+ CV1800B_BYPASS_MUX(CLK_AXI_VIP, "clk_axi_vip", clk_vip_sys_parents,
+ REG_CLK_EN_2, 4,
+ REG_DIV_CLK_AXI_VIP, 16, 4, 3,
+ REG_DIV_CLK_AXI_VIP, 8, 2,
+ REG_CLK_BYP_0, 22,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_0, "clk_src_vip_sys_0", clk_vip_sys_parents,
+ REG_CLK_EN_2, 5,
+ REG_DIV_CLK_SRC_VIP_SYS_0, 16, 4, 6,
+ REG_DIV_CLK_SRC_VIP_SYS_0, 8, 2,
+ REG_CLK_BYP_0, 23,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_1, "clk_src_vip_sys_1", clk_vip_sys_parents,
+ REG_CLK_EN_2, 6,
+ REG_DIV_CLK_SRC_VIP_SYS_1, 16, 4, 6,
+ REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2,
+ REG_CLK_BYP_0, 24,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_2, "clk_src_vip_sys_2", clk_vip_sys_parents,
+ REG_CLK_EN_3, 29,
+ REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2,
+ REG_DIV_CLK_SRC_VIP_SYS_2, 8, 2,
+ REG_CLK_BYP_1, 1,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_3, "clk_src_vip_sys_3", clk_vip_sys_parents,
+ REG_CLK_EN_4, 15,
+ REG_DIV_CLK_SRC_VIP_SYS_3, 16, 4, 2,
+ REG_DIV_CLK_SRC_VIP_SYS_3, 8, 2,
+ REG_CLK_BYP_1, 8,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_SRC_VIP_SYS_4, "clk_src_vip_sys_4", clk_vip_sys_parents,
+ REG_CLK_EN_4, 16,
+ REG_DIV_CLK_SRC_VIP_SYS_4, 16, 4, 3,
+ REG_DIV_CLK_SRC_VIP_SYS_4, 8, 2,
+ REG_CLK_BYP_1, 9,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_AXI_VIDEO_CODEC, "clk_axi_video_codec", clk_axi_video_codec_parents,
+ REG_CLK_EN_2, 8,
+ REG_DIV_CLK_AXI_VIDEO_CODEC, 16, 4, 2,
+ REG_DIV_CLK_AXI_VIDEO_CODEC, 8, 2,
+ REG_CLK_BYP_0, 26,
+ 0),
+ CV1800B_BYPASS_MUX(CLK_VC_SRC0, "clk_vc_src0", clk_vc_src0_parents,
+ REG_CLK_EN_2, 9,
+ REG_DIV_CLK_VC_SRC0, 16, 4, 2,
+ REG_DIV_CLK_VC_SRC0, 8, 2,
+ REG_CLK_BYP_0, 27,
+ 0),
+};
+
+struct cv1800b_clk_mmux cv1800b_mmux_info[] = {
+ CV1800B_MMUX(CLK_C906_0, "clk_c906_0", clk_c906_0_parents,
+ REG_CLK_EN_4, 13,
+ REG_DIV_CLK_C906_0_0, 16, 4, 1,
+ REG_DIV_CLK_C906_0_1, 16, 4, 2,
+ REG_DIV_CLK_C906_0_0, 8, 2,
+ REG_DIV_CLK_C906_0_1, 8, 2,
+ REG_CLK_BYP_1, 6,
+ REG_CLK_SEL_0, 23,
+ CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE),
+ CV1800B_MMUX(CLK_C906_1, "clk_c906_1", clk_c906_1_parents,
+ REG_CLK_EN_4, 14,
+ REG_DIV_CLK_C906_1_0, 16, 4, 2,
+ REG_DIV_CLK_C906_1_1, 16, 4, 3,
+ REG_DIV_CLK_C906_1_0, 8, 2,
+ REG_DIV_CLK_C906_1_1, 8, 2,
+ REG_CLK_BYP_1, 7,
+ REG_CLK_SEL_0, 24,
+ CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE),
+ CV1800B_MMUX(CLK_A53, "clk_a53", clk_a53_parents,
+ REG_CLK_EN_0, 0,
+ REG_DIV_CLK_A53_0, 16, 4, 1,
+ REG_DIV_CLK_A53_1, 16, 4, 2,
+ REG_DIV_CLK_A53_0, 8, 2,
+ REG_DIV_CLK_A53_1, 8, 2,
+ REG_CLK_BYP_0, 0,
+ REG_CLK_SEL_0, 0,
+ CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE),
+};
+
+static struct cv1800b_clk_audio cv1800b_audio_info[] = {
+ CV1800B_AUDIO(CLK_A24M, "clk_a24m", "clk_mipimpll",
+ REG_APLL_FRAC_DIV_CTRL, 0,
+ REG_APLL_FRAC_DIV_CTRL, 3,
+ REG_APLL_FRAC_DIV_CTRL, 1,
+ REG_APLL_FRAC_DIV_CTRL, 2,
+ REG_APLL_FRAC_DIV_M, 0, 22,
+ REG_APLL_FRAC_DIV_N, 0, 22,
+ 0),
+};
+
+static struct cv1800b_clk_ipll cv1800b_ipll_info[] = {
+ CV1800B_IPLL(CLK_FPLL, "clk_fpll", "osc", REG_FPLL_CSR,
+ REG_PLL_G6_CTRL, 8,
+ REG_PLL_G6_STATUS, 2,
+ CLK_IS_CRITICAL),
+ CV1800B_IPLL(CLK_MIPIMPLL, "clk_mipimpll", "osc", REG_MIPIMPLL_CSR,
+ REG_PLL_G2_CTRL, 0,
+ REG_PLL_G2_STATUS, 0,
+ CLK_IS_CRITICAL),
+};
+
+static struct cv1800b_clk_fpll cv1800b_fpll_info[] = {
+ CV1800B_FPLL(CLK_MPLL, "clk_mpll", "osc", REG_MPLL_CSR,
+ REG_PLL_G6_CTRL, 0,
+ REG_PLL_G6_STATUS, 0,
+ REG_PLL_G6_SSC_SYN_CTRL, 2,
+ REG_PLL_G6_SSC_SYN_CTRL, 0,
+ REG_MPLL_SSC_SYN_CTRL, REG_MPLL_SSC_SYN_SET,
+ CLK_IS_CRITICAL),
+ CV1800B_FPLL(CLK_TPLL, "clk_tpll", "osc", REG_TPLL_CSR,
+ REG_PLL_G6_CTRL, 4,
+ REG_PLL_G6_STATUS, 1,
+ REG_PLL_G6_SSC_SYN_CTRL, 3,
+ REG_PLL_G6_SSC_SYN_CTRL, 0,
+ REG_TPLL_SSC_SYN_CTRL, REG_TPLL_SSC_SYN_SET,
+ CLK_IS_CRITICAL),
+ CV1800B_FPLL(CLK_A0PLL, "clk_a0pll", "clk_mipimpll", REG_A0PLL_CSR,
+ REG_PLL_G2_CTRL, 4,
+ REG_PLL_G2_STATUS, 1,
+ REG_PLL_G2_SSC_SYN_CTRL, 2,
+ REG_PLL_G2_SSC_SYN_CTRL, 0,
+ REG_A0PLL_SSC_SYN_CTRL, REG_A0PLL_SSC_SYN_SET,
+ CLK_IS_CRITICAL),
+ CV1800B_FPLL(CLK_DISPPLL, "clk_disppll", "clk_mipimpll", REG_DISPPLL_CSR,
+ REG_PLL_G2_CTRL, 8,
+ REG_PLL_G2_STATUS, 2,
+ REG_PLL_G2_SSC_SYN_CTRL, 3,
+ REG_PLL_G2_SSC_SYN_CTRL, 0,
+ REG_DISPPLL_SSC_SYN_CTRL, REG_DISPPLL_SSC_SYN_SET,
+ CLK_IS_CRITICAL),
+ CV1800B_FPLL(CLK_CAM0PLL, "clk_cam0pll", "clk_mipimpll", REG_CAM0PLL_CSR,
+ REG_PLL_G2_CTRL, 12,
+ REG_PLL_G2_STATUS, 3,
+ REG_PLL_G2_SSC_SYN_CTRL, 4,
+ REG_PLL_G2_SSC_SYN_CTRL, 0,
+ REG_CAM0PLL_SSC_SYN_CTRL, REG_CAM0PLL_SSC_SYN_SET,
+ CLK_IGNORE_UNUSED),
+ CV1800B_FPLL(CLK_CAM1PLL, "clk_cam1pll", "clk_mipimpll", REG_CAM1PLL_CSR,
+ REG_PLL_G2_CTRL, 16,
+ REG_PLL_G2_STATUS, 4,
+ REG_PLL_G2_SSC_SYN_CTRL, 5,
+ REG_PLL_G2_SSC_SYN_CTRL, 0,
+ REG_CAM1PLL_SSC_SYN_CTRL, REG_CAM1PLL_SSC_SYN_SET,
+ CLK_IS_CRITICAL),
+};
+
+static int cv1800b_register_clk(struct udevice *dev)
+{
+ struct clk osc;
+ ulong osc_rate;
+ void *base = devfdt_get_addr_ptr(dev);
+ int i, ret;
+
+ ret = clk_get_by_index(dev, 0, &osc);
+ if (ret) {
+ pr_err("Failed to get clock\n");
+ return ret;
+ }
+
+ osc_rate = clk_get_rate(&osc);
+ clk_dm(CV1800B_CLK_OSC, clk_register_fixed_rate(NULL, "osc", osc_rate));
+ clk_dm(CV1800B_CLK_BYPASS, clk_register_fixed_rate(NULL, "bypass", osc_rate));
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_ipll_info); i++) {
+ struct cv1800b_clk_ipll *ipll = &cv1800b_ipll_info[i];
+
+ ipll->base = base;
+ ret = clk_register(&ipll->clk, "cv1800b_clk_ipll", ipll->name,
+ ipll->parent_name);
+ if (ret) {
+ pr_err("Failed to register ipll %s\n", ipll->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_fpll_info); i++) {
+ struct cv1800b_clk_fpll *fpll = &cv1800b_fpll_info[i];
+
+ fpll->ipll.base = base;
+ ret = clk_register(&fpll->ipll.clk, "cv1800b_clk_fpll",
+ fpll->ipll.name, fpll->ipll.parent_name);
+ if (ret) {
+ pr_err("Failed to register fpll %s\n", fpll->ipll.name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_div_info); i++) {
+ struct cv1800b_clk_div *div = &cv1800b_div_info[i];
+
+ div->base = base;
+ ret = clk_register(&div->clk, "cv1800b_clk_div", div->name,
+ div->parent_name);
+ if (ret) {
+ pr_err("Failed to register div %s\n", div->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_fixed_div_info); i++) {
+ struct cv1800b_clk_fixed_div *fixed_div =
+ &cv1800b_fixed_div_info[i];
+
+ fixed_div->base = base;
+ ret = clk_register(&fixed_div->clk, "cv1800b_clk_fixed_div",
+ fixed_div->name, fixed_div->parent_name);
+ if (ret) {
+ pr_err("Failed to register fixed div %s\n",
+ fixed_div->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_fixed_div_info); i++) {
+ struct cv1800b_clk_bypass_fixed_div *bypass_fixed_div =
+ &cv1800b_bypass_fixed_div_info[i];
+
+ bypass_fixed_div->div.base = base;
+ ret = clk_register(&bypass_fixed_div->div.clk,
+ "cv1800b_clk_bypass_fixed_div",
+ bypass_fixed_div->div.name,
+ bypass_fixed_div->div.parent_name);
+ if (ret) {
+ pr_err("Failed to register bypass fixed div %s\n",
+ bypass_fixed_div->div.name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_mux_info); i++) {
+ struct cv1800b_clk_mux *mux = &cv1800b_mux_info[i];
+ int parent;
+
+ mux->base = base;
+ parent = cv1800b_clk_getfield(base, &mux->mux);
+ ret = clk_register(&mux->clk, "cv1800b_clk_mux", mux->name,
+ mux->parent_names[parent]);
+ if (ret) {
+ pr_err("Failed to register mux %s\n", mux->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_mmux_info); i++) {
+ struct cv1800b_clk_mmux *mmux = &cv1800b_mmux_info[i];
+ int clk_sel, parent, idx;
+
+ mmux->base = base;
+ clk_sel = cv1800b_clk_getbit(base, &mmux->clk_sel) ? 0 : 1;
+ parent = cv1800b_clk_getfield(base, &mmux->mux[clk_sel]);
+ for (idx = 0; idx < mmux->num_parents; idx++) {
+ if (clk_sel == mmux->parent_infos[idx].clk_sel &&
+ parent == mmux->parent_infos[idx].index)
+ break;
+ }
+ ret = clk_register(&mmux->clk, "cv1800b_clk_mmux", mmux->name,
+ mmux->parent_infos[idx].name);
+ if (ret) {
+ pr_err("Failed to register mmux %s\n", mmux->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_audio_info); i++) {
+ struct cv1800b_clk_audio *audio = &cv1800b_audio_info[i];
+
+ audio->base = base;
+ ret = clk_register(&audio->clk, "cv1800b_clk_audio",
+ audio->name, audio->parent_name);
+ if (ret) {
+ pr_err("Failed to register audio %s\n", audio->name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_mux_info); i++) {
+ struct cv1800b_clk_bypass_mux *bypass_mux =
+ &cv1800b_bypass_mux_info[i];
+ int parent;
+
+ bypass_mux->mux.base = base;
+ parent = cv1800b_clk_getfield(base, &bypass_mux->mux.mux);
+ ret = clk_register(&bypass_mux->mux.clk,
+ "cv1800b_clk_bypass_mux",
+ bypass_mux->mux.name,
+ bypass_mux->mux.parent_names[parent]);
+ if (ret) {
+ pr_err("Failed to register bypass mux %s\n",
+ bypass_mux->mux.name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_bypass_div_info); i++) {
+ struct cv1800b_clk_bypass_div *bypass_div =
+ &cv1800b_bypass_div_info[i];
+
+ bypass_div->div.base = base;
+ ret = clk_register(&bypass_div->div.clk,
+ "cv1800b_clk_bypass_div",
+ bypass_div->div.name,
+ bypass_div->div.parent_name);
+ if (ret) {
+ pr_err("Failed to register bypass div %s\n",
+ bypass_div->div.name);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cv1800b_gate_info); i++) {
+ struct cv1800b_clk_gate *gate = &cv1800b_gate_info[i];
+
+ gate->base = base;
+ ret = clk_register(&gate->clk, "cv1800b_clk_gate", gate->name,
+ gate->parent_name);
+ if (ret) {
+ pr_err("Failed to register gate %s\n", gate->name);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int cv1800b_clk_probe(struct udevice *dev)
+{
+ return cv1800b_register_clk(dev);
+}
+
+static int cv1800b_clk_enable(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);
+
+ if (err)
+ return err;
+ return clk_enable(c);
+}
+
+static int cv1800b_clk_disable(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);
+
+ if (err)
+ return err;
+ return clk_disable(c);
+}
+
+static ulong cv1800b_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong cv1800b_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int cv1800b_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);
+
+ if (err)
+ return err;
+ err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(parent->id), &p);
+ if (err)
+ return err;
+ return clk_set_parent(c, p);
+}
+
+const struct clk_ops cv1800b_clk_ops = {
+ .enable = cv1800b_clk_enable,
+ .disable = cv1800b_clk_disable,
+ .get_rate = cv1800b_clk_get_rate,
+ .set_rate = cv1800b_clk_set_rate,
+ .set_parent = cv1800b_clk_set_parent,
+};
+
+static const struct udevice_id cv1800b_clk_of_match[] = {
+ { .compatible = "sophgo,cv1800-clk" },
+ { },
+};
+
+U_BOOT_DRIVER(sophgo_clk) = {
+ .name = "cv1800b_clk",
+ .id = UCLASS_CLK,
+ .of_match = cv1800b_clk_of_match,
+ .probe = cv1800b_clk_probe,
+ .ops = &cv1800b_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/sophgo/clk-cv1800b.h b/drivers/clk/sophgo/clk-cv1800b.h
new file mode 100644
index 0000000..1e7107b
--- /dev/null
+++ b/drivers/clk/sophgo/clk-cv1800b.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#ifndef _CLK_SOPHGO_CV1800_H_
+#define _CLK_SOPHGO_CV1800_H_
+
+#include <dt-bindings/clock/sophgo,cv1800.h>
+
+#define CV1800_CLK_MAX (CLK_XTAL_AP + 1)
+#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1)
+
+#define REG_PLL_G2_CTRL 0x800
+#define REG_PLL_G2_STATUS 0x804
+#define REG_MIPIMPLL_CSR 0x808
+#define REG_A0PLL_CSR 0x80C
+#define REG_DISPPLL_CSR 0x810
+#define REG_CAM0PLL_CSR 0x814
+#define REG_CAM1PLL_CSR 0x818
+#define REG_PLL_G2_SSC_SYN_CTRL 0x840
+#define REG_A0PLL_SSC_SYN_CTRL 0x850
+#define REG_A0PLL_SSC_SYN_SET 0x854
+#define REG_A0PLL_SSC_SYN_SPAN 0x858
+#define REG_A0PLL_SSC_SYN_STEP 0x85C
+#define REG_DISPPLL_SSC_SYN_CTRL 0x860
+#define REG_DISPPLL_SSC_SYN_SET 0x864
+#define REG_DISPPLL_SSC_SYN_SPAN 0x868
+#define REG_DISPPLL_SSC_SYN_STEP 0x86C
+#define REG_CAM0PLL_SSC_SYN_CTRL 0x870
+#define REG_CAM0PLL_SSC_SYN_SET 0x874
+#define REG_CAM0PLL_SSC_SYN_SPAN 0x878
+#define REG_CAM0PLL_SSC_SYN_STEP 0x87C
+#define REG_CAM1PLL_SSC_SYN_CTRL 0x880
+#define REG_CAM1PLL_SSC_SYN_SET 0x884
+#define REG_CAM1PLL_SSC_SYN_SPAN 0x888
+#define REG_CAM1PLL_SSC_SYN_STEP 0x88C
+#define REG_APLL_FRAC_DIV_CTRL 0x890
+#define REG_APLL_FRAC_DIV_M 0x894
+#define REG_APLL_FRAC_DIV_N 0x898
+#define REG_MIPIMPLL_CLK_CSR 0x8A0
+#define REG_A0PLL_CLK_CSR 0x8A4
+#define REG_DISPPLL_CLK_CSR 0x8A8
+#define REG_CAM0PLL_CLK_CSR 0x8AC
+#define REG_CAM1PLL_CLK_CSR 0x8B0
+#define REG_CLK_CAM0_SRC_DIV 0x8C0
+#define REG_CLK_CAM1_SRC_DIV 0x8C4
+
+/* top_pll_g6 */
+#define REG_PLL_G6_CTRL 0x900
+#define REG_PLL_G6_STATUS 0x904
+#define REG_MPLL_CSR 0x908
+#define REG_TPLL_CSR 0x90C
+#define REG_FPLL_CSR 0x910
+#define REG_PLL_G6_SSC_SYN_CTRL 0x940
+#define REG_DPLL_SSC_SYN_CTRL 0x950
+#define REG_DPLL_SSC_SYN_SET 0x954
+#define REG_DPLL_SSC_SYN_SPAN 0x958
+#define REG_DPLL_SSC_SYN_STEP 0x95C
+#define REG_MPLL_SSC_SYN_CTRL 0x960
+#define REG_MPLL_SSC_SYN_SET 0x964
+#define REG_MPLL_SSC_SYN_SPAN 0x968
+#define REG_MPLL_SSC_SYN_STEP 0x96C
+#define REG_TPLL_SSC_SYN_CTRL 0x970
+#define REG_TPLL_SSC_SYN_SET 0x974
+#define REG_TPLL_SSC_SYN_SPAN 0x978
+#define REG_TPLL_SSC_SYN_STEP 0x97C
+
+/* clkgen */
+#define REG_CLK_EN_0 0x000
+#define REG_CLK_EN_1 0x004
+#define REG_CLK_EN_2 0x008
+#define REG_CLK_EN_3 0x00C
+#define REG_CLK_EN_4 0x010
+#define REG_CLK_SEL_0 0x020
+#define REG_CLK_BYP_0 0x030
+#define REG_CLK_BYP_1 0x034
+
+#define REG_DIV_CLK_A53_0 0x040
+#define REG_DIV_CLK_A53_1 0x044
+#define REG_DIV_CLK_CPU_AXI0 0x048
+#define REG_DIV_CLK_CPU_GIC 0x050
+#define REG_DIV_CLK_TPU 0x054
+#define REG_DIV_CLK_EMMC 0x064
+#define REG_DIV_CLK_EMMC_100K 0x06C
+#define REG_DIV_CLK_SD0 0x070
+#define REG_DIV_CLK_SD0_100K 0x078
+#define REG_DIV_CLK_SD1 0x07C
+#define REG_DIV_CLK_SD1_100K 0x084
+#define REG_DIV_CLK_SPI_NAND 0x088
+#define REG_DIV_CLK_ETH0_500M 0x08C
+#define REG_DIV_CLK_ETH1_500M 0x090
+#define REG_DIV_CLK_GPIO_DB 0x094
+#define REG_DIV_CLK_SDMA_AUD0 0x098
+#define REG_DIV_CLK_SDMA_AUD1 0x09C
+#define REG_DIV_CLK_SDMA_AUD2 0x0A0
+#define REG_DIV_CLK_SDMA_AUD3 0x0A4
+#define REG_DIV_CLK_CAM0_200 0x0A8
+#define REG_DIV_CLK_AXI4 0x0B8
+#define REG_DIV_CLK_AXI6 0x0BC
+#define REG_DIV_CLK_DSI_ESC 0x0C4
+#define REG_DIV_CLK_AXI_VIP 0x0C8
+#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0
+#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8
+#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0
+#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4
+#define REG_DIV_CLK_VC_SRC0 0x0EC
+#define REG_DIV_CLK_1M 0x0FC
+#define REG_DIV_CLK_SPI 0x100
+#define REG_DIV_CLK_I2C 0x104
+#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110
+#define REG_DIV_CLK_AUDSRC 0x118
+#define REG_DIV_CLK_PWM_SRC_0 0x120
+#define REG_DIV_CLK_AP_DEBUG 0x128
+#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C
+#define REG_DIV_CLK_C906_0_0 0x130
+#define REG_DIV_CLK_C906_0_1 0x134
+#define REG_DIV_CLK_C906_1_0 0x138
+#define REG_DIV_CLK_C906_1_1 0x13C
+#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140
+#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144
+
+#endif /* _CLK_SOPHGO_CV1800_H_ */
diff --git a/drivers/clk/sophgo/clk-ip.c b/drivers/clk/sophgo/clk-ip.c
new file mode 100644
index 0000000..d571fa6
--- /dev/null
+++ b/drivers/clk/sophgo/clk-ip.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dm.h>
+#include <div64.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+
+#include "clk-common.h"
+#include "clk-ip.h"
+
+static int get_parent_index(struct clk *clk, const char *const *parent_name,
+ u8 num_parents)
+{
+ const char *name = clk_hw_get_name(clk);
+ int i;
+
+ for (i = 0; i < num_parents; i++) {
+ if (!strcmp(name, parent_name[i]))
+ return i;
+ }
+
+ return -1;
+}
+
+/* GATE */
+#define to_cv1800b_clk_gate(_clk) \
+ container_of(_clk, struct cv1800b_clk_gate, clk)
+
+static int gate_enable(struct clk *clk)
+{
+ struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk);
+
+ return cv1800b_clk_setbit(gate->base, &gate->gate);
+}
+
+static int gate_disable(struct clk *clk)
+{
+ struct cv1800b_clk_gate *gate = to_cv1800b_clk_gate(clk);
+
+ return cv1800b_clk_clrbit(gate->base, &gate->gate);
+}
+
+static ulong gate_get_rate(struct clk *clk)
+{
+ return clk_get_parent_rate(clk);
+}
+
+const struct clk_ops cv1800b_clk_gate_ops = {
+ .disable = gate_disable,
+ .enable = gate_enable,
+ .get_rate = gate_get_rate,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_gate) = {
+ .name = "cv1800b_clk_gate",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* DIV */
+#define CLK_DIV_EN_FACTOR BIT(3)
+
+#define to_cv1800b_clk_div(_clk) container_of(_clk, struct cv1800b_clk_div, clk)
+
+static int div_enable(struct clk *clk)
+{
+ struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk);
+
+ return cv1800b_clk_setbit(div->base, &div->gate);
+}
+
+static int div_disable(struct clk *clk)
+{
+ struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk);
+
+ return cv1800b_clk_clrbit(div->base, &div->gate);
+}
+
+static ulong div_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk);
+ ulong val;
+
+ if (div->div_init == 0 ||
+ readl(div->base + div->div.offset) & CLK_DIV_EN_FACTOR)
+ val = cv1800b_clk_getfield(div->base, &div->div);
+ else
+ val = div->div_init;
+
+ return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);
+}
+
+static ulong div_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_div *div = to_cv1800b_clk_div(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 val;
+
+ val = DIV_ROUND_UP_ULL(parent_rate, rate);
+ val = min_t(u32, val, clk_div_mask(div->div.width));
+
+ cv1800b_clk_setfield(div->base, &div->div, val);
+ if (div->div_init > 0)
+ setbits_le32(div->base + div->div.offset, CLK_DIV_EN_FACTOR);
+
+ return DIV_ROUND_UP_ULL(parent_rate, val);
+}
+
+const struct clk_ops cv1800b_clk_div_ops = {
+ .disable = div_disable,
+ .enable = div_enable,
+ .get_rate = div_get_rate,
+ .set_rate = div_set_rate,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_div) = {
+ .name = "cv1800b_clk_div",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_div_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#define to_cv1800b_clk_bypass_div(_clk) \
+ container_of(_clk, struct cv1800b_clk_bypass_div, div.clk)
+
+static ulong bypass_div_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk);
+
+ if (cv1800b_clk_getbit(div->div.base, &div->bypass))
+ return 0;
+
+ return div_get_rate(clk);
+}
+
+static ulong bypass_div_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk);
+
+ if (cv1800b_clk_getbit(div->div.base, &div->bypass))
+ return 0;
+
+ return div_set_rate(clk, rate);
+}
+
+static int bypass_div_set_parent(struct clk *clk, struct clk *pclk)
+{
+ struct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk);
+
+ if (pclk->id == CV1800B_CLK_BYPASS) {
+ cv1800b_clk_setbit(div->div.base, &div->bypass);
+ return 0;
+ }
+
+ if (strcmp(clk_hw_get_name(pclk), div->div.parent_name))
+ return -EINVAL;
+
+ cv1800b_clk_clrbit(div->div.base, &div->bypass);
+ return 0;
+}
+
+const struct clk_ops cv1800b_clk_bypass_div_ops = {
+ .disable = div_disable,
+ .enable = div_enable,
+ .get_rate = bypass_div_get_rate,
+ .set_rate = bypass_div_set_rate,
+ .set_parent = bypass_div_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_bypass_div) = {
+ .name = "cv1800b_clk_bypass_div",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_bypass_div_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* FIXED DIV */
+#define to_cv1800b_clk_fixed_div(_clk) \
+ container_of(_clk, struct cv1800b_clk_fixed_div, clk)
+
+static int fixed_div_enable(struct clk *clk)
+{
+ struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk);
+
+ return cv1800b_clk_setbit(div->base, &div->gate);
+}
+
+static int fixed_div_disable(struct clk *clk)
+{
+ struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk);
+
+ return cv1800b_clk_clrbit(div->base, &div->gate);
+}
+
+static ulong fixed_div_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_fixed_div *div = to_cv1800b_clk_fixed_div(clk);
+
+ return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), div->div);
+}
+
+const struct clk_ops cv1800b_clk_fixed_div_ops = {
+ .disable = fixed_div_disable,
+ .enable = fixed_div_enable,
+ .get_rate = fixed_div_get_rate,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_fixed_div) = {
+ .name = "cv1800b_clk_fixed_div",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_fixed_div_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#define to_cv1800b_clk_bypass_fixed_div(_clk) \
+ container_of(_clk, struct cv1800b_clk_bypass_fixed_div, div.clk)
+
+static ulong bypass_fixed_div_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_bypass_fixed_div *div =
+ to_cv1800b_clk_bypass_fixed_div(clk);
+
+ if (cv1800b_clk_getbit(div->div.base, &div->bypass))
+ return 0;
+
+ return fixed_div_get_rate(clk);
+}
+
+static int bypass_fixed_div_set_parent(struct clk *clk, struct clk *pclk)
+{
+ struct cv1800b_clk_bypass_fixed_div *div =
+ to_cv1800b_clk_bypass_fixed_div(clk);
+
+ if (pclk->id == CV1800B_CLK_BYPASS) {
+ cv1800b_clk_setbit(div->div.base, &div->bypass);
+ return 0;
+ }
+
+ if (strcmp(clk_hw_get_name(pclk), div->div.parent_name))
+ return -EINVAL;
+
+ cv1800b_clk_clrbit(div->div.base, &div->bypass);
+ return 0;
+}
+
+const struct clk_ops cv1800b_clk_bypass_fixed_div_ops = {
+ .disable = fixed_div_disable,
+ .enable = fixed_div_enable,
+ .get_rate = bypass_fixed_div_get_rate,
+ .set_parent = bypass_fixed_div_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_bypass_fixed_div) = {
+ .name = "cv1800b_clk_bypass_fixed_div",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_bypass_fixed_div_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* MUX */
+#define to_cv1800b_clk_mux(_clk) container_of(_clk, struct cv1800b_clk_mux, clk)
+
+static int mux_enable(struct clk *clk)
+{
+ struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);
+
+ return cv1800b_clk_setbit(mux->base, &mux->gate);
+}
+
+static int mux_disable(struct clk *clk)
+{
+ struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);
+
+ return cv1800b_clk_clrbit(mux->base, &mux->gate);
+}
+
+static ulong mux_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);
+ ulong val;
+
+ if (mux->div_init == 0 ||
+ readl(mux->base + mux->div.offset) & CLK_DIV_EN_FACTOR)
+ val = cv1800b_clk_getfield(mux->base, &mux->div);
+ else
+ val = mux->div_init;
+
+ return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);
+}
+
+static ulong mux_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ ulong val;
+
+ val = DIV_ROUND_UP_ULL(parent_rate, rate);
+ val = min_t(u32, val, clk_div_mask(mux->div.width));
+
+ cv1800b_clk_setfield(mux->base, &mux->div, val);
+ if (mux->div_init > 0)
+ setbits_le32(mux->base + mux->div.offset, CLK_DIV_EN_FACTOR);
+
+ return DIV_ROUND_UP_ULL(parent_rate, val);
+}
+
+static int mux_set_parent(struct clk *clk, struct clk *pclk)
+{
+ struct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);
+ int index = get_parent_index(pclk, mux->parent_names, mux->num_parents);
+
+ if (index < 0)
+ return -EINVAL;
+
+ cv1800b_clk_setfield(mux->base, &mux->mux, index);
+ return 0;
+}
+
+const struct clk_ops cv1800b_clk_mux_ops = {
+ .disable = mux_disable,
+ .enable = mux_enable,
+ .get_rate = mux_get_rate,
+ .set_rate = mux_set_rate,
+ .set_parent = mux_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_mux) = {
+ .name = "cv1800b_clk_mux",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_mux_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#define to_cv1800b_clk_bypass_mux(_clk) \
+ container_of(_clk, struct cv1800b_clk_bypass_mux, mux.clk)
+
+static ulong bypass_mux_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk);
+
+ if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass))
+ return 0;
+
+ return mux_get_rate(clk);
+}
+
+static ulong bypass_mux_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk);
+
+ if (cv1800b_clk_getbit(mux->mux.base, &mux->bypass))
+ return 0;
+
+ return mux_set_rate(clk, rate);
+}
+
+static int bypass_mux_set_parent(struct clk *clk, struct clk *pclk)
+{
+ struct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk);
+ int index;
+
+ if (pclk->id == CV1800B_CLK_BYPASS) {
+ cv1800b_clk_setbit(mux->mux.base, &mux->bypass);
+ return 0;
+ }
+
+ index = get_parent_index(pclk, mux->mux.parent_names,
+ mux->mux.num_parents);
+ if (index < 0)
+ return -EINVAL;
+
+ cv1800b_clk_clrbit(mux->mux.base, &mux->bypass);
+ cv1800b_clk_setfield(mux->mux.base, &mux->mux.mux, index);
+ return 0;
+}
+
+const struct clk_ops cv1800b_clk_bypass_mux_ops = {
+ .disable = mux_disable,
+ .enable = mux_enable,
+ .get_rate = bypass_mux_get_rate,
+ .set_rate = bypass_mux_set_rate,
+ .set_parent = bypass_mux_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_bypass_mux) = {
+ .name = "cv1800b_clk_bypass_mux",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_bypass_mux_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* MMUX */
+#define to_cv1800b_clk_mmux(_clk) \
+ container_of(_clk, struct cv1800b_clk_mmux, clk)
+
+static int mmux_enable(struct clk *clk)
+{
+ struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);
+
+ return cv1800b_clk_setbit(mmux->base, &mmux->gate);
+}
+
+static int mmux_disable(struct clk *clk)
+{
+ struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);
+
+ return cv1800b_clk_clrbit(mmux->base, &mmux->gate);
+}
+
+static ulong mmux_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);
+ int clk_sel = 1;
+ ulong reg, val;
+
+ if (cv1800b_clk_getbit(mmux->base, &mmux->bypass))
+ return 0;
+
+ if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel))
+ clk_sel = 0;
+
+ reg = readl(mmux->base + mmux->div[clk_sel].offset);
+
+ if (mmux->div_init[clk_sel] == 0 || reg & CLK_DIV_EN_FACTOR)
+ val = cv1800b_clk_getfield(mmux->base, &mmux->div[clk_sel]);
+ else
+ val = mmux->div_init[clk_sel];
+
+ return DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);
+}
+
+static ulong mmux_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);
+ int clk_sel = 1;
+ ulong parent_rate = clk_get_parent_rate(clk);
+ ulong val;
+
+ if (cv1800b_clk_getbit(mmux->base, &mmux->bypass))
+ return 0;
+
+ if (cv1800b_clk_getbit(mmux->base, &mmux->clk_sel))
+ clk_sel = 0;
+
+ val = DIV_ROUND_UP_ULL(parent_rate, rate);
+ val = min_t(u32, val, clk_div_mask(mmux->div[clk_sel].width));
+
+ cv1800b_clk_setfield(mmux->base, &mmux->div[clk_sel], val);
+ if (mmux->div_init[clk_sel] > 0)
+ setbits_le32(mmux->base + mmux->div[clk_sel].offset,
+ CLK_DIV_EN_FACTOR);
+
+ return DIV_ROUND_UP_ULL(parent_rate, val);
+}
+
+static int mmux_set_parent(struct clk *clk, struct clk *pclk)
+{
+ struct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);
+ const char *pname = clk_hw_get_name(pclk);
+ int i;
+ u8 clk_sel, index;
+
+ if (pclk->id == CV1800B_CLK_BYPASS) {
+ cv1800b_clk_setbit(mmux->base, &mmux->bypass);
+ return 0;
+ }
+
+ for (i = 0; i < mmux->num_parents; i++) {
+ if (!strcmp(pname, mmux->parent_infos[i].name))
+ break;
+ }
+
+ if (i == mmux->num_parents)
+ return -EINVAL;
+
+ clk_sel = mmux->parent_infos[i].clk_sel;
+ index = mmux->parent_infos[i].index;
+ cv1800b_clk_clrbit(mmux->base, &mmux->bypass);
+ if (clk_sel)
+ cv1800b_clk_clrbit(mmux->base, &mmux->clk_sel);
+ else
+ cv1800b_clk_setbit(mmux->base, &mmux->clk_sel);
+
+ cv1800b_clk_setfield(mmux->base, &mmux->mux[clk_sel], index);
+ return 0;
+}
+
+const struct clk_ops cv1800b_clk_mmux_ops = {
+ .disable = mmux_disable,
+ .enable = mmux_enable,
+ .get_rate = mmux_get_rate,
+ .set_rate = mmux_set_rate,
+ .set_parent = mmux_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_mmux) = {
+ .name = "cv1800b_clk_mmux",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_mmux_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* AUDIO CLK */
+#define to_cv1800b_clk_audio(_clk) \
+ container_of(_clk, struct cv1800b_clk_audio, clk)
+
+static int aclk_enable(struct clk *clk)
+{
+ struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk);
+
+ cv1800b_clk_setbit(aclk->base, &aclk->src_en);
+ cv1800b_clk_setbit(aclk->base, &aclk->output_en);
+ return 0;
+}
+
+static int aclk_disable(struct clk *clk)
+{
+ struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk);
+
+ cv1800b_clk_clrbit(aclk->base, &aclk->src_en);
+ cv1800b_clk_clrbit(aclk->base, &aclk->output_en);
+ return 0;
+}
+
+static ulong aclk_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk);
+ u64 parent_rate = clk_get_parent_rate(clk);
+ u32 m, n;
+
+ if (!cv1800b_clk_getbit(aclk->base, &aclk->div_en))
+ return 0;
+
+ m = cv1800b_clk_getfield(aclk->base, &aclk->m);
+ n = cv1800b_clk_getfield(aclk->base, &aclk->n);
+
+ return DIV_ROUND_UP_ULL(n * parent_rate, m * 2);
+}
+
+static u32 gcd(u32 a, u32 b)
+{
+ u32 t;
+
+ while (b != 0) {
+ t = a % b;
+ a = b;
+ b = t;
+ }
+ return a;
+}
+
+static void aclk_determine_mn(ulong parent_rate, ulong rate, u32 *m, u32 *n)
+{
+ u32 tm = parent_rate / 2;
+ u32 tn = rate;
+ u32 tcommon = gcd(tm, tn);
+ *m = tm / tcommon;
+ *n = tn / tcommon;
+}
+
+static ulong aclk_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 m, n;
+
+ aclk_determine_mn(parent_rate, rate, &m, &n);
+
+ cv1800b_clk_setfield(aclk->base, &aclk->m, m);
+ cv1800b_clk_setfield(aclk->base, &aclk->n, n);
+
+ cv1800b_clk_setbit(aclk->base, &aclk->div_en);
+ cv1800b_clk_setbit(aclk->base, &aclk->div_up);
+
+ return DIV_ROUND_UP_ULL(parent_rate * n, m * 2);
+}
+
+const struct clk_ops cv1800b_clk_audio_ops = {
+ .disable = aclk_disable,
+ .enable = aclk_enable,
+ .get_rate = aclk_get_rate,
+ .set_rate = aclk_set_rate,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_audio) = {
+ .name = "cv1800b_clk_audio",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_clk_audio_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/sophgo/clk-ip.h b/drivers/clk/sophgo/clk-ip.h
new file mode 100644
index 0000000..09d15d8
--- /dev/null
+++ b/drivers/clk/sophgo/clk-ip.h
@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ *
+ */
+
+#ifndef __CLK_SOPHGO_IP_H__
+#define __CLK_SOPHGO_IP_H__
+
+#include <clk.h>
+
+#include "clk-common.h"
+
+struct cv1800b_mmux_parent_info {
+ const char *name;
+ u8 clk_sel;
+ u8 index;
+};
+
+struct cv1800b_clk_gate {
+ struct clk clk;
+ const char *name;
+ const char *parent_name;
+ void __iomem *base;
+ struct cv1800b_clk_regbit gate;
+};
+
+struct cv1800b_clk_div {
+ struct clk clk;
+ const char *name;
+ const char *parent_name;
+ void __iomem *base;
+ struct cv1800b_clk_regbit gate;
+ struct cv1800b_clk_regfield div;
+ int div_init;
+};
+
+struct cv1800b_clk_bypass_div {
+ struct cv1800b_clk_div div;
+ struct cv1800b_clk_regbit bypass;
+};
+
+struct cv1800b_clk_fixed_div {
+ struct clk clk;
+ const char *name;
+ const char *parent_name;
+ void __iomem *base;
+ struct cv1800b_clk_regbit gate;
+ int div;
+};
+
+struct cv1800b_clk_bypass_fixed_div {
+ struct cv1800b_clk_fixed_div div;
+ struct cv1800b_clk_regbit bypass;
+};
+
+struct cv1800b_clk_mux {
+ struct clk clk;
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ void __iomem *base;
+ struct cv1800b_clk_regbit gate;
+ struct cv1800b_clk_regfield div;
+ int div_init;
+ struct cv1800b_clk_regfield mux;
+};
+
+struct cv1800b_clk_bypass_mux {
+ struct cv1800b_clk_mux mux;
+ struct cv1800b_clk_regbit bypass;
+};
+
+struct cv1800b_clk_mmux {
+ struct clk clk;
+ const char *name;
+ const struct cv1800b_mmux_parent_info *parent_infos;
+ u8 num_parents;
+ void __iomem *base;
+ struct cv1800b_clk_regbit gate;
+ struct cv1800b_clk_regfield div[2];
+ int div_init[2];
+ struct cv1800b_clk_regfield mux[2];
+ struct cv1800b_clk_regbit bypass;
+ struct cv1800b_clk_regbit clk_sel;
+};
+
+struct cv1800b_clk_audio {
+ struct clk clk;
+ const char *name;
+ const char *parent_name;
+ void __iomem *base;
+ struct cv1800b_clk_regbit src_en;
+ struct cv1800b_clk_regbit output_en;
+ struct cv1800b_clk_regbit div_en;
+ struct cv1800b_clk_regbit div_up;
+ struct cv1800b_clk_regfield m;
+ struct cv1800b_clk_regfield n;
+};
+
+#define CV1800B_GATE(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \
+ }
+
+#define CV1800B_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, _div_width, \
+ _div_init, _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \
+ .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \
+ _div_width), \
+ .div_init = _div_init, \
+ }
+
+#define CV1800B_BYPASS_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, \
+ _div_width, _div_init, \
+ _bypass_offset, _bypass_shift, \
+ _flags) \
+ { \
+ .div = CV1800B_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, _div_width, \
+ _div_init, _flags), \
+ .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \
+ _bypass_shift), \
+ }
+
+#define CV1800B_FIXED_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div, _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \
+ .div = _div, \
+ }
+
+#define CV1800B_BYPASS_FIXED_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div, \
+ _bypass_offset, _bypass_shift, \
+ _flags) \
+ { \
+ .div = CV1800B_FIXED_DIV(_id, _name, _parent, \
+ _gate_offset, _gate_shift, \
+ _div, _flags), \
+ .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \
+ _bypass_shift) \
+ }
+
+#define CV1800B_MUX(_id, _name, _parents, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, _div_width, _div_init, \
+ _mux_offset, _mux_shift, _mux_width, \
+ _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \
+ .div = CV1800B_CLK_REGFIELD(_div_offset, _div_shift, \
+ _div_width), \
+ .div_init = _div_init, \
+ .mux = CV1800B_CLK_REGFIELD(_mux_offset, _mux_shift, \
+ _mux_width), \
+ }
+
+#define CV1800B_BYPASS_MUX(_id, _name, _parents, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, \
+ _div_width, _div_init, \
+ _mux_offset, _mux_shift, _mux_width, \
+ _bypass_offset, _bypass_shift, \
+ _flags) \
+ { \
+ .mux = CV1800B_MUX(_id, _name, _parents, \
+ _gate_offset, _gate_shift, \
+ _div_offset, _div_shift, \
+ _div_width, _div_init, \
+ _mux_offset, _mux_shift, _mux_width, \
+ _flags), \
+ .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \
+ _bypass_shift), \
+ }
+
+#define CV1800B_MMUX(_id, _name, _parents, \
+ _gate_offset, _gate_shift, \
+ _div0_offset, _div0_shift, _div0_width, _div0_init,\
+ _div1_offset, _div1_shift, _div1_width, _div1_init,\
+ _mux0_offset, _mux0_shift, _mux0_width, \
+ _mux1_offset, _mux1_shift, _mux1_width, \
+ _bypass_offset, _bypass_shift, \
+ _clk_sel_offset, _clk_sel_shift, \
+ _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_infos = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .gate = CV1800B_CLK_REGBIT(_gate_offset, _gate_shift), \
+ .div = { \
+ CV1800B_CLK_REGFIELD(_div0_offset, _div0_shift, \
+ _div0_width), \
+ CV1800B_CLK_REGFIELD(_div1_offset, _div1_shift, \
+ _div1_width), \
+ }, \
+ .div_init = { _div0_init, _div1_init }, \
+ .mux = { \
+ CV1800B_CLK_REGFIELD(_mux0_offset, _mux0_shift, \
+ _mux0_width), \
+ CV1800B_CLK_REGFIELD(_mux1_offset, _mux1_shift, \
+ _mux1_width), \
+ }, \
+ .bypass = CV1800B_CLK_REGBIT(_bypass_offset, \
+ _bypass_shift), \
+ .clk_sel = CV1800B_CLK_REGBIT(_clk_sel_offset, \
+ _clk_sel_shift), \
+ }
+
+#define CV1800B_AUDIO(_id, _name, _parent, \
+ _src_en_offset, _src_en_shift, \
+ _output_en_offset, _output_en_shift, \
+ _div_en_offset, _div_en_shift, \
+ _div_up_offset, _div_up_shift, \
+ _m_offset, _m_shift, _m_width, \
+ _n_offset, _n_shift, _n_width, \
+ _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .src_en = CV1800B_CLK_REGBIT(_src_en_offset, \
+ _src_en_shift), \
+ .output_en = CV1800B_CLK_REGBIT(_output_en_offset, \
+ _output_en_shift), \
+ .div_en = CV1800B_CLK_REGBIT(_div_en_offset, \
+ _div_en_shift), \
+ .div_up = CV1800B_CLK_REGBIT(_div_up_offset, \
+ _div_up_shift), \
+ .m = CV1800B_CLK_REGFIELD(_m_offset, _m_shift, \
+ _m_width), \
+ .n = CV1800B_CLK_REGFIELD(_n_offset, _n_shift, \
+ _n_width), \
+ }
+
+extern const struct clk_ops cv1800b_clk_gate_ops;
+extern const struct clk_ops cv1800b_clk_div_ops;
+extern const struct clk_ops cv1800b_clk_bypass_div_ops;
+extern const struct clk_ops cv1800b_clk_fixed_div_ops;
+extern const struct clk_ops cv1800b_clk_bypass_fixed_div_ops;
+extern const struct clk_ops cv1800b_clk_mux_ops;
+extern const struct clk_ops cv1800b_clk_bypass_mux_ops;
+extern const struct clk_ops cv1800b_clk_mmux_ops;
+extern const struct clk_ops cv1800b_clk_audio_ops;
+
+#endif /* __CLK_SOPHGO_IP_H__ */
diff --git a/drivers/clk/sophgo/clk-pll.c b/drivers/clk/sophgo/clk-pll.c
new file mode 100644
index 0000000..c99aa0b
--- /dev/null
+++ b/drivers/clk/sophgo/clk-pll.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <div64.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+
+#include "clk-common.h"
+#include "clk-pll.h"
+
+#define PLL_PRE_DIV_MIN 1
+#define PLL_PRE_DIV_MAX 127
+#define PLL_POST_DIV_MIN 1
+#define PLL_POST_DIV_MAX 127
+#define PLL_DIV_MIN 6
+#define PLL_DIV_MAX 127
+#define PLL_ICTRL_MIN 0
+#define PLL_ICTRL_MAX 7
+#define PLL_MODE_MIN 0
+#define PLL_MODE_MAX 3
+#define FOR_RANGE(x, RANGE) for (x = RANGE##_MIN; x <= RANGE##_MAX; x++)
+
+#define PLL_ICTRL GENMASK(26, 24)
+#define PLL_DIV_SEL GENMASK(23, 17)
+#define PLL_SEL_MODE GENMASK(16, 15)
+#define PLL_POST_DIV_SEL GENMASK(14, 8)
+#define PLL_PRE_DIV_SEL GENMASK(6, 0)
+#define PLL_MASK_ALL (PLL_ICTRL | PLL_DIV_SEL | PLL_SEL_MODE | PLL_POST_DIV_SEL | PLL_PRE_DIV_SEL)
+
+/* IPLL */
+#define to_clk_ipll(dev) container_of(dev, struct cv1800b_clk_ipll, clk)
+
+static int cv1800b_ipll_enable(struct clk *clk)
+{
+ struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
+
+ cv1800b_clk_clrbit(pll->base, &pll->pll_pwd);
+ return 0;
+}
+
+static int cv1800b_ipll_disable(struct clk *clk)
+{
+ struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
+
+ cv1800b_clk_setbit(pll->base, &pll->pll_pwd);
+ return 0;
+}
+
+static ulong cv1800b_ipll_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
+
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 reg = readl(pll->base + pll->pll_reg);
+ u32 pre_div = FIELD_GET(PLL_PRE_DIV_SEL, reg);
+ u32 post_div = FIELD_GET(PLL_POST_DIV_SEL, reg);
+ u32 div = FIELD_GET(PLL_DIV_SEL, reg);
+
+ return DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div);
+}
+
+static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 pre_div, post_div, div;
+ u32 pre_div_sel, post_div_sel, div_sel;
+ ulong new_rate, best_rate = 0;
+ u32 mode, ictrl;
+ u32 test, val;
+
+ FOR_RANGE(pre_div, PLL_PRE_DIV)
+ {
+ FOR_RANGE(post_div, PLL_POST_DIV)
+ {
+ FOR_RANGE(div, PLL_DIV)
+ {
+ new_rate =
+ DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div);
+ if (rate - new_rate < rate - best_rate) {
+ best_rate = new_rate;
+ pre_div_sel = pre_div;
+ post_div_sel = post_div;
+ div_sel = div;
+ }
+ }
+ }
+ }
+
+ FOR_RANGE(mode, PLL_MODE)
+ {
+ FOR_RANGE(ictrl, PLL_ICTRL)
+ {
+ test = 184 * (1 + mode) * (1 + ictrl) / 2;
+ if (test > 20 * div_sel && test < 35 * div_sel) {
+ val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) |
+ FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) |
+ FIELD_PREP(PLL_DIV_SEL, div_sel) |
+ FIELD_PREP(PLL_ICTRL, ictrl) |
+ FIELD_PREP(PLL_SEL_MODE, mode);
+ clrsetbits_le32(pll->base + pll->pll_reg, PLL_MASK_ALL, val);
+ return best_rate;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+const struct clk_ops cv1800b_ipll_ops = {
+ .enable = cv1800b_ipll_enable,
+ .disable = cv1800b_ipll_disable,
+ .get_rate = cv1800b_ipll_get_rate,
+ .set_rate = cv1800b_ipll_set_rate,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_ipll) = {
+ .name = "cv1800b_clk_ipll",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_ipll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* FPLL */
+#define to_clk_fpll(dev) container_of(dev, struct cv1800b_clk_fpll, ipll.clk)
+
+static ulong cv1800b_fpll_get_rate(struct clk *clk)
+{
+ struct cv1800b_clk_fpll *pll = to_clk_fpll(clk);
+ u32 val, syn_set;
+ u32 pre_div, post_div, div;
+ u8 mult = 1;
+ ulong divisor, remainder, rate;
+
+ if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en))
+ return cv1800b_ipll_get_rate(clk);
+
+ syn_set = readl(pll->ipll.base + pll->syn.set);
+ if (syn_set == 0)
+ return 0;
+
+ val = readl(pll->ipll.base + pll->ipll.pll_reg);
+ pre_div = FIELD_GET(PLL_PRE_DIV_SEL, val);
+ post_div = FIELD_GET(PLL_POST_DIV_SEL, val);
+ div = FIELD_GET(PLL_DIV_SEL, val);
+
+ if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half))
+ mult = 2;
+
+ divisor = (ulong)pre_div * post_div * syn_set;
+ rate = (clk_get_parent_rate(clk) * div) << 25;
+ remainder = rate % divisor;
+ rate /= divisor;
+ return rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor);
+}
+
+static ulong cv1800b_find_syn(ulong rate, ulong parent_rate, ulong pre_div, ulong post_div,
+ ulong div, u32 *syn)
+{
+ u32 syn_min = (4 << 26) + 1;
+ u32 syn_max = U32_MAX;
+ u32 mid;
+ ulong new_rate;
+ u32 mult = 1;
+ ulong divisor, remainder;
+
+ while (syn_min < syn_max) {
+ mid = ((ulong)syn_min + syn_max) / 2;
+ divisor = pre_div * post_div * mid;
+ new_rate = (parent_rate * div) << 25;
+ remainder = do_div(new_rate, divisor);
+ new_rate = new_rate * mult + DIV_ROUND_CLOSEST_ULL(remainder * mult, divisor);
+ if (new_rate > rate) {
+ syn_max = mid + 1;
+ } else if (new_rate < rate) {
+ syn_min = mid - 1;
+ } else {
+ syn_min = mid;
+ break;
+ }
+ }
+ *syn = syn_min;
+ return new_rate;
+}
+
+static ulong cv1800b_fpll_set_rate(struct clk *clk, ulong rate)
+{
+ struct cv1800b_clk_fpll *pll = to_clk_fpll(clk);
+ ulong parent_rate = clk_get_parent_rate(clk);
+ u32 pre_div, post_div, div;
+ u32 pre_div_sel, post_div_sel, div_sel;
+ u32 syn, syn_sel;
+ ulong new_rate, best_rate = 0;
+ u32 mult = 1;
+ u32 mode, ictrl;
+
+ if (!cv1800b_clk_getbit(pll->ipll.base, &pll->syn.en))
+ return cv1800b_ipll_set_rate(clk, rate);
+
+ if (cv1800b_clk_getbit(pll->ipll.base, &pll->syn.clk_half))
+ mult = 2;
+
+ FOR_RANGE(pre_div, PLL_PRE_DIV)
+ {
+ FOR_RANGE(post_div, PLL_POST_DIV)
+ {
+ FOR_RANGE(div, PLL_DIV)
+ {
+ new_rate = cv1800b_find_syn(rate, parent_rate, pre_div, post_div,
+ div, &syn);
+ if (rate - new_rate < rate - best_rate) {
+ best_rate = new_rate;
+ pre_div_sel = pre_div;
+ post_div_sel = post_div;
+ div_sel = div;
+ syn_sel = syn;
+ }
+ }
+ }
+ }
+
+ FOR_RANGE(mode, PLL_MODE)
+ {
+ FOR_RANGE(ictrl, PLL_ICTRL)
+ {
+ u32 test = 184 * (1 + mode) * (1 + ictrl) / 2;
+
+ if (test > 10 * div_sel && test <= 24 * div_sel) {
+ u32 val = FIELD_PREP(PLL_PRE_DIV_SEL, pre_div_sel) |
+ FIELD_PREP(PLL_POST_DIV_SEL, post_div_sel) |
+ FIELD_PREP(PLL_DIV_SEL, div_sel) |
+ FIELD_PREP(PLL_ICTRL, ictrl) |
+ FIELD_PREP(PLL_SEL_MODE, mode);
+ clrsetbits_le32(pll->ipll.base + pll->ipll.pll_reg, PLL_MASK_ALL,
+ val);
+ writel(syn_sel, pll->ipll.base + pll->syn.set);
+ return best_rate;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int cv1800b_fpll_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct cv1800b_clk_fpll *pll = to_clk_fpll(clk);
+
+ if (parent->id == CV1800B_CLK_BYPASS)
+ cv1800b_clk_setbit(pll->ipll.base, &pll->syn.en);
+ else
+ cv1800b_clk_clrbit(pll->ipll.base, &pll->syn.en);
+
+ return 0;
+}
+
+const struct clk_ops cv1800b_fpll_ops = {
+ .enable = cv1800b_ipll_enable,
+ .disable = cv1800b_ipll_disable,
+ .get_rate = cv1800b_fpll_get_rate,
+ .set_rate = cv1800b_fpll_set_rate,
+ .set_parent = cv1800b_fpll_set_parent,
+};
+
+U_BOOT_DRIVER(cv1800b_clk_fpll) = {
+ .name = "cv1800b_clk_fpll",
+ .id = UCLASS_CLK,
+ .ops = &cv1800b_fpll_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/sophgo/clk-pll.h b/drivers/clk/sophgo/clk-pll.h
new file mode 100644
index 0000000..bea9bd8
--- /dev/null
+++ b/drivers/clk/sophgo/clk-pll.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ *
+ */
+
+#ifndef __clk_SOPHGO_PLL_H__
+#define __clk_SOPHGO_PLL_H__
+
+#include <clk.h>
+
+#include "clk-common.h"
+
+struct cv1800b_clk_synthesizer {
+ struct cv1800b_clk_regbit en;
+ struct cv1800b_clk_regbit clk_half;
+ u32 ctrl;
+ u32 set;
+};
+
+struct cv1800b_clk_ipll {
+ struct clk clk;
+ const char *name;
+ const char *parent_name;
+ void __iomem *base;
+ u32 pll_reg;
+ struct cv1800b_clk_regbit pll_pwd;
+ struct cv1800b_clk_regbit pll_status;
+};
+
+struct cv1800b_clk_fpll {
+ struct cv1800b_clk_ipll ipll;
+ struct cv1800b_clk_synthesizer syn;
+};
+
+#define CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \
+ _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \
+ _flags) \
+ { \
+ .clk = { \
+ .id = CV1800B_CLK_ID_TRANSFORM(_id), \
+ .flags = _flags, \
+ }, \
+ .name = _name, \
+ .parent_name = _parent_name, \
+ .pll_reg = _pll_reg, \
+ .pll_pwd = CV1800B_CLK_REGBIT(_pll_pwd_offset, _pll_pwd_shift), \
+ .pll_status = CV1800B_CLK_REGBIT(_pll_status_offset, \
+ _pll_status_shift), \
+ }
+
+#define CV1800B_FPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \
+ _pll_pwd_shift, _pll_status_offset, _pll_status_shift, \
+ _syn_en_offset, _syn_en_shift, _syn_clk_half_offset, \
+ _syn_clk_half_shift, _syn_ctrl_offset, _syn_set_offset, \
+ _flags) \
+ { \
+ .ipll = CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, \
+ _pll_pwd_offset, _pll_pwd_shift, \
+ _pll_status_offset, _pll_status_shift, \
+ _flags), \
+ .syn = { \
+ .en = CV1800B_CLK_REGBIT(_syn_en_offset, _syn_en_shift),\
+ .clk_half = CV1800B_CLK_REGBIT(_syn_clk_half_offset, \
+ _syn_clk_half_shift), \
+ .ctrl = _syn_ctrl_offset, \
+ .set = _syn_set_offset, \
+ }, \
+ }
+
+extern const struct clk_ops cv1800b_ipll_ops;
+extern const struct clk_ops cv1800b_fpll_ops;
+
+#endif /* __clk_SOPHGO_PLL_H__ */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 1a7be4d..c39abe3 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -146,6 +146,7 @@
config SPL_DM_SEQ_ALIAS
bool "Support numbered aliases in device tree in SPL"
depends on SPL_DM
+ select SPL_STRTO
help
Most boards will have a '/aliases' node containing the path to
numbered devices (e.g. serial0 = &serial0). This feature can be
diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index 5ec30d5..5cbaa97 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -40,7 +40,7 @@
/* print the first 20 characters to not break the tree-format. */
printf(CONFIG_IS_ENABLED(USE_TINY_PRINTF) ? " %s %d [ %c ] %s " :
" %-10.10s %3d [ %c ] %-20.20s ", dev->uclass->uc_drv->name,
- dev_get_uclass_index(dev, NULL),
+ dev->seq_,
flags & DM_FLAG_ACTIVATED ? '+' : ' ', dev->driver->name);
for (i = depth; i >= 0; i--) {
@@ -129,7 +129,7 @@
{
struct udevice *root;
- printf(" Class Index Probed Driver Name\n");
+ printf(" Class Seq Probed Driver Name\n");
printf("-----------------------------------------------------------\n");
root = dm_root();
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 9e59968..2aa58b0 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -19,11 +19,10 @@
DECLARE_GLOBAL_DATA_PTR;
-fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index)
+#if CONFIG_IS_ENABLED(OF_REAL) || CONFIG_IS_ENABLED(OF_CONTROL)
+fdt_addr_t devfdt_get_addr_index_parent(const struct udevice *dev, int index,
+ int offset, int parent)
{
-#if CONFIG_IS_ENABLED(OF_REAL)
- int offset = dev_of_offset(dev);
- int parent = fdt_parent_offset(gd->fdt_blob, offset);
fdt_addr_t addr;
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
@@ -89,6 +88,15 @@
#endif
return addr;
+}
+#endif
+
+fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index)
+{
+#if CONFIG_IS_ENABLED(OF_REAL)
+ int offset = dev_of_offset(dev);
+ int parent = fdt_parent_offset(gd->fdt_blob, offset);
+ return devfdt_get_addr_index_parent(dev, index, offset, parent);
#else
return FDT_ADDR_T_NONE;
#endif
@@ -113,14 +121,16 @@
* next call to the exisiting dev_get_xxx function which handles
* all config options.
*/
- fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev_of_offset(dev),
- "reg", index, size, false);
+ int offset = dev_of_offset(dev);
+ int parent = fdt_parent_offset(gd->fdt_blob, offset);
+ fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent, offset,
+ "reg", index, size, false);
/*
* Get the base address via the existing function which handles
* all Kconfig cases
*/
- return devfdt_get_addr_index(dev, index);
+ return devfdt_get_addr_index_parent(dev, index, offset, parent);
#else
return FDT_ADDR_T_NONE;
#endif
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 4d563b4..7e3b371 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -762,8 +762,9 @@
return of_read_number(prop_val, na);
}
} else {
- na = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
- ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
+ ofnode parent = ofnode_get_parent(node);
+ na = ofnode_read_simple_addr_cells(parent);
+ ns = ofnode_read_simple_size_cells(parent);
return fdtdec_get_addr_size_fixed(ofnode_to_fdt(node),
ofnode_to_offset(node), "reg",
index, na, ns, size,
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 304d5b0..5cb5fa2 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -168,18 +168,21 @@
int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index)
{
+ ofnode parent;
struct regmap *map;
int addr_len, size_len;
int ret;
- addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
+ parent = ofnode_get_parent(node);
+
+ addr_len = ofnode_read_simple_addr_cells(parent);
if (addr_len < 0) {
dm_warn("%s: Error while reading the addr length (ret = %d)\n",
ofnode_get_name(node), addr_len);
return addr_len;
}
- size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
+ size_len = ofnode_read_simple_size_cells(parent);
if (size_len < 0) {
dm_warn("%s: Error while reading the size length: (ret = %d)\n",
ofnode_get_name(node), size_len);
@@ -241,6 +244,7 @@
int regmap_init_mem(ofnode node, struct regmap **mapp)
{
+ ofnode parent;
struct regmap_range *range;
struct regmap *map;
int count;
@@ -249,14 +253,16 @@
int index;
int ret;
- addr_len = ofnode_read_simple_addr_cells(ofnode_get_parent(node));
+ parent = ofnode_get_parent(node);
+
+ addr_len = ofnode_read_simple_addr_cells(parent);
if (addr_len < 0) {
dm_warn("%s: Error while reading the addr length (ret = %d)\n",
ofnode_get_name(node), addr_len);
return addr_len;
}
- size_len = ofnode_read_simple_size_cells(ofnode_get_parent(node));
+ size_len = ofnode_read_simple_size_cells(parent);
if (size_len < 0) {
dm_warn("%s: Error while reading the size length: (ret = %d)\n",
ofnode_get_name(node), size_len);
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 60deca9..6c0a8c0 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -60,6 +60,10 @@
return "93(12)";/* iMX93 9x9 Dual core without NPU */
case MXC_CPU_IMX9311:
return "93(11)";/* iMX93 9x9 Single core without NPU */
+ case MXC_CPU_IMX9302:
+ return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */
+ case MXC_CPU_IMX9301:
+ return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */
default:
return "??";
}
diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig
index 9bf3171..473e3e5 100644
--- a/drivers/crypto/aspeed/Kconfig
+++ b/drivers/crypto/aspeed/Kconfig
@@ -18,3 +18,13 @@
Enabling this allows the use of RSA/ECC operations in hardware without requiring the
software implementations. It also improves performance and saves code size.
+
+config ASPEED_CPTRA_SHA
+ bool "Caliptra SHA ACC for Aspeed AST27xx SoCs"
+ depends on DM_HASH
+ help
+ Select this option to enable a driver for using the SHA accelerator provided
+ by Caliptra 1.0, which is integrated in AST27xx BMC SoCs.
+
+ Enabling this allows the use of SHA operations in hardware. Note that only
+ SHA384 and SHA512 are supported by Caliptra 1.0.
diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makefile
index 58b55fc..570587e 100644
--- a/drivers/crypto/aspeed/Makefile
+++ b/drivers/crypto/aspeed/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o
obj-$(CONFIG_ASPEED_ACRY) += aspeed_acry.o
+obj-$(CONFIG_ASPEED_CPTRA_SHA) += cptra_sha.o
diff --git a/drivers/crypto/aspeed/cptra_sha.c b/drivers/crypto/aspeed/cptra_sha.c
new file mode 100644
index 0000000..26b97bdd
--- /dev/null
+++ b/drivers/crypto/aspeed/cptra_sha.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2024 ASPEED Technology Inc.
+ */
+#include <asm/io.h>
+#include <config.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <malloc.h>
+#include <u-boot/hash.h>
+#include <watchdog.h>
+
+/* SHA register offsets */
+#define CPTRA_SHA_LOCK 0x00
+#define CPTRA_SHA_USER 0x04
+#define CPTRA_SHA_MODE 0x08
+#define CPTRA_SHA_MODE_ENDIAN BIT(2)
+#define CPTRA_SHA_MODE_SEL GENMASK(1, 0)
+#define CPTRA_SHA_DLEN 0x10
+#define CPTRA_SHA_DATAIN 0x14
+#define CPTRA_SHA_EXEC 0x18
+#define CPTRA_SHA_STS 0x1c
+#define CPTRA_SHA_STS_SOC_LOCK BIT(1)
+#define CPTRA_SHA_STS_VLD BIT(0)
+#define CPTRA_SHA_DIGEST(n) (0x20 + ((n) << 2))
+#define CPTRA_SHA_CTRL 0x60
+#define CPTRA_SHA_CTRL_ZEROIZE BIT(0)
+
+enum cptra_sha_modes {
+ CPTRA_SHA384_STREAM,
+ CPTRA_SHA512_STREAM,
+};
+
+struct cptra_sha_ctx {
+ enum HASH_ALGO algo;
+ uint32_t dgst_len;
+};
+
+struct cptra_sha {
+ void *regs;
+};
+
+static int cptra_sha_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp)
+{
+ struct cptra_sha_ctx *cs_ctx;
+ struct cptra_sha *cs;
+ uint32_t mode;
+ uint32_t reg;
+ int rc;
+
+ cs_ctx = malloc(sizeof(struct cptra_sha_ctx));
+ if (!cs_ctx)
+ return -ENOMEM;
+
+ memset(cs_ctx, 0, sizeof(struct cptra_sha_ctx));
+
+ cs_ctx->algo = algo;
+
+ switch (algo) {
+ case HASH_ALGO_SHA384:
+ mode = CPTRA_SHA384_STREAM;
+ cs_ctx->dgst_len = 48;
+ break;
+ case HASH_ALGO_SHA512:
+ mode = CPTRA_SHA512_STREAM;
+ cs_ctx->dgst_len = 64;
+ break;
+ default:
+ rc = -EINVAL;
+ goto free_n_out;
+ };
+
+ cs = dev_get_priv(dev);
+
+ /* get CPTRA SHA lock */
+ if (readl_poll_timeout(cs->regs + CPTRA_SHA_LOCK, reg, reg == 0, 1000000))
+ return -EBUSY;
+
+ /* zero clear SHA */
+ writel(CPTRA_SHA_CTRL_ZEROIZE, cs->regs + CPTRA_SHA_CTRL);
+
+ /* zero clear length */
+ writel(0x0, cs->regs + CPTRA_SHA_DLEN);
+
+ /* set SHA mode */
+ reg = readl(cs->regs + CPTRA_SHA_MODE);
+ reg &= ~(CPTRA_SHA_MODE_SEL);
+ reg |= FIELD_PREP(CPTRA_SHA_MODE_SEL, mode);
+ writel(reg, cs->regs + CPTRA_SHA_MODE);
+
+ *ctxp = cs_ctx;
+
+ return 0;
+
+free_n_out:
+ free(cs_ctx);
+
+ return rc;
+}
+
+static int cptra_sha_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen)
+{
+ struct cptra_sha *cs;
+ uint32_t din_be;
+ uint32_t dlen_sum;
+ uint8_t *p8;
+ uint32_t i;
+
+ cs = dev_get_priv(dev);
+
+ /* update length */
+ dlen_sum = readl(cs->regs + CPTRA_SHA_DLEN) + ilen;
+ writel(dlen_sum, cs->regs + CPTRA_SHA_DLEN);
+
+ din_be = 0;
+ for (i = 0, p8 = (uint8_t *)ibuf; i < ilen; ++i) {
+ if (i && (i % sizeof(din_be) == 0)) {
+ writel(din_be, cs->regs + CPTRA_SHA_DATAIN);
+ din_be = 0;
+ }
+
+ din_be <<= 8;
+ din_be |= p8[i];
+ }
+
+ if (i % sizeof(din_be))
+ din_be <<= (8 * (sizeof(din_be) - (i % sizeof(din_be))));
+
+ writel(din_be, cs->regs + CPTRA_SHA_DATAIN);
+
+ return 0;
+}
+
+static int cptra_sha_finish(struct udevice *dev, void *ctx, void *obuf)
+{
+ struct cptra_sha_ctx *cs_ctx;
+ struct cptra_sha *cs;
+ uint32_t i, *p32;
+ uint32_t sts;
+
+ cs = dev_get_priv(dev);
+ cs_ctx = (struct cptra_sha_ctx *)ctx;
+
+ /* trigger SHA calculation */
+ writel(0x1, cs->regs + CPTRA_SHA_EXEC);
+
+ /* wait for completion */
+ while (1) {
+ sts = readl(cs->regs + CPTRA_SHA_STS);
+ if (sts & CPTRA_SHA_STS_VLD)
+ break;
+ }
+
+ /* get the SHA digest in big-endian */
+ p32 = (uint32_t *)obuf;
+ for (i = 0; i < (cs_ctx->dgst_len / sizeof(*p32)); ++i, p32++)
+ *p32 = be32_to_cpu(readl(cs->regs + CPTRA_SHA_DIGEST(i)));
+
+ /* release CPTRA SHA lock */
+ writel(0x1, cs->regs + CPTRA_SHA_LOCK);
+
+ free(cs_ctx);
+
+ return 0;
+}
+
+static int cptra_sha_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen,
+ void *obuf, uint32_t chunk_sz)
+{
+ const void *cur, *end;
+ uint32_t chunk;
+ void *ctx;
+ int rc;
+
+ rc = cptra_sha_init(dev, algo, &ctx);
+ if (rc)
+ return rc;
+
+ if (IS_ENABLED(CONFIG_HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) {
+ cur = ibuf;
+ end = ibuf + ilen;
+
+ while (cur < end) {
+ chunk = end - cur;
+ if (chunk > chunk_sz)
+ chunk = chunk_sz;
+
+ rc = cptra_sha_update(dev, ctx, cur, chunk);
+ if (rc)
+ return rc;
+
+ cur += chunk;
+ schedule();
+ }
+ } else {
+ rc = cptra_sha_update(dev, ctx, ibuf, ilen);
+ if (rc)
+ return rc;
+ }
+
+ rc = cptra_sha_finish(dev, ctx, obuf);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static int cptra_sha_digest(struct udevice *dev, enum HASH_ALGO algo,
+ const void *ibuf, const uint32_t ilen, void *obuf)
+{
+ /* re-use the watchdog version with input length as the chunk_sz */
+ return cptra_sha_digest_wd(dev, algo, ibuf, ilen, obuf, ilen);
+}
+
+static int cptra_sha_probe(struct udevice *dev)
+{
+ struct cptra_sha *cs = dev_get_priv(dev);
+
+ cs->regs = (void *)devfdt_get_addr(dev);
+ if (cs->regs == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map Caliptra SHA ACC registers\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int cptra_sha_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct hash_ops cptra_sha_ops = {
+ .hash_init = cptra_sha_init,
+ .hash_update = cptra_sha_update,
+ .hash_finish = cptra_sha_finish,
+ .hash_digest_wd = cptra_sha_digest_wd,
+ .hash_digest = cptra_sha_digest,
+};
+
+static const struct udevice_id cptra_sha_ids[] = {
+ { .compatible = "aspeed,ast2700-cptra-sha" },
+ { }
+};
+
+U_BOOT_DRIVER(aspeed_cptra_sha) = {
+ .name = "aspeed_cptra_sha",
+ .id = UCLASS_HASH,
+ .of_match = cptra_sha_ids,
+ .ops = &cptra_sha_ops,
+ .probe = cptra_sha_probe,
+ .remove = cptra_sha_remove,
+ .priv_auto = sizeof(struct cptra_sha),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 31091bb..888dfb7 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -111,7 +111,7 @@
#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, 0, buf, len);
#else
- ret = i2c_read(dev->chip, addr, alen, buf, len);
+ ret = 0;
#endif
return ret;
@@ -162,7 +162,6 @@
};
dev = &ldev;
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index cf5bdad..14278f5 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,10 @@
dram_pll_init(MHZ(266));
dram_disable_bypass();
break;
+ case 933:
+ dram_pll_init(MHZ(233));
+ dram_disable_bypass();
+ break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 9712047..aadd7e8 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -7,7 +7,7 @@
config DFU_OVER_USB
bool
select HASH
- depends on USB_GADGET
+ depends on USB_GADGET_DOWNLOAD
config DFU_OVER_TFTP
bool
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index b7e674f..e23d09e 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -2118,6 +2118,9 @@
if (ret)
dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ udma_alloc_tchan_raw(uc);
+
return ret;
}
@@ -2166,6 +2169,9 @@
dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
ret);
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ udma_alloc_rchan_raw(uc);
+
return ret;
}
diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
index e0767fc..96c6496 100644
--- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c
+++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -11,7 +11,7 @@
#include <log.h>
#include <malloc.h>
#include <string.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/devres.h>
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index e591333..719cfa7 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2450,6 +2450,12 @@
return ret;
}
+static int ti_sci_cmd_rm_udmap_rx_flow_cfg_noop(const struct ti_sci_handle *handle,
+ const struct ti_sci_msg_rm_udmap_flow_cfg *params)
+{
+ return 0;
+}
+
/**
* ti_sci_cmd_set_fwl_region() - Request for configuring a firewall region
* @handle: pointer to TI SCI handle
@@ -2895,7 +2901,7 @@
udmap_ops = &ops->rm_udmap_ops;
udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;
udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;
- udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;
+ udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg_noop;
return ret;
}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fcca694..3996333 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -157,6 +157,13 @@
is found in the AST2400, AST2500 and AST2600 BMC SoCs and
provides access to over 200 GPIOs on each chip.
+config ASPEED_G7_GPIO
+ bool "Aspeed G7 GPIO Driver"
+ help
+ Say yes here to support the Aspeed G7 GPIO driver. The controller
+ is found in the AST2700 BMC SoCs and provides access to over 200
+ GPIOs on each chip.
+
config DA8XX_GPIO
bool "DA8xx GPIO Driver"
help
@@ -301,6 +308,15 @@
Support GPIO controllers on Nuvovon NPCM SoCs.
NPCM7xx/NPCM8xx contain 8 GPIO banks, each bank contains 32 pins.
+config NPCM_SGPIO
+ bool "Nuvoton NPCM SGPIO driver"
+ depends on DM_GPIO
+ help
+ Support Nuvoton BMC NPCM7xx/NPCM8xx sgpio driver support.
+ Nuvoton NPCM SGPIO module is combine serial to parallel IC (HC595)
+ and parallel to serial IC (HC165).
+ BMC can use this driver to increase 64 GPI pins and 64 GPO pins to use.
+
config OMAP_GPIO
bool "TI OMAP GPIO driver"
depends on ARCH_OMAP2PLUS
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4a29315..da0faf0 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -13,6 +13,7 @@
obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o
obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o
+obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o
@@ -27,6 +28,7 @@
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o
+obj-$(CONFIG_NPCM_SGPIO) += npcm_sgpio.o
obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o
obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o
diff --git a/drivers/gpio/gpio-aspeed-g7.c b/drivers/gpio/gpio-aspeed-g7.c
new file mode 100644
index 0000000..4c6ab86
--- /dev/null
+++ b/drivers/gpio/gpio-aspeed-g7.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ * Billy Tsai <billy_tsai@aspeedtech.com>
+ */
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include <config.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/sizes.h>
+
+struct aspeed_gpio_priv {
+ void *regs;
+};
+
+#define GPIO_G7_IRQ_STS_BASE 0x100
+#define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4)
+#define GPIO_G7_CTRL_REG_BASE 0x180
+#define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4)
+#define GPIO_G7_OUT_DATA BIT(0)
+#define GPIO_G7_DIR BIT(1)
+#define GPIO_G7_IRQ_EN BIT(2)
+#define GPIO_G7_IRQ_TYPE0 BIT(3)
+#define GPIO_G7_IRQ_TYPE1 BIT(4)
+#define GPIO_G7_IRQ_TYPE2 BIT(5)
+#define GPIO_G7_RST_TOLERANCE BIT(6)
+#define GPIO_G7_DEBOUNCE_SEL GENMASK(8, 7)
+#define GPIO_G7_INPUT_MASK BIT(9)
+#define GPIO_G7_IRQ_STS BIT(12)
+#define GPIO_G7_IN_DATA BIT(13)
+/*
+ * The configuration of the following registers should be determined
+ * outside of the GPIO driver.
+ */
+#define GPIO_G7_PRIVILEGE_W_REG_BASE 0x810
+#define GPIO_G7_PRIVILEGE_W_REG_OFFSET(x) (GPIO_G7_PRIVILEGE_W_REG_BASE + ((x) >> 2) * 0x4)
+#define GPIO_G7_PRIVILEGE_R_REG_BASE 0x910
+#define GPIO_G7_PRIVILEGE_R_REG_OFFSET(x) (GPIO_G7_PRIVILEGE_R_REG_BASE + ((x) >> 2) * 0x4)
+#define GPIO_G7_IRQ_TARGET_REG_BASE 0xA10
+#define GPIO_G7_IRQ_TARGET_REG_OFFSET(x) (GPIO_G7_IRQ_TARGET_REG_BASE + ((x) >> 2) * 0x4)
+#define GPIO_G7_IRQ_TO_INTC2_18 BIT(0)
+#define GPIO_G7_IRQ_TO_INTC2_19 BIT(1)
+#define GPIO_G7_IRQ_TO_INTC2_20 BIT(2)
+#define GPIO_G7_IRQ_TO_SIO BIT(3)
+#define GPIO_G7_IRQ_TARGET_RESET_TOLERANCE BIT(6)
+#define GPIO_G7_IRQ_TARGET_W_PROTECT BIT(7)
+
+static int
+aspeed_gpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset);
+ u32 dir = readl(addr);
+
+ dir &= ~GPIO_G7_DIR;
+ writel(dir, addr);
+
+ return 0;
+}
+
+static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset);
+ u32 data = readl(addr);
+
+ if (value)
+ data |= GPIO_G7_OUT_DATA;
+ else
+ data &= ~GPIO_G7_OUT_DATA;
+ writel(data, addr);
+ data |= GPIO_G7_DIR;
+ writel(data, addr);
+
+ return 0;
+}
+
+static int aspeed_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset);
+
+ return !!(readl(addr) & GPIO_G7_IN_DATA);
+}
+
+static int
+aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
+{
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset);
+ u32 data = readl(addr);
+
+ if (value)
+ data |= GPIO_G7_OUT_DATA;
+ else
+ data &= ~GPIO_G7_OUT_DATA;
+
+ writel(data, addr);
+
+ return 0;
+}
+
+static int aspeed_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr = priv->regs + GPIO_G7_CTRL_REG_OFFSET(offset);
+
+ if (readl(addr) & GPIO_G7_DIR)
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops aspeed_gpio_ops = {
+ .direction_input = aspeed_gpio_direction_input,
+ .direction_output = aspeed_gpio_direction_output,
+ .get_value = aspeed_gpio_get_value,
+ .set_value = aspeed_gpio_set_value,
+ .get_function = aspeed_gpio_get_function,
+};
+
+static int aspeed_gpio_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct aspeed_gpio_priv *priv = dev_get_priv(dev);
+
+ uc_priv->bank_name = dev->name;
+ ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count);
+ priv->regs = devfdt_get_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id aspeed_gpio_ids[] = {
+ { .compatible = "aspeed,ast2700-gpio", },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_aspeed) = {
+ .name = "gpio-aspeed",
+ .id = UCLASS_GPIO,
+ .of_match = aspeed_gpio_ids,
+ .ops = &aspeed_gpio_ops,
+ .probe = aspeed_gpio_probe,
+ .priv_auto = sizeof(struct aspeed_gpio_priv),
+};
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index cac6b32..28176e1 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -133,7 +133,10 @@
regs = (struct gpio_regs *)gpio_ports[port];
- val = (readl(®s->gpio_psr) >> gpio) & 0x01;
+ if ((readl(®s->gpio_dir) >> gpio) & 0x01)
+ val = (readl(®s->gpio_dr) >> gpio) & 0x01;
+ else
+ val = (readl(®s->gpio_psr) >> gpio) & 0x01;
return val;
}
@@ -210,7 +213,10 @@
static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
{
- return (readl(®s->gpio_psr) >> offset) & 0x01;
+ if ((readl(®s->gpio_dir) >> offset) & 0x01)
+ return (readl(®s->gpio_dr) >> offset) & 0x01;
+ else
+ return (readl(®s->gpio_psr) >> offset) & 0x01;
}
/* set GPIO pin 'gpio' as an input */
diff --git a/drivers/gpio/npcm_sgpio.c b/drivers/gpio/npcm_sgpio.c
new file mode 100644
index 0000000..6d73287
--- /dev/null
+++ b/drivers/gpio/npcm_sgpio.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corp.
+ */
+
+#include <dm.h>
+#include <asm/gpio.h>
+#include <linux/io.h>
+
+#define MAX_NR_HW_SGPIO 64
+#define NPCM_CLK_MHZ 8000000
+
+#define NPCM_IOXCFG1 0x2A
+
+#define NPCM_IOXCTS 0x28
+#define NPCM_IOXCTS_IOXIF_EN BIT(7)
+#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1)
+#define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2)
+
+#define NPCM_IOXCFG2 0x2B
+#define NPCM_IOXCFG2_PORT GENMASK(3, 0)
+
+#define GPIO_BANK(x) ((x) / 8)
+#define GPIO_BIT(x) ((x) % 8)
+
+struct npcm_sgpio_priv {
+ void __iomem *base;
+ u32 nin_sgpio;
+ u32 nout_sgpio;
+ u32 in_port;
+ u32 out_port;
+};
+
+struct npcm_sgpio_bank {
+ u8 rdata_reg;
+ u8 wdata_reg;
+ u8 event_config;
+ u8 event_status;
+};
+
+enum npcm_sgpio_reg {
+ READ_DATA,
+ WRITE_DATA,
+ EVENT_CFG,
+ EVENT_STS,
+};
+
+static const struct npcm_sgpio_bank npcm_sgpio_banks[] = {
+ {
+ .wdata_reg = 0x00,
+ .rdata_reg = 0x08,
+ .event_config = 0x10,
+ .event_status = 0x20,
+ },
+ {
+ .wdata_reg = 0x01,
+ .rdata_reg = 0x09,
+ .event_config = 0x12,
+ .event_status = 0x21,
+ },
+ {
+ .wdata_reg = 0x02,
+ .rdata_reg = 0x0a,
+ .event_config = 0x14,
+ .event_status = 0x22,
+ },
+ {
+ .wdata_reg = 0x03,
+ .rdata_reg = 0x0b,
+ .event_config = 0x16,
+ .event_status = 0x23,
+ },
+ {
+ .wdata_reg = 0x04,
+ .rdata_reg = 0x0c,
+ .event_config = 0x18,
+ .event_status = 0x24,
+ },
+ {
+ .wdata_reg = 0x05,
+ .rdata_reg = 0x0d,
+ .event_config = 0x1a,
+ .event_status = 0x25,
+ },
+ {
+ .wdata_reg = 0x06,
+ .rdata_reg = 0x0e,
+ .event_config = 0x1c,
+ .event_status = 0x26,
+ },
+ {
+ .wdata_reg = 0x07,
+ .rdata_reg = 0x0f,
+ .event_config = 0x1e,
+ .event_status = 0x27,
+ },
+};
+
+static void __iomem *bank_reg(struct npcm_sgpio_priv *gpio,
+ const struct npcm_sgpio_bank *bank,
+ const enum npcm_sgpio_reg reg)
+{
+ switch (reg) {
+ case READ_DATA:
+ return gpio->base + bank->rdata_reg;
+ case WRITE_DATA:
+ return gpio->base + bank->wdata_reg;
+ case EVENT_CFG:
+ return gpio->base + bank->event_config;
+ case EVENT_STS:
+ return gpio->base + bank->event_status;
+ default:
+ /* actually if code runs to here, it's an error case */
+ printf("Getting here is an error condition\n");
+ return NULL;
+ }
+}
+
+static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset)
+{
+ unsigned int bank = GPIO_BANK(offset);
+
+ return &npcm_sgpio_banks[bank];
+}
+
+static int npcm_sgpio_direction_input(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+
+ if (offset < priv->nout_sgpio) {
+ printf("Error: Offset %d is a output pin\n", offset);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int npcm_sgpio_direction_output(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+ const struct npcm_sgpio_bank *bank = offset_to_bank(offset);
+ void __iomem *addr;
+ u8 reg = 0;
+
+ if (offset >= priv->nout_sgpio) {
+ printf("Error: Offset %d is a input pin\n", offset);
+ return -EINVAL;
+ }
+
+ addr = bank_reg(priv, bank, WRITE_DATA);
+ reg = ioread8(addr);
+
+ if (value)
+ reg |= BIT(GPIO_BIT(offset));
+ else
+ reg &= ~BIT(GPIO_BIT(offset));
+
+ iowrite8(reg, addr);
+
+ return 0;
+}
+
+static int npcm_sgpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+ const struct npcm_sgpio_bank *bank;
+ void __iomem *addr;
+ u8 reg;
+
+ if (offset < priv->nout_sgpio) {
+ bank = offset_to_bank(offset);
+ addr = bank_reg(priv, bank, WRITE_DATA);
+ } else {
+ offset -= priv->nout_sgpio;
+ bank = offset_to_bank(offset);
+ addr = bank_reg(priv, bank, READ_DATA);
+ }
+
+ reg = ioread8(addr);
+
+ return !!(reg & BIT(GPIO_BIT(offset)));
+}
+
+static int npcm_sgpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ return npcm_sgpio_direction_output(dev, offset, value);
+}
+
+static int npcm_sgpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+
+ if (offset < priv->nout_sgpio)
+ return GPIOF_OUTPUT;
+
+ return GPIOF_INPUT;
+}
+
+static void npcm_sgpio_setup_enable(struct npcm_sgpio_priv *gpio, bool enable)
+{
+ u8 reg;
+
+ reg = ioread8(gpio->base + NPCM_IOXCTS);
+ reg = (reg & ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC;
+
+ if (enable)
+ reg |= NPCM_IOXCTS_IOXIF_EN;
+ else
+ reg &= ~NPCM_IOXCTS_IOXIF_EN;
+
+ iowrite8(reg, gpio->base + NPCM_IOXCTS);
+}
+
+static int npcm_sgpio_init_port(struct udevice *dev)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+ u8 in_port, out_port, set_port, reg, set_clk;
+
+ npcm_sgpio_setup_enable(priv, false);
+
+ in_port = GPIO_BANK(priv->nin_sgpio);
+ if (GPIO_BIT(priv->nin_sgpio) > 0)
+ in_port += 1;
+
+ out_port = GPIO_BANK(priv->nout_sgpio);
+ if (GPIO_BIT(priv->nout_sgpio) > 0)
+ out_port += 1;
+
+ priv->in_port = in_port;
+ priv->out_port = out_port;
+
+ set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 | (in_port & NPCM_IOXCFG2_PORT);
+ set_clk = 0x07;
+
+ iowrite8(set_port, priv->base + NPCM_IOXCFG2);
+ iowrite8(set_clk, priv->base + NPCM_IOXCFG1);
+
+ reg = ioread8(priv->base + NPCM_IOXCFG2);
+
+ return reg == set_port ? 0 : -EINVAL;
+}
+
+static const struct dm_gpio_ops npcm_sgpio_ops = {
+ .direction_input = npcm_sgpio_direction_input,
+ .direction_output = npcm_sgpio_direction_output,
+ .get_value = npcm_sgpio_get_value,
+ .set_value = npcm_sgpio_set_value,
+ .get_function = npcm_sgpio_get_function,
+};
+
+static int npcm_sgpio_probe(struct udevice *dev)
+{
+ struct npcm_sgpio_priv *priv = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ int rc;
+
+ priv->base = dev_read_addr_ptr(dev);
+ ofnode_read_u32(dev_ofnode(dev), "nuvoton,input-ngpios", &priv->nin_sgpio);
+ ofnode_read_u32(dev_ofnode(dev), "nuvoton,output-ngpios", &priv->nout_sgpio);
+
+ if (priv->nin_sgpio > MAX_NR_HW_SGPIO || priv->nout_sgpio > MAX_NR_HW_SGPIO)
+ return -EINVAL;
+
+ rc = npcm_sgpio_init_port(dev);
+ if (rc < 0)
+ return rc;
+
+ uc_priv->gpio_count = priv->nin_sgpio + priv->nout_sgpio;
+ uc_priv->bank_name = dev->name;
+
+ npcm_sgpio_setup_enable(priv, true);
+
+ return 0;
+}
+
+static const struct udevice_id npcm_sgpio_match[] = {
+ { .compatible = "nuvoton,npcm845-sgpio" },
+ { .compatible = "nuvoton,npcm750-sgpio" },
+ { }
+};
+
+U_BOOT_DRIVER(npcm_sgpio) = {
+ .name = "npcm_sgpio",
+ .id = UCLASS_GPIO,
+ .of_match = npcm_sgpio_match,
+ .probe = npcm_sgpio_probe,
+ .priv_auto = sizeof(struct npcm_sgpio_priv),
+ .ops = &npcm_sgpio_ops,
+};
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 7c43a55..cccd450 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -33,137 +33,8 @@
return i2c_adap_p;
}
-#if !defined(CFG_SYS_I2C_DIRECT_BUS)
-struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
- CFG_SYS_I2C_BUSES;
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-/*
- * i2c_mux_set()
- * -------------
- *
- * This turns on the given channel on I2C multiplexer chip connected to
- * a given I2C adapter directly or via other multiplexers. In the latter
- * case the entire multiplexer chain must be initialized first starting
- * with the one connected directly to the adapter. When disabling a chain
- * muxes must be programmed in reverse order, starting with the one
- * farthest from the adapter.
- *
- * mux_id is the multiplexer chip type from defined in i2c.h. So far only
- * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT
- * supported (anybody uses them?)
- */
-
-static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
- int channel)
-{
- uint8_t buf;
- int ret;
-
- /* channel < 0 - turn off the mux */
- if (channel < 0) {
- buf = 0;
- ret = adap->write(adap, chip, 0, 0, &buf, 1);
- if (ret)
- printf("%s: Could not turn off the mux.\n", __func__);
- return ret;
- }
-
- switch (mux_id) {
- case I2C_MUX_PCA9540_ID:
- case I2C_MUX_PCA9542_ID:
- if (channel > 1)
- return -1;
- buf = (uint8_t)((channel & 0x01) | (1 << 2));
- break;
- case I2C_MUX_PCA9544_ID:
- if (channel > 3)
- return -1;
- buf = (uint8_t)((channel & 0x03) | (1 << 2));
- break;
- case I2C_MUX_PCA9547_ID:
- if (channel > 7)
- return -1;
- buf = (uint8_t)((channel & 0x07) | (1 << 3));
- break;
- case I2C_MUX_PCA9548_ID:
- if (channel > 7)
- return -1;
- buf = (uint8_t)(0x01 << channel);
- break;
- default:
- printf("%s: wrong mux id: %d\n", __func__, mux_id);
- return -1;
- }
-
- ret = adap->write(adap, chip, 0, 0, &buf, 1);
- if (ret)
- printf("%s: could not set mux: id: %d chip: %x channel: %d\n",
- __func__, mux_id, chip, channel);
- return ret;
-}
-
-static int i2c_mux_set_all(void)
-{
- struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
- int i;
-
- /* Connect requested bus if behind muxes */
- if (i2c_bus_tmp->next_hop[0].chip != 0) {
- /* Set all muxes along the path to that bus */
- for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) {
- int ret;
-
- if (i2c_bus_tmp->next_hop[i].chip == 0)
- break;
-
- ret = i2c_mux_set(I2C_ADAP,
- i2c_bus_tmp->next_hop[i].mux.id,
- i2c_bus_tmp->next_hop[i].chip,
- i2c_bus_tmp->next_hop[i].channel);
- if (ret != 0)
- return ret;
- }
- }
- return 0;
-}
-
-static int i2c_mux_disconnect_all(void)
-{
- struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
- int i;
- uint8_t buf = 0;
-
- if (I2C_ADAP->init_done == 0)
- return 0;
-
- /* Disconnect current bus (turn off muxes if any) */
- if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
- (I2C_ADAP->init_done != 0)) {
- i = CFG_SYS_I2C_MAX_HOPS;
- do {
- uint8_t chip;
- int ret;
-
- chip = i2c_bus_tmp->next_hop[--i].chip;
- if (chip == 0)
- continue;
-
- ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
- if (ret != 0) {
- printf("i2c: mux disconnect error\n");
- return ret;
- }
- } while (i > 0);
- }
-
- return 0;
-}
-#endif
-
/*
* i2c_init_bus():
* ---------------
@@ -237,11 +108,6 @@
if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
return 0;
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- if (bus >= CFG_SYS_NUM_I2C_BUSES)
- return -1;
-#endif
-
max = ll_entry_count(struct i2c_adapter, i2c);
if (I2C_ADAPTER(bus) >= max) {
printf("Error, wrong i2c adapter %d max %d possible\n",
@@ -249,17 +115,10 @@
return -2;
}
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- i2c_mux_disconnect_all();
-#endif
-
gd->cur_i2c_bus = bus;
if (I2C_ADAP->init_done == 0)
i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- i2c_mux_set_all();
-#endif
return 0;
}
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 84c0050..2f3cb59 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -620,6 +620,7 @@
__attribute__((weak, alias("__enable_i2c_clk")));
#if !CONFIG_IS_ENABLED(DM_I2C)
+
/*
* Read data from I2C device
*
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 89ddf82..79f7a32 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -107,16 +107,13 @@
/*-----------------------------------------------------------------------
* Local functions
*/
-#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
static void send_reset (void);
-#endif
static void send_start (void);
static void send_stop (void);
static void send_ack (int);
static int write_byte (uchar byte);
static uchar read_byte (int);
-#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
/*-----------------------------------------------------------------------
* Send a reset sequence consisting of 9 clocks with the data signal high
* to clock any confused device back into an idle state. Also send a
@@ -144,7 +141,6 @@
send_stop();
I2C_TRISTATE;
}
-#endif
/*-----------------------------------------------------------------------
* START: High -> Low on SDA while SCL is High
@@ -277,12 +273,6 @@
*/
static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
-#if defined(CONFIG_SYS_I2C_INIT_BOARD)
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
- i2c_init_board();
-#else
/*
* WARNING: Do NOT save speed in a static variable: if the
* I2C routines are called before RAM is initialized (to read
@@ -290,7 +280,6 @@
* system will crash.
*/
send_reset ();
-#endif
}
/*-----------------------------------------------------------------------
diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c
index 9327dea..611ac7c 100644
--- a/drivers/iommu/apple_dart.c
+++ b/drivers/iommu/apple_dart.c
@@ -70,7 +70,6 @@
struct apple_dart_priv {
void *base;
- struct lmb lmb;
u64 *l1, *l2;
int bypass, shift;
@@ -124,7 +123,7 @@
off = (phys_addr_t)addr - paddr;
psize = ALIGN(size + off, DART_PAGE_SIZE);
- dva = lmb_alloc(&priv->lmb, psize, DART_PAGE_SIZE);
+ dva = lmb_alloc(psize, DART_PAGE_SIZE);
idx = dva / DART_PAGE_SIZE;
for (i = 0; i < psize / DART_PAGE_SIZE; i++) {
@@ -160,7 +159,7 @@
(unsigned long)&priv->l2[idx + i]);
priv->flush_tlb(priv);
- lmb_free(&priv->lmb, dva, psize);
+ lmb_free(dva, psize);
}
static struct iommu_ops apple_dart_ops = {
@@ -213,8 +212,7 @@
priv->dvabase = DART_PAGE_SIZE;
priv->dvaend = SZ_4G - DART_PAGE_SIZE;
- lmb_init(&priv->lmb);
- lmb_add(&priv->lmb, priv->dvabase, priv->dvaend - priv->dvabase);
+ lmb_add(priv->dvabase, priv->dvaend - priv->dvabase);
/* Disable translations. */
for (sid = 0; sid < priv->nsid; sid++)
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 7b646d8..1b5a09b 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -381,6 +381,7 @@
static const struct udevice_id qcom_smmu500_ids[] = {
{ .compatible = "qcom,sdm845-smmu-500" },
+ { .compatible = "qcom,sc7280-smmu-500" },
{ .compatible = "qcom,smmu-500", },
{ /* sentinel */ }
};
diff --git a/drivers/iommu/sandbox_iommu.c b/drivers/iommu/sandbox_iommu.c
index e37976f..c5eefec 100644
--- a/drivers/iommu/sandbox_iommu.c
+++ b/drivers/iommu/sandbox_iommu.c
@@ -5,28 +5,20 @@
#include <dm.h>
#include <iommu.h>
-#include <lmb.h>
#include <asm/io.h>
+#include <asm/test.h>
#include <linux/sizes.h>
-#define IOMMU_PAGE_SIZE SZ_4K
-
-struct sandbox_iommu_priv {
- struct lmb lmb;
-};
-
static dma_addr_t sandbox_iommu_map(struct udevice *dev, void *addr,
size_t size)
{
- struct sandbox_iommu_priv *priv = dev_get_priv(dev);
phys_addr_t paddr, dva;
phys_size_t psize, off;
- paddr = ALIGN_DOWN(virt_to_phys(addr), IOMMU_PAGE_SIZE);
+ paddr = ALIGN_DOWN(virt_to_phys(addr), SANDBOX_IOMMU_PAGE_SIZE);
off = virt_to_phys(addr) - paddr;
- psize = ALIGN(size + off, IOMMU_PAGE_SIZE);
-
- dva = lmb_alloc(&priv->lmb, psize, IOMMU_PAGE_SIZE);
+ psize = ALIGN(size + off, SANDBOX_IOMMU_PAGE_SIZE);
+ dva = (phys_addr_t)SANDBOX_IOMMU_DVA_ADDR;
return dva + off;
}
@@ -34,15 +26,12 @@
static void sandbox_iommu_unmap(struct udevice *dev, dma_addr_t addr,
size_t size)
{
- struct sandbox_iommu_priv *priv = dev_get_priv(dev);
phys_addr_t dva;
phys_size_t psize;
- dva = ALIGN_DOWN(addr, IOMMU_PAGE_SIZE);
+ dva = ALIGN_DOWN(addr, SANDBOX_IOMMU_PAGE_SIZE);
psize = size + (addr - dva);
- psize = ALIGN(psize, IOMMU_PAGE_SIZE);
-
- lmb_free(&priv->lmb, dva, psize);
+ psize = ALIGN(psize, SANDBOX_IOMMU_PAGE_SIZE);
}
static struct iommu_ops sandbox_iommu_ops = {
@@ -50,16 +39,6 @@
.unmap = sandbox_iommu_unmap,
};
-static int sandbox_iommu_probe(struct udevice *dev)
-{
- struct sandbox_iommu_priv *priv = dev_get_priv(dev);
-
- lmb_init(&priv->lmb);
- lmb_add(&priv->lmb, 0x89abc000, SZ_16K);
-
- return 0;
-}
-
static const struct udevice_id sandbox_iommu_ids[] = {
{ .compatible = "sandbox,iommu" },
{ /* sentinel */ }
@@ -69,7 +48,5 @@
.name = "sandbox_iommu",
.id = UCLASS_IOMMU,
.of_match = sandbox_iommu_ids,
- .priv_auto = sizeof(struct sandbox_iommu_priv),
.ops = &sandbox_iommu_ops,
- .probe = sandbox_iommu_probe,
};
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index 3745504..b753419 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2020, 2023 NXP
+ * Copyright 2024 Mathieu Othacehe <othacehe@gnu.org>
*
*/
#include <hang.h>
#include <malloc.h>
+#include <memalign.h>
#include <asm/io.h>
#include <dm.h>
#include <asm/mach-imx/ele_api.h>
@@ -527,6 +529,81 @@
return ret;
}
+int ele_derive_huk(u8 *key, size_t key_size, u8 *seed, size_t seed_size)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ struct ele_msg msg;
+ int msg_size = sizeof(struct ele_msg);
+ u8 *seed_aligned, *key_aligned;
+ int ret, size;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ if (key_size != 16 && key_size != 32) {
+ printf("key size can only be 16 or 32\n");
+ return -EINVAL;
+ }
+
+ if (seed_size >= (1U << 16) - 1) {
+ printf("seed size is too large\n");
+ return -EINVAL;
+ }
+
+ seed_aligned = memalign(ARCH_DMA_MINALIGN, seed_size);
+ if (!seed_aligned) {
+ printf("failed to alloc memory\n");
+ return -EINVAL;
+ }
+ memcpy(seed_aligned, seed, seed_size);
+
+ key_aligned = memalign(ARCH_DMA_MINALIGN, key_size);
+ if (!key_aligned) {
+ printf("failed to alloc memory\n");
+ ret = -EINVAL;
+ goto ret_seed;
+ }
+
+ size = ALIGN(seed_size, ARCH_DMA_MINALIGN);
+ flush_dcache_range((ulong)seed_aligned,
+ (ulong)seed_aligned + size);
+
+ size = ALIGN(key_size, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range((ulong)key_aligned,
+ (ulong)key_aligned + size);
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 7;
+ msg.command = ELE_CMD_DERIVE_KEY;
+ msg.data[0] = upper_32_bits((ulong)key_aligned);
+ msg.data[1] = lower_32_bits((ulong)key_aligned);
+ msg.data[2] = upper_32_bits((ulong)seed_aligned);
+ msg.data[3] = lower_32_bits((ulong)seed_aligned);
+ msg.data[4] = seed_size << 16 | key_size;
+ msg.data[5] = compute_crc(&msg);
+
+ ret = misc_call(dev, false, &msg, msg_size, &msg, msg_size);
+ if (ret) {
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+ goto ret_key;
+ }
+
+ invalidate_dcache_range((ulong)key_aligned,
+ (ulong)key_aligned + size);
+ memcpy(key, key_aligned, key_size);
+
+ret_key:
+ free(key_aligned);
+ret_seed:
+ free(seed_aligned);
+
+ return ret;
+}
+
int ele_commit(u16 fuse_id, u32 *response, u32 *info_type)
{
struct udevice *dev = gd->arch.ele_dev;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 72c3fb6..235c477 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -60,6 +60,7 @@
obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence6.o
obj-$(CONFIG_MMC_SDHCI_CV1800B) += cv1800b_sdhci.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
index 54a2ba4..1af5ec0 100644
--- a/drivers/mmc/ca_dw_mmc.c
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -86,7 +86,7 @@
clk_div = 1;
}
- return SD_SCLK_MAX / clk_div / (host->div + 1);
+ return SD_SCLK_MAX / clk_div;
}
static int ca_dwmmc_of_to_plat(struct udevice *dev)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index f4ecd74..8551eac 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -20,6 +20,47 @@
#define PAGE_SIZE 4096
+/* Internal DMA Controller (IDMAC) descriptor for 32-bit addressing mode */
+struct dwmci_idmac32 {
+ u32 des0; /* Control descriptor */
+ u32 des1; /* Buffer size */
+ u32 des2; /* Buffer physical address */
+ u32 des3; /* Next descriptor physical address */
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Internal DMA Controller (IDMAC) descriptor for 64-bit addressing mode */
+struct dwmci_idmac64 {
+ u32 des0; /* Control descriptor */
+ u32 des1; /* Reserved */
+ u32 des2; /* Buffer sizes */
+ u32 des3; /* Reserved */
+ u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */
+ u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */
+ u32 des6; /* Lower 32-bits of Next Descriptor Address */
+ u32 des7; /* Upper 32-bits of Next Descriptor Address */
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Register offsets for DW MMC blocks with 32-bit IDMAC */
+static const struct dwmci_idmac_regs dwmci_idmac_regs32 = {
+ .dbaddrl = DWMCI_DBADDR,
+ .idsts = DWMCI_IDSTS,
+ .idinten = DWMCI_IDINTEN,
+ .dscaddrl = DWMCI_DSCADDR,
+ .bufaddrl = DWMCI_BUFADDR,
+};
+
+/* Register offsets for DW MMC blocks with 64-bit IDMAC */
+static const struct dwmci_idmac_regs dwmci_idmac_regs64 = {
+ .dbaddrl = DWMCI_DBADDRL,
+ .dbaddru = DWMCI_DBADDRU,
+ .idsts = DWMCI_IDSTS64,
+ .idinten = DWMCI_IDINTEN64,
+ .dscaddrl = DWMCI_DSCADDRL,
+ .dscaddru = DWMCI_DSCADDRU,
+ .bufaddrl = DWMCI_BUFADDRL,
+ .bufaddru = DWMCI_BUFADDRU,
+};
+
static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
unsigned long timeout = 1000;
@@ -35,57 +76,98 @@
return 0;
}
-static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
- u32 desc0, u32 desc1, u32 desc2)
+static void dwmci_set_idma_desc32(struct dwmci_idmac32 *desc, u32 control,
+ u32 buf_size, u32 buf_addr)
{
- struct dwmci_idmac *desc = idmac;
+ phys_addr_t desc_phys = virt_to_phys(desc);
+ u32 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac32);
- desc->flags = desc0;
- desc->cnt = desc1;
- desc->addr = desc2;
- desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
+ desc->des0 = control;
+ desc->des1 = buf_size;
+ desc->des2 = buf_addr;
+ desc->des3 = next_desc_phys;
}
-static void dwmci_prepare_data(struct dwmci_host *host,
- struct mmc_data *data,
- struct dwmci_idmac *cur_idmac,
- void *bounce_buffer)
+static void dwmci_set_idma_desc64(struct dwmci_idmac64 *desc, u32 control,
+ u32 buf_size, u64 buf_addr)
{
- unsigned long ctrl;
- unsigned int i = 0, flags, cnt, blk_cnt;
- ulong data_start, data_end;
-
- blk_cnt = data->blocks;
+ phys_addr_t desc_phys = virt_to_phys(desc);
+ u64 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac64);
- dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+ desc->des0 = control;
+ desc->des1 = 0;
+ desc->des2 = buf_size;
+ desc->des3 = 0;
+ desc->des4 = buf_addr & 0xffffffff;
+ desc->des5 = buf_addr >> 32;
+ desc->des6 = next_desc_phys & 0xffffffff;
+ desc->des7 = next_desc_phys >> 32;
+}
- /* Clear IDMAC interrupt */
- dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
+static void dwmci_prepare_desc(struct dwmci_host *host, struct mmc_data *data,
+ void *cur_idmac, void *bounce_buffer)
+{
+ struct dwmci_idmac32 *desc32 = cur_idmac;
+ struct dwmci_idmac64 *desc64 = cur_idmac;
+ ulong data_start, data_end;
+ unsigned int blk_cnt, i;
data_start = (ulong)cur_idmac;
- dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
+ blk_cnt = data->blocks;
- do {
- flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
- flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
+ for (i = 0;; i++) {
+ phys_addr_t buf_phys = virt_to_phys(bounce_buffer);
+ unsigned int flags, cnt;
+
+ flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH;
+ if (i == 0)
+ flags |= DWMCI_IDMAC_FS;
if (blk_cnt <= 8) {
flags |= DWMCI_IDMAC_LD;
cnt = data->blocksize * blk_cnt;
- } else
+ } else {
cnt = data->blocksize * 8;
+ }
- dwmci_set_idma_desc(cur_idmac, flags, cnt,
- (ulong)bounce_buffer + (i * PAGE_SIZE));
+ if (host->dma_64bit_address) {
+ dwmci_set_idma_desc64(desc64, flags, cnt,
+ buf_phys + i * PAGE_SIZE);
+ desc64++;
+ } else {
+ dwmci_set_idma_desc32(desc32, flags, cnt,
+ buf_phys + i * PAGE_SIZE);
+ desc32++;
+ }
- cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- i++;
- } while(1);
+ }
- data_end = (ulong)cur_idmac;
+ if (host->dma_64bit_address)
+ data_end = (ulong)desc64;
+ else
+ data_end = (ulong)desc32;
flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
+}
+
+static void dwmci_prepare_data(struct dwmci_host *host, struct mmc_data *data,
+ void *cur_idmac, void *bounce_buffer)
+{
+ const u32 idmacl = virt_to_phys(cur_idmac) & 0xffffffff;
+ const u32 idmacu = (u64)virt_to_phys(cur_idmac) >> 32;
+ unsigned long ctrl;
+
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+
+ /* Clear IDMAC interrupt */
+ dwmci_writel(host, host->regs->idsts, 0xffffffff);
+
+ dwmci_writel(host, host->regs->dbaddrl, idmacl);
+ if (host->dma_64bit_address)
+ dwmci_writel(host, host->regs->dbaddru, idmacu);
+
+ dwmci_prepare_desc(host, data, cur_idmac, bounce_buffer);
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
@@ -132,90 +214,86 @@
return timeout;
}
-static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+static int dwmci_data_transfer_fifo(struct dwmci_host *host,
+ struct mmc_data *data, u32 mask)
{
- struct mmc *mmc = host->mmc;
+ const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
+ const u32 int_tx = mask & DWMCI_INTMSK_TXDR;
int ret = 0;
- u32 timeout, mask, size, i, len = 0;
- u32 *buf = NULL;
- ulong start = get_timer(0);
- u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
- RX_WMARK_SHIFT) + 1) * 2;
+ u32 len = 0, size, i;
+ u32 *buf;
- size = data->blocksize * data->blocks;
+ size = (data->blocksize * data->blocks) / 4;
+ if (!host->fifo_mode || !size)
+ return 0;
+
if (data->flags == MMC_DATA_READ)
buf = (unsigned int *)data->dest;
else
buf = (unsigned int *)data->src;
- timeout = dwmci_get_timeout(mmc, size);
+ if (data->flags == MMC_DATA_READ && int_rx) {
+ dwmci_writel(host, DWMCI_RINTSTS, int_rx);
+ while (size) {
+ ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, &len);
+ if (ret < 0)
+ break;
+
+ len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK;
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ *buf++ = dwmci_readl(host, DWMCI_DATA);
+ size = size > len ? (size - len) : 0;
+ }
+ } else if (data->flags == MMC_DATA_WRITE && int_tx) {
+ while (size) {
+ ret = dwmci_fifo_ready(host, DWMCI_FIFO_FULL, &len);
+ if (ret < 0)
+ break;
+
+ len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ dwmci_writel(host, DWMCI_DATA, *buf++);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR);
+ }
- size /= 4;
+ return ret;
+}
+
+static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+{
+ struct mmc *mmc = host->mmc;
+ int ret = 0;
+ u32 timeout, mask, size;
+ ulong start = get_timer(0);
+
+ size = data->blocksize * data->blocks;
+ timeout = dwmci_get_timeout(mmc, size);
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
- /* Error during data transfer. */
+ /* Error during data transfer */
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
debug("%s: DATA ERROR!\n", __func__);
ret = -EINVAL;
break;
}
- if (host->fifo_mode && size) {
- len = 0;
- if (data->flags == MMC_DATA_READ &&
- (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
- dwmci_writel(host, DWMCI_RINTSTS,
- mask & (DWMCI_INTMSK_RXDR |
- DWMCI_INTMSK_DTO));
- while (size) {
- ret = dwmci_fifo_ready(host,
- DWMCI_FIFO_EMPTY,
- &len);
- if (ret < 0)
- break;
+ ret = dwmci_data_transfer_fifo(host, data, mask);
- len = (len >> DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK;
- len = min(size, len);
- for (i = 0; i < len; i++)
- *buf++ =
- dwmci_readl(host, DWMCI_DATA);
- size = size > len ? (size - len) : 0;
- }
- } else if (data->flags == MMC_DATA_WRITE &&
- (mask & DWMCI_INTMSK_TXDR)) {
- while (size) {
- ret = dwmci_fifo_ready(host,
- DWMCI_FIFO_FULL,
- &len);
- if (ret < 0)
- break;
-
- len = fifo_depth - ((len >>
- DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK);
- len = min(size, len);
- for (i = 0; i < len; i++)
- dwmci_writel(host, DWMCI_DATA,
- *buf++);
- size = size > len ? (size - len) : 0;
- }
- dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_TXDR);
- }
- }
-
- /* Data arrived correctly. */
+ /* Data arrived correctly */
if (mask & DWMCI_INTMSK_DTO) {
ret = 0;
break;
}
- /* Check for timeout. */
+ /* Check for timeout */
if (get_timer(start) > timeout) {
- debug("%s: Timeout waiting for data!\n",
- __func__);
+ debug("%s: Timeout waiting for data!\n", __func__);
ret = -ETIMEDOUT;
break;
}
@@ -223,11 +301,38 @@
dwmci_writel(host, DWMCI_RINTSTS, mask);
+ return ret;
+}
+
+static int dwmci_dma_transfer(struct dwmci_host *host, uint flags,
+ struct bounce_buffer *bbstate)
+{
+ int ret;
+ u32 mask, ctrl;
+
+ if (flags == MMC_DATA_READ)
+ mask = DWMCI_IDINTEN_RI;
+ else
+ mask = DWMCI_IDINTEN_TI;
+
+ ret = wait_for_bit_le32(host->ioaddr + host->regs->idsts, mask, true,
+ 1000, false);
+ if (ret)
+ debug("%s: DWMCI_IDINTEN mask 0x%x timeout\n", __func__, mask);
+
+ /* Clear interrupts */
+ dwmci_writel(host, host->regs->idsts, DWMCI_IDINTEN_MASK);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~DWMCI_DMA_EN;
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ bounce_buffer_stop(bbstate);
return ret;
}
static int dwmci_set_transfer_mode(struct dwmci_host *host,
- struct mmc_data *data)
+ struct mmc_data *data)
{
unsigned long mode;
@@ -238,33 +343,30 @@
return mode;
}
-#ifdef CONFIG_DM_MMC
-static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static void dwmci_wait_while_busy(struct dwmci_host *host, struct mmc_cmd *cmd)
{
-#endif
- struct dwmci_host *host = mmc->priv;
- ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
- data ? DIV_ROUND_UP(data->blocks, 8) : 0);
- int ret = 0, flags = 0, i;
- unsigned int timeout = 500;
- u32 retry = 100000;
- u32 mask, ctrl;
- ulong start = get_timer(0);
- struct bounce_buffer bbstate;
+ unsigned int timeout = 500; /* msec */
+ ulong start;
+ start = get_timer(0);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (get_timer(start) > timeout) {
- debug("%s: Timeout on data busy, continue anyway\n", __func__);
+ debug("%s: Timeout on data busy, continue anyway\n",
+ __func__);
break;
}
}
+}
+
+static int dwmci_send_cmd_common(struct dwmci_host *host, struct mmc_cmd *cmd,
+ struct mmc_data *data, void *cur_idmac)
+{
+ int ret, flags = 0, i;
+ u32 retry = 100000;
+ u32 mask;
+ struct bounce_buffer bbstate;
+ dwmci_wait_while_busy(host, cmd);
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
if (data) {
@@ -276,12 +378,12 @@
} else {
if (data->flags == MMC_DATA_READ) {
ret = bounce_buffer_start(&bbstate,
- (void*)data->dest,
+ (void *)data->dest,
data->blocksize *
data->blocks, GEN_BB_WRITE);
} else {
ret = bounce_buffer_start(&bbstate,
- (void*)data->src,
+ (void *)data->src,
data->blocksize *
data->blocks, GEN_BB_READ);
}
@@ -316,9 +418,9 @@
if (cmd->resp_type & MMC_RSP_CRC)
flags |= DWMCI_CMD_CHECK_CRC;
- flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
+ flags |= cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG;
- debug("Sending CMD%d\n",cmd->cmdidx);
+ debug("Sending CMD%d\n", cmd->cmdidx);
dwmci_writel(host, DWMCI_CMD, flags);
@@ -332,7 +434,7 @@
}
if (i == retry) {
- debug("%s: Timeout.\n", __func__);
+ debug("%s: Timeout\n", __func__);
return -ETIMEDOUT;
}
@@ -345,14 +447,14 @@
* below shall be debug(). eMMC cards also do not favor
* CMD8, please keep that in mind.
*/
- debug("%s: Response Timeout.\n", __func__);
+ debug("%s: Response Timeout\n", __func__);
return -ETIMEDOUT;
} else if (mask & DWMCI_INTMSK_RE) {
- debug("%s: Response Error.\n", __func__);
+ debug("%s: Response Error\n", __func__);
return -EIO;
} else if ((cmd->resp_type & MMC_RSP_CRC) &&
(mask & DWMCI_INTMSK_RCRC)) {
- debug("%s: Response CRC Error.\n", __func__);
+ debug("%s: Response CRC Error\n", __func__);
return -EIO;
}
@@ -369,26 +471,8 @@
if (data) {
ret = dwmci_data_transfer(host, data);
-
- /* only dma mode need it */
- if (!host->fifo_mode) {
- if (data->flags == MMC_DATA_READ)
- mask = DWMCI_IDINTEN_RI;
- else
- mask = DWMCI_IDINTEN_TI;
- ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
- mask, true, 1000, false);
- if (ret)
- debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
- __func__, mask);
- /* clear interrupts */
- dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
-
- ctrl = dwmci_readl(host, DWMCI_CTRL);
- ctrl &= ~(DWMCI_DMA_EN);
- dwmci_writel(host, DWMCI_CTRL, ctrl);
- bounce_buffer_stop(&bbstate);
- }
+ if (!host->fifo_mode)
+ ret = dwmci_dma_transfer(host, data->flags, &bbstate);
}
udelay(100);
@@ -396,40 +480,39 @@
return ret;
}
-static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+#ifdef CONFIG_DM_MMC
+static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
- u32 div, status;
- int timeout = 10000;
- unsigned long sclk;
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+#endif
+ struct dwmci_host *host = mmc->priv;
+ const size_t buf_size = data ? DIV_ROUND_UP(data->blocks, 8) : 0;
- if ((freq == host->clock) || (freq == 0))
- return 0;
- /*
- * If host->get_mmc_clk isn't defined,
- * then assume that host->bus_hz is source clock value.
- * host->bus_hz should be set by user.
- */
- if (host->get_mmc_clk)
- sclk = host->get_mmc_clk(host, freq);
- else if (host->bus_hz)
- sclk = host->bus_hz;
- else {
- debug("%s: Didn't get source clock value.\n", __func__);
- return -EINVAL;
+ if (host->dma_64bit_address) {
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac64, idmac, buf_size);
+ return dwmci_send_cmd_common(host, cmd, data, idmac);
+ } else {
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac32, idmac, buf_size);
+ return dwmci_send_cmd_common(host, cmd, data, idmac);
}
-
- if (sclk == freq)
- div = 0; /* bypass mode */
- else
- div = DIV_ROUND_UP(sclk, 2 * freq);
+}
- dwmci_writel(host, DWMCI_CLKENA, 0);
- dwmci_writel(host, DWMCI_CLKSRC, 0);
+static int dwmci_control_clken(struct dwmci_host *host, bool on)
+{
+ const u32 val = on ? DWMCI_CLKEN_ENABLE | DWMCI_CLKEN_LOW_PWR : 0;
+ const u32 cmd_only_clk = DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK;
+ int timeout = 10000;
+ u32 status;
- dwmci_writel(host, DWMCI_CLKDIV, div);
- dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
- DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+ dwmci_writel(host, DWMCI_CLKENA, val);
+ /* Inform CIU */
+ dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_START | cmd_only_clk);
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- < 0) {
@@ -438,20 +521,62 @@
}
} while (status & DWMCI_CMD_START);
- dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
- DWMCI_CLKEN_LOW_PWR);
+ return 0;
+}
- dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
- DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+/*
+ * Update the clock divider.
+ *
+ * To prevent a clock glitch keep the clock stopped during the update of
+ * clock divider and clock source.
+ */
+static int dwmci_update_div(struct dwmci_host *host, u32 div)
+{
+ int ret;
- timeout = 10000;
- do {
- status = dwmci_readl(host, DWMCI_CMD);
- if (timeout-- < 0) {
- debug("%s: Timeout!\n", __func__);
- return -ETIMEDOUT;
- }
- } while (status & DWMCI_CMD_START);
+ /* Disable clock */
+ ret = dwmci_control_clken(host, false);
+ if (ret)
+ return ret;
+
+ /* Set clock to desired speed */
+ dwmci_writel(host, DWMCI_CLKDIV, div);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ /* Enable clock */
+ return dwmci_control_clken(host, true);
+}
+
+static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+{
+ u32 div;
+ unsigned long sclk;
+ int ret;
+
+ if (freq == host->clock || freq == 0)
+ return 0;
+
+ /*
+ * If host->get_mmc_clk isn't defined, then assume that host->bus_hz is
+ * source clock value. host->bus_hz should be set by user.
+ */
+ if (host->get_mmc_clk) {
+ sclk = host->get_mmc_clk(host, freq);
+ } else if (host->bus_hz) {
+ sclk = host->bus_hz;
+ } else {
+ debug("%s: Didn't get source clock value\n", __func__);
+ return -EINVAL;
+ }
+
+ if (sclk == freq)
+ div = 0; /* bypass mode */
+ else
+ div = DIV_ROUND_UP(sclk, 2 * freq);
+
+ ret = dwmci_update_div(host, div);
+ if (ret)
+ return ret;
host->clock = freq;
@@ -469,7 +594,7 @@
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
- debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
+ debug("Bus width = %d, clock: %d\n", mmc->bus_width, mmc->clock);
dwmci_setup_bus(host, mmc->clock);
switch (mmc->bus_width) {
@@ -524,6 +649,48 @@
return 0;
}
+static void dwmci_init_fifo(struct dwmci_host *host)
+{
+ u32 fifo_thr, fifoth_val;
+
+ if (!host->fifo_depth) {
+ u32 fifo_size;
+
+ /*
+ * Automatically detect FIFO depth from FIFOTH register.
+ * Power-on value of RX_WMark is FIFO_DEPTH-1.
+ */
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+ host->fifo_depth = fifo_size;
+ }
+
+ fifo_thr = host->fifo_depth / 2;
+ fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_thr - 1) | TX_WMARK(fifo_thr);
+ dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+}
+
+static void dwmci_init_dma(struct dwmci_host *host)
+{
+ int addr_config;
+
+ if (host->fifo_mode)
+ return;
+
+ addr_config = (dwmci_readl(host, DWMCI_HCON) >> 27) & 0x1;
+ if (addr_config == 1) {
+ host->dma_64bit_address = true;
+ host->regs = &dwmci_idmac_regs64;
+ debug("%s: IDMAC supports 64-bit address mode\n", __func__);
+ } else {
+ host->dma_64bit_address = false;
+ host->regs = &dwmci_idmac_regs32;
+ debug("%s: IDMAC supports 32-bit address mode\n", __func__);
+ }
+
+ dwmci_writel(host, host->regs->idinten, DWMCI_IDINTEN_MASK);
+}
+
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = mmc->priv;
@@ -541,30 +708,18 @@
/* Enumerate at 400KHz */
dwmci_setup_bus(host, mmc->cfg->f_min);
- dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
+ dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff);
dwmci_writel(host, DWMCI_INTMASK, 0);
- dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
+ dwmci_writel(host, DWMCI_TMOUT, 0xffffffff);
- dwmci_writel(host, DWMCI_IDINTEN, 0);
dwmci_writel(host, DWMCI_BMOD, 1);
-
- if (!host->fifoth_val) {
- uint32_t fifo_size;
-
- fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
- fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
- host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
- TX_WMARK(fifo_size / 2);
- }
- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
+ dwmci_init_fifo(host);
+ dwmci_init_dma(host);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
- if (!host->fifo_mode)
- dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
-
return 0;
}
@@ -590,7 +745,7 @@
#endif
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
- u32 max_clk, u32 min_clk)
+ u32 max_clk, u32 min_clk)
{
cfg->name = host->name;
#ifndef CONFIG_DM_MMC
@@ -626,7 +781,7 @@
dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
- if (host->mmc == NULL)
+ if (!host->mmc)
return -1;
return 0;
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index a51f762..c8bf89d 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -4,10 +4,9 @@
* Jaehoon Chung <jh80.chung@samsung.com>
*/
+#include <clk.h>
#include <dwmmc.h>
-#include <fdtdec.h>
#include <asm/global_data.h>
-#include <linux/libfdt.h>
#include <malloc.h>
#include <errno.h>
#include <asm/arch/dwmmc.h>
@@ -15,6 +14,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>
+#include <linux/err.h>
#include <linux/printk.h>
#define DWMMC_MAX_CH_NUM 4
@@ -23,6 +23,11 @@
#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
+#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
+
+/* Quirks */
+#define DWMCI_QUIRK_DISABLE_SMU BIT(0)
+
#ifdef CONFIG_DM_MMC
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,35 +38,117 @@
};
#endif
-/* Exynos implmentation specific drver private data */
+/* Chip specific data */
+struct exynos_dwmmc_variant {
+ u32 clksel; /* CLKSEL register offset */
+ u8 div; /* (optional) fixed clock divider value: 0..7 */
+ u32 quirks; /* quirk flags - see DWMCI_QUIRK_... */
+};
+
+/* Exynos implementation specific driver private data */
struct dwmci_exynos_priv_data {
#ifdef CONFIG_DM_MMC
struct dwmci_host host;
#endif
+ struct clk clk;
u32 sdr_timing;
+ u32 ddr_timing;
+ const struct exynos_dwmmc_variant *chip;
};
-/*
- * Function used as callback function to initialise the
- * CLKSEL register for every mmc channel.
- */
-static int exynos_dwmci_clksel(struct dwmci_host *host)
+static struct dwmci_exynos_priv_data *exynos_dwmmc_get_priv(
+ struct dwmci_host *host)
{
#ifdef CONFIG_DM_MMC
- struct dwmci_exynos_priv_data *priv =
- container_of(host, struct dwmci_exynos_priv_data, host);
+ return container_of(host, struct dwmci_exynos_priv_data, host);
#else
- struct dwmci_exynos_priv_data *priv = host->priv;
+ return host->priv;
#endif
- dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
+}
+
+/**
+ * exynos_dwmmc_get_sclk - Get source clock (SDCLKIN) rate
+ * @host: MMC controller object
+ * @rate: Will contain clock rate, Hz
+ *
+ * Return: 0 on success or negative value on error
+ */
+static int exynos_dwmmc_get_sclk(struct dwmci_host *host, unsigned long *rate)
+{
+#ifdef CONFIG_CPU_V7A
+ *rate = get_mmc_clk(host->dev_index);
+#else
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ *rate = clk_get_rate(&priv->clk);
+#endif
+
+ if (IS_ERR_VALUE(*rate))
+ return *rate;
return 0;
}
-unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
+/**
+ * exynos_dwmmc_set_sclk - Set source clock (SDCLKIN) rate
+ * @host: MMC controller object
+ * @rate: Desired clock rate, Hz
+ *
+ * Return: 0 on success or negative value on error
+ */
+static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate)
{
+ int err;
+
+#ifdef CONFIG_CPU_V7A
unsigned long sclk;
- int8_t clk_div;
+ unsigned int div;
+
+ err = exynos_dwmmc_get_sclk(host, &sclk);
+ if (err)
+ return err;
+
+ div = DIV_ROUND_UP(sclk, rate);
+ set_mmc_clk(host->dev_index, div);
+#else
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ err = clk_set_rate(&priv->clk, rate);
+ if (err < 0)
+ return err;
+#endif
+
+ return 0;
+}
+
+/* Configure CLKSEL register with chosen timing values */
+static int exynos_dwmci_clksel(struct dwmci_host *host)
+{
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+ u32 timing;
+
+ if (host->mmc->selected_mode == MMC_DDR_52)
+ timing = priv->ddr_timing;
+ else
+ timing = priv->sdr_timing;
+
+ dwmci_writel(host, priv->chip->clksel, timing);
+
+ return 0;
+}
+
+/**
+ * exynos_dwmmc_get_ciu_div - Get internal clock divider value
+ * @host: MMC controller object
+ *
+ * Returns: Divider value, in range of 1..8
+ */
+static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)
+{
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ if (priv->chip->div)
+ return priv->chip->div + 1;
/*
* Since SDCLKIN is divided inside controller by the DIVRATIO
@@ -69,22 +156,42 @@
* clock value to calculate the CLKDIV value.
* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
*/
- clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
- & DWMCI_DIVRATIO_MASK) + 1;
- sclk = get_mmc_clk(host->dev_index);
+ return ((dwmci_readl(host, priv->chip->clksel) >> DWMCI_DIVRATIO_BIT)
+ & DWMCI_DIVRATIO_MASK) + 1;
+}
- /*
- * Assume to know divider value.
- * When clock unit is broken, need to set "host->div"
- */
- return sclk / clk_div / (host->div + 1);
+static unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
+{
+ unsigned long sclk;
+ u8 clk_div;
+ int err;
+
+ /* Should be double rate for DDR mode */
+ if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
+ freq *= 2;
+
+ clk_div = exynos_dwmmc_get_ciu_div(host);
+ err = exynos_dwmmc_set_sclk(host, freq * clk_div);
+ if (err) {
+ printf("DWMMC%d: failed to set clock rate (%d); "
+ "continue anyway\n", host->dev_index, err);
+ }
+
+ err = exynos_dwmmc_get_sclk(host, &sclk);
+ if (err) {
+ printf("DWMMC%d: failed to get clock rate (%d)\n",
+ host->dev_index, err);
+ return 0;
+ }
+
+ return sclk / clk_div;
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
{
- struct dwmci_exynos_priv_data *priv = host->priv;
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
- if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+ if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) {
dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
dwmci_writel(host, EMMCP_SEND0, 0);
dwmci_writel(host, EMMCP_CTRL0,
@@ -94,73 +201,27 @@
MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
}
- /* Set to timing value at initial time */
if (priv->sdr_timing)
exynos_dwmci_clksel(host);
}
-static int exynos_dwmci_core_init(struct dwmci_host *host)
-{
- unsigned int div;
- unsigned long freq, sclk;
-
- if (host->bus_hz)
- freq = host->bus_hz;
- else
- freq = DWMMC_MAX_FREQ;
-
- /* request mmc clock vlaue of 52MHz. */
- sclk = get_mmc_clk(host->dev_index);
- div = DIV_ROUND_UP(sclk, freq);
- /* set the clock divisor for mmc */
- set_mmc_clk(host->dev_index, div);
-
- host->name = "EXYNOS DWMMC";
-#ifdef CONFIG_EXYNOS5420
- host->quirks = DWMCI_QUIRK_DISABLE_SMU;
-#endif
- host->board_init = exynos_dwmci_board_init;
-
- host->caps = MMC_MODE_DDR_52MHz;
- host->clksel = exynos_dwmci_clksel;
- host->get_mmc_clk = exynos_dwmci_get_clk;
-
-#ifndef CONFIG_DM_MMC
- /* Add the mmc channel to be registered with mmc core */
- if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
- printf("DWMMC%d registration failed\n", host->dev_index);
- return -1;
- }
-#endif
-
- return 0;
-}
-
-static int do_dwmci_init(struct dwmci_host *host)
+#ifdef CONFIG_DM_MMC
+static int exynos_dwmmc_of_to_plat(struct udevice *dev)
{
- int flag, err;
+ struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ u32 div, timing[2];
+ int err;
- flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
- err = exynos_pinmux_config(host->dev_id, flag);
- if (err) {
- printf("DWMMC%d not configure\n", host->dev_index);
- return err;
- }
+ priv->chip = (struct exynos_dwmmc_variant *)dev_get_driver_data(dev);
- return exynos_dwmci_core_init(host);
-}
+#ifdef CONFIG_CPU_V7A
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
-static int exynos_dwmci_get_config(const void *blob, int node,
- struct dwmci_host *host,
- struct dwmci_exynos_priv_data *priv)
-{
- int err = 0;
- u32 base, timing[3];
-
- /* Extract device id for each mmc channel */
+ /* Obtain device ID for current MMC channel */
host->dev_id = pinmux_decode_periph_id(blob, node);
-
- host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
+ host->dev_index = dev_read_u32_default(dev, "index", host->dev_id);
if (host->dev_index == host->dev_id)
host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
@@ -168,31 +229,34 @@
printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
return -EINVAL;
}
-
- /* Get the bus width from the device node (Default is 4bit buswidth) */
- host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
+#else
+ if (dev_read_bool(dev, "non-removable"))
+ host->dev_index = 0; /* eMMC */
+ else
+ host->dev_index = 2; /* SD card */
+#endif
- /* Set the base address from the device node */
- base = fdtdec_get_addr(blob, node, "reg");
- if (!base) {
+ host->ioaddr = dev_read_addr_ptr(dev);
+ if (!host->ioaddr) {
printf("DWMMC%d: Can't get base address\n", host->dev_index);
return -EINVAL;
}
- host->ioaddr = (void *)base;
+
+ if (priv->chip->div)
+ div = priv->chip->div;
+ else
+ div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0);
- /* Extract the timing info from the node */
- err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
+ err = dev_read_u32_array(dev, "samsung,dw-mshc-sdr-timing", timing, 2);
if (err) {
- printf("DWMMC%d: Can't get sdr-timings for devider\n",
- host->dev_index);
+ printf("DWMMC%d: Can't get sdr-timings\n", host->dev_index);
return -EINVAL;
}
-
- priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
- DWMCI_SET_DRV_CLK(timing[1]) |
- DWMCI_SET_DIV_RATIO(timing[2]));
+ priv->sdr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(div);
- /* sdr_timing didn't assigned anything, use the default value */
+ /* sdr_timing wasn't set, use the default value */
if (!priv->sdr_timing) {
if (host->dev_index == 0)
priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
@@ -200,35 +264,82 @@
priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
}
- host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
- host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
- host->div = fdtdec_get_int(blob, node, "div", 0);
+ err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2);
+ if (err) {
+ debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n",
+ host->dev_index);
+ priv->ddr_timing = priv->sdr_timing;
+ } else {
+ priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(div);
+ }
+
+ host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+ host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+ host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0);
return 0;
}
-#ifdef CONFIG_DM_MMC
static int exynos_dwmmc_probe(struct udevice *dev)
{
struct exynos_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ unsigned long freq;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
- priv);
+#ifndef CONFIG_CPU_V7A
+ err = clk_get_by_index(dev, 1, &priv->clk); /* ciu */
if (err)
return err;
- err = do_dwmci_init(host);
- if (err)
+#endif
+
+#ifdef CONFIG_CPU_V7A
+ int flag;
+
+ flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ err = exynos_pinmux_config(host->dev_id, flag);
+ if (err) {
+ printf("DWMMC%d not configure\n", host->dev_index);
return err;
+ }
+#endif
+ if (host->bus_hz)
+ freq = host->bus_hz;
+ else
+ freq = DWMMC_MAX_FREQ;
+
+ err = exynos_dwmmc_set_sclk(host, freq);
+ if (err) {
+ printf("DWMMC%d: failed to set clock rate on probe (%d); "
+ "continue anyway\n", host->dev_index, err);
+ }
+
+ host->name = dev->name;
+ host->board_init = exynos_dwmci_board_init;
+ host->caps = MMC_MODE_DDR_52MHz;
+ host->clksel = exynos_dwmci_clksel;
+ host->get_mmc_clk = exynos_dwmci_get_clk;
+
+#ifdef CONFIG_BLK
dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
host->mmc = &plat->mmc;
+#else
+ err = add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
+ if (err) {
+ printf("DWMMC%d registration failed\n", host->dev_index);
+ return err;
+ }
+#endif
+
host->mmc->priv = &priv->host;
- host->priv = dev;
upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
+ host->priv = dev;
return dwmci_probe(dev);
}
@@ -240,9 +351,34 @@
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct exynos_dwmmc_variant exynos4_drv_data = {
+ .clksel = DWMCI_CLKSEL,
+ .div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1,
+};
+
+static const struct exynos_dwmmc_variant exynos5_drv_data = {
+ .clksel = DWMCI_CLKSEL,
+#ifdef CONFIG_EXYNOS5420
+ .quirks = DWMCI_QUIRK_DISABLE_SMU,
+#endif
+};
+
+static const struct exynos_dwmmc_variant exynos7_smu_drv_data = {
+ .clksel = DWMCI_CLKSEL64,
+ .quirks = DWMCI_QUIRK_DISABLE_SMU,
+};
+
static const struct udevice_id exynos_dwmmc_ids[] = {
- { .compatible = "samsung,exynos4412-dw-mshc" },
- { .compatible = "samsung,exynos-dwmmc" },
+ {
+ .compatible = "samsung,exynos4412-dw-mshc",
+ .data = (ulong)&exynos4_drv_data,
+ }, {
+ .compatible = "samsung,exynos-dwmmc",
+ .data = (ulong)&exynos5_drv_data,
+ }, {
+ .compatible = "samsung,exynos7-dw-mshc-smu",
+ .data = (ulong)&exynos7_smu_drv_data,
+ },
{ }
};
@@ -250,9 +386,10 @@
.name = "exynos_dwmmc",
.id = UCLASS_MMC,
.of_match = exynos_dwmmc_ids,
+ .of_to_plat = exynos_dwmmc_of_to_plat,
.bind = exynos_dwmmc_bind,
- .ops = &dm_dwmci_ops,
.probe = exynos_dwmmc_probe,
+ .ops = &dm_dwmci_ops,
.priv_auto = sizeof(struct dwmci_exynos_priv_data),
.plat_auto = sizeof(struct exynos_mmc_plat),
};
diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h
index 782d92b..36187cf 100644
--- a/drivers/mmc/ftsdc010_mci.h
+++ b/drivers/mmc/ftsdc010_mci.h
@@ -28,7 +28,6 @@
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
struct mmc *mmc;
void *priv;
bool fifo_mode;
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index c68a915..0302f5c 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -36,7 +36,7 @@
struct hisi_mmc_data {
unsigned int clock;
bool use_fifo;
- u32 fifoth_val;
+ u32 fifo_depth;
};
static int hi6220_dwmmc_of_to_plat(struct udevice *dev)
@@ -125,7 +125,7 @@
host->mmc = &plat->mmc;
host->fifo_mode = mmc_data->use_fifo;
- host->fifoth_val = mmc_data->fifoth_val;
+ host->fifo_depth = mmc_data->fifo_depth;
host->mmc->priv = &priv->host;
upriv->mmc = host->mmc;
host->mmc->dev = dev;
@@ -158,8 +158,7 @@
static const struct hisi_mmc_data hi3798mv2x_mmc_data = {
.clock = 50000000,
.use_fifo = false,
- // FIFO depth is 256
- .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80),
+ .fifo_depth = 256,
};
static const struct udevice_id hi6220_dwmmc_ids[] = {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index cf8277c..96b0e20 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -30,6 +30,41 @@
#define DEFAULT_CMD6_TIMEOUT_MS 500
+/**
+ * names of emmc BOOT_PARTITION_ENABLE values
+ *
+ * Boot Area Partitions - name consistent with Linux
+ */
+const char *emmc_boot_part_names[] = {
+ "default", /* EMMC_BOOT_PART_DEFAULT */
+ "boot0", /* EMMC_BOOT_PART_BOOT1 */
+ "boot1", /* EMMC_BOOT_PART_BOOT2 */
+ "",
+ "",
+ "",
+ "",
+ "user", /* EMMC_BOOT_PART_USER */
+};
+
+/**
+ * names of emmc 'hardware partitions' consistent with:
+ * - value used in mmc_switch()
+ * - value used by PARTITION_CONFIG PARTITION_ACCESS field
+ *
+ * Boot Area Partitions - name consistent with Linux
+ * General Perpose Partitions - name consistent with 'mmc hwpartition' usage
+ */
+const char *emmc_hwpart_names[] = {
+ "user", /* EMMC_HWPART_DEFAULT */
+ "boot0", /* EMMC_HWPART_BOOT1 */
+ "boot1", /* EMMC_HWPART_BOOT2 */
+ "rpmb", /* EMMC_HWPART_RPMB */
+ "gp1", /* EMMC_HWPART_GP1 */
+ "gp2", /* EMMC_HWPART_GP2 */
+ "gp3", /* EMMC_HWPART_GP3 */
+ "gp4", /* EMMC_HWPART_GP4 */
+};
+
static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -294,7 +329,7 @@
if (status & MMC_STATUS_MASK) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Status Error: 0x%08x\n", status);
+ log_err("Status Error: %#08x\n", status);
#endif
return -ECOMM;
}
@@ -307,7 +342,7 @@
if (timeout_ms <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Timeout waiting card ready\n");
+ log_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
}
@@ -449,7 +484,7 @@
if (blkcnt > 1) {
if (mmc_send_stop_transmission(mmc, false)) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("mmc fail to send stop cmd\n");
+ log_err("mmc fail to send stop cmd\n");
#endif
return 0;
}
@@ -500,8 +535,8 @@
if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, block_dev->lba);
+ log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
+ start + blkcnt, block_dev->lba);
#endif
return 0;
}
@@ -962,8 +997,8 @@
* Extended CSD. Reconfigure the controller to run at HS mode.
*/
if (hsdowngrade) {
- mmc_select_mode(mmc, MMC_HS);
- mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
+ mmc_select_mode(mmc, MMC_HS_52);
+ mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS_52), false);
}
#endif
@@ -996,7 +1031,7 @@
return 0;
if (!ext_csd) {
- pr_err("No ext_csd found!\n"); /* this should enver happen */
+ log_err("No ext_csd found!\n"); /* this should never happen */
return -ENOTSUPP;
}
@@ -1108,17 +1143,17 @@
return -EINVAL;
if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
- pr_err("eMMC >= 4.4 required for enhanced user data area\n");
+ log_err("eMMC >= 4.4 required for enhanced user data area\n");
return -EMEDIUMTYPE;
}
if (!(mmc->part_support & PART_SUPPORT)) {
- pr_err("Card does not support partitioning\n");
+ log_err("Card does not support partitioning\n");
return -EMEDIUMTYPE;
}
if (!mmc->hc_wp_grp_size) {
- pr_err("Card does not define HC WP group size\n");
+ log_err("Card does not define HC WP group size\n");
return -EMEDIUMTYPE;
}
@@ -1126,8 +1161,7 @@
if (conf->user.enh_size) {
if (conf->user.enh_size % mmc->hc_wp_grp_size ||
conf->user.enh_start % mmc->hc_wp_grp_size) {
- pr_err("User data enhanced area not HC WP group "
- "size aligned\n");
+ log_err("User data enhanced area not HC WP group size aligned\n");
return -EINVAL;
}
part_attrs |= EXT_CSD_ENH_USR;
@@ -1145,8 +1179,8 @@
for (pidx = 0; pidx < 4; pidx++) {
if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
- pr_err("GP%i partition not HC WP group size "
- "aligned\n", pidx+1);
+ log_err("GP%i partition not HC WP group-size aligned\n",
+ pidx + 1);
return -EINVAL;
}
gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
@@ -1157,7 +1191,7 @@
}
if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
- pr_err("Card does not support enhanced attribute\n");
+ log_err("Card does not support enhanced attribute\n");
return -EMEDIUMTYPE;
}
@@ -1170,8 +1204,8 @@
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
if (tot_enh_size_mult > max_enh_size_mult) {
- pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
- tot_enh_size_mult, max_enh_size_mult);
+ log_err("Total enhanced size exceeds maximum (%#x > %#x)\n",
+ tot_enh_size_mult, max_enh_size_mult);
return -EMEDIUMTYPE;
}
@@ -1204,7 +1238,7 @@
if (ext_csd[EXT_CSD_PARTITION_SETTING] &
EXT_CSD_PARTITION_SETTING_COMPLETED) {
- pr_err("Card already partitioned\n");
+ log_err("Card already partitioned\n");
return -EPERM;
}
@@ -1875,7 +1909,7 @@
}
}
- pr_err("unable to select a mode\n");
+ log_err("unable to select a mode\n");
return -ENOTSUPP;
}
@@ -2043,7 +2077,7 @@
}
/* Set back to HS */
- mmc_set_card_speed(mmc, MMC_HS, true);
+ mmc_set_card_speed(mmc, MMC_HS_52, true);
err = mmc_hs400_prepare_ddr(mmc);
if (err)
@@ -2253,7 +2287,7 @@
}
}
- pr_err("unable to select a mode : %d\n", err);
+ log_err("unable to select a mode: %d\n", err);
return -ENOTSUPP;
}
@@ -2921,7 +2955,8 @@
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
if (!quiet)
- pr_err("Card did not respond to voltage select! : %d\n", err);
+ log_err("Card did not respond to voltage select! : %d\n",
+ err);
#endif
return -EOPNOTSUPP;
}
@@ -2954,7 +2989,7 @@
| MMC_CAP(MMC_LEGACY) |
MMC_MODE_1BIT);
} else {
- pr_err("bus_mode requested is not supported\n");
+ log_err("bus_mode requested is not supported\n");
return -EINVAL;
}
}
@@ -2974,7 +3009,7 @@
if (no_card) {
mmc->has_init = 0;
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("MMC: no card present\n");
+ log_err("MMC: no card present\n");
#endif
return -ENOMEDIUM;
}
@@ -3004,6 +3039,20 @@
return err;
}
+static void __maybe_unused mmc_cyclic_cd_poll(struct cyclic_info *c)
+{
+ struct mmc *m = CONFIG_IS_ENABLED(CYCLIC, (container_of(c, struct mmc, cyclic)), (NULL));
+
+ if (!m->has_init)
+ return;
+
+ if (mmc_getcd(m))
+ return;
+
+ mmc_deinit(m);
+ m->has_init = 0;
+}
+
int mmc_init(struct mmc *mmc)
{
int err = 0;
@@ -3026,6 +3075,14 @@
if (err)
pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
+ if (CONFIG_IS_ENABLED(CYCLIC, (!mmc->cyclic.func), (NULL))) {
+ /* Register cyclic function for card detect polling */
+ CONFIG_IS_ENABLED(CYCLIC, (cyclic_register(&mmc->cyclic,
+ mmc_cyclic_cd_poll,
+ 100 * 1000,
+ mmc->cfg->name)));
+ }
+
return err;
}
@@ -3033,6 +3090,9 @@
{
u32 caps_filtered;
+ if (CONFIG_IS_ENABLED(CYCLIC, (mmc->cyclic.func), (NULL)))
+ CONFIG_IS_ENABLED(CYCLIC, (cyclic_unregister(&mmc->cyclic)));
+
if (!CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) &&
!CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) &&
!CONFIG_IS_ENABLED(MMC_HS400_SUPPORT))
@@ -3103,7 +3163,7 @@
uclass_foreach_dev(dev, uc) {
ret = device_probe(dev);
if (ret)
- pr_err("%s - probe failed: %d\n", dev->name, ret);
+ log_err("%s - probe failed: %d\n", dev->name, ret);
}
return 0;
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index f5e9930..4e5c932 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -32,6 +32,8 @@
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
+#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
+
struct msm_sdhc_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -46,6 +48,7 @@
struct msm_sdhc_variant_info {
bool mci_removed;
+ u32 core_vendor_spec;
u32 core_vendor_spec_capabilities0;
};
@@ -54,11 +57,14 @@
static int msm_sdc_clk_init(struct udevice *dev)
{
struct msm_sdhc *prv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
ofnode node = dev_ofnode(dev);
ulong clk_rate;
int ret, i = 0, n_clks;
const char *clk_name;
+ var_info = (void *)dev_get_driver_data(dev);
+
ret = ofnode_read_u32(node, "clock-frequency", (uint *)(&clk_rate));
if (ret)
clk_rate = 201500000;
@@ -105,6 +111,9 @@
return -EINVAL;
}
+ writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
+ prv->host.ioaddr + var_info->core_vendor_spec);
+
return 0;
}
@@ -254,12 +263,14 @@
static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
.mci_removed = false,
+ .core_vendor_spec = 0x10c,
.core_vendor_spec_capabilities0 = 0x11c,
};
static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
.mci_removed = true,
+ .core_vendor_spec = 0x20c,
.core_vendor_spec_capabilities0 = 0x21c,
};
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
index 2e1ce54..80df617 100644
--- a/drivers/mmc/nexell_dw_mmc.c
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -186,10 +186,7 @@
struct dwmci_host *host = &priv->host;
struct udevice *pwr_dev __maybe_unused;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_size / 2 - 1) |
- TX_WMARK(priv->fifo_size / 2);
-
+ host->fifo_depth = priv->fifo_size;
host->fifo_mode = priv->fifo_mode;
dwmci_setup_cfg(&plat->cfg, host, priv->max_freq, priv->min_freq);
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 549fb80..fb77b04 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -138,10 +138,7 @@
if (ret < 0)
return ret;
#endif
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_depth / 2 - 1) |
- TX_WMARK(priv->fifo_depth / 2);
-
+ host->fifo_depth = priv->fifo_depth;
host->fifo_mode = priv->fifo_mode;
#if CONFIG_IS_ENABLED(MMC_PWRSEQ)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 80dbb38..278019f 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -166,7 +166,7 @@
host->index = dev_id - PERIPH_ID_SDMMC0;
/* Get bus width */
- bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
if (bus_width <= 0) {
debug("MMC: Can't get bus-width\n");
return -EINVAL;
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index 07ec35a0..7d169ef 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -16,56 +16,7 @@
#include <linux/libfdt.h>
#include <mmc.h>
#include <sdhci.h>
-
-/* HRS - Host Register Set (specific to Cadence) */
-#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
-#define SDHCI_CDNS_HRS04_ACK BIT(26)
-#define SDHCI_CDNS_HRS04_RD BIT(25)
-#define SDHCI_CDNS_HRS04_WR BIT(24)
-#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
-#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
-#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
-
-#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
-#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
-#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
-#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
-#define SDHCI_CDNS_HRS06_MODE_SD 0x0
-#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
-#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
-#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
-
-/* SRS - Slot Register Set (SDHCI-compatible) */
-#define SDHCI_CDNS_SRS_BASE 0x200
-
-/* PHY */
-#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
-#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
-#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
-#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
-#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
-#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
-#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
-#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
-#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
-#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
-
-/*
- * The tuned val register is 6 bit-wide, but not the whole of the range is
- * available. The range 0-42 seems to be available (then 43 wraps around to 0)
- * but I am not quite sure if it is official. Use only 0 to 39 for safety.
- */
-#define SDHCI_CDNS_MAX_TUNING_LOOP 40
-
-struct sdhci_cdns_plat {
- struct mmc_config cfg;
- struct mmc mmc;
- void __iomem *hrs_addr;
-};
+#include "sdhci-cadence.h"
struct sdhci_cdns_phy_cfg {
const char *property;
@@ -162,6 +113,9 @@
tmp &= ~SDHCI_CDNS_HRS06_MODE;
tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
+
+ if (device_is_compatible(mmc->dev, "cdns,sd6hc"))
+ sdhci_cdns6_phy_adj(mmc->dev, plat, mode);
}
static const struct sdhci_ops sdhci_cdns_ops = {
@@ -175,6 +129,9 @@
u32 tmp;
int i, ret;
+ if (device_is_compatible(plat->mmc.dev, "cdns,sd6hc"))
+ return sdhci_cdns6_set_tune_val(plat, val);
+
if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
return -EINVAL;
@@ -281,7 +238,10 @@
if (ret)
return ret;
- ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
+ if (device_is_compatible(dev, "cdns,sd6hc"))
+ ret = sdhci_cdns6_phy_init(dev, plat);
+ else
+ ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
return ret;
@@ -300,6 +260,7 @@
static const struct udevice_id sdhci_cdns_match[] = {
{ .compatible = "socionext,uniphier-sd4hc" },
{ .compatible = "cdns,sd4hc" },
+ { .compatible = "cdns,sd6hc" },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h
new file mode 100644
index 0000000..7101f00
--- /dev/null
+++ b/drivers/mmc/sdhci-cadence.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef SDHCI_CADENCE_H_
+#define SDHCI_CADENCE_H_
+
+/* HRS - Host Register Set (specific to Cadence) */
+/* PHY access port */
+#define SDHCI_CDNS_HRS04 0x10
+/* Cadence V4 HRS04 Description*/
+#define SDHCI_CDNS_HRS04_ACK BIT(26)
+#define SDHCI_CDNS_HRS04_RD BIT(25)
+#define SDHCI_CDNS_HRS04_WR BIT(24)
+#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
+#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
+#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
+
+#define SDHCI_CDNS_HRS05 0x14
+
+/* eMMC control */
+#define SDHCI_CDNS_HRS06 0x18
+#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
+#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
+#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
+#define SDHCI_CDNS_HRS06_MODE_SD 0x0
+#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
+#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
+#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
+
+/* SRS - Slot Register Set (SDHCI-compatible) */
+#define SDHCI_CDNS_SRS_BASE 0x200
+
+/* Cadence V4 PHY Setting*/
+#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
+#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
+#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
+#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
+#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
+#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
+#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
+#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
+#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
+#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
+
+/*
+ * The tuned val register is 6 bit-wide, but not the whole of the range is
+ * available. The range 0-42 seems to be available (then 43 wraps around to 0)
+ * but I am not quite sure if it is official. Use only 0 to 39 for safety.
+ */
+#define SDHCI_CDNS_MAX_TUNING_LOOP 40
+
+struct sdhci_cdns_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void __iomem *hrs_addr;
+};
+
+int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode);
+int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat);
+int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val);
+
+#endif
diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c
new file mode 100644
index 0000000..a5ed873
--- /dev/null
+++ b/drivers/mmc/sdhci-cadence6.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0-or-platform_driver
+/*
+ * Copyright (C) 2023 Starfive.
+ * Author: Kuan Lim Lee <kuanlim.lee@starfivetech.com>
+ */
+
+#include <dm.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/sizes.h>
+#include <linux/libfdt.h>
+#include <mmc.h>
+#include <sdhci.h>
+#include "sdhci-cadence.h"
+
+/* IO Delay Information */
+#define SDHCI_CDNS_HRS07 0X1C
+#define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16)
+#define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0)
+
+/* PHY Control and Status */
+#define SDHCI_CDNS_HRS09 0x24
+#define SDHCI_CDNS_HRS09_RDDATA_EN BIT(16)
+#define SDHCI_CDNS_HRS09_RDCMD_EN BIT(15)
+#define SDHCI_CDNS_HRS09_EXTENDED_WR_MODE BIT(3)
+#define SDHCI_CDNS_HRS09_EXTENDED_RD_MODE BIT(2)
+#define SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE BIT(1)
+#define SDHCI_CDNS_HRS09_PHY_SW_RESET BIT(0)
+
+/* SDCLK adjustment */
+#define SDHCI_CDNS_HRS10 0x28
+#define SDHCI_CDNS_HRS10_HCSDCLKADJ GENMASK(19, 16)
+
+/* CMD/DAT output delay */
+#define SDHCI_CDNS_HRS16 0x40
+
+/* PHY Special Function Registers */
+/* register to control the DQ related timing */
+#define PHY_DQ_TIMING_REG_ADDR 0x2000
+
+/* register to control the DQS related timing */
+#define PHY_DQS_TIMING_REG_ADDR 0x2004
+
+/* register to control the gate and loopback control related timing */
+#define PHY_GATE_LPBK_CTRL_REG_ADDR 0x2008
+
+/* register to control the Master DLL logic */
+#define PHY_DLL_MASTER_CTRL_REG_ADDR 0x200C
+
+/* register to control the Slave DLL logic */
+#define PHY_DLL_SLAVE_CTRL_REG_ADDR 0x2010
+#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY GENMASK(31, 24)
+#define PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY GENMASK(7, 0)
+
+#define SDHCI_CDNS6_PHY_CFG_NUM 4
+#define SDHCI_CDNS6_CTRL_CFG_NUM 4
+
+struct sdhci_cdns6_phy_cfg {
+ const char *property;
+ u32 val;
+};
+
+struct sdhci_cdns6_ctrl_cfg {
+ const char *property;
+ u32 val;
+};
+
+static struct sdhci_cdns6_phy_cfg sd_ds_phy_cfgs[] = {
+ { "cdns,phy-dqs-timing-delay-sd-ds", 0x00380004, },
+ { "cdns,phy-gate-lpbk_ctrl-delay-sd-ds", 0x01A00040, },
+ { "cdns,phy-dll-slave-ctrl-sd-ds", 0x00000000, },
+ { "cdns,phy-dq-timing-delay-sd-ds", 0x00000001, },
+};
+
+static struct sdhci_cdns6_phy_cfg emmc_sdr_phy_cfgs[] = {
+ { "cdns,phy-dqs-timing-delay-semmc-sdr", 0x00380004, },
+ { "cdns,phy-gate-lpbk_ctrl-delay-emmc-sdr", 0x01A00040, },
+ { "cdns,phy-dll-slave-ctrl-emmc-sdr", 0x00000000, },
+ { "cdns,phy-dq-timing-delay-emmc-sdr", 0x00000001, },
+};
+
+static struct sdhci_cdns6_phy_cfg emmc_ddr_phy_cfgs[] = {
+ { "cdns,phy-dqs-timing-delay-emmc-ddr", 0x00380004, },
+ { "cdns,phy-gate-lpbk_ctrl-delay-emmc-ddr", 0x01A00040, },
+ { "cdns,phy-dll-slave-ctrl-emmc-ddr", 0x00000000, },
+ { "cdns,phy-dq-timing-delay-emmc-ddr", 0x10000001, },
+};
+
+static struct sdhci_cdns6_phy_cfg emmc_hs200_phy_cfgs[] = {
+ { "cdns,phy-dqs-timing-delay-emmc-hs200", 0x00380004, },
+ { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs200", 0x01A00040, },
+ { "cdns,phy-dll-slave-ctrl-emmc-hs200", 0x00DADA00, },
+ { "cdns,phy-dq-timing-delay-emmc-hs200", 0x00000001, },
+};
+
+static struct sdhci_cdns6_phy_cfg emmc_hs400_phy_cfgs[] = {
+ { "cdns,phy-dqs-timing-delay-emmc-hs400", 0x00280004, },
+ { "cdns,phy-gate-lpbk_ctrl-delay-emmc-hs400", 0x01A00040, },
+ { "cdns,phy-dll-slave-ctrl-emmc-hs400", 0x00DAD800, },
+ { "cdns,phy-dq-timing-delay-emmc-hs400", 0x00000001, },
+};
+
+static struct sdhci_cdns6_ctrl_cfg sd_ds_ctrl_cfgs[] = {
+ { "cdns,ctrl-hrs09-timing-delay-sd-ds", 0x0001800C, },
+ { "cdns,ctrl-hrs10-lpbk_ctrl-delay-sd-ds", 0x00020000, },
+ { "cdns,ctrl-hrs16-slave-ctrl-sd-ds", 0x00000000, },
+ { "cdns,ctrl-hrs07-timing-delay-sd-ds", 0x00080000, },
+};
+
+static struct sdhci_cdns6_ctrl_cfg emmc_sdr_ctrl_cfgs[] = {
+ { "cdns,ctrl-hrs09-timing-delay-emmc-sdr", 0x0001800C, },
+ { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-sdr", 0x00030000, },
+ { "cdns,ctrl-hrs16-slave-ctrl-emmc-sdr", 0x00000000, },
+ { "cdns,ctrl-hrs07-timing-delay-emmc-sdr", 0x00080000, },
+};
+
+static struct sdhci_cdns6_ctrl_cfg emmc_ddr_ctrl_cfgs[] = {
+ { "cdns,ctrl-hrs09-timing-delay-emmc-ddr", 0x0001800C, },
+ { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-ddr", 0x00020000, },
+ { "cdns,ctrl-hrs16-slave-ctrl-emmc-ddr", 0x11000001, },
+ { "cdns,ctrl-hrs07-timing-delay-emmc-ddr", 0x00090001, },
+};
+
+static struct sdhci_cdns6_ctrl_cfg emmc_hs200_ctrl_cfgs[] = {
+ { "cdns,ctrl-hrs09-timing-delay-emmc-hs200", 0x00018000, },
+ { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs200", 0x00080000, },
+ { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs200", 0x00000000, },
+ { "cdns,ctrl-hrs07-timing-delay-emmc-hs200", 0x00090000, },
+};
+
+static struct sdhci_cdns6_ctrl_cfg emmc_hs400_ctrl_cfgs[] = {
+ { "cdns,ctrl-hrs09-timing-delay-emmc-hs400", 0x00018000, },
+ { "cdns,ctrl-hrs10-lpbk_ctrl-delay-emmc-hs400", 0x00080000, },
+ { "cdns,ctrl-hrs16-slave-ctrl-emmc-hs400", 0x11000000, },
+ { "cdns,ctrl-hrs07-timing-delay-emmc-hs400", 0x00080000, },
+};
+
+static u32 sdhci_cdns6_read_phy_reg(struct sdhci_cdns_plat *plat, u32 addr)
+{
+ writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04);
+ return readl(plat->hrs_addr + SDHCI_CDNS_HRS05);
+}
+
+static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u32 val)
+{
+ writel(addr, plat->hrs_addr + SDHCI_CDNS_HRS04);
+ writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05);
+}
+
+static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset)
+{
+ void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09;
+ u32 tmp;
+ int ret;
+
+ tmp = readl(reg);
+ tmp &= ~SDHCI_CDNS_HRS09_PHY_SW_RESET;
+
+ /* Switch On DLL Reset */
+ if (reset)
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 0);
+ else
+ tmp |= FIELD_PREP(SDHCI_CDNS_HRS09_PHY_SW_RESET, 1);
+
+ writel(tmp, reg);
+
+ /* After reset, wait until HRS09.PHY_INIT_COMPLETE is set to 1 within 3000us*/
+ if (!reset) {
+ ret = readl_poll_timeout(reg, tmp, (tmp & SDHCI_CDNS_HRS09_PHY_INIT_COMPLETE),
+ 3000);
+ }
+
+ return ret;
+}
+
+int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ struct sdhci_cdns6_phy_cfg *sdhci_cdns6_phy_cfgs;
+ struct sdhci_cdns6_ctrl_cfg *sdhci_cdns6_ctrl_cfgs;
+ const fdt32_t *prop;
+ u32 tmp;
+ int i, ret;
+
+ switch (mode) {
+ case SDHCI_CDNS_HRS06_MODE_SD:
+ sdhci_cdns6_phy_cfgs = sd_ds_phy_cfgs;
+ sdhci_cdns6_ctrl_cfgs = sd_ds_ctrl_cfgs;
+ break;
+
+ case SDHCI_CDNS_HRS06_MODE_MMC_SDR:
+ sdhci_cdns6_phy_cfgs = emmc_sdr_phy_cfgs;
+ sdhci_cdns6_ctrl_cfgs = emmc_sdr_ctrl_cfgs;
+ break;
+
+ case SDHCI_CDNS_HRS06_MODE_MMC_DDR:
+ sdhci_cdns6_phy_cfgs = emmc_ddr_phy_cfgs;
+ sdhci_cdns6_ctrl_cfgs = emmc_ddr_ctrl_cfgs;
+ break;
+
+ case SDHCI_CDNS_HRS06_MODE_MMC_HS200:
+ sdhci_cdns6_phy_cfgs = emmc_hs200_phy_cfgs;
+ sdhci_cdns6_ctrl_cfgs = emmc_hs200_ctrl_cfgs;
+ break;
+
+ case SDHCI_CDNS_HRS06_MODE_MMC_HS400:
+ sdhci_cdns6_phy_cfgs = emmc_hs400_phy_cfgs;
+ sdhci_cdns6_ctrl_cfgs = emmc_hs400_ctrl_cfgs;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = 0; i < SDHCI_CDNS6_PHY_CFG_NUM; i++) {
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ sdhci_cdns6_phy_cfgs[i].property, NULL);
+ if (prop)
+ sdhci_cdns6_phy_cfgs[i].val = *prop;
+ }
+
+ for (i = 0; i < SDHCI_CDNS6_CTRL_CFG_NUM; i++) {
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ sdhci_cdns6_ctrl_cfgs[i].property, NULL);
+ if (prop)
+ sdhci_cdns6_ctrl_cfgs[i].val = *prop;
+ }
+
+ /* Switch On the DLL Reset */
+ sdhci_cdns6_reset_phy_dll(plat, true);
+
+ sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val);
+ sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val);
+ sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val);
+
+ /* Switch Off the DLL Reset */
+ ret = sdhci_cdns6_reset_phy_dll(plat, false);
+ if (ret) {
+ printf("sdhci_cdns6_reset_phy is not completed\n");
+ return ret;
+ }
+
+ /* Set PHY DQ TIMING control register */
+ sdhci_cdns6_write_phy_reg(plat, PHY_DQ_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[3].val);
+
+ /* Set HRS09 register */
+ tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS09);
+ tmp &= ~(SDHCI_CDNS_HRS09_EXTENDED_WR_MODE |
+ SDHCI_CDNS_HRS09_EXTENDED_RD_MODE |
+ SDHCI_CDNS_HRS09_RDDATA_EN |
+ SDHCI_CDNS_HRS09_RDCMD_EN);
+ tmp |= sdhci_cdns6_ctrl_cfgs[0].val;
+ writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS09);
+
+ /* Set HRS10 register */
+ tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS10);
+ tmp &= ~SDHCI_CDNS_HRS10_HCSDCLKADJ;
+ tmp |= sdhci_cdns6_ctrl_cfgs[1].val;
+ writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS10);
+
+ /* Set HRS16 register */
+ writel(sdhci_cdns6_ctrl_cfgs[2].val, plat->hrs_addr + SDHCI_CDNS_HRS16);
+
+ /* Set HRS07 register */
+ writel(sdhci_cdns6_ctrl_cfgs[3].val, plat->hrs_addr + SDHCI_CDNS_HRS07);
+
+ return 0;
+}
+
+int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat)
+{
+ return sdhci_cdns6_phy_adj(dev, plat, SDHCI_CDNS_HRS06_MODE_SD);
+}
+
+int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val)
+{
+ u32 tmp, tuneval;
+
+ tuneval = (val * 256) / SDHCI_CDNS_MAX_TUNING_LOOP;
+
+ tmp = sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR);
+ tmp &= ~(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY |
+ PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY);
+ tmp |= FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_CMD_DELAY, tuneval) |
+ FIELD_PREP(PHY_DLL_SLAVE_CTRL_REG_READ_DQS_DELAY, tuneval);
+ sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp);
+
+ return 0;
+}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 560b7e8..4833b51 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -32,8 +32,7 @@
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
- printf("%s: Reset 0x%x never completed.\n",
- __func__, (int)mask);
+ log_warning("Reset %#x never completed\n", mask);
return;
}
timeout--;
@@ -139,8 +138,7 @@
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- pr_debug("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ log_debug("Error detected in status(%#x)!\n", stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
@@ -173,7 +171,7 @@
if (timeout-- > 0)
udelay(10);
else {
- printf("%s: Transfer data timeout\n", __func__);
+ log_err("Transfer data timeout\n");
return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
@@ -232,13 +230,13 @@
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (time >= cmd_timeout) {
- printf("%s: MMC: %d busy ", __func__, mmc_dev);
+ log_warning("mmc%d busy ", mmc_dev);
if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
cmd_timeout += cmd_timeout;
- printf("timeout increasing to: %u ms.\n",
- cmd_timeout);
+ log_warning("timeout increasing to: %u ms\n",
+ cmd_timeout);
} else {
- puts("timeout.\n");
+ log_warning("timeout\n");
return -ECOMM;
}
}
@@ -316,8 +314,8 @@
}
if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
- printf("%s: Timeout for status update: %08x %08x\n",
- __func__, stat, mask);
+ log_warning("Timeout for status update: %08x %08x\n",
+ stat, mask);
return -ETIMEDOUT;
}
} while ((stat & mask) != mask);
@@ -358,7 +356,7 @@
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct sdhci_host *host = mmc->priv;
- debug("%s\n", __func__);
+ log_debug("sdhci tuning\n");
if (host->ops && host->ops->platform_execute_tuning) {
err = host->ops->platform_execute_tuning(mmc, opcode);
@@ -380,8 +378,7 @@
while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
(SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
if (timeout == 0) {
- printf("%s: Timeout to wait cmd & data inhibit\n",
- __func__);
+ log_err("Timeout waiting for cmd & data inhibit\n");
return -EBUSY;
}
@@ -397,7 +394,7 @@
if (host->ops && host->ops->set_delay) {
ret = host->ops->set_delay(host);
if (ret) {
- printf("%s: Error while setting tap delay\n", __func__);
+ log_err("Error while setting tap delay\n");
return ret;
}
}
@@ -405,7 +402,7 @@
if (host->ops && host->ops->config_dll) {
ret = host->ops->config_dll(host, clock, false);
if (ret) {
- printf("%s: Error while configuring dll\n", __func__);
+ log_err("Error configuring dll\n");
return ret;
}
}
@@ -456,7 +453,7 @@
if (host->ops && host->ops->config_dll) {
ret = host->ops->config_dll(host, clock, true);
if (ret) {
- printf("%s: Error while configuring dll\n", __func__);
+ log_err("Error while configuring dll\n");
return ret;
}
}
@@ -472,8 +469,7 @@
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
& SDHCI_CLOCK_INT_STABLE)) {
if (timeout == 0) {
- printf("%s: Internal clock never stabilised.\n",
- __func__);
+ log_err("Internal clock never stabilised.\n");
return -EBUSY;
}
timeout--;
@@ -738,8 +734,7 @@
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
host->align_buffer = memalign(8, 512 * 1024);
if (!host->align_buffer) {
- printf("%s: Aligned buffer alloc failed!!!\n",
- __func__);
+ log_err("Aligned buffer alloc failed\n");
return -ENOMEM;
}
}
@@ -881,20 +876,18 @@
#else
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#endif
- debug("%s, caps: 0x%x\n", __func__, caps);
+ log_debug("caps: %#x\n", caps);
#if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA)
if ((caps & SDHCI_CAN_DO_SDMA)) {
host->flags |= USE_SDMA;
} else {
- debug("%s: Your controller doesn't support SDMA!!\n",
- __func__);
+ log_debug("Controller doesn't support SDMA\n");
}
#endif
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
if (!(caps & SDHCI_CAN_DO_ADMA2)) {
- printf("%s: Your controller doesn't support ADMA!!\n",
- __func__);
+ log_err("Controller doesn't support ADMA\n");
return -EINVAL;
}
if (!host->adma_desc_table) {
@@ -927,7 +920,7 @@
#else
caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
#endif
- debug("%s, caps_1: 0x%x\n", __func__, caps_1);
+ log_debug("caps_1: %#x\n", caps_1);
host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
SDHCI_CLOCK_MUL_SHIFT;
@@ -953,8 +946,7 @@
host->max_clk *= host->clk_mul;
}
if (host->max_clk == 0) {
- printf("%s: Hardware doesn't specify base clock frequency\n",
- __func__);
+ log_err("Hardware doesn't specify base clock frequency\n");
return -EINVAL;
}
if (f_max && (f_max < host->max_clk))
@@ -1047,7 +1039,7 @@
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL) {
- printf("%s: mmc create fail!\n", __func__);
+ log_err("mmc create fail\n");
return -ENOMEM;
}
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c
index 9bdbe50..47ab565 100644
--- a/drivers/mmc/snps_dw_mmc.c
+++ b/drivers/mmc/snps_dw_mmc.c
@@ -12,6 +12,7 @@
#include <dwmmc.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <linux/libfdt.h>
#include <linux/err.h>
@@ -29,6 +30,7 @@
struct snps_dwmci_priv_data {
struct dwmci_host host;
u32 f_max;
+ struct gpio_desc cd_gpio;
};
static int snps_dwmmc_clk_setup(struct udevice *dev)
@@ -81,7 +83,7 @@
host->ioaddr = dev_read_addr_ptr(dev);
/*
- * If fifo-depth is unset don't set fifoth_val - we will try to
+ * If fifo-depth is unset don't set fifo_depth - we will try to
* auto detect it.
*/
ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
@@ -89,9 +91,7 @@
if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX)
return -EINVAL;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) |
- TX_WMARK(fifo_depth / 2);
+ host->fifo_depth = fifo_depth;
}
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
@@ -106,6 +106,10 @@
if (!ret && priv->f_max < CLOCK_MIN)
return -EINVAL;
+ if (CONFIG_IS_ENABLED(DM_GPIO))
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
+
host->fifo_mode = dev_read_bool(dev, "fifo-mode");
host->name = dev->name;
host->dev_index = 0;
@@ -119,6 +123,9 @@
struct snps_dwmci_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&priv->cd_gpio))
+ return dm_gpio_get_value(&priv->cd_gpio);
+
return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
}
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index f738019..3147d30 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -134,8 +134,8 @@
* We only have one dwmmc block on gen5 SoCFPGA.
*/
host->dev_index = 0;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+
+ host->fifo_depth = fifo_depth;
priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"drvsel", 3);
priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 28d2b45..24d0556 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -105,6 +105,19 @@
struct reset_ctl_bulk resets;
};
+enum arasan_sdhci_compatible {
+ SDHCI_COMPATIBLE_SDHCI_89A,
+ SDHCI_COMPATIBLE_VERSAL_NET_EMMC,
+};
+
+static bool arasan_sdhci_is_compatible(struct udevice *dev,
+ enum arasan_sdhci_compatible family)
+{
+ enum arasan_sdhci_compatible compat = dev_get_driver_data(dev);
+
+ return compat == family;
+}
+
/* For Versal platforms zynqmp_mmio_write() won't be available */
__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
{
@@ -422,7 +435,7 @@
mdelay(1);
- if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+ if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A))
arasan_zynqmp_dll_reset(host, priv->node_id);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
@@ -470,7 +483,7 @@
udelay(1);
- if (device_is_compatible(mmc->dev, "xlnx,zynqmp-8.9a"))
+ if (arasan_sdhci_is_compatible(mmc->dev, SDHCI_COMPATIBLE_SDHCI_89A))
arasan_zynqmp_dll_reset(host, priv->node_id);
/* Enable only interrupts served by the SD controller */
@@ -858,7 +871,7 @@
dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
- device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) {
ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
if (ret)
return ret;
@@ -869,7 +882,7 @@
} else if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
- device_is_compatible(dev, "xlnx,versal-8.9a")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) {
ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
if (ret)
return ret;
@@ -879,7 +892,7 @@
return ret;
} else if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
- device_is_compatible(dev, "xlnx,versal-net-emmc")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) {
if (mmc->clock >= MIN_PHY_CLK_HZ)
if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
@@ -933,7 +946,7 @@
int i;
if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
- device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
@@ -948,7 +961,7 @@
if ((IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
- device_is_compatible(dev, "xlnx,versal-8.9a")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_iclk_phases[i];
clk_data->clk_phase_out[i] = versal_oclk_phases[i];
@@ -957,7 +970,7 @@
if ((IS_ENABLED(CONFIG_ARCH_VERSAL_NET) ||
IS_ENABLED(CONFIG_ARCH_VERSAL2)) &&
- device_is_compatible(dev, "xlnx,versal-net-emmc")) {
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC)) {
for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
@@ -1101,7 +1114,7 @@
host = priv->host;
#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
- if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
+ if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_SDHCI_89A)) {
ret = zynqmp_pm_is_function_supported(PM_IOCTL,
IOCTL_SET_SD_CONFIG);
if (!ret) {
@@ -1111,7 +1124,7 @@
}
}
#endif
- if (device_is_compatible(dev, "xlnx,versal-net-emmc"))
+ if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC))
priv->internal_phy_reg = true;
ret = clk_get_by_index(dev, 0, &clk);
@@ -1145,7 +1158,7 @@
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
- device_is_compatible(dev, "xlnx,versal-net-emmc"))
+ arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC))
host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
@@ -1228,8 +1241,8 @@
}
static const struct udevice_id arasan_sdhci_ids[] = {
- { .compatible = "arasan,sdhci-8.9a" },
- { .compatible = "xlnx,versal-net-emmc" },
+ { .compatible = "arasan,sdhci-8.9a", .data = SDHCI_COMPATIBLE_SDHCI_89A },
+ { .compatible = "xlnx,versal-net-emmc", .data = SDHCI_COMPATIBLE_VERSAL_NET_EMMC },
{ }
};
diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
index c266158..e5c8df7 100644
--- a/drivers/mtd/altera_qspi.c
+++ b/drivers/mtd/altera_qspi.c
@@ -96,7 +96,7 @@
ret = mtd_erase(mtd, &instr);
flash_set_verbose(0);
if (ret)
- return ERR_PROTECTED;
+ return FL_ERR_PROTECTED;
puts(" done\n");
return 0;
@@ -114,7 +114,7 @@
ret = mtd_write(mtd, to, cnt, &retlen, src);
if (ret)
- return ERR_PROTECTED;
+ return FL_ERR_PROTECTED;
return 0;
}
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index a7826e8..e505028 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -593,11 +593,11 @@
flash_read_long(info, sector, 0));
flash_write_cmd(info, sector, 0, info->cmd_reset);
udelay(1);
- return ERR_TIMEOUT;
+ return FL_ERR_TIMEOUT;
}
udelay(1); /* also triggers watchdog */
}
- return ERR_OK;
+ return FL_ERR_OK;
}
/*-----------------------------------------------------------------------
@@ -616,9 +616,9 @@
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
- if (retcode == ERR_OK &&
+ if (retcode == FL_ERR_OK &&
!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
+ retcode = FL_ERR_INVAL;
printf("Flash %s error at address %lx\n", prompt,
info->start[sector]);
if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS |
@@ -627,14 +627,14 @@
} else if (flash_isset(info, sector, 0,
FLASH_STATUS_ECLBS)) {
puts("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
+ retcode = FL_ERR_NOT_ERASED;
} else if (flash_isset(info, sector, 0,
FLASH_STATUS_PSLBS)) {
puts("Locking Error\n");
}
if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
puts("Block locked.\n");
- retcode = ERR_PROTECTED;
+ retcode = FL_ERR_PROTECTED;
}
if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
puts("Vpp Low Error.\n");
@@ -702,12 +702,12 @@
if (get_timer(start) > tout) {
printf("Flash %s timeout at address %lx data %lx\n",
prompt, (ulong)dst, (ulong)flash_read8(dst));
- return ERR_TIMEOUT;
+ return FL_ERR_TIMEOUT;
}
udelay(1); /* also triggers watchdog */
}
#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
- return ERR_OK;
+ return FL_ERR_OK;
}
/*-----------------------------------------------------------------------
@@ -810,7 +810,7 @@
break;
}
if (!flag)
- return ERR_NOT_ERASED;
+ return FL_ERR_NOT_ERASED;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -899,7 +899,7 @@
shift = 3;
break;
default:
- retcode = ERR_INVAL;
+ retcode = FL_ERR_INVAL;
goto out_unmap;
}
@@ -930,7 +930,7 @@
}
}
if (!flag) {
- retcode = ERR_NOT_ERASED;
+ retcode = FL_ERR_NOT_ERASED;
goto out_unmap;
}
@@ -950,7 +950,7 @@
retcode = flash_status_check(info, sector,
info->buffer_write_tout,
"write to buffer");
- if (retcode == ERR_OK) {
+ if (retcode == FL_ERR_OK) {
/* reduce the number of loops by the width of
* the port
*/
@@ -975,7 +975,7 @@
src += 8, dst += 8;
break;
default:
- retcode = ERR_INVAL;
+ retcode = FL_ERR_INVAL;
goto out_unmap;
}
}
@@ -1025,7 +1025,7 @@
}
break;
default:
- retcode = ERR_INVAL;
+ retcode = FL_ERR_INVAL;
goto out_unmap;
}
@@ -1043,7 +1043,7 @@
default:
debug("Unknown Command Set\n");
- retcode = ERR_INVAL;
+ retcode = FL_ERR_INVAL;
break;
}
@@ -1389,7 +1389,7 @@
if (i > cnt)
i = cnt;
rc = flash_write_cfibuffer(info, wp, src, i);
- if (rc != ERR_OK)
+ if (rc != FL_ERR_OK)
return rc;
i -= i & (info->portwidth - 1);
wp += i;
@@ -1398,7 +1398,7 @@
FLASH_SHOW_PROGRESS(scale, dots, digit, i);
/* Only check every once in a while */
if ((cnt & 0xFFFF) < buffered_size && ctrlc())
- return ERR_ABORTED;
+ return FL_ERR_ABORTED;
}
#else
while (cnt >= info->portwidth) {
@@ -1413,7 +1413,7 @@
FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
/* Only check every once in a while */
if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
- return ERR_ABORTED;
+ return FL_ERR_ABORTED;
}
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
index 12499a7..28c851f10 100644
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -39,6 +39,7 @@
#define NFC_CMD_RB BIT(20)
#define NFC_CMD_SCRAMBLER_ENABLE BIT(19)
#define NFC_CMD_SCRAMBLER_DISABLE 0
+#define NFC_CMD_SHORTMODE_ENABLE 1
#define NFC_CMD_SHORTMODE_DISABLE 0
#define NFC_CMD_RB_INT BIT(14)
#define NFC_CMD_RB_INT_NO_PIN ((0xb << 10) | BIT(18) | BIT(16))
@@ -77,6 +78,8 @@
#define DMA_DIR(dir) ((dir) ? NFC_CMD_N2M : NFC_CMD_M2N)
+#define NFC_SHORT_MODE_ECC_SZ 384
+
#define ECC_CHECK_RETURN_FF -1
#define NAND_CE0 (0xe << 10)
@@ -140,6 +143,8 @@
struct meson_nfc_nand_chip {
struct list_head node;
struct nand_chip nand;
+ u32 boot_pages;
+ u32 boot_page_step;
u32 bch_mode;
u8 *data_buf;
@@ -228,28 +233,49 @@
nfc->reg_base + NFC_REG_CMD);
}
+static int meson_nfc_is_boot_page(struct nand_chip *nand, int page)
+{
+ const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
+
+ return (nand->options & NAND_IS_BOOT_MEDIUM) &&
+ !(page % meson_chip->boot_page_step) &&
+ (page < meson_chip->boot_pages);
+}
+
-static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir,
- int scrambler)
+static void meson_nfc_cmd_access(struct nand_chip *nand, bool raw, bool dir, int page)
{
+ const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
struct mtd_info *mtd = nand_to_mtd(nand);
const struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
- const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand);
- u32 bch = meson_chip->bch_mode, cmd;
int len = mtd->writesize, pagesize, pages;
+ unsigned int scrambler;
+ u32 cmd;
- pagesize = nand->ecc.size;
+ if (nand->options & NAND_NEED_SCRAMBLING)
+ scrambler = NFC_CMD_SCRAMBLER_ENABLE;
+ else
+ scrambler = NFC_CMD_SCRAMBLER_DISABLE;
if (raw) {
len = mtd->writesize + mtd->oobsize;
cmd = len | scrambler | DMA_DIR(dir);
- writel(cmd, nfc->reg_base + NFC_REG_CMD);
- return;
- }
+ } else if (meson_nfc_is_boot_page(nand, page)) {
+ pagesize = NFC_SHORT_MODE_ECC_SZ >> 3;
+ pages = mtd->writesize / 512;
+
+ scrambler = NFC_CMD_SCRAMBLER_ENABLE;
+ cmd = CMDRWGEN(DMA_DIR(dir), scrambler, NFC_ECC_BCH8_1K,
+ NFC_CMD_SHORTMODE_ENABLE, pagesize, pages);
+ } else {
+ pagesize = nand->ecc.size >> 3;
+ pages = len / nand->ecc.size;
- pages = len / nand->ecc.size;
+ cmd = CMDRWGEN(DMA_DIR(dir), scrambler, meson_chip->bch_mode,
+ NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
+ }
- cmd = CMDRWGEN(DMA_DIR(dir), scrambler, bch,
- NFC_CMD_SHORTMODE_DISABLE, pagesize, pages);
+ if (scrambler == NFC_CMD_SCRAMBLER_ENABLE)
+ meson_nfc_cmd_seed(nfc, page);
writel(cmd, nfc->reg_base + NFC_REG_CMD);
}
@@ -565,14 +591,7 @@
return ret;
}
- if (nand->options & NAND_NEED_SCRAMBLING) {
- meson_nfc_cmd_seed(nfc, page);
- meson_nfc_cmd_access(nand, raw, DIRWRITE,
- NFC_CMD_SCRAMBLER_ENABLE);
- } else {
- meson_nfc_cmd_access(nand, raw, DIRWRITE,
- NFC_CMD_SCRAMBLER_DISABLE);
- }
+ meson_nfc_cmd_access(nand, raw, DIRWRITE, page);
cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
writel(cmd, nfc->reg_base + NFC_REG_CMD);
@@ -643,14 +662,7 @@
if (ret)
return ret;
- if (nand->options & NAND_NEED_SCRAMBLING) {
- meson_nfc_cmd_seed(nfc, page);
- meson_nfc_cmd_access(nand, raw, DIRREAD,
- NFC_CMD_SCRAMBLER_ENABLE);
- } else {
- meson_nfc_cmd_access(nand, raw, DIRREAD,
- NFC_CMD_SCRAMBLER_DISABLE);
- }
+ meson_nfc_cmd_access(nand, raw, DIRREAD, page);
meson_nfc_wait_dma_finish(nfc);
meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
@@ -1137,6 +1149,24 @@
goto err_chip_buf_free;
}
+ if (nand->options & NAND_IS_BOOT_MEDIUM) {
+ ret = ofnode_read_u32(node, "amlogic,boot-pages",
+ &meson_chip->boot_pages);
+ if (ret) {
+ dev_err(dev, "could not retrieve 'amlogic,boot-pages' property: %d",
+ ret);
+ goto err_chip_buf_free;
+ }
+
+ ret = ofnode_read_u32(node, "amlogic,boot-page-step",
+ &meson_chip->boot_page_step);
+ if (ret) {
+ dev_err(dev, "could not retrieve 'amlogic,boot-page-step' property: %d",
+ ret);
+ goto err_chip_buf_free;
+ }
+ }
+
ret = nand_register(0, mtd);
if (ret) {
dev_err(dev, "'nand_register()' failed: %d\n", ret);
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 4401bdc..0545c23 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4454,6 +4454,9 @@
if (ret == 16)
chip->options |= NAND_BUSWIDTH_16;
+ if (ofnode_read_bool(node, "nand-is-boot-medium"))
+ chip->options |= NAND_IS_BOOT_MEDIUM;
+
if (ofnode_read_bool(node, "nand-on-flash-bbt"))
chip->bbt_options |= NAND_BBT_USE_FLASH;
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 92a92ad..a36e2a1 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -1188,7 +1188,10 @@
return ret;
base = devm_ioremap(dev, res.start, resource_size(&res));
- gpmc_nand_init(nand, base);
+ ret = gpmc_nand_init(nand, base);
+ if (ret)
+ return ret;
+
mtd->dev = dev;
nand_set_flash_node(nand, dev_ofnode(dev));
diff --git a/drivers/mtd/nvmxip/nvmxip-uclass.c b/drivers/mtd/nvmxip/nvmxip-uclass.c
index 254f04e..d18bd0e 100644
--- a/drivers/mtd/nvmxip/nvmxip-uclass.c
+++ b/drivers/mtd/nvmxip/nvmxip-uclass.c
@@ -47,19 +47,13 @@
return ret;
}
- log_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name);
+ log_debug("[%s]: the block device %s ready for use\n", udev->name,
+ bdev_name);
return 0;
}
-static int nvmxip_post_bind(struct udevice *udev)
-{
- dev_or_flags(udev, DM_FLAG_PROBE_AFTER_BIND);
- return 0;
-}
-
UCLASS_DRIVER(nvmxip) = {
.name = "nvmxip",
.id = UCLASS_NVMXIP,
- .post_bind = nvmxip_post_bind,
};
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
index 941f204..0354582 100644
--- a/drivers/mtd/renesas_rpc_hf.c
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -387,6 +387,7 @@
static const struct udevice_id rpc_hf_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{}
};
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index aea611f..8f7a77e 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -44,6 +44,12 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+/*
+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
+ * for larger flash
+ */
+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
+
#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
struct sfdp_parameter_header {
@@ -855,6 +861,20 @@
DEFAULT_READY_WAIT_JIFFIES);
}
+static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long size)
+{
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ unsigned long timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(size / SZ_2M));
+ return spi_nor_wait_till_ready_with_timeout(nor, timeout);
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
/*
* This "clean_bar" is necessary in a situation when one was accessing
@@ -989,7 +1009,7 @@
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
bool addr_known = false;
- u32 addr, len, rem;
+ u32 addr, len, rem, max_size;
int ret, err;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
@@ -1003,6 +1023,7 @@
addr = instr->addr;
len = instr->len;
+ max_size = instr->len;
instr->state = MTD_ERASING;
addr_known = true;
@@ -1035,7 +1056,13 @@
addr += ret;
len -= ret;
+ if (max_size == mtd->size &&
+ !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
+ ret = spi_nor_erase_chip_wait_till_ready(nor, mtd->size);
+ } else {
+ ret = spi_nor_wait_till_ready(nor);
+ }
+
- ret = spi_nor_wait_till_ready(nor);
if (ret)
goto erase_err;
}
diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c
index 21750e1..9c6b15b 100644
--- a/drivers/mtd/ubi/fastmap.c
+++ b/drivers/mtd/ubi/fastmap.c
@@ -581,13 +581,11 @@
struct ubi_ainf_peb *aeb;
struct ubi_ainf_volume *av;
struct rb_node *rb1, *rb2;
- int n = 0;
+ int n;
- list_for_each_entry(aeb, &ai->erase, u.list)
- n++;
+ n = list_count_nodes(&ai->erase);
- list_for_each_entry(aeb, &ai->free, u.list)
- n++;
+ n += list_count_nodes(&ai->free);
ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb)
ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb)
diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c
index e112545..e06f446 100644
--- a/drivers/mux/mmio.c
+++ b/drivers/mux/mmio.c
@@ -31,6 +31,7 @@
static const struct udevice_id mmio_mux_of_match[] = {
{ .compatible = "mmio-mux" },
+ { .compatible = "reg-mux" },
{ /* sentinel */ },
};
@@ -45,7 +46,11 @@
int ret;
int i;
- regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
+ if (ofnode_device_is_compatible(dev_ofnode(dev), "mmio-mux"))
+ regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
+ else
+ regmap_init_mem(dev_ofnode(dev), ®map);
+
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "failed to get regmap: %d\n", ret);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 69ae7c0..e7d0ddf 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -243,6 +243,13 @@
The Synopsys Designware Ethernet QOS IP block with the specific
configuration used in IMX soc.
+config DWC_ETH_QOS_INTEL
+ bool "Synopsys DWC Ethernet QOS device support for Intel"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with the specific
+ configuration used in the Intel Elkhart-Lake soc.
+
config DWC_ETH_QOS_ROCKCHIP
bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
depends on DWC_ETH_QOS
@@ -461,6 +468,7 @@
config FTGMAC100
bool "Ftgmac100 Ethernet Support"
select PHYLIB
+ depends on NET
help
This driver supports the Faraday's FTGMAC100 Gigabit SoC
Ethernet controller that can be found on Aspeed SoCs (which
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 425dd72..4946a63 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
+obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o
obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o
diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c
index f2e4392..2e1f3cd 100644
--- a/drivers/net/aspeed_mdio.c
+++ b/drivers/net/aspeed_mdio.c
@@ -113,6 +113,7 @@
static const struct udevice_id aspeed_mdio_ids[] = {
{ .compatible = "aspeed,ast2600-mdio" },
+ { .compatible = "aspeed,ast2700-mdio" },
{ }
};
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 43f0ec7..3415c41 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -32,6 +32,7 @@
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <errno.h>
#include <eth_phy.h>
#include <log.h>
@@ -1301,6 +1302,13 @@
debug("%s(dev=%p):\n", __func__, dev);
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ pr_err("eqos_get_base_addr_dt failed: %d\n", ret);
+ return ret;
+ }
+ eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
+
ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
if (ret) {
pr_err("reset_get_by_name(rst) failed: %d\n", ret);
@@ -1375,6 +1383,69 @@
return 0;
}
+static int eqos_bind(struct udevice *dev)
+{
+ static int dev_num;
+ const size_t name_sz = 16;
+ char name[name_sz];
+
+ /* Device name defaults to DT node name. */
+ if (ofnode_valid(dev_ofnode(dev)))
+ return 0;
+
+ /* Assign unique names in case there is no DT node. */
+ snprintf(name, name_sz, "eth_eqos#%d", dev_num++);
+ return device_set_name(dev, name);
+}
+
+/*
+ * Get driver data based on the device tree. Boards not using a device tree can
+ * overwrite this function.
+ */
+__weak void *eqos_get_driver_data(struct udevice *dev)
+{
+ return (void *)dev_get_driver_data(dev);
+}
+
+static fdt_addr_t eqos_get_base_addr_common(struct udevice *dev, fdt_addr_t addr)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ if (addr == FDT_ADDR_T_NONE) {
+#if CONFIG_IS_ENABLED(FDT_64BIT)
+ dev_err(dev, "addr=0x%llx is invalid.\n", addr);
+#else
+ dev_err(dev, "addr=0x%x is invalid.\n", addr);
+#endif
+ return -EINVAL;
+ }
+
+ eqos->regs = addr;
+ eqos->mac_regs = (void *)(addr + EQOS_MAC_REGS_BASE);
+ eqos->mtl_regs = (void *)(addr + EQOS_MTL_REGS_BASE);
+ eqos->dma_regs = (void *)(addr + EQOS_DMA_REGS_BASE);
+
+ return 0;
+}
+
+int eqos_get_base_addr_dt(struct udevice *dev)
+{
+ fdt_addr_t addr = dev_read_addr(dev);
+ return eqos_get_base_addr_common(dev, addr);
+}
+
+int eqos_get_base_addr_pci(struct udevice *dev)
+{
+ fdt_addr_t addr;
+ void *paddr;
+
+ paddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
+ PCI_REGION_MEM);
+ addr = paddr ? (fdt_addr_t)paddr : FDT_ADDR_T_NONE;
+
+ return eqos_get_base_addr_common(dev, addr);
+}
+
static int eqos_probe(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1383,17 +1454,12 @@
debug("%s(dev=%p):\n", __func__, dev);
eqos->dev = dev;
- eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = dev_read_addr(dev);
- if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("dev_read_addr() failed\n");
+ eqos->config = eqos_get_driver_data(dev);
+ if (!eqos->config) {
+ pr_err("Failed to get driver data.\n");
return -ENODEV;
}
- eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
- eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
- eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
- eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
@@ -1574,6 +1640,7 @@
.name = "eth_eqos",
.id = UCLASS_ETH,
.of_match = of_match_ptr(eqos_ids),
+ .bind = eqos_bind,
.probe = eqos_probe,
.remove = eqos_remove,
.ops = &eqos_ops,
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index a06390a..ce57e22 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -3,8 +3,11 @@
* Copyright 2022 NXP
*/
-#include <phy_interface.h>
+#include <asm/gpio.h>
+#include <clk.h>
#include <linux/bitops.h>
+#include <phy_interface.h>
+#include <reset.h>
/* Core registers */
@@ -286,7 +289,10 @@
void eqos_flush_desc_generic(void *desc);
void eqos_inval_buffer_generic(void *buf, size_t size);
void eqos_flush_buffer_generic(void *buf, size_t size);
+int eqos_get_base_addr_dt(struct udevice *dev);
+int eqos_get_base_addr_pci(struct udevice *dev);
int eqos_null_ops(struct udevice *dev);
+void *eqos_get_driver_data(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
extern struct eqos_config eqos_rockchip_config;
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index d6bed27..6424328 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -47,6 +47,12 @@
debug("%s(dev=%p):\n", __func__, dev);
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ dev_dbg(dev, "eqos_get_base_addr_dt failed: %d", ret);
+ goto err_probe;
+ }
+
interface = eqos->config->interface(dev);
if (interface == PHY_INTERFACE_MODE_NA) {
diff --git a/drivers/net/dwc_eth_qos_intel.c b/drivers/net/dwc_eth_qos_intel.c
new file mode 100644
index 0000000..a2c6825
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_intel.c
@@ -0,0 +1,449 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023-2024 DENX Software Engineering GmbH
+ * Philip Oberfichtner <pro@denx.de>
+ *
+ * Based on linux v6.6.39, especially drivers/net/ethernet/stmicro/stmmac
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <net.h>
+#include <pci.h>
+
+#include "dwc_eth_qos.h"
+#include "dwc_eth_qos_intel.h"
+
+static struct pci_device_id intel_pci_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_RGMII1G) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII1) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_SGMII2G5) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5) },
+ {}
+};
+
+static int pci_config(struct udevice *dev)
+{
+ u32 val;
+
+ /* Try to enable I/O accesses and bus-mastering */
+ dm_pci_read_config32(dev, PCI_COMMAND, &val);
+ val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ dm_pci_write_config32(dev, PCI_COMMAND, val);
+
+ /* Make sure it worked */
+ dm_pci_read_config32(dev, PCI_COMMAND, &val);
+ if (!(val & PCI_COMMAND_MEMORY)) {
+ dev_err(dev, "%s: Can't enable I/O memory\n", __func__);
+ return -ENOSPC;
+ }
+
+ if (!(val & PCI_COMMAND_MASTER)) {
+ dev_err(dev, "%s: Can't enable bus-mastering\n", __func__);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static void limit_fifo_size(struct udevice *dev)
+{
+ /*
+ * As described in Intel Erratum EHL22, Document Number: 636674-2.1,
+ * the PSE GbE Controllers advertise a wrong RX and TX fifo size.
+ * Software should limit this value to 64KB.
+ */
+ struct eqos_priv *eqos = dev_get_priv(dev);
+
+ eqos->tx_fifo_sz = 0x8000;
+ eqos->rx_fifo_sz = 0x8000;
+}
+
+static int serdes_status_poll(struct udevice *dev,
+ unsigned char phyaddr, unsigned char phyreg,
+ unsigned short mask, unsigned short val)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ unsigned int retries = 10;
+ unsigned short val_rd;
+
+ do {
+ miiphy_read(eqos->mii->name, phyaddr, phyreg, &val_rd);
+ if ((val_rd & mask) == (val & mask))
+ return 0;
+ udelay(POLL_DELAY_US);
+ } while (--retries);
+
+ return -ETIMEDOUT;
+}
+
+ /* Returns -ve if MAC is unknown and 0 on success */
+static int mac_check_pse(const struct udevice *dev, bool *is_pse)
+{
+ struct pci_child_plat *plat = dev_get_parent_plat(dev);
+
+ if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL)
+ return -ENXIO;
+
+ switch (plat->device) {
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5:
+ *is_pse = 1;
+ return 0;
+
+ case PCI_DEVICE_ID_INTEL_EHL_RGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_SGMII1:
+ case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5:
+ *is_pse = 0;
+ return 0;
+ };
+
+ return -ENXIO;
+}
+
+/* Check if we're in 2G5 mode */
+static bool serdes_link_mode_2500(struct udevice *dev)
+{
+ const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR;
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ unsigned short data;
+
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR, &data);
+ if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5)
+ return true;
+
+ return false;
+}
+
+static int serdes_powerup(struct udevice *dev)
+{
+ /* Based on linux/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c */
+
+ const unsigned char phyad = INTEL_MGBE_ADHOC_ADDR;
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ unsigned short data;
+ int ret;
+ bool is_pse;
+
+ /* Set the serdes rate and the PCLK rate */
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
+
+ data &= ~SERDES_RATE_MASK;
+ data &= ~SERDES_PCLK_MASK;
+
+ if (serdes_link_mode_2500(dev))
+ data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
+ else
+ data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
+
+ miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
+
+ /* assert clk_req */
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
+ data |= SERDES_PLL_CLK;
+ miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
+
+ /* check for clk_ack assertion */
+ ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
+ SERDES_PLL_CLK, SERDES_PLL_CLK);
+
+ if (ret) {
+ dev_err(dev, "Serdes PLL clk request timeout\n");
+ return ret;
+ }
+
+ /* assert lane reset*/
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
+ data |= SERDES_RST;
+ miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
+
+ /* check for assert lane reset reflection */
+ ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
+ SERDES_RST, SERDES_RST);
+
+ if (ret) {
+ dev_err(dev, "Serdes assert lane reset timeout\n");
+ return ret;
+ }
+
+ /* move power state to P0 */
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
+ data &= ~SERDES_PWR_ST_MASK;
+ data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
+ miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
+
+ /* Check for P0 state */
+ ret = serdes_status_poll(dev, phyad, SERDES_GSR0,
+ SERDES_PWR_ST_MASK,
+ SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
+
+ if (ret) {
+ dev_err(dev, "Serdes power state P0 timeout.\n");
+ return ret;
+ }
+
+ /* PSE only - ungate SGMII PHY Rx Clock*/
+ ret = mac_check_pse(dev, &is_pse);
+ if (ret) {
+ dev_err(dev, "Failed to determine MAC type.\n");
+ return ret;
+ }
+
+ if (is_pse) {
+ miiphy_read(eqos->mii->name, phyad, SERDES_GCR0, &data);
+ data |= SERDES_PHY_RX_CLK;
+ miiphy_write(eqos->mii->name, phyad, SERDES_GCR0, data);
+ }
+
+ return 0;
+}
+
+static int xpcs_access(struct udevice *dev, int reg, int v)
+{
+ /*
+ * Common read/write helper function
+ *
+ * It may seem a bit odd at a first glance that we use bus->read()
+ * directly insetad of one of the wrapper functions. But:
+ *
+ * (1) phy_read() can't be used because we do not access an acutal PHY,
+ * but a MAC-internal submodule.
+ *
+ * (2) miiphy_read() can't be used because it assumes MDIO_DEVAD_NONE.
+ */
+
+ int port = INTEL_MGBE_XPCS_ADDR;
+ int devad = 0x1f;
+ u16 val;
+ struct eqos_priv *eqos;
+ struct mii_dev *bus;
+
+ eqos = dev_get_priv(dev);
+ bus = eqos->mii;
+
+ if (v < 0)
+ return bus->read(bus, port, devad, reg);
+
+ val = v;
+ return bus->write(bus, port, devad, reg, val);
+}
+
+static int xpcs_read(struct udevice *dev, int reg)
+{
+ return xpcs_access(dev, reg, -1);
+}
+
+static int xpcs_write(struct udevice *dev, int reg, u16 val)
+{
+ return xpcs_access(dev, reg, val);
+}
+
+static int xpcs_clr_bits(struct udevice *dev, int reg, u16 bits)
+{
+ int ret;
+
+ ret = xpcs_read(dev, reg);
+ if (ret < 0)
+ return ret;
+
+ ret &= ~bits;
+
+ return xpcs_write(dev, reg, ret);
+}
+
+static int xpcs_set_bits(struct udevice *dev, int reg, u16 bits)
+{
+ int ret;
+
+ ret = xpcs_read(dev, reg);
+ if (ret < 0)
+ return ret;
+
+ ret |= bits;
+
+ return xpcs_write(dev, reg, ret);
+}
+
+static int xpcs_init(struct udevice *dev)
+{
+ /* Based on linux/drivers/net/pcs/pcs-xpcs.c */
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ phy_interface_t interface = eqos->config->interface(dev);
+
+ if (interface != PHY_INTERFACE_MODE_SGMII)
+ return 0;
+
+ if (xpcs_clr_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN) ||
+ xpcs_set_bits(dev, VR_MII_AN_CTRL, XPCS_MODE_SGMII) ||
+ xpcs_set_bits(dev, VR_MII_DIG_CTRL1, XPCS_MAC_AUTO_SW) ||
+ xpcs_set_bits(dev, VR_MII_MMD_CTRL, XPCS_AN_CL37_EN))
+ return -EIO;
+
+ return 0;
+}
+
+static int eqos_probe_ressources_intel(struct udevice *dev)
+{
+ int ret;
+
+ ret = eqos_get_base_addr_pci(dev);
+ if (ret) {
+ dev_err(dev, "eqos_get_base_addr_pci failed: %d\n", ret);
+ return ret;
+ }
+
+ limit_fifo_size(dev);
+
+ ret = pci_config(dev);
+ if (ret) {
+ dev_err(dev, "pci_config failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct eqos_config eqos_intel_config;
+
+/*
+ * overwrite __weak function from eqos_intel.c
+ *
+ * For PCI devices the devcie tree is optional. Choose driver data based on PCI
+ * IDs instead.
+ */
+void *eqos_get_driver_data(struct udevice *dev)
+{
+ const struct pci_device_id *id;
+ const struct pci_child_plat *plat;
+
+ plat = dev_get_parent_plat(dev);
+
+ if (!plat)
+ return NULL;
+
+ /* last intel_pci_ids element is zero initialized */
+ for (id = intel_pci_ids; id->vendor != 0; id++) {
+ if (id->vendor == plat->vendor && id->device == plat->device)
+ return &eqos_intel_config;
+ }
+
+ return NULL;
+}
+
+static int eqos_start_resets_intel(struct udevice *dev)
+{
+ int ret;
+
+ ret = xpcs_init(dev);
+ if (ret) {
+ dev_err(dev, "xpcs init failed.\n");
+ return ret;
+ }
+
+ ret = serdes_powerup(dev);
+ if (ret) {
+ dev_err(dev, "Failed to power up serdes.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_intel(struct udevice *dev)
+{
+ return 0;
+}
+
+static int eqos_get_enetaddr_intel(struct udevice *dev)
+{
+ /* Assume MAC address is programmed by previous boot stage */
+ struct eth_pdata *plat = dev_get_plat(dev);
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ u8 *lo = (u8 *)&eqos->mac_regs->address0_low;
+ u8 *hi = (u8 *)&eqos->mac_regs->address0_high;
+
+ plat->enetaddr[0] = lo[0];
+ plat->enetaddr[1] = lo[1];
+ plat->enetaddr[2] = lo[2];
+ plat->enetaddr[3] = lo[3];
+ plat->enetaddr[4] = hi[0];
+ plat->enetaddr[5] = hi[1];
+
+ return 0;
+}
+
+static phy_interface_t eqos_get_interface_intel(const struct udevice *dev)
+{
+ struct pci_child_plat *plat = dev_get_parent_plat(dev);
+
+ if (!plat || plat->vendor != PCI_VENDOR_ID_INTEL)
+ return PHY_INTERFACE_MODE_NA;
+
+ switch (plat->device) {
+ /* The GbE Host Controller has no RGMII interface */
+ case PCI_DEVICE_ID_INTEL_EHL_RGMII1G:
+ return PHY_INTERFACE_MODE_NA;
+
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G:
+ return PHY_INTERFACE_MODE_RGMII;
+
+ /* Host SGMII and Host SGMII2G5 share the same device id */
+ case PCI_DEVICE_ID_INTEL_EHL_SGMII1:
+ case PCI_DEVICE_ID_INTEL_EHL_SGMII2G5:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G:
+ case PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5:
+ return PHY_INTERFACE_MODE_SGMII;
+ };
+
+ return PHY_INTERFACE_MODE_NA;
+}
+
+static struct eqos_ops eqos_intel_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_ressources_intel,
+ .eqos_remove_resources = eqos_null_ops,
+ .eqos_stop_resets = eqos_null_ops,
+ .eqos_start_resets = eqos_start_resets_intel,
+ .eqos_stop_clks = eqos_null_ops,
+ .eqos_start_clks = eqos_null_ops,
+ .eqos_calibrate_pads = eqos_null_ops,
+ .eqos_disable_calibration = eqos_null_ops,
+ .eqos_set_tx_clk_speed = eqos_null_ops,
+ .eqos_get_enetaddr = eqos_get_enetaddr_intel,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_intel,
+};
+
+struct eqos_config eqos_intel_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 10,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = eqos_get_interface_intel,
+ .ops = &eqos_intel_ops
+};
+
+extern U_BOOT_DRIVER(eth_eqos);
+U_BOOT_PCI_DEVICE(eth_eqos, intel_pci_ids);
diff --git a/drivers/net/dwc_eth_qos_intel.h b/drivers/net/dwc_eth_qos_intel.h
new file mode 100644
index 0000000..847c75e
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_intel.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2023-2024 DENX Software Engineering GmbH
+ * Philip Oberfichtner <pro@denx.de>
+ *
+ * This header is based on linux v6.6.39,
+ *
+ * drivers/net/pcs/pcs-xpcs.h
+ * drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h,
+ *
+ * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates
+ * Copyright (c) 2020 Intel Corporation
+ */
+
+#ifndef __DWMAC_INTEL_H__
+#define __DWMAC_INTEL_H__
+
+#define POLL_DELAY_US 8
+
+/* SERDES Register */
+#define SERDES_GCR 0x0 /* Global Conguration */
+#define SERDES_GSR0 0x5 /* Global Status Reg0 */
+#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
+
+/* SERDES defines */
+#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
+#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
+#define SERDES_RST BIT(2) /* Serdes Reset */
+#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
+#define SERDES_RATE_MASK GENMASK(9, 8)
+#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
+#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
+#define SERDES_PWR_ST_SHIFT 4
+#define SERDES_PWR_ST_P0 0x0
+#define SERDES_PWR_ST_P3 0x3
+#define SERDES_LINK_MODE_2G5 0x3
+#define SERSED_LINK_MODE_1G 0x2
+#define SERDES_PCLK_37p5MHZ 0x0
+#define SERDES_PCLK_70MHZ 0x1
+#define SERDES_RATE_PCIE_GEN1 0x0
+#define SERDES_RATE_PCIE_GEN2 0x1
+#define SERDES_RATE_PCIE_SHIFT 8
+#define SERDES_PCLK_SHIFT 12
+
+#define INTEL_MGBE_ADHOC_ADDR 0x15
+#define INTEL_MGBE_XPCS_ADDR 0x16
+
+/* XPCS defines */
+#define XPCS_MODE_SGMII BIT(2)
+#define XPCS_MAC_AUTO_SW BIT(9)
+#define XPCS_AN_CL37_EN BIT(12)
+
+#define VR_MII_MMD_CTRL 0x0000
+#define VR_MII_DIG_CTRL1 0x8000
+#define VR_MII_AN_CTRL 0x8001
+
+#endif /* __DWMAC_INTEL_H__ */
diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
index 77d6263..de0ae09 100644
--- a/drivers/net/dwc_eth_qos_qcom.c
+++ b/drivers/net/dwc_eth_qos_qcom.c
@@ -522,6 +522,12 @@
debug("%s(dev=%p):\n", __func__, dev);
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ pr_err("eqos_get_base_addr_dt failed: %d\n", ret);
+ return ret;
+ }
+
interface = eqos->config->interface(dev);
if (interface == PHY_INTERFACE_MODE_NA) {
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index c4557e5..9fc8c68 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -311,6 +311,12 @@
int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
int ret;
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret);
+ return ret;
+ }
+
data = calloc(1, sizeof(struct rockchip_platform_data));
if (!data)
return -ENOMEM;
diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c
index 09e714c..d9ace43 100644
--- a/drivers/net/dwc_eth_qos_starfive.c
+++ b/drivers/net/dwc_eth_qos_starfive.c
@@ -183,6 +183,12 @@
struct starfive_platform_data *data;
int ret;
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ pr_err("eqos_get_base_addr_dt failed: %d\n", ret);
+ return ret;
+ }
+
data = calloc(1, sizeof(struct starfive_platform_data));
if (!data)
return -ENOMEM;
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c
index cffaa10..f3a973f 100644
--- a/drivers/net/dwc_eth_qos_stm32.c
+++ b/drivers/net/dwc_eth_qos_stm32.c
@@ -234,6 +234,12 @@
interface = eqos->config->interface(dev);
+ ret = eqos_get_base_addr_dt(dev);
+ if (ret) {
+ dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret);
+ return ret;
+ }
+
if (interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "Invalid PHY interface\n");
return -EINVAL;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0a0d92b..d6d5cb5 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -615,8 +615,7 @@
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
- fec_open(dev);
- return 0;
+ return fec_open(dev);
}
/**
@@ -818,6 +817,9 @@
return -ENOMEM;
}
+ if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN))
+ return 0;
+
/* Check if any critical events have happened */
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
@@ -1210,10 +1212,13 @@
else if (interface == PHY_INTERFACE_MODE_RGMII ||
interface == PHY_INTERFACE_MODE_RGMII_ID ||
interface == PHY_INTERFACE_MODE_RGMII_RXID ||
- interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ interface == PHY_INTERFACE_MODE_RGMII_TXID) {
freq = 125000000;
- else
+ if (is_imx93())
+ freq = freq << 1;
+ } else {
return -EINVAL;
+ }
ret = clk_set_rate(clk_ref, freq);
if (ret < 0)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 19f3f0f..63fe4b2 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -26,7 +26,8 @@
#include "fm.h"
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
+#if ((defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
+ !defined(CONFIG_BITBANGMII))
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
TBIANA_FULL_DUPLEX)
@@ -701,8 +702,11 @@
supported |= SUPPORTED_2500baseX_Full;
#endif
+#if (CONFIG_IS_ENABLED(MII) || CONFIG_IS_ENABLED(CMD_MII)) && \
+ !CONFIG_IS_ENABLED(BITBANGMII)
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(fm_eth);
+#endif
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_MDIO
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 8781e50..f5ea2e7 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -26,6 +26,7 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/printk.h>
+#include <linux/bitfield.h>
#include "ftgmac100.h"
@@ -57,8 +58,17 @@
enum ftgmac100_model {
FTGMAC100_MODEL_FARADAY,
FTGMAC100_MODEL_ASPEED,
+ FTGMAC100_MODEL_ASPEED_AST2700,
};
+union ftgmac100_dma_addr {
+ dma_addr_t addr;
+ struct {
+ u32 lo;
+ u32 hi;
+ };
+};
+
/**
* struct ftgmac100_data - private data for the FTGMAC100 driver
*
@@ -96,6 +106,8 @@
/* End of RX/TX ring buffer bits. Depend on model */
u32 rxdes0_edorr_mask;
u32 txdes0_edotr_mask;
+
+ bool is_ast2700;
};
/*
@@ -222,7 +234,7 @@
struct phy_device *phydev;
int ret;
- if (IS_ENABLED(CONFIG_DM_MDIO))
+ if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
phydev = dm_eth_phy_connect(dev);
else
phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
@@ -320,8 +332,9 @@
struct eth_pdata *plat = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
+ union ftgmac100_dma_addr dma_addr = {.hi = 0, .lo = 0};
struct phy_device *phydev = priv->phydev;
- unsigned int maccr;
+ unsigned int maccr, dblac, desc_size;
ulong start, end;
int ret;
int i;
@@ -341,6 +354,7 @@
priv->rx_index = 0;
for (i = 0; i < PKTBUFSTX; i++) {
+ priv->txdes[i].txdes2 = 0;
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
@@ -351,7 +365,14 @@
flush_dcache_range(start, end);
for (i = 0; i < PKTBUFSRX; i++) {
- priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+ unsigned int ip_align = 0;
+
+ dma_addr.addr = (dma_addr_t)net_rx_packets[i];
+ priv->rxdes[i].rxdes2 = FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, dma_addr.hi);
+ /* For IP alignment */
+ if ((dma_addr.lo & (PKTALIGN - 1)) == 0)
+ ip_align = 2;
+ priv->rxdes[i].rxdes3 = dma_addr.lo + ip_align;
priv->rxdes[i].rxdes0 = 0;
}
priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
@@ -361,10 +382,25 @@
flush_dcache_range(start, end);
/* transmit ring */
- writel((u32)priv->txdes, &ftgmac100->txr_badr);
+ dma_addr.addr = (dma_addr_t)priv->txdes;
+ writel(dma_addr.lo, &ftgmac100->txr_badr);
+ writel(dma_addr.hi, &ftgmac100->txr_badr_hi);
/* receive ring */
- writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
+ dma_addr.addr = (dma_addr_t)priv->rxdes;
+ writel(dma_addr.lo, &ftgmac100->rxr_badr);
+ writel(dma_addr.hi, &ftgmac100->rxr_badr_hi);
+
+ /* Configure TX/RX decsriptor size
+ * This size is calculated based on cache line.
+ */
+ desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT;
+ /* The descriptor size is at least 2 descriptor units. */
+ if (desc_size < 2)
+ desc_size = 2;
+ dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12);
+ dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size);
+ writel(dblac, &ftgmac100->dblac);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
@@ -382,6 +418,10 @@
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
+ if (priv->is_ast2700 && (priv->phydev->interface == PHY_INTERFACE_MODE_RMII ||
+ priv->phydev->interface == PHY_INTERFACE_MODE_NCSI))
+ maccr |= FTGMAC100_MACCR_RMII_ENABLE;
+
writel(maccr, &ftgmac100->maccr);
ret = phy_startup(phydev);
@@ -410,6 +450,14 @@
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ /*
+ * Make sure there are no stale data in write-back over this area, which
+ * might get written into the memory while the ftgmac100 also writes
+ * into the same memory area.
+ */
+ flush_dcache_range((ulong)net_rx_packets[priv->rx_index],
+ (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN);
+
/* Release buffer to DMA and flush descriptor */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
flush_dcache_range(des_start, des_end);
@@ -431,9 +479,11 @@
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
- ulong data_start = curr_des->rxdes3;
+ union ftgmac100_dma_addr data_start = { .lo = 0, .hi = 0 };
ulong data_end;
+ data_start.hi = FIELD_GET(FTGMAC100_RXDES2_RXBUF_BADR_HI, curr_des->rxdes2);
+ data_start.lo = curr_des->rxdes3;
invalidate_dcache_range(des_start, des_end);
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
@@ -453,9 +503,9 @@
__func__, priv->rx_index, rxlen);
/* Invalidate received data */
- data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
- invalidate_dcache_range(data_start, data_end);
- *packetp = (uchar *)data_start;
+ data_end = data_start.addr + roundup(rxlen, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start.addr, data_end);
+ *packetp = (uchar *)data_start.addr;
return rxlen;
}
@@ -481,6 +531,7 @@
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
+ union ftgmac100_dma_addr dma_addr;
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
@@ -499,10 +550,12 @@
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
- curr_des->txdes3 = (unsigned int)packet;
+ dma_addr.addr = (dma_addr_t)packet;
+ curr_des->txdes2 = FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, dma_addr.hi);
+ curr_des->txdes3 = dma_addr.lo;
/* Flush data to be sent */
- data_start = curr_des->txdes3;
+ data_start = (ulong)dma_addr.addr;
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
flush_dcache_range(data_start, data_end);
@@ -565,6 +618,11 @@
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
priv->rxdes0_edorr_mask = BIT(30);
priv->txdes0_edotr_mask = BIT(30);
+ priv->is_ast2700 = false;
+ } else if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED_AST2700) {
+ priv->rxdes0_edorr_mask = BIT(30);
+ priv->txdes0_edotr_mask = BIT(30);
+ priv->is_ast2700 = true;
} else {
priv->rxdes0_edorr_mask = BIT(15);
priv->txdes0_edotr_mask = BIT(15);
@@ -655,10 +713,11 @@
};
static const struct udevice_id ftgmac100_ids[] = {
- { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
- { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
- { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
- { }
+ { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
+ { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
+ { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
+ { .compatible = "aspeed,ast2700-mac", .data = FTGMAC100_MODEL_ASPEED_AST2700 },
+ {}
};
U_BOOT_DRIVER(ftgmac100) = {
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index f7874ae..c38b57c 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -66,6 +66,13 @@
unsigned int rx_runt; /* 0xc0 */
unsigned int rx_crcer_ftl; /* 0xc4 */
unsigned int rx_col_lost; /* 0xc8 */
+ unsigned int reserved[43]; /* 0xcc - 0x174 */
+ unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */
+ unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */
+ unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */
+ unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */
+ unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */
+ unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */
};
/*
@@ -111,6 +118,7 @@
#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
+#define FTGMAC100_DESC_UNIT 8
#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
#define FTGMAC100_DBLAC_IFG_INC BIT(23)
@@ -157,6 +165,7 @@
#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
#define FTGMAC100_MACCR_FAST_MODE BIT(19)
+#define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */
#define FTGMAC100_MACCR_SW_RST BIT(31)
/*
@@ -183,7 +192,7 @@
unsigned int txdes1;
unsigned int txdes2; /* not used by HW */
unsigned int txdes3; /* TXBUF_BADR */
-} __aligned(16);
+} __aligned(ARCH_DMA_MINALIGN);
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
#define FTGMAC100_TXDES0_EDOTR BIT(15)
@@ -201,6 +210,8 @@
#define FTGMAC100_TXDES1_TX2FIC BIT(30)
#define FTGMAC100_TXDES1_TXIC BIT(31)
+#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16)
+
/*
* Receive descriptor, aligned to 16 bytes
*/
@@ -209,7 +220,7 @@
unsigned int rxdes1;
unsigned int rxdes2; /* not used by HW */
unsigned int rxdes3; /* RXBUF_BADR */
-} __aligned(16);
+} __aligned(ARCH_DMA_MINALIGN);
#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
#define FTGMAC100_RXDES0_EDORR BIT(15)
@@ -240,4 +251,6 @@
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
+#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16)
+
#endif /* __FTGMAC100_H */
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 73064b2..a9efc50 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -368,6 +368,7 @@
config PHY_NCSI
bool "NC-SI based PHY"
+ depends on NET
endif #PHYLIB
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index fe7d108..461805a 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -228,7 +228,6 @@
struct clk tx_clk;
struct clk pclk;
u32 max_speed;
- bool int_pcs;
bool dma_64bit;
u32 clk_en_info;
struct reset_ctl_bulk resets;
@@ -504,8 +503,7 @@
* Set SGMII enable PCS selection only if internal PCS/PMA
* core is used and interface is SGMII.
*/
- if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
- priv->int_pcs) {
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
}
@@ -529,8 +527,7 @@
writel(nwcfg, ®s->nwcfg);
#ifdef CONFIG_ARM64
- if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
- priv->int_pcs) {
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
/*
* Disable AN for fixed link configuration, enable otherwise.
* Must be written after PCS_SEL is set in nwconfig,
@@ -992,8 +989,6 @@
return -EINVAL;
priv->interface = pdata->phy_interface;
- priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
-
priv->clk_en_info = dev_get_driver_data(dev);
return 0;
diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
index 04d8cc2..d88d850 100644
--- a/drivers/pci/pcie_mediatek.c
+++ b/drivers/pci/pcie_mediatek.c
@@ -524,7 +524,7 @@
mtk_pcie_port_free(port);
}
-static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
+static int mtk_pcie_parse_port(struct udevice *dev, u32 slot, int index)
{
struct mtk_pcie *pcie = dev_get_priv(dev);
struct mtk_pcie_port *port;
@@ -545,11 +545,11 @@
if (err)
return err;
- err = reset_get_by_index(dev, slot, &port->reset);
+ err = reset_get_by_index(dev, index, &port->reset);
if (err)
return err;
- err = generic_phy_get_by_index(dev, slot, &port->phy);
+ err = generic_phy_get_by_index(dev, index, &port->phy);
if (err)
return err;
@@ -631,18 +631,58 @@
return 0;
}
+static int mtk_pcie_subsys_get(struct udevice *dev)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ ofnode cfg_node;
+ fdt_addr_t addr;
+
+ cfg_node = ofnode_by_compatible(ofnode_null(),
+ "mediatek,generic-pciecfg");
+ if (!ofnode_valid(cfg_node))
+ return -ENOENT;
+
+ addr = ofnode_get_addr(cfg_node);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ pcie->base = map_physmem(addr, 0, MAP_NOCACHE);
+ if (!pcie->base)
+ return -ENOENT;
+
+ return 0;
+}
+
static int mtk_pcie_probe(struct udevice *dev)
{
struct mtk_pcie *pcie = dev_get_priv(dev);
struct mtk_pcie_port *port, *tmp;
+ bool split_pcie_node = false;
ofnode subnode;
+ unsigned int slot;
int err;
INIT_LIST_HEAD(&pcie->ports);
- pcie->base = dev_remap_addr_name(dev, "subsys");
- if (!pcie->base)
- return -ENOENT;
+ /* Check if upstream implementation is used */
+ err = mtk_pcie_subsys_get(dev);
+ if (!err) {
+ /*
+ * Assume split port node implementation with "mediatek,generic-pciecfg"
+ * found. We check reg-names and check if the node is for port0 or port1.
+ */
+ split_pcie_node = true;
+ if (!strcmp(dev_read_string(dev, "reg-names"), "port0"))
+ slot = 0;
+ else if (!strcmp(dev_read_string(dev, "reg-names"), "port1"))
+ slot = 1;
+ else
+ return -EINVAL;
+ } else {
+ pcie->base = dev_remap_addr_name(dev, "subsys");
+ if (!pcie->base)
+ return -ENOENT;
+ }
err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
if (err)
@@ -653,20 +693,27 @@
if (err)
return err;
- dev_for_each_subnode(subnode, dev) {
- struct fdt_pci_addr addr;
- u32 slot = 0;
+ if (!split_pcie_node) {
+ dev_for_each_subnode(subnode, dev) {
+ struct fdt_pci_addr addr;
- if (!ofnode_is_enabled(subnode))
- continue;
+ slot = 0;
- err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
- if (err)
- return err;
+ if (!ofnode_is_enabled(subnode))
+ continue;
- slot = PCI_DEV(addr.phys_hi);
+ err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
+ if (err)
+ return err;
- err = mtk_pcie_parse_port(dev, slot);
+ slot = PCI_DEV(addr.phys_hi);
+
+ err = mtk_pcie_parse_port(dev, slot, slot);
+ if (err)
+ return err;
+ }
+ } else {
+ err = mtk_pcie_parse_port(dev, slot, 0);
if (err)
return err;
}
@@ -682,28 +729,54 @@
{
struct mtk_pcie *pcie = dev_get_priv(dev);
struct mtk_pcie_port *port, *tmp;
- struct fdt_pci_addr addr;
+ bool split_pcie_node = false;
ofnode subnode;
unsigned int slot;
int err;
INIT_LIST_HEAD(&pcie->ports);
- pcie->base = dev_remap_addr_name(dev, "subsys");
- if (!pcie->base)
- return -ENOENT;
+ /* Check if upstream implementation is used */
+ err = mtk_pcie_subsys_get(dev);
+ if (!err) {
+ /*
+ * Assume split port node implementation with "mediatek,generic-pciecfg"
+ * found. We check reg-names and check if the node is for port0 or port1.
+ */
+ split_pcie_node = true;
+ if (!strcmp(dev_read_string(dev, "reg-names"), "port0"))
+ slot = 0;
+ else if (!strcmp(dev_read_string(dev, "reg-names"), "port1"))
+ slot = 1;
+ else
+ return -EINVAL;
+ } else {
+ pcie->base = dev_remap_addr_name(dev, "subsys");
+ if (!pcie->base)
+ return -ENOENT;
+ }
pcie->priv = dev;
- dev_for_each_subnode(subnode, dev) {
- if (!ofnode_is_enabled(subnode))
- continue;
+ if (!split_pcie_node) {
+ dev_for_each_subnode(subnode, dev) {
+ struct fdt_pci_addr addr;
- err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
- if (err)
- return err;
+ slot = 0;
+
+ if (!ofnode_is_enabled(subnode))
+ continue;
+
+ err = ofnode_read_pci_addr(subnode, 0, "reg", &addr, NULL);
+ if (err)
+ return err;
- slot = PCI_DEV(addr.phys_hi);
+ slot = PCI_DEV(addr.phys_hi);
+ err = mtk_pcie_parse_port_v2(dev, slot);
+ if (err)
+ return err;
+ }
+ } else {
err = mtk_pcie_parse_port_v2(dev, slot);
if (err)
return err;
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index f5e23f3..2c9d5a1 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -1126,7 +1126,7 @@
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
- dev_info(dev, "sierra probed\n");
+ dev_dbg(dev, "sierra probed\n");
return 0;
clk_disable:
diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c
index 7c292ca..b278f99 100644
--- a/drivers/phy/phy-rcar-gen3.c
+++ b/drivers/phy/phy-rcar-gen3.c
@@ -8,6 +8,7 @@
#include <clk.h>
#include <div64.h>
#include <dm.h>
+#include <dm/device_compat.h>
#include <fdtdec.h>
#include <generic-phy.h>
#include <malloc.h>
@@ -31,8 +32,13 @@
#define USB2_LINECTRL1 0x610
#define USB2_ADPCTRL 0x630
+/* INT_ENABLE */
+#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
+#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
+#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
+
/* USBCTR */
-#define USB2_USBCTR_PLL_RST BIT(1)
+#define USB2_USBCTR_PLL_RST BIT(1)
/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
@@ -43,11 +49,23 @@
/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
+/* OBINTSTA and OBINTEN */
+#define USB2_OBINT_SESSVLDCHG BIT(12)
+#define USB2_OBINT_IDDIGCHG BIT(11)
+
+/* VBCTRL */
+#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+
/* LINECTRL1 */
+#define USB2_LINECTRL1_DPRPD_EN BIT(19)
#define USB2_LINECTRL1_DP_RPD BIT(18)
+#define USB2_LINECTRL1_DMRPD_EN BIT(17)
#define USB2_LINECTRL1_DM_RPD BIT(16)
/* ADPCTRL */
+#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
+#define USB2_ADPCTRL_IDDIG BIT(19)
+#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
struct rcar_gen3_phy {
@@ -65,12 +83,14 @@
writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
- setbits_le32(priv->regs + USB2_LINECTRL1,
- USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
+ return 0;
+}
- clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
+static int rcar_gen3_phy_phy_exit(struct phy *phy)
+{
+ struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
- setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+ writel(0, priv->regs + USB2_INT_ENABLE);
return 0;
}
@@ -102,10 +122,70 @@
return regulator_set_enable(priv->vbus_supply, false);
}
+static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
+ struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+ u32 adpctrl;
+
+ if (mode == PHY_MODE_USB_OTG) {
+ if (submode) {
+ /* OTG submode is used as initialization indicator */
+ writel(USB2_INT_ENABLE_UCOM_INTEN |
+ USB2_INT_ENABLE_USBH_INTB_EN |
+ USB2_INT_ENABLE_USBH_INTA_EN,
+ priv->regs + USB2_INT_ENABLE);
+ setbits_le32(priv->regs + USB2_VBCTRL,
+ USB2_VBCTRL_DRVVBUSSEL);
+ writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG,
+ priv->regs + USB2_OBINTSTA);
+ setbits_le32(priv->regs + USB2_OBINTEN,
+ USB2_OBINT_SESSVLDCHG |
+ USB2_OBINT_IDDIGCHG);
+ setbits_le32(priv->regs + USB2_ADPCTRL,
+ USB2_ADPCTRL_IDPULLUP);
+ clrsetbits_le32(priv->regs + USB2_LINECTRL1,
+ USB2_LINECTRL1_DP_RPD |
+ USB2_LINECTRL1_DM_RPD |
+ USB2_LINECTRL1_DPRPD_EN |
+ USB2_LINECTRL1_DMRPD_EN,
+ USB2_LINECTRL1_DPRPD_EN |
+ USB2_LINECTRL1_DMRPD_EN);
+ }
+
+ adpctrl = readl(priv->regs + USB2_ADPCTRL);
+ if ((adpctrl & adpdevmask) == adpdevmask)
+ mode = PHY_MODE_USB_DEVICE;
+ else
+ mode = PHY_MODE_USB_HOST;
+ }
+
+ if (mode == PHY_MODE_USB_HOST) {
+ clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
+ setbits_le32(priv->regs + USB2_LINECTRL1,
+ USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
+ setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+ } else if (mode == PHY_MODE_USB_DEVICE) {
+ setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
+ clrsetbits_le32(priv->regs + USB2_LINECTRL1,
+ USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD,
+ USB2_LINECTRL1_DM_RPD);
+ clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+ } else {
+ dev_err(phy->dev, "Unknown mode %d\n", mode);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct phy_ops rcar_gen3_phy_phy_ops = {
.init = rcar_gen3_phy_phy_init,
+ .exit = rcar_gen3_phy_phy_exit,
.power_on = rcar_gen3_phy_phy_power_on,
.power_off = rcar_gen3_phy_phy_power_off,
+ .set_mode = rcar_gen3_phy_phy_set_mode,
};
static int rcar_gen3_phy_probe(struct udevice *dev)
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index acdcda1..777d952 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -508,7 +508,8 @@
return ret;
}
-int generic_setup_phy(struct udevice *dev, struct phy *phy, int index)
+int generic_setup_phy(struct udevice *dev, struct phy *phy, int index,
+ enum phy_mode mode, int submode)
{
int ret;
@@ -520,10 +521,18 @@
if (ret)
return ret;
+ ret = generic_phy_set_mode(phy, mode, submode);
+ if (ret)
+ goto phys_mode_err;
+
ret = generic_phy_power_on(phy);
if (ret)
- generic_phy_exit(phy);
+ goto phys_mode_err;
+
+ return 0;
+phys_mode_err:
+ generic_phy_exit(phy);
return ret;
}
diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c
index b159147..e70d204 100644
--- a/drivers/phy/sandbox-phy.c
+++ b/drivers/phy/sandbox-phy.c
@@ -72,6 +72,18 @@
return 0;
}
+static int
+sandbox_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ if (submode)
+ return -EOPNOTSUPP;
+
+ if (mode != PHY_MODE_USB_HOST)
+ return -EINVAL;
+
+ return 0;
+}
+
static int sandbox_phy_bind(struct udevice *dev)
{
if (dev_get_driver_data(dev) != DRIVER_DATA)
@@ -96,6 +108,7 @@
.power_off = sandbox_phy_power_off,
.init = sandbox_phy_init,
.exit = sandbox_phy_exit,
+ .set_mode = sandbox_phy_set_mode,
};
static const struct udevice_id sandbox_phy_ids[] = {
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index ff49819..67e564f 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -48,6 +48,7 @@
#define GPIO_OES 0x70 /* Output Enable Set */
#define GPIO_OEC 0x74 /* Output Enable Clear */
+#define NPCM8XX_NUM_GPIO_BANK 8
#define NPCM8XX_GPIO_PER_BANK 32
#define GPIOX_OFFSET 16
@@ -967,6 +968,18 @@
}
#endif
+static void npcm8xx_pinctrl_clear_events(struct npcm8xx_pinctrl_priv *priv)
+{
+ void __iomem *base;
+ int i;
+
+ for (i = 0; i < NPCM8XX_NUM_GPIO_BANK; i++) {
+ base = priv->gpio_base + (0x1000 * i);
+ clrbits_le32(base + GPIO_EVEN, 0xFFFFFFFF);
+ setbits_le32(base + GPIO_EVST, 0xFFFFFFFF);
+ }
+}
+
static struct pinctrl_ops npcm8xx_pinctrl_ops = {
.set_state = pinctrl_generic_set_state,
.get_pins_count = npcm8xx_get_pins_count,
@@ -1001,6 +1014,11 @@
if (IS_ERR(priv->rst_regmap))
return -EINVAL;
+ /*
+ * Clear all previous gpio events, otherwise it may produce
+ * unexpected interrupts during kernel booting.
+ */
+ npcm8xx_pinctrl_clear_events(priv);
return 0;
}
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
index 2464acf..81a9327 100644
--- a/drivers/pinctrl/pinctrl-generic.c
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -22,7 +22,7 @@
if (!ops->get_pins_count || !ops->get_pin_name) {
dev_dbg(dev, "get_pins_count or get_pin_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
npins = ops->get_pins_count(dev);
@@ -35,7 +35,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -53,7 +53,7 @@
if (!ops->get_groups_count || !ops->get_group_name) {
dev_dbg(dev, "get_groups_count or get_group_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
ngroups = ops->get_groups_count(dev);
@@ -66,7 +66,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
#if CONFIG_IS_ENABLED(PINMUX)
@@ -86,7 +86,7 @@
if (!ops->get_functions_count || !ops->get_function_name) {
dev_dbg(dev,
"get_functions_count or get_function_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
nfuncs = ops->get_functions_count(dev);
@@ -99,7 +99,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -119,14 +119,14 @@
if (is_group) {
if (!ops->pinmux_group_set) {
dev_dbg(dev, "pinmux_group_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinmux_group_set(dev, selector, func_selector);
} else {
if (!ops->pinmux_set) {
dev_dbg(dev, "pinmux_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinmux_set(dev, selector, func_selector);
}
@@ -162,7 +162,7 @@
if (!ops->pinconf_num_params || !ops->pinconf_params) {
dev_dbg(dev, "pinconf_num_params or pinconf_params missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
p = ops->pinconf_params;
@@ -176,7 +176,7 @@
}
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -198,7 +198,7 @@
if (is_group) {
if (!ops->pinconf_group_set) {
dev_dbg(dev, "pinconf_group_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinconf_group_set(dev, selector, param,
@@ -206,7 +206,7 @@
} else {
if (!ops->pinconf_set) {
dev_dbg(dev, "pinconf_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinconf_set(dev, selector, param, argument);
}
@@ -215,7 +215,7 @@
static int pinconf_prop_name_to_param(struct udevice *dev,
const char *property, u32 *default_value)
{
- return -ENOSYS;
+ return -ENOENT;
}
static int pinconf_enable_setting(struct udevice *dev, bool is_group,
diff --git a/drivers/pinctrl/pinctrl-sandbox.c b/drivers/pinctrl/pinctrl-sandbox.c
index a5d0566..f6921b5 100644
--- a/drivers/pinctrl/pinctrl-sandbox.c
+++ b/drivers/pinctrl/pinctrl-sandbox.c
@@ -42,7 +42,7 @@
{ "GPIO0", "SPI CS0" },
{ "GPIO1", "SPI CS1" },
{ "GPIO2", "PWM0" },
- { "GPIO3", "PWM1" },
+ { "GPIO3", "ONEWIRE" },
};
#define SANDBOX_GROUP_I2C_UART 0
@@ -63,6 +63,7 @@
FUNC(GPIO),
FUNC(CS),
FUNC(PWM),
+ FUNC(ONEWIRE),
#undef FUNC
};
@@ -166,6 +167,7 @@
break;
case SANDBOX_PINMUX_CS:
case SANDBOX_PINMUX_PWM:
+ case SANDBOX_PINMUX_ONEWIRE:
mux = BIT(pin_selector);
break;
default:
diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
index a871fc4..c2fc1c6 100644
--- a/drivers/power/power_i2c.c
+++ b/drivers/power/power_i2c.c
@@ -33,8 +33,6 @@
p->bus);
return -ENXIO;
}
-#else /* Non DM I2C support - will be removed */
- I2C_SET_BUS(p->bus);
#endif
switch (pmic_i2c_tx_num) {
@@ -93,9 +91,6 @@
return -ENXIO;
}
ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num);
-#else /* Non DM I2C support - will be removed */
- I2C_SET_BUS(p->bus);
- ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
#endif
if (ret)
return ret;
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index bc061c2..958f337 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -383,6 +383,15 @@
features for TPS80031/TPS80032 PMICs. The driver implements
get/set api for: value and enable.
+config DM_REGULATOR_TPS6287X
+ bool "Enable driver for TPS6287x Power Regulator"
+ depends on DM_REGULATOR
+ help
+ The TPS6287X is a step down converter with a fast transient
+ response. This driver supports all four variants of the chip
+ (TPS62870, TPS62871, TPS62872, TPS62873). It implements the
+ get/set api for value only, as the power line is always on.
+
config DM_REGULATOR_STPMIC1
bool "Enable driver for STPMIC1 regulators"
depends on DM_REGULATOR && PMIC_STPMIC1
@@ -402,6 +411,15 @@
regulators. It is recommended that this option be enabled on
i.MX6 platform.
+config SPL_DM_REGULATOR_TPS6287X
+ bool "Enable driver for TPS6287x Power Regulator"
+ depends on SPL_DM_REGULATOR
+ help
+ The TPS6287X is a step down converter with a fast transient
+ response. This driver supports all four variants of the chip
+ (TPS62870, TPS62871, TPS62872, TPS62873). It implements the
+ get/set api for value only, as the power line is always on.
+
config SPL_DM_REGULATOR_STPMIC1
bool "Enable driver for STPMIC1 regulators in SPL"
depends on SPL_DM_REGULATOR && PMIC_STPMIC1
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 56a5276..54db088 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -35,6 +35,7 @@
obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o
obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS6287X) += tps6287x_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c
index 98c89bf..996da41 100644
--- a/drivers/power/regulator/fixed.c
+++ b/drivers/power/regulator/fixed.c
@@ -17,7 +17,7 @@
#include "regulator_common.h"
-struct fixed_clock_regulator_plat {
+struct fixed_clock_regulator_priv {
struct clk *enable_clock;
unsigned int clk_enable_counter;
};
@@ -83,14 +83,14 @@
static int fixed_clock_regulator_get_enable(struct udevice *dev)
{
- struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
+ struct fixed_clock_regulator_priv *priv = dev_get_priv(dev);
return priv->clk_enable_counter > 0;
}
static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable)
{
- struct fixed_clock_regulator_plat *priv = dev_get_priv(dev);
+ struct fixed_clock_regulator_priv *priv = dev_get_priv(dev);
struct regulator_common_plat *plat = dev_get_plat(dev);
int ret = 0;
@@ -113,6 +113,17 @@
return ret;
}
+static int fixed_clock_regulator_probe(struct udevice *dev)
+{
+ struct fixed_clock_regulator_priv *priv = dev_get_priv(dev);
+
+ priv->enable_clock = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->enable_clock))
+ return PTR_ERR(priv->enable_clock);
+
+ return 0;
+}
+
static const struct dm_regulator_ops fixed_regulator_ops = {
.get_value = fixed_regulator_get_value,
.get_current = fixed_regulator_get_current,
@@ -149,6 +160,8 @@
.id = UCLASS_REGULATOR,
.ops = &fixed_clock_regulator_ops,
.of_match = fixed_clock_regulator_ids,
+ .probe = fixed_clock_regulator_probe,
.of_to_plat = fixed_regulator_of_to_plat,
- .plat_auto = sizeof(struct fixed_clock_regulator_plat),
+ .plat_auto = sizeof(struct regulator_common_plat),
+ .priv_auto = sizeof(struct fixed_clock_regulator_priv),
};
diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c
index 06fd3f3..2dc261d 100644
--- a/drivers/power/regulator/qcom-rpmh-regulator.c
+++ b/drivers/power/regulator/qcom-rpmh-regulator.c
@@ -357,6 +357,69 @@
.get_mode = rpmh_regulator_vrm_get_mode,
};
+static struct dm_regulator_mode pmic_mode_map_pmic5_bob[] = {
+ {
+ .id = REGULATOR_MODE_LPM,
+ .register_value = PMIC5_BOB_MODE_PFM,
+ .name = "PMIC5_BOB_MODE_PFM"
+ }, {
+ .id = REGULATOR_MODE_AUTO,
+ .register_value = PMIC5_BOB_MODE_AUTO,
+ .name = "PMIC5_BOB_MODE_AUTO"
+ }, {
+ .id = REGULATOR_MODE_HPM,
+ .register_value = PMIC5_BOB_MODE_PWM,
+ .name = "PMIC5_BOB_MODE_PWM"
+ },
+};
+
+static struct dm_regulator_mode pmic_mode_map_pmic5_smps[] = {
+ {
+ .id = REGULATOR_MODE_RETENTION,
+ .register_value = PMIC5_SMPS_MODE_RETENTION,
+ .name = "PMIC5_SMPS_MODE_RETENTION"
+ }, {
+ .id = REGULATOR_MODE_LPM,
+ .register_value = PMIC5_SMPS_MODE_PFM,
+ .name = "PMIC5_SMPS_MODE_PFM"
+ }, {
+ .id = REGULATOR_MODE_AUTO,
+ .register_value = PMIC5_SMPS_MODE_AUTO,
+ .name = "PMIC5_SMPS_MODE_AUTO"
+ }, {
+ .id = REGULATOR_MODE_HPM,
+ .register_value = PMIC5_SMPS_MODE_PWM,
+ .name = "PMIC5_SMPS_MODE_PWM"
+ },
+};
+
+static const struct rpmh_vreg_hw_data pmic5_bob = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_range = REGULATOR_LINEAR_RANGE(3000000, 0, 31, 32000),
+ .n_voltages = 32,
+ .pmic_mode_map = pmic_mode_map_pmic5_bob,
+ .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_bob),
+};
+
+static const struct rpmh_vreg_hw_data pmic5_ftsmps525_lv = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_range = REGULATOR_LINEAR_RANGE(300000, 0, 267, 4000),
+ .n_voltages = 268,
+ .pmic_mode_map = pmic_mode_map_pmic5_smps,
+ .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps),
+};
+
+static const struct rpmh_vreg_hw_data pmic5_ftsmps525_mv = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_range = REGULATOR_LINEAR_RANGE(600000, 0, 267, 8000),
+ .n_voltages = 268,
+ .pmic_mode_map = pmic_mode_map_pmic5_smps,
+ .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_smps),
+};
+
static struct dm_regulator_mode pmic_mode_map_pmic5_ldo[] = {
{
.id = REGULATOR_MODE_RETENTION,
@@ -393,6 +456,16 @@
.n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo),
};
+static const struct rpmh_vreg_hw_data pmic5_nldo515 = {
+ .regulator_type = VRM,
+ .ops = &rpmh_regulator_vrm_drms_ops,
+ .voltage_range = REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000),
+ .n_voltages = 211,
+ .hpm_min_load_uA = 30000,
+ .pmic_mode_map = pmic_mode_map_pmic5_ldo,
+ .n_modes = ARRAY_SIZE(pmic_mode_map_pmic5_ldo),
+};
+
#define RPMH_VREG(_name, _resource_name, _hw_data, _supply_name) \
{ \
.name = _name, \
@@ -412,6 +485,57 @@
{}
};
+static const struct rpmh_vreg_init_data pm8550_vreg_data[] = {
+ RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo5", "ldo%s5", &pmic5_pldo, "vdd-l5-l16"),
+ RPMH_VREG("ldo6", "ldo%s6", &pmic5_pldo, "vdd-l6-l7"),
+ RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo, "vdd-l6-l7"),
+ RPMH_VREG("ldo8", "ldo%s8", &pmic5_pldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo9", "ldo%s9", &pmic5_pldo, "vdd-l8-l9"),
+ RPMH_VREG("ldo10", "ldo%s10", &pmic5_nldo515, "vdd-l1-l4-l10"),
+ RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
+ RPMH_VREG("ldo12", "ldo%s12", &pmic5_nldo515, "vdd-l12"),
+ RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo, "vdd-l2-l13-l14"),
+ RPMH_VREG("ldo15", "ldo%s15", &pmic5_nldo515, "vdd-l15"),
+ RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l5-l16"),
+ RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l17"),
+ RPMH_VREG("bob1", "bob%s1", &pmic5_bob, "vdd-bob1"),
+ RPMH_VREG("bob2", "bob%s2", &pmic5_bob, "vdd-bob2"),
+ {}
+};
+
+static const struct rpmh_vreg_init_data pm8550vs_vreg_data[] = {
+ RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"),
+ RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"),
+ RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"),
+ RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_lv, "vdd-s4"),
+ RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"),
+ RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_mv, "vdd-s6"),
+ RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
+ RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ {}
+};
+
+static const struct rpmh_vreg_init_data pm8550ve_vreg_data[] = {
+ RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps525_lv, "vdd-s1"),
+ RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps525_lv, "vdd-s2"),
+ RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps525_lv, "vdd-s3"),
+ RPMH_VREG("smps4", "smp%s4", &pmic5_ftsmps525_mv, "vdd-s4"),
+ RPMH_VREG("smps5", "smp%s5", &pmic5_ftsmps525_lv, "vdd-s5"),
+ RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps525_lv, "vdd-s6"),
+ RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps525_lv, "vdd-s7"),
+ RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps525_lv, "vdd-s8"),
+ RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo515, "vdd-l1"),
+ RPMH_VREG("ldo2", "ldo%s2", &pmic5_nldo515, "vdd-l2"),
+ RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo515, "vdd-l3"),
+ {}
+};
+
/* probe an individual regulator */
static int rpmh_regulator_probe(struct udevice *dev)
{
@@ -526,6 +650,18 @@
.compatible = "qcom,pm8150l-rpmh-regulators",
.data = (ulong)pm8150l_vreg_data,
},
+ {
+ .compatible = "qcom,pm8550-rpmh-regulators",
+ .data = (ulong)pm8550_vreg_data,
+ },
+ {
+ .compatible = "qcom,pm8550ve-rpmh-regulators",
+ .data = (ulong)pm8550ve_vreg_data,
+ },
+ {
+ .compatible = "qcom,pm8550vs-rpmh-regulators",
+ .data = (ulong)pm8550vs_vreg_data,
+ },
{ /* sentinal */ },
};
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 88a8525..decd080 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -55,14 +55,16 @@
struct dm_regulator_uclass_plat *uc_pdata;
int ret, old_uV = uV, is_enabled = 0;
+ if (!ops || !ops->set_value)
+ return -ENOSYS;
+
uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
return -EINVAL;
if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
return -EINVAL;
-
- if (!ops || !ops->set_value)
- return -ENOSYS;
+ if (uV == -ENODATA)
+ return -EINVAL;
if (uc_pdata->ramp_delay) {
is_enabled = regulator_get_enable(dev);
@@ -85,14 +87,16 @@
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
struct dm_regulator_uclass_plat *uc_pdata;
+ if (!ops || !ops->set_suspend_value)
+ return -ENOSYS;
+
uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uV != -ENODATA && uV < uc_pdata->min_uV)
return -EINVAL;
if (uc_pdata->max_uV != -ENODATA && uV > uc_pdata->max_uV)
return -EINVAL;
-
- if (!ops->set_suspend_value)
- return -ENOSYS;
+ if (uV == -ENODATA)
+ return -EINVAL;
return ops->set_suspend_value(dev, uV);
}
@@ -101,7 +105,7 @@
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- if (!ops->get_suspend_value)
+ if (!ops || !ops->get_suspend_value)
return -ENOSYS;
return ops->get_suspend_value(dev);
@@ -136,14 +140,16 @@
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
struct dm_regulator_uclass_plat *uc_pdata;
+ if (!ops || !ops->set_current)
+ return -ENOSYS;
+
uc_pdata = dev_get_uclass_plat(dev);
if (uc_pdata->min_uA != -ENODATA && uA < uc_pdata->min_uA)
return -EINVAL;
if (uc_pdata->max_uA != -ENODATA && uA > uc_pdata->max_uA)
return -EINVAL;
-
- if (!ops || !ops->set_current)
- return -ENOSYS;
+ if (uA == -ENODATA)
+ return -EINVAL;
return ops->set_current(dev, uA);
}
@@ -210,7 +216,7 @@
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- if (!ops->set_suspend_enable)
+ if (!ops || !ops->set_suspend_enable)
return -ENOSYS;
return ops->set_suspend_enable(dev, enable);
@@ -220,7 +226,7 @@
{
const struct dm_regulator_ops *ops = dev_get_driver_ops(dev);
- if (!ops->get_suspend_enable)
+ if (!ops || !ops->get_suspend_enable)
return -ENOSYS;
return ops->get_suspend_enable(dev);
@@ -299,7 +305,7 @@
if (ret == -ENOSYS)
ret = 0;
- if (!ret && uc_pdata->suspend_on) {
+ if (!ret && uc_pdata->suspend_on && uc_pdata->suspend_uV != -ENODATA) {
ret = regulator_set_suspend_value(dev, uc_pdata->suspend_uV);
if (ret == -ENOSYS)
ret = 0;
@@ -308,6 +314,11 @@
return ret;
}
+ if (uc_pdata->force_off) {
+ ret = regulator_set_enable(dev, false);
+ goto out;
+ }
+
if (!uc_pdata->always_on && !uc_pdata->boot_on) {
ret = -EMEDIUMTYPE;
goto out;
@@ -334,17 +345,6 @@
return ret;
}
-int regulator_unset(struct udevice *dev)
-{
- struct dm_regulator_uclass_plat *uc_pdata;
-
- uc_pdata = dev_get_uclass_plat(dev);
- if (uc_pdata && uc_pdata->force_off)
- return regulator_set_enable(dev, false);
-
- return -EMEDIUMTYPE;
-}
-
static void regulator_show(struct udevice *dev, int ret)
{
struct dm_regulator_uclass_plat *uc_pdata;
@@ -433,6 +433,8 @@
const char *property = "regulator-name";
uc_pdata = dev_get_uclass_plat(dev);
+ uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on");
+ uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
/* Regulator's mandatory constraint */
uc_pdata->name = dev_read_string(dev, property);
@@ -444,13 +446,21 @@
return -EINVAL;
}
- if (regulator_name_is_unique(dev, uc_pdata->name))
- return 0;
+ if (!regulator_name_is_unique(dev, uc_pdata->name)) {
+ debug("'%s' of dev: '%s', has nonunique value: '%s\n",
+ property, dev->name, uc_pdata->name);
+ return -EINVAL;
+ }
- debug("'%s' of dev: '%s', has nonunique value: '%s\n",
- property, dev->name, uc_pdata->name);
+ /*
+ * In case the regulator has regulator-always-on or
+ * regulator-boot-on DT property, trigger probe() to
+ * configure its default state during startup.
+ */
+ if (uc_pdata->always_on || uc_pdata->boot_on)
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
- return -EINVAL;
+ return 0;
}
static int regulator_pre_probe(struct udevice *dev)
@@ -473,8 +483,6 @@
-ENODATA);
uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp",
-ENODATA);
- uc_pdata->always_on = dev_read_bool(dev, "regulator-always-on");
- uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
@@ -504,56 +512,18 @@
return 0;
}
-int regulators_enable_boot_on(bool verbose)
+static int regulator_post_probe(struct udevice *dev)
{
- struct udevice *dev;
- struct uclass *uc;
int ret;
- ret = uclass_get(UCLASS_REGULATOR, &uc);
- if (ret)
+ ret = regulator_autoset(dev);
+ if (ret && ret != -EMEDIUMTYPE && ret != -EALREADY && ret != ENOSYS)
return ret;
- for (uclass_first_device(UCLASS_REGULATOR, &dev);
- dev;
- uclass_next_device(&dev)) {
- ret = regulator_autoset(dev);
- if (ret == -EMEDIUMTYPE || ret == -EALREADY) {
- ret = 0;
- continue;
- }
- if (verbose)
- regulator_show(dev, ret);
- if (ret == -ENOSYS)
- ret = 0;
- }
-
- return ret;
-}
-
-int regulators_enable_boot_off(bool verbose)
-{
- struct udevice *dev;
- struct uclass *uc;
- int ret;
- ret = uclass_get(UCLASS_REGULATOR, &uc);
- if (ret)
- return ret;
- for (uclass_first_device(UCLASS_REGULATOR, &dev);
- dev;
- uclass_next_device(&dev)) {
- ret = regulator_unset(dev);
- if (ret == -EMEDIUMTYPE) {
- ret = 0;
- continue;
- }
- if (verbose)
- regulator_show(dev, ret);
- if (ret == -ENOSYS)
- ret = 0;
- }
+ if (_DEBUG)
+ regulator_show(dev, ret);
- return ret;
+ return 0;
}
UCLASS_DRIVER(regulator) = {
@@ -561,5 +531,6 @@
.name = "regulator",
.post_bind = regulator_post_bind,
.pre_probe = regulator_pre_probe,
+ .post_probe = regulator_post_probe,
.per_device_plat_auto = sizeof(struct dm_regulator_uclass_plat),
};
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index 34e6151..375d06e 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -381,7 +381,7 @@
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
- __func__, uvolt, buck + 1, info->vsel_reg, mask, val);
+ __func__, uvolt, buck, info->vsel_reg, mask, val);
if (priv->variant == RK816_ID) {
pmic_clrsetbits(pmic, info->vsel_reg, mask, val);
@@ -415,7 +415,7 @@
break;
case RK806_ID:
value = RK806_POWER_EN_CLRSETBITS(buck % 4, enable);
- en_reg = RK806_POWER_EN((buck + 1) / 4);
+ en_reg = RK806_POWER_EN(buck / 4);
ret = pmic_reg_write(pmic, en_reg, value);
break;
case RK808_ID:
@@ -470,7 +470,7 @@
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
debug("%s: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
- __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val);
+ __func__, uvolt, buck, info->vsel_sleep_reg, mask, val);
return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val);
}
@@ -494,7 +494,7 @@
break;
case RK806_ID:
mask = BIT(buck % 4);
- ret = pmic_reg_read(pmic, RK806_POWER_EN((buck + 1) / 4));
+ ret = pmic_reg_read(pmic, RK806_POWER_EN(buck / 4));
break;
case RK808_ID:
case RK818_ID:
@@ -539,12 +539,13 @@
{
u8 reg;
- if (buck + 1 >= 9) {
+ if (buck >= 8) {
+ /* BUCK9 and BUCK10 */
reg = RK806_POWER_SLP_EN1;
- mask = BIT(buck + 1 - 3);
+ mask = BIT(buck - 2);
} else {
reg = RK806_POWER_SLP_EN0;
- mask = BIT(buck + 1);
+ mask = BIT(buck);
}
ret = pmic_clrsetbits(pmic, reg, mask, enable ? mask : 0);
}
@@ -590,12 +591,13 @@
{
u8 reg;
- if (buck + 1 >= 9) {
+ if (buck >= 8) {
+ /* BUCK9 and BUCK10 */
reg = RK806_POWER_SLP_EN1;
- mask = BIT(buck + 1 - 3);
+ mask = BIT(buck - 2);
} else {
reg = RK806_POWER_SLP_EN0;
- mask = BIT(buck + 1);
+ mask = BIT(buck);
}
val = pmic_reg_read(pmic, reg);
}
diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c
new file mode 100644
index 0000000..6d18571
--- /dev/null
+++ b/drivers/power/regulator/tps6287x_regulator.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <dm/device_compat.h>
+#include <power/regulator.h>
+
+#define TPS6287X_REG_VSET 0x0
+#define TPS6287X_REG_CONTROL1 0x1
+#define TPS6287X_REG_CONTROL2 0x2
+#define TPS6287X_REG_CONTROL3 0x3
+#define TPS6287X_REG_STATUS 0x4
+#define TPS6287X_REG_VSET_VSET_MASK 0xff
+#define TPS6287X_REG_CONTROL2_VRANGE_MASK 0xc
+
+struct tps6287x_regulator_config {
+ u32 vmin;
+ u32 vmax;
+};
+
+struct tps6287x_regulator_pdata {
+ u8 vsel_offset;
+ struct udevice *i2c;
+ struct tps6287x_regulator_config *config;
+};
+
+static struct tps6287x_regulator_config tps6287x_data = {
+ .vmin = 400000,
+ .vmax = 3350000,
+};
+
+static int tps6287x_regulator_set_value(struct udevice *dev, int uV)
+{
+ struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev);
+ u8 regval, vset;
+ int ret;
+
+ if (uV < pdata->config->vmin || uV > pdata->config->vmax)
+ return -EINVAL;
+ /*
+ * Based on the value of VRANGE bit field of CONTROL2 reg the range
+ * varies.
+ */
+ ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1);
+ if (ret) {
+ dev_err(dev, "CTRL2 reg read failed: %d\n", ret);
+ return ret;
+ }
+
+ regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK;
+ regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1;
+
+ /*
+ * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV
+ * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV
+ * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV
+ * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV
+ */
+ switch (regval) {
+ case 0:
+ vset = (uV - 400000) / 1250;
+ break;
+ case 1:
+ vset = (uV - 400000) / 2500;
+ break;
+ case 2:
+ vset = (uV - 400000) / 5000;
+ break;
+ case 3:
+ vset = (uV - 800000) / 10000;
+ break;
+ default:
+ pr_err("%s: invalid regval %d\n", dev->name, regval);
+ return -EINVAL;
+ }
+
+ return dm_i2c_write(pdata->i2c, TPS6287X_REG_VSET, &vset, 1);
+}
+
+static int tps6287x_regulator_get_value(struct udevice *dev)
+{
+ u8 regval, vset;
+ int uV;
+ int ret;
+ struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev);
+
+ /*
+ * Based on the value of VRANGE bit field of CONTROL2 reg the range
+ * varies.
+ */
+ ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_CONTROL2, ®val, 1);
+ if (ret) {
+ dev_err(dev, "i2c read failed: %d\n", ret);
+ return ret;
+ }
+
+ regval &= TPS6287X_REG_CONTROL2_VRANGE_MASK;
+ regval >>= ffs(TPS6287X_REG_CONTROL2_VRANGE_MASK) - 1;
+
+ ret = dm_i2c_read(pdata->i2c, TPS6287X_REG_VSET, &vset, 1);
+ if (ret) {
+ dev_err(dev, "i2c VSET read failed: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * VRANGE = 0. Increment step 1250 uV starting with 0 --> 400000 uV
+ * VRANGE = 1. Increment step 2500 uV starting with 0 --> 400000 uV
+ * VRANGE = 2. Increment step 5000 uV starting with 0 --> 400000 uV
+ * VRANGE = 3. Increment step 10000 uV starting with 0 --> 800000 uV
+ */
+ switch (regval) {
+ case 0:
+ uV = 400000 + vset * 1250;
+ break;
+ case 1:
+ uV = 400000 + vset * 2500;
+ break;
+ case 2:
+ uV = 400000 + vset * 5000;
+ break;
+ case 3:
+ uV = 800000 + vset * 10000;
+ break;
+ default:
+ pr_err("%s: invalid regval %d\n", dev->name, regval);
+ return -EINVAL;
+ }
+
+ return uV;
+}
+
+static int tps6287x_regulator_probe(struct udevice *dev)
+{
+ struct tps6287x_regulator_pdata *pdata = dev_get_plat(dev);
+ int ret, slave_id;
+
+ pdata->config = (void *)dev_get_driver_data(dev);
+
+ slave_id = devfdt_get_addr_index(dev, 0);
+
+ ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c);
+ if (ret) {
+ dev_err(dev, "i2c dev get failed.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_regulator_ops tps6287x_regulator_ops = {
+ .get_value = tps6287x_regulator_get_value,
+ .set_value = tps6287x_regulator_set_value,
+};
+
+static const struct udevice_id tps6287x_regulator_ids[] = {
+ { .compatible = "ti,tps62873", .data = (ulong)&tps6287x_data },
+ { },
+};
+
+U_BOOT_DRIVER(tps6287x_regulator) = {
+ .name = "tps6287x_regulator",
+ .id = UCLASS_REGULATOR,
+ .ops = &tps6287x_regulator_ops,
+ .of_match = tps6287x_regulator_ids,
+ .plat_auto = sizeof(struct tps6287x_regulator_pdata),
+ .probe = tps6287x_regulator_probe,
+};
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 320ea7c..bb37b39 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -20,10 +20,11 @@
u32 cr;
writel(0, &pwm->ir);
- cr = PWMCR_PRESCALER(prescale) |
+
+ cr = readl(&pwm->cr) & PWMCR_EN;
+ cr |= PWMCR_PRESCALER(prescale) |
PWMCR_DOZEEN | PWMCR_WAITEN |
PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
-
writel(cr, &pwm->cr);
/* set duty cycles */
writel(duty_cycles, &pwm->sar);
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index c9c46cc..fdb2e78 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -14,7 +14,7 @@
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
-obj-$(CONFIG_ARCH_ASPEED) += aspeed/
+obj-$(CONFIG_ASPEED_RAM) += aspeed/
obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig
index 0deab86..e491846 100644
--- a/drivers/ram/aspeed/Kconfig
+++ b/drivers/ram/aspeed/Kconfig
@@ -1,6 +1,7 @@
menuconfig ASPEED_RAM
bool "ASPEED SDRAM configuration"
- depends on RAM && ARCH_ASPEED
+ depends on RAM
+ depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX
default ARCH_ASPEED
help
Configuration options for DDR SDRAM on ASPEED systems.
@@ -8,8 +9,6 @@
RAM initialisation is always built in for the platform. This menu
allows customisation of the configuration used.
-if ASPEED_RAM
-
config ASPEED_DDR4_DUALX8
bool "Enable Dual X8 DDR4 die"
depends on ASPEED_RAM
@@ -74,4 +73,24 @@
select DDR4 target data rate at 1600M
endchoice
+choice
+ prompt "AST2700 DDR target date rate"
+ default ASPEED_DDR_3200
+ depends on ASPEED_RAM
+ depends on TARGET_ASPEED_AST2700_IBEX
+
+config ASPEED_DDR_1600
+ bool "1600 Mbps"
+ help
+ select DDR target data rate at 1600M
+
+config ASPEED_DDR_2400
+ bool "2400 Mbps"
+ help
+ select DDR target data rate at 2400M
+
-endif # End of ASPEED_RAM
+config ASPEED_DDR_3200
+ bool "3200 Mbps"
+ help
+ select DDR target data rate at 3200M
+endchoice
diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile
index 7ac10af..1f0b22c 100644
--- a/drivers/ram/aspeed/Makefile
+++ b/drivers/ram/aspeed/Makefile
@@ -2,3 +2,4 @@
#
obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o
+obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o
diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c
new file mode 100644
index 0000000..de593c1
--- /dev/null
+++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c
@@ -0,0 +1,2700 @@
+// SPDX-License-Identifier: GPL-2.0+
+// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main()
+// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence()
+// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct()
+// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct()
+// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault()
+// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault()
+
+////##############################################################
+//
+//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any
+//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault()
+//// User should only override values in userInputBasic and userInputAdvanced.
+//// IMPORTANT: in this function, user shall not override any values in the
+//// messageblock directly on the data structue as the might be overwritten by
+//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set
+//// messageblock parameters for override values to remain pervasive if
+//// desired
+//
+////##############################################################
+
+dwc_ddrphy_phyinit_userCustom_overrideUserInput();
+//
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4RxPreambleLength[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D4TxPreambleLength[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Is2Ttiming[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x31f
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x45
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0xa
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x52
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x12
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MsgMisc to 0x7
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].Pstate to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PllBypassEn to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DRAMFreq to 0xc80
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyVref to 0x40
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DramType to 0x2
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DisabledDbyte to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].EnabledDQs to 0x10
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresent to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsPresentD1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AddrMirror to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyCfg to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].SequenceCtrl to 0x31f
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].HdtCtrl to 0xc8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].PhyConfigOverride to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].DFIMRLMargin to 0x2
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR0 to 0x2150
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR1 to 0x101
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR2 to 0x228
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR3 to 0x400
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR4 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR5 to 0x500
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].MR6 to 0x104f
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].X16Present to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].CsSetupGDDec to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl4 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl5 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl6 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].AcsmOdtCtrl7 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR0Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR1Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR2Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].VrefDqR3Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_CAS_L to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ALT_WCAS_L to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].D4Misc to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].ExtTrainOpt to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_1D[0].NVDIMM to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MsgMisc to 0x7
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].Pstate to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PllBypassEn to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DRAMFreq to 0xc80
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyVref to 0x40
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DramType to 0x2
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DisabledDbyte to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].EnabledDQs to 0x10
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresent to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsPresentD1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AddrMirror to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyCfg to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].SequenceCtrl to 0x31f
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].HdtCtrl to 0xc8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].PhyConfigOverride to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].DFIMRLMargin to 0x2
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR0 to 0x2150
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR1 to 0x101
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR2 to 0x228
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR3 to 0x400
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR4 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR5 to 0x500
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].MR6 to 0x104f
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].X16Present to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].CsSetupGDDec to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl4 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl5 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl6 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].AcsmOdtCtrl7 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR0Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR1Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR2Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib0 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib1 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib2 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib3 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib4 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib5 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib6 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib7 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib8 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib9 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib10 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib11 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib12 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib13 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib14 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib15 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib16 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib17 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib18 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].VrefDqR3Nib19 to 0xf
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_CAS_L to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ALT_WCAS_L to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].D4Misc to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].ExtTrainOpt to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR4U_2D[0].NVDIMM to 0x0
+// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput()
+//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb()
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DramType override to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].Pstate override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DRAMFreq override to 0xc80
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PllBypassEn override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].EnabledDQs override to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].PhyCfg override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].DisabledDbyte override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_1D[0].X16Present override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DramType to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].Pstate to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DRAMFreq to 0x856
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].EnabledDQs to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].PhyCfg to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].DisabledDbyte to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[1].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DramType to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].Pstate to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DRAMFreq to 0x74a
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].EnabledDQs to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].PhyCfg to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].DisabledDbyte to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[2].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DramType to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].Pstate to 0x3
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DRAMFreq to 0x640
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].EnabledDQs to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].PhyCfg to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].DisabledDbyte to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR4U_1D[3].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DramType override to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].Pstate override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DRAMFreq override to 0xc80
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PllBypassEn override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].EnabledDQs override to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].PhyCfg override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].DisabledDbyte override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR4U_2D[0].X16Present override to 0x0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1
+////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps
+//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb()
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // Printing values in user input structure
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600
+//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067
+//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933
+//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800
+//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10
+//// [phyinit_print_dat] pUserInputBasic->DramType = 0
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1
+//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0
+//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0
+//// [phyinit_print_dat] pUserInputBasic->Train2D = 0
+//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1
+//// [phyinit_print_dat] pUserInputBasic->DimmType = 4
+//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1
+//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2
+//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 10
+//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0
+//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 11
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 11
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9
+//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 69
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 82
+//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 799
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 3
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 3
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 18
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0
+//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Is2Ttiming[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0
+//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0
+//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1
+//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15
+//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1
+//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247
+//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 0
+//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f
+//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f
+//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR4U_1D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DramType = 0x2
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].EnabledDQs = 0x10
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresent = 0x1
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsPresentD1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AddrMirror = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].SequenceCtrl = 0x31f
+//// [phyinit_print_dat] mb_DDR4U_1D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR4U_1D[0].Rx2D_CmdSpacing = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MREP_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR4U_1D[0].DDR4_RXEN_OFFSET = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR0 = 0x2150
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR1 = 0x101
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR2 = 0x228
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR3 = 0x400
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR5 = 0x500
+//// [phyinit_print_dat] mb_DDR4U_1D[0].MR6 = 0x104f
+//// [phyinit_print_dat] mb_DDR4U_1D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].CsSetupGDDec = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].RTT_NOM_WR_PARK7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].AcsmOdtCtrl7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR0Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR1Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR2Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].VrefDqR3Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_CAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ALT_WCAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].D4Misc = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].ExtTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_1D[0].NVDIMM = 0x0
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // Printing values of 2D message block input/inout fields, PState=0
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f
+//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f
+//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DramType = 0x2
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].EnabledDQs = 0x10
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresent = 0x1
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsPresentD1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AddrMirror = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].SequenceCtrl = 0x31f
+//// [phyinit_print_dat] mb_DDR4U_2D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Share2DVrefResult = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Delay_Weight2D = 0x20
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Voltage_Weight2D = 0x80
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Rx2D_CmdSpacing = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MREP_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VoltageRange2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1_EQU_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_rd2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].advSearch_wr2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].moreDebug2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6_EQU_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].TX2D_DB_DFE_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsWriteNoise = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AdvTrainOpt2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].Misc2D = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR0 = 0x2150
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR1 = 0x101
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR2 = 0x228
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR3 = 0x400
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR5 = 0x500
+//// [phyinit_print_dat] mb_DDR4U_2D[0].MR6 = 0x104f
+//// [phyinit_print_dat] mb_DDR4U_2D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].CsSetupGDDec = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].RTT_NOM_WR_PARK7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl0 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl1 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl2 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl3 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl4 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl5 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl6 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].AcsmOdtCtrl7 = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR0Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR1Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR2Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib0 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib1 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib2 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib3 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib4 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib5 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib6 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib7 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib8 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib9 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib10 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib11 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib12 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib13 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib14 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib15 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib16 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib17 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib18 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].VrefDqR3Nib19 = 0xf
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_CAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ALT_WCAS_L = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].D4Misc = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].ExtTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR4U_2D[0].NVDIMM = 0x0
+
+////##############################################################
+////
+//// Step (A) : Bring up VDD, VDDQ, and VAA
+////
+//// The power supplies can come up and stabilize in any order.
+//// While the power supplies are coming up, all outputs will be unknown and
+//// the values of the inputs are don't cares.
+////
+////##############################################################
+
+dwc_ddrphy_phyinit_userCustom_A_bringupPower();
+
+//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower()
+//
+//
+////##############################################################
+////
+//// 4.3.2(B) Start Clocks and Reset the PHY
+////
+//// Following is one possbile sequence to reset the PHY. Other sequences are also possible.
+//// See section 5.2.2 of the PUB for other possible reset sequences.
+////
+//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X.
+//// 2. Start DfiClk and APBCLK
+//// 3. Drive Reset to 1 and PRESETn_APB to 0.
+//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY.
+//// 4. Wait a minimum of 8 cycles.
+//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted),
+//// DfiClk synchronously switches to any legal input frequency.
+//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY.
+//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset.
+//// 8. Wait a minimum of 1 Cycle.
+//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus.
+////10. The PHY is now in the reset state and is ready to accept APB transactions.
+////
+////##############################################################
+//
+//
+dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc);
+
+//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy()
+//
+
+////##############################################################
+////
+//// Step (C) Initialize PHY Configuration
+////
+//// Load the required PHY configuration registers for the appropriate mode and memory configuration
+////
+////##############################################################
+//
+
+//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig()
+//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1
+dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for MASTER
+dwc_ddrphy_apb_wr(0x20029, 0xc4); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10029, 0xc4); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x11029, 0xc4); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x31 for all ANIBs
+dwc_ddrphy_apb_wr(0x29, 0xc4); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x1029, 0xc4); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x2029, 0xc4); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x3029, 0xc4); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x4029, 0xc4); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x5029, 0xc4); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x6029, 0xc4); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x7029, 0xc4); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x8029, 0xc4); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x9029, 0xc4); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0
+dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0
+dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0
+dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x11e
+dwc_ddrphy_apb_wr(0x55, 0x11e); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x11e
+dwc_ddrphy_apb_wr(0x1055, 0x11e); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x11e
+dwc_ddrphy_apb_wr(0x2055, 0x11e); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x11e
+dwc_ddrphy_apb_wr(0x3055, 0x11e); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x11e
+dwc_ddrphy_apb_wr(0x4055, 0x11e); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x15a
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x15a
+dwc_ddrphy_apb_wr(0x5055, 0x15a); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x11e
+dwc_ddrphy_apb_wr(0x6055, 0x11e); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x11e
+dwc_ddrphy_apb_wr(0x7055, 0x11e); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x11e
+dwc_ddrphy_apb_wr(0x8055, 0x11e); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x11e
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x11e
+dwc_ddrphy_apb_wr(0x9055, 0x11e); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x172
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x372
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+dwc_ddrphy_apb_wr(0x2008c, 0x372); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride
+//// [phyinit_C_initPhyConfig] PUB revision is 0x0350.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200c7, 0x61); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200ca, 0x400f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200cc, 0xd2); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings
+
+//
+////##############################################################
+////
+//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs
+//// The values programmed here assume ideal properties of DfiClk
+//// and Pclk including:
+//// - DfiClk skew
+//// - DfiClk jitter
+//// - DfiClk PVT variations
+//// - Pclk skew
+//// - Pclk jitter
+////
+//// PLL Bypassed mode:
+//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5
+//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5
+////
+//// PLL Enabled mode:
+//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5
+//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5
+////
+////##############################################################
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1
+dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0
+dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x8
+dwc_ddrphy_apb_wr(0x20024, 0x8); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2
+dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0
+dwc_ddrphy_apb_wr(0x1004d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0
+dwc_ddrphy_apb_wr(0x1014d, 0x4); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0
+dwc_ddrphy_apb_wr(0x1104d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0
+dwc_ddrphy_apb_wr(0x1114d, 0x4); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1
+dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0
+dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0
+dwc_ddrphy_apb_wr(0x10049, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0
+dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0
+dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0
+dwc_ddrphy_apb_wr(0x10149, 0xfff); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0
+dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0
+dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0
+dwc_ddrphy_apb_wr(0x11049, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0
+dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0
+dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0
+dwc_ddrphy_apb_wr(0x11149, 0xfff); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0
+dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0
+//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1
+dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode
+//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x2
+dwc_ddrphy_apb_wr(0x20075, 0x2); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode
+//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2
+//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2
+dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320
+dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0
+//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9
+//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0
+dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8
+dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2500
+dwc_ddrphy_apb_wr(0x10043, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2500
+dwc_ddrphy_apb_wr(0x10143, 0x2500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2500
+dwc_ddrphy_apb_wr(0x11043, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2500
+dwc_ddrphy_apb_wr(0x11143, 0x2500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c
+dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0
+dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0
+//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0
+dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren
+//// [phyinit_C_initPhyConfig] Programming ATxOdtDrvStren of ANIB_0 to 0x0
+dwc_ddrphy_apb_wr(0x42, 0x0); // DWC_DDRPHYA_ANIB0_base0_ATxOdtDrvStren
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0
+dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0
+//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat*
+dwc_ddrphy_apb_wr(0x200f0, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0
+dwc_ddrphy_apb_wr(0x200f1, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1
+dwc_ddrphy_apb_wr(0x200f2, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2
+dwc_ddrphy_apb_wr(0x200f3, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3
+dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4
+dwc_ddrphy_apb_wr(0x200f5, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5
+dwc_ddrphy_apb_wr(0x200f6, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6
+dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64
+dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8
+dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc
+dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c
+dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0
+//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power.
+dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1
+//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power.
+dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1
+//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0
+dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0
+dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DMIPinPresent::RdDbiEnabled to 0x0
+dwc_ddrphy_apb_wr(0x2002d, 0x0); // DWC_DDRPHYA_MASTER0_base0_DMIPinPresent_p0
+// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x0
+dwc_ddrphy_apb_wr(0x20040, 0x0); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080
+dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0
+// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1
+dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER
+dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs
+dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs
+dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes
+dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0
+dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0
+dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0
+dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0
+dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0
+dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1
+dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1
+dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1
+dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0
+dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2
+dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2
+dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2
+dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0
+dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3
+dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3
+dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3
+dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0
+dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4
+dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4
+dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4
+dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0
+dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5
+dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5
+dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5
+dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0
+dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6
+dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6
+dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6
+dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0
+dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7
+dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7
+dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7
+dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0
+dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8
+dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8
+dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8
+dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0
+dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0
+dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0
+dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0
+dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0
+dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1
+dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1
+dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1
+dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0
+dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2
+dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2
+dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2
+dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0
+dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3
+dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3
+dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3
+dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0
+dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4
+dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4
+dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4
+dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0
+dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5
+dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5
+dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5
+dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0
+dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6
+dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6
+dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6
+dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0
+dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7
+dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7
+dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7
+dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0
+dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8
+dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8
+dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1
+dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0
+//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0
+dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc
+dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont
+//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig()
+//
+//
+////##############################################################
+////
+//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any
+//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to
+//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig().
+//// This function is executed before training and thus any override here might affect
+//// training result.
+////
+//// IMPORTANT: in this function, user shall not override any values in userInputBasic and
+//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput()
+//// to modify values in those data structures.
+////
+////##############################################################
+//
+//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain()
+//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain()
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0)
+//
+//
+////##############################################################
+////
+//// (D) Load the 1D IMEM image
+////
+//// This function loads the training firmware IMEM image into the SRAM.
+//// See PhyInit App Note for detailed description and function usage
+////
+////##############################################################
+//
+//
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2
+dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_imem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000
+//#ifdef TRAIN_LOADBIN
+dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0);
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM()
+//
+//
+////##############################################################
+////
+//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0
+////
+//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step,
+//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>.
+////
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc);
+
+//
+//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk()
+//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0)
+//
+//
+////##############################################################
+////
+//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//
+//// 1. Load the firmware DMEM segment to initialize the data structures.
+//
+//// 2. Write the Firmware Message Block with the required contents detailing the training parameters.
+//
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4/ddr4_pmu_train_dmem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000
+//#ifdef TRAIN_LOADBIN
+dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0);
+
+dwc_ddrphy_apb_wr_32b(0x58000, 0x100);
+dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000);
+dwc_ddrphy_apb_wr_32b(0x58004, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240);
+dwc_ddrphy_apb_wr_32b(0x58008, 0x1);
+dwc_ddrphy_apb_wr_32b(0x5800a, 0x31f0000);
+dwc_ddrphy_apb_wr_32b(0x5800c, 0xc8);
+dwc_ddrphy_apb_wr_32b(0x5800e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58010, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58012, 0x2);
+dwc_ddrphy_apb_wr_32b(0x58014, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58016, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58018, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58020, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58022, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58024, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58026, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58028, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000);
+dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101);
+dwc_ddrphy_apb_wr_32b(0x58032, 0x400);
+dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500);
+dwc_ddrphy_apb_wr_32b(0x58036, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58038, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58040, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000);
+dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f);
+dwc_ddrphy_apb_wr_32b(0x5806c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5806e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58070, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58072, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58074, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58076, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58078, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58080, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58082, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58084, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58086, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58088, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58090, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58092, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58094, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58096, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58098, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fe, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58100, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58102, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58104, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58106, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58108, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58110, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58112, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58114, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58116, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58118, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58120, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58122, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58124, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58126, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58128, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58130, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58132, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58134, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58136, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58138, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58140, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58142, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58144, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58146, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58148, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58150, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58152, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58154, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58156, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58158, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58160, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58162, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58164, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58166, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58168, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58170, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58172, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58174, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58176, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58178, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58180, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58182, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58184, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58186, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58188, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58190, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58192, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58194, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58196, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58198, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fe, 0x0);
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM()
+//
+//
+////##############################################################
+////
+//// 4.3.7(G) Execute the Training Firmware
+////
+//// The training firmware is executed with the following procedure:
+////
+////##############################################################
+//
+//
+//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and
+//// ResetToMicro fields to 1 (all other fields should be zero).
+//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero).
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000.
+dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging"
+//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message.
+dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc);
+
+//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone()
+//// 4. Halt the microcontroller."
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap
+//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW()
+//
+//
+////##############################################################
+////
+//// 4.3.8(H) Read the Message Block results
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//
+//2. Read the Firmware Message Block to obtain the results from the training.
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+//Example:
+//if (Train2D)
+//{
+// _read_2d_message_block_outputs_
+//}
+//else
+//{
+// _read_1d_message_block_outputs_
+//}
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0);
+
+//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock()
+//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// 4. If training is required at another frequency, repeat the operations starting at step (E).
+//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock()
+//
+//
+////##############################################################
+////
+//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0
+////
+//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step,
+//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>.
+////
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc);
+
+//
+//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk()
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=1)
+//
+//
+////##############################################################
+////
+//// (D) Load the 2D IMEM image
+////
+//// This function loads the training firmware IMEM image into the SRAM.
+//// See PhyInit App Note for detailed description and function usage
+////
+////##############################################################
+//
+//
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_imem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000
+dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 1);
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 2D] End of dwc_ddrphy_phyinit_D_loadIMEM()
+//// [phyinit_F_loadDMEM, 2D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=1)
+//
+//
+////##############################################################
+////
+//// 4.3.5(F) Load the 2D DMEM image and write the 2D Message Block parameters for the training firmware
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//
+//// 1. Load the firmware DMEM segment to initialize the data structures.
+//
+//// 2. Write the Firmware Message Block with the required contents detailing the training parameters.
+//
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-16-52-55/firmware/Latest/training/ddr4_2d/ddr4_2d_pmu_train_dmem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000
+dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 1);
+dwc_ddrphy_apb_wr_32b(0x58000, 0x100);
+dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000);
+dwc_ddrphy_apb_wr_32b(0x58004, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58006, 0x10000240);
+dwc_ddrphy_apb_wr_32b(0x58008, 0x1);
+//printf("- <DWC_DDRPHY/TRAIN>: Override 2D DMEM image for SequenceCtrl, RX2D_TrainOpt, TX2D_TrainOpt, Delay_Weight2D, and Voltage_Weight2D\n");
+// uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5800b, Direction=In
+ // SequenceCtrl[0] = Run DevInit - Device/PHY initialization. Should always be set
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+dwc_ddrphy_apb_wr_32b(0x5800a, 0x0610000);
+
+// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value.
+// uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5800c, Direction=In
+ // 0x04 = Maximal debug messages (e.g., Eye contours)
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+// uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5800c, Direction=In
+// uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5800d, Direction=In
+ #ifdef DWC_DEBUG
+//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1e0a);
+ #else
+//dwc_ddrphy_apb_wr_32b(0x5800c, 0x001e1ec8);
+dwc_ddrphy_apb_wr_32b(0x5800c, 0x000000c8);
+ #endif
+// uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5800e, Direction=In
+// uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In
+dwc_ddrphy_apb_wr_32b(0x5800e, 0x8020);
+
+dwc_ddrphy_apb_wr_32b(0x58010, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58012, 0x2);
+dwc_ddrphy_apb_wr_32b(0x58014, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58016, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58018, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58020, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58022, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58024, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58026, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58028, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802e, 0x21500000);
+dwc_ddrphy_apb_wr_32b(0x58030, 0x2280101);
+dwc_ddrphy_apb_wr_32b(0x58032, 0x400);
+dwc_ddrphy_apb_wr_32b(0x58034, 0x104f0500);
+dwc_ddrphy_apb_wr_32b(0x58036, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58038, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58040, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58042, 0xf0f0000);
+dwc_ddrphy_apb_wr_32b(0x58044, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58046, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58048, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804a, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804c, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5804e, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58050, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58052, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58054, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58056, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58058, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805a, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805c, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5805e, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58060, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58062, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58064, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58066, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x58068, 0xf0f0f0f);
+dwc_ddrphy_apb_wr_32b(0x5806a, 0xf0f);
+dwc_ddrphy_apb_wr_32b(0x5806c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5806e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58070, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58072, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58074, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58076, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58078, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58080, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58082, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58084, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58086, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58088, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58090, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58092, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58094, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58096, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58098, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fe, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58100, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58102, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58104, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58106, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58108, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58110, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58112, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58114, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58116, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58118, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58120, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58122, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58124, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58126, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58128, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58130, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58132, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58134, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58136, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58138, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58140, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58142, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58144, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58146, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58148, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58150, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58152, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58154, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58156, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58158, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58160, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58162, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58164, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58166, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58168, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58170, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58172, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58174, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58176, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58178, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58180, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58182, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58184, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58186, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58188, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58190, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58192, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58194, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58196, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58198, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fe, 0x0);
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_F_loadDMEM, 2D] End of dwc_ddrphy_phyinit_F_loadDMEM()
+//
+//
+////##############################################################
+////
+//// 4.3.7(G) Execute the Training Firmware
+////
+//// The training firmware is executed with the following procedure:
+////
+////##############################################################
+//
+//
+//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and
+//// ResetToMicro fields to 1 (all other fields should be zero).
+//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero).
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000.
+dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging"
+//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message.
+dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc);
+
+//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone()
+//// 4. Halt the microcontroller."
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap
+//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW()
+//
+//
+////##############################################################
+////
+//// 4.3.8(H) Read the Message Block results
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//
+//2. Read the Firmware Message Block to obtain the results from the training.
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+//Example:
+//if (Train2D)
+//{
+// _read_2d_message_block_outputs_
+//}
+//else
+//{
+// _read_1d_message_block_outputs_
+//}
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 1);
+
+//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock()
+//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// 4. If training is required at another frequency, repeat the operations starting at step (E).
+//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock()
+//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits()
+//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x000000ff, rtt_required = 0x0000000f
+//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000
+//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits()
+//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage()
+//
+//
+////##############################################################
+////
+//// 4.3.9(I) Load PHY Init Engine Image
+////
+//// Load the PHY Initialization Engine memory with the provided initialization sequence.
+////
+////##############################################################
+//
+//
+//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1
+dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// [phyinit_I_loadPIEImage] Programming PIE Production Code
+//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections()
+//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000
+dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 90029
+dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2
+dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0
+dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1
+dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2
+dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0
+dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1
+dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2
+dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0
+dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1
+dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2
+dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0
+dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1
+dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2
+dwc_ddrphy_apb_wr(0x9003b, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0
+dwc_ddrphy_apb_wr(0x9003c, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1
+dwc_ddrphy_apb_wr(0x9003d, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2
+dwc_ddrphy_apb_wr(0x9003e, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0
+dwc_ddrphy_apb_wr(0x9003f, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1
+dwc_ddrphy_apb_wr(0x90040, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2
+dwc_ddrphy_apb_wr(0x90041, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0
+dwc_ddrphy_apb_wr(0x90042, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1
+dwc_ddrphy_apb_wr(0x90043, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2
+dwc_ddrphy_apb_wr(0x90044, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0
+dwc_ddrphy_apb_wr(0x90045, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1
+dwc_ddrphy_apb_wr(0x90046, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2
+dwc_ddrphy_apb_wr(0x90047, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0
+dwc_ddrphy_apb_wr(0x90048, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1
+dwc_ddrphy_apb_wr(0x90049, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2
+dwc_ddrphy_apb_wr(0x9004a, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0
+dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1
+dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2
+dwc_ddrphy_apb_wr(0x9004d, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0
+dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1
+dwc_ddrphy_apb_wr(0x9004f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2
+dwc_ddrphy_apb_wr(0x90050, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0
+dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1
+dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2
+dwc_ddrphy_apb_wr(0x90053, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0
+dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1
+dwc_ddrphy_apb_wr(0x90055, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2
+dwc_ddrphy_apb_wr(0x90056, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0
+dwc_ddrphy_apb_wr(0x90057, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1
+dwc_ddrphy_apb_wr(0x90058, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2
+dwc_ddrphy_apb_wr(0x90059, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0
+dwc_ddrphy_apb_wr(0x9005a, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1
+dwc_ddrphy_apb_wr(0x9005b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2
+dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0
+dwc_ddrphy_apb_wr(0x9005d, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1
+dwc_ddrphy_apb_wr(0x9005e, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2
+dwc_ddrphy_apb_wr(0x9005f, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0
+dwc_ddrphy_apb_wr(0x90060, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1
+dwc_ddrphy_apb_wr(0x90061, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2
+dwc_ddrphy_apb_wr(0x90062, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0
+dwc_ddrphy_apb_wr(0x90063, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1
+dwc_ddrphy_apb_wr(0x90064, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2
+dwc_ddrphy_apb_wr(0x90065, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0
+dwc_ddrphy_apb_wr(0x90066, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1
+dwc_ddrphy_apb_wr(0x90067, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2
+dwc_ddrphy_apb_wr(0x90068, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0
+dwc_ddrphy_apb_wr(0x90069, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1
+dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2
+dwc_ddrphy_apb_wr(0x9006b, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0
+dwc_ddrphy_apb_wr(0x9006c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1
+dwc_ddrphy_apb_wr(0x9006d, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2
+dwc_ddrphy_apb_wr(0x9006e, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0
+dwc_ddrphy_apb_wr(0x9006f, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1
+dwc_ddrphy_apb_wr(0x90070, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2
+dwc_ddrphy_apb_wr(0x90071, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0
+dwc_ddrphy_apb_wr(0x90072, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1
+dwc_ddrphy_apb_wr(0x90073, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2
+dwc_ddrphy_apb_wr(0x90074, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0
+dwc_ddrphy_apb_wr(0x90075, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1
+dwc_ddrphy_apb_wr(0x90076, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2
+dwc_ddrphy_apb_wr(0x90077, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0
+dwc_ddrphy_apb_wr(0x90078, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1
+dwc_ddrphy_apb_wr(0x90079, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2
+dwc_ddrphy_apb_wr(0x9007a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0
+dwc_ddrphy_apb_wr(0x9007b, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1
+dwc_ddrphy_apb_wr(0x9007c, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2
+dwc_ddrphy_apb_wr(0x9007d, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0
+dwc_ddrphy_apb_wr(0x9007e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1
+dwc_ddrphy_apb_wr(0x9007f, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2
+dwc_ddrphy_apb_wr(0x90080, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0
+dwc_ddrphy_apb_wr(0x90081, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1
+dwc_ddrphy_apb_wr(0x90082, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2
+dwc_ddrphy_apb_wr(0x90083, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0
+dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1
+dwc_ddrphy_apb_wr(0x90085, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2
+dwc_ddrphy_apb_wr(0x90086, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0
+dwc_ddrphy_apb_wr(0x90087, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1
+dwc_ddrphy_apb_wr(0x90088, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2
+dwc_ddrphy_apb_wr(0x90089, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0
+dwc_ddrphy_apb_wr(0x9008a, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1
+dwc_ddrphy_apb_wr(0x9008b, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2
+dwc_ddrphy_apb_wr(0x9008c, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0
+dwc_ddrphy_apb_wr(0x9008d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1
+dwc_ddrphy_apb_wr(0x9008e, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2
+dwc_ddrphy_apb_wr(0x9008f, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0
+dwc_ddrphy_apb_wr(0x90090, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1
+dwc_ddrphy_apb_wr(0x90091, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2
+dwc_ddrphy_apb_wr(0x90092, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0
+dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1
+dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2
+dwc_ddrphy_apb_wr(0x90095, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0
+dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1
+dwc_ddrphy_apb_wr(0x90097, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2
+dwc_ddrphy_apb_wr(0x90098, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0
+dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1
+dwc_ddrphy_apb_wr(0x9009a, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2
+dwc_ddrphy_apb_wr(0x9009b, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0
+dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1
+dwc_ddrphy_apb_wr(0x9009d, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2
+dwc_ddrphy_apb_wr(0x9009e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0
+dwc_ddrphy_apb_wr(0x9009f, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1
+dwc_ddrphy_apb_wr(0x900a0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2
+dwc_ddrphy_apb_wr(0x900a1, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0
+dwc_ddrphy_apb_wr(0x900a2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1
+dwc_ddrphy_apb_wr(0x900a3, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2
+dwc_ddrphy_apb_wr(0x900a4, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0
+dwc_ddrphy_apb_wr(0x900a5, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1
+dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2
+dwc_ddrphy_apb_wr(0x900a7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0
+dwc_ddrphy_apb_wr(0x900a8, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1
+dwc_ddrphy_apb_wr(0x900a9, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2
+dwc_ddrphy_apb_wr(0x900aa, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0
+dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1
+dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2
+dwc_ddrphy_apb_wr(0x900ad, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0
+dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1
+dwc_ddrphy_apb_wr(0x900af, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2
+dwc_ddrphy_apb_wr(0x900b0, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0
+dwc_ddrphy_apb_wr(0x900b1, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1
+dwc_ddrphy_apb_wr(0x900b2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2
+dwc_ddrphy_apb_wr(0x900b3, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0
+dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1
+dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2
+dwc_ddrphy_apb_wr(0x900b6, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0
+dwc_ddrphy_apb_wr(0x900b7, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1
+dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2
+dwc_ddrphy_apb_wr(0x900b9, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0
+dwc_ddrphy_apb_wr(0x900ba, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1
+dwc_ddrphy_apb_wr(0x900bb, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2
+//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0
+dwc_ddrphy_apb_wr(0x900bc, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0
+dwc_ddrphy_apb_wr(0x900bd, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1
+dwc_ddrphy_apb_wr(0x900be, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2
+dwc_ddrphy_apb_wr(0x900bf, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0
+dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1
+dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2
+dwc_ddrphy_apb_wr(0x900c2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0
+dwc_ddrphy_apb_wr(0x900c3, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1
+dwc_ddrphy_apb_wr(0x900c4, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2
+dwc_ddrphy_apb_wr(0x900c5, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0
+dwc_ddrphy_apb_wr(0x900c6, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1
+dwc_ddrphy_apb_wr(0x900c7, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2
+//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0
+dwc_ddrphy_apb_wr(0x900c8, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0
+dwc_ddrphy_apb_wr(0x900c9, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1
+dwc_ddrphy_apb_wr(0x900ca, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2
+dwc_ddrphy_apb_wr(0x900cb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0
+dwc_ddrphy_apb_wr(0x900cc, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1
+dwc_ddrphy_apb_wr(0x900cd, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2
+dwc_ddrphy_apb_wr(0x900ce, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0
+dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1
+dwc_ddrphy_apb_wr(0x900d0, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2
+dwc_ddrphy_apb_wr(0x900d1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0
+dwc_ddrphy_apb_wr(0x900d2, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1
+dwc_ddrphy_apb_wr(0x900d3, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2
+dwc_ddrphy_apb_wr(0x900d4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0
+dwc_ddrphy_apb_wr(0x900d5, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1
+dwc_ddrphy_apb_wr(0x900d6, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2
+dwc_ddrphy_apb_wr(0x900d7, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0
+dwc_ddrphy_apb_wr(0x900d8, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1
+dwc_ddrphy_apb_wr(0x900d9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2
+dwc_ddrphy_apb_wr(0x900da, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0
+dwc_ddrphy_apb_wr(0x900db, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1
+dwc_ddrphy_apb_wr(0x900dc, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2
+dwc_ddrphy_apb_wr(0x900dd, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0
+dwc_ddrphy_apb_wr(0x900de, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1
+dwc_ddrphy_apb_wr(0x900df, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2
+dwc_ddrphy_apb_wr(0x900e0, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0
+dwc_ddrphy_apb_wr(0x900e1, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1
+dwc_ddrphy_apb_wr(0x900e2, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2
+dwc_ddrphy_apb_wr(0x900e3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0
+dwc_ddrphy_apb_wr(0x900e4, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1
+dwc_ddrphy_apb_wr(0x900e5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2
+dwc_ddrphy_apb_wr(0x900e6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0
+dwc_ddrphy_apb_wr(0x900e7, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1
+dwc_ddrphy_apb_wr(0x900e8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2
+dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0
+dwc_ddrphy_apb_wr(0x900ea, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1
+dwc_ddrphy_apb_wr(0x900eb, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2
+dwc_ddrphy_apb_wr(0x900ec, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0
+dwc_ddrphy_apb_wr(0x900ed, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1
+dwc_ddrphy_apb_wr(0x900ee, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2
+dwc_ddrphy_apb_wr(0x900ef, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0
+dwc_ddrphy_apb_wr(0x900f0, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1
+dwc_ddrphy_apb_wr(0x900f1, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2
+dwc_ddrphy_apb_wr(0x900f2, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0
+dwc_ddrphy_apb_wr(0x900f3, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1
+dwc_ddrphy_apb_wr(0x900f4, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2
+dwc_ddrphy_apb_wr(0x900f5, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0
+dwc_ddrphy_apb_wr(0x900f6, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1
+dwc_ddrphy_apb_wr(0x900f7, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 900f8 to 90006
+dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7
+dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride
+//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections()
+//seq0b_LoadPstateSeqProductionCode(): ---------------------------------------------------------------------------------------------------
+//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0.
+//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 56.
+//seq0b_LoadPstateSeqProductionCode(): ---------------------------------------------------------------------------------------------------
+dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0
+dwc_ddrphy_apb_wr(0x90026, 0x38); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15
+dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0
+dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1
+dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2
+dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3
+dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4
+dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5
+dwc_ddrphy_apb_wr(0x90012, 0xffff); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6
+dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7
+//// [phyinit_I_loadPIEImage] Programming D4PowerControl::D4CATxDllLP to 0x1
+//// [phyinit_I_loadPIEImage] Programming AcLcdlMasDis to 0xfff
+dwc_ddrphy_apb_wr(0x2006d, 0x1); // DWC_DDRPHYA_MASTER0_base0_D4PowerControl
+dwc_ddrphy_apb_wr(0x200e8, 0xfff); // DWC_DDRPHYA_MASTER0_base0_AcLcdlMasDis
+//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered.
+//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1
+//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1
+//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19
+dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap
+dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate
+//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0
+dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// Disabling Ucclk (PMU) and Hclk (training hardware)
+dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables
+//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage()
+//
+//
+////##############################################################
+////
+//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any
+//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain()
+//// This function is executed after training
+////
+//// IMPORTANT: in this function, user shall not override any values in userInputBasic and
+//// userInputAdvanced data structures. Only CSR programming should be done in this function.
+////
+//// Sequence of Events in this function are:
+//// 1. Enable APB access.
+//// 2. Issue register writes
+//// 3. Isolate APB access.
+//
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_customPostTrain();
+
+//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain()
+//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode()
+//
+//
+////##############################################################
+////
+//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization
+////
+//// Initialize the PHY to mission mode as follows:
+////
+//// 1. Set the PHY input clocks to the desired frequency.
+//// 2. Initialize the PHY to mission mode by performing DFI Initialization.
+//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>.
+//// Note: The PHY training firmware initializes the DRAM state. if skip
+//// training is used, the DRAM state is not initialized.
+////
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc);
+
+//
+//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode()
+// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence()
+// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main()
diff --git a/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c
new file mode 100644
index 0000000..d21bcda
--- /dev/null
+++ b/drivers/ram/aspeed/dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c
@@ -0,0 +1,6930 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+// [dwc_ddrphy_phyinit_main] Start of dwc_ddrphy_phyinit_main()
+// [dwc_ddrphy_phyinit_sequence] Start of dwc_ddrphy_phyinit_sequence()
+// [dwc_ddrphy_phyinit_initStruct] Start of dwc_ddrphy_phyinit_initStruct()
+// [dwc_ddrphy_phyinit_initStruct] End of dwc_ddrphy_phyinit_initStruct()
+// [dwc_ddrphy_phyinit_setDefault] Start of dwc_ddrphy_phyinit_setDefault()
+// [dwc_ddrphy_phyinit_setDefault] End of dwc_ddrphy_phyinit_setDefault()
+
+////##############################################################
+//
+//// dwc_ddrphy_phyinit_userCustom_overrideUserInput is a user-editable function. User can edit this function according to their needs.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_overrideUserInput() is to override any
+//// any field in Phyinit data structure set by dwc_ddrphy_phyinit_setDefault()
+//// User should only override values in userInputBasic and userInputAdvanced.
+//// IMPORTANT: in this function, user shall not override any values in the
+//// messageblock directly on the data structue as the might be overwritten by
+//// dwc_ddrphy_phyinit_calcMb(). Use dwc_ddrphy_phyinit_setMb() to set
+//// messageblock parameters for override values to remain pervasive if
+//// desired
+//
+////##############################################################
+
+dwc_ddrphy_phyinit_userCustom_overrideUserInput();
+//
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramType' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DimmType' to 0x4
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumDbyte' to 0x2
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi0' to 0x2
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumActiveDbyteDfi1' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumAnib' to 0xa
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi0' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumRank_dfi1' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[0]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[1]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[2]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DramDataWidth[3]' to 0x10
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'NumPStates' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Frequency[0]' to 0x640
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PllBypass[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DfiFreqRatio[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Dfi1Exists' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ExtCalResVal' to 0xf0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'ODTImpedance[0]' to 0x78
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxImpedance[0]' to 0x3c
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MemAlertEn' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'MtestPUImp' to 0xf0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisDynAdrTri[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrTrainInterval[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrMaxReqToAck[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'PhyMstrCtrlMode[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'WDQSExt' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalInterval' to 0x9
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'CalOnce' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'RxEnBackOff' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TrainSequenceCtrl' to 0x837f
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlOpt' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'SnpsUmctlF0RC5x[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseDQ[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallDQ[0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseAC' to 0x66
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallAC' to 0x26
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'IsHighVDD' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewRiseCK' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'TxSlewFallCK' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg0[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg1[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg2[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnTdqs2dqTrackingTg3[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DqsOscRunTimeSel[0]' to 0x100
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnRxDqsTracking[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5TxDqPreambleCtrl[0]' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'D5DisableRetraining' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'DisablePmuEcc' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'EnableMAlertAsync' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'Apb32BitMode' to 0x1
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQS2DQ' to 0x2ee
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tDQSCK' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_override' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][0]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][1]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][2]' to 0x0
+//// [dwc_ddrphy_phyinit_setUserInput] Setting PHYINIT field 'tCASL_add[0][3]' to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MsgMisc to 0x7
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].Pstate to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PllBypassEn to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DRAMFreq to 0xc80
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyVref to 0x40
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].D5Misc to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].SequenceCtrl to 0x837f
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].HdtCtrl to 0xc8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyCfg to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DFIMRLMargin to 0x2
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].X16Present to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].UseBroadcastMR to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].DisabledDbyte to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CATrainOpt to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].PhyConfigOverride to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChA to 0x10
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChA to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A0 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A0 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A0 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A0 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A0 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A0 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A0 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A0 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A0 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A0 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A1 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A1 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A1 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A1 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A1 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A1 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A1 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A1 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A1 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A1 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A2 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A2 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A2 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A2 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A2 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A2 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A2 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A2 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A2 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A2 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_A3 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_A3 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_A3 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_A3 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_A3 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_A3 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_A3 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_A3 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_A3 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_A3 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_A3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_A3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_A3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_A3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].EnabledDQsChB to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].CsPresentChB to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B0 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B0 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B0 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B0 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B0 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B0 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B0 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B0 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B0 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B0 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B0 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B0 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B1 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B1 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B1 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B1 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B1 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B1 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B1 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B1 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B1 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B1 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B1 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B1 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B2 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B2 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B2 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B2 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B2 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B2 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B2 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B2 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B2 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B2 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B2 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B2 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR0_B3 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR2_B3 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR3_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR4_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR5_B3 to 0x20
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR6_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR8_B3 to 0x8
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR10_B3 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR11_B3 to 0x2d
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR12_B3 to 0xd6
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR13_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR14_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR15_B3 to 0x3
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR111_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR32_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR33_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR34_B3 to 0x11
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR35_B3 to 0x4
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR37_B3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR38_B3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR39_B3 to 0x2c
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR50_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR51_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].MR52_B3 to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_START to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].WL_ADJ_END to 0x0
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D0 to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChA_D1 to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D0 to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].RCW00_ChB_D1 to 0x1
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib0 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib1 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib2 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib3 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib4 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib5 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib6 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib7 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib8 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib9 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib10 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib11 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib12 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib13 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib14 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib15 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib16 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib17 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib18 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR0Nib19 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib0 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib1 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib2 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib3 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib4 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib5 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib6 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib7 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib8 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib9 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib10 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib11 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib12 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib13 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib14 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib15 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib16 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib17 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib18 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR1Nib19 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib0 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib1 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib2 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib3 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib4 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib5 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib6 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib7 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib8 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib9 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib10 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib11 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib12 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib13 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib14 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib15 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib16 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib17 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib18 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR2Nib19 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib0 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib1 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib2 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib3 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib4 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib5 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib6 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib7 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib8 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib9 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib10 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib11 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib12 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib13 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib14 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib15 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib16 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib17 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib18 to 0x17
+// [dwc_ddrphy_phyinit_setMb] Setting mb_DDR5U_1D[0].VrefDqR3Nib19 to 0x17
+// [dwc_ddrphy_phyinit_userCustom_overrideUserInput] End of dwc_ddrphy_phyinit_userCustom_overrideUserInput()
+//[dwc_ddrphy_phyinit_calcMb] Start of dwc_ddrphy_phyinit_calcMb()
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].Pstate override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].DRAMFreq override to 0xc80
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].PllBypassEn override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].X16Present override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChA override to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] mb_DDR5U_1D[0].EnabledDQsChB override to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].Pstate to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].DRAMFreq to 0x856
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChA to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[1].EnabledDQsChB to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].Pstate to 0x2
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].DRAMFreq to 0x74a
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChA to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[2].EnabledDQsChB to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].Pstate to 0x3
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].DRAMFreq to 0x640
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].PllBypassEn to 0x0
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].X16Present to 0x1
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChA to 0x10
+//// [dwc_ddrphy_phyinit_softSetMb] Setting mb_DDR5U_1D[3].EnabledDQsChB to 0x0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[0] = 1
+////[dwc_ddrphy_phyinit_calcMb] TG_active[1] = 0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[2] = 0
+////[dwc_ddrphy_phyinit_calcMb] TG_active[3] = 0
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=0] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=1] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=2] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_CK [pstate=0][tg=3] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] tDIMM_DQ [pstate=0][tg=3] = 0 ps
+////[dwc_ddrphy_phyinit_calcMb] userInputSim.tCASL_add[pstate=0][tg=3] = 0 ps
+//[dwc_ddrphy_phyinit_calcMb] End of dwc_ddrphy_phyinit_calcMb()
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // Printing values in user input structure
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[0] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[1] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[2] = 16
+//// [phyinit_print_dat] pUserInputBasic->DramDataWidth[3] = 16
+//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi1 = 0
+//// [phyinit_print_dat] pUserInputBasic->DramType = 1
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitValOvr = 0
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[0] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[1] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[2] = 3
+//// [phyinit_print_dat] pUserInputBasic->ARdPtrInitVal[3] = 3
+//// [phyinit_print_dat] pUserInputBasic->Dfi1Exists = 0
+//// [phyinit_print_dat] pUserInputBasic->Frequency[0] = 1600
+//// [phyinit_print_dat] pUserInputBasic->Frequency[1] = 1067
+//// [phyinit_print_dat] pUserInputBasic->Frequency[2] = 933
+//// [phyinit_print_dat] pUserInputBasic->Frequency[3] = 800
+//// [phyinit_print_dat] pUserInputBasic->NumActiveDbyteDfi0 = 2
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[0] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[1] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[2] = 0
+//// [phyinit_print_dat] pUserInputBasic->DisPtrInitClrTxTracking[3] = 0
+//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi0 = 1
+//// [phyinit_print_dat] pUserInputBasic->NumPStates = 1
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[0] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[1] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[2] = 0
+//// [phyinit_print_dat] pUserInputBasic->PllBypass[3] = 0
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[0] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[1] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[2] = 1
+//// [phyinit_print_dat] pUserInputBasic->DfiFreqRatio[3] = 1
+//// [phyinit_print_dat] pUserInputBasic->NumAnib = 10
+//// [phyinit_print_dat] pUserInputBasic->DimmType = 4
+//// [phyinit_print_dat] pUserInputBasic->NumRank_dfi1 = 0
+//// [phyinit_print_dat] pUserInputBasic->NumDbyte = 2
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg1[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg0[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlF0RC5x[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl2[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->IsHighVDD = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DramByteSwap[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->ExtCalResVal = 240
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4TxPreambleLength[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->RxEnBackOff = 1
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvLaneSel[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->CalOnce = 0
+//// [phyinit_print_dat] pUserInputAdvanced->Apb32BitMode = 1
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseCK = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallAC = 38
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallCK = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisablePmuEcc = 1
+//// [phyinit_print_dat] pUserInputAdvanced->SnpsUmctlOpt = 0
+//// [phyinit_print_dat] pUserInputAdvanced->WDQSExt = 0
+//// [phyinit_print_dat] pUserInputAdvanced->VREGCtrl_LP2_PwrSavings_En = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseAC = 102
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DisDynAdrTri[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AnibRcvEn[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg3[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrTrainInterval[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->rtt_term_en = 0
+//// [phyinit_print_dat] pUserInputAdvanced->AlertRecoveryEnable = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewRiseDQ[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->en_16LogicalRanks_3DS = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[1] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[2] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D4RxPreambleLength[3] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrCtrlMode[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxSlewFallDQ[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[4] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[5] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[6] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->NvAnibRcvSel[7] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[0] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[1] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[2] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedanceCtrl1[3] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->Nibble_ECC = 15
+//// [phyinit_print_dat] pUserInputAdvanced->D5DisableRetraining = 0
+//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[0] = 256
+//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[1] = 256
+//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[2] = 256
+//// [phyinit_print_dat] pUserInputAdvanced->DqsOscRunTimeSel[3] = 256
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[0] = 120
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[1] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[2] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->ODTImpedance[3] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->MtestPUImp = 240
+//// [phyinit_print_dat] pUserInputAdvanced->EnableMAlertAsync = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[0] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->PhyMstrMaxReqToAck[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->RedundantCs_en = 0
+//// [phyinit_print_dat] pUserInputAdvanced->CalInterval = 9
+//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->D5TxDqPreambleCtrl[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->MemAlertEn = 0
+//// [phyinit_print_dat] pUserInputAdvanced->ATxImpedance = 53247
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnTdqs2dqTrackingTg2[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->en_3DS = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[0] = 1
+//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[1] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[2] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->EnRxDqsTracking[3] = 0
+//// [phyinit_print_dat] pUserInputAdvanced->RstRxTrkState = 0
+//// [phyinit_print_dat] pUserInputAdvanced->TrainSequenceCtrl = 33663
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[0] = 60
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[1] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[2] = 25
+//// [phyinit_print_dat] pUserInputAdvanced->TxImpedance[3] = 25
+//// [phyinit_print_dat] pUserInputSim->tDQS2DQ = 750
+//// [phyinit_print_dat] pUserInputSim->tDQSCK = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[0] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[1] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[2] = 0
+//// [phyinit_print_dat] pUserInputSim->tSTAOFF[3] = 0
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // Printing values of 1D message block input/inout fields, PState=0
+//// [phyinit_print_dat] //
+//// [phyinit_print_dat] // ####################################################
+//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f
+//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].AdvTrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MsgMisc = 0x7
+//// [phyinit_print_dat] mb_DDR5U_1D[0].Pstate = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PllBypassEn = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DRAMFreq = 0xc80
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RXEN_ADJ = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_DFE_Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyVref = 0x40
+//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].SequenceCtrl = 0x837f
+//// [phyinit_print_dat] mb_DDR5U_1D[0].HdtCtrl = 0xc8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyCfg = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFIMRLMargin = 0x2
+//// [phyinit_print_dat] mb_DDR5U_1D[0].X16Present = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].UseBroadcastMR = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].D5Quickboot = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDbyte = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CATrainOpt = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_DFE_Misc = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].TX2D_TrainOpt = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].Share2DVrefResult = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MRE_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DWL_MIN_PULSE = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].PhyConfigOverride = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChA = 0x10
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChA = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A0 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A0 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A0 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A1 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A1 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A1 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A2 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A2 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A2 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_A3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_A3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_A3 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_A3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_A3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_A3 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_A3 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_A3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_A3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_A3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_A3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].EnabledDQsChB = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].CsPresentChB = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B0 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B0 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B0 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B0 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B0 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B0 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B0_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B1 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B1 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B1 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B1 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B1 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B1 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B1_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B2 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B2 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B2 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B2 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B2 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B2 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B2_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR0_B3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR2_B3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR4_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR5_B3 = 0x20
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR6_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR8_B3 = 0x8
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR10_B3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3 = 0x2d
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3 = 0xd6
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR14_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR15_B3 = 0x3
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR111_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR34_B3 = 0x11
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR35_B3 = 0x4
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR32_ORG_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR37_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR38_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR39_B3 = 0x2c
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR11_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR12_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR13_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_ORG_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR33_B3_next = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR50_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR51_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR52_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DFE_GainBias_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WR_RD_RTT_PARK_B3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_START = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].WL_ADJ_END = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D0 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChA_D1 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChA_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D0 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW00_ChB_D1 = 0x1
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW01_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW02_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW03_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW04_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW05_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW06_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW07_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW08_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW09_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW0F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW10_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW11_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW12_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW13_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW14_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW15_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW16_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW17_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW18_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW19_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW1F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW20_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW21_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW22_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW23_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW24_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW25_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW26_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW27_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW28_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW29_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW2F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW30_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW31_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW32_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW33_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW34_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW35_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW36_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW37_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW38_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW39_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW3F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW40_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW41_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW42_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW43_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW44_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW45_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW46_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW47_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW48_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW49_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW4F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW50_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW51_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW52_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW53_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW54_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW55_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW56_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW57_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW58_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW59_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW5F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW60_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW61_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW62_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW63_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW64_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW65_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW66_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW67_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW68_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW69_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW6F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW70_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW71_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW72_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW73_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW74_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW75_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW76_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW77_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW78_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW79_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].RCW7F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW00_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW01_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW02_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW03_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW04_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW05_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW06_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW07_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW08_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW09_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW0F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW10_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW11_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW12_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW13_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW14_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW15_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW16_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW17_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW18_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW19_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW1F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW20_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW21_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW22_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW23_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW24_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW25_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW26_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW27_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW28_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW29_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW2F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW30_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW31_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW32_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW33_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW34_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW35_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW36_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW37_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW38_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW39_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW3F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW40_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW41_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW42_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW43_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW44_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW45_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW46_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW47_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW48_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW49_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW4F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW50_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW51_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW52_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW53_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW54_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW55_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW56_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW57_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW58_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW59_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW5F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW60_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW61_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW62_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW63_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW64_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW65_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW66_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW67_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW68_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW69_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW6F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW70_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW71_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW72_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW73_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW74_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW75_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW76_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW77_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW78_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW79_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7A_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7B_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7C_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7D_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7E_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].BCW7F_ChB_D1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR0Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR1Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR2Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib0 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib1 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib2 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib3 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib4 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib5 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib6 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib7 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib8 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib9 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib10 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib11 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib12 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib13 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib14 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib15 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib16 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib17 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib18 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefDqR3Nib19 = 0x17
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].MR3R3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCSR3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR0Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR1Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR2Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib4 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib5 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib6 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib7 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib8 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib9 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib10 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib11 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib12 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib13 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib14 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib15 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib16 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib17 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib18 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].VrefCAR3Nib19 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR0 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR1 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR2 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB0LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB1LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB2LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB3LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB4LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB5LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB6LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB7LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB8LaneR3 = 0x0
+//// [phyinit_print_dat] mb_DDR5U_1D[0].DisabledDB9LaneR3 = 0x0
+
+////##############################################################
+////
+//// Step (A) : Bring up VDD, VDDQ, and VAA
+////
+//// The power supplies can come up and stabilize in any order.
+//// While the power supplies are coming up, all outputs will be unknown and
+//// the values of the inputs are don't cares.
+////
+////##############################################################
+
+dwc_ddrphy_phyinit_userCustom_A_bringupPower();
+
+//[dwc_ddrphy_phyinit_userCustom_A_bringupPower] End of dwc_ddrphy_phyinit_userCustom_A_bringupPower()
+//
+//
+////##############################################################
+////
+//// 4.3.2(B) Start Clocks and Reset the PHY
+////
+//// Following is one possbile sequence to reset the PHY. Other sequences are also possible.
+//// See section 5.2.2 of the PUB for other possible reset sequences.
+////
+//// 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X.
+//// 2. Start DfiClk and APBCLK
+//// 3. Drive Reset to 1 and PRESETn_APB to 0.
+//// Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY.
+//// 4. Wait a minimum of 8 cycles.
+//// 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted),
+//// DfiClk synchronously switches to any legal input frequency.
+//// 6. Wait a minimum of 64 cycles. Note: This is the reset period for the PHY.
+//// 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states before the deassertion of Reset.
+//// 8. Wait a minimum of 1 Cycle.
+//// 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus.
+////10. The PHY is now in the reset state and is ready to accept APB transactions.
+////
+////##############################################################
+//
+//
+dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(sdrammc);
+
+//// [dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy] End of dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy()
+//
+
+////##############################################################
+////
+//// Step (C) Initialize PHY Configuration
+////
+//// Load the required PHY configuration registers for the appropriate mode and memory configuration
+////
+////##############################################################
+//
+
+//// [phyinit_C_initPhyConfig] Start of dwc_ddrphy_phyinit_C_initPhyConfig()
+//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1
+dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for MASTER
+dwc_ddrphy_apb_wr(0x20029, 0x58); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl1_p0
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10029, 0x58); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x11029, 0x58); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl1_p0
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl1::VshDAC to 0x16 for all ANIBs
+dwc_ddrphy_apb_wr(0x29, 0x58); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x1029, 0x58); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x2029, 0x58); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x3029, 0x58); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x4029, 0x58); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x5029, 0x58); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x6029, 0x58); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x7029, 0x58); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x8029, 0x58); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x9029, 0x58); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl1_p0
+dwc_ddrphy_apb_wr(0x90301, 0x59); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR1_p0
+dwc_ddrphy_apb_wr(0x90302, 0x58); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::CsrTxSrc to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate::TxPreDrvMode to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxSlewRate to 0x0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for TxSlewRate::CsrTxSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+dwc_ddrphy_apb_wr(0x1005f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b0_p0
+dwc_ddrphy_apb_wr(0x1015f, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxSlewRate_b1_p0
+dwc_ddrphy_apb_wr(0x1105f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b0_p0
+dwc_ddrphy_apb_wr(0x1115f, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxSlewRate_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::ATxPreDrvMode to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 0 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 0 to 0x1be
+dwc_ddrphy_apb_wr(0x55, 0x1be); // DWC_DDRPHYA_ANIB0_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 1 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 1 to 0x1be
+dwc_ddrphy_apb_wr(0x1055, 0x1be); // DWC_DDRPHYA_ANIB1_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 2 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 2 to 0x1be
+dwc_ddrphy_apb_wr(0x2055, 0x1be); // DWC_DDRPHYA_ANIB2_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 3 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 3 to 0x1be
+dwc_ddrphy_apb_wr(0x3055, 0x1be); // DWC_DDRPHYA_ANIB3_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 4 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 4 to 0x1be
+dwc_ddrphy_apb_wr(0x4055, 0x1be); // DWC_DDRPHYA_ANIB4_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 5 to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 5 to 0x0
+dwc_ddrphy_apb_wr(0x5055, 0x0); // DWC_DDRPHYA_ANIB5_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 6 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 6 to 0x1be
+dwc_ddrphy_apb_wr(0x6055, 0x1be); // DWC_DDRPHYA_ANIB6_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 7 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 7 to 0x1be
+dwc_ddrphy_apb_wr(0x7055, 0x1be); // DWC_DDRPHYA_ANIB7_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 8 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 8 to 0x1be
+dwc_ddrphy_apb_wr(0x8055, 0x1be); // DWC_DDRPHYA_ANIB8_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate::CsrATxSrc ANIB 9 to 0x1be
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxSlewRate ANIB 9 to 0x1be
+dwc_ddrphy_apb_wr(0x9055, 0x1be); // DWC_DDRPHYA_ANIB9_base0_ATxSlewRate_p0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for ATxSlewRate::CsrATxSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::CsrTxOvSrc to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseN to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride::TxCalBaseP to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalPreDriverOverride to 0x300
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for CalPreDriverOverride::CsrTxOvSrc are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult the "Output Slew Rate" section of HSpice Model App Note in specific technology for recommended settings
+
+dwc_ddrphy_apb_wr(0x2008c, 0x300); // DWC_DDRPHYA_MASTER0_base0_CalPreDriverOverride
+//// [phyinit_C_initPhyConfig] PUB revision is 0x0350.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl2::PllFreqSel to 0x19 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200c5, 0x19); // DWC_DDRPHYA_MASTER0_base0_PllCtrl2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpPropCtrl to 0x3 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1::PllCpIntCtrl to 0x1 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl1 to 0x61 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200c7, 0x21); // DWC_DDRPHYA_MASTER0_base0_PllCtrl1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllTestMode to 0x400f based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200ca, 0x402f); // DWC_DDRPHYA_MASTER0_base0_PllTestMode_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpPropGsCtrl to 0x6 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4::PllCpIntGsCtrl to 0x12 based on DfiClk frequency = 800.
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming PllCtrl4 to 0xd2 based on DfiClk frequency = 800.
+dwc_ddrphy_apb_wr(0x200cc, 0x17f); // DWC_DDRPHYA_MASTER0_base0_PllCtrl4_p0
+//// [phyinit_C_initPhyConfig] ### NOTE ### Optimal setting for PllCtrl1 and PllTestMode are technology specific.
+//// [phyinit_C_initPhyConfig] ### NOTE ### Please consult technology specific PHY Databook for recommended settings
+
+//
+////##############################################################
+////
+//// Program ARdPtrInitVal based on Frequency and PLL Bypass inputs
+//// The values programmed here assume ideal properties of DfiClk
+//// and Pclk including:
+//// - DfiClk skew
+//// - DfiClk jitter
+//// - DfiClk PVT variations
+//// - Pclk skew
+//// - Pclk jitter
+////
+//// PLL Bypassed mode:
+//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 2-5
+//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5
+////
+//// PLL Enabled mode:
+//// For MemClk frequency > 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 1-5
+//// For MemClk frequency < 933MHz, the valid range of ARdPtrInitVal_p0[3:0] is: 0-5
+////
+////##############################################################
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ARdPtrInitVal to 0x1
+dwc_ddrphy_apb_wr(0x2002e, 0x1); // DWC_DDRPHYA_MASTER0_base0_ARdPtrInitVal_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DisPtrInitClrTxTracking to 0x0
+dwc_ddrphy_apb_wr(0x20051, 0x0); // DWC_DDRPHYA_MASTER0_base0_PtrInitTrackingModeCntrl_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckRxDqsPre to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::TwoTckTxDqsPre to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::PositionDfeInit to 0x2
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPreamble to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl::DDR5RxPostamble to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreambleControl to 0x88
+dwc_ddrphy_apb_wr(0x20024, 0x88); // DWC_DDRPHYA_MASTER0_base0_DqsPreambleControl_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::EnTxDqsPreamblePattern to 0x7
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern::TxDqsPreamblePattern to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPreamblePattern to 0x701
+dwc_ddrphy_apb_wr(0x200a1, 0x701); // DWC_DDRPHYA_MASTER0_base0_DqsPreamblePattern_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::EnTxDqsPostamblePattern to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern::TxDqsPostamblePattern to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqsPostamblePattern to 0x0
+dwc_ddrphy_apb_wr(0x200a2, 0x0); // DWC_DDRPHYA_MASTER0_base0_DqsPostamblePattern_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::EnTxDmPreamblePattern to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern::TxDmPreamblePattern to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DmPreamblePattern to 0xf5
+dwc_ddrphy_apb_wr(0x200fe, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DmPreamblePattern_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::EnTxDqPreamblePatternU0 to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0::TxDqPreamblePatternU0 to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU0 to 0xf5
+dwc_ddrphy_apb_wr(0x200fc, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::EnTxDqPreamblePatternU1 to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1::TxDqPreamblePatternU1 to 0xf
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DqPreamblePatternU1 to 0xf5
+dwc_ddrphy_apb_wr(0x200fd, 0xf5); // DWC_DDRPHYA_MASTER0_base0_DqPreamblePatternU1_p0
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxPreambleMode to 0x1
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl::DllRxBurstLengthMode to 0x0
+//// [phyinit_C_initPhyConfig] Programming DbyteDllModeCntrl to 0x2
+dwc_ddrphy_apb_wr(0x2003a, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteDllModeCntrl
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPu to 0x4
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxOdtDrvStren::TxOdtStrenPd to 0x0
+dwc_ddrphy_apb_wr(0x1004d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b0_p0
+dwc_ddrphy_apb_wr(0x1014d, 0x104); // DWC_DDRPHYA_DBYTE0_base0_TxOdtDrvStren_b1_p0
+dwc_ddrphy_apb_wr(0x1104d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b0_p0
+dwc_ddrphy_apb_wr(0x1114d, 0x104); // DWC_DDRPHYA_DBYTE1_base0_TxOdtDrvStren_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenP to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ADrvStrenN to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxReserved13x12 to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseN to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming ATxImpedance::ATxCalBaseP to 0x1
+dwc_ddrphy_apb_wr(0x43, 0xcfff); // DWC_DDRPHYA_ANIB0_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x1043, 0xcfff); // DWC_DDRPHYA_ANIB1_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x2043, 0xcfff); // DWC_DDRPHYA_ANIB2_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x3043, 0xcfff); // DWC_DDRPHYA_ANIB3_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x4043, 0xcfff); // DWC_DDRPHYA_ANIB4_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x5043, 0xcfff); // DWC_DDRPHYA_ANIB5_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x6043, 0xcfff); // DWC_DDRPHYA_ANIB6_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x7043, 0xcfff); // DWC_DDRPHYA_ANIB7_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x8043, 0xcfff); // DWC_DDRPHYA_ANIB8_base0_ATxImpedance
+dwc_ddrphy_apb_wr(0x9043, 0xcfff); // DWC_DDRPHYA_ANIB9_base0_ATxImpedance
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqHiPu to 0xc
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl0::TxStrenEqLoPd to 0xc
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPu to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl1::TxStrenPd to 0x3f
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqLoPu to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TxImpedanceCtrl2::TxStrenEqHiPd to 0x0
+dwc_ddrphy_apb_wr(0x10041, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b0_p0
+dwc_ddrphy_apb_wr(0x10049, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b0_p0
+dwc_ddrphy_apb_wr(0x1004b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b0_p0
+dwc_ddrphy_apb_wr(0x10141, 0x30c); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl0_b1_p0
+dwc_ddrphy_apb_wr(0x10149, 0x79e); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl1_b1_p0
+dwc_ddrphy_apb_wr(0x1014b, 0x0); // DWC_DDRPHYA_DBYTE0_base0_TxImpedanceCtrl2_b1_p0
+dwc_ddrphy_apb_wr(0x11041, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b0_p0
+dwc_ddrphy_apb_wr(0x11049, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b0_p0
+dwc_ddrphy_apb_wr(0x1104b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b0_p0
+dwc_ddrphy_apb_wr(0x11141, 0x30c); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl0_b1_p0
+dwc_ddrphy_apb_wr(0x11149, 0x79e); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl1_b1_p0
+dwc_ddrphy_apb_wr(0x1114b, 0x0); // DWC_DDRPHYA_DBYTE1_base0_TxImpedanceCtrl2_b1_p0
+//// [phyinit_C_initPhyConfig] Programming DfiMode to 0x1
+dwc_ddrphy_apb_wr(0x20018, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiMode
+//// [phyinit_C_initPhyConfig] Programming DfiCAMode to 0x10
+dwc_ddrphy_apb_wr(0x20075, 0x10); // DWC_DDRPHYA_MASTER0_base0_DfiCAMode
+//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPd50 to 0x2
+//// [phyinit_C_initPhyConfig] Programming CalDrvStr0::CalDrvStrPu50 to 0x2
+dwc_ddrphy_apb_wr(0x20050, 0x82); // DWC_DDRPHYA_MASTER0_base0_CalDrvStr0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming CalUclkInfo::CalUClkTicksPer1uS to 0x320
+dwc_ddrphy_apb_wr(0x20008, 0x320); // DWC_DDRPHYA_MASTER0_base0_CalUclkInfo_p0
+//// [phyinit_C_initPhyConfig] Programming CalRate::CalInterval to 0x9
+//// [phyinit_C_initPhyConfig] Programming CalRate::CalOnce to 0x0
+dwc_ddrphy_apb_wr(0x20088, 0x9); // DWC_DDRPHYA_MASTER0_base0_CalRate
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInSel to 0x0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x1f
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0xf8
+dwc_ddrphy_apb_wr(0x200b2, 0xf8); // DWC_DDRPHYA_MASTER0_base0_VrefInGlobal_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=0) to 0x2900
+dwc_ddrphy_apb_wr(0x10043, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=0, Upper/Lower=1) to 0x2900
+dwc_ddrphy_apb_wr(0x10143, 0x2900); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=0) to 0x2900
+dwc_ddrphy_apb_wr(0x11043, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl (Byte=1, Upper/Lower=1) to 0x2900
+dwc_ddrphy_apb_wr(0x11143, 0x2900); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl_b1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Programming DqDqsRcvCntrl2 to 0x1c
+dwc_ddrphy_apb_wr(0x1004c, 0x1c); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl2_p0
+dwc_ddrphy_apb_wr(0x1104c, 0x1c); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DisDynAdrTri_p0 to 0x1
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming TristateModeCA::DDR2TMode_p0 to 0x0
+dwc_ddrphy_apb_wr(0x20019, 0x5); // DWC_DDRPHYA_MASTER0_base0_TristateModeCA_p0
+//// [phyinit_C_initPhyConfig] Programming DfiFreqXlat*
+dwc_ddrphy_apb_wr(0x200f0, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat0
+dwc_ddrphy_apb_wr(0x200f1, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat1
+dwc_ddrphy_apb_wr(0x200f2, 0x4444); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat2
+dwc_ddrphy_apb_wr(0x200f3, 0x8888); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat3
+dwc_ddrphy_apb_wr(0x200f4, 0x5555); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat4
+dwc_ddrphy_apb_wr(0x200f5, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat5
+dwc_ddrphy_apb_wr(0x200f6, 0x0); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat6
+dwc_ddrphy_apb_wr(0x200f7, 0xf000); // DWC_DDRPHYA_MASTER0_base0_DfiFreqXlat7
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY0 to 0x64
+dwc_ddrphy_apb_wr(0x2000b, 0x64); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY0_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY1 to 0xc8
+dwc_ddrphy_apb_wr(0x2000c, 0xc8); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY1_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY2 to 0x2bc
+dwc_ddrphy_apb_wr(0x2000d, 0x2bc); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY2_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming Seq0BDLY3 to 0x2c
+dwc_ddrphy_apb_wr(0x2000e, 0x2c); // DWC_DDRPHYA_MASTER0_base0_Seq0BDLY3_p0
+//// [phyinit_C_initPhyConfig] Disabling DBYTE 0 Lane 8 (DBI) Receiver to save power.
+dwc_ddrphy_apb_wr(0x1004a, 0x500); // DWC_DDRPHYA_DBYTE0_base0_DqDqsRcvCntrl1
+//// [phyinit_C_initPhyConfig] Disabling DBYTE 1 Lane 8 (DBI) Receiver to save power.
+dwc_ddrphy_apb_wr(0x1104a, 0x500); // DWC_DDRPHYA_DBYTE1_base0_DqDqsRcvCntrl1
+//// [phyinit_C_initPhyConfig] Programming MasterX4Config::X4TG to 0x0
+dwc_ddrphy_apb_wr(0x20025, 0x0); // DWC_DDRPHYA_MASTER0_base0_MasterX4Config
+// [phyinit_C_initPhyConfig] Programming DfiDataEnLatency::WLm13 and RLm13
+dwc_ddrphy_apb_wr(0x2019a, 0x18); // DWC_DDRPHYA_MASTER0_base0_DfiDataEnLatency
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, rd_Crc = 0 cwl= 24 , cl = 26 mr_cl =2 MR0_A0 = 0x8
+dwc_ddrphy_apb_wr(0x400f5, 0x1200); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl5_p0
+dwc_ddrphy_apb_wr(0x400f6, 0x10); // DWC_DDRPHYA_ACSM0_base0_AcsmCtrl6_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxEnPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RxValPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0RdcsPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0TxEnPulse to 2060
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0WrcsPulse to 2060
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopPulse to 2062
+dwc_ddrphy_apb_wr(0x20120, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxEnPulse_p0
+dwc_ddrphy_apb_wr(0x20121, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RxValPulse_p0
+dwc_ddrphy_apb_wr(0x20124, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0RdcsPulse_p0
+dwc_ddrphy_apb_wr(0x20122, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0TxEnPulse_p0
+dwc_ddrphy_apb_wr(0x20123, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0WrcsPulse_p0
+dwc_ddrphy_apb_wr(0x20125, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopPulse_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM0SnoopVal to 801
+dwc_ddrphy_apb_wr(0x2012e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0SnoopVal
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxEnPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RxValPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1RdcsPulse to 2062
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1TxEnPulse to 2060
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1WrcsPulse to 2060
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopPulse to 2062
+dwc_ddrphy_apb_wr(0x20140, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxEnPulse_p0
+dwc_ddrphy_apb_wr(0x20141, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RxValPulse_p0
+dwc_ddrphy_apb_wr(0x20144, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1RdcsPulse_p0
+dwc_ddrphy_apb_wr(0x20142, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1TxEnPulse_p0
+dwc_ddrphy_apb_wr(0x20143, 0x80c); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1WrcsPulse_p0
+dwc_ddrphy_apb_wr(0x20145, 0x80e); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopPulse_p0
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming D5ACSM1SnoopVal to 801
+dwc_ddrphy_apb_wr(0x2014e, 0x321); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1SnoopVal
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming GPR7(csrAlertRecovery) to 0x0
+dwc_ddrphy_apb_wr(0x90307, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR7_p0
+// [phyinit_C_initPhyConfig] Programming TimingModeCntrl::Dly64Prec to 0x1
+dwc_ddrphy_apb_wr(0x20040, 0x1); // DWC_DDRPHYA_MASTER0_base0_TimingModeCntrl
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x1); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x1); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x1); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x1 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x1); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x1); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x1); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x1); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x1); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x1); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x1); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x1); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x1); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x1); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming AcClkDLLControl to 0x1080
+dwc_ddrphy_apb_wr(0x200ea, 0x1080); // DWC_DDRPHYA_MASTER0_base0_AcClkDLLControl_p0
+// [phyinit_C_initPhyConfig] Programming ArcPmuEccCtl to 0x1
+dwc_ddrphy_apb_wr(0xc0086, 0x1); // DWC_DDRPHYA_DRTUB0_ArcPmuEccCtl
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x9820 for MASTER
+dwc_ddrphy_apb_wr(0x2002b, 0x9820); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all DBYTEs
+dwc_ddrphy_apb_wr(0x1002b, 0x8020); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x1102b, 0x8020); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Programming VREGCtrl2 to 0x8020 for all ANIBs
+dwc_ddrphy_apb_wr(0x2b, 0x8020); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x102b, 0x8020); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x202b, 0x8020); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x302b, 0x8020); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x402b, 0x8020); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x502b, 0x8020); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x602b, 0x8020); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x702b, 0x8020); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x802b, 0x8020); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl2
+dwc_ddrphy_apb_wr(0x902b, 0x8020); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl2
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for MASTER
+dwc_ddrphy_apb_wr(0x20066, 0x0); // DWC_DDRPHYA_MASTER0_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all DBYTEs
+dwc_ddrphy_apb_wr(0x10066, 0x0); // DWC_DDRPHYA_DBYTE0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x11066, 0x0); // DWC_DDRPHYA_DBYTE1_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming VREGCtrl3::VshCtrlUpdate to 0x0 for all ANIBs
+dwc_ddrphy_apb_wr(0x66, 0x0); // DWC_DDRPHYA_ANIB0_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x1066, 0x0); // DWC_DDRPHYA_ANIB1_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x2066, 0x0); // DWC_DDRPHYA_ANIB2_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x3066, 0x0); // DWC_DDRPHYA_ANIB3_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x4066, 0x0); // DWC_DDRPHYA_ANIB4_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x5066, 0x0); // DWC_DDRPHYA_ANIB5_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x6066, 0x0); // DWC_DDRPHYA_ANIB6_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x7066, 0x0); // DWC_DDRPHYA_ANIB7_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x8066, 0x0); // DWC_DDRPHYA_ANIB8_base0_VREGCtrl3
+dwc_ddrphy_apb_wr(0x9066, 0x0); // DWC_DDRPHYA_ANIB9_base0_VREGCtrl3
+// [phyinit_C_initPhyConfig] Programming VrefDAC0 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC1 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC2 to 0x3f for all DBYTEs and lanes
+// [phyinit_C_initPhyConfig] Programming VrefDAC3 to 0x3f for all DBYTEs and lanes
+dwc_ddrphy_apb_wr(0x10040, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r0_p0
+dwc_ddrphy_apb_wr(0x10030, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r0
+dwc_ddrphy_apb_wr(0x10050, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r0
+dwc_ddrphy_apb_wr(0x10060, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r0
+dwc_ddrphy_apb_wr(0x10140, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r1_p0
+dwc_ddrphy_apb_wr(0x10130, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r1
+dwc_ddrphy_apb_wr(0x10150, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r1
+dwc_ddrphy_apb_wr(0x10160, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r1
+dwc_ddrphy_apb_wr(0x10240, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r2_p0
+dwc_ddrphy_apb_wr(0x10230, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r2
+dwc_ddrphy_apb_wr(0x10250, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r2
+dwc_ddrphy_apb_wr(0x10260, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r2
+dwc_ddrphy_apb_wr(0x10340, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r3_p0
+dwc_ddrphy_apb_wr(0x10330, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r3
+dwc_ddrphy_apb_wr(0x10350, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r3
+dwc_ddrphy_apb_wr(0x10360, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r3
+dwc_ddrphy_apb_wr(0x10440, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r4_p0
+dwc_ddrphy_apb_wr(0x10430, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r4
+dwc_ddrphy_apb_wr(0x10450, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r4
+dwc_ddrphy_apb_wr(0x10460, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r4
+dwc_ddrphy_apb_wr(0x10540, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r5_p0
+dwc_ddrphy_apb_wr(0x10530, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r5
+dwc_ddrphy_apb_wr(0x10550, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r5
+dwc_ddrphy_apb_wr(0x10560, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r5
+dwc_ddrphy_apb_wr(0x10640, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r6_p0
+dwc_ddrphy_apb_wr(0x10630, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r6
+dwc_ddrphy_apb_wr(0x10650, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r6
+dwc_ddrphy_apb_wr(0x10660, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r6
+dwc_ddrphy_apb_wr(0x10740, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r7_p0
+dwc_ddrphy_apb_wr(0x10730, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r7
+dwc_ddrphy_apb_wr(0x10750, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r7
+dwc_ddrphy_apb_wr(0x10760, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r7
+dwc_ddrphy_apb_wr(0x10840, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC0_r8_p0
+dwc_ddrphy_apb_wr(0x10830, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC1_r8
+dwc_ddrphy_apb_wr(0x10850, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC2_r8
+dwc_ddrphy_apb_wr(0x10860, 0x3f); // DWC_DDRPHYA_DBYTE0_base0_VrefDAC3_r8
+dwc_ddrphy_apb_wr(0x11040, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r0_p0
+dwc_ddrphy_apb_wr(0x11030, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r0
+dwc_ddrphy_apb_wr(0x11050, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r0
+dwc_ddrphy_apb_wr(0x11060, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r0
+dwc_ddrphy_apb_wr(0x11140, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r1_p0
+dwc_ddrphy_apb_wr(0x11130, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r1
+dwc_ddrphy_apb_wr(0x11150, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r1
+dwc_ddrphy_apb_wr(0x11160, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r1
+dwc_ddrphy_apb_wr(0x11240, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r2_p0
+dwc_ddrphy_apb_wr(0x11230, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r2
+dwc_ddrphy_apb_wr(0x11250, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r2
+dwc_ddrphy_apb_wr(0x11260, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r2
+dwc_ddrphy_apb_wr(0x11340, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r3_p0
+dwc_ddrphy_apb_wr(0x11330, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r3
+dwc_ddrphy_apb_wr(0x11350, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r3
+dwc_ddrphy_apb_wr(0x11360, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r3
+dwc_ddrphy_apb_wr(0x11440, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r4_p0
+dwc_ddrphy_apb_wr(0x11430, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r4
+dwc_ddrphy_apb_wr(0x11450, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r4
+dwc_ddrphy_apb_wr(0x11460, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r4
+dwc_ddrphy_apb_wr(0x11540, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r5_p0
+dwc_ddrphy_apb_wr(0x11530, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r5
+dwc_ddrphy_apb_wr(0x11550, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r5
+dwc_ddrphy_apb_wr(0x11560, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r5
+dwc_ddrphy_apb_wr(0x11640, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r6_p0
+dwc_ddrphy_apb_wr(0x11630, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r6
+dwc_ddrphy_apb_wr(0x11650, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r6
+dwc_ddrphy_apb_wr(0x11660, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r6
+dwc_ddrphy_apb_wr(0x11740, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r7_p0
+dwc_ddrphy_apb_wr(0x11730, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r7
+dwc_ddrphy_apb_wr(0x11750, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r7
+dwc_ddrphy_apb_wr(0x11760, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r7
+dwc_ddrphy_apb_wr(0x11840, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC0_r8_p0
+dwc_ddrphy_apb_wr(0x11830, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC1_r8
+dwc_ddrphy_apb_wr(0x11850, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC2_r8
+dwc_ddrphy_apb_wr(0x11860, 0x3f); // DWC_DDRPHYA_DBYTE1_base0_VrefDAC3_r8
+//// [phyinit_C_initPhyConfig] Pstate=0, Memclk=1600MHz, Programming DfiFreqRatio_p0 to 0x1
+dwc_ddrphy_apb_wr(0x200fa, 0x1); // DWC_DDRPHYA_MASTER0_base0_DfiFreqRatio_p0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=0) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=0) to 0x0
+dwc_ddrphy_apb_wr(0x100aa, 0x0); // DWC_DDRPHYA_DBYTE0_base0_PptCtlStatic
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg0 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg1 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg2 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::DOCByteSelTg3 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg0 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg1 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg2 (dbyte=1) to 0x0
+//// [phyinit_C_initPhyConfig] Programming PptCtlStatic::NoX4onUpperNibbleTg3 (dbyte=1) to 0x0
+dwc_ddrphy_apb_wr(0x110aa, 0x0); // DWC_DDRPHYA_DBYTE1_base0_PptCtlStatic
+//// [phyinit_C_initPhyConfig] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0
+dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=0) to 0xc
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=4) to 0x8
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=6) to 0xf
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=7) to 0xf
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=8) to 0xf
+//// [phyinit_C_initPhyConfig] Programming AForceTriCont (anib=9) to 0xf
+dwc_ddrphy_apb_wr(0x28, 0xc); // DWC_DDRPHYA_ANIB0_base0_AForceTriCont
+dwc_ddrphy_apb_wr(0x4028, 0x8); // DWC_DDRPHYA_ANIB4_base0_AForceTriCont
+dwc_ddrphy_apb_wr(0x6028, 0xf); // DWC_DDRPHYA_ANIB6_base0_AForceTriCont
+dwc_ddrphy_apb_wr(0x7028, 0xf); // DWC_DDRPHYA_ANIB7_base0_AForceTriCont
+dwc_ddrphy_apb_wr(0x8028, 0xf); // DWC_DDRPHYA_ANIB8_base0_AForceTriCont
+dwc_ddrphy_apb_wr(0x9028, 0xf); // DWC_DDRPHYA_ANIB9_base0_AForceTriCont
+//// [phyinit_C_initPhyConfig] End of dwc_ddrphy_phyinit_C_initPhyConfig()
+//
+//
+////##############################################################
+////
+//// dwc_ddrphy_phyinit_userCustom_customPreTrain is a user-editable function.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_customPreTrain() is to override any
+//// any message block fields calculated by Phyinit in dwc_ddrphy_phyinit_calcMb() or to
+//// override any CSR values programmed by Phyinit in dwc_ddrphy_phyinit_C_initPhyConfig().
+//// This function is executed before training and thus any override here might affect
+//// training result.
+////
+//// IMPORTANT: in this function, user shall not override any values in userInputBasic and
+//// userInputAdvanced data structures. Use dwc_ddrphy_phyinit_userCustom_overrideUserInput()
+//// to modify values in those data structures.
+////
+////##############################################################
+//
+//// [phyinit_userCustom_customPreTrain] Start of dwc_ddrphy_phyinit_userCustom_customPreTrain()
+//// [phyinit_userCustom_customPreTrain] End of dwc_ddrphy_phyinit_userCustom_customPreTrain()
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Start of dwc_ddrphy_phyinit_D_loadIMEM (Train2D=0)
+//
+//
+////##############################################################
+////
+//// (D) Load the 1D IMEM image
+////
+//// This function loads the training firmware IMEM image into the SRAM.
+//// See PhyInit App Note for detailed description and function usage
+////
+////##############################################################
+//
+//
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] Programming MemResetL to 0x2
+dwc_ddrphy_apb_wr(0x20060, 0x2); // DWC_DDRPHYA_MASTER0_base0_MemResetL
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_imem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x50000 size 0x8000
+dwc_ddrphy_phyinit_userCustom_D_loadIMEM(sdrammc, 0);
+
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_D_loadIMEM, 1D] End of dwc_ddrphy_phyinit_D_loadIMEM()
+//
+//
+////##############################################################
+////
+//// 4.3.5(E) Set the PHY input clocks to the desired frequency for pstate 0
+////
+//// Set the PHY input Dfi Clk to the desired operating frequency associated with the given Pstate. Before proceeding to the next step,
+//// the clock should be stable at the new frequency. For more information on clocking requirements, see "Clocks" on page <XXX>.
+////
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_E_setDfiClk(sdrammc);
+
+//
+//// [dwc_ddrphy_phyinit_userCustom_E_setDfiClk] End of dwc_ddrphy_phyinit_userCustom_E_setDfiClk()
+//// [phyinit_F_loadDMEM, 1D] Start of dwc_ddrphy_phyinit_F_loadDMEM (pstate=0, Train2D=0)
+//
+//
+////##############################################################
+////
+//// 4.3.5(F) Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//
+//// 1. Load the firmware DMEM segment to initialize the data structures.
+//
+//// 2. Write the Firmware Message Block with the required contents detailing the training parameters.
+//
+// [dwc_ddrphy_phyinit_storeIncvFile] Reading input file: /home/jerry_ku/Project/Development/ast2700dev/ddr45phy_tsmc12/coreConsultant/config3_3.50a/2022-12-12-17-01-49/firmware/Latest/training/ddr5/ddr5_pmu_train_dmem.incv
+
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [dwc_ddrphy_phyinit_WriteOutMem] STARTING 32bit write. offset 0x58000 size 0x8000
+
+dwc_ddrphy_phyinit_userCustom_F_loadDMEM(sdrammc, 0, 0);
+
+dwc_ddrphy_apb_wr_32b(0x58000, 0x100);
+dwc_ddrphy_apb_wr_32b(0x58002, 0xc800000);
+dwc_ddrphy_apb_wr_32b(0x58004, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58006, 0x40);
+if (IS_ENABLED(CONFIG_ASPEED_PHY_TRAINING_MESSAGE))
+ dwc_ddrphy_apb_wr_32b(0x58008, 0x04827f);
+else
+ dwc_ddrphy_apb_wr_32b(0x58008, 0xc8827f);
+// Redmine 1392: Set X16Present=1 by Synopsys's comment
+// 0x5800b[7:0]=DFIMRLMargin, 0x5800b[15:8]=X16Present
+dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000);
+// Redmine 1456: Skip_CA13_during_CAtraining during DDR5
+dwc_ddrphy_apb_wr_32b(0x5800c, 0x10000001);
+// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value.
+// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In
+// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In
+//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00);
+//#elif defined(TRAIN_1D)
+//printf("- <DWC_DDRPHY TRAIN>: Enable RdDQS1D, WrDQ1D for 1D training");
+// #ifdef DWC_DEBUG
+//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0x05: Detailed debug messages (e.g. Eye delays)");
+//dwc_ddrphy_apb_wr_32b(0x58008, 0x05821f);
+// #else
+//printf("- <DWC_DDRPHY TRAIN>: Debug level = 0xC8: Stage completion");
+//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8821f);
+// #endif
+//// Redmine 1392: Set X16Present=1 by Synopsys's comment
+//dwc_ddrphy_apb_wr_32b(0x5800a, 0x01020000);
+//// Redmine 1456: Skip_CA13_during_CAtraining during DDR5
+//dwc_ddrphy_apb_wr_32b(0x5800c, 0x18000001);
+//// Redmine 1392: To speed up data collection, set the voltage and delay step size in Rx2D_TrainOpt and Tx2D_TrainOpt to its maximum value.
+//// uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5800e, Direction=In
+//// uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5800f, Direction=In
+//dwc_ddrphy_apb_wr_32b(0x5800e, 0x001e1e00);
+//#else
+//dwc_ddrphy_apb_wr_32b(0x58008, 0xc8837f);
+//dwc_ddrphy_apb_wr_32b(0x5800a, 0x20000);
+//dwc_ddrphy_apb_wr_32b(0x5800c, 0x8000001);
+//dwc_ddrphy_apb_wr_32b(0x5800e, 0x0);
+//#endif
+dwc_ddrphy_apb_wr_32b(0x58010, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58012, 0x110);
+dwc_ddrphy_apb_wr_32b(0x58014, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58016, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58018, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5801e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58020, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58022, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58024, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58026, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58028, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5802e, 0x84080000); //MR0 0x5802f=0x8(CL=26), MR2 0x5802f=0x84(OP[2]=1 2N mode, OP[7]=enable internal WL training)
+dwc_ddrphy_apb_wr_32b(0x58030, 0x200000); //MR5 0x58031=0x20(OP[5]=1 DM enable, OP[2:1]=0 pu 34ohm, 1=40ohm, 2=48ohm, OP7:6]=pd)
+dwc_ddrphy_apb_wr_32b(0x58032, 0x2d000800); //MR8 0x58032=0x08(OP[4:3]=1 Write preamble 2 tCK) MR10 0x58033=0x2d(Vref 75%)
+dwc_ddrphy_apb_wr_32b(0x58034, 0xd62d);
+dwc_ddrphy_apb_wr_32b(0x58036, 0x04240003); //MR32 0x58037=0x24(OP[2:0]=4 CK ODT 80, OP[5:3]=4 CS ODT 80ohm), MR33 0x58037=0x4(OP[2:0]=4 CA ODTt 80ohm)
+dwc_ddrphy_apb_wr_32b(0x58038, 0x2c000499); //MR34 0x58038(OP[5:3]=3 RTT_WR 80)
+dwc_ddrphy_apb_wr_32b(0x5803a, 0x2c2c);
+dwc_ddrphy_apb_wr_32b(0x5803c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5803e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58040, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58042, 0x408);
+dwc_ddrphy_apb_wr_32b(0x58044, 0x8000020);
+dwc_ddrphy_apb_wr_32b(0x58046, 0xd62d2d00);
+dwc_ddrphy_apb_wr_32b(0x58048, 0x30000);
+dwc_ddrphy_apb_wr_32b(0x5804a, 0x4110000);
+dwc_ddrphy_apb_wr_32b(0x5804c, 0x2c2c2c00);
+dwc_ddrphy_apb_wr_32b(0x5804e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58050, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58052, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58054, 0x4080000);
+dwc_ddrphy_apb_wr_32b(0x58056, 0x200000);
+dwc_ddrphy_apb_wr_32b(0x58058, 0x2d000800);
+dwc_ddrphy_apb_wr_32b(0x5805a, 0xd62d);
+dwc_ddrphy_apb_wr_32b(0x5805c, 0x3);
+dwc_ddrphy_apb_wr_32b(0x5805e, 0x2c000411);
+dwc_ddrphy_apb_wr_32b(0x58060, 0x2c2c);
+dwc_ddrphy_apb_wr_32b(0x58062, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58064, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58066, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58068, 0x408);
+dwc_ddrphy_apb_wr_32b(0x5806a, 0x8000020);
+dwc_ddrphy_apb_wr_32b(0x5806c, 0xd62d2d00);
+dwc_ddrphy_apb_wr_32b(0x5806e, 0x30000);
+dwc_ddrphy_apb_wr_32b(0x58070, 0x4110000);
+dwc_ddrphy_apb_wr_32b(0x58072, 0x2c2c2c00);
+dwc_ddrphy_apb_wr_32b(0x58074, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58076, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58078, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5807e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58080, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58082, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58084, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58086, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58088, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5808e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58090, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58092, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58094, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58096, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58098, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5809e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580a4, 0x4080000);
+dwc_ddrphy_apb_wr_32b(0x580a6, 0x200000);
+dwc_ddrphy_apb_wr_32b(0x580a8, 0x2d000800);
+dwc_ddrphy_apb_wr_32b(0x580aa, 0xd62d);
+dwc_ddrphy_apb_wr_32b(0x580ac, 0x3);
+dwc_ddrphy_apb_wr_32b(0x580ae, 0x2c000411);
+dwc_ddrphy_apb_wr_32b(0x580b0, 0x2c2c);
+dwc_ddrphy_apb_wr_32b(0x580b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580b8, 0x408);
+dwc_ddrphy_apb_wr_32b(0x580ba, 0x8000020);
+dwc_ddrphy_apb_wr_32b(0x580bc, 0xd62d2d00);
+dwc_ddrphy_apb_wr_32b(0x580be, 0x30000);
+dwc_ddrphy_apb_wr_32b(0x580c0, 0x4110000);
+dwc_ddrphy_apb_wr_32b(0x580c2, 0x2c2c2c00);
+dwc_ddrphy_apb_wr_32b(0x580c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ca, 0x4080000);
+dwc_ddrphy_apb_wr_32b(0x580cc, 0x200000);
+dwc_ddrphy_apb_wr_32b(0x580ce, 0x2d000800);
+dwc_ddrphy_apb_wr_32b(0x580d0, 0xd62d);
+dwc_ddrphy_apb_wr_32b(0x580d2, 0x3);
+dwc_ddrphy_apb_wr_32b(0x580d4, 0x2c000411);
+dwc_ddrphy_apb_wr_32b(0x580d6, 0x2c2c);
+dwc_ddrphy_apb_wr_32b(0x580d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580de, 0x408);
+dwc_ddrphy_apb_wr_32b(0x580e0, 0x8000020);
+dwc_ddrphy_apb_wr_32b(0x580e2, 0xd62d2d00);
+dwc_ddrphy_apb_wr_32b(0x580e4, 0x30000);
+dwc_ddrphy_apb_wr_32b(0x580e6, 0x4110000);
+dwc_ddrphy_apb_wr_32b(0x580e8, 0x2c2c2c00);
+dwc_ddrphy_apb_wr_32b(0x580ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x580fe, 0xa00060); // WL_ADJ_START, WL_ADJ_END
+dwc_ddrphy_apb_wr_32b(0x58100, 0x1);
+dwc_ddrphy_apb_wr_32b(0x58102, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58104, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58106, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58108, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5810e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58110, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58112, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58114, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58116, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58118, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5811e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58120, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58122, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58124, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58126, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58128, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5812e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58130, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58132, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58134, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58136, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58138, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5813e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58140, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58142, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58144, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58146, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58148, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5814e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58150, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58152, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58154, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58156, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58158, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5815e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58160, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58162, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58164, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58166, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58168, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5816e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58170, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58172, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58174, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58176, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58178, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5817e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58180, 0x1);
+dwc_ddrphy_apb_wr_32b(0x58182, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58184, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58186, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58188, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5818e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58190, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58192, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58194, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58196, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58198, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5819e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x581fe, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58200, 0x1);
+dwc_ddrphy_apb_wr_32b(0x58202, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58204, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58206, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58208, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5820a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5820c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5820e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58210, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58212, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58214, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58216, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58218, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5821a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5821c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5821e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58220, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58222, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58224, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58226, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58228, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5822a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5822c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5822e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58230, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58232, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58234, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58236, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58238, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5823a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5823c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5823e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58240, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58242, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58244, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58246, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58248, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5824a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5824c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5824e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58250, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58252, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58254, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58256, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58258, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5825a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5825c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5825e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58260, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58262, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58264, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58266, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58268, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5826a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5826c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5826e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58270, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58272, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58274, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58276, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58278, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5827a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5827c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5827e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58280, 0x1);
+dwc_ddrphy_apb_wr_32b(0x58282, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58284, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58286, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58288, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5828a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5828c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5828e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58290, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58292, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58294, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58296, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58298, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5829a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5829c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5829e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x582fe, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58300, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58302, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58304, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58306, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58308, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5830a, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5830c, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5830e, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58310, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58312, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58314, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58316, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58318, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5831a, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5831c, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x5831e, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58320, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58322, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58324, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58326, 0x17171717);
+dwc_ddrphy_apb_wr_32b(0x58328, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5832a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5832c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5832e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58330, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58332, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58334, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58336, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58338, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5833a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5833c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5833e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58340, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58342, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58344, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58346, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58348, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5834a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5834c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5834e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58350, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58352, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58354, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58356, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58358, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5835a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5835c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5835e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58360, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58362, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58364, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58366, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58368, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5836a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5836c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5836e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58370, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58372, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58374, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58376, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58378, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5837a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5837c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5837e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58380, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58382, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58384, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58386, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58388, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5838a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5838c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5838e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58390, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58392, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58394, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58396, 0x0);
+dwc_ddrphy_apb_wr_32b(0x58398, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5839a, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5839c, 0x0);
+dwc_ddrphy_apb_wr_32b(0x5839e, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583a0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583a2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583a4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583a6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583a8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583aa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ac, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ae, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583b0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583b2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583b4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583b6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583b8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ba, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583bc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583be, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583c0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583c2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583c4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583c6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583c8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ca, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583cc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ce, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583d0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583d2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583d4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583d6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583d8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583da, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583dc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583de, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583e0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583e2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583e4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583e6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583e8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ea, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ec, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583ee, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583f0, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583f2, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583f4, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583f6, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583f8, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583fa, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583fc, 0x0);
+dwc_ddrphy_apb_wr_32b(0x583fe, 0x0);
+//// [dwc_ddrphy_phyinit_WriteOutMem] DONE. Index 0x8000
+//// 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+//// This allows the firmware unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_F_loadDMEM, 1D] End of dwc_ddrphy_phyinit_F_loadDMEM()
+//
+//
+////##############################################################
+////
+//// 4.3.7(G) Execute the Training Firmware
+////
+//// The training firmware is executed with the following procedure:
+////
+////##############################################################
+//
+//
+//// 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the StallToMicro and
+//// ResetToMicro fields to 1 (all other fields should be zero).
+//// Then rewrite the CSR so that only the StallToMicro remains set (all other fields should be zero).
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+dwc_ddrphy_apb_wr(0xd0099, 0x9); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 2. Begin execution of the training firmware by setting the MicroReset CSR to 4'b0000.
+dwc_ddrphy_apb_wr(0xd0099, 0x0); // DWC_DDRPHYA_APBONLY0_MicroReset
+//
+//// 3. Wait for the training firmware to complete by following the procedure in "uCtrl Initialization and Mailbox Messaging"
+//// 4.3.7 3. Wait for the training firmware to complete. Implement timeout function or follow the procedure in "3.4 Running the firmware" of the Training Firmware Application Note to poll the Mailbox message.
+dwc_ddrphy_phyinit_userCustom_G_waitFwDone(sdrammc);
+
+//// [dwc_ddrphy_phyinit_userCustom_G_waitFwDone] End of dwc_ddrphy_phyinit_userCustom_G_waitFwDone()
+//// 4. Halt the microcontroller."
+dwc_ddrphy_apb_wr(0xd0099, 0x1); // DWC_DDRPHYA_APBONLY0_MicroReset
+dwc_ddrphy_apb_wr(0x20089, 0x0); // DWC_DDRPHYA_MASTER0_base0_CalZap
+//// [dwc_ddrphy_phyinit_G_execFW] End of dwc_ddrphy_phyinit_G_execFW()
+//
+//
+////##############################################################
+////
+//// 4.3.8(H) Read the Message Block results
+////
+//// The procedure is as follows:
+////
+////##############################################################
+//
+//
+//// 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//
+//2. Read the Firmware Message Block to obtain the results from the training.
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+//Example:
+//if (Train2D)
+//{
+// _read_2d_message_block_outputs_
+//}
+//else
+//{
+// _read_1d_message_block_outputs_
+//}
+//This can be accomplished by issuing APB read commands to the DMEM addresses.
+dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(sdrammc, 0);
+
+//[dwc_ddrphy_phyinit_userCustom_H_readMsgBlock] End of dwc_ddrphy_phyinit_userCustom_H_readMsgBlock()
+//// 3. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// 4. If training is required at another frequency, repeat the operations starting at step (E).
+//// [dwc_ddrphy_phyinit_H_readMsgBlock] End of dwc_ddrphy_phyinit_H_readMsgBlock()
+//// [initRuntimeConfigEnableBits] Start of initRuntimeConfigEnableBits()
+//// [initRuntimeConfigEnableBits] enableBits[0] = 0x00000009
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A0 = 0x00000000, rtt_required = 0x00000001
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A1 = 0x00000000, rtt_required = 0x00000002
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A2 = 0x00000000, rtt_required = 0x00000004
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_A3 = 0x00000000, rtt_required = 0x00000008
+//// [initRuntimeConfigEnableBits] enableBits[1] = 0x00000000
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B0 = 0x00000000, rtt_required = 0x00000001
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B1 = 0x00000000, rtt_required = 0x00000002
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B2 = 0x00000000, rtt_required = 0x00000004
+//// [initRuntimeConfigEnableBits] WR_RD_RTT_PARK_B3 = 0x00000000, rtt_required = 0x00000008
+//// [initRuntimeConfigEnableBits] enableBits[2] = 0x00000000
+//// [initRuntimeConfigEnableBits] End of initRuntimeConfigEnableBits()
+//// [phyinit_I_loadPIEImage] Start of dwc_ddrphy_phyinit_I_loadPIEImage()
+//
+//
+////##############################################################
+////
+//// 4.3.9(I) Load PHY Init Engine Image
+////
+//// Load the PHY Initialization Engine memory with the provided initialization sequence.
+////
+////##############################################################
+//
+//
+//// Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0.
+//// This allows the memory controller unrestricted access to the configuration CSRs.
+dwc_ddrphy_apb_wr(0xd0000, 0x0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x1
+dwc_ddrphy_apb_wr(0x200a6, 0x2); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// [phyinit_I_loadPIEImage] Programming PIE Production Code
+//// [phyinit_LoadPIECodeSections] Start of dwc_ddrphy_phyinit_LoadPIECodeSections()
+//// [phyinit_LoadPIECodeSections] Moving start address from 0 to 90000
+dwc_ddrphy_apb_wr(0x90000, 0x10); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x90001, 0x400); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x90002, 0x10e); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x90003, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x90004, 0x0); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x90005, 0x8); // DWC_DDRPHYA_INITENG0_base0_PreSequenceReg0b1s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 90006 to 41000
+dwc_ddrphy_apb_wr(0x41000, 0x3fff);
+dwc_ddrphy_apb_wr(0x41001, 0xff00);
+dwc_ddrphy_apb_wr(0x41002, 0x3f);
+dwc_ddrphy_apb_wr(0x41003, 0x2c1);
+dwc_ddrphy_apb_wr(0x41004, 0x3fff);
+dwc_ddrphy_apb_wr(0x41005, 0xff00);
+dwc_ddrphy_apb_wr(0x41006, 0x3f);
+dwc_ddrphy_apb_wr(0x41007, 0xa01);
+dwc_ddrphy_apb_wr(0x41008, 0x3fff);
+dwc_ddrphy_apb_wr(0x41009, 0xff00);
+dwc_ddrphy_apb_wr(0x4100a, 0x3f);
+dwc_ddrphy_apb_wr(0x4100b, 0x1);
+dwc_ddrphy_apb_wr(0x4100c, 0xffff);
+dwc_ddrphy_apb_wr(0x4100d, 0xff03);
+dwc_ddrphy_apb_wr(0x4100e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4100f, 0x0);
+dwc_ddrphy_apb_wr(0x41010, 0xffff);
+dwc_ddrphy_apb_wr(0x41011, 0xff03);
+dwc_ddrphy_apb_wr(0x41012, 0x3ff);
+dwc_ddrphy_apb_wr(0x41013, 0x1c1);
+dwc_ddrphy_apb_wr(0x41014, 0xffff);
+dwc_ddrphy_apb_wr(0x41015, 0xff03);
+dwc_ddrphy_apb_wr(0x41016, 0x3ff);
+dwc_ddrphy_apb_wr(0x41017, 0x1);
+dwc_ddrphy_apb_wr(0x41018, 0xffff);
+dwc_ddrphy_apb_wr(0x41019, 0xff03);
+dwc_ddrphy_apb_wr(0x4101a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4101b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4101c, 0xffff);
+dwc_ddrphy_apb_wr(0x4101d, 0xff03);
+dwc_ddrphy_apb_wr(0x4101e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4101f, 0x101);
+dwc_ddrphy_apb_wr(0x41020, 0x3fff);
+dwc_ddrphy_apb_wr(0x41021, 0xff00);
+dwc_ddrphy_apb_wr(0x41022, 0x3f);
+dwc_ddrphy_apb_wr(0x41023, 0x1);
+dwc_ddrphy_apb_wr(0x41024, 0x3fff);
+dwc_ddrphy_apb_wr(0x41025, 0xff00);
+dwc_ddrphy_apb_wr(0x41026, 0x3ff);
+dwc_ddrphy_apb_wr(0x41027, 0x1);
+dwc_ddrphy_apb_wr(0x41028, 0xffff);
+dwc_ddrphy_apb_wr(0x41029, 0xff03);
+dwc_ddrphy_apb_wr(0x4102a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4102b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4102c, 0xffff);
+dwc_ddrphy_apb_wr(0x4102d, 0xff03);
+dwc_ddrphy_apb_wr(0x4102e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4102f, 0xf901);
+dwc_ddrphy_apb_wr(0x41030, 0xffff);
+dwc_ddrphy_apb_wr(0x41031, 0xff03);
+dwc_ddrphy_apb_wr(0x41032, 0x3ff);
+dwc_ddrphy_apb_wr(0x41033, 0x2c1);
+dwc_ddrphy_apb_wr(0x41034, 0xffff);
+dwc_ddrphy_apb_wr(0x41035, 0xff03);
+dwc_ddrphy_apb_wr(0x41036, 0x3ff);
+dwc_ddrphy_apb_wr(0x41037, 0x5901);
+dwc_ddrphy_apb_wr(0x41038, 0x5a5);
+dwc_ddrphy_apb_wr(0x41039, 0x4000);
+dwc_ddrphy_apb_wr(0x4103a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4103b, 0x1);
+dwc_ddrphy_apb_wr(0x4103c, 0xc000);
+dwc_ddrphy_apb_wr(0x4103d, 0x3);
+dwc_ddrphy_apb_wr(0x4103e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4103f, 0x0);
+dwc_ddrphy_apb_wr(0x41040, 0xc000);
+dwc_ddrphy_apb_wr(0x41041, 0x3);
+dwc_ddrphy_apb_wr(0x41042, 0x3c0);
+dwc_ddrphy_apb_wr(0x41043, 0x2c1);
+dwc_ddrphy_apb_wr(0x41044, 0xc000);
+dwc_ddrphy_apb_wr(0x41045, 0x3);
+dwc_ddrphy_apb_wr(0x41046, 0x3c0);
+dwc_ddrphy_apb_wr(0x41047, 0xa01);
+dwc_ddrphy_apb_wr(0x41048, 0xef);
+dwc_ddrphy_apb_wr(0x41049, 0xef00);
+dwc_ddrphy_apb_wr(0x4104a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4104b, 0x1);
+dwc_ddrphy_apb_wr(0x4104c, 0xc000);
+dwc_ddrphy_apb_wr(0x4104d, 0x3);
+dwc_ddrphy_apb_wr(0x4104e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4104f, 0x0);
+dwc_ddrphy_apb_wr(0x41050, 0xc000);
+dwc_ddrphy_apb_wr(0x41051, 0x3);
+dwc_ddrphy_apb_wr(0x41052, 0x3c0);
+dwc_ddrphy_apb_wr(0x41053, 0x2c1);
+dwc_ddrphy_apb_wr(0x41054, 0xc000);
+dwc_ddrphy_apb_wr(0x41055, 0x3);
+dwc_ddrphy_apb_wr(0x41056, 0x3c0);
+dwc_ddrphy_apb_wr(0x41057, 0xff01);
+dwc_ddrphy_apb_wr(0x41058, 0xc000);
+dwc_ddrphy_apb_wr(0x41059, 0x3);
+dwc_ddrphy_apb_wr(0x4105a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4105b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4105c, 0xc000);
+dwc_ddrphy_apb_wr(0x4105d, 0x3);
+dwc_ddrphy_apb_wr(0x4105e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4105f, 0xff01);
+dwc_ddrphy_apb_wr(0x41060, 0xc000);
+dwc_ddrphy_apb_wr(0x41061, 0x3);
+dwc_ddrphy_apb_wr(0x41062, 0x3c0);
+dwc_ddrphy_apb_wr(0x41063, 0x2c1);
+dwc_ddrphy_apb_wr(0x41064, 0xc000);
+dwc_ddrphy_apb_wr(0x41065, 0x3);
+dwc_ddrphy_apb_wr(0x41066, 0x3c0);
+dwc_ddrphy_apb_wr(0x41067, 0xa01);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0
+dwc_ddrphy_apb_wr(0x41068, 0x85d5);
+dwc_ddrphy_apb_wr(0x41069, 0x63);
+dwc_ddrphy_apb_wr(0x4106a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4106b, 0x400);
+dwc_ddrphy_apb_wr(0x4106c, 0xc000);
+dwc_ddrphy_apb_wr(0x4106d, 0x3);
+dwc_ddrphy_apb_wr(0x4106e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4106f, 0x0);
+dwc_ddrphy_apb_wr(0x41070, 0xc000);
+dwc_ddrphy_apb_wr(0x41071, 0x3);
+dwc_ddrphy_apb_wr(0x41072, 0x3c0);
+dwc_ddrphy_apb_wr(0x41073, 0x2c1);
+dwc_ddrphy_apb_wr(0x41074, 0xc000);
+dwc_ddrphy_apb_wr(0x41075, 0x3);
+dwc_ddrphy_apb_wr(0x41076, 0x3c0);
+dwc_ddrphy_apb_wr(0x41077, 0x1001);
+dwc_ddrphy_apb_wr(0x41078, 0x85f5);
+dwc_ddrphy_apb_wr(0x41079, 0x63);
+dwc_ddrphy_apb_wr(0x4107a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4107b, 0x800);
+dwc_ddrphy_apb_wr(0x4107c, 0xc000);
+dwc_ddrphy_apb_wr(0x4107d, 0x3);
+dwc_ddrphy_apb_wr(0x4107e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4107f, 0x0);
+dwc_ddrphy_apb_wr(0x41080, 0xc000);
+dwc_ddrphy_apb_wr(0x41081, 0x3);
+dwc_ddrphy_apb_wr(0x41082, 0x3c0);
+dwc_ddrphy_apb_wr(0x41083, 0x2c1);
+dwc_ddrphy_apb_wr(0x41084, 0xc000);
+dwc_ddrphy_apb_wr(0x41085, 0x3);
+dwc_ddrphy_apb_wr(0x41086, 0x3c0);
+dwc_ddrphy_apb_wr(0x41087, 0x1001);
+dwc_ddrphy_apb_wr(0x41088, 0x45d5);
+dwc_ddrphy_apb_wr(0x41089, 0x63);
+dwc_ddrphy_apb_wr(0x4108a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4108b, 0x401);
+dwc_ddrphy_apb_wr(0x4108c, 0xc000);
+dwc_ddrphy_apb_wr(0x4108d, 0x3);
+dwc_ddrphy_apb_wr(0x4108e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4108f, 0x1);
+dwc_ddrphy_apb_wr(0x41090, 0xc000);
+dwc_ddrphy_apb_wr(0x41091, 0x3);
+dwc_ddrphy_apb_wr(0x41092, 0x3c0);
+dwc_ddrphy_apb_wr(0x41093, 0x2c1);
+dwc_ddrphy_apb_wr(0x41094, 0xc000);
+dwc_ddrphy_apb_wr(0x41095, 0x3);
+dwc_ddrphy_apb_wr(0x41096, 0x3c0);
+dwc_ddrphy_apb_wr(0x41097, 0x1001);
+dwc_ddrphy_apb_wr(0x41098, 0x45f5);
+dwc_ddrphy_apb_wr(0x41099, 0x63);
+dwc_ddrphy_apb_wr(0x4109a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4109b, 0x801);
+dwc_ddrphy_apb_wr(0x4109c, 0xc000);
+dwc_ddrphy_apb_wr(0x4109d, 0x3);
+dwc_ddrphy_apb_wr(0x4109e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4109f, 0x1);
+dwc_ddrphy_apb_wr(0x410a0, 0xc000);
+dwc_ddrphy_apb_wr(0x410a1, 0x3);
+dwc_ddrphy_apb_wr(0x410a2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410a3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410a4, 0xc000);
+dwc_ddrphy_apb_wr(0x410a5, 0x3);
+dwc_ddrphy_apb_wr(0x410a6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410a7, 0x1001);
+dwc_ddrphy_apb_wr(0x410a8, 0xc5d5);
+dwc_ddrphy_apb_wr(0x410a9, 0x62);
+dwc_ddrphy_apb_wr(0x410aa, 0x3c0);
+dwc_ddrphy_apb_wr(0x410ab, 0x402);
+dwc_ddrphy_apb_wr(0x410ac, 0xc000);
+dwc_ddrphy_apb_wr(0x410ad, 0x3);
+dwc_ddrphy_apb_wr(0x410ae, 0x3c0);
+dwc_ddrphy_apb_wr(0x410af, 0x2);
+dwc_ddrphy_apb_wr(0x410b0, 0xc000);
+dwc_ddrphy_apb_wr(0x410b1, 0x3);
+dwc_ddrphy_apb_wr(0x410b2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410b3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410b4, 0xc000);
+dwc_ddrphy_apb_wr(0x410b5, 0x3);
+dwc_ddrphy_apb_wr(0x410b6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410b7, 0x1001);
+dwc_ddrphy_apb_wr(0x410b8, 0xc5f5);
+dwc_ddrphy_apb_wr(0x410b9, 0x62);
+dwc_ddrphy_apb_wr(0x410ba, 0x3c0);
+dwc_ddrphy_apb_wr(0x410bb, 0x802);
+dwc_ddrphy_apb_wr(0x410bc, 0xc000);
+dwc_ddrphy_apb_wr(0x410bd, 0x3);
+dwc_ddrphy_apb_wr(0x410be, 0x3c0);
+dwc_ddrphy_apb_wr(0x410bf, 0x2);
+dwc_ddrphy_apb_wr(0x410c0, 0xc000);
+dwc_ddrphy_apb_wr(0x410c1, 0x3);
+dwc_ddrphy_apb_wr(0x410c2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410c3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410c4, 0xc000);
+dwc_ddrphy_apb_wr(0x410c5, 0x3);
+dwc_ddrphy_apb_wr(0x410c6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410c7, 0x1001);
+dwc_ddrphy_apb_wr(0x410c8, 0xc5d5);
+dwc_ddrphy_apb_wr(0x410c9, 0x61);
+dwc_ddrphy_apb_wr(0x410ca, 0x3c0);
+dwc_ddrphy_apb_wr(0x410cb, 0x403);
+dwc_ddrphy_apb_wr(0x410cc, 0xc000);
+dwc_ddrphy_apb_wr(0x410cd, 0x3);
+dwc_ddrphy_apb_wr(0x410ce, 0x3c0);
+dwc_ddrphy_apb_wr(0x410cf, 0x3);
+dwc_ddrphy_apb_wr(0x410d0, 0xc000);
+dwc_ddrphy_apb_wr(0x410d1, 0x3);
+dwc_ddrphy_apb_wr(0x410d2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410d3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410d4, 0xc000);
+dwc_ddrphy_apb_wr(0x410d5, 0x3);
+dwc_ddrphy_apb_wr(0x410d6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410d7, 0x1001);
+dwc_ddrphy_apb_wr(0x410d8, 0xc5f5);
+dwc_ddrphy_apb_wr(0x410d9, 0x61);
+dwc_ddrphy_apb_wr(0x410da, 0x3c0);
+dwc_ddrphy_apb_wr(0x410db, 0x803);
+dwc_ddrphy_apb_wr(0x410dc, 0xc000);
+dwc_ddrphy_apb_wr(0x410dd, 0x3);
+dwc_ddrphy_apb_wr(0x410de, 0x3c0);
+dwc_ddrphy_apb_wr(0x410df, 0x3);
+dwc_ddrphy_apb_wr(0x410e0, 0xc000);
+dwc_ddrphy_apb_wr(0x410e1, 0x3);
+dwc_ddrphy_apb_wr(0x410e2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410e3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410e4, 0xc000);
+dwc_ddrphy_apb_wr(0x410e5, 0x3);
+dwc_ddrphy_apb_wr(0x410e6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410e7, 0x1d01);
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0
+dwc_ddrphy_apb_wr(0x410e8, 0x213);
+dwc_ddrphy_apb_wr(0x410e9, 0x0);
+dwc_ddrphy_apb_wr(0x410ea, 0x3c0);
+dwc_ddrphy_apb_wr(0x410eb, 0x1);
+dwc_ddrphy_apb_wr(0x410ec, 0xc000);
+dwc_ddrphy_apb_wr(0x410ed, 0x3);
+dwc_ddrphy_apb_wr(0x410ee, 0x3c0);
+dwc_ddrphy_apb_wr(0x410ef, 0x0);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0
+dwc_ddrphy_apb_wr(0x410f0, 0xc000);
+dwc_ddrphy_apb_wr(0x410f1, 0x3);
+dwc_ddrphy_apb_wr(0x410f2, 0x3c0);
+dwc_ddrphy_apb_wr(0x410f3, 0x2c1);
+dwc_ddrphy_apb_wr(0x410f4, 0xc000);
+dwc_ddrphy_apb_wr(0x410f5, 0x3);
+dwc_ddrphy_apb_wr(0x410f6, 0x3c0);
+dwc_ddrphy_apb_wr(0x410f7, 0xef00);
+dwc_ddrphy_apb_wr(0x410f8, 0xc000);
+dwc_ddrphy_apb_wr(0x410f9, 0x3);
+dwc_ddrphy_apb_wr(0x410fa, 0x3c0);
+dwc_ddrphy_apb_wr(0x410fb, 0x2c1);
+dwc_ddrphy_apb_wr(0x410fc, 0xc000);
+dwc_ddrphy_apb_wr(0x410fd, 0x3);
+dwc_ddrphy_apb_wr(0x410fe, 0x3c0);
+dwc_ddrphy_apb_wr(0x410ff, 0x5900);
+dwc_ddrphy_apb_wr(0x41100, 0x217);
+dwc_ddrphy_apb_wr(0x41101, 0x1700);
+dwc_ddrphy_apb_wr(0x41102, 0x3c2);
+dwc_ddrphy_apb_wr(0x41103, 0x1);
+dwc_ddrphy_apb_wr(0x41104, 0xc000);
+dwc_ddrphy_apb_wr(0x41105, 0x3);
+dwc_ddrphy_apb_wr(0x41106, 0x3c0);
+dwc_ddrphy_apb_wr(0x41107, 0x0);
+dwc_ddrphy_apb_wr(0x41108, 0xc000);
+dwc_ddrphy_apb_wr(0x41109, 0x3);
+dwc_ddrphy_apb_wr(0x4110a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4110b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4110c, 0xc000);
+dwc_ddrphy_apb_wr(0x4110d, 0x3);
+dwc_ddrphy_apb_wr(0x4110e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4110f, 0x400);
+dwc_ddrphy_apb_wr(0x41110, 0x3fff);
+dwc_ddrphy_apb_wr(0x41111, 0xff00);
+dwc_ddrphy_apb_wr(0x41112, 0x3f);
+dwc_ddrphy_apb_wr(0x41113, 0x2e1);
+dwc_ddrphy_apb_wr(0x41114, 0x3fff);
+dwc_ddrphy_apb_wr(0x41115, 0xff00);
+dwc_ddrphy_apb_wr(0x41116, 0x3f);
+dwc_ddrphy_apb_wr(0x41117, 0xa21);
+dwc_ddrphy_apb_wr(0x41118, 0x3fff);
+dwc_ddrphy_apb_wr(0x41119, 0xff00);
+dwc_ddrphy_apb_wr(0x4111a, 0x3f);
+dwc_ddrphy_apb_wr(0x4111b, 0x21);
+dwc_ddrphy_apb_wr(0x4111c, 0xffff);
+dwc_ddrphy_apb_wr(0x4111d, 0xff03);
+dwc_ddrphy_apb_wr(0x4111e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4111f, 0x20);
+dwc_ddrphy_apb_wr(0x41120, 0xffff);
+dwc_ddrphy_apb_wr(0x41121, 0xff03);
+dwc_ddrphy_apb_wr(0x41122, 0x3ff);
+dwc_ddrphy_apb_wr(0x41123, 0x1e1);
+dwc_ddrphy_apb_wr(0x41124, 0xffff);
+dwc_ddrphy_apb_wr(0x41125, 0xff03);
+dwc_ddrphy_apb_wr(0x41126, 0x3ff);
+dwc_ddrphy_apb_wr(0x41127, 0x21);
+dwc_ddrphy_apb_wr(0x41128, 0xffff);
+dwc_ddrphy_apb_wr(0x41129, 0xff03);
+dwc_ddrphy_apb_wr(0x4112a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4112b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4112c, 0xffff);
+dwc_ddrphy_apb_wr(0x4112d, 0xff03);
+dwc_ddrphy_apb_wr(0x4112e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4112f, 0x121);
+dwc_ddrphy_apb_wr(0x41130, 0x3fff);
+dwc_ddrphy_apb_wr(0x41131, 0xff00);
+dwc_ddrphy_apb_wr(0x41132, 0x3ff);
+dwc_ddrphy_apb_wr(0x41133, 0x21);
+dwc_ddrphy_apb_wr(0x41134, 0x3fff);
+dwc_ddrphy_apb_wr(0x41135, 0xff00);
+dwc_ddrphy_apb_wr(0x41136, 0x3ff);
+dwc_ddrphy_apb_wr(0x41137, 0x21);
+dwc_ddrphy_apb_wr(0x41138, 0x3fff);
+dwc_ddrphy_apb_wr(0x41139, 0xff00);
+dwc_ddrphy_apb_wr(0x4113a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4113b, 0x21);
+dwc_ddrphy_apb_wr(0x4113c, 0xffff);
+dwc_ddrphy_apb_wr(0x4113d, 0xff03);
+dwc_ddrphy_apb_wr(0x4113e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4113f, 0x21);
+dwc_ddrphy_apb_wr(0x41140, 0xffff);
+dwc_ddrphy_apb_wr(0x41141, 0xff03);
+dwc_ddrphy_apb_wr(0x41142, 0x3ff);
+dwc_ddrphy_apb_wr(0x41143, 0x2e1);
+dwc_ddrphy_apb_wr(0x41144, 0xffff);
+dwc_ddrphy_apb_wr(0x41145, 0xff03);
+dwc_ddrphy_apb_wr(0x41146, 0x3ff);
+dwc_ddrphy_apb_wr(0x41147, 0xf921);
+dwc_ddrphy_apb_wr(0x41148, 0xffff);
+dwc_ddrphy_apb_wr(0x41149, 0xff03);
+dwc_ddrphy_apb_wr(0x4114a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4114b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4114c, 0xffff);
+dwc_ddrphy_apb_wr(0x4114d, 0xff03);
+dwc_ddrphy_apb_wr(0x4114e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4114f, 0x5921);
+dwc_ddrphy_apb_wr(0x41150, 0x5a5);
+dwc_ddrphy_apb_wr(0x41151, 0xa500);
+dwc_ddrphy_apb_wr(0x41152, 0x3c5);
+dwc_ddrphy_apb_wr(0x41153, 0x21);
+dwc_ddrphy_apb_wr(0x41154, 0xc040);
+dwc_ddrphy_apb_wr(0x41155, 0x4003);
+dwc_ddrphy_apb_wr(0x41156, 0x3c0);
+dwc_ddrphy_apb_wr(0x41157, 0x20);
+dwc_ddrphy_apb_wr(0x41158, 0xc000);
+dwc_ddrphy_apb_wr(0x41159, 0x3);
+dwc_ddrphy_apb_wr(0x4115a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4115b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4115c, 0xc000);
+dwc_ddrphy_apb_wr(0x4115d, 0x3);
+dwc_ddrphy_apb_wr(0x4115e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4115f, 0xa21);
+dwc_ddrphy_apb_wr(0x41160, 0xef);
+dwc_ddrphy_apb_wr(0x41161, 0xef00);
+dwc_ddrphy_apb_wr(0x41162, 0x3c0);
+dwc_ddrphy_apb_wr(0x41163, 0x21);
+dwc_ddrphy_apb_wr(0x41164, 0xc000);
+dwc_ddrphy_apb_wr(0x41165, 0x3);
+dwc_ddrphy_apb_wr(0x41166, 0x3c0);
+dwc_ddrphy_apb_wr(0x41167, 0x20);
+dwc_ddrphy_apb_wr(0x41168, 0xc000);
+dwc_ddrphy_apb_wr(0x41169, 0x3);
+dwc_ddrphy_apb_wr(0x4116a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4116b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4116c, 0xc000);
+dwc_ddrphy_apb_wr(0x4116d, 0x3);
+dwc_ddrphy_apb_wr(0x4116e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4116f, 0xff21);
+dwc_ddrphy_apb_wr(0x41170, 0xc000);
+dwc_ddrphy_apb_wr(0x41171, 0x3);
+dwc_ddrphy_apb_wr(0x41172, 0x3c0);
+dwc_ddrphy_apb_wr(0x41173, 0x2e1);
+dwc_ddrphy_apb_wr(0x41174, 0xc000);
+dwc_ddrphy_apb_wr(0x41175, 0x3);
+dwc_ddrphy_apb_wr(0x41176, 0x3c0);
+dwc_ddrphy_apb_wr(0x41177, 0xff21);
+dwc_ddrphy_apb_wr(0x41178, 0xc000);
+dwc_ddrphy_apb_wr(0x41179, 0x3);
+dwc_ddrphy_apb_wr(0x4117a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4117b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4117c, 0xc000);
+dwc_ddrphy_apb_wr(0x4117d, 0x3);
+dwc_ddrphy_apb_wr(0x4117e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4117f, 0xa21);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 1
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0
+dwc_ddrphy_apb_wr(0x41180, 0x85d5);
+dwc_ddrphy_apb_wr(0x41181, 0xd563);
+dwc_ddrphy_apb_wr(0x41182, 0x3c5);
+dwc_ddrphy_apb_wr(0x41183, 0x420);
+dwc_ddrphy_apb_wr(0x41184, 0xc000);
+dwc_ddrphy_apb_wr(0x41185, 0x3);
+dwc_ddrphy_apb_wr(0x41186, 0x3c0);
+dwc_ddrphy_apb_wr(0x41187, 0x20);
+dwc_ddrphy_apb_wr(0x41188, 0xc000);
+dwc_ddrphy_apb_wr(0x41189, 0x3);
+dwc_ddrphy_apb_wr(0x4118a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4118b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4118c, 0xc000);
+dwc_ddrphy_apb_wr(0x4118d, 0x3);
+dwc_ddrphy_apb_wr(0x4118e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4118f, 0x1001);
+dwc_ddrphy_apb_wr(0x41190, 0x85f5);
+dwc_ddrphy_apb_wr(0x41191, 0xf563);
+dwc_ddrphy_apb_wr(0x41192, 0x3c5);
+dwc_ddrphy_apb_wr(0x41193, 0x820);
+dwc_ddrphy_apb_wr(0x41194, 0xc000);
+dwc_ddrphy_apb_wr(0x41195, 0x3);
+dwc_ddrphy_apb_wr(0x41196, 0x3c0);
+dwc_ddrphy_apb_wr(0x41197, 0x20);
+dwc_ddrphy_apb_wr(0x41198, 0xc000);
+dwc_ddrphy_apb_wr(0x41199, 0x3);
+dwc_ddrphy_apb_wr(0x4119a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4119b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4119c, 0xc000);
+dwc_ddrphy_apb_wr(0x4119d, 0x3);
+dwc_ddrphy_apb_wr(0x4119e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4119f, 0x1001);
+dwc_ddrphy_apb_wr(0x411a0, 0x45d5);
+dwc_ddrphy_apb_wr(0x411a1, 0xd563);
+dwc_ddrphy_apb_wr(0x411a2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411a3, 0x421);
+dwc_ddrphy_apb_wr(0x411a4, 0xc000);
+dwc_ddrphy_apb_wr(0x411a5, 0x3);
+dwc_ddrphy_apb_wr(0x411a6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411a7, 0x21);
+dwc_ddrphy_apb_wr(0x411a8, 0xc000);
+dwc_ddrphy_apb_wr(0x411a9, 0x3);
+dwc_ddrphy_apb_wr(0x411aa, 0x3c0);
+dwc_ddrphy_apb_wr(0x411ab, 0x2c1);
+dwc_ddrphy_apb_wr(0x411ac, 0xc000);
+dwc_ddrphy_apb_wr(0x411ad, 0x3);
+dwc_ddrphy_apb_wr(0x411ae, 0x3c0);
+dwc_ddrphy_apb_wr(0x411af, 0x1001);
+dwc_ddrphy_apb_wr(0x411b0, 0x45f5);
+dwc_ddrphy_apb_wr(0x411b1, 0xf563);
+dwc_ddrphy_apb_wr(0x411b2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411b3, 0x821);
+dwc_ddrphy_apb_wr(0x411b4, 0xc000);
+dwc_ddrphy_apb_wr(0x411b5, 0x3);
+dwc_ddrphy_apb_wr(0x411b6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411b7, 0x21);
+dwc_ddrphy_apb_wr(0x411b8, 0xc000);
+dwc_ddrphy_apb_wr(0x411b9, 0x3);
+dwc_ddrphy_apb_wr(0x411ba, 0x3c0);
+dwc_ddrphy_apb_wr(0x411bb, 0x2c1);
+dwc_ddrphy_apb_wr(0x411bc, 0xc000);
+dwc_ddrphy_apb_wr(0x411bd, 0x3);
+dwc_ddrphy_apb_wr(0x411be, 0x3c0);
+dwc_ddrphy_apb_wr(0x411bf, 0x1001);
+dwc_ddrphy_apb_wr(0x411c0, 0xc5d5);
+dwc_ddrphy_apb_wr(0x411c1, 0xd562);
+dwc_ddrphy_apb_wr(0x411c2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411c3, 0x422);
+dwc_ddrphy_apb_wr(0x411c4, 0xc000);
+dwc_ddrphy_apb_wr(0x411c5, 0x3);
+dwc_ddrphy_apb_wr(0x411c6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411c7, 0x22);
+dwc_ddrphy_apb_wr(0x411c8, 0xc000);
+dwc_ddrphy_apb_wr(0x411c9, 0x3);
+dwc_ddrphy_apb_wr(0x411ca, 0x3c0);
+dwc_ddrphy_apb_wr(0x411cb, 0x2c1);
+dwc_ddrphy_apb_wr(0x411cc, 0xc000);
+dwc_ddrphy_apb_wr(0x411cd, 0x3);
+dwc_ddrphy_apb_wr(0x411ce, 0x3c0);
+dwc_ddrphy_apb_wr(0x411cf, 0x1001);
+dwc_ddrphy_apb_wr(0x411d0, 0xc5f5);
+dwc_ddrphy_apb_wr(0x411d1, 0xf562);
+dwc_ddrphy_apb_wr(0x411d2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411d3, 0x822);
+dwc_ddrphy_apb_wr(0x411d4, 0xc000);
+dwc_ddrphy_apb_wr(0x411d5, 0x3);
+dwc_ddrphy_apb_wr(0x411d6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411d7, 0x22);
+dwc_ddrphy_apb_wr(0x411d8, 0xc000);
+dwc_ddrphy_apb_wr(0x411d9, 0x3);
+dwc_ddrphy_apb_wr(0x411da, 0x3c0);
+dwc_ddrphy_apb_wr(0x411db, 0x2c1);
+dwc_ddrphy_apb_wr(0x411dc, 0xc000);
+dwc_ddrphy_apb_wr(0x411dd, 0x3);
+dwc_ddrphy_apb_wr(0x411de, 0x3c0);
+dwc_ddrphy_apb_wr(0x411df, 0x1001);
+dwc_ddrphy_apb_wr(0x411e0, 0xc5d5);
+dwc_ddrphy_apb_wr(0x411e1, 0xd561);
+dwc_ddrphy_apb_wr(0x411e2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411e3, 0x423);
+dwc_ddrphy_apb_wr(0x411e4, 0xc000);
+dwc_ddrphy_apb_wr(0x411e5, 0x3);
+dwc_ddrphy_apb_wr(0x411e6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411e7, 0x23);
+dwc_ddrphy_apb_wr(0x411e8, 0xc000);
+dwc_ddrphy_apb_wr(0x411e9, 0x3);
+dwc_ddrphy_apb_wr(0x411ea, 0x3c0);
+dwc_ddrphy_apb_wr(0x411eb, 0x2c1);
+dwc_ddrphy_apb_wr(0x411ec, 0xc000);
+dwc_ddrphy_apb_wr(0x411ed, 0x3);
+dwc_ddrphy_apb_wr(0x411ee, 0x3c0);
+dwc_ddrphy_apb_wr(0x411ef, 0x1001);
+dwc_ddrphy_apb_wr(0x411f0, 0xc5f5);
+dwc_ddrphy_apb_wr(0x411f1, 0xf561);
+dwc_ddrphy_apb_wr(0x411f2, 0x3c5);
+dwc_ddrphy_apb_wr(0x411f3, 0x823);
+dwc_ddrphy_apb_wr(0x411f4, 0xc000);
+dwc_ddrphy_apb_wr(0x411f5, 0x3);
+dwc_ddrphy_apb_wr(0x411f6, 0x3c0);
+dwc_ddrphy_apb_wr(0x411f7, 0x23);
+dwc_ddrphy_apb_wr(0x411f8, 0xc000);
+dwc_ddrphy_apb_wr(0x411f9, 0x3);
+dwc_ddrphy_apb_wr(0x411fa, 0x3c0);
+dwc_ddrphy_apb_wr(0x411fb, 0x2c1);
+dwc_ddrphy_apb_wr(0x411fc, 0xc000);
+dwc_ddrphy_apb_wr(0x411fd, 0x3);
+dwc_ddrphy_apb_wr(0x411fe, 0x3c0);
+dwc_ddrphy_apb_wr(0x411ff, 0x1d01);
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0
+dwc_ddrphy_apb_wr(0x41200, 0x213);
+dwc_ddrphy_apb_wr(0x41201, 0x1300);
+dwc_ddrphy_apb_wr(0x41202, 0x3c2);
+dwc_ddrphy_apb_wr(0x41203, 0x21);
+dwc_ddrphy_apb_wr(0x41204, 0xc000);
+dwc_ddrphy_apb_wr(0x41205, 0x3);
+dwc_ddrphy_apb_wr(0x41206, 0x3c0);
+dwc_ddrphy_apb_wr(0x41207, 0x20);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0
+dwc_ddrphy_apb_wr(0x41208, 0xc000);
+dwc_ddrphy_apb_wr(0x41209, 0x3);
+dwc_ddrphy_apb_wr(0x4120a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4120b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4120c, 0xc000);
+dwc_ddrphy_apb_wr(0x4120d, 0x3);
+dwc_ddrphy_apb_wr(0x4120e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4120f, 0xef20);
+dwc_ddrphy_apb_wr(0x41210, 0xc000);
+dwc_ddrphy_apb_wr(0x41211, 0x3);
+dwc_ddrphy_apb_wr(0x41212, 0x3c0);
+dwc_ddrphy_apb_wr(0x41213, 0x2e1);
+dwc_ddrphy_apb_wr(0x41214, 0xc000);
+dwc_ddrphy_apb_wr(0x41215, 0x3);
+dwc_ddrphy_apb_wr(0x41216, 0x3c0);
+dwc_ddrphy_apb_wr(0x41217, 0x5920);
+dwc_ddrphy_apb_wr(0x41218, 0x217);
+dwc_ddrphy_apb_wr(0x41219, 0x1700);
+dwc_ddrphy_apb_wr(0x4121a, 0x3c2);
+dwc_ddrphy_apb_wr(0x4121b, 0x21);
+dwc_ddrphy_apb_wr(0x4121c, 0xc000);
+dwc_ddrphy_apb_wr(0x4121d, 0x3);
+dwc_ddrphy_apb_wr(0x4121e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4121f, 0x20);
+dwc_ddrphy_apb_wr(0x41220, 0xc000);
+dwc_ddrphy_apb_wr(0x41221, 0x3);
+dwc_ddrphy_apb_wr(0x41222, 0x3c0);
+dwc_ddrphy_apb_wr(0x41223, 0x2e1);
+dwc_ddrphy_apb_wr(0x41224, 0xc000);
+dwc_ddrphy_apb_wr(0x41225, 0x3);
+dwc_ddrphy_apb_wr(0x41226, 0x3c0);
+dwc_ddrphy_apb_wr(0x41227, 0x420);
+//// [phyinit_LoadPIECodeSections] Moving start address from 41228 to 42000
+dwc_ddrphy_apb_wr(0x42000, 0x3fff);
+dwc_ddrphy_apb_wr(0x42001, 0xff00);
+dwc_ddrphy_apb_wr(0x42002, 0x3f);
+dwc_ddrphy_apb_wr(0x42003, 0x2c1);
+dwc_ddrphy_apb_wr(0x42004, 0x3fff);
+dwc_ddrphy_apb_wr(0x42005, 0xff00);
+dwc_ddrphy_apb_wr(0x42006, 0x3f);
+dwc_ddrphy_apb_wr(0x42007, 0xa01);
+dwc_ddrphy_apb_wr(0x42008, 0x3fff);
+dwc_ddrphy_apb_wr(0x42009, 0xff00);
+dwc_ddrphy_apb_wr(0x4200a, 0x3f);
+dwc_ddrphy_apb_wr(0x4200b, 0x1);
+dwc_ddrphy_apb_wr(0x4200c, 0xffff);
+dwc_ddrphy_apb_wr(0x4200d, 0xff03);
+dwc_ddrphy_apb_wr(0x4200e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4200f, 0x0);
+dwc_ddrphy_apb_wr(0x42010, 0xffff);
+dwc_ddrphy_apb_wr(0x42011, 0xff03);
+dwc_ddrphy_apb_wr(0x42012, 0x3ff);
+dwc_ddrphy_apb_wr(0x42013, 0x1c1);
+dwc_ddrphy_apb_wr(0x42014, 0xffff);
+dwc_ddrphy_apb_wr(0x42015, 0xff03);
+dwc_ddrphy_apb_wr(0x42016, 0x3ff);
+dwc_ddrphy_apb_wr(0x42017, 0x1);
+dwc_ddrphy_apb_wr(0x42018, 0xffff);
+dwc_ddrphy_apb_wr(0x42019, 0xff03);
+dwc_ddrphy_apb_wr(0x4201a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4201b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4201c, 0xffff);
+dwc_ddrphy_apb_wr(0x4201d, 0xff03);
+dwc_ddrphy_apb_wr(0x4201e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4201f, 0x101);
+dwc_ddrphy_apb_wr(0x42020, 0x3fff);
+dwc_ddrphy_apb_wr(0x42021, 0xff00);
+dwc_ddrphy_apb_wr(0x42022, 0x3f);
+dwc_ddrphy_apb_wr(0x42023, 0x1);
+dwc_ddrphy_apb_wr(0x42024, 0x3fff);
+dwc_ddrphy_apb_wr(0x42025, 0xff00);
+dwc_ddrphy_apb_wr(0x42026, 0x3ff);
+dwc_ddrphy_apb_wr(0x42027, 0x1);
+dwc_ddrphy_apb_wr(0x42028, 0xffff);
+dwc_ddrphy_apb_wr(0x42029, 0xff03);
+dwc_ddrphy_apb_wr(0x4202a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4202b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4202c, 0xffff);
+dwc_ddrphy_apb_wr(0x4202d, 0xff03);
+dwc_ddrphy_apb_wr(0x4202e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4202f, 0xf901);
+dwc_ddrphy_apb_wr(0x42030, 0xffff);
+dwc_ddrphy_apb_wr(0x42031, 0xff03);
+dwc_ddrphy_apb_wr(0x42032, 0x3ff);
+dwc_ddrphy_apb_wr(0x42033, 0x2c1);
+dwc_ddrphy_apb_wr(0x42034, 0xffff);
+dwc_ddrphy_apb_wr(0x42035, 0xff03);
+dwc_ddrphy_apb_wr(0x42036, 0x3ff);
+dwc_ddrphy_apb_wr(0x42037, 0x5901);
+dwc_ddrphy_apb_wr(0x42038, 0x5a5);
+dwc_ddrphy_apb_wr(0x42039, 0x4000);
+dwc_ddrphy_apb_wr(0x4203a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4203b, 0x1);
+dwc_ddrphy_apb_wr(0x4203c, 0xc000);
+dwc_ddrphy_apb_wr(0x4203d, 0x3);
+dwc_ddrphy_apb_wr(0x4203e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4203f, 0x0);
+dwc_ddrphy_apb_wr(0x42040, 0xc000);
+dwc_ddrphy_apb_wr(0x42041, 0x3);
+dwc_ddrphy_apb_wr(0x42042, 0x3c0);
+dwc_ddrphy_apb_wr(0x42043, 0x2c1);
+dwc_ddrphy_apb_wr(0x42044, 0xc000);
+dwc_ddrphy_apb_wr(0x42045, 0x3);
+dwc_ddrphy_apb_wr(0x42046, 0x3c0);
+dwc_ddrphy_apb_wr(0x42047, 0xa01);
+dwc_ddrphy_apb_wr(0x42048, 0xef);
+dwc_ddrphy_apb_wr(0x42049, 0xef00);
+dwc_ddrphy_apb_wr(0x4204a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4204b, 0x1);
+dwc_ddrphy_apb_wr(0x4204c, 0xc000);
+dwc_ddrphy_apb_wr(0x4204d, 0x3);
+dwc_ddrphy_apb_wr(0x4204e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4204f, 0x0);
+dwc_ddrphy_apb_wr(0x42050, 0xc000);
+dwc_ddrphy_apb_wr(0x42051, 0x3);
+dwc_ddrphy_apb_wr(0x42052, 0x3c0);
+dwc_ddrphy_apb_wr(0x42053, 0x2c1);
+dwc_ddrphy_apb_wr(0x42054, 0xc000);
+dwc_ddrphy_apb_wr(0x42055, 0x3);
+dwc_ddrphy_apb_wr(0x42056, 0x3c0);
+dwc_ddrphy_apb_wr(0x42057, 0xff01);
+dwc_ddrphy_apb_wr(0x42058, 0xc000);
+dwc_ddrphy_apb_wr(0x42059, 0x3);
+dwc_ddrphy_apb_wr(0x4205a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4205b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4205c, 0xc000);
+dwc_ddrphy_apb_wr(0x4205d, 0x3);
+dwc_ddrphy_apb_wr(0x4205e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4205f, 0xff01);
+dwc_ddrphy_apb_wr(0x42060, 0xc000);
+dwc_ddrphy_apb_wr(0x42061, 0x3);
+dwc_ddrphy_apb_wr(0x42062, 0x3c0);
+dwc_ddrphy_apb_wr(0x42063, 0x2c1);
+dwc_ddrphy_apb_wr(0x42064, 0xc000);
+dwc_ddrphy_apb_wr(0x42065, 0x3);
+dwc_ddrphy_apb_wr(0x42066, 0x3c0);
+dwc_ddrphy_apb_wr(0x42067, 0xa01);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0
+dwc_ddrphy_apb_wr(0x42068, 0x85d5);
+dwc_ddrphy_apb_wr(0x42069, 0x63);
+dwc_ddrphy_apb_wr(0x4206a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4206b, 0x400);
+dwc_ddrphy_apb_wr(0x4206c, 0xc000);
+dwc_ddrphy_apb_wr(0x4206d, 0x3);
+dwc_ddrphy_apb_wr(0x4206e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4206f, 0x0);
+dwc_ddrphy_apb_wr(0x42070, 0xc000);
+dwc_ddrphy_apb_wr(0x42071, 0x3);
+dwc_ddrphy_apb_wr(0x42072, 0x3c0);
+dwc_ddrphy_apb_wr(0x42073, 0x2c1);
+dwc_ddrphy_apb_wr(0x42074, 0xc000);
+dwc_ddrphy_apb_wr(0x42075, 0x3);
+dwc_ddrphy_apb_wr(0x42076, 0x3c0);
+dwc_ddrphy_apb_wr(0x42077, 0x1001);
+dwc_ddrphy_apb_wr(0x42078, 0x85f5);
+dwc_ddrphy_apb_wr(0x42079, 0x63);
+dwc_ddrphy_apb_wr(0x4207a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4207b, 0x800);
+dwc_ddrphy_apb_wr(0x4207c, 0xc000);
+dwc_ddrphy_apb_wr(0x4207d, 0x3);
+dwc_ddrphy_apb_wr(0x4207e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4207f, 0x0);
+dwc_ddrphy_apb_wr(0x42080, 0xc000);
+dwc_ddrphy_apb_wr(0x42081, 0x3);
+dwc_ddrphy_apb_wr(0x42082, 0x3c0);
+dwc_ddrphy_apb_wr(0x42083, 0x2c1);
+dwc_ddrphy_apb_wr(0x42084, 0xc000);
+dwc_ddrphy_apb_wr(0x42085, 0x3);
+dwc_ddrphy_apb_wr(0x42086, 0x3c0);
+dwc_ddrphy_apb_wr(0x42087, 0x1001);
+dwc_ddrphy_apb_wr(0x42088, 0x45d5);
+dwc_ddrphy_apb_wr(0x42089, 0x63);
+dwc_ddrphy_apb_wr(0x4208a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4208b, 0x401);
+dwc_ddrphy_apb_wr(0x4208c, 0xc000);
+dwc_ddrphy_apb_wr(0x4208d, 0x3);
+dwc_ddrphy_apb_wr(0x4208e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4208f, 0x1);
+dwc_ddrphy_apb_wr(0x42090, 0xc000);
+dwc_ddrphy_apb_wr(0x42091, 0x3);
+dwc_ddrphy_apb_wr(0x42092, 0x3c0);
+dwc_ddrphy_apb_wr(0x42093, 0x2c1);
+dwc_ddrphy_apb_wr(0x42094, 0xc000);
+dwc_ddrphy_apb_wr(0x42095, 0x3);
+dwc_ddrphy_apb_wr(0x42096, 0x3c0);
+dwc_ddrphy_apb_wr(0x42097, 0x1001);
+dwc_ddrphy_apb_wr(0x42098, 0x45f5);
+dwc_ddrphy_apb_wr(0x42099, 0x63);
+dwc_ddrphy_apb_wr(0x4209a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4209b, 0x801);
+dwc_ddrphy_apb_wr(0x4209c, 0xc000);
+dwc_ddrphy_apb_wr(0x4209d, 0x3);
+dwc_ddrphy_apb_wr(0x4209e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4209f, 0x1);
+dwc_ddrphy_apb_wr(0x420a0, 0xc000);
+dwc_ddrphy_apb_wr(0x420a1, 0x3);
+dwc_ddrphy_apb_wr(0x420a2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420a3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420a4, 0xc000);
+dwc_ddrphy_apb_wr(0x420a5, 0x3);
+dwc_ddrphy_apb_wr(0x420a6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420a7, 0x1001);
+dwc_ddrphy_apb_wr(0x420a8, 0xc5d5);
+dwc_ddrphy_apb_wr(0x420a9, 0x62);
+dwc_ddrphy_apb_wr(0x420aa, 0x3c0);
+dwc_ddrphy_apb_wr(0x420ab, 0x402);
+dwc_ddrphy_apb_wr(0x420ac, 0xc000);
+dwc_ddrphy_apb_wr(0x420ad, 0x3);
+dwc_ddrphy_apb_wr(0x420ae, 0x3c0);
+dwc_ddrphy_apb_wr(0x420af, 0x2);
+dwc_ddrphy_apb_wr(0x420b0, 0xc000);
+dwc_ddrphy_apb_wr(0x420b1, 0x3);
+dwc_ddrphy_apb_wr(0x420b2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420b3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420b4, 0xc000);
+dwc_ddrphy_apb_wr(0x420b5, 0x3);
+dwc_ddrphy_apb_wr(0x420b6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420b7, 0x1001);
+dwc_ddrphy_apb_wr(0x420b8, 0xc5f5);
+dwc_ddrphy_apb_wr(0x420b9, 0x62);
+dwc_ddrphy_apb_wr(0x420ba, 0x3c0);
+dwc_ddrphy_apb_wr(0x420bb, 0x802);
+dwc_ddrphy_apb_wr(0x420bc, 0xc000);
+dwc_ddrphy_apb_wr(0x420bd, 0x3);
+dwc_ddrphy_apb_wr(0x420be, 0x3c0);
+dwc_ddrphy_apb_wr(0x420bf, 0x2);
+dwc_ddrphy_apb_wr(0x420c0, 0xc000);
+dwc_ddrphy_apb_wr(0x420c1, 0x3);
+dwc_ddrphy_apb_wr(0x420c2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420c3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420c4, 0xc000);
+dwc_ddrphy_apb_wr(0x420c5, 0x3);
+dwc_ddrphy_apb_wr(0x420c6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420c7, 0x1001);
+dwc_ddrphy_apb_wr(0x420c8, 0xc5d5);
+dwc_ddrphy_apb_wr(0x420c9, 0x61);
+dwc_ddrphy_apb_wr(0x420ca, 0x3c0);
+dwc_ddrphy_apb_wr(0x420cb, 0x403);
+dwc_ddrphy_apb_wr(0x420cc, 0xc000);
+dwc_ddrphy_apb_wr(0x420cd, 0x3);
+dwc_ddrphy_apb_wr(0x420ce, 0x3c0);
+dwc_ddrphy_apb_wr(0x420cf, 0x3);
+dwc_ddrphy_apb_wr(0x420d0, 0xc000);
+dwc_ddrphy_apb_wr(0x420d1, 0x3);
+dwc_ddrphy_apb_wr(0x420d2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420d3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420d4, 0xc000);
+dwc_ddrphy_apb_wr(0x420d5, 0x3);
+dwc_ddrphy_apb_wr(0x420d6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420d7, 0x1001);
+dwc_ddrphy_apb_wr(0x420d8, 0xc5f5);
+dwc_ddrphy_apb_wr(0x420d9, 0x61);
+dwc_ddrphy_apb_wr(0x420da, 0x3c0);
+dwc_ddrphy_apb_wr(0x420db, 0x803);
+dwc_ddrphy_apb_wr(0x420dc, 0xc000);
+dwc_ddrphy_apb_wr(0x420dd, 0x3);
+dwc_ddrphy_apb_wr(0x420de, 0x3c0);
+dwc_ddrphy_apb_wr(0x420df, 0x3);
+dwc_ddrphy_apb_wr(0x420e0, 0xc000);
+dwc_ddrphy_apb_wr(0x420e1, 0x3);
+dwc_ddrphy_apb_wr(0x420e2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420e3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420e4, 0xc000);
+dwc_ddrphy_apb_wr(0x420e5, 0x3);
+dwc_ddrphy_apb_wr(0x420e6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420e7, 0x1d01);
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0
+dwc_ddrphy_apb_wr(0x420e8, 0x213);
+dwc_ddrphy_apb_wr(0x420e9, 0x0);
+dwc_ddrphy_apb_wr(0x420ea, 0x3c0);
+dwc_ddrphy_apb_wr(0x420eb, 0x1);
+dwc_ddrphy_apb_wr(0x420ec, 0xc000);
+dwc_ddrphy_apb_wr(0x420ed, 0x3);
+dwc_ddrphy_apb_wr(0x420ee, 0x3c0);
+dwc_ddrphy_apb_wr(0x420ef, 0x0);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0
+dwc_ddrphy_apb_wr(0x420f0, 0xc000);
+dwc_ddrphy_apb_wr(0x420f1, 0x3);
+dwc_ddrphy_apb_wr(0x420f2, 0x3c0);
+dwc_ddrphy_apb_wr(0x420f3, 0x2c1);
+dwc_ddrphy_apb_wr(0x420f4, 0xc000);
+dwc_ddrphy_apb_wr(0x420f5, 0x3);
+dwc_ddrphy_apb_wr(0x420f6, 0x3c0);
+dwc_ddrphy_apb_wr(0x420f7, 0xef00);
+dwc_ddrphy_apb_wr(0x420f8, 0xc000);
+dwc_ddrphy_apb_wr(0x420f9, 0x3);
+dwc_ddrphy_apb_wr(0x420fa, 0x3c0);
+dwc_ddrphy_apb_wr(0x420fb, 0x2c1);
+dwc_ddrphy_apb_wr(0x420fc, 0xc000);
+dwc_ddrphy_apb_wr(0x420fd, 0x3);
+dwc_ddrphy_apb_wr(0x420fe, 0x3c0);
+dwc_ddrphy_apb_wr(0x420ff, 0x5900);
+dwc_ddrphy_apb_wr(0x42100, 0x217);
+dwc_ddrphy_apb_wr(0x42101, 0x1700);
+dwc_ddrphy_apb_wr(0x42102, 0x3c2);
+dwc_ddrphy_apb_wr(0x42103, 0x1);
+dwc_ddrphy_apb_wr(0x42104, 0xc000);
+dwc_ddrphy_apb_wr(0x42105, 0x3);
+dwc_ddrphy_apb_wr(0x42106, 0x3c0);
+dwc_ddrphy_apb_wr(0x42107, 0x0);
+dwc_ddrphy_apb_wr(0x42108, 0xc000);
+dwc_ddrphy_apb_wr(0x42109, 0x3);
+dwc_ddrphy_apb_wr(0x4210a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4210b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4210c, 0xc000);
+dwc_ddrphy_apb_wr(0x4210d, 0x3);
+dwc_ddrphy_apb_wr(0x4210e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4210f, 0x400);
+dwc_ddrphy_apb_wr(0x42110, 0x3fff);
+dwc_ddrphy_apb_wr(0x42111, 0xff00);
+dwc_ddrphy_apb_wr(0x42112, 0x3f);
+dwc_ddrphy_apb_wr(0x42113, 0x2e1);
+dwc_ddrphy_apb_wr(0x42114, 0x3fff);
+dwc_ddrphy_apb_wr(0x42115, 0xff00);
+dwc_ddrphy_apb_wr(0x42116, 0x3f);
+dwc_ddrphy_apb_wr(0x42117, 0xa21);
+dwc_ddrphy_apb_wr(0x42118, 0x3fff);
+dwc_ddrphy_apb_wr(0x42119, 0xff00);
+dwc_ddrphy_apb_wr(0x4211a, 0x3f);
+dwc_ddrphy_apb_wr(0x4211b, 0x21);
+dwc_ddrphy_apb_wr(0x4211c, 0xffff);
+dwc_ddrphy_apb_wr(0x4211d, 0xff03);
+dwc_ddrphy_apb_wr(0x4211e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4211f, 0x20);
+dwc_ddrphy_apb_wr(0x42120, 0xffff);
+dwc_ddrphy_apb_wr(0x42121, 0xff03);
+dwc_ddrphy_apb_wr(0x42122, 0x3ff);
+dwc_ddrphy_apb_wr(0x42123, 0x1e1);
+dwc_ddrphy_apb_wr(0x42124, 0xffff);
+dwc_ddrphy_apb_wr(0x42125, 0xff03);
+dwc_ddrphy_apb_wr(0x42126, 0x3ff);
+dwc_ddrphy_apb_wr(0x42127, 0x21);
+dwc_ddrphy_apb_wr(0x42128, 0xffff);
+dwc_ddrphy_apb_wr(0x42129, 0xff03);
+dwc_ddrphy_apb_wr(0x4212a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4212b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4212c, 0xffff);
+dwc_ddrphy_apb_wr(0x4212d, 0xff03);
+dwc_ddrphy_apb_wr(0x4212e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4212f, 0x121);
+dwc_ddrphy_apb_wr(0x42130, 0x3fff);
+dwc_ddrphy_apb_wr(0x42131, 0xff00);
+dwc_ddrphy_apb_wr(0x42132, 0x3ff);
+dwc_ddrphy_apb_wr(0x42133, 0x21);
+dwc_ddrphy_apb_wr(0x42134, 0x3fff);
+dwc_ddrphy_apb_wr(0x42135, 0xff00);
+dwc_ddrphy_apb_wr(0x42136, 0x3ff);
+dwc_ddrphy_apb_wr(0x42137, 0x21);
+dwc_ddrphy_apb_wr(0x42138, 0x3fff);
+dwc_ddrphy_apb_wr(0x42139, 0xff00);
+dwc_ddrphy_apb_wr(0x4213a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4213b, 0x21);
+dwc_ddrphy_apb_wr(0x4213c, 0xffff);
+dwc_ddrphy_apb_wr(0x4213d, 0xff03);
+dwc_ddrphy_apb_wr(0x4213e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4213f, 0x21);
+dwc_ddrphy_apb_wr(0x42140, 0xffff);
+dwc_ddrphy_apb_wr(0x42141, 0xff03);
+dwc_ddrphy_apb_wr(0x42142, 0x3ff);
+dwc_ddrphy_apb_wr(0x42143, 0x2e1);
+dwc_ddrphy_apb_wr(0x42144, 0xffff);
+dwc_ddrphy_apb_wr(0x42145, 0xff03);
+dwc_ddrphy_apb_wr(0x42146, 0x3ff);
+dwc_ddrphy_apb_wr(0x42147, 0xf921);
+dwc_ddrphy_apb_wr(0x42148, 0xffff);
+dwc_ddrphy_apb_wr(0x42149, 0xff03);
+dwc_ddrphy_apb_wr(0x4214a, 0x3ff);
+dwc_ddrphy_apb_wr(0x4214b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4214c, 0xffff);
+dwc_ddrphy_apb_wr(0x4214d, 0xff03);
+dwc_ddrphy_apb_wr(0x4214e, 0x3ff);
+dwc_ddrphy_apb_wr(0x4214f, 0x5921);
+dwc_ddrphy_apb_wr(0x42150, 0x5a5);
+dwc_ddrphy_apb_wr(0x42151, 0xa500);
+dwc_ddrphy_apb_wr(0x42152, 0x3c5);
+dwc_ddrphy_apb_wr(0x42153, 0x21);
+dwc_ddrphy_apb_wr(0x42154, 0xc040);
+dwc_ddrphy_apb_wr(0x42155, 0x4003);
+dwc_ddrphy_apb_wr(0x42156, 0x3c0);
+dwc_ddrphy_apb_wr(0x42157, 0x20);
+dwc_ddrphy_apb_wr(0x42158, 0xc000);
+dwc_ddrphy_apb_wr(0x42159, 0x3);
+dwc_ddrphy_apb_wr(0x4215a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4215b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4215c, 0xc000);
+dwc_ddrphy_apb_wr(0x4215d, 0x3);
+dwc_ddrphy_apb_wr(0x4215e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4215f, 0xa21);
+dwc_ddrphy_apb_wr(0x42160, 0xef);
+dwc_ddrphy_apb_wr(0x42161, 0xef00);
+dwc_ddrphy_apb_wr(0x42162, 0x3c0);
+dwc_ddrphy_apb_wr(0x42163, 0x21);
+dwc_ddrphy_apb_wr(0x42164, 0xc000);
+dwc_ddrphy_apb_wr(0x42165, 0x3);
+dwc_ddrphy_apb_wr(0x42166, 0x3c0);
+dwc_ddrphy_apb_wr(0x42167, 0x20);
+dwc_ddrphy_apb_wr(0x42168, 0xc000);
+dwc_ddrphy_apb_wr(0x42169, 0x3);
+dwc_ddrphy_apb_wr(0x4216a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4216b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4216c, 0xc000);
+dwc_ddrphy_apb_wr(0x4216d, 0x3);
+dwc_ddrphy_apb_wr(0x4216e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4216f, 0xff21);
+dwc_ddrphy_apb_wr(0x42170, 0xc000);
+dwc_ddrphy_apb_wr(0x42171, 0x3);
+dwc_ddrphy_apb_wr(0x42172, 0x3c0);
+dwc_ddrphy_apb_wr(0x42173, 0x2e1);
+dwc_ddrphy_apb_wr(0x42174, 0xc000);
+dwc_ddrphy_apb_wr(0x42175, 0x3);
+dwc_ddrphy_apb_wr(0x42176, 0x3c0);
+dwc_ddrphy_apb_wr(0x42177, 0xff21);
+dwc_ddrphy_apb_wr(0x42178, 0xc000);
+dwc_ddrphy_apb_wr(0x42179, 0x3);
+dwc_ddrphy_apb_wr(0x4217a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4217b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4217c, 0xc000);
+dwc_ddrphy_apb_wr(0x4217d, 0x3);
+dwc_ddrphy_apb_wr(0x4217e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4217f, 0xa21);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 200000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 400000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 1000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 2000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 4000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 8000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80000000, type = 2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 10, type = 0
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 4, type = 0
+dwc_ddrphy_apb_wr(0x42180, 0x85d5);
+dwc_ddrphy_apb_wr(0x42181, 0xd563);
+dwc_ddrphy_apb_wr(0x42182, 0x3c5);
+dwc_ddrphy_apb_wr(0x42183, 0x420);
+dwc_ddrphy_apb_wr(0x42184, 0xc000);
+dwc_ddrphy_apb_wr(0x42185, 0x3);
+dwc_ddrphy_apb_wr(0x42186, 0x3c0);
+dwc_ddrphy_apb_wr(0x42187, 0x20);
+dwc_ddrphy_apb_wr(0x42188, 0xc000);
+dwc_ddrphy_apb_wr(0x42189, 0x3);
+dwc_ddrphy_apb_wr(0x4218a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4218b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4218c, 0xc000);
+dwc_ddrphy_apb_wr(0x4218d, 0x3);
+dwc_ddrphy_apb_wr(0x4218e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4218f, 0x1001);
+dwc_ddrphy_apb_wr(0x42190, 0x85f5);
+dwc_ddrphy_apb_wr(0x42191, 0xf563);
+dwc_ddrphy_apb_wr(0x42192, 0x3c5);
+dwc_ddrphy_apb_wr(0x42193, 0x820);
+dwc_ddrphy_apb_wr(0x42194, 0xc000);
+dwc_ddrphy_apb_wr(0x42195, 0x3);
+dwc_ddrphy_apb_wr(0x42196, 0x3c0);
+dwc_ddrphy_apb_wr(0x42197, 0x20);
+dwc_ddrphy_apb_wr(0x42198, 0xc000);
+dwc_ddrphy_apb_wr(0x42199, 0x3);
+dwc_ddrphy_apb_wr(0x4219a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4219b, 0x2c1);
+dwc_ddrphy_apb_wr(0x4219c, 0xc000);
+dwc_ddrphy_apb_wr(0x4219d, 0x3);
+dwc_ddrphy_apb_wr(0x4219e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4219f, 0x1001);
+dwc_ddrphy_apb_wr(0x421a0, 0x45d5);
+dwc_ddrphy_apb_wr(0x421a1, 0xd563);
+dwc_ddrphy_apb_wr(0x421a2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421a3, 0x421);
+dwc_ddrphy_apb_wr(0x421a4, 0xc000);
+dwc_ddrphy_apb_wr(0x421a5, 0x3);
+dwc_ddrphy_apb_wr(0x421a6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421a7, 0x21);
+dwc_ddrphy_apb_wr(0x421a8, 0xc000);
+dwc_ddrphy_apb_wr(0x421a9, 0x3);
+dwc_ddrphy_apb_wr(0x421aa, 0x3c0);
+dwc_ddrphy_apb_wr(0x421ab, 0x2c1);
+dwc_ddrphy_apb_wr(0x421ac, 0xc000);
+dwc_ddrphy_apb_wr(0x421ad, 0x3);
+dwc_ddrphy_apb_wr(0x421ae, 0x3c0);
+dwc_ddrphy_apb_wr(0x421af, 0x1001);
+dwc_ddrphy_apb_wr(0x421b0, 0x45f5);
+dwc_ddrphy_apb_wr(0x421b1, 0xf563);
+dwc_ddrphy_apb_wr(0x421b2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421b3, 0x821);
+dwc_ddrphy_apb_wr(0x421b4, 0xc000);
+dwc_ddrphy_apb_wr(0x421b5, 0x3);
+dwc_ddrphy_apb_wr(0x421b6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421b7, 0x21);
+dwc_ddrphy_apb_wr(0x421b8, 0xc000);
+dwc_ddrphy_apb_wr(0x421b9, 0x3);
+dwc_ddrphy_apb_wr(0x421ba, 0x3c0);
+dwc_ddrphy_apb_wr(0x421bb, 0x2c1);
+dwc_ddrphy_apb_wr(0x421bc, 0xc000);
+dwc_ddrphy_apb_wr(0x421bd, 0x3);
+dwc_ddrphy_apb_wr(0x421be, 0x3c0);
+dwc_ddrphy_apb_wr(0x421bf, 0x1001);
+dwc_ddrphy_apb_wr(0x421c0, 0xc5d5);
+dwc_ddrphy_apb_wr(0x421c1, 0xd562);
+dwc_ddrphy_apb_wr(0x421c2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421c3, 0x422);
+dwc_ddrphy_apb_wr(0x421c4, 0xc000);
+dwc_ddrphy_apb_wr(0x421c5, 0x3);
+dwc_ddrphy_apb_wr(0x421c6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421c7, 0x22);
+dwc_ddrphy_apb_wr(0x421c8, 0xc000);
+dwc_ddrphy_apb_wr(0x421c9, 0x3);
+dwc_ddrphy_apb_wr(0x421ca, 0x3c0);
+dwc_ddrphy_apb_wr(0x421cb, 0x2c1);
+dwc_ddrphy_apb_wr(0x421cc, 0xc000);
+dwc_ddrphy_apb_wr(0x421cd, 0x3);
+dwc_ddrphy_apb_wr(0x421ce, 0x3c0);
+dwc_ddrphy_apb_wr(0x421cf, 0x1001);
+dwc_ddrphy_apb_wr(0x421d0, 0xc5f5);
+dwc_ddrphy_apb_wr(0x421d1, 0xf562);
+dwc_ddrphy_apb_wr(0x421d2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421d3, 0x822);
+dwc_ddrphy_apb_wr(0x421d4, 0xc000);
+dwc_ddrphy_apb_wr(0x421d5, 0x3);
+dwc_ddrphy_apb_wr(0x421d6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421d7, 0x22);
+dwc_ddrphy_apb_wr(0x421d8, 0xc000);
+dwc_ddrphy_apb_wr(0x421d9, 0x3);
+dwc_ddrphy_apb_wr(0x421da, 0x3c0);
+dwc_ddrphy_apb_wr(0x421db, 0x2c1);
+dwc_ddrphy_apb_wr(0x421dc, 0xc000);
+dwc_ddrphy_apb_wr(0x421dd, 0x3);
+dwc_ddrphy_apb_wr(0x421de, 0x3c0);
+dwc_ddrphy_apb_wr(0x421df, 0x1001);
+dwc_ddrphy_apb_wr(0x421e0, 0xc5d5);
+dwc_ddrphy_apb_wr(0x421e1, 0xd561);
+dwc_ddrphy_apb_wr(0x421e2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421e3, 0x423);
+dwc_ddrphy_apb_wr(0x421e4, 0xc000);
+dwc_ddrphy_apb_wr(0x421e5, 0x3);
+dwc_ddrphy_apb_wr(0x421e6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421e7, 0x23);
+dwc_ddrphy_apb_wr(0x421e8, 0xc000);
+dwc_ddrphy_apb_wr(0x421e9, 0x3);
+dwc_ddrphy_apb_wr(0x421ea, 0x3c0);
+dwc_ddrphy_apb_wr(0x421eb, 0x2c1);
+dwc_ddrphy_apb_wr(0x421ec, 0xc000);
+dwc_ddrphy_apb_wr(0x421ed, 0x3);
+dwc_ddrphy_apb_wr(0x421ee, 0x3c0);
+dwc_ddrphy_apb_wr(0x421ef, 0x1001);
+dwc_ddrphy_apb_wr(0x421f0, 0xc5f5);
+dwc_ddrphy_apb_wr(0x421f1, 0xf561);
+dwc_ddrphy_apb_wr(0x421f2, 0x3c5);
+dwc_ddrphy_apb_wr(0x421f3, 0x823);
+dwc_ddrphy_apb_wr(0x421f4, 0xc000);
+dwc_ddrphy_apb_wr(0x421f5, 0x3);
+dwc_ddrphy_apb_wr(0x421f6, 0x3c0);
+dwc_ddrphy_apb_wr(0x421f7, 0x23);
+dwc_ddrphy_apb_wr(0x421f8, 0xc000);
+dwc_ddrphy_apb_wr(0x421f9, 0x3);
+dwc_ddrphy_apb_wr(0x421fa, 0x3c0);
+dwc_ddrphy_apb_wr(0x421fb, 0x2c1);
+dwc_ddrphy_apb_wr(0x421fc, 0xc000);
+dwc_ddrphy_apb_wr(0x421fd, 0x3);
+dwc_ddrphy_apb_wr(0x421fe, 0x3c0);
+dwc_ddrphy_apb_wr(0x421ff, 0x1d01);
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0
+dwc_ddrphy_apb_wr(0x42200, 0x213);
+dwc_ddrphy_apb_wr(0x42201, 0x1300);
+dwc_ddrphy_apb_wr(0x42202, 0x3c2);
+dwc_ddrphy_apb_wr(0x42203, 0x21);
+dwc_ddrphy_apb_wr(0x42204, 0xc000);
+dwc_ddrphy_apb_wr(0x42205, 0x3);
+dwc_ddrphy_apb_wr(0x42206, 0x3c0);
+dwc_ddrphy_apb_wr(0x42207, 0x20);
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0
+dwc_ddrphy_apb_wr(0x42208, 0xc000);
+dwc_ddrphy_apb_wr(0x42209, 0x3);
+dwc_ddrphy_apb_wr(0x4220a, 0x3c0);
+dwc_ddrphy_apb_wr(0x4220b, 0x2e1);
+dwc_ddrphy_apb_wr(0x4220c, 0xc000);
+dwc_ddrphy_apb_wr(0x4220d, 0x3);
+dwc_ddrphy_apb_wr(0x4220e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4220f, 0xef20);
+dwc_ddrphy_apb_wr(0x42210, 0xc000);
+dwc_ddrphy_apb_wr(0x42211, 0x3);
+dwc_ddrphy_apb_wr(0x42212, 0x3c0);
+dwc_ddrphy_apb_wr(0x42213, 0x2e1);
+dwc_ddrphy_apb_wr(0x42214, 0xc000);
+dwc_ddrphy_apb_wr(0x42215, 0x3);
+dwc_ddrphy_apb_wr(0x42216, 0x3c0);
+dwc_ddrphy_apb_wr(0x42217, 0x5920);
+dwc_ddrphy_apb_wr(0x42218, 0x217);
+dwc_ddrphy_apb_wr(0x42219, 0x1700);
+dwc_ddrphy_apb_wr(0x4221a, 0x3c2);
+dwc_ddrphy_apb_wr(0x4221b, 0x21);
+dwc_ddrphy_apb_wr(0x4221c, 0xc000);
+dwc_ddrphy_apb_wr(0x4221d, 0x3);
+dwc_ddrphy_apb_wr(0x4221e, 0x3c0);
+dwc_ddrphy_apb_wr(0x4221f, 0x20);
+dwc_ddrphy_apb_wr(0x42220, 0xc000);
+dwc_ddrphy_apb_wr(0x42221, 0x3);
+dwc_ddrphy_apb_wr(0x42222, 0x3c0);
+dwc_ddrphy_apb_wr(0x42223, 0x2e1);
+dwc_ddrphy_apb_wr(0x42224, 0xc000);
+dwc_ddrphy_apb_wr(0x42225, 0x3);
+dwc_ddrphy_apb_wr(0x42226, 0x3c0);
+dwc_ddrphy_apb_wr(0x42227, 0x420);
+//// [phyinit_LoadPIECodeSections] Moving start address from 42228 to 90029
+dwc_ddrphy_apb_wr(0x90029, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x9002a, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x9002b, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x9002c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x9002d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x9002e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b1s2
+dwc_ddrphy_apb_wr(0x9002f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s0
+dwc_ddrphy_apb_wr(0x90030, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s1
+dwc_ddrphy_apb_wr(0x90031, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b2s2
+dwc_ddrphy_apb_wr(0x90032, 0xb); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s0
+dwc_ddrphy_apb_wr(0x90033, 0x480); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s1
+dwc_ddrphy_apb_wr(0x90034, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b3s2
+dwc_ddrphy_apb_wr(0x90035, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s0
+dwc_ddrphy_apb_wr(0x90036, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s1
+dwc_ddrphy_apb_wr(0x90037, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b4s2
+dwc_ddrphy_apb_wr(0x90038, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s0
+dwc_ddrphy_apb_wr(0x90039, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s1
+dwc_ddrphy_apb_wr(0x9003a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b5s2
+dwc_ddrphy_apb_wr(0x9003b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s0
+dwc_ddrphy_apb_wr(0x9003c, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s1
+dwc_ddrphy_apb_wr(0x9003d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b6s2
+dwc_ddrphy_apb_wr(0x9003e, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s0
+dwc_ddrphy_apb_wr(0x9003f, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s1
+dwc_ddrphy_apb_wr(0x90040, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b7s2
+dwc_ddrphy_apb_wr(0x90041, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s0
+dwc_ddrphy_apb_wr(0x90042, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s1
+dwc_ddrphy_apb_wr(0x90043, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b8s2
+dwc_ddrphy_apb_wr(0x90044, 0x107); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s0
+dwc_ddrphy_apb_wr(0x90045, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s1
+dwc_ddrphy_apb_wr(0x90046, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b9s2
+dwc_ddrphy_apb_wr(0x90047, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s0
+dwc_ddrphy_apb_wr(0x90048, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s1
+dwc_ddrphy_apb_wr(0x90049, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b10s2
+dwc_ddrphy_apb_wr(0x9004a, 0x147); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s0
+dwc_ddrphy_apb_wr(0x9004b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s1
+dwc_ddrphy_apb_wr(0x9004c, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b11s2
+dwc_ddrphy_apb_wr(0x9004d, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s0
+dwc_ddrphy_apb_wr(0x9004e, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s1
+dwc_ddrphy_apb_wr(0x9004f, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b12s2
+dwc_ddrphy_apb_wr(0x90050, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s0
+dwc_ddrphy_apb_wr(0x90051, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s1
+dwc_ddrphy_apb_wr(0x90052, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b13s2
+dwc_ddrphy_apb_wr(0x90053, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s0
+dwc_ddrphy_apb_wr(0x90054, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s1
+dwc_ddrphy_apb_wr(0x90055, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b14s2
+dwc_ddrphy_apb_wr(0x90056, 0x4f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s0
+dwc_ddrphy_apb_wr(0x90057, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s1
+dwc_ddrphy_apb_wr(0x90058, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b15s2
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 800, type = 0
+dwc_ddrphy_apb_wr(0x90059, 0x100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s0
+dwc_ddrphy_apb_wr(0x9005a, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s1
+dwc_ddrphy_apb_wr(0x9005b, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b16s2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0
+dwc_ddrphy_apb_wr(0x9005c, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s0
+dwc_ddrphy_apb_wr(0x9005d, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s1
+dwc_ddrphy_apb_wr(0x9005e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b17s2
+dwc_ddrphy_apb_wr(0x9005f, 0x11); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s0
+dwc_ddrphy_apb_wr(0x90060, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s1
+dwc_ddrphy_apb_wr(0x90061, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b18s2
+dwc_ddrphy_apb_wr(0x90062, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s0
+dwc_ddrphy_apb_wr(0x90063, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s1
+dwc_ddrphy_apb_wr(0x90064, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b19s2
+dwc_ddrphy_apb_wr(0x90065, 0x14f); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s0
+dwc_ddrphy_apb_wr(0x90066, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s1
+dwc_ddrphy_apb_wr(0x90067, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b20s2
+dwc_ddrphy_apb_wr(0x90068, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s0
+dwc_ddrphy_apb_wr(0x90069, 0x45a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s1
+dwc_ddrphy_apb_wr(0x9006a, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b21s2
+dwc_ddrphy_apb_wr(0x9006b, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s0
+dwc_ddrphy_apb_wr(0x9006c, 0x530); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s1
+dwc_ddrphy_apb_wr(0x9006d, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b22s2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 800, type = 0
+dwc_ddrphy_apb_wr(0x9006e, 0xc100); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s0
+dwc_ddrphy_apb_wr(0x9006f, 0x15c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s1
+dwc_ddrphy_apb_wr(0x90070, 0x139); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b23s2
+dwc_ddrphy_apb_wr(0x90071, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s0
+dwc_ddrphy_apb_wr(0x90072, 0x65a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s1
+dwc_ddrphy_apb_wr(0x90073, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b24s2
+dwc_ddrphy_apb_wr(0x90074, 0x41); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s0
+dwc_ddrphy_apb_wr(0x90075, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s1
+dwc_ddrphy_apb_wr(0x90076, 0x179); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b25s2
+dwc_ddrphy_apb_wr(0x90077, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s0
+dwc_ddrphy_apb_wr(0x90078, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s1
+dwc_ddrphy_apb_wr(0x90079, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b26s2
+dwc_ddrphy_apb_wr(0x9007a, 0x40c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s0
+dwc_ddrphy_apb_wr(0x9007b, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s1
+dwc_ddrphy_apb_wr(0x9007c, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b27s2
+dwc_ddrphy_apb_wr(0x9007d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s0
+dwc_ddrphy_apb_wr(0x9007e, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s1
+dwc_ddrphy_apb_wr(0x9007f, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b28s2
+dwc_ddrphy_apb_wr(0x90080, 0x4040); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s0
+dwc_ddrphy_apb_wr(0x90081, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s1
+dwc_ddrphy_apb_wr(0x90082, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b29s2
+dwc_ddrphy_apb_wr(0x90083, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s0
+dwc_ddrphy_apb_wr(0x90084, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s1
+dwc_ddrphy_apb_wr(0x90085, 0x48); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b30s2
+dwc_ddrphy_apb_wr(0x90086, 0x40); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s0
+dwc_ddrphy_apb_wr(0x90087, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s1
+dwc_ddrphy_apb_wr(0x90088, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b31s2
+dwc_ddrphy_apb_wr(0x90089, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s0
+dwc_ddrphy_apb_wr(0x9008a, 0x658); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s1
+dwc_ddrphy_apb_wr(0x9008b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b32s2
+dwc_ddrphy_apb_wr(0x9008c, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s0
+dwc_ddrphy_apb_wr(0x9008d, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s1
+dwc_ddrphy_apb_wr(0x9008e, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b33s2
+dwc_ddrphy_apb_wr(0x9008f, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s0
+dwc_ddrphy_apb_wr(0x90090, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s1
+dwc_ddrphy_apb_wr(0x90091, 0x78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b34s2
+dwc_ddrphy_apb_wr(0x90092, 0x549); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s0
+dwc_ddrphy_apb_wr(0x90093, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s1
+dwc_ddrphy_apb_wr(0x90094, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b35s2
+dwc_ddrphy_apb_wr(0x90095, 0xd49); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s0
+dwc_ddrphy_apb_wr(0x90096, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s1
+dwc_ddrphy_apb_wr(0x90097, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b36s2
+dwc_ddrphy_apb_wr(0x90098, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s0
+dwc_ddrphy_apb_wr(0x90099, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s1
+dwc_ddrphy_apb_wr(0x9009a, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b37s2
+dwc_ddrphy_apb_wr(0x9009b, 0x94c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s0
+dwc_ddrphy_apb_wr(0x9009c, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s1
+dwc_ddrphy_apb_wr(0x9009d, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b38s2
+dwc_ddrphy_apb_wr(0x9009e, 0x442); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s0
+dwc_ddrphy_apb_wr(0x9009f, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s1
+dwc_ddrphy_apb_wr(0x900a0, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b39s2
+dwc_ddrphy_apb_wr(0x900a1, 0x42); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s0
+dwc_ddrphy_apb_wr(0x900a2, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s1
+dwc_ddrphy_apb_wr(0x900a3, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b40s2
+dwc_ddrphy_apb_wr(0x900a4, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s0
+dwc_ddrphy_apb_wr(0x900a5, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s1
+dwc_ddrphy_apb_wr(0x900a6, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b41s2
+dwc_ddrphy_apb_wr(0x900a7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s0
+dwc_ddrphy_apb_wr(0x900a8, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s1
+dwc_ddrphy_apb_wr(0x900a9, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b42s2
+dwc_ddrphy_apb_wr(0x900aa, 0xa); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s0
+dwc_ddrphy_apb_wr(0x900ab, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s1
+dwc_ddrphy_apb_wr(0x900ac, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b43s2
+dwc_ddrphy_apb_wr(0x900ad, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s0
+dwc_ddrphy_apb_wr(0x900ae, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s1
+dwc_ddrphy_apb_wr(0x900af, 0x149); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b44s2
+dwc_ddrphy_apb_wr(0x900b0, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s0
+dwc_ddrphy_apb_wr(0x900b1, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s1
+dwc_ddrphy_apb_wr(0x900b2, 0x159); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b45s2
+dwc_ddrphy_apb_wr(0x900b3, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s0
+dwc_ddrphy_apb_wr(0x900b4, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s1
+dwc_ddrphy_apb_wr(0x900b5, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b46s2
+dwc_ddrphy_apb_wr(0x900b6, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s0
+dwc_ddrphy_apb_wr(0x900b7, 0x3c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s1
+dwc_ddrphy_apb_wr(0x900b8, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b47s2
+dwc_ddrphy_apb_wr(0x900b9, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s0
+dwc_ddrphy_apb_wr(0x900ba, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s1
+dwc_ddrphy_apb_wr(0x900bb, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b48s2
+dwc_ddrphy_apb_wr(0x900bc, 0xc); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s0
+dwc_ddrphy_apb_wr(0x900bd, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s1
+dwc_ddrphy_apb_wr(0x900be, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b49s2
+dwc_ddrphy_apb_wr(0x900bf, 0x3); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s0
+dwc_ddrphy_apb_wr(0x900c0, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s1
+dwc_ddrphy_apb_wr(0x900c1, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b50s2
+dwc_ddrphy_apb_wr(0x900c2, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s0
+dwc_ddrphy_apb_wr(0x900c3, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s1
+dwc_ddrphy_apb_wr(0x900c4, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b51s2
+//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 8, type = 0
+dwc_ddrphy_apb_wr(0x900c5, 0x3a); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s0
+dwc_ddrphy_apb_wr(0x900c6, 0x1e2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s1
+dwc_ddrphy_apb_wr(0x900c7, 0x9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b52s2
+dwc_ddrphy_apb_wr(0x900c8, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s0
+dwc_ddrphy_apb_wr(0x900c9, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s1
+dwc_ddrphy_apb_wr(0x900ca, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b53s2
+dwc_ddrphy_apb_wr(0x900cb, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s0
+dwc_ddrphy_apb_wr(0x900cc, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s1
+dwc_ddrphy_apb_wr(0x900cd, 0x16e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b54s2
+dwc_ddrphy_apb_wr(0x900ce, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s0
+dwc_ddrphy_apb_wr(0x900cf, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s1
+dwc_ddrphy_apb_wr(0x900d0, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b55s2
+dwc_ddrphy_apb_wr(0x900d1, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s0
+dwc_ddrphy_apb_wr(0x900d2, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s1
+dwc_ddrphy_apb_wr(0x900d3, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b56s2
+dwc_ddrphy_apb_wr(0x900d4, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s0
+dwc_ddrphy_apb_wr(0x900d5, 0x978); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s1
+dwc_ddrphy_apb_wr(0x900d6, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b57s2
+dwc_ddrphy_apb_wr(0x900d7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s0
+dwc_ddrphy_apb_wr(0x900d8, 0xa78); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s1
+dwc_ddrphy_apb_wr(0x900d9, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b58s2
+dwc_ddrphy_apb_wr(0x900da, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0
+dwc_ddrphy_apb_wr(0x900db, 0x980); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s1
+dwc_ddrphy_apb_wr(0x900dc, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s2
+dwc_ddrphy_apb_wr(0x900dd, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s0
+dwc_ddrphy_apb_wr(0x900de, 0xa80); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s1
+dwc_ddrphy_apb_wr(0x900df, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b60s2
+dwc_ddrphy_apb_wr(0x900e0, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s0
+dwc_ddrphy_apb_wr(0x900e1, 0x952); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s1
+dwc_ddrphy_apb_wr(0x900e2, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b61s2
+dwc_ddrphy_apb_wr(0x900e3, 0x32); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s0
+dwc_ddrphy_apb_wr(0x900e4, 0xa52); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s1
+dwc_ddrphy_apb_wr(0x900e5, 0x69); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b62s2
+dwc_ddrphy_apb_wr(0x900e6, 0x2); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s0
+dwc_ddrphy_apb_wr(0x900e7, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s1
+dwc_ddrphy_apb_wr(0x900e8, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b63s2
+dwc_ddrphy_apb_wr(0x900e9, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s0
+dwc_ddrphy_apb_wr(0x900ea, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s1
+dwc_ddrphy_apb_wr(0x900eb, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b64s2
+dwc_ddrphy_apb_wr(0x900ec, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s0
+dwc_ddrphy_apb_wr(0x900ed, 0x1400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s1
+dwc_ddrphy_apb_wr(0x900ee, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b65s2
+dwc_ddrphy_apb_wr(0x900ef, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s0
+dwc_ddrphy_apb_wr(0x900f0, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s1
+dwc_ddrphy_apb_wr(0x900f1, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b66s2
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 20, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 80, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 40, type = 0
+//// [phyinit_LoadPIECodeSections] No match for ANY enable_bits = 100, type = 0
+//// [phyinit_LoadPIECodeSections] Matched NO enable_bits = 2, type = 0
+dwc_ddrphy_apb_wr(0x900f2, 0x2cd); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s0
+dwc_ddrphy_apb_wr(0x900f3, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s1
+dwc_ddrphy_apb_wr(0x900f4, 0x68); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b67s2
+dwc_ddrphy_apb_wr(0x900f5, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s0
+dwc_ddrphy_apb_wr(0x900f6, 0x8e8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s1
+dwc_ddrphy_apb_wr(0x900f7, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b68s2
+dwc_ddrphy_apb_wr(0x900f8, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s0
+dwc_ddrphy_apb_wr(0x900f9, 0x3c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s1
+dwc_ddrphy_apb_wr(0x900fa, 0x1e9); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b69s2
+dwc_ddrphy_apb_wr(0x900fb, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s0
+dwc_ddrphy_apb_wr(0x900fc, 0x370); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s1
+dwc_ddrphy_apb_wr(0x900fd, 0x169); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b70s2
+dwc_ddrphy_apb_wr(0x900fe, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s0
+dwc_ddrphy_apb_wr(0x900ff, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s1
+dwc_ddrphy_apb_wr(0x90100, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b71s2
+dwc_ddrphy_apb_wr(0x90101, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s0
+dwc_ddrphy_apb_wr(0x90102, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s1
+dwc_ddrphy_apb_wr(0x90103, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b72s2
+dwc_ddrphy_apb_wr(0x90104, 0x10); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s0
+dwc_ddrphy_apb_wr(0x90105, 0x8138); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s1
+dwc_ddrphy_apb_wr(0x90106, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b73s2
+//// [phyinit_LoadPIECodeSections] Matched ANY enable_bits = 1, type = 0
+dwc_ddrphy_apb_wr(0x90107, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s0
+dwc_ddrphy_apb_wr(0x90108, 0x400); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s1
+dwc_ddrphy_apb_wr(0x90109, 0x10e); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b74s2
+dwc_ddrphy_apb_wr(0x9010a, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s0
+dwc_ddrphy_apb_wr(0x9010b, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s1
+dwc_ddrphy_apb_wr(0x9010c, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b75s2
+dwc_ddrphy_apb_wr(0x9010d, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s0
+dwc_ddrphy_apb_wr(0x9010e, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s1
+dwc_ddrphy_apb_wr(0x9010f, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b76s2
+dwc_ddrphy_apb_wr(0x90110, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s0
+dwc_ddrphy_apb_wr(0x90111, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s1
+dwc_ddrphy_apb_wr(0x90112, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b77s2
+dwc_ddrphy_apb_wr(0x90113, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s0
+dwc_ddrphy_apb_wr(0x90114, 0x448); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s1
+dwc_ddrphy_apb_wr(0x90115, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b78s2
+dwc_ddrphy_apb_wr(0x90116, 0xf); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s0
+dwc_ddrphy_apb_wr(0x90117, 0x7c0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s1
+dwc_ddrphy_apb_wr(0x90118, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b79s2
+dwc_ddrphy_apb_wr(0x90119, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s0
+dwc_ddrphy_apb_wr(0x9011a, 0xe8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s1
+dwc_ddrphy_apb_wr(0x9011b, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b80s2
+dwc_ddrphy_apb_wr(0x9011c, 0x7); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s0
+dwc_ddrphy_apb_wr(0x9011d, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s1
+dwc_ddrphy_apb_wr(0x9011e, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b81s2
+dwc_ddrphy_apb_wr(0x9011f, 0x47); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s0
+dwc_ddrphy_apb_wr(0x90120, 0x630); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s1
+dwc_ddrphy_apb_wr(0x90121, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b82s2
+dwc_ddrphy_apb_wr(0x90122, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s0
+dwc_ddrphy_apb_wr(0x90123, 0x618); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s1
+dwc_ddrphy_apb_wr(0x90124, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b83s2
+dwc_ddrphy_apb_wr(0x90125, 0x18); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s0
+dwc_ddrphy_apb_wr(0x90126, 0xe0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s1
+dwc_ddrphy_apb_wr(0x90127, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b84s2
+dwc_ddrphy_apb_wr(0x90128, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s0
+dwc_ddrphy_apb_wr(0x90129, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s1
+dwc_ddrphy_apb_wr(0x9012a, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b85s2
+dwc_ddrphy_apb_wr(0x9012b, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s0
+dwc_ddrphy_apb_wr(0x9012c, 0x8140); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s1
+dwc_ddrphy_apb_wr(0x9012d, 0x10c); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b86s2
+dwc_ddrphy_apb_wr(0x9012e, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s0
+dwc_ddrphy_apb_wr(0x9012f, 0x478); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s1
+dwc_ddrphy_apb_wr(0x90130, 0x109); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b87s2
+dwc_ddrphy_apb_wr(0x90131, 0x0); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s0
+dwc_ddrphy_apb_wr(0x90132, 0x1); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s1
+dwc_ddrphy_apb_wr(0x90133, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b88s2
+dwc_ddrphy_apb_wr(0x90134, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s0
+dwc_ddrphy_apb_wr(0x90135, 0x4); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s1
+dwc_ddrphy_apb_wr(0x90136, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b89s2
+dwc_ddrphy_apb_wr(0x90137, 0x8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s0
+dwc_ddrphy_apb_wr(0x90138, 0x7c8); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s1
+dwc_ddrphy_apb_wr(0x90139, 0x101); // DWC_DDRPHYA_INITENG0_base0_SequenceReg0b90s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 9013a to 90006
+dwc_ddrphy_apb_wr(0x90006, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s0
+dwc_ddrphy_apb_wr(0x90007, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s1
+dwc_ddrphy_apb_wr(0x90008, 0x8); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b0s2
+dwc_ddrphy_apb_wr(0x90009, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s0
+dwc_ddrphy_apb_wr(0x9000a, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s1
+dwc_ddrphy_apb_wr(0x9000b, 0x0); // DWC_DDRPHYA_INITENG0_base0_PostSequenceReg0b1s2
+//// [phyinit_LoadPIECodeSections] Moving start address from 9000c to d00e7
+dwc_ddrphy_apb_wr(0xd00e7, 0x400); // DWC_DDRPHYA_APBONLY0_SequencerOverride
+//// [phyinit_LoadPIECodeSections] End of dwc_ddrphy_phyinit_LoadPIECodeSections()
+dwc_ddrphy_apb_wr(0x20240, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat0
+dwc_ddrphy_apb_wr(0x20242, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat2
+dwc_ddrphy_apb_wr(0x20241, 0x4300); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat1
+dwc_ddrphy_apb_wr(0x20243, 0x8944); // DWC_DDRPHYA_MASTER0_base0_D5ACSMPtrXlat3
+//seq0b_LoadPstateSeqProductionCode(): ---------------------------------------------------------------------------------------------------
+//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b0000 start vector registers with 0.
+//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1000 start vector register with 54.
+//seq0b_LoadPstateSeqProductionCode(): Programming the 0B sequencer 0b1111 start vector register with 77.
+//seq0b_LoadPstateSeqProductionCode(): ---------------------------------------------------------------------------------------------------
+dwc_ddrphy_apb_wr(0x90017, 0x0); // DWC_DDRPHYA_INITENG0_base0_StartVector0b0
+dwc_ddrphy_apb_wr(0x9001f, 0x36); // DWC_DDRPHYA_INITENG0_base0_StartVector0b8
+dwc_ddrphy_apb_wr(0x90026, 0x4d); // DWC_DDRPHYA_INITENG0_base0_StartVector0b15
+dwc_ddrphy_apb_wr(0x9000c, 0x0); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag0
+dwc_ddrphy_apb_wr(0x9000d, 0x173); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag1
+dwc_ddrphy_apb_wr(0x9000e, 0x60); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag2
+dwc_ddrphy_apb_wr(0x9000f, 0x6110); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag3
+dwc_ddrphy_apb_wr(0x90010, 0x2152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag4
+dwc_ddrphy_apb_wr(0x90011, 0xdfbd); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag5
+dwc_ddrphy_apb_wr(0x90012, 0x8060); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag6
+dwc_ddrphy_apb_wr(0x90013, 0x6152); // DWC_DDRPHYA_INITENG0_base0_Seq0BDisableFlag7
+//// [phyinit_I_loadPIEImage] Enabling Phy Master Interface for DRAM drift compensation
+//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrTrainInterval to 0x0
+//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup::PhyMstrMaxReqToAck to 0x0
+dwc_ddrphy_apb_wr(0x20010, 0x0); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup_p0
+//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming PPTTrainSetup2::PhyMstrFreqOverride to 0x3
+dwc_ddrphy_apb_wr(0x20011, 0x3); // DWC_DDRPHYA_MASTER0_base0_PPTTrainSetup2_p0
+//// [phyinit_I_loadPIEImage] Programming D5ACSMXlatSelect to 0x1
+dwc_ddrphy_apb_wr(0x20281, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSMXlatSelect
+//// [phyinit_I_loadPIEImage] Programming DbyteRxEnTrain::EnDqsSampNegRxEn to 0x1
+dwc_ddrphy_apb_wr(0x2003b, 0x2); // DWC_DDRPHYA_MASTER0_base0_DbyteRxEnTrain
+//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming TrackingModeCntrl to 0x131f
+dwc_ddrphy_apb_wr(0x20041, 0x131f); // DWC_DDRPHYA_MASTER0_base0_TrackingModeCntrl_p0
+//// [phyinit_I_loadPIEImage] Programming D5ACSM0MaskCs to 0xe
+dwc_ddrphy_apb_wr(0x20131, 0xe); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0MaskCs
+//// [phyinit_I_loadPIEImage] Programming D5ACSM1MaskCs to 0xf
+dwc_ddrphy_apb_wr(0x20151, 0xf); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1MaskCs
+//// [phyinit_I_loadPIEImage] Pstate=0, Memclk=1600MHz, Programming Seq0BGPR6[0] with OuterLoopRepeatCnt values to 0x2
+dwc_ddrphy_apb_wr(0x90306, 0x2); // DWC_DDRPHYA_INITENG0_base0_Seq0BGPR6_p0
+//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>OuterLoopRepeatCnt=2
+dwc_ddrphy_apb_wr(0x2012a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0OuterLoopRepeatCnt
+dwc_ddrphy_apb_wr(0x2014a, 0x2); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1OuterLoopRepeatCnt
+//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AddressMask=7ff
+dwc_ddrphy_apb_wr(0x20126, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AddressMask
+dwc_ddrphy_apb_wr(0x20146, 0x7ff); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AddressMask
+//// [phyinit_I_loadPIEImage] Programming D5ACSM<0/1>AlgaIncVal=1
+dwc_ddrphy_apb_wr(0x20127, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM0AlgaIncVal
+dwc_ddrphy_apb_wr(0x20147, 0x1); // DWC_DDRPHYA_MASTER0_base0_D5ACSM1AlgaIncVal
+//// [phyinit_I_loadPIEImage] Turn on calibration and hold idle until dfi_init_start is asserted sequence is triggered.
+//// [phyinit_I_loadPIEImage] Programming CalZap to 0x1
+//// [phyinit_I_loadPIEImage] Programming CalRate::CalRun to 0x1
+//// [phyinit_I_loadPIEImage] Programming CalRate to 0x19
+dwc_ddrphy_apb_wr(0x20089, 0x1); // DWC_DDRPHYA_MASTER0_base0_CalZap
+dwc_ddrphy_apb_wr(0x20088, 0x19); // DWC_DDRPHYA_MASTER0_base0_CalRate
+//// [phyinit_I_loadPIEImage] Programming ForceClkGaterEnables::ForcePubDxClkEnLow to 0x0
+dwc_ddrphy_apb_wr(0x200a6, 0x0); // DWC_DDRPHYA_MASTER0_base0_ForceClkGaterEnables
+//// Disabling Ucclk (PMU) and Hclk (training hardware)
+dwc_ddrphy_apb_wr(0xc0080, 0x0); // DWC_DDRPHYA_DRTUB0_UcclkHclkEnables
+//// Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1.
+dwc_ddrphy_apb_wr(0xd0000, 0x1); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+//// [phyinit_userCustom_wait] Wait 40 DfiClks
+//// [phyinit_I_loadPIEImage] End of dwc_ddrphy_phyinit_I_loadPIEImage()
+//
+//
+////##############################################################
+////
+//// dwc_ddrphy_phyinit_userCustom_customPostTrain is a user-editable function.
+////
+//// The purpose of dwc_ddrphy_phyinit_userCustom_customPostTrain() is to override any
+//// CSR values programmed by the training firmware or dwc_ddrphy_phyinit_progCsrSkipTrain()
+//// This function is executed after training
+////
+//// IMPORTANT: in this function, user shall not override any values in userInputBasic and
+//// userInputAdvanced data structures. Only CSR programming should be done in this function.
+////
+//// Sequence of Events in this function are:
+//// 1. Enable APB access.
+//// 2. Issue register writes
+//// 3. Isolate APB access.
+//
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_customPostTrain();
+
+//// [dwc_ddrphy_phyinit_userCustom_customPostTrain] End of dwc_ddrphy_phyinit_userCustom_customPostTrain()
+//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] Start of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode()
+//
+//
+////##############################################################
+////
+//// 4.3.10(J) Initialize the PHY to Mission Mode through DFI Initialization
+////
+//// Initialize the PHY to mission mode as follows:
+////
+//// 1. Set the PHY input clocks to the desired frequency.
+//// 2. Initialize the PHY to mission mode by performing DFI Initialization.
+//// Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>.
+//// Note: The PHY training firmware initializes the DRAM state. if skip
+//// training is used, the DRAM state is not initialized.
+////
+////##############################################################
+//
+dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(sdrammc);
+
+//
+//// [dwc_ddrphy_phyinit_userCustom_J_enterMissionMode] End of dwc_ddrphy_phyinit_userCustom_J_enterMissionMode()
+// [dwc_ddrphy_phyinit_sequence] End of dwc_ddrphy_phyinit_sequence()
+// [dwc_ddrphy_phyinit_main] End of dwc_ddrphy_phyinit_main()
diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c
new file mode 100644
index 0000000..4a019c4
--- /dev/null
+++ b/drivers/ram/aspeed/sdram_ast2700.c
@@ -0,0 +1,1036 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <asm/io.h>
+#include <asm/arch/fmc_hdr.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/sdram.h>
+#include <config.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+#include <ram.h>
+
+enum ddr_type {
+ DDR4_1600 = 0x0,
+ DDR4_2400,
+ DDR4_3200,
+ DDR5_3200,
+
+ DDR_TYPES
+};
+
+enum ddr_size {
+ DDR_SIZE_256MB,
+ DDR_SIZE_512MB,
+ DDR_SIZE_1GB,
+ DDR_SIZE_2GB,
+
+ DDR_SIZE_MAX,
+};
+
+#define IS_DDR4(t) \
+ (((t) <= DDR4_3200) ? 1 : 0)
+
+struct sdrammc_ac_timing {
+ u32 t_cl;
+ u32 t_cwl;
+ u32 t_bl;
+ u32 t_rcd; /* ACT-to-read/write command delay */
+ u32 t_rp; /* PRE command period */
+ u32 t_ras; /* ACT-to-PRE command delay */
+ u32 t_rrd; /* ACT-to-ACT delay for different BG */
+ u32 t_rrd_l; /* ACT-to-ACT delay for same BG */
+ u32 t_faw; /* Four active window */
+ u32 t_rtp; /* Read-to-PRE command delay */
+ u32 t_wtr; /* Minimum write to read command for different BG */
+ u32 t_wtr_l; /* Minimum write to read command for same BG */
+ u32 t_wtr_a; /* Write to read command for same BG with auto precharge */
+ u32 t_wtp; /* Minimum write to precharge command delay */
+ u32 t_rtw; /* minimum read to write command */
+ u32 t_ccd_l; /* CAS-to-CAS delay for same BG */
+ u32 t_dllk; /* DLL locking time */
+ u32 t_cksre; /* valid clock before after self-refresh or power-down entry/exit process */
+ u32 t_pd; /* power-down entry to exit minimum width */
+ u32 t_xp; /* exit power-down to valid command delay */
+ u32 t_rfc; /* refresh time period */
+ u32 t_mrd;
+ u32 t_refsbrd;
+ u32 t_rfcsb;
+ u32 t_cshsr;
+ u32 t_zq;
+};
+
+static const struct sdrammc_ac_timing ac_table[] = {
+ [DDR4_1600] = {
+ .t_cl = 10, .t_cwl = 9, .t_bl = 8, .t_rcd = 10,
+ .t_rp = 10, .t_ras = 28, .t_rrd = 5, .t_rrd_l = 6,
+ .t_faw = 28, .t_rtp = 6, .t_wtr = 2, .t_wtr_l = 6,
+ .t_wtr_a = 0, .t_wtp = 12, .t_rtw = 0, .t_ccd_l = 5,
+ .t_dllk = 597, .t_cksre = 8, .t_pd = 4, .t_xp = 5,
+ .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0,
+ .t_cshsr = 0, .t_zq = 80,
+ },
+ [DDR4_2400] = {
+ .t_cl = 15, .t_cwl = 12, .t_bl = 8, .t_rcd = 16,
+ .t_rp = 16, .t_ras = 39, .t_rrd = 7, .t_rrd_l = 8,
+ .t_faw = 37, .t_rtp = 10, .t_wtr = 4, .t_wtr_l = 10,
+ .t_wtr_a = 0, .t_wtp = 19, .t_rtw = 0, .t_ccd_l = 7,
+ .t_dllk = 768, .t_cksre = 13, .t_pd = 7, .t_xp = 8,
+ .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0,
+ .t_cshsr = 0, .t_zq = 80,
+ },
+ [DDR4_3200] = {
+ .t_cl = 20, .t_cwl = 16, .t_bl = 8, .t_rcd = 20,
+ .t_rp = 20, .t_ras = 52, .t_rrd = 9, .t_rrd_l = 11,
+ .t_faw = 48, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 12,
+ .t_wtr_a = 0, .t_wtp = 24, .t_rtw = 0, .t_ccd_l = 8,
+ .t_dllk = 1023, .t_cksre = 16, .t_pd = 8, .t_xp = 10,
+ .t_rfc = 880, .t_mrd = 24, .t_refsbrd = 0, .t_rfcsb = 0,
+ .t_cshsr = 0, .t_zq = 80,
+ },
+ [DDR5_3200] = {
+ .t_cl = 26, .t_cwl = 24, .t_bl = 16, .t_rcd = 26,
+ .t_rp = 26, .t_ras = 52, .t_rrd = 8, .t_rrd_l = 8,
+ .t_faw = 40, .t_rtp = 12, .t_wtr = 4, .t_wtr_l = 16,
+ .t_wtr_a = 36, .t_wtp = 48, .t_rtw = 0, .t_ccd_l = 8,
+ .t_dllk = 1024, .t_cksre = 9, .t_pd = 13, .t_xp = 13,
+ .t_rfc = 880, .t_mrd = 23, .t_refsbrd = 48, .t_rfcsb = 208,
+ .t_cshsr = 30,
+ .t_zq = 48,
+ },
+};
+
+struct sdrammc {
+ u32 type;
+ void __iomem *regs;
+ void __iomem *phy;
+ void __iomem *scu0;
+ void __iomem *scu1;
+ const struct sdrammc_ac_timing *ac;
+ struct ram_info info;
+};
+
+static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+ void *scu0 = sdrammc->scu0;
+ size_t vga_memsz[] = {
+ SZ_32M,
+ SZ_64M,
+ };
+ u32 reg, sel, dual = 0;
+
+ sel = readl(®s->gfmcfg) & 0x1;
+
+ reg = readl(scu0 + SCU0_PCI_MISC70);
+ if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) {
+ debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M);
+ dual++;
+ }
+
+ reg = readl(scu0 + SCU0_PCI_MISC80);
+ if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) {
+ debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M);
+ dual++;
+ }
+
+ return vga_memsz[sel] * dual;
+}
+
+static int sdrammc_calc_size(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 val, test_pattern = 0xdeadbeef;
+ size_t sz;
+
+ struct {
+ u32 size;
+ int rfc[2];
+ } ddr_capacity[] = {
+ { 0x10000000UL, {208, 256} }, /* 256MB */
+ { 0x20000000UL, {208, 416} }, /* 512MB */
+ { 0x40000000UL, {208, 560} }, /* 1GB */
+ { 0x80000000UL, {472, 880} }, /* 2GB */
+ };
+
+ /* Configure ram size to max to enable whole area */
+ val = readl(®s->mcfg);
+ val &= ~(0x7 << 2);
+ writel(val | (DDR_SIZE_2GB << 2), ®s->mcfg);
+
+ /* Clear basement. */
+ writel(0, (void *)CFG_SYS_SDRAM_BASE);
+
+ for (sz = DDR_SIZE_2GB - 1; sz > DDR_SIZE_256MB; sz--) {
+ test_pattern = (test_pattern << 4) + sz;
+ writel(test_pattern, (void *)(CFG_SYS_SDRAM_BASE + ddr_capacity[sz].size));
+
+ if (readl((void *)CFG_SYS_SDRAM_BASE) != test_pattern)
+ break;
+ }
+
+ /* re-configure ram size to dramc. */
+ val = readl(®s->mcfg);
+ val &= ~(0x7 << 2);
+ writel(val | ((sz + 1) << 2), ®s->mcfg);
+
+ /* update rfc in ac_timing5 register. */
+ val = readl(®s->actime5);
+ val &= ~(0x3ff);
+ val |= (ddr_capacity[sz + 1].rfc[IS_DDR4(sdrammc->type)] >> 1);
+ writel(val, ®s->actime5);
+
+ /* report actual ram base and size to kernel */
+ sdrammc->info.base = CFG_SYS_SDRAM_BASE;
+ sdrammc->info.size = ddr_capacity[sz + 1].size;
+
+ /* reserve the VGA memory */
+ sdrammc->info.size -= ast2700_sdrammc_get_vga_mem_size(sdrammc);
+
+ return 0;
+}
+
+static int sdrammc_bist(struct sdrammc *sdrammc, u32 addr, u32 size, u32 cfg, u32 timeout)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 val;
+ u32 err = 0;
+
+ writel(0, ®s->bistcfg);
+ writel(cfg, ®s->bistcfg);
+ writel(addr >> 4, ®s->bist_addr);
+ writel(size >> 4, ®s->bist_size);
+ writel(0x89abcdef, ®s->bist_patt);
+ writel(cfg | DRAMC_BISTCFG_START, ®s->bistcfg);
+
+ while (!(readl(®s->intr_status) & DRAMC_IRQSTA_BIST_DONE))
+ ;
+
+ writel(DRAMC_IRQSTA_BIST_DONE, ®s->intr_clear);
+
+ val = readl(®s->bist_res);
+
+ if (val & DRAMC_BISTRES_DONE) {
+ if (val & DRAMC_BISTRES_FAIL)
+ err++;
+ } else {
+ err++;
+ }
+
+ return err;
+}
+
+static void sdrammc_enable_refresh(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+
+ /* refresh update */
+ clrbits_le32(®s->refctl, 0x8000);
+}
+
+static void sdrammc_mr_send(struct sdrammc *sdrammc, u32 ctrl, u32 op)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+
+ writel(op, ®s->mrwr);
+ writel(ctrl | DRAMC_MRCTL_CMD_START, ®s->mrctl);
+
+ while (!(readl(®s->intr_status) & DRAMC_IRQSTA_MR_DONE))
+ ;
+
+ writel(DRAMC_IRQSTA_MR_DONE, ®s->intr_clear);
+}
+
+static void sdrammc_config_mrs(struct sdrammc *sdrammc)
+{
+ const struct sdrammc_ac_timing *ac = sdrammc->ac;
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 mr0_cas, mr0_rtp, mr0_val;
+ u32 mr6_tccd_l, mr6_val;
+ u32 mr2_cwl, mr2_val;
+ u32 mr1_val;
+ u32 mr3_val;
+ u32 mr4_val;
+ u32 mr5_val;
+
+ if (!IS_DDR4(sdrammc->type))
+ return;
+
+ //-------------------------------------------------------------------
+ // CAS Latency (Table-15)
+ //-------------------------------------------------------------------
+ switch (ac->t_cl) {
+ case 9:
+ mr0_cas = 0x00; //5'b00000;
+ break;
+ case 10:
+ mr0_cas = 0x01; //5'b00001;
+ break;
+ case 11:
+ mr0_cas = 0x02; //5'b00010;
+ break;
+ case 12:
+ mr0_cas = 0x03; //5'b00011;
+ break;
+ case 13:
+ mr0_cas = 0x04; //5'b00100;
+ break;
+ case 14:
+ mr0_cas = 0x05; //5'b00101;
+ break;
+ case 15:
+ mr0_cas = 0x06; //5'b00110;
+ break;
+ case 16:
+ mr0_cas = 0x07; //5'b00111;
+ break;
+ case 18:
+ mr0_cas = 0x08; //5'b01000;
+ break;
+ case 20:
+ mr0_cas = 0x09; //5'b01001;
+ break;
+ case 22:
+ mr0_cas = 0x0a; //5'b01010;
+ break;
+ case 24:
+ mr0_cas = 0x0b; //5'b01011;
+ break;
+ case 23:
+ mr0_cas = 0x0c; //5'b01100;
+ break;
+ case 17:
+ mr0_cas = 0x0d; //5'b01101;
+ break;
+ case 19:
+ mr0_cas = 0x0e; //5'b01110;
+ break;
+ case 21:
+ mr0_cas = 0x0f; //5'b01111;
+ break;
+ case 25:
+ mr0_cas = 0x10; //5'b10000;
+ break;
+ case 26:
+ mr0_cas = 0x11; //5'b10001;
+ break;
+ case 27:
+ mr0_cas = 0x12; //5'b10010;
+ break;
+ case 28:
+ mr0_cas = 0x13; //5'b10011;
+ break;
+ case 30:
+ mr0_cas = 0x15; //5'b10101;
+ break;
+ case 32:
+ mr0_cas = 0x17; //5'b10111;
+ break;
+ }
+
+ //-------------------------------------------------------------------
+ // WR and RTP (Table-14)
+ //-------------------------------------------------------------------
+ switch (ac->t_rtp) {
+ case 5:
+ mr0_rtp = 0x0; //4'b0000;
+ break;
+ case 6:
+ mr0_rtp = 0x1; //4'b0001;
+ break;
+ case 7:
+ mr0_rtp = 0x2; //4'b0010;
+ break;
+ case 8:
+ mr0_rtp = 0x3; //4'b0011;
+ break;
+ case 9:
+ mr0_rtp = 0x4; //4'b0100;
+ break;
+ case 10:
+ mr0_rtp = 0x5; //4'b0101;
+ break;
+ case 12:
+ mr0_rtp = 0x6; //4'b0110;
+ break;
+ case 11:
+ mr0_rtp = 0x7; //4'b0111;
+ break;
+ case 13:
+ mr0_rtp = 0x8; //4'b1000;
+ break;
+ }
+
+ //-------------------------------------------------------------------
+ // CAS Write Latency (Table-21)
+ //-------------------------------------------------------------------
+ switch (ac->t_cwl) {
+ case 9:
+ mr2_cwl = 0x0; // 3'b000; // 1600
+ break;
+ case 10:
+ mr2_cwl = 0x1; // 3'b001; // 1866
+ break;
+ case 11:
+ mr2_cwl = 0x2; // 3'b010; // 2133
+ break;
+ case 12:
+ mr2_cwl = 0x3; // 3'b011; // 2400
+ break;
+ case 14:
+ mr2_cwl = 0x4; // 3'b100; // 2666
+ break;
+ case 16:
+ mr2_cwl = 0x5; // 3'b101; // 2933/3200
+ break;
+ case 18:
+ mr2_cwl = 0x6; // 3'b110;
+ break;
+ case 20:
+ mr2_cwl = 0x7; // 3'b111;
+ break;
+ }
+
+ //-------------------------------------------------------------------
+ // tCCD_L and tDLLK
+ //-------------------------------------------------------------------
+ switch (ac->t_ccd_l) {
+ case 4:
+ mr6_tccd_l = 0x0; //3'b000; // rate <= 1333
+ break;
+ case 5:
+ mr6_tccd_l = 0x1; //3'b001; // 1333 < rate <= 1866
+ break;
+ case 6:
+ mr6_tccd_l = 0x2; //3'b010; // 1866 < rate <= 2400
+ break;
+ case 7:
+ mr6_tccd_l = 0x3; //3'b011; // 2400 < rate <= 2666
+ break;
+ case 8:
+ mr6_tccd_l = 0x4; //3'b100; // 2666 < rate <= 3200
+ break;
+ }
+
+ /*
+ * mr0_val =
+ * mr0_rtp[3], // 13
+ * mr0_cas[4], // 12
+ * mr0_rtp[2:0], // 13,11-9: WR and RTP
+ * 1'b0, // 8: DLL reset
+ * 1'b0, // 7: TM
+ * mr0_cas[3:1], // 6-4,2: CAS latency
+ * 1'b0, // 3: sequential
+ * mr0_cas[0],
+ * 2'b00 // 1-0: burst length
+ */
+ mr0_val = ((mr0_cas & 0x1) << 2) |
+ (((mr0_cas >> 1) & 0x7) << 4) |
+ (((mr0_cas >> 4) & 0x1) << 12) |
+ ((mr0_rtp & 0x7) << 9) |
+ (((mr0_rtp >> 3) & 0x1) << 13);
+
+ /*
+ * 3'b2 //[10:8]: rtt_nom, 000:disable,001:rzq/4,010:rzq/2,011:rzq/6,100:rzq/1,101:rzq/5,110:rzq/3,111:rzq/7
+ * 1'b0 //[7]: write leveling enable
+ * 2'b0 //[6:5]: reserved
+ * 2'b0 //[4:3]: additive latency
+ * 2'b0 //[2:1]: output driver impedance
+ * 1'b1 //[0]: enable dll
+ */
+ mr1_val = 0x201;
+
+ /*
+ * [10:9]: rtt_wr, 00:dynamic odt off, 01:rzq/2, 10:rzq/1, 11: hi-z
+ * [8]: 0
+ */
+ mr2_val = ((mr2_cwl & 0x7) << 3) | 0x200;
+
+ mr3_val = 0;
+
+ mr4_val = 0;
+
+ /*
+ * mr5_val = {
+ * 1'b0, // 13: RFU
+ * 1'b0, // 12: read DBI
+ * 1'b0, // 11: write DBI
+ * 1'b1, // 10: Data mask
+ * 1'b0, // 9: C/A parity persistent error
+ * 3'b000, // 8-6: RTT_PARK (disable)
+ * 1'b1, // 5: ODT input buffer during power down mode
+ * 1'b0, // 4: C/A parity status
+ * 1'b0, // 3: CRC error clear
+ * 3'b0 // 2-0: C/A parity latency mode
+ * };
+ */
+ mr5_val = 0x420;
+
+ /*
+ * mr6_val = {
+ * 1'b0, // 13, 9-8: RFU
+ * mr6_tccd_l[2:0], // 12-10: tCCD_L
+ * 2'b0, // 13, 9-8: RFU
+ * 1'b0, // 7: VrefDQ training enable
+ * 1'b0, // 6: VrefDQ training range
+ * 6'b0 // 5-0: VrefDQ training value
+ * };
+ */
+ mr6_val = ((mr6_tccd_l & 0x7) << 10);
+
+ writel((mr1_val << 16) + mr0_val, ®s->mr01);
+ writel((mr3_val << 16) + mr2_val, ®s->mr23);
+ writel((mr5_val << 16) + mr4_val, ®s->mr45);
+ writel(mr6_val, ®s->mr67);
+
+ /* Power-up initialization sequence */
+ sdrammc_mr_send(sdrammc, MR_ADDR(3), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(6), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(5), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(4), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(2), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(1), 0);
+ sdrammc_mr_send(sdrammc, MR_ADDR(0), 0);
+}
+
+static void sdrammc_exit_self_refresh(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+
+ /* exit self-refresh after phy init */
+ setbits_le32(®s->mctl, DRAMC_MCTL_SELF_REF_START);
+
+ /* query if self-ref done */
+ while (!(readl(®s->intr_status) & DRAMC_IRQSTA_REF_DONE))
+ ;
+
+ /* clear status */
+ writel(DRAMC_IRQSTA_REF_DONE, ®s->intr_clear);
+ udelay(1);
+}
+
+/* user-customized functions for the vendor PHY init code */
+#define DWC_PHY_IMEM_OFST 0x50000
+#define DWC_PHY_DMEM_OFST 0x58000
+#define DWC_PHY_MB_START_STREAM_MSG 0x8
+#define DWC_PHY_MB_TRAIN_SUCCESS 0x7
+#define DWC_PHY_MB_TRAIN_FAIL 0xff
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+ writew((data), sdrammc->phy + ((addr) << 1))
+
+#define dwc_ddrphy_apb_rd(addr) \
+ readw(sdrammc->phy + ((addr) << 1))
+
+#define dwc_ddrphy_apb_wr_32b(addr, data) \
+ writel((data), sdrammc->phy + ((addr) << 1))
+
+#define dwc_ddrphy_apb_rd_32b(addr) \
+ readl(sdrammc->phy + ((addr) << 1))
+
+void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox)
+{
+ u32 val;
+
+ /* 1. Poll the UctWriteProtShadow, looking for a 0 */
+ while (dwc_ddrphy_apb_rd(0xd0004) & BIT(0))
+ ;
+
+ /* 2. When a 0 is seen, read the UctWriteOnlyShadow register to get the major message number. */
+ *mbox = dwc_ddrphy_apb_rd(0xd0032) & 0xffff;
+
+ /* 3. If reading a streaming or SMBus message, also read the UctDatWriteOnlyShadow register. */
+ if (mode) {
+ val = (dwc_ddrphy_apb_rd(0xd0034)) & 0xffff;
+ *mbox |= (val << 16);
+ }
+
+ /* 4. Write the DctWriteProt to 0 to acknowledge the reception of the message */
+ dwc_ddrphy_apb_wr(0xd0031, 0);
+
+ /* 5. Poll the UctWriteProtShadow, looking for a 1 */
+ while (!(dwc_ddrphy_apb_rd(0xd0004) & BIT(0)))
+ ;
+
+ /* 6. When a 1 is seen, write the DctWriteProt to 1 to complete the protocol */
+ dwc_ddrphy_apb_wr(0xd0031, 1);
+}
+
+uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half)
+{
+ u32 data_word;
+
+ data_word = dwc_ddrphy_apb_rd_32b((addr_half >> 1) << 1);
+
+ if (addr_half & 0x1)
+ data_word = data_word >> 16;
+ else
+ data_word &= 0xffff;
+
+ return data_word;
+}
+
+int dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(struct sdrammc *sdrammc, int train2D)
+{
+ u32 msg;
+
+ if (IS_DDR4(sdrammc->type)) {
+ /* DWC_PHY_DDR4_MB_RESULT */
+ msg = dwc_readMsgBlock(sdrammc, 0x5800a);
+ if (msg & 0xff)
+ debug("%s: Training Failure index (0x%x)\n", __func__, msg);
+ else
+ debug("%s: %dD Training Passed\n", __func__, train2D ? 2 : 1);
+ } else {
+ /* DWC_PHY_DDR5_MB_RESULT */
+ msg = dwc_readMsgBlock(sdrammc, 0x58007);
+ if (msg & 0xff00)
+ debug("%s: Training Failure index (0x%x)\n", __func__, msg);
+ else
+ debug("%s: DDR5 1D/2D Training Passed\n", __func__);
+
+ /* DWC_PHY_DDR5_MB_RESULT_ADR */
+ msg = dwc_readMsgBlock(sdrammc, 0x5800a);
+ debug("%s: Result Address Offset (0x%x)\n", __func__, msg);
+ }
+
+ return 0;
+}
+
+void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void)
+{
+ /* do nothing */
+}
+
+void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+
+ /*
+ * 1. Drive PwrOkIn to 0. Note: Reset, DfiClk, and APBCLK can be X.
+ * 2. Start DfiClk and APBCLK
+ * 3. Drive Reset to 1 and PRESETn_APB to 0.
+ * Note: The combination of PwrOkIn=0 and Reset=1 signals a cold reset to the PHY.
+ */
+ writel(DRAMC_MCTL_PHY_RESET, ®s->mctl);
+ udelay(2);
+
+ /*
+ * 5. Drive PwrOkIn to 1. Once the PwrOkIn is asserted (and Reset is still asserted),
+ * DfiClk synchronously switches to any legal input frequency.
+ */
+ writel(DRAMC_MCTL_PHY_RESET | DRAMC_MCTL_PHY_POWER_ON, ®s->mctl);
+ udelay(2);
+
+ /*
+ * 7. Drive Reset to 0. Note: All DFI and APB inputs must be driven at valid reset states
+ * before the deassertion of Reset.
+ */
+ writel(DRAMC_MCTL_PHY_POWER_ON, ®s->mctl);
+ udelay(2);
+
+ /*
+ * 9. Drive PRESETn_APB to 1 to de-assert reset on the ABP bus.
+ * 10. The PHY is now in the reset state and is ready to accept APB transactions.
+ */
+}
+
+void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void)
+{
+ /* do nothing */
+}
+
+void dwc_ddrphy_phyinit_userCustom_customPostTrain(void)
+{
+ /* do nothing */
+}
+
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(struct sdrammc *sdrammc)
+{
+ dwc_ddrphy_apb_wr(0xd0031, 1); /* DWC_DCTWRITEPROT */
+ dwc_ddrphy_apb_wr(0xd0033, 1); /* DWC_UCTWRITEPROT */
+}
+
+void dwc_ddrphy_phyinit_userCustom_G_waitFwDone(struct sdrammc *sdrammc)
+{
+ u32 mbox, msg = 0;
+
+ while (msg != DWC_PHY_MB_TRAIN_SUCCESS && msg != DWC_PHY_MB_TRAIN_FAIL) {
+ dwc_get_mailbox(sdrammc, 0, &mbox);
+ msg = mbox & 0xffff;
+ }
+}
+
+void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(struct sdrammc *sdrammc)
+{
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 val;
+
+ /*
+ * 1. Set the PHY input clocks to the desired frequency.
+ * 2. Initialize the PHY to mission mode by performing DFI Initialization.
+ * Please see the DFI specification for more information. See the DFI frequency bus encoding in section <XXX>.
+ * Note: The PHY training firmware initializes the DRAM state. if skip
+ * training is used, the DRAM state is not initialized.
+ */
+
+ writel(0xffffffff, (void *)®s->intr_mask);
+
+ writel(0x0, (void *)®s->dcfg);
+
+ if (!IS_DDR4(sdrammc->type)) {
+ dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ dwc_ddrphy_apb_wr(0x20240, 0x3900); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */
+ dwc_ddrphy_apb_wr(0x900da, 8); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */
+ dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ }
+
+ /* phy init start */
+ val = readl((void *)®s->mctl);
+ val = val | DRAMC_MCTL_PHY_INIT_START;
+ writel(val, (void *)®s->mctl);
+
+ /* wait phy complete */
+ while (1) {
+ val = readl(®s->intr_status) & DRAMC_IRQSTA_PHY_INIT_DONE;
+ if (val == DRAMC_IRQSTA_PHY_INIT_DONE)
+ break;
+ }
+
+ writel(0xffff, (void *)®s->intr_clear);
+
+ while (readl((void *)®s->intr_status))
+ ;
+
+ if (!IS_DDR4(sdrammc->type)) {
+ dwc_ddrphy_apb_wr(0xd0000, 0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ dwc_ddrphy_apb_wr(0x20240, 0x4300); /* DWC_DDRPHYA_MASTER0_base0_D5ACSMPtr0lat0 */
+ dwc_ddrphy_apb_wr(0x900da, 0); /* DWC_DDRPHYA_INITENG0_base0_SequenceReg0b59s0 */
+ dwc_ddrphy_apb_wr(0xd0000, 1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+ }
+}
+
+int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int train2D)
+{
+ u32 imem_ofst, imem_size;
+ u32 pb_type;
+
+ if (IS_DDR4(sdrammc->type))
+ pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_IMEM : PBT_DDR4_PMU_TRAIN_IMEM;
+ else
+ pb_type = PBT_DDR5_PMU_TRAIN_IMEM;
+
+ fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size);
+
+ memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1),
+ (void *)(0x20000000 + imem_ofst), imem_size);
+
+ return 0;
+}
+
+int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc,
+ const int pState, const int train2D)
+{
+ u32 dmem_ofst, dmem_size;
+ u32 pb_type;
+
+ if (IS_DDR4(sdrammc->type))
+ pb_type = (train2D) ? PBT_DDR4_2D_PMU_TRAIN_DMEM : PBT_DDR4_PMU_TRAIN_DMEM;
+ else
+ pb_type = PBT_DDR5_PMU_TRAIN_DMEM;
+
+ fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size);
+
+ memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1),
+ (void *)(0x20000000 + dmem_ofst), dmem_size);
+
+ return 0;
+}
+
+static void sdrammc_dwc_phy_init(struct sdrammc *sdrammc)
+{
+ /* enable ddr phy free-run clock */
+ writel(SCU0_CLKGATE1_CLR_DDRPHY, sdrammc->scu0 + SCU0_CLKGATE1_CLR);
+
+ /* include the vendor-provided PHY init code */
+ if (IS_DDR4(sdrammc->type)) {
+ #include "dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c"
+ } else {
+ #include "dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c"
+ }
+}
+
+static void sdrammc_config_ac_timing(struct sdrammc *sdrammc)
+{
+ const struct sdrammc_ac_timing *ac = sdrammc->ac;
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 actime;
+
+#define ACTIME1(ccd, rrd_l, rrd, mrd) \
+ (((ccd) << 24) | \
+ (((rrd_l) >> 1) << 16) | \
+ (((rrd) >> 1) << 8) | \
+ ((mrd) >> 1))
+
+#define ACTIME2(faw, rp, ras, rcd) \
+ ((((faw) >> 1) << 24) | \
+ (((rp) >> 1) << 16) | \
+ (((ras) >> 1) << 8) | \
+ ((rcd) >> 1))
+
+#define ACTIME3(wtr, rtw, wtp, rtp) \
+ ((((wtr) >> 1) << 24) | \
+ (((rtw) >> 1) << 16) | \
+ (((wtp) >> 1) << 8) | \
+ ((rtp) >> 1))
+
+#define ACTIME4(wtr_a, wtr_l) \
+ ((((wtr_a) >> 1) << 8) | \
+ ((wtr_l) >> 1))
+
+#define ACTIME5(refsbrd, rfcsb, rfc) \
+ ((((refsbrd) >> 1) << 20) | \
+ (((rfcsb) >> 1) << 10) | \
+ ((rfc) >> 1))
+
+#define ACTIME6(cshsr, pd, xp, cksre) \
+ ((((cshsr) >> 1) << 24) | \
+ (((pd) >> 1) << 16) | \
+ (((xp) >> 1) << 8) | \
+ ((cksre) >> 1))
+
+#define ACTIME7(zqcs, dllk) \
+ ((((zqcs) >> 1) << 10) | \
+ ((dllk) >> 1))
+
+ actime = ACTIME1(ac->t_ccd_l, ac->t_rrd_l, ac->t_rrd, ac->t_mrd);
+ writel(actime, ®s->actime1);
+
+ actime = ACTIME2(ac->t_faw, ac->t_rp, ac->t_ras, ac->t_rcd);
+ writel(actime, ®s->actime2);
+
+ actime = ACTIME3(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr,
+ ac->t_cl - ac->t_cwl + (ac->t_bl / 2) + 2,
+ ac->t_cwl + ac->t_bl / 2 + ac->t_wtp,
+ ac->t_rtp);
+ writel(actime, ®s->actime3);
+
+ actime = ACTIME4(ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_a,
+ ac->t_cwl + ac->t_bl / 2 + ac->t_wtr_l);
+ writel(actime, ®s->actime4);
+
+ actime = ACTIME5(ac->t_refsbrd, ac->t_rfcsb, ac->t_rfc);
+ writel(actime, ®s->actime5);
+
+ actime = ACTIME6(ac->t_cshsr, ac->t_pd, ac->t_xp, ac->t_cksre);
+ writel(actime, ®s->actime6);
+
+ actime = ACTIME7(ac->t_zq, ac->t_dllk);
+ writel(actime, ®s->actime7);
+}
+
+static void sdrammc_config_registers(struct sdrammc *sdrammc)
+{
+ const struct sdrammc_ac_timing *ac = sdrammc->ac;
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 reg;
+
+ u32 dram_size = 5;
+ u32 t_phy_wrdata;
+ u32 t_phy_wrlat;
+ u32 t_phy_rddata_en;
+ u32 t_phy_odtlat;
+ u32 t_phy_odtext;
+
+ if (IS_DDR4(sdrammc->type)) {
+ t_phy_wrlat = ac->t_cwl - 5 - 4;
+ t_phy_rddata_en = ac->t_cl - 5 - 4;
+ t_phy_wrdata = 2;
+ t_phy_odtlat = ac->t_cwl - 5 - 4;
+ t_phy_odtext = 0;
+ } else {
+ t_phy_wrlat = ac->t_cwl - 13 - 3;
+ t_phy_rddata_en = ac->t_cl - 13 - 3;
+ t_phy_wrdata = 6;
+ t_phy_odtlat = 0;
+ t_phy_odtext = 0;
+ }
+
+ writel(0x20 + (dram_size << 2) + !!!IS_DDR4(sdrammc->type), ®s->mcfg);
+
+ reg = (t_phy_odtext << 20) + (t_phy_odtlat << 16) +
+ (t_phy_rddata_en << 10) + (t_phy_wrdata << 6) +
+ t_phy_wrlat;
+ writel(reg, ®s->dfi_timing);
+ writel(0, ®s->dctl);
+
+ writel(0x40b48200, ®s->refctl);
+
+ writel(0x42aa1800, ®s->zqctl);
+
+ writel(0, ®s->arbctl);
+
+ if (!IS_DDR4(sdrammc->type))
+ writel(0, ®s->refmng_ctl);
+
+ writel(0xffffffff, ®s->intr_mask);
+}
+
+static void sdrammc_init(struct sdrammc *sdrammc)
+{
+ u32 reg;
+
+ reg = readl(sdrammc->scu1 + SCU1_HWSTRAP1);
+
+ if (reg & SCU1_HWSTRAP1_DDR4) {
+ if (IS_ENABLED(CONFIG_ASPEED_DDR_1600))
+ sdrammc->type = DDR4_1600;
+ else if (IS_ENABLED(CONFIG_ASPEED_DDR_2400))
+ sdrammc->type = DDR4_2400;
+ else if (IS_ENABLED(CONFIG_ASPEED_DDR_3200))
+ sdrammc->type = DDR4_3200;
+ } else {
+ sdrammc->type = DDR5_3200;
+ }
+
+ sdrammc->ac = &ac_table[sdrammc->type];
+
+ sdrammc_config_ac_timing(sdrammc);
+ sdrammc_config_registers(sdrammc);
+}
+
+static int ast2700_sdrammc_probe(struct udevice *dev)
+{
+ struct sdrammc *sdrammc = dev_get_priv(dev);
+ struct sdrammc_regs *regs = sdrammc->regs;
+ u32 bistcfg;
+ u32 reg;
+ int rc;
+
+ /* skip DRAM init if already done */
+ reg = readl(sdrammc->scu0 + SCU0_VGA0_SCRATCH);
+ if (reg & SCU0_VGA0_SCRATCH_DRAM_INIT)
+ goto out;
+
+ /* unlock DRAM controller */
+ writel(DRAMC_UNLK_KEY, ®s->prot_key);
+
+ sdrammc_init(sdrammc);
+
+ sdrammc_dwc_phy_init(sdrammc);
+
+ sdrammc_exit_self_refresh(sdrammc);
+
+ sdrammc_config_mrs(sdrammc);
+
+ sdrammc_enable_refresh(sdrammc);
+
+ bistcfg = FIELD_PREP(DRAMC_BISTCFG_PMODE, BIST_PMODE_CRC) |
+ FIELD_PREP(DRAMC_BISTCFG_BMODE, BIST_BMODE_RW_SWITCH) |
+ DRAMC_BISTCFG_ENABLE;
+
+ rc = sdrammc_bist(sdrammc, 0, 0x10000, bistcfg, 0x200000);
+ if (rc) {
+ debug("bist test failed, type=%d\n", sdrammc->type);
+ return rc;
+ }
+
+ /* set DRAM init flag */
+ reg |= SCU0_VGA0_SCRATCH_DRAM_INIT;
+ writel(reg, sdrammc->scu0 + SCU0_VGA0_SCRATCH);
+
+out:
+ sdrammc_calc_size(sdrammc);
+
+ return 0;
+}
+
+static int ast2700_sdrammc_of_to_plat(struct udevice *dev)
+{
+ struct sdrammc *sdrammc = dev_get_priv(dev);
+ u32 phandle;
+ ofnode node;
+ int rc;
+
+ sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0);
+ if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map DRAM register\n");
+ return -ENODEV;
+ }
+
+ sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1);
+ if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map PHY memory\n");
+ return -ENODEV;
+ }
+
+ rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu0", &phandle);
+ if (rc) {
+ debug("cannot find SCU0 handle\n");
+ return -ENODEV;
+ }
+
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ debug("cannot get SCU0 node\n");
+ return -ENODEV;
+ }
+
+ sdrammc->scu0 = (void *)ofnode_get_addr(node);
+ if (sdrammc->scu0 == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map SCU0 register\n");
+ return -ENODEV;
+ }
+
+ rc = ofnode_read_u32(dev_ofnode(dev), "aspeed,scu1", &phandle);
+ if (rc) {
+ debug("cannot find SCU1 handle\n");
+ return -ENODEV;
+ }
+
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node)) {
+ debug("cannot get SCU1 node\n");
+ return -ENODEV;
+ }
+
+ sdrammc->scu1 = (void *)ofnode_get_addr(node);
+ if (sdrammc->scu1 == (void *)FDT_ADDR_T_NONE) {
+ debug("cannot map SCU1 register\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int ast2700_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct sdrammc *sdrammc = dev_get_priv(dev);
+
+ *info = sdrammc->info;
+
+ return 0;
+}
+
+static struct ram_ops ast2700_sdrammc_ops = {
+ .get_info = ast2700_sdrammc_get_info,
+};
+
+static const struct udevice_id ast2700_sdrammc_ids[] = {
+ { .compatible = "aspeed,ast2700-sdrammc" },
+ { }
+};
+
+U_BOOT_DRIVER(sdrammc_ast2700) = {
+ .name = "aspeed_ast2700_sdrammc",
+ .id = UCLASS_RAM,
+ .of_match = ast2700_sdrammc_ids,
+ .ops = &ast2700_sdrammc_ops,
+ .of_to_plat = ast2700_sdrammc_of_to_plat,
+ .probe = ast2700_sdrammc_probe,
+ .priv_auto = sizeof(struct sdrammc),
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
index 11ef242..9f9abfe 100644
--- a/drivers/ram/k3-ddrss/lpddr4.c
+++ b/drivers/ram/k3-ddrss/lpddr4.c
@@ -155,10 +155,11 @@
u32 result = 0U;
result = lpddr4_startsf(pd);
- if (result == (u32)0) {
+ if (result == (u32)0)
result = lpddr4_enablepiinitiator(pd);
+ if (result == (u32)0)
result = lpddr4_startsequencecontroller(pd);
- }
+
return result;
}
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index e64354d..3233ff8 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -158,9 +158,19 @@
uc_pdata->driver_plat_data = pdata->driver_plat_data;
}
- /* Else try using device Name */
- if (!uc_pdata->name)
- uc_pdata->name = dev->name;
+ /* Else try using a combination of device Name and devices's parent's name */
+ if (!uc_pdata->name) {
+ /* 2 in the rproc_name_size indicates 1 for null and one for '-' */
+ int rproc_name_size = strlen(dev->name) + strlen(dev->parent->name) + 2;
+ char *buf;
+
+ buf = malloc(rproc_name_size);
+ if (!buf)
+ return -ENOMEM;
+
+ snprintf(buf, rproc_name_size, "%s-%s", dev->name, dev->parent->name);
+ uc_pdata->name = buf;
+ }
if (!uc_pdata->name) {
debug("Unnamed device!");
return -EINVAL;
diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
index 08736ea..67be18e 100644
--- a/drivers/soc/qcom/cmd-db.c
+++ b/drivers/soc/qcom/cmd-db.c
@@ -6,6 +6,7 @@
#define pr_fmt(fmt) "cmd-db: " fmt
+#include <asm/system.h>
#include <dm.h>
#include <dm/ofnode.h>
#include <dm/device_compat.h>
@@ -141,7 +142,7 @@
ent = rsc_to_entry_header(rsc_hdr);
for (j = 0; j < le16_to_cpu(rsc_hdr->cnt); j++, ent++) {
- if (memcmp(ent->id, query, sizeof(ent->id)) == 0) {
+ if (strncmp(ent->id, query, sizeof(ent->id)) == 0) {
if (eh)
*eh = ent;
if (rh)
@@ -182,9 +183,10 @@
}
EXPORT_SYMBOL_GPL(cmd_db_read_addr);
-int cmd_db_bind(struct udevice *dev)
+static int cmd_db_bind(struct udevice *dev)
{
void __iomem *base;
+ fdt_size_t size;
ofnode node;
if (cmd_db_header)
@@ -194,12 +196,15 @@
debug("%s(%s)\n", __func__, ofnode_get_name(node));
- base = (void __iomem *)ofnode_get_addr(node);
+ base = (void __iomem *)ofnode_get_addr_size(node, "reg", &size);
if ((fdt_addr_t)base == FDT_ADDR_T_NONE) {
log_err("%s: Failed to read base address\n", __func__);
return -ENOENT;
}
+ /* On SM8550/SM8650 and newer SoCs cmd-db might not be mapped */
+ mmu_map_region((phys_addr_t)base, (phys_size_t)size, false);
+
cmd_db_header = base;
if (!cmd_db_magic_matches(cmd_db_header)) {
log_err("%s: Invalid Command DB Magic\n", __func__);
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 61fb2e6..aee9e55 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -294,6 +294,48 @@
}
/**
+ * __tcs_set_trigger() - Start xfer on a TCS or unset trigger on a borrowed TCS
+ * @drv: The controller.
+ * @tcs_id: The global ID of this TCS.
+ * @trigger: If true then untrigger/retrigger. If false then just untrigger.
+ *
+ * In the normal case we only ever call with "trigger=true" to start a
+ * transfer. That will un-trigger/disable the TCS from the last transfer
+ * then trigger/enable for this transfer.
+ *
+ * If we borrowed a wake TCS for an active-only transfer we'll also call
+ * this function with "trigger=false" to just do the un-trigger/disable
+ * before using the TCS for wake purposes again.
+ *
+ * Note that the AP is only in charge of triggering active-only transfers.
+ * The AP never triggers sleep/wake values using this function.
+ */
+static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger)
+{
+ u32 enable;
+ u32 reg = drv->regs[RSC_DRV_CONTROL];
+
+ /*
+ * HW req: Clear the DRV_CONTROL and enable TCS again
+ * While clearing ensure that the AMC mode trigger is cleared
+ * and then the mode enable is cleared.
+ */
+ enable = read_tcs_reg(drv, reg, tcs_id);
+ enable &= ~TCS_AMC_MODE_TRIGGER;
+ write_tcs_reg_sync(drv, reg, tcs_id, enable);
+ enable &= ~TCS_AMC_MODE_ENABLE;
+ write_tcs_reg_sync(drv, reg, tcs_id, enable);
+
+ if (trigger) {
+ /* Enable the AMC mode on the TCS and then trigger the TCS */
+ enable = TCS_AMC_MODE_ENABLE;
+ write_tcs_reg_sync(drv, reg, tcs_id, enable);
+ enable |= TCS_AMC_MODE_TRIGGER;
+ write_tcs_reg(drv, reg, tcs_id, enable);
+ }
+}
+
+/**
* rpmh_rsc_send_data() - Write / trigger active-only message.
* @drv: The controller.
* @msg: The data to be sent.
@@ -348,6 +390,7 @@
* of __tcs_set_trigger() below.
*/
__tcs_buffer_write(drv, tcs_id, 0, msg);
+ __tcs_set_trigger(drv, tcs_id, true);
/* U-Boot: Now wait for the TCS to be cleared, indicating that we're done */
for (i = 0; i < USEC_PER_SEC; i++) {
diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
index f958239..8227d8b 100644
--- a/drivers/soc/ti/k3-navss-ringacc-u-boot.c
+++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
@@ -25,9 +25,16 @@
#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24)
#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24)
+#define KNAV_RINGACC_CFG_RING_SIZE_MASK GENMASK(19, 0)
+
static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
{
- writel(0, &ring->cfg->size);
+ u32 reg;
+
+ reg = readl(&ring->cfg->size);
+ reg &= ~KNAV_RINGACC_CFG_RING_SIZE_MASK;
+ reg |= ring->size;
+ writel(reg, &ring->cfg->size);
}
static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
@@ -35,7 +42,7 @@
u32 val;
val = readl(&ring->cfg->size);
- val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
+ val &= ~KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
writel(val, &ring->cfg->size);
}
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index b2643a3..14114a6 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -1028,8 +1028,8 @@
struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
struct k3_ringacc_init_data *data)
{
+ void __iomem *base_rt, *base_cfg;
struct k3_nav_ringacc *ringacc;
- void __iomem *base_rt;
int i;
ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
@@ -1047,6 +1047,20 @@
if (!base_rt)
return ERR_PTR(-EINVAL);
+ /*
+ * Since register property is defined as "ring" for PKTDMA and
+ * "cfg" for UDMA, configure base address of ring configuration
+ * register accordingly.
+ */
+ base_cfg = dev_remap_addr_name(dev, "ring");
+ pr_debug("ring %p\n", base_cfg);
+ if (!base_cfg) {
+ base_cfg = dev_remap_addr_name(dev, "cfg");
+ pr_debug("cfg %p\n", base_cfg);
+ if (!base_cfg)
+ return ERR_PTR(-EINVAL);
+ }
+
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
ringacc->num_rings * 2,
@@ -1061,6 +1075,7 @@
for (i = 0; i < ringacc->num_rings; i++) {
struct k3_nav_ring *ring = &ringacc->rings[i];
+ ring->cfg = base_cfg + KNAV_RINGACC_CFG_REGS_STEP * i;
ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
ring->parent = ringacc;
ring->ring_id = i;
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index e6b602c..f1e6f9f 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,6 +145,12 @@
#define RPC_PHYCNT_WBUF BIT(2)
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
+#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
+#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+
+#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
+#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+
#define RPC_PHYINT 0x0088 /* R/W */
#define RPC_PHYINT_RSTEN BIT(18)
#define RPC_PHYINT_WPEN BIT(17)
@@ -227,6 +233,12 @@
struct udevice *bus = dev->parent;
struct rpc_spi_priv *priv = dev_get_priv(bus);
+ setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
+ RPCIF_PHYOFFSET1_DDRTMG(3));
+ clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
+ RPCIF_PHYOFFSET2_OCTTMG(7),
+ RPCIF_PHYOFFSET2_OCTTMG(4));
+
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
priv->regs + RPC_PHYCNT);
@@ -277,24 +289,24 @@
writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
smenr |= RPC_DRENR_CDE;
- writel(0, priv->regs + RPC_DREAR);
if (op->addr.nbytes == 4) {
writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0xF);
} else if (op->addr.nbytes == 3) {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0x7);
} else {
+ writel(0, priv->regs + RPC_DREAR);
smenr |= RPC_DRENR_ADE(0);
}
- writel(0, priv->regs + RPC_DRDMCR);
- if (op->dummy.nbytes) {
- writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
+ if (op->dummy.nbytes)
smenr |= RPC_DRENR_DME;
- }
+ writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
writel(0, priv->regs + RPC_DROPR);
+ writel(0, priv->regs + RPC_DRDRENR);
writel(smenr, priv->regs + RPC_DRENR);
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
@@ -453,6 +465,7 @@
static const struct udevice_id rpc_spi_ids[] = {
{ .compatible = "renesas,r7s72100-rpc-if" },
{ .compatible = "renesas,rcar-gen3-rpc-if" },
+ { .compatible = "renesas,rcar-gen4-rpc-if" },
{ }
};
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index 9bdb4a5..a8ec2f4 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -237,6 +237,18 @@
return 0;
}
+static int retrieve_num_chipselects(struct udevice *dev)
+{
+ int chipselects;
+ int ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "num-chipselects", &chipselects);
+ if (ret)
+ return ret;
+
+ return chipselects;
+}
+
static int soft_spi_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
@@ -249,7 +261,15 @@
ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
GPIOD_IS_OUT | cs_flags);
- if (ret)
+ /*
+ * If num-chipselects is zero we're ignoring absence of cs-gpios. This
+ * code relies on the fact that `gpio_request_by_name` call above
+ * initiailizes plat->cs to correct value with invalid GPIO even when
+ * there is no cs-gpios node in dts. All other functions which work
+ * with plat->cs verify it via `dm_gpio_is_valid` before using it, so
+ * such value doesn't cause any problems.
+ */
+ if (ret && retrieve_num_chipselects(dev) != 0)
return -EINVAL;
ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
@@ -271,7 +291,7 @@
ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
GPIOD_IS_IN);
if (ret)
- ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+ ret = gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso,
GPIOD_IS_IN);
if (ret)
plat->flags |= SPI_MASTER_NO_RX;
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6b1de82..cb6fc0e 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -106,6 +106,12 @@
This is mostly because they all share several registers which
makes it difficult to completely separate them.
+config AST_IBEX_TIMER
+ bool "Aspeed ast2700 Ibex timer"
+ depends on TIMER
+ help
+ Select this to enable a timer support for the Ibex RV32-based MCUs in AST2700.
+
config ATCPIT100_TIMER
bool "ATCPIT100 timer support"
depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fb95c88..fec4af3 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
+obj-$(CONFIG_AST_IBEX_TIMER) += ast_ibex_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
diff --git a/drivers/timer/ast_ibex_timer.c b/drivers/timer/ast_ibex_timer.c
new file mode 100644
index 0000000..2618396
--- /dev/null
+++ b/drivers/timer/ast_ibex_timer.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Aspeed Technology Inc.
+ */
+
+#include <asm/csr.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+
+#define CSR_MCYCLE 0xb00
+#define CSR_MCYCLEH 0xb80
+
+static u64 ast_ibex_timer_get_count(struct udevice *dev)
+{
+ uint32_t cnt_l, cnt_h;
+
+ cnt_l = csr_read(CSR_MCYCLE);
+ cnt_h = csr_read(CSR_MCYCLEH);
+
+ return ((uint64_t)cnt_h << 32) | cnt_l;
+}
+
+static int ast_ibex_timer_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct timer_ops ast_ibex_timer_ops = {
+ .get_count = ast_ibex_timer_get_count,
+};
+
+static const struct udevice_id ast_ibex_timer_ids[] = {
+ { .compatible = "aspeed,ast2700-ibex-timer" },
+ { }
+};
+
+U_BOOT_DRIVER(ast_ibex_timer) = {
+ .name = "ast_ibex_timer",
+ .id = UCLASS_TIMER,
+ .of_match = ast_ibex_timer_ids,
+ .probe = ast_ibex_timer_probe,
+ .ops = &ast_ibex_timer_ops,
+};
diff --git a/drivers/timer/npcm-timer.c b/drivers/timer/npcm-timer.c
index 9463fd2..5627c23 100644
--- a/drivers/timer/npcm-timer.c
+++ b/drivers/timer/npcm-timer.c
@@ -3,93 +3,53 @@
* Copyright (c) 2022 Nuvoton Technology Corp.
*/
-#include <clk.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
-#define NPCM_TIMER_CLOCK_RATE 1000000UL /* 1MHz timer */
-#define NPCM_TIMER_INPUT_RATE 25000000UL /* Rate of input clock */
-#define NPCM_TIMER_TDR_MASK GENMASK(23, 0)
-#define NPCM_TIMER_MAX_VAL NPCM_TIMER_TDR_MASK /* max counter value */
+#define NPCM_TIMER_CLOCK_RATE 25000000UL /* 25MHz */
/* Register offsets */
-#define TCR0 0x0 /* Timer Control and Status Register */
-#define TICR0 0x8 /* Timer Initial Count Register */
-#define TDR0 0x10 /* Timer Data Register */
+#define SECCNT 0x0 /* Seconds Counter Register */
+#define CNTR25M 0x4 /* 25MHz Counter Register */
-/* TCR fields */
-#define TCR_MODE_PERIODIC BIT(27)
-#define TCR_EN BIT(30)
-#define TCR_PRESCALE (NPCM_TIMER_INPUT_RATE / NPCM_TIMER_CLOCK_RATE - 1)
-
-enum input_clock_type {
- INPUT_CLOCK_FIXED, /* input clock rate is fixed */
- INPUT_CLOCK_NON_FIXED
-};
-
-/**
- * struct npcm_timer_priv - private data for npcm timer driver
- * npcm timer is a 24-bits down-counting timer.
- *
- * @last_count: last hw counter value
- * @counter: the value to be returned for get_count ops
- */
struct npcm_timer_priv {
void __iomem *base;
- u32 last_count;
- u64 counter;
};
static u64 npcm_timer_get_count(struct udevice *dev)
{
struct npcm_timer_priv *priv = dev_get_priv(dev);
- u32 val;
+ u64 reg_sec, reg_25m;
+ u64 counter;
- /* The timer is counting down */
- val = readl(priv->base + TDR0) & NPCM_TIMER_TDR_MASK;
- if (val <= priv->last_count)
- priv->counter += priv->last_count - val;
- else
- priv->counter += priv->last_count + (NPCM_TIMER_MAX_VAL + 1 - val);
- priv->last_count = val;
+ reg_sec = readl(priv->base + SECCNT);
+ reg_25m = readl(priv->base + CNTR25M);
+ /*
+ * When CNTR25M reaches 25M, it goes to 0 and SECCNT is increased by 1.
+ * When CNTR25M is zero, wait for CNTR25M to become non-zero in case
+ * SECCNT is not updated yet.
+ */
+ if (reg_25m == 0) {
+ while (reg_25m == 0)
+ reg_25m = readl(priv->base + CNTR25M);
+ reg_sec = readl(priv->base + SECCNT);
+ }
+ counter = reg_sec * NPCM_TIMER_CLOCK_RATE + reg_25m;
- return priv->counter;
+ return counter;
}
static int npcm_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct npcm_timer_priv *priv = dev_get_priv(dev);
- enum input_clock_type type = dev_get_driver_data(dev);
- struct clk clk;
- int ret;
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
- if (type == INPUT_CLOCK_NON_FIXED) {
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
-
- ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
- if (ret < 0)
- return ret;
- }
-
- /*
- * Configure timer and start
- * periodic mode
- * timer clock rate = input clock / prescale
- */
- writel(0, priv->base + TCR0);
- writel(NPCM_TIMER_MAX_VAL, priv->base + TICR0);
- writel(TCR_EN | TCR_MODE_PERIODIC | TCR_PRESCALE,
- priv->base + TCR0);
-
return 0;
}
@@ -98,8 +58,8 @@
};
static const struct udevice_id npcm_timer_ids[] = {
- { .compatible = "nuvoton,npcm845-timer", .data = INPUT_CLOCK_FIXED},
- { .compatible = "nuvoton,npcm750-timer", .data = INPUT_CLOCK_NON_FIXED},
+ { .compatible = "nuvoton,npcm845-timer"},
+ { .compatible = "nuvoton,npcm750-timer"},
{}
};
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index a972d87..311aaa7 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -99,7 +99,8 @@
config USB_KEYBOARD
bool "USB Keyboard support"
- select DM_KEYBOARD if DM_USB
+ depends on DM_USB
+ select DM_KEYBOARD
select SYS_STDIO_DEREGISTER
---help---
Say Y here if you want to use a USB keyboard for U-Boot command line
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index 32b2c41..ac7e469 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -965,6 +965,12 @@
if (priv_dev->dev_ver <= DEV_VER_V2)
cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
+ /* Flush TRBs */
+ flush_dcache_range((unsigned long)priv_ep->trb_pool,
+ (unsigned long)priv_ep->trb_pool +
+ ROUND(sizeof(struct cdns3_trb) * priv_ep->num_trbs,
+ CONFIG_SYS_CACHELINE_SIZE));
+
trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
/*
@@ -1153,6 +1159,13 @@
priv_ep->endpoint.desc->bEndpointAddress);
#endif
+ /* Invalidate TRBs */
+ invalidate_dcache_range((unsigned long)priv_ep->trb_pool,
+ (unsigned long)priv_ep->trb_pool +
+ ROUND(sizeof(struct cdns3_trb) *
+ priv_ep->num_trbs,
+ CONFIG_SYS_CACHELINE_SIZE));
+
if (!cdns3_request_handled(priv_ep, priv_req))
goto prepare_next_td;
diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index 24420e3..b5176bb 100644
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -196,7 +196,7 @@
priv->fd != -1) {
offset = os_lseek(priv->fd, info->seek_block * info->block_size,
OS_SEEK_SET);
- if (offset == (off_t)-1)
+ if (offset < 0)
setup_fail_response(priv);
else
setup_response(priv);
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 4621a6f..f20a16e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -323,7 +323,8 @@
bool "Support DFU (Device Firmware Upgrade) in SPL"
select SPL_HASH
select SPL_DFU_NO_RESET
- depends on SPL_RAM_SUPPORT
+ select SPL_RAM_SUPPORT
+ depends on DFU_OVER_USB
help
This feature enables the DFU (Device Firmware Upgrade) in SPL with
RAM memory device support. The ROM code will load and execute
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f99553d..a77037a 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -7,16 +7,28 @@
* Bo Shen <voice.shen@atmel.com>
*/
-#include <linux/bitops.h>
-#include <linux/errno.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
#include <linux/list.h>
-#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/atmel_usba_udc.h>
-#include <malloc.h>
+
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+#include <mach/atmel_usba_udc.h>
+
+static int usba_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver);
+static int usba_udc_stop(struct usb_gadget *gadget);
+#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
#include "atmel_usba_udc.h"
@@ -506,10 +518,32 @@
return 0;
}
+static int usba_udc_pullup(struct usb_gadget *gadget, int is_on)
+{
+ struct usba_udc *udc = to_usba_udc(gadget);
+ u32 ctrl;
+
+ ctrl = usba_readl(udc, CTRL);
+
+ if (is_on)
+ ctrl &= ~USBA_DETACH;
+ else
+ ctrl |= USBA_DETACH;
+
+ usba_writel(udc, CTRL, ctrl);
+
+ return 0;
+}
+
static const struct usb_gadget_ops usba_udc_ops = {
.get_frame = usba_udc_get_frame,
.wakeup = usba_udc_wakeup,
.set_selfpowered = usba_udc_set_selfpowered,
+ .pullup = usba_udc_pullup,
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ .udc_start = usba_udc_start,
+ .udc_stop = usba_udc_stop,
+#endif
};
static struct usb_endpoint_descriptor usba_ep0_desc = {
@@ -1153,7 +1187,7 @@
return 0;
}
-static int atmel_usba_start(struct usba_udc *udc)
+static int usba_udc_enable(struct usba_udc *udc)
{
udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
@@ -1168,7 +1202,7 @@
return 0;
}
-static int atmel_usba_stop(struct usba_udc *udc)
+static int usba_udc_disable(struct usba_udc *udc)
{
udc->gadget.speed = USB_SPEED_UNKNOWN;
reset_all_endpoints(udc);
@@ -1179,6 +1213,47 @@
return 0;
}
+static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata,
+ struct usba_udc *udc)
+{
+ struct usba_ep *eps;
+ int i;
+
+ eps = malloc(sizeof(struct usba_ep) * pdata->num_ep);
+ if (!eps) {
+ log_err("failed to alloc eps\n");
+ return NULL;
+ }
+
+ udc->gadget.ep0 = &eps[0].ep;
+
+ INIT_LIST_HEAD(&udc->gadget.ep_list);
+ INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+ for (i = 0; i < pdata->num_ep; i++) {
+ struct usba_ep *ep = &eps[i];
+
+ ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+ ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+ ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+ ep->ep.ops = &usba_ep_ops;
+ ep->ep.name = pdata->ep[i].name;
+ ep->ep.maxpacket = pdata->ep[i].fifo_size;
+ ep->fifo_size = ep->ep.maxpacket;
+ ep->udc = udc;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->nr_banks = pdata->ep[i].nr_banks;
+ ep->index = pdata->ep[i].index;
+ ep->can_dma = pdata->ep[i].can_dma;
+ ep->can_isoc = pdata->ep[i].can_isoc;
+ if (i)
+ list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+ };
+
+ return eps;
+}
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
static struct usba_udc controller = {
.regs = (unsigned *)ATMEL_BASE_UDPHS,
.fifo = (unsigned *)ATMEL_BASE_UDPHS_FIFO,
@@ -1204,22 +1279,22 @@
int ret;
if (!driver || !driver->bind || !driver->setup) {
- printf("bad paramter\n");
+ log_err("bad parameter\n");
return -EINVAL;
}
if (udc->driver) {
- printf("UDC already has a gadget driver\n");
+ log_err("UDC already has a gadget driver\n");
return -EBUSY;
}
- atmel_usba_start(udc);
+ usba_udc_enable(udc);
udc->driver = driver;
ret = driver->bind(&udc->gadget);
if (ret) {
- pr_err("driver->bind() returned %d\n", ret);
+ log_err("driver->bind() returned %d\n", ret);
udc->driver = NULL;
}
@@ -1231,7 +1306,7 @@
struct usba_udc *udc = &controller;
if (!driver || !driver->unbind || !driver->disconnect) {
- pr_err("bad paramter\n");
+ log_err("bad parameter\n");
return -EINVAL;
}
@@ -1239,58 +1314,145 @@
driver->unbind(&udc->gadget);
udc->driver = NULL;
- atmel_usba_stop(udc);
+ usba_udc_disable(udc);
return 0;
}
-static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata,
- struct usba_udc *udc)
+int usba_udc_probe(struct usba_platform_data *pdata)
{
- struct usba_ep *eps;
- int i;
+ struct usba_udc *udc;
- eps = malloc(sizeof(struct usba_ep) * pdata->num_ep);
- if (!eps) {
- pr_err("failed to alloc eps\n");
- return NULL;
- }
+ udc = &controller;
- udc->gadget.ep0 = &eps[0].ep;
+ udc->usba_ep = usba_udc_pdata(pdata, udc);
- INIT_LIST_HEAD(&udc->gadget.ep_list);
- INIT_LIST_HEAD(&eps[0].ep.ep_list);
+ return 0;
+}
- for (i = 0; i < pdata->num_ep; i++) {
- struct usba_ep *ep = &eps[i];
+#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+struct usba_priv_data {
+ struct clk_bulk clks;
+ struct usba_udc udc;
+};
- ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
- ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
- ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
- ep->ep.ops = &usba_ep_ops;
- ep->ep.name = pdata->ep[i].name;
- ep->ep.maxpacket = pdata->ep[i].fifo_size;
- ep->fifo_size = ep->ep.maxpacket;
- ep->udc = udc;
- INIT_LIST_HEAD(&ep->queue);
- ep->nr_banks = pdata->ep[i].nr_banks;
- ep->index = pdata->ep[i].index;
- ep->can_dma = pdata->ep[i].can_dma;
- ep->can_isoc = pdata->ep[i].can_isoc;
- if (i)
- list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
- };
+static int usba_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver)
+{
+ struct usba_udc *udc = to_usba_udc(gadget);
- return eps;
+ usba_udc_enable(udc);
+
+ udc->driver = driver;
+ return 0;
}
-int usba_udc_probe(struct usba_platform_data *pdata)
+static int usba_udc_stop(struct usb_gadget *gadget)
{
- struct usba_udc *udc;
+ struct usba_udc *udc = to_usba_udc(gadget);
- udc = &controller;
+ udc->driver = NULL;
- udc->usba_ep = usba_udc_pdata(pdata, udc);
+ usba_udc_disable(udc);
+ return 0;
+}
+
+static int usba_udc_clk_init(struct udevice *dev, struct clk_bulk *clks)
+{
+ int ret;
+
+ ret = clk_get_bulk(dev, clks);
+ if (ret == -ENOSYS)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(clks);
+ if (ret) {
+ clk_release_bulk(clks);
+ return ret;
+ }
return 0;
}
+
+static int usba_udc_probe(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+ struct usba_udc *udc = &priv->udc;
+ int ret;
+
+ udc->fifo = (void __iomem *)dev_remap_addr_index(dev, FIFO_IOMEM_ID);
+ if (!udc->fifo)
+ return -EINVAL;
+
+ udc->regs = (void __iomem *)dev_remap_addr_index(dev, CTRL_IOMEM_ID);
+ if (!udc->regs)
+ return -EINVAL;
+
+ ret = usba_udc_clk_init(dev, &priv->clks);
+ if (ret)
+ return ret;
+
+ udc->usba_ep = usba_udc_pdata(&pdata, udc);
+
+ udc->gadget.ops = &usba_udc_ops;
+ udc->gadget.speed = USB_SPEED_HIGH,
+ udc->gadget.is_dualspeed = 1,
+ udc->gadget.name = "atmel_usba_udc",
+
+ ret = usb_add_gadget_udc((struct device *)dev, &udc->gadget);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ free(udc->usba_ep);
+
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static int usba_udc_remove(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+
+ usb_del_gadget_udc(&priv->udc.gadget);
+
+ free(priv->udc.usba_ep);
+
+ clk_release_bulk(&priv->clks);
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static int usba_udc_handle_interrupts(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+
+ return usba_udc_irq(&priv->udc);
+}
+
+static const struct usb_gadget_generic_ops usba_udc_gadget_ops = {
+ .handle_interrupts = usba_udc_handle_interrupts,
+};
+
+static const struct udevice_id usba_udc_ids[] = {
+ { .compatible = "atmel,at91sam9rl-udc" },
+ { .compatible = "atmel,at91sam9g45-udc" },
+ { .compatible = "atmel,sama5d3-udc" },
+ {}
+};
+
+U_BOOT_DRIVER(atmel_usba_udc) = {
+ .name = "atmel_usba_udc",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_match = usba_udc_ids,
+ .ops = &usba_udc_gadget_ops,
+ .probe = usba_udc_probe,
+ .remove = usba_udc_remove,
+ .priv_auto = sizeof(struct usba_priv_data),
+};
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index f6cb48c..7f5e98f 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -211,6 +211,9 @@
#define EP0_EPT_SIZE USBA_EPT_SIZE_64
#define EP0_NR_BANKS 1
+#define FIFO_IOMEM_ID 0
+#define CTRL_IOMEM_ID 1
+
#define DBG_ERR 0x0001 /* report all error returns */
#define DBG_HW 0x0002 /* debug hardware initialization */
#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index 514c097..5d62eb4 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -842,9 +842,7 @@
struct spl_load_info load;
debug("Found FIT\n");
- load.priv = header;
- spl_set_bl_len(&load, 1);
- load.read = sdp_load_read;
+ spl_load_init(&load, sdp_load_read, header, 1);
spl_load_simple_fit(spl_image, &load, 0,
header);
@@ -855,9 +853,7 @@
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- load.priv = header;
- spl_set_bl_len(&load, 1);
- load.read = sdp_load_read;
+ spl_load_init(&load, sdp_load_read, header, 1);
spl_load_imx_container(spl_image, &load, 0);
return SDP_EXIT;
}
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index fbe62bb..723d1cd 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -83,7 +83,7 @@
#if CONFIG_IS_ENABLED(DM)
UCLASS_DRIVER(usb_gadget_generic) = {
.id = UCLASS_USB_GADGET_GENERIC,
- .name = "usb",
+ .name = "usb_gadget",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
#endif
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 23c3ed2..1ae3619 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -94,7 +94,7 @@
if (err)
goto reset_err;
- err = generic_setup_phy(dev, &priv->phy, 0);
+ err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0);
if (err)
goto regulator_err;
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index ff33608..a759aea 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -80,7 +80,7 @@
hcor = (struct ehci_hcor *)((phys_addr_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
- ret = generic_setup_phy(dev, &p->phy, 0);
+ ret = generic_setup_phy(dev, &p->phy, 0, PHY_MODE_USB_HOST, 0);
if (ret)
goto cleanup_iface;
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 44912de..d8f521b 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -79,6 +79,10 @@
/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#ifndef CFG_MXC_USB_PORTSC
+#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
int mxc_set_usbcontrol(int port, unsigned int flags)
{
unsigned int v;
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 31cd8a5..a93fa5d 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -703,7 +703,7 @@
usb_phy_enable(ehci, priv->phy_addr);
#endif
#else
- ret = generic_setup_phy(dev, &priv->phy, 0);
+ ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0);
if (ret)
goto err_regulator;
#endif
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 5726865..8d05b14 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -30,7 +30,7 @@
int ret;
u32 cmd;
- ret = generic_setup_phy(dev, &priv->phy, 0);
+ ret = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0);
if (ret)
return ret;
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index f1325cd..cc44226 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -50,7 +50,7 @@
goto reset_err;
}
- err = generic_setup_phy(dev, &priv->phy, 0);
+ err = generic_setup_phy(dev, &priv->phy, 0, PHY_MODE_USB_HOST, 0);
if (err)
goto reset_err;
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index ed04cae..bf89bf8 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -94,10 +94,6 @@
static void isp1301_configure(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_set_bus_num(I2C_2);
-#endif
-
/*
* LPC32XX only supports DAT_SE0 USB mode
* This sequence is important
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
index 039b220..fdeb3ca 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -403,7 +403,6 @@
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
- gd->fb_base = fbi->fix.smem_start;
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
@@ -633,7 +632,6 @@
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
- gd->fb_base = fb_start;
return 0;
}
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 792d631..e72839c 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -335,7 +335,6 @@
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
- gd->fb_base = plat->base;
return ret;
}
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index a5aa8dd..41bb764 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -145,13 +145,26 @@
*addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE);
gd->video_bottom = *addrp;
- gd->fb_base = *addrp;
debug("Video frame buffers from %lx to %lx\n", gd->video_bottom,
gd->video_top);
return 0;
}
+ulong video_get_fb(void)
+{
+ struct udevice *dev;
+
+ uclass_find_first_device(UCLASS_VIDEO, &dev);
+ if (dev) {
+ const struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ return uc_plat->base;
+ }
+
+ return 0;
+}
+
int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend,
int yend, u32 colour)
{
@@ -210,7 +223,6 @@
return -ENOENT;
gd->video_bottom = ho->fb;
- gd->fb_base = ho->fb;
gd->video_top = ho->fb + ho->size;
debug("%s: Reserving %lx bytes at %08x as per bloblist received\n",
__func__, (unsigned long)ho->size, (u32)ho->fb);
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
index 1405b29..76abfea 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -49,7 +49,7 @@
DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
(upper_32_bits((u64)&cur_desc)));
cur_desc.next_desr = lower_32_bits((u64)&cur_desc);
- cur_desc.src_addr = lower_32_bits((u64)gd->fb_base);
+ cur_desc.src_addr = lower_32_bits((u64)video_get_fb());
}
static void dma_set_descriptor_address(struct udevice *dev)
@@ -2134,7 +2134,6 @@
dev_dbg(dev, "BPP in bits %d, bpix %d\n",
priv->non_live_graphics->bpp, uc_priv->bpix);
- uc_priv->fb = (void *)gd->fb_base;
uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active;
uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active;
/* Calculated by core but need it for my own setup */
diff --git a/dts/upstream/Bindings/arm/airoha.yaml b/dts/upstream/Bindings/arm/airoha.yaml
index 3292c66..7c38c08 100644
--- a/dts/upstream/Bindings/arm/airoha.yaml
+++ b/dts/upstream/Bindings/arm/airoha.yaml
@@ -22,6 +22,10 @@
- enum:
- airoha,en7523-evb
- const: airoha,en7523
+ - items:
+ - enum:
+ - airoha,en7581-evb
+ - const: airoha,en7581
additionalProperties: true
diff --git a/dts/upstream/Bindings/arm/amlogic.yaml b/dts/upstream/Bindings/arm/amlogic.yaml
index a374b98..0647851 100644
--- a/dts/upstream/Bindings/arm/amlogic.yaml
+++ b/dts/upstream/Bindings/arm/amlogic.yaml
@@ -91,6 +91,7 @@
- libretech,aml-s905x-cc
- libretech,aml-s905x-cc-v2
- nexbox,a95x
+ - osmc,vero4k
- const: amlogic,s905x
- const: amlogic,meson-gxl
@@ -107,6 +108,13 @@
- const: amlogic,s905d
- const: amlogic,meson-gxl
+ - description: Boards with the Amlogic Meson GXLX S905L SoC
+ items:
+ - enum:
+ - amlogic,p271
+ - const: amlogic,s905l
+ - const: amlogic,meson-gxlx
+
- description: Boards with the Amlogic Meson GXM S912 SoC
items:
- enum:
@@ -169,6 +177,8 @@
- azw,gtking
- azw,gtking-pro
- bananapi,bpi-m2s
+ - dream,dreambox-one
+ - dream,dreambox-two
- hardkernel,odroid-go-ultra
- hardkernel,odroid-n2
- hardkernel,odroid-n2l
diff --git a/dts/upstream/Bindings/arm/amlogic/analog-top.txt b/dts/upstream/Bindings/arm/amlogic/analog-top.txt
deleted file mode 100644
index 101dc21..0000000
--- a/dts/upstream/Bindings/arm/amlogic/analog-top.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Amlogic Meson8 and Meson8b "analog top" registers:
---------------------------------------------------
-
-The analog top registers contain information about the so-called
-"metal revision" (which encodes the "minor version") of the SoC.
-
-Required properties:
-- reg: the register range of the analog top registers
-- compatible: depending on the SoC this should be one of:
- - "amlogic,meson8-analog-top"
- - "amlogic,meson8b-analog-top"
- along with "syscon"
-
-
-Example:
-
- analog_top: analog-top@81a8 {
- compatible = "amlogic,meson8-analog-top", "syscon";
- reg = <0x81a8 0x14>;
- };
diff --git a/dts/upstream/Bindings/arm/amlogic/assist.txt b/dts/upstream/Bindings/arm/amlogic/assist.txt
deleted file mode 100644
index 7656812..0000000
--- a/dts/upstream/Bindings/arm/amlogic/assist.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Amlogic Meson6/Meson8/Meson8b assist registers:
------------------------------------------------
-
-The assist registers contain basic information about the SoC,
-for example the encoded SoC part number.
-
-Required properties:
-- reg: the register range of the assist registers
-- compatible: should be "amlogic,meson-mx-assist" along with "syscon"
-
-
-Example:
-
- assist: assist@7c00 {
- compatible = "amlogic,meson-mx-assist", "syscon";
- reg = <0x7c00 0x200>;
- };
diff --git a/dts/upstream/Bindings/arm/amlogic/bootrom.txt b/dts/upstream/Bindings/arm/amlogic/bootrom.txt
deleted file mode 100644
index 407e27f..0000000
--- a/dts/upstream/Bindings/arm/amlogic/bootrom.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Amlogic Meson6/Meson8/Meson8b bootrom:
---------------------------------------
-
-The bootrom register area can be used to access SoC specific
-information, such as the "misc version".
-
-Required properties:
-- reg: the register range of the bootrom registers
-- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"
-
-
-Example:
-
- bootrom: bootrom@d9040000 {
- compatible = "amlogic,meson-mx-bootrom", "syscon";
- reg = <0xd9040000 0x10000>;
- };
diff --git a/dts/upstream/Bindings/arm/amlogic/pmu.txt b/dts/upstream/Bindings/arm/amlogic/pmu.txt
deleted file mode 100644
index 72f8d081..0000000
--- a/dts/upstream/Bindings/arm/amlogic/pmu.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Amlogic Meson8 and Meson8b power-management-unit:
--------------------------------------------------
-
-The pmu is used to turn off and on different power domains of the SoCs
-This includes the power to the CPU cores.
-
-Required node properties:
-- compatible value : depending on the SoC this should be one of:
- "amlogic,meson8-pmu"
- "amlogic,meson8b-pmu"
-- reg : physical base address and the size of the registers window
-
-Example:
-
- pmu@c81000e4 {
- compatible = "amlogic,meson8b-pmu", "syscon";
- reg = <0xc81000e0 0x18>;
- };
diff --git a/dts/upstream/Bindings/arm/arm,coresight-dummy-sink.yaml b/dts/upstream/Bindings/arm/arm,coresight-dummy-sink.yaml
index c960c8e..08b89b6 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-dummy-sink.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-dummy-sink.yaml
@@ -30,7 +30,7 @@
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- - James Clark <james.clark@arm.com>
+ - James Clark <james.clark@linaro.org>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
diff --git a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
index 6745b4c..d50a603 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
@@ -29,7 +29,7 @@
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- - James Clark <james.clark@arm.com>
+ - James Clark <james.clark@linaro.org>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
diff --git a/dts/upstream/Bindings/arm/arm,juno-fpga-apb-regs.yaml b/dts/upstream/Bindings/arm/arm,juno-fpga-apb-regs.yaml
new file mode 100644
index 0000000..ce5f2e1
--- /dev/null
+++ b/dts/upstream/Bindings/arm/arm,juno-fpga-apb-regs.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Juno FPGA APB Registers
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+properties:
+ compatible:
+ items:
+ - const: arm,juno-fpga-apb-regs
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+patternProperties:
+ "^led@[0-9a-f]+,[0-9a-f]$":
+ $ref: /schemas/leds/register-bit-led.yaml#
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@10000 {
+ compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd";
+ reg = <0x010000 0x1000>;
+ ranges = <0x0 0x10000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ led@8,0 {
+ compatible = "register-bit-led";
+ reg = <0x08 0x04>;
+ offset = <0x08>;
+ mask = <0x01>;
+ label = "vexpress:0";
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
diff --git a/dts/upstream/Bindings/arm/atmel-sysregs.txt b/dts/upstream/Bindings/arm/atmel-sysregs.txt
index 67a66bf..7374beb 100644
--- a/dts/upstream/Bindings/arm/atmel-sysregs.txt
+++ b/dts/upstream/Bindings/arm/atmel-sysregs.txt
@@ -41,35 +41,6 @@
reg = <0xffffe800 0x200>;
};
-RAMC PHY Controller required properties:
-- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
-- reg: Should contain registers location and length
-
-Example:
-
- ddr3phy: ddr3phy@e3804000 {
- compatible = "microchip,sama7g5-ddr3phy", "syscon";
- reg = <0xe3804000 0x1000>;
-};
-
-Special Function Registers (SFR)
-
-Special Function Registers (SFR) manage specific aspects of the integrated
-memory, bridge implementations, processor and other functionality not controlled
-elsewhere.
-
-required properties:
-- compatible: Should be "atmel,<chip>-sfr", "syscon" or
- "atmel,<chip>-sfrbu", "syscon"
- <chip> can be "sama5d3", "sama5d4" or "sama5d2".
- It also can be "microchip,sam9x60-sfr", "syscon".
-- reg: Should contain registers location and length
-
- sfr@f0038000 {
- compatible = "atmel,sama5d3-sfr", "syscon";
- reg = <0xf0038000 0x60>;
- };
-
Security Module (SECUMOD)
The Security Module macrocell provides all necessary secure functions to avoid
diff --git a/dts/upstream/Bindings/arm/axis.txt b/dts/upstream/Bindings/arm/axis.txt
index ae345e1..ebd33a8 100644
--- a/dts/upstream/Bindings/arm/axis.txt
+++ b/dts/upstream/Bindings/arm/axis.txt
@@ -7,22 +7,6 @@
Required root node properties:
- compatible = "axis,artpec6";
-ARTPEC-6 System Controller
---------------------------
-
-The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
-and resets.
-
-Required properties:
-- compatible: "axis,artpec6-syscon", "syscon"
-- reg: Address and length of the register bank.
-
-Example:
- syscon {
- compatible = "axis,artpec6-syscon", "syscon";
- reg = <0xf8000000 0x48>;
- };
-
ARTPEC-6 Development board:
---------------------------
Required root node properties:
diff --git a/dts/upstream/Bindings/arm/bcm/bcm2835.yaml b/dts/upstream/Bindings/arm/bcm/bcm2835.yaml
index 162a39d..e4ff71f 100644
--- a/dts/upstream/Bindings/arm/bcm/bcm2835.yaml
+++ b/dts/upstream/Bindings/arm/bcm/bcm2835.yaml
@@ -23,6 +23,12 @@
- raspberrypi,4-model-b
- const: brcm,bcm2711
+ - description: BCM2712 based Boards
+ items:
+ - enum:
+ - raspberrypi,5-model-b
+ - const: brcm,bcm2712
+
- description: BCM2835 based Boards
items:
- enum:
diff --git a/dts/upstream/Bindings/arm/cpu-enable-method/al,alpine-smp b/dts/upstream/Bindings/arm/cpu-enable-method/al,alpine-smp
index 35e5afb..cc7b140 100644
--- a/dts/upstream/Bindings/arm/cpu-enable-method/al,alpine-smp
+++ b/dts/upstream/Bindings/arm/cpu-enable-method/al,alpine-smp
@@ -27,16 +27,6 @@
- reg : Offset and length of the register set for the device
-* Alpine System-Fabric Service Registers
-
-The System-Fabric Service Registers allow various operation on CPU and
-system fabric, like powering CPUs off.
-
-Properties:
-- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
-- reg : Offset and length of the register set for the device
-
-
Example:
cpus {
diff --git a/dts/upstream/Bindings/arm/cpus.yaml b/dts/upstream/Bindings/arm/cpus.yaml
index cc5a21b..f308ff6 100644
--- a/dts/upstream/Bindings/arm/cpus.yaml
+++ b/dts/upstream/Bindings/arm/cpus.yaml
@@ -147,6 +147,7 @@
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-a720
+ - arm,cortex-a725
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -161,10 +162,15 @@
- arm,cortex-x2
- arm,cortex-x3
- arm,cortex-x4
+ - arm,cortex-x925
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
+ - arm,neoverse-n3
- arm,neoverse-v1
+ - arm,neoverse-v2
+ - arm,neoverse-v3
+ - arm,neoverse-v3ae
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
diff --git a/dts/upstream/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/dts/upstream/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml
index 526f508..bd39cf1 100644
--- a/dts/upstream/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml
+++ b/dts/upstream/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX7ULP System Integration Module
maintainers:
- - Anson Huang <anson.huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
description: |
The system integration module (SIM) provides system control and chip configuration
diff --git a/dts/upstream/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/dts/upstream/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
deleted file mode 100644
index 44aa3c4..0000000
--- a/dts/upstream/Bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Freescale Vybrid Miscellaneous System Control - CPU Configuration
-
-The MSCM IP contains multiple sub modules, this binding describes the first
-block of registers which contains CPU configuration information.
-
-Required properties:
-- compatible: "fsl,vf610-mscm-cpucfg", "syscon"
-- reg: the register range of the MSCM CPU configuration registers
-
-Example:
- mscm_cpucfg: cpucfg@40001000 {
- compatible = "fsl,vf610-mscm-cpucfg", "syscon";
- reg = <0x40001000 0x800>;
- }
diff --git a/dts/upstream/Bindings/arm/fsl.yaml b/dts/upstream/Bindings/arm/fsl.yaml
index 6d185d0..80747d7 100644
--- a/dts/upstream/Bindings/arm/fsl.yaml
+++ b/dts/upstream/Bindings/arm/fsl.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Li Yang <leoyang.li@nxp.com>
properties:
$nodename:
@@ -363,6 +362,12 @@
- const: gw,ventana
- const: fsl,imx6q
+ - description: i.MX6Q Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
+ items:
+ - const: kontron,imx6q-samx6i-ads2
+ - const: kontron,imx6q-samx6i
+ - const: fsl,imx6q
+
- description: i.MX6Q PHYTEC phyBOARD-Mira
items:
- enum:
@@ -544,6 +549,12 @@
- const: gw,ventana
- const: fsl,imx6dl
+ - description: i.MX6DL Kontron SMARC-sAMX6i on SMARC Eval Carrier 2.0
+ items:
+ - const: kontron,imx6dl-samx6i-ads2
+ - const: kontron,imx6dl-samx6i
+ - const: fsl,imx6dl
+
- description: i.MX6DL PHYTEC phyBOARD-Mira
items:
- enum:
@@ -946,6 +957,13 @@
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
+ - description: Compulab i.MX8MM UCM SoM based boards
+ items:
+ - enum:
+ - compulab,imx8mm-iot-gateway # i.MX8MM Compulab IoT-Gateway
+ - const: compulab,imx8mm-ucm-som # i.MX8MM Compulab UCM SoM
+ - const: fsl,imx8mm
+
- description: Emtop i.MX8MM based Boards
items:
- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1
@@ -1145,8 +1163,9 @@
version as an industrial computing device.
items:
- enum:
- - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
- - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
+ - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
+ - tq,imx8mp-tqma8mpql-mba8mp-ras314 # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MP-RAS314
+ - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
- const: fsl,imx8mp
- description: i.MX8MQ based Boards
@@ -1272,9 +1291,16 @@
- description: i.MX93 based Boards
items:
- enum:
+ - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: i.MX95 based Boards
+ items:
+ - enum:
+ - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
+ - const: fsl,imx95
+
- description: i.MXRT1050 based Boards
items:
- enum:
diff --git a/dts/upstream/Bindings/arm/keystone/ti,sci.yaml b/dts/upstream/Bindings/arm/keystone/ti,sci.yaml
index 7f06b10..25a2b42 100644
--- a/dts/upstream/Bindings/arm/keystone/ti,sci.yaml
+++ b/dts/upstream/Bindings/arm/keystone/ti,sci.yaml
@@ -20,7 +20,7 @@
initialized early into boot process and provides services to Operating Systems
on multiple processors including ones running Linux.
- See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
+ See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
The TI-SCI node describes the Texas Instrument's System Controller entity node.
This parent node may optionally have additional children nodes which describe
diff --git a/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml b/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
index 16d2e13..538d91b 100644
--- a/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
+++ b/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
@@ -82,4 +82,22 @@
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
+ - description:
+ SolidRun CN9130 SoM based single-board computers
+ items:
+ - enum:
+ - solidrun,cn9130-clearfog-base
+ - solidrun,cn9130-clearfog-pro
+ - solidrun,cn9131-solidwan
+ - const: solidrun,cn9130-sr-som
+ - const: marvell,cn9130
+
+ - description:
+ SolidRun CN9132 COM-Express Type 7 based single-board computers
+ items:
+ - enum:
+ - solidrun,cn9132-clearfog
+ - const: solidrun,cn9132-sr-cex7
+ - const: marvell,cn9130
+
additionalProperties: true
diff --git a/dts/upstream/Bindings/arm/marvell/marvell,dove.txt b/dts/upstream/Bindings/arm/marvell/marvell,dove.txt
index aaaf64c..e10e852 100644
--- a/dts/upstream/Bindings/arm/marvell/marvell,dove.txt
+++ b/dts/upstream/Bindings/arm/marvell/marvell,dove.txt
@@ -5,18 +5,3 @@
Required root node property:
- compatible: must contain "marvell,dove";
-
-* Global Configuration registers
-
-Global Configuration registers of Dove SoC are shared by a syscon node.
-
-Required properties:
-- compatible: must contain "marvell,dove-global-config" and "syscon".
-- reg: base address and size of the Global Configuration registers.
-
-Example:
-
-gconf: global-config@e802c {
- compatible = "marvell,dove-global-config", "syscon";
- reg = <0xe802c 0x14>;
-};
diff --git a/dts/upstream/Bindings/arm/mediatek.yaml b/dts/upstream/Bindings/arm/mediatek.yaml
index 09f9ffd..1d4bb50 100644
--- a/dts/upstream/Bindings/arm/mediatek.yaml
+++ b/dts/upstream/Bindings/arm/mediatek.yaml
@@ -85,12 +85,15 @@
- const: mediatek,mt7629
- items:
- enum:
+ - cudy,wr3000-v1
+ - openwrt,one
- xiaomi,ax3000t
- const: mediatek,mt7981b
- items:
- enum:
- acelink,ew-7886cax
- bananapi,bpi-r3
+ - bananapi,bpi-r3mini
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
- items:
@@ -293,6 +296,13 @@
- const: google,tentacruel-sku327683
- const: google,tentacruel
- const: mediatek,mt8186
+ - description: Google Voltorb (Acer Chromebook 311 C723/C732T)
+ items:
+ - enum:
+ - google,voltorb-sku589824
+ - google,voltorb-sku589825
+ - const: google,voltorb
+ - const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8186-evb
@@ -342,6 +352,14 @@
- const: google,tomato-rev3
- const: google,tomato
- const: mediatek,mt8195
+ - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa)
+ items:
+ - const: google,dojo-sku7
+ - const: google,dojo-sku5
+ - const: google,dojo-sku3
+ - const: google,dojo-sku1
+ - const: google,dojo
+ - const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8195-demo
@@ -353,6 +371,12 @@
- const: mediatek,mt8365
- items:
- enum:
+ - mediatek,mt8390-evk
+ - const: mediatek,mt8390
+ - const: mediatek,mt8188
+ - items:
+ - enum:
+ - kontron,3-5-sbc-i1200
- mediatek,mt8395-evk
- radxa,nio-12l
- const: mediatek,mt8395
diff --git a/dts/upstream/Bindings/arm/pmu.yaml b/dts/upstream/Bindings/arm/pmu.yaml
index 99b5e95..528544d 100644
--- a/dts/upstream/Bindings/arm/pmu.yaml
+++ b/dts/upstream/Bindings/arm/pmu.yaml
@@ -53,14 +53,20 @@
- arm,cortex-a710-pmu
- arm,cortex-a715-pmu
- arm,cortex-a720-pmu
+ - arm,cortex-a725-pmu
- arm,cortex-x1-pmu
- arm,cortex-x2-pmu
- arm,cortex-x3-pmu
- arm,cortex-x4-pmu
+ - arm,cortex-x925-pmu
- arm,neoverse-e1-pmu
- arm,neoverse-n1-pmu
- arm,neoverse-n2-pmu
+ - arm,neoverse-n3-pmu
- arm,neoverse-v1-pmu
+ - arm,neoverse-v2-pmu
+ - arm,neoverse-v3-pmu
+ - arm,neoverse-v3ae-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
- nvidia,denver-pmu
diff --git a/dts/upstream/Bindings/arm/qcom.yaml b/dts/upstream/Bindings/arm/qcom.yaml
index ae88541..f08e13b 100644
--- a/dts/upstream/Bindings/arm/qcom.yaml
+++ b/dts/upstream/Bindings/arm/qcom.yaml
@@ -42,6 +42,7 @@
msm8996
msm8998
qcs404
+ qcs8550
qcm2290
qcm6490
qdu1000
@@ -96,6 +97,7 @@
- items:
- enum:
- qcom,apq8016-sbc
+ - schneider,apq8016-hmibsc
- const: qcom,apq8016
- items:
@@ -104,6 +106,7 @@
- huawei,sturgeon
- lg,lenok
- samsung,matisse-wifi
+ - samsung,milletwifi
- const: qcom,apq8026
- items:
@@ -138,6 +141,7 @@
- microsoft,makepeace
- microsoft,moneypenny
- motorola,falcon
+ - samsung,ms013g
- samsung,s3ve3g
- const: qcom,msm8226
@@ -175,6 +179,7 @@
- items:
- enum:
- lge,hammerhead
+ - samsung,hlte
- sony,xperia-amami
- sony,xperia-honami
- const: qcom,msm8974
@@ -182,8 +187,10 @@
- items:
- enum:
- fairphone,fp2
+ - htc,m8
- oneplus,bacon
- samsung,klte
+ - sony,xperia-aries
- sony,xperia-castor
- sony,xperia-leo
- const: qcom,msm8974pro
@@ -203,8 +210,13 @@
- asus,z00l
- gplus,fl8005a
- huawei,g7
+ - lg,c50
+ - lg,m216
- longcheer,l8910
- longcheer,l8150
+ - motorola,harpia
+ - motorola,osprey
+ - motorola,surnia
- qcom,msm8916-mtp
- samsung,a3u-eur
- samsung,a5u-eur
@@ -316,6 +328,7 @@
- items:
- enum:
- qcom,ipq5018-rdp432-c2
+ - tplink,archer-ax55-v1
- const: qcom,ipq5018
- items:
@@ -366,6 +379,7 @@
- fairphone,fp5
- qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2
+ - shift,otter
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
@@ -802,6 +816,7 @@
- items:
- enum:
+ - lenovo,tbx605f
- motorola,ali
- const: qcom,sdm450
@@ -883,6 +898,7 @@
- items:
- enum:
- qcom,sa8775p-ride
+ - qcom,sa8775p-ride-r3
- const: qcom,sa8775p
- items:
@@ -1004,17 +1020,28 @@
- qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
+ - samsung,q5q
- sony,pdx234
- const: qcom,sm8550
- items:
- enum:
+ - qcom,qcs8550-aim300-aiot
+ - const: qcom,qcs8550-aim300
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
+ - items:
+ - enum:
+ - qcom,sm8650-hdk
- qcom,sm8650-mtp
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
+ - asus,vivobook-s15
+ - lenovo,yoga-slim7x
- qcom,x1e80100-crd
- qcom,x1e80100-qcp
- const: qcom,x1e80100
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index e04c213..1ef09fb 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -248,6 +248,13 @@
- const: friendlyarm,nanopc-t6
- const: rockchip,rk3588
+ - description: FriendlyElec CM3588-based boards
+ items:
+ - enum:
+ - friendlyarm,cm3588-nas
+ - const: friendlyarm,cm3588
+ - const: rockchip,rk3588
+
- description: GameForce Chi
items:
- const: gameforce,chi
@@ -627,6 +634,11 @@
- const: mqmaker,miqi
- const: rockchip,rk3288
+ - description: Neardi LBA3368
+ items:
+ - const: neardi,lba3368
+ - const: rockchip,rk3368
+
- description: Netxeon R89 board
items:
- const: netxeon,r89
@@ -799,11 +811,21 @@
- const: radxa,rock3a
- const: rockchip,rk3568
+ - description: Radxa ROCK 3B
+ items:
+ - const: radxa,rock-3b
+ - const: rockchip,rk3568
+
- description: Radxa ROCK 3C
items:
- const: radxa,rock-3c
- const: rockchip,rk3566
+ - description: Radxa ROCK 5 ITX
+ items:
+ - const: radxa,rock-5-itx
+ - const: rockchip,rk3588
+
- description: Radxa ROCK 5A
items:
- const: radxa,rock-5a
@@ -814,6 +836,18 @@
- const: radxa,rock-5b
- const: rockchip,rk3588
+ - description: Radxa ROCK S0
+ items:
+ - const: radxa,rock-s0
+ - const: rockchip,rk3308
+
+ - description: Radxa ZERO 3W/3E
+ items:
+ - enum:
+ - radxa,zero-3e
+ - radxa,zero-3w
+ - const: rockchip,rk3566
+
- description: Rikomagic MK808 v1
items:
- const: rikomagic,mk808
@@ -959,6 +993,14 @@
- const: wolfvision,rk3568-pf5
- const: rockchip,rk3568
+ - description: Xunlong Orange Pi 3B
+ items:
+ - enum:
+ - xunlong,orangepi-3b-v1.1
+ - xunlong,orangepi-3b-v2.1
+ - const: xunlong,orangepi-3b
+ - const: rockchip,rk3566
+
- description: Xunlong Orange Pi 5 Plus
items:
- const: xunlong,orangepi-5-plus
diff --git a/dts/upstream/Bindings/arm/rtsm-dcscb.txt b/dts/upstream/Bindings/arm/rtsm-dcscb.txt
deleted file mode 100644
index 3b8fbf3..0000000
--- a/dts/upstream/Bindings/arm/rtsm-dcscb.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-ARM Dual Cluster System Configuration Block
--------------------------------------------
-
-The Dual Cluster System Configuration Block (DCSCB) provides basic
-functionality for controlling clocks, resets and configuration pins in
-the Dual Cluster System implemented by the Real-Time System Model (RTSM).
-
-Required properties:
-
-- compatible : should be "arm,rtsm,dcscb"
-
-- reg : physical base address and the size of the registers window
-
-Example:
-
- dcscb@60000000 {
- compatible = "arm,rtsm,dcscb";
- reg = <0x60000000 0x1000>;
- };
diff --git a/dts/upstream/Bindings/arm/spear-misc.txt b/dts/upstream/Bindings/arm/spear-misc.txt
deleted file mode 100644
index e404e25..0000000
--- a/dts/upstream/Bindings/arm/spear-misc.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-SPEAr Misc configuration
-===========================
-SPEAr SOCs have some miscellaneous registers which are used to configure
-few properties of different peripheral controllers.
-
-misc node required properties:
-
-- compatible Should be "st,spear1340-misc", "syscon".
-- reg: Address range of misc space up to 8K
diff --git a/dts/upstream/Bindings/arm/stm32/stm32.yaml b/dts/upstream/Bindings/arm/stm32/stm32.yaml
index bc2f433..5809994 100644
--- a/dts/upstream/Bindings/arm/stm32/stm32.yaml
+++ b/dts/upstream/Bindings/arm/stm32/stm32.yaml
@@ -59,6 +59,12 @@
- prt,prtt1s # Protonic PRTT1S
- const: st,stm32mp151
+ - description: DH STM32MP135 DHCOR SoM based Boards
+ items:
+ - const: dh,stm32mp135f-dhcor-dhsbc
+ - const: dh,stm32mp135f-dhcor-som
+ - const: st,stm32mp135
+
- description: DH STM32MP151 DHCOR SoM based Boards
items:
- const: dh,stm32mp151a-dhcor-testbench
diff --git a/dts/upstream/Bindings/arm/sunxi.yaml b/dts/upstream/Bindings/arm/sunxi.yaml
index c2a158b..09dc6f4 100644
--- a/dts/upstream/Bindings/arm/sunxi.yaml
+++ b/dts/upstream/Bindings/arm/sunxi.yaml
@@ -708,12 +708,12 @@
- const: olimex,a64-teres-i
- const: allwinner,sun50i-a64
- - description: Pine64
+ - description: Pine64 PINE A64
items:
- const: pine64,pine64
- const: allwinner,sun50i-a64
- - description: Pine64+
+ - description: Pine64 PINE A64+
items:
- const: pine64,pine64-plus
- const: allwinner,sun50i-a64
@@ -724,17 +724,17 @@
- const: sochip,s3
- const: allwinner,sun8i-v3
- - description: Pine64 PineH64 model A
+ - description: Pine64 PINE H64 Model A
items:
- const: pine64,pine-h64
- const: allwinner,sun50i-h6
- - description: Pine64 PineH64 model B
+ - description: Pine64 PINE H64 Model B
items:
- const: pine64,pine-h64-model-b
- const: allwinner,sun50i-h6
- - description: Pine64 LTS
+ - description: Pine64 PINE A64 LTS
items:
- const: pine64,pine64-lts
- const: allwinner,sun50i-r18
@@ -763,17 +763,17 @@
- const: pine64,pinephone
- const: allwinner,sun50i-a64
- - description: Pine64 PineTab, Development Sample
+ - description: Pine64 PineTab Developer Sample
items:
- const: pine64,pinetab
- const: allwinner,sun50i-a64
- - description: Pine64 PineTab, Early Adopter's batch (and maybe later ones)
+ - description: Pine64 PineTab Early Adopter
items:
- const: pine64,pinetab-early-adopter
- const: allwinner,sun50i-a64
- - description: Pine64 SoPine Baseboard
+ - description: Pine64 SOPINE
items:
- const: pine64,sopine-baseboard
- const: pine64,sopine
diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml b/dts/upstream/Bindings/arm/ti/k3.yaml
index 52b51fd..4d9c5fb 100644
--- a/dts/upstream/Bindings/arm/ti/k3.yaml
+++ b/dts/upstream/Bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@
- ti,am62a7-sk
- const: ti,am62a7
+ - description: K3 AM62A7 SoC PHYTEC phyBOARD-Lyra
+ items:
+ - const: phytec,am62a7-phyboard-lyra-rdk
+ - const: phytec,am62a-phycore-som
+ - const: ti,am62a7
+
- description: K3 AM62P5 SoC and Boards
items:
- enum:
diff --git a/dts/upstream/Bindings/ata/ahci-fsl-qoriq.txt b/dts/upstream/Bindings/ata/ahci-fsl-qoriq.txt
deleted file mode 100644
index 7c3ca0e..0000000
--- a/dts/upstream/Bindings/ata/ahci-fsl-qoriq.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Binding for Freescale QorIQ AHCI SATA Controller
-
-Required properties:
- - reg: Physical base address and size of the controller's register area.
- - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
- chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
- - clocks: Input clock specifier. Refer to common clock bindings.
- - interrupts: Interrupt specifier. Refer to interrupt binding.
-
-Optional properties:
- - dma-coherent: Enable AHCI coherent DMA operation.
- - reg-names: register area names when there are more than 1 register area.
-
-Examples:
- sata@3200000 {
- compatible = "fsl,ls1021a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- dma-coherent;
- };
diff --git a/dts/upstream/Bindings/ata/fsl,ahci.yaml b/dts/upstream/Bindings/ata/fsl,ahci.yaml
new file mode 100644
index 0000000..ea4428b
--- /dev/null
+++ b/dts/upstream/Bindings/ata/fsl,ahci.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/fsl,ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QorIQ AHCI SATA Controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: SATA controller for ls1012a
+ items:
+ - const: fsl,ls1012a-ahci
+ - const: fsl,ls1043a-ahci
+ - enum:
+ - fsl,ls1021a-ahci
+ - fsl,ls1028a-ahci
+ - fsl,ls1043a-ahci
+ - fsl,ls1046a-ahci
+ - fsl,ls1088a-ahci
+ - fsl,ls2080a-ahci
+ - fsl,lx2160a-ahci
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: ahci
+ - const: sata-ecc
+ minItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sata@3200000 {
+ compatible = "fsl,ls1021a-ahci";
+ reg = <0x3200000 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&platform_clk 1>;
+ dma-coherent;
+ };
diff --git a/dts/upstream/Bindings/ata/rockchip,dwc-ahci.yaml b/dts/upstream/Bindings/ata/rockchip,dwc-ahci.yaml
index b5e5767..13eaa8d 100644
--- a/dts/upstream/Bindings/ata/rockchip,dwc-ahci.yaml
+++ b/dts/upstream/Bindings/ata/rockchip,dwc-ahci.yaml
@@ -35,6 +35,9 @@
ports-implemented:
const: 1
+ power-domains:
+ maxItems: 1
+
sata-port@0:
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
diff --git a/dts/upstream/Bindings/cache/qcom,llcc.yaml b/dts/upstream/Bindings/cache/qcom,llcc.yaml
index b9a9f2c..68ea5f7 100644
--- a/dts/upstream/Bindings/cache/qcom,llcc.yaml
+++ b/dts/upstream/Bindings/cache/qcom,llcc.yaml
@@ -21,6 +21,7 @@
compatible:
enum:
- qcom,qdu1000-llcc
+ - qcom,sa8775p-llcc
- qcom,sc7180-llcc
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
@@ -84,6 +85,33 @@
compatible:
contains:
enum:
+ - qcom,sa8775p-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC4 base register region
+ - description: LLCC5 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc4_base
+ - const: llcc5_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sc7280-llcc
then:
properties:
@@ -141,8 +169,31 @@
- qcom,sm8150-llcc
- qcom,sm8250-llcc
- qcom,sm8350-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sm8450-llcc
- qcom,sm8550-llcc
+ - qcom,sm8650-llcc
then:
properties:
reg:
@@ -151,7 +202,8 @@
- description: LLCC1 base register region
- description: LLCC2 base register region
- description: LLCC3 base register region
- - description: LLCC broadcast base register region
+ - description: LLCC broadcast OR register region
+ - description: LLCC broadcast AND register region
reg-names:
items:
- const: llcc0_base
@@ -159,6 +211,7 @@
- const: llcc2_base
- const: llcc3_base
- const: llcc_broadcast_base
+ - const: llcc_broadcast_and_base
additionalProperties: false
diff --git a/dts/upstream/Bindings/cache/starfive,jh8100-starlink-cache.yaml b/dts/upstream/Bindings/cache/starfive,jh8100-starlink-cache.yaml
new file mode 100644
index 0000000..6d61098
--- /dev/null
+++ b/dts/upstream/Bindings/cache/starfive,jh8100-starlink-cache.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive StarLink Cache Controller
+
+maintainers:
+ - Joshua Yeong <joshua.yeong@starfivetech.com>
+
+description:
+ StarFive's StarLink Cache Controller manages the L3 cache shared between
+ clusters of CPU cores. The cache driver enables RISC-V non-standard cache
+ management as an alternative to instructions in the RISC-V Zicbom extension.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+# We need a select here so we don't match all nodes with 'cache'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh8100-starlink-cache
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jh8100-starlink-cache
+ - const: cache
+
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cache-controller@15000000 {
+ compatible = "starfive,jh8100-starlink-cache", "cache";
+ reg = <0x0 0x15000000 0x0 0x278>;
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <8192>;
+ cache-size = <0x400000>;
+ cache-unified;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml b/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml
index 3f42666..84353fd 100644
--- a/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml
+++ b/dts/upstream/Bindings/clock/airoha,en7523-scu.yaml
@@ -35,7 +35,7 @@
reg:
minItems: 2
- maxItems: 3
+ maxItems: 4
"#clock-cells":
description:
@@ -43,6 +43,10 @@
clocks.
const: 1
+ '#reset-cells':
+ description: ID of the controller reset line
+ const: 1
+
required:
- compatible
- reg
@@ -60,6 +64,8 @@
- description: scu base address
- description: misc scu base address
+ '#reset-cells': false
+
- if:
properties:
compatible:
@@ -70,6 +76,7 @@
items:
- description: scu base address
- description: misc scu base address
+ - description: reset base address
- description: pb scu base address
additionalProperties: false
@@ -83,3 +90,19 @@
<0x1fb00000 0x1000>;
#clock-cells = <1>;
};
+
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ scuclk: clock-controller@1fa20000 {
+ compatible = "airoha,en7581-scu";
+ reg = <0x0 0x1fa20000 0x0 0x400>,
+ <0x0 0x1fb00000 0x0 0x90>,
+ <0x0 0x1fb00830 0x0 0x8>,
+ <0x0 0x1fbe3400 0x0 0xfc>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/amlogic,a1-peripherals-clkc.yaml b/dts/upstream/Bindings/clock/amlogic,a1-peripherals-clkc.yaml
index 6d84cee..2568ad7 100644
--- a/dts/upstream/Bindings/clock/amlogic,a1-peripherals-clkc.yaml
+++ b/dts/upstream/Bindings/clock/amlogic,a1-peripherals-clkc.yaml
@@ -30,6 +30,8 @@
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
+ - description: input sys pll
+ minItems: 6 # sys_pll is optional
clock-names:
items:
@@ -39,6 +41,8 @@
- const: fclk_div7
- const: hifi_pll
- const: xtal
+ - const: sys_pll
+ minItems: 6 # sys_pll is optional
required:
- compatible
@@ -65,9 +69,10 @@
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
- <&xtal>;
+ <&xtal>,
+ <&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
- "hifi_pll", "xtal";
+ "hifi_pll", "xtal", "sys_pll";
};
};
diff --git a/dts/upstream/Bindings/clock/amlogic,a1-pll-clkc.yaml b/dts/upstream/Bindings/clock/amlogic,a1-pll-clkc.yaml
index a59b188..c99274d 100644
--- a/dts/upstream/Bindings/clock/amlogic,a1-pll-clkc.yaml
+++ b/dts/upstream/Bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -26,11 +26,15 @@
items:
- description: input fixpll_in
- description: input hifipll_in
+ - description: input syspll_in
+ minItems: 2 # syspll_in is optional
clock-names:
items:
- const: fixpll_in
- const: hifipll_in
+ - const: syspll_in
+ minItems: 2 # syspll_in is optional
required:
- compatible
@@ -53,7 +57,8 @@
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
- <&clkc_periphs CLKID_HIFIPLL_IN>;
- clock-names = "fixpll_in", "hifipll_in";
+ <&clkc_periphs CLKID_HIFIPLL_IN>,
+ <&clkc_periphs CLKID_SYSPLL_IN>;
+ clock-names = "fixpll_in", "hifipll_in", "syspll_in";
};
};
diff --git a/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.txt b/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.txt
deleted file mode 100644
index 3a8948c..0000000
--- a/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* Amlogic AXG Audio Clock Controllers
-
-The Amlogic AXG audio clock controller generates and supplies clock to the
-other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
-devices.
-
-Required Properties:
-
-- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
- "amlogic,g12a-audio-clkc" for G12A,
- "amlogic,sm1-audio-clkc" for S905X3.
-- reg : physical base address of the clock controller and length of
- memory mapped region.
-- clocks : a list of phandle + clock-specifier pairs for the clocks listed
- in clock-names.
-- clock-names : must contain the following:
- * "pclk" - Main peripheral bus clock
- may contain the following:
- * "mst_in[0-7]" - 8 input plls to generate clock signals
- * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
- components.
- * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
- components.
-- resets : phandle of the internal reset line
-- #clock-cells : should be 1.
-- #reset-cells : should be 1 on the g12a (and following) soc family
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
-used in device tree sources.
-
-Example:
-
-clkc_audio: clock-controller@0 {
- compatible = "amlogic,axg-audio-clkc";
- reg = <0x0 0x0 0x0 0xb4>;
- #clock-cells = <1>;
-
- clocks = <&clkc CLKID_AUDIO>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL3>,
- <&clkc CLKID_HIFI_PLL>,
- <&clkc CLKID_FCLK_DIV3>,
- <&clkc CLKID_FCLK_DIV4>,
- <&clkc CLKID_GP0_PLL>;
- clock-names = "pclk",
- "mst_in0",
- "mst_in1",
- "mst_in2",
- "mst_in3",
- "mst_in4",
- "mst_in5",
- "mst_in6",
- "mst_in7";
- resets = <&reset RESET_AUDIO>;
-};
diff --git a/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.yaml b/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.yaml
new file mode 100644
index 0000000..fd7982d
--- /dev/null
+++ b/dts/upstream/Bindings/clock/amlogic,axg-audio-clkc.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic AXG Audio Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+
+description:
+ The Amlogic AXG audio clock controller generates and supplies clock to the
+ other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
+ devices.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,axg-audio-clkc
+ - amlogic,g12a-audio-clkc
+ - amlogic,sm1-audio-clkc
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: main peripheral bus clock
+ - description: input plls to generate clock signals N0
+ - description: input plls to generate clock signals N1
+ - description: input plls to generate clock signals N2
+ - description: input plls to generate clock signals N3
+ - description: input plls to generate clock signals N4
+ - description: input plls to generate clock signals N5
+ - description: input plls to generate clock signals N6
+ - description: input plls to generate clock signals N7
+ - description: slave bit clock N0 provided by external components
+ - description: slave bit clock N1 provided by external components
+ - description: slave bit clock N2 provided by external components
+ - description: slave bit clock N3 provided by external components
+ - description: slave bit clock N4 provided by external components
+ - description: slave bit clock N5 provided by external components
+ - description: slave bit clock N6 provided by external components
+ - description: slave bit clock N7 provided by external components
+ - description: slave bit clock N8 provided by external components
+ - description: slave bit clock N9 provided by external components
+ - description: slave sample clock N0 provided by external components
+ - description: slave sample clock N1 provided by external components
+ - description: slave sample clock N2 provided by external components
+ - description: slave sample clock N3 provided by external components
+ - description: slave sample clock N4 provided by external components
+ - description: slave sample clock N5 provided by external components
+ - description: slave sample clock N6 provided by external components
+ - description: slave sample clock N7 provided by external components
+ - description: slave sample clock N8 provided by external components
+ - description: slave sample clock N9 provided by external components
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: pclk
+ - const: mst_in0
+ - const: mst_in1
+ - const: mst_in2
+ - const: mst_in3
+ - const: mst_in4
+ - const: mst_in5
+ - const: mst_in6
+ - const: mst_in7
+ - const: slv_sclk0
+ - const: slv_sclk1
+ - const: slv_sclk2
+ - const: slv_sclk3
+ - const: slv_sclk4
+ - const: slv_sclk5
+ - const: slv_sclk6
+ - const: slv_sclk7
+ - const: slv_sclk8
+ - const: slv_sclk9
+ - const: slv_lrclk0
+ - const: slv_lrclk1
+ - const: slv_lrclk2
+ - const: slv_lrclk3
+ - const: slv_lrclk4
+ - const: slv_lrclk5
+ - const: slv_lrclk6
+ - const: slv_lrclk7
+ - const: slv_lrclk8
+ - const: slv_lrclk9
+
+ resets:
+ description: internal reset line
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+ - resets
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,g12a-audio-clkc
+ - amlogic,sm1-audio-clkc
+ then:
+ required:
+ - '#reset-cells'
+ else:
+ properties:
+ '#reset-cells': false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/axg-clkc.h>
+ #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_audio: clock-controller@0 {
+ compatible = "amlogic,axg-audio-clkc";
+ reg = <0x0 0x0 0x0 0xb4>;
+ #clock-cells = <1>;
+
+ clocks = <&clkc CLKID_AUDIO>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL3>,
+ <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_GP0_PLL>,
+ <&slv_sclk0>,
+ <&slv_sclk1>,
+ <&slv_sclk2>,
+ <&slv_sclk3>,
+ <&slv_sclk4>,
+ <&slv_sclk5>,
+ <&slv_sclk6>,
+ <&slv_sclk7>,
+ <&slv_sclk8>,
+ <&slv_sclk9>,
+ <&slv_lrclk0>,
+ <&slv_lrclk1>,
+ <&slv_lrclk2>,
+ <&slv_lrclk3>,
+ <&slv_lrclk4>,
+ <&slv_lrclk5>,
+ <&slv_lrclk6>,
+ <&slv_lrclk7>,
+ <&slv_lrclk8>,
+ <&slv_lrclk9>;
+ clock-names = "pclk",
+ "mst_in0",
+ "mst_in1",
+ "mst_in2",
+ "mst_in3",
+ "mst_in4",
+ "mst_in5",
+ "mst_in6",
+ "mst_in7",
+ "slv_sclk0",
+ "slv_sclk1",
+ "slv_sclk2",
+ "slv_sclk3",
+ "slv_sclk4",
+ "slv_sclk5",
+ "slv_sclk6",
+ "slv_sclk7",
+ "slv_sclk8",
+ "slv_sclk9",
+ "slv_lrclk0",
+ "slv_lrclk1",
+ "slv_lrclk2",
+ "slv_lrclk3",
+ "slv_lrclk4",
+ "slv_lrclk5",
+ "slv_lrclk6",
+ "slv_lrclk7",
+ "slv_lrclk8",
+ "slv_lrclk9";
+ resets = <&reset RESET_AUDIO>;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/amlogic,c3-peripherals-clkc.yaml b/dts/upstream/Bindings/clock/amlogic,c3-peripherals-clkc.yaml
new file mode 100644
index 0000000..98e30b8
--- /dev/null
+++ b/dts/upstream/Bindings/clock/amlogic,c3-peripherals-clkc.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic C3 series Peripheral Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,c3-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 16
+ items:
+ - description: input oscillator (usually at 24MHz)
+ - description: input oscillators multiplexer
+ - description: input fix pll
+ - description: input fclk div 2
+ - description: input fclk div 2p5
+ - description: input fclk div 3
+ - description: input fclk div 4
+ - description: input fclk div 5
+ - description: input fclk div 7
+ - description: input gp0 pll
+ - description: input gp1 pll
+ - description: input hifi pll
+ - description: input sys clk
+ - description: input axi clk
+ - description: input sys pll div 16
+ - description: input cpu clk div 16
+ - description: input pad clock for rtc clk (optional)
+
+ clock-names:
+ minItems: 16
+ items:
+ - const: xtal_24m
+ - const: oscin
+ - const: fix
+ - const: fdiv2
+ - const: fdiv2p5
+ - const: fdiv3
+ - const: fdiv4
+ - const: fdiv5
+ - const: fdiv7
+ - const: gp0
+ - const: gp1
+ - const: hifi
+ - const: sysclk
+ - const: axiclk
+ - const: sysplldiv16
+ - const: cpudiv16
+ - const: pad_osc
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@0 {
+ compatible = "amlogic,c3-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x49c>;
+ #clock-cells = <1>;
+ clocks = <&xtal_24m>,
+ <&scmi_clk 8>,
+ <&scmi_clk 12>,
+ <&clkc_pll 3>,
+ <&clkc_pll 5>,
+ <&clkc_pll 7>,
+ <&clkc_pll 9>,
+ <&clkc_pll 11>,
+ <&clkc_pll 13>,
+ <&clkc_pll 15>,
+ <&scmi_clk 13>,
+ <&clkc_pll 17>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 14>,
+ <&scmi_clk 15>;
+ clock-names = "xtal_24m",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/amlogic,c3-pll-clkc.yaml b/dts/upstream/Bindings/clock/amlogic,c3-pll-clkc.yaml
new file mode 100644
index 0000000..43de3c6
--- /dev/null
+++ b/dts/upstream/Bindings/clock/amlogic,c3-pll-clkc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic C3 series PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Chuan Liu <chuan.liu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,c3-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input top pll
+ - description: input mclk pll
+
+ clock-names:
+ items:
+ - const: top
+ - const: mclk
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8000 {
+ compatible = "amlogic,c3-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ clocks = <&scmi_clk 2>,
+ <&scmi_clk 5>;
+ clock-names = "top", "mclk";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/fsl,qoriq-clock-legacy.yaml b/dts/upstream/Bindings/clock/fsl,qoriq-clock-legacy.yaml
new file mode 100644
index 0000000..97b96a1
--- /dev/null
+++ b/dts/upstream/Bindings/clock/fsl,qoriq-clock-legacy.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Legacy Clock Block on Freescale QorIQ Platforms
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ These nodes are deprecated. Kernels should continue to support
+ device trees with these nodes, but new device trees should not use them.
+
+ Most of the bindings are from the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ enum:
+ - fsl,qoriq-core-pll-1.0
+ - fsl,qoriq-core-pll-2.0
+ - fsl,qoriq-core-mux-1.0
+ - fsl,qoriq-core-mux-2.0
+ - fsl,qoriq-sysclk-1.0
+ - fsl,qoriq-sysclk-2.0
+ - fsl,qoriq-platform-pll-1.0
+ - fsl,qoriq-platform-pll-2.0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 8
+
+ '#clock-cells':
+ minimum: 0
+ maximum: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,qoriq-sysclk-1.0
+ - fsl,qoriq-sysclk-2.0
+ then:
+ properties:
+ '#clock-cells':
+ const: 0
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,qoriq-core-pll-1.0
+ - fsl,qoriq-core-pll-2.0
+ then:
+ properties:
+ '#clock-cells':
+ const: 1
+ description: |
+ * 0 - equal to the PLL frequency
+ * 1 - equal to the PLL frequency divided by 2
+ * 2 - equal to the PLL frequency divided by 4
+
diff --git a/dts/upstream/Bindings/clock/fsl,qoriq-clock.yaml b/dts/upstream/Bindings/clock/fsl,qoriq-clock.yaml
new file mode 100644
index 0000000..95a3e3b
--- /dev/null
+++ b/dts/upstream/Bindings/clock/fsl,qoriq-clock.yaml
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock Block on Freescale QorIQ Platforms
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ Freescale QorIQ chips take primary clocking input from the external
+ SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+ multiple phase locked loops (PLL) to create a variety of frequencies
+ which can then be passed to a variety of internal logic, including
+ cores and peripheral IP blocks.
+ Please refer to the Reference Manual for details.
+
+ All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+ which the chip complies.
+
+ Chassis Version Example Chips
+ --------------- -------------
+ 1.0 p4080, p5020, p5040
+ 2.0 t4240
+
+ Clock Provider
+
+ The clockgen node should act as a clock provider, though in older device
+ trees the children of the clockgen node are the clock providers.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,p2041-clockgen
+ - fsl,p3041-clockgen
+ - fsl,p4080-clockgen
+ - fsl,p5020-clockgen
+ - fsl,p5040-clockgen
+ - const: fsl,qoriq-clockgen-1.0
+ - items:
+ - enum:
+ - fsl,t1023-clockgen
+ - fsl,t1024-clockgen
+ - fsl,t1040-clockgen
+ - fsl,t1042-clockgen
+ - fsl,t2080-clockgen
+ - fsl,t2081-clockgen
+ - fsl,t4240-clockgen
+ - const: fsl,qoriq-clockgen-2.0
+ - items:
+ - enum:
+ - fsl,b4420-clockgen
+ - fsl,b4860-clockgen
+ - const: fsl,b4-clockgen
+ - items:
+ - enum:
+ - fsl,ls1012a-clockgen
+ - fsl,ls1021a-clockgen
+ - fsl,ls1028a-clockgen
+ - fsl,ls1043a-clockgen
+ - fsl,ls1046a-clockgen
+ - fsl,ls1088a-clockgen
+ - fsl,ls2080a-clockgen
+ - fsl,lx2160a-clockgen
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ '#clock-cells':
+ const: 2
+ description: |
+ The first cell of the clock specifier is the clock type, and the
+ second cell is the clock index for the specified type.
+
+ Type# Name Index Cell
+ 0 sysclk must be 0
+ 1 cmux index (n in CLKCnCSR)
+ 2 hwaccel index (n in CLKCGnHWACSR)
+ 3 fman 0 for fm1, 1 for fm2
+ 4 platform pll n=pll/(n+1). For example, when n=1,
+ that means output_freq=PLL_freq/2.
+ 5 coreclk must be 0
+
+ clock-frequency:
+ description: Input system clock frequency (SYSCLK)
+
+ clocks:
+ items:
+ - description:
+ sysclk may be provided as an input clock. Either clock-frequency
+ or clocks must be provided.
+ - description:
+ A second input clock, called "coreclk", may be provided if
+ core PLLs are based on a different input clock from the
+ platform PLL.
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: sysclk
+ - const: coreclk
+
+patternProperties:
+ '^mux[0-9]@[a-f0-9]+$':
+ deprecated: true
+ $ref: fsl,qoriq-clock-legacy.yaml
+
+ '^sysclk(-[a-z0-9]+)?$':
+ deprecated: true
+ $ref: fsl,qoriq-clock-legacy.yaml
+
+ '^pll[0-9]@[a-f0-9]+$':
+ deprecated: true
+ $ref: fsl,qoriq-clock-legacy.yaml
+
+ '^platform\-pll@[a-f0-9]+$':
+ deprecated: true
+ $ref: fsl,qoriq-clock-legacy.yaml
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ /* clock provider example */
+ global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <133333333>;
+ #clock-cells = <2>;
+ };
+
+ - |
+ /* Legacy example */
+ global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ ranges = <0x0 0xe1000 0x1000>;
+ clock-frequency = <133333333>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #clock-cells = <2>;
+
+ sysclk: sysclk {
+ compatible = "fsl,qoriq-sysclk-1.0";
+ clock-output-names = "sysclk";
+ #clock-cells = <0>;
+ };
+
+ pll0: pll0@800 {
+ compatible = "fsl,qoriq-core-pll-1.0";
+ reg = <0x800 0x4>;
+ #clock-cells = <1>;
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ compatible = "fsl,qoriq-core-pll-1.0";
+ reg = <0x820 0x4>;
+ #clock-cells = <1>;
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ compatible = "fsl,qoriq-core-mux-1.0";
+ reg = <0x0 0x4>;
+ #clock-cells = <0>;
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ compatible = "fsl,qoriq-core-mux-1.0";
+ reg = <0x20 0x4>;
+ #clock-cells = <0>;
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+ clock-output-names = "cmux1";
+ };
+
+ platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/imx6q-clock.yaml b/dts/upstream/Bindings/clock/imx6q-clock.yaml
index bae4fcb..cd3c04c 100644
--- a/dts/upstream/Bindings/clock/imx6q-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx6q-clock.yaml
@@ -7,7 +7,8 @@
title: Freescale i.MX6 Quad Clock Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/clock/imx6sl-clock.yaml b/dts/upstream/Bindings/clock/imx6sl-clock.yaml
index c85ff6e..6713bbb 100644
--- a/dts/upstream/Bindings/clock/imx6sl-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx6sl-clock.yaml
@@ -7,7 +7,8 @@
title: Freescale i.MX6 SoloLite Clock Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/clock/imx6sll-clock.yaml b/dts/upstream/Bindings/clock/imx6sll-clock.yaml
index 6b549ed..6d64cf9 100644
--- a/dts/upstream/Bindings/clock/imx6sll-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx6sll-clock.yaml
@@ -7,7 +7,8 @@
title: Freescale i.MX6 SLL Clock Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/clock/imx6sx-clock.yaml b/dts/upstream/Bindings/clock/imx6sx-clock.yaml
index 55dcad1..77afa4b 100644
--- a/dts/upstream/Bindings/clock/imx6sx-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx6sx-clock.yaml
@@ -7,7 +7,8 @@
title: Freescale i.MX6 SoloX Clock Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/clock/imx6ul-clock.yaml b/dts/upstream/Bindings/clock/imx6ul-clock.yaml
index be54d4d..d57e18a 100644
--- a/dts/upstream/Bindings/clock/imx6ul-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx6ul-clock.yaml
@@ -7,7 +7,8 @@
title: Freescale i.MX6 UltraLite Clock Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/clock/imx7d-clock.yaml b/dts/upstream/Bindings/clock/imx7d-clock.yaml
index e7d8427..880d602 100644
--- a/dts/upstream/Bindings/clock/imx7d-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx7d-clock.yaml
@@ -8,7 +8,6 @@
maintainers:
- Frank Li <Frank.Li@nxp.com>
- - Anson Huang <Anson.Huang@nxp.com>
description: |
The clock consumer should specify the desired clock by having the clock
diff --git a/dts/upstream/Bindings/clock/imx8m-clock.yaml b/dts/upstream/Bindings/clock/imx8m-clock.yaml
index 80539f8..c643d4a 100644
--- a/dts/upstream/Bindings/clock/imx8m-clock.yaml
+++ b/dts/upstream/Bindings/clock/imx8m-clock.yaml
@@ -7,7 +7,8 @@
title: NXP i.MX8M Family Clock Control Module
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Abel Vesa <abelvesa@kernel.org>
+ - Peng Fan <peng.fan@nxp.com>
description: |
NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
diff --git a/dts/upstream/Bindings/clock/mediatek,mt7622-pciesys.yaml b/dts/upstream/Bindings/clock/mediatek,mt7622-pciesys.yaml
index c77111d..9c3913f 100644
--- a/dts/upstream/Bindings/clock/mediatek,mt7622-pciesys.yaml
+++ b/dts/upstream/Bindings/clock/mediatek,mt7622-pciesys.yaml
@@ -14,9 +14,11 @@
properties:
compatible:
- enum:
- - mediatek,mt7622-pciesys
- - mediatek,mt7629-pciesys
+ oneOf:
+ - items:
+ - const: mediatek,mt7622-pciesys
+ - const: syscon
+ - const: mediatek,mt7629-pciesys
reg:
maxItems: 1
@@ -38,7 +40,7 @@
examples:
- |
clock-controller@1a100800 {
- compatible = "mediatek,mt7622-pciesys";
+ compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/dts/upstream/Bindings/clock/mediatek,mt8188-sys-clock.yaml b/dts/upstream/Bindings/clock/mediatek,mt8188-sys-clock.yaml
index 4cf8d3a..db13d51 100644
--- a/dts/upstream/Bindings/clock/mediatek,mt8188-sys-clock.yaml
+++ b/dts/upstream/Bindings/clock/mediatek,mt8188-sys-clock.yaml
@@ -39,6 +39,9 @@
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/clock/milbeaut-clock.yaml b/dts/upstream/Bindings/clock/milbeaut-clock.yaml
index 0af1c56..d786f1e 100644
--- a/dts/upstream/Bindings/clock/milbeaut-clock.yaml
+++ b/dts/upstream/Bindings/clock/milbeaut-clock.yaml
@@ -40,38 +40,11 @@
additionalProperties: false
examples:
- # Clock controller node:
- |
- m10v-clk-ctrl@1d021000 {
+ clock-controller@1d021000 {
compatible = "socionext,milbeaut-m10v-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;
};
-
- # Required an external clock for Clock controller node:
- - |
- clocks {
- clki40mhz: clki40mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <40000000>;
- };
- /* other clocks */
- };
-
- # The clock consumer shall specify the desired clock-output of the clock
- # controller as below by specifying output-id in its "clk" phandle cell.
- # 2: uart
- # 4: 32-bit timer
- # 7: UHS-I/II
- - |
- serial@1e700010 {
- compatible = "socionext,milbeaut-usio-uart";
- reg = <0x1e700010 0x10>;
- interrupts = <0 141 0x4>, <0 149 0x4>;
- interrupt-names = "rx", "tx";
- clocks = <&clk 2>;
- };
-
...
diff --git a/dts/upstream/Bindings/clock/qcom,dispcc-sc8280xp.yaml b/dts/upstream/Bindings/clock/qcom,dispcc-sc8280xp.yaml
index 3cb996b..ffae037 100644
--- a/dts/upstream/Bindings/clock/qcom,dispcc-sc8280xp.yaml
+++ b/dts/upstream/Bindings/clock/qcom,dispcc-sc8280xp.yaml
@@ -40,31 +40,19 @@
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
power-domains:
items:
- description: MMCX power domain
required:
- compatible
- - reg
- clocks
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,dispcc-sm6350.yaml b/dts/upstream/Bindings/clock/qcom,dispcc-sm6350.yaml
index 8efac3f..46403b9 100644
--- a/dts/upstream/Bindings/clock/qcom,dispcc-sm6350.yaml
+++ b/dts/upstream/Bindings/clock/qcom,dispcc-sm6350.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Display Clock & Reset Controller on SM6350
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
@@ -37,28 +37,16 @@
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,dispcc-sm8x50.yaml b/dts/upstream/Bindings/clock/qcom,dispcc-sm8x50.yaml
index 59cc88a..53a5ab3 100644
--- a/dts/upstream/Bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/dts/upstream/Bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -27,6 +27,7 @@
- qcom,sm8350-dispcc
clocks:
+ minItems: 7
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
+ - description: Link clock from eDP PHY
+ - description: VCO DIV clock from eDP PHY
+ - description: Link clock from DP1 PHY
+ - description: VCO DIV clock from DP1 PHY
+ - description: Link clock from DP2 PHY
+ - description: VCO DIV clock from DP2 PHY
clock-names:
+ minItems: 7
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
@@ -45,18 +53,12 @@
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
+ - const: edp_phy_pll_link_clk
+ - const: edp_phy_pll_vco_div_clk
+ - const: dptx1_phy_pll_link_clk
+ - const: dptx1_phy_pll_vco_div_clk
+ - const: dptx2_phy_pll_link_clk
+ - const: dptx2_phy_pll_vco_div_clk
power-domains:
description:
@@ -70,14 +72,26 @@
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc8180x-dispcc
+ then:
+ properties:
+ clocks:
+ maxItems: 7
+ clock-names:
+ maxItems: 7
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/upstream/Bindings/clock/qcom,gcc-apq8064.yaml
index 1921117..27df7e3 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-apq8064.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-apq8064.yaml
@@ -69,6 +69,8 @@
const: 1
deprecated: true
+ '#power-domain-cells': false
+
required:
- compatible
@@ -81,7 +83,6 @@
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
thermal-sensor {
compatible = "qcom,msm8960-tsens";
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-apq8084.yaml b/dts/upstream/Bindings/clock/qcom,gcc-apq8084.yaml
index d846082..0a0a26d 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-apq8084.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-apq8084.yaml
@@ -51,6 +51,7 @@
required:
- compatible
+ - '#power-domain-cells'
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq4019.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq4019.yaml
index fb3957d..0120489 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-ipq4019.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq4019.yaml
@@ -34,6 +34,8 @@
- const: xo
- const: sleep_clk
+ '#power-domain-cells': false
+
required:
- compatible
@@ -45,7 +47,6 @@
compatible = "qcom,gcc-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml
index af5d883..4d2614d 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml
@@ -36,6 +36,8 @@
- const: xo
- const: sleep_clk
+ '#power-domain-cells': false
+
required:
- compatible
- clocks
@@ -51,7 +53,6 @@
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
};
...
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq8064.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq8064.yaml
index 93f3084..a715573 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-ipq8064.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq8064.yaml
@@ -46,6 +46,8 @@
allOf:
- $ref: /schemas/thermal/qcom-tsens.yaml#
+ '#power-domain-cells': false
+
required:
- compatible
- clocks
@@ -65,7 +67,6 @@
clock-names = "pxo", "cxo", "pll4";
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
tsens: thermal-sensor {
compatible = "qcom,ipq8064-tsens";
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
index 2d44ddc..38b9e42 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
@@ -39,6 +39,7 @@
required:
- compatible
+ - '#power-domain-cells'
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-mdm9607.yaml b/dts/upstream/Bindings/clock/qcom,gcc-mdm9607.yaml
new file mode 100644
index 0000000..d7da30b
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,gcc-mdm9607.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains.
+
+ See also::
+ include/dt-bindings/clock/qcom,gcc-mdm9607.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-mdm9607
+
+required:
+ - compatible
+ - '#power-domain-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@900000 {
+ compatible = "qcom,gcc-mdm9607";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-mdm9615.yaml b/dts/upstream/Bindings/clock/qcom,gcc-mdm9615.yaml
new file mode 100644
index 0000000..418dea3
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,gcc-mdm9615.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains.
+
+ See also::
+ include/dt-bindings/clock/qcom,gcc-mdm9615.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-mdm9615
+
+ clocks:
+ items:
+ - description: CXO clock
+ - description: PLL4 from LLC
+
+ '#power-domain-cells': false
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@900000 {
+ compatible = "qcom,gcc-mdm9615";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&cxo_board>,
+ <&lcc_pll4>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8660.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8660.yaml
index c9e9855..e03b6d0 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8660.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8660.yaml
@@ -34,6 +34,8 @@
- const: pxo
- const: cxo
+ '#power-domain-cells': false
+
required:
- compatible
@@ -47,7 +49,6 @@
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8909.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8909.yaml
index b914625..ce1f5a6 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8909.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8909.yaml
@@ -42,6 +42,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8916.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8916.yaml
index ad84c0f..258b6b9 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8916.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8916.yaml
@@ -48,6 +48,7 @@
required:
- compatible
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8953.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8953.yaml
index fe9fd4c..fe1f5f3 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8953.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8953.yaml
@@ -42,6 +42,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8974.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8974.yaml
index 1927aec..929fafc 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8974.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8974.yaml
@@ -41,6 +41,7 @@
required:
- compatible
+ - '#power-domain-cells'
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8976.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8976.yaml
index 62d6f1f..cd49704 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8976.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8976.yaml
@@ -49,6 +49,7 @@
- clocks
- clock-names
- vdd_gfx-supply
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8994.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8994.yaml
index 8f0f20c..10afe98 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8994.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8994.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Global Clock & Reset Controller on MSM8994
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@@ -35,6 +35,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8996.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8996.yaml
index 97523cc..013fd07 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8996.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8996.yaml
@@ -50,6 +50,7 @@
required:
- compatible
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-msm8998.yaml b/dts/upstream/Bindings/clock/qcom,gcc-msm8998.yaml
index 58f7fb2..abae658 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-msm8998.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-msm8998.yaml
@@ -38,6 +38,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-other.yaml b/dts/upstream/Bindings/clock/qcom,gcc-other.yaml
deleted file mode 100644
index 7d05f0f..0000000
--- a/dts/upstream/Bindings/clock/qcom,gcc-other.yaml
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Global Clock & Reset Controller
-
-maintainers:
- - Stephen Boyd <sboyd@kernel.org>
- - Taniya Das <quic_tdas@quicinc.com>
-
-description: |
- Qualcomm global clock control module provides the clocks, resets and power
- domains.
-
- See also::
- include/dt-bindings/clock/qcom,gcc-msm8953.h
- include/dt-bindings/clock/qcom,gcc-mdm9607.h
-
-allOf:
- - $ref: qcom,gcc.yaml#
-
-properties:
- compatible:
- enum:
- - qcom,gcc-mdm9607
-
-required:
- - compatible
-
-unevaluatedProperties: false
-
-examples:
- - |
- clock-controller@900000 {
- compatible = "qcom,gcc-mdm9607";
- reg = <0x900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-...
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-qcm2290.yaml b/dts/upstream/Bindings/clock/qcom,gcc-qcm2290.yaml
index c9bec46..38c4c8c 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-qcm2290.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-qcm2290.yaml
@@ -33,6 +33,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-qcs404.yaml b/dts/upstream/Bindings/clock/qcom,gcc-qcs404.yaml
index 7bc6c57..9475546 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-qcs404.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-qcs404.yaml
@@ -40,6 +40,7 @@
required:
- compatible
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sc7180.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sc7180.yaml
index 7aae21a..1847bbe 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sc7180.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sc7180.yaml
@@ -40,6 +40,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sc7280.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sc7280.yaml
index c4ca08d..4e4f68b 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sc7280.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sc7280.yaml
@@ -51,6 +51,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sc8180x.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sc8180x.yaml
index a1085ef..b4784ec 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sc8180x.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sc8180x.yaml
@@ -40,6 +40,7 @@
- clocks
- clock-names
- power-domains
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sc8280xp.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sc8280xp.yaml
index 5681e53..5cfde8a 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sc8280xp.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sc8280xp.yaml
@@ -65,6 +65,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sdm660.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sdm660.yaml
index 52e7412..724ce04 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sdm660.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sdm660.yaml
@@ -40,6 +40,7 @@
required:
- compatible
+ - '#power-domain-cells'
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sdm845.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sdm845.yaml
index 0595da0..ef0a204 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sdm845.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sdm845.yaml
@@ -35,6 +35,7 @@
required:
- compatible
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sdx55.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sdx55.yaml
index 428e954..30819f3 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sdx55.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sdx55.yaml
@@ -34,6 +34,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sdx65.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sdx65.yaml
index 523e18d..9154492 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sdx65.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sdx65.yaml
@@ -39,6 +39,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm6115.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm6115.yaml
index a5ad0a3..ecb69c7 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm6115.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm6115.yaml
@@ -33,6 +33,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm6125.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm6125.yaml
index 8e37623..1fe68e0 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm6125.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm6125.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Global Clock & Reset Controller on SM6125
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@@ -33,6 +33,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm6350.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm6350.yaml
index d1b26ab..78e232f 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm6350.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm6350.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Global Clock & Reset Controller on SM6350
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@@ -35,6 +35,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm8150.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm8150.yaml
index 58ccb7d..1dcf97c 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm8150.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm8150.yaml
@@ -34,6 +34,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm8250.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm8250.yaml
index 5d77c09..979ff0a 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm8250.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm8250.yaml
@@ -36,6 +36,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm8350.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm8350.yaml
index b4fdde7..594e87f 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm8350.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm8350.yaml
@@ -55,6 +55,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-sm8450.yaml b/dts/upstream/Bindings/clock/qcom,gcc-sm8450.yaml
index 75259f4..d848361 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-sm8450.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-sm8450.yaml
@@ -49,6 +49,7 @@
- compatible
- clocks
- clock-names
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,gcc.yaml b/dts/upstream/Bindings/clock/qcom,gcc.yaml
index 7888251..513d6fd 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc.yaml
@@ -35,7 +35,6 @@
- reg
- '#clock-cells'
- '#reset-cells'
- - '#power-domain-cells'
additionalProperties: true
diff --git a/dts/upstream/Bindings/clock/qcom,gpucc-sdm660.yaml b/dts/upstream/Bindings/clock/qcom,gpucc-sdm660.yaml
index 0518ea9..79bb90d 100644
--- a/dts/upstream/Bindings/clock/qcom,gpucc-sdm660.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gpucc-sdm660.yaml
@@ -33,28 +33,16 @@
- const: gcc_gpu_gpll0_clk
- const: gcc_gpu_gpll0_div_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,gpucc.yaml b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
index f57aced..0858fd6 100644
--- a/dts/upstream/Bindings/clock/qcom,gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
@@ -56,25 +56,10 @@
vdd-gfx-supply:
description: Regulator supply for the VDD_GFX pads
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
# Require that power-domains and vdd-gfx-supply are not both present
@@ -83,7 +68,10 @@
- power-domains
- vdd-gfx-supply
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,ipq5018-gcc.yaml b/dts/upstream/Bindings/clock/qcom,ipq5018-gcc.yaml
index ef84a0c..489d0fc 100644
--- a/dts/upstream/Bindings/clock/qcom,ipq5018-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,ipq5018-gcc.yaml
@@ -33,6 +33,8 @@
- description: UNIPHY RX clock source
- description: UNIPHY TX clk source
+ '#power-domain-cells': false
+
required:
- compatible
- clocks
@@ -58,6 +60,5 @@
<&uniphy_tx_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
};
...
diff --git a/dts/upstream/Bindings/clock/qcom,ipq5332-gcc.yaml b/dts/upstream/Bindings/clock/qcom,ipq5332-gcc.yaml
index 718fe06..adc30d8 100644
--- a/dts/upstream/Bindings/clock/qcom,ipq5332-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,ipq5332-gcc.yaml
@@ -30,6 +30,8 @@
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
- description: USB PCIE wrapper pipe clock source
+ '#power-domain-cells': false
+
required:
- compatible
- clocks
@@ -47,7 +49,6 @@
<&pcie_2lane_phy_pipe_clk_x1>,
<&usb_pcie_wrapper_pipe_clk>;
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
};
...
diff --git a/dts/upstream/Bindings/clock/qcom,ipq9574-gcc.yaml b/dts/upstream/Bindings/clock/qcom,ipq9574-gcc.yaml
index 944a0ea..27ae993 100644
--- a/dts/upstream/Bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,ipq9574-gcc.yaml
@@ -33,6 +33,11 @@
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
+ '#power-domain-cells': false
+
+ '#interconnect-cells':
+ const: 1
+
required:
- compatible
- clocks
@@ -57,6 +62,5 @@
<&usb3phy_0_cc_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
};
...
diff --git a/dts/upstream/Bindings/clock/qcom,msm8998-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,msm8998-gpucc.yaml
index 7b271ae..b9b218e 100644
--- a/dts/upstream/Bindings/clock/qcom,msm8998-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,msm8998-gpucc.yaml
@@ -29,28 +29,16 @@
- const: xo
- const: gpll0
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,qca8k-nsscc.yaml b/dts/upstream/Bindings/clock/qcom,qca8k-nsscc.yaml
new file mode 100644
index 0000000..6147338
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,qca8k-nsscc.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Luo Jie <quic_luoj@quicinc.com>
+
+description: |
+ Qualcomm NSS clock control module provides the clocks and resets
+ on QCA8386(switch mode)/QCA8084(PHY mode)
+
+ See also::
+ include/dt-bindings/clock/qcom,qca8k-nsscc.h
+ include/dt-bindings/reset/qcom,qca8k-nsscc.h
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,qca8084-nsscc
+ - items:
+ - enum:
+ - qcom,qca8082-nsscc
+ - qcom,qca8085-nsscc
+ - qcom,qca8384-nsscc
+ - qcom,qca8385-nsscc
+ - qcom,qca8386-nsscc
+ - const: qcom,qca8084-nsscc
+
+ clocks:
+ items:
+ - description: Chip reference clock source
+ - description: UNIPHY0 RX 312P5M/125M clock source
+ - description: UNIPHY0 TX 312P5M/125M clock source
+ - description: UNIPHY1 RX 312P5M/125M clock source
+ - description: UNIPHY1 TX 312P5M/125M clock source
+ - description: UNIPHY1 RX 312P5M clock source
+ - description: UNIPHY1 TX 312P5M clock source
+
+ reg:
+ items:
+ - description: MDIO bus address for Clock & Reset Controller register
+
+ reset-gpios:
+ description: GPIO connected to the chip
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reset-gpios
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-controller@18 {
+ compatible = "qcom,qca8084-nsscc";
+ reg = <0x18>;
+ reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
+ clocks = <&pcs0_pll>,
+ <&qca8k_uniphy0_rx>,
+ <&qca8k_uniphy0_tx>,
+ <&qca8k_uniphy1_rx>,
+ <&qca8k_uniphy1_tx>,
+ <&qca8k_uniphy1_rx312p5m>,
+ <&qca8k_uniphy1_tx312p5m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,qcm2290-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,qcm2290-dispcc.yaml
index 4a00f2d..243be4f 100644
--- a/dts/upstream/Bindings/clock/qcom,qcm2290-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,qcm2290-dispcc.yaml
@@ -37,28 +37,16 @@
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,qcm2290-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,qcm2290-gpucc.yaml
new file mode 100644
index 0000000..7348808
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,qcm2290-gpucc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on QCM2290
+
+maintainers:
+ - Konrad Dybcio <konradybcio@kernel.org>
+
+description: |
+ Qualcomm graphics clock control module provides the clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also::
+ include/dt-bindings/clock/qcom,qcm2290-gpucc.h
+
+properties:
+ compatible:
+ const: qcom,qcm2290-gpucc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AHB interface clock,
+ - description: SoC CXO clock
+ - description: GPLL0 main branch source
+ - description: GPLL0 div branch source
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the CX power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing required CX performance point.
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@5990000 {
+ compatible = "qcom,qcm2290-gpucc";
+ reg = <0x0 0x05990000 0x0 0x9000>;
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,qdu1000-gcc.yaml b/dts/upstream/Bindings/clock/qcom,qdu1000-gcc.yaml
index d712b1a..86befef 100644
--- a/dts/upstream/Bindings/clock/qcom,qdu1000-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,qdu1000-gcc.yaml
@@ -31,6 +31,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sa8775p-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sa8775p-gcc.yaml
index 0f641c2..addbd32 100644
--- a/dts/upstream/Bindings/clock/qcom,sa8775p-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sa8775p-gcc.yaml
@@ -46,6 +46,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sc7180-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sc7180-dispcc.yaml
index 1c9ce30..0d8ea44 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7180-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7180-dispcc.yaml
@@ -37,28 +37,16 @@
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sc7280-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sc7280-dispcc.yaml
index c42b0ef..2317766 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7280-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7280-dispcc.yaml
@@ -41,28 +41,16 @@
- const: edp_phy_pll_link_clk
- const: edp_phy_pll_vco_div_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sdm845-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sdm845-dispcc.yaml
index 719844d..220f400 100644
--- a/dts/upstream/Bindings/clock/qcom,sdm845-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sdm845-dispcc.yaml
@@ -46,28 +46,16 @@
- const: dp_link_clk_divsel_ten
- const: dp_vco_divided_clk_src_mux
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sdx75-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sdx75-gcc.yaml
index 98921fa..567182a 100644
--- a/dts/upstream/Bindings/clock/qcom,sdx75-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sdx75-gcc.yaml
@@ -41,6 +41,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sm4450-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm4450-gcc.yaml
index 5953c8d..0ac92d7 100644
--- a/dts/upstream/Bindings/clock/qcom,sm4450-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm4450-gcc.yaml
@@ -32,6 +32,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sm6115-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm6115-dispcc.yaml
index f802a2e..00be366 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6115-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6115-dispcc.yaml
@@ -28,27 +28,15 @@
- description: Pixel clock from DSI PHY0
- description: GPLL0 DISP DIV clock from GCC
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm6115-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm6115-gpucc.yaml
index cf19f44..4ff17a9 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6115-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6115-gpucc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Graphics Clock & Reset Controller on SM6115
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
diff --git a/dts/upstream/Bindings/clock/qcom,sm6125-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm6125-gpucc.yaml
index 374a184..10a9c96 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6125-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6125-gpucc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Graphics Clock & Reset Controller on SM6125
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm graphics clock control module provides clocks and power domains on
diff --git a/dts/upstream/Bindings/clock/qcom,sm6350-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm6350-camcc.yaml
index fd6658c..c03b30f 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6350-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6350-camcc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Camera Clock & Reset Controller on SM6350
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
diff --git a/dts/upstream/Bindings/clock/qcom,sm6375-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm6375-dispcc.yaml
index 183b1c7..3cd422a 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6375-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6375-dispcc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Display Clock & Reset Controller on SM6375
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
diff --git a/dts/upstream/Bindings/clock/qcom,sm6375-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm6375-gcc.yaml
index 295d4bb..de4e906 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6375-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6375-gcc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Global Clock & Reset Controller on SM6375
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@@ -31,6 +31,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/clock/qcom,sm6375-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm6375-gpucc.yaml
index cf4cad7..d9dd479 100644
--- a/dts/upstream/Bindings/clock/qcom,sm6375-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm6375-gpucc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Graphics Clock & Reset Controller on SM6375
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
diff --git a/dts/upstream/Bindings/clock/qcom,sm7150-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm7150-camcc.yaml
new file mode 100644
index 0000000..7be4b10
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm7150-camcc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on SM7150
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+ - David Wronek <david@mainlining.org>
+ - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+ Qualcomm camera clock control module provides the clocks, resets and power
+ domains on SM7150.
+
+ See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-camcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board XO Active-Only source
+ - description: Sleep clock source
+
+ power-domains:
+ maxItems: 1
+ description:
+ CX power domain.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@ad00000 {
+ compatible = "qcom,sm7150-camcc";
+ reg = <0xad00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm7150-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm7150-dispcc.yaml
new file mode 100644
index 0000000..b8d6e1d
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm7150-dispcc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller for SM7150
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+ - David Wronek <david@mainlining.org>
+ - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+ Qualcomm display clock control module provides the clocks, resets and power
+ domains on SM7150.
+
+ See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: GPLL0 source from GCC
+ - description: Sleep clock source
+ - description: Byte clock from MDSS DSI PHY0
+ - description: Pixel clock from MDSS DSI PHY0
+ - description: Byte clock from MDSS DSI PHY1
+ - description: Pixel clock from MDSS DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ power-domains:
+ maxItems: 1
+ description:
+ CX power domain.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm7150-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm7150-dispcc";
+ reg = <0x0af00000 0x200000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&sleep_clk>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm7150-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm7150-gcc.yaml
index 0eb76d9..4d7bbbf 100644
--- a/dts/upstream/Bindings/clock/qcom,sm7150-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm7150-gcc.yaml
@@ -30,6 +30,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sm7150-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sm7150-videocc.yaml
new file mode 100644
index 0000000..037ffc7
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm7150-videocc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SM7150
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+ - David Wronek <david@mainlining.org>
+ - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+ Qualcomm video clock control module provides the clocks, resets and power
+ domains on SM7150.
+
+ See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-videocc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+
+ power-domains:
+ maxItems: 1
+ description:
+ CX power domain.
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ videocc: clock-controller@ab00000 {
+ compatible = "qcom,sm7150-videocc";
+ reg = <0x0ab00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm8350-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sm8350-videocc.yaml
index 46d1d91..5c2ecec 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8350-videocc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8350-videocc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm SM8350 Video Clock & Reset Controller
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm video clock control module provides the clocks, resets and power
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
index fa0e5b6..f58edfc 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -8,15 +8,17 @@
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+ - Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
- See also::
+ See also:
+ include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
- include/dt-bindings/clock/qcom,sc8280xp-camcc.h
+ include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
@@ -28,6 +30,7 @@
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
+ - qcom,sm8650-camcc
- qcom,x1e80100-camcc
clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-dispcc.yaml
index 2f22310..4794c53 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-dispcc.yaml
@@ -40,18 +40,6 @@
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@@ -64,13 +52,13 @@
required:
- compatible
- - reg
- clocks
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
index 3697430..d10bb00 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Graphics Clock & Reset Controller on SM8450
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
@@ -34,27 +34,15 @@
- description: GPLL0 main branch source
- description: GPLL0 div branch source
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- clocks
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml
index bad8f01..b2792b4 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-videocc.yaml
@@ -8,21 +8,22 @@
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
+ - Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.
- See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
+ See also:
+ include/dt-bindings/clock/qcom,sm8450-videocc.h
+ include/dt-bindings/clock/qcom,sm8650-videocc.h
properties:
compatible:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
-
- reg:
- maxItems: 1
+ - qcom,sm8650-videocc
clocks:
items:
@@ -39,26 +40,17 @@
description:
A phandle to an OPP node describing required MMCX performance point.
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
required:
- compatible
- - reg
- clocks
- power-domains
- required-opps
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
index bad0260..c17035a1 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
@@ -45,18 +45,6 @@
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@@ -69,13 +57,13 @@
required:
- compatible
- - reg
- clocks
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-gcc.yaml
index 0c706de..d83b64d 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-gcc.yaml
@@ -34,6 +34,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml
index b54761c..976f29c 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml
@@ -35,6 +35,7 @@
required:
- compatible
- clocks
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qcom,videocc.yaml b/dts/upstream/Bindings/clock/qcom,videocc.yaml
index 6999e36..340c7e5 100644
--- a/dts/upstream/Bindings/clock/qcom,videocc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,videocc.yaml
@@ -37,18 +37,6 @@
minItems: 1
maxItems: 3
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@@ -61,21 +49,19 @@
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- '#power-domain-cells'
allOf:
+ - $ref: qcom,gcc.yaml#
+
- if:
properties:
compatible:
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
- - qcom,sm8150-videocc
then:
properties:
clocks:
@@ -105,6 +91,22 @@
properties:
compatible:
enum:
+ - qcom,sm8150-videocc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: AHB
+ - description: Board XO source
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+
+ - if:
+ properties:
+ compatible:
+ enum:
- qcom,sm8250-videocc
then:
properties:
@@ -119,7 +121,7 @@
- const: bi_tcxo
- const: bi_tcxo_ao
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
index 14a796d..5951a60 100644
--- a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
@@ -41,6 +41,7 @@
- compatible
- clocks
- power-domains
+ - '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
diff --git a/dts/upstream/Bindings/clock/qoriq-clock.txt b/dts/upstream/Bindings/clock/qoriq-clock.txt
deleted file mode 100644
index 10119d9..0000000
--- a/dts/upstream/Bindings/clock/qoriq-clock.txt
+++ /dev/null
@@ -1,212 +0,0 @@
-* Clock Block on Freescale QorIQ Platforms
-
-Freescale QorIQ chips take primary clocking input from the external
-SYSCLK signal. The SYSCLK input (frequency) is multiplied using
-multiple phase locked loops (PLL) to create a variety of frequencies
-which can then be passed to a variety of internal logic, including
-cores and peripheral IP blocks.
-Please refer to the Reference Manual for details.
-
-All references to "1.0" and "2.0" refer to the QorIQ chassis version to
-which the chip complies.
-
-Chassis Version Example Chips
---------------- -------------
-1.0 p4080, p5020, p5040
-2.0 t4240, b4860
-
-1. Clock Block Binding
-
-Required properties:
-- compatible: Should contain a chip-specific clock block compatible
- string and (if applicable) may contain a chassis-version clock
- compatible string.
-
- Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
- * "fsl,p2041-clockgen"
- * "fsl,p3041-clockgen"
- * "fsl,p4080-clockgen"
- * "fsl,p5020-clockgen"
- * "fsl,p5040-clockgen"
- * "fsl,t1023-clockgen"
- * "fsl,t1024-clockgen"
- * "fsl,t1040-clockgen"
- * "fsl,t1042-clockgen"
- * "fsl,t2080-clockgen"
- * "fsl,t2081-clockgen"
- * "fsl,t4240-clockgen"
- * "fsl,b4420-clockgen"
- * "fsl,b4860-clockgen"
- * "fsl,ls1012a-clockgen"
- * "fsl,ls1021a-clockgen"
- * "fsl,ls1028a-clockgen"
- * "fsl,ls1043a-clockgen"
- * "fsl,ls1046a-clockgen"
- * "fsl,ls1088a-clockgen"
- * "fsl,ls2080a-clockgen"
- * "fsl,lx2160a-clockgen"
- Chassis-version clock strings include:
- * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
- * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
-- reg: Describes the address of the device's resources within the
- address space defined by its parent bus, and resource zero
- represents the clock register set
-
-Optional properties:
-- ranges: Allows valid translation between child's address space and
- parent's. Must be present if the device has sub-nodes.
-- #address-cells: Specifies the number of cells used to represent
- physical base addresses. Must be present if the device has
- sub-nodes and set to 1 if present
-- #size-cells: Specifies the number of cells used to represent
- the size of an address. Must be present if the device has
- sub-nodes and set to 1 if present
-- clock-frequency: Input system clock frequency (SYSCLK)
-- clocks: If clock-frequency is not specified, sysclk may be provided
- as an input clock. Either clock-frequency or clocks must be
- provided.
- A second input clock, called "coreclk", may be provided if
- core PLLs are based on a different input clock from the
- platform PLL.
-- clock-names: Required if a coreclk is present. Valid names are
- "sysclk" and "coreclk".
-
-2. Clock Provider
-
-The clockgen node should act as a clock provider, though in older device
-trees the children of the clockgen node are the clock providers.
-
-When the clockgen node is a clock provider, #clock-cells = <2>.
-The first cell of the clock specifier is the clock type, and the
-second cell is the clock index for the specified type.
-
- Type# Name Index Cell
- 0 sysclk must be 0
- 1 cmux index (n in CLKCnCSR)
- 2 hwaccel index (n in CLKCGnHWACSR)
- 3 fman 0 for fm1, 1 for fm2
- 4 platform pll n=pll/(n+1). For example, when n=1,
- that means output_freq=PLL_freq/2.
- 5 coreclk must be 0
-
-3. Example
-
- clockgen: global-utilities@e1000 {
- compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
- clock-frequency = <133333333>;
- reg = <0xe1000 0x1000>;
- #clock-cells = <2>;
- };
-
- fman@400000 {
- ...
- clocks = <&clockgen 3 0>;
- ...
- };
-}
-4. Legacy Child Nodes
-
-NOTE: These nodes are deprecated. Kernels should continue to support
-device trees with these nodes, but new device trees should not use them.
-
-Most of the bindings are from the common clock binding[1].
- [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : Should include one of the following:
- * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
- * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
- * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
- * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
- * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
- * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
-- #clock-cells: From common clock binding. The number of cells in a
- clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
- clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
- For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
- clock-specifier cell may take the following values:
- * 0 - equal to the PLL frequency
- * 1 - equal to the PLL frequency divided by 2
- * 2 - equal to the PLL frequency divided by 4
-
-Recommended properties:
-- clocks: Should be the phandle of input parent clock
-- clock-names: From common clock binding, indicates the clock name
-- clock-output-names: From common clock binding, indicates the names of
- output clocks
-- reg: Should be the offset and length of clock block base address.
- The length should be 4.
-
-Legacy Example:
-/ {
- clockgen: global-utilities@e1000 {
- compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- clock-frequency = <133333333>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
-
- platform-pll: platform-pll@c00 {
- #clock-cells = <1>;
- reg = <0xc00 0x4>;
- compatible = "fsl,qoriq-platform-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "platform-pll", "platform-pll-div2";
- };
- };
-};
-
-Example for legacy clock consumer:
-
-/ {
- cpu0: PowerPC,e5500@0 {
- ...
- clocks = <&mux0>;
- ...
- };
-};
diff --git a/dts/upstream/Bindings/clock/renesas,rzg2l-cpg.yaml b/dts/upstream/Bindings/clock/renesas,rzg2l-cpg.yaml
index 4e3b0c4..0440f23 100644
--- a/dts/upstream/Bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/dts/upstream/Bindings/clock/renesas,rzg2l-cpg.yaml
@@ -62,7 +62,7 @@
'#reset-cells':
description:
- The single reset specifier cell must be the module number, as defined in
+ The single reset specifier cell must be the reset number, as defined in
<dt-bindings/clock/r9a0*-cpg.h>.
const: 1
diff --git a/dts/upstream/Bindings/clock/sophgo,sg2042-clkgen.yaml b/dts/upstream/Bindings/clock/sophgo,sg2042-clkgen.yaml
new file mode 100644
index 0000000..e7a9255
--- /dev/null
+++ b/dts/upstream/Bindings/clock/sophgo,sg2042-clkgen.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Clock Generator for divider/mux/gate
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-clkgen
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main PLL
+ - description: Fixed PLL
+ - description: DDR PLL 0
+ - description: DDR PLL 1
+
+ clock-names:
+ items:
+ - const: mpll
+ - const: fpll
+ - const: dpll0
+ - const: dpll1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@30012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x30012000 0x1000>;
+ clocks = <&pllclk 0>,
+ <&pllclk 1>,
+ <&pllclk 2>,
+ <&pllclk 3>;
+ clock-names = "mpll",
+ "fpll",
+ "dpll0",
+ "dpll1";
+ #clock-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/sophgo,sg2042-pll.yaml b/dts/upstream/Bindings/clock/sophgo,sg2042-pll.yaml
new file mode 100644
index 0000000..1a417a6
--- /dev/null
+++ b/dts/upstream/Bindings/clock/sophgo,sg2042-pll.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PLL Clock Generator
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
+ - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
+
+ clock-names:
+ items:
+ - const: cgi_main
+ - const: cgi_dpll0
+ - const: cgi_dpll1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000000 {
+ compatible = "sophgo,sg2042-pll";
+ reg = <0x10000000 0x10000>;
+ clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+ clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
+ #clock-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/sophgo,sg2042-rpgate.yaml b/dts/upstream/Bindings/clock/sophgo,sg2042-rpgate.yaml
new file mode 100644
index 0000000..1491fb8
--- /dev/null
+++ b/dts/upstream/Bindings/clock/sophgo,sg2042-rpgate.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-rpgate
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Gate clock for RP subsystem
+
+ clock-names:
+ items:
+ - const: rpgate
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@20000000 {
+ compatible = "sophgo,sg2042-rpgate";
+ reg = <0x20000000 0x10000>;
+ clocks = <&clkgen 85>;
+ clock-names = "rpgate";
+ #clock-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/sprd,sc9860-clk.txt b/dts/upstream/Bindings/clock/sprd,sc9860-clk.txt
deleted file mode 100644
index aaaf02c..0000000
--- a/dts/upstream/Bindings/clock/sprd,sc9860-clk.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-Spreadtrum SC9860 Clock Binding
-------------------------
-
-Required properties:
-- compatible: should contain the following compatible strings:
- - "sprd,sc9860-pmu-gate"
- - "sprd,sc9860-pll"
- - "sprd,sc9860-ap-clk"
- - "sprd,sc9860-aon-prediv"
- - "sprd,sc9860-apahb-gate"
- - "sprd,sc9860-aon-gate"
- - "sprd,sc9860-aonsecure-clk"
- - "sprd,sc9860-agcp-gate"
- - "sprd,sc9860-gpu-clk"
- - "sprd,sc9860-vsp-clk"
- - "sprd,sc9860-vsp-gate"
- - "sprd,sc9860-cam-clk"
- - "sprd,sc9860-cam-gate"
- - "sprd,sc9860-disp-clk"
- - "sprd,sc9860-disp-gate"
- - "sprd,sc9860-apapb-gate"
-
-- #clock-cells: must be 1
-
-- clocks : Should be the input parent clock(s) phandle for the clock, this
- property here just simply shows which clock group the clocks'
- parents are in, since each clk node would represent many clocks
- which are defined in the driver. The detailed dependency
- relationship (i.e. how many parents and which are the parents)
- are implemented in driver code.
-
-Optional properties:
-
-- reg: Contain the registers base address and length. It must be configured
- only if no 'sprd,syscon' under the node.
-
-- sprd,syscon: phandle to the syscon which is in the same address area with
- the clock, and so we can get regmap for the clocks from the
- syscon device.
-
-Example:
-
- pmu_gate: pmu-gate {
- compatible = "sprd,sc9860-pmu-gate";
- sprd,syscon = <&pmu_regs>;
- clocks = <&ext_26m>;
- #clock-cells = <1>;
- };
-
- pll: pll {
- compatible = "sprd,sc9860-pll";
- sprd,syscon = <&ana_regs>;
- clocks = <&pmu_gate 0>;
- #clock-cells = <1>;
- };
-
- ap_clk: clock-controller@20000000 {
- compatible = "sprd,sc9860-ap-clk";
- reg = <0 0x20000000 0 0x400>;
- clocks = <&ext_26m>, <&pll 0>,
- <&pmu_gate 0>;
- #clock-cells = <1>;
- };
diff --git a/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml b/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml
new file mode 100644
index 0000000..502cd72
--- /dev/null
+++ b/dts/upstream/Bindings/clock/sprd,sc9860-clk.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC9860 clock
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - sprd,sc9860-agcp-gate
+ - sprd,sc9860-aonsecure-clk
+ - sprd,sc9860-aon-gate
+ - sprd,sc9860-aon-prediv
+ - sprd,sc9860-apahb-gate
+ - sprd,sc9860-apapb-gate
+ - sprd,sc9860-ap-clk
+ - sprd,sc9860-cam-clk
+ - sprd,sc9860-cam-gate
+ - sprd,sc9860-disp-clk
+ - sprd,sc9860-disp-gate
+ - sprd,sc9860-gpu-clk
+ - sprd,sc9860-pll
+ - sprd,sc9860-pmu-gate
+ - sprd,sc9860-vsp-clk
+ - sprd,sc9860-vsp-gate
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ '#clock-cells':
+ const: 1
+
+ sprd,syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the syscon which is in the same address area with the
+ clock, and so we can get regmap for the clocks from the syscon device
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,sc9860-agcp-gate
+ - sprd,sc9860-aon-gate
+ - sprd,sc9860-apahb-gate
+ - sprd,sc9860-apapb-gate
+ - sprd,sc9860-cam-gate
+ - sprd,sc9860-disp-gate
+ - sprd,sc9860-gpu-clk
+ - sprd,sc9860-pll
+ - sprd,sc9860-pmu-gate
+ - sprd,sc9860-vsp-gate
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,sc9860-aonsecure-clk
+ - sprd,sc9860-cam-clk
+ - sprd,sc9860-disp-clk
+ - sprd,sc9860-vsp-clk
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,sc9860-aon-prediv
+ - sprd,sc9860-ap-clk
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,sc9860-aonsecure-clk
+ - sprd,sc9860-aon-prediv
+ - sprd,sc9860-ap-clk
+ - sprd,sc9860-cam-clk
+ - sprd,sc9860-disp-clk
+ - sprd,sc9860-gpu-clk
+ - sprd,sc9860-vsp-clk
+ then:
+ required:
+ - reg
+ properties:
+ sprd,syscon: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sprd,sc9860-agcp-gate
+ - sprd,sc9860-aon-gate
+ - sprd,sc9860-apahb-gate
+ - sprd,sc9860-apapb-gate
+ - sprd,sc9860-cam-gate
+ - sprd,sc9860-disp-gate
+ - sprd,sc9860-pll
+ - sprd,sc9860-pmu-gate
+ - sprd,sc9860-vsp-gate
+ then:
+ required:
+ - sprd,syscon
+ properties:
+ reg: false
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu-gate {
+ compatible = "sprd,sc9860-pmu-gate";
+ clocks = <&ext_26m>;
+ #clock-cells = <1>;
+ sprd,syscon = <&pmu_regs>;
+ };
+
+ clock-controller@20000000 {
+ compatible = "sprd,sc9860-ap-clk";
+ reg = <0 0x20000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/clock/stericsson,abx500.txt b/dts/upstream/Bindings/clock/stericsson,abx500.txt
deleted file mode 100644
index dbaa886..0000000
--- a/dts/upstream/Bindings/clock/stericsson,abx500.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Clock bindings for ST-Ericsson ABx500 clocks
-
-Required properties :
-- compatible : shall contain the following:
- "stericsson,ab8500-clk"
-- #clock-cells should be <1>
-
-The ABx500 clocks need to be placed as a subnode of an AB8500
-device node, see mfd/ab8500.txt
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/ste-ab8500.h header and can be used in device
-tree sources.
-
-Example:
-
-clock-controller {
- compatible = "stericsson,ab8500-clk";
- #clock-cells = <1>;
-};
diff --git a/dts/upstream/Bindings/clock/thead,th1520-clk-ap.yaml b/dts/upstream/Bindings/clock/thead,th1520-clk-ap.yaml
new file mode 100644
index 0000000..0129bd0
--- /dev/null
+++ b/dts/upstream/Bindings/clock/thead,th1520-clk-ap.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD TH1520 AP sub-system clock controller
+
+description: |
+ The T-HEAD TH1520 AP sub-system clock controller configures the
+ CPU, DPU, GMAC and TEE PLLs.
+
+ SoC reference manual
+ https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
+
+maintainers:
+ - Jisheng Zhang <jszhang@kernel.org>
+ - Wei Fu <wefu@redhat.com>
+ - Drew Fustini <dfustini@tenstorrent.com>
+
+properties:
+ compatible:
+ const: thead,th1520-clk-ap
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: main oscillator (24MHz)
+
+ "#clock-cells":
+ const: 1
+ description:
+ See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/thead,th1520-clk-ap.h>
+ clock-controller@ef010000 {
+ compatible = "thead,th1520-clk-ap";
+ reg = <0xef010000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/ti,sci-clk.yaml b/dts/upstream/Bindings/clock/ti,sci-clk.yaml
index 0a9d6a4..66e8e66 100644
--- a/dts/upstream/Bindings/clock/ti,sci-clk.yaml
+++ b/dts/upstream/Bindings/clock/ti,sci-clk.yaml
@@ -36,7 +36,7 @@
The second cell should contain the clock ID.
- Please see http://processors.wiki.ti.com/index.php/TISCI for
+ Please see https://software-dl.ti.com/tisci/esd/latest/index.html for
protocol documentation for the values to be used for different devices.
additionalProperties: false
diff --git a/dts/upstream/Bindings/clock/ti-keystone-pllctrl.txt b/dts/upstream/Bindings/clock/ti-keystone-pllctrl.txt
deleted file mode 100644
index c35cb6c..0000000
--- a/dts/upstream/Bindings/clock/ti-keystone-pllctrl.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Device tree bindings for Texas Instruments keystone pll controller
-
-The main pll controller used to drive theC66x CorePacs, the switch fabric,
-and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
-the NETCP modules) requires a PLL Controller to manage the various clock
-divisions, gating, and synchronization.
-
-Required properties:
-
-- compatible: "ti,keystone-pllctrl", "syscon"
-
-- reg: contains offset/length value for pll controller
- registers space.
-
-Example:
-
-pllctrl: pll-controller@02310000 {
- compatible = "ti,keystone-pllctrl", "syscon";
- reg = <0x02310000 0x200>;
-};
diff --git a/dts/upstream/Bindings/counter/ti-eqep.yaml b/dts/upstream/Bindings/counter/ti-eqep.yaml
index 85f1ff8..c882ab5 100644
--- a/dts/upstream/Bindings/counter/ti-eqep.yaml
+++ b/dts/upstream/Bindings/counter/ti-eqep.yaml
@@ -11,7 +11,9 @@
properties:
compatible:
- const: ti,am3352-eqep
+ enum:
+ - ti,am3352-eqep
+ - ti,am62-eqep
reg:
maxItems: 1
@@ -21,19 +23,35 @@
maxItems: 1
clocks:
- description: The clock that determines the SYSCLKOUT rate for the eQEP
- peripheral.
+ description: The functional and interface clock that determines the clock
+ rate for the eQEP peripheral.
maxItems: 1
clock-names:
const: sysclkout
+ power-domains:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,am62-eqep
+ then:
+ properties:
+ clock-names: false
+
+ required:
+ - power-domains
+
required:
- compatible
- reg
- interrupts
- clocks
- - clock-names
additionalProperties: false
@@ -43,7 +61,6 @@
compatible = "ti,am3352-eqep";
reg = <0x180 0x80>;
clocks = <&l4ls_gclk>;
- clock-names = "sysclkout";
interrupts = <79>;
};
diff --git a/dts/upstream/Bindings/crypto/allwinner,sun8i-ce.yaml b/dts/upstream/Bindings/crypto/allwinner,sun8i-ce.yaml
index 4287678..da47b60 100644
--- a/dts/upstream/Bindings/crypto/allwinner,sun8i-ce.yaml
+++ b/dts/upstream/Bindings/crypto/allwinner,sun8i-ce.yaml
@@ -18,6 +18,7 @@
- allwinner,sun50i-a64-crypto
- allwinner,sun50i-h5-crypto
- allwinner,sun50i-h6-crypto
+ - allwinner,sun50i-h616-crypto
reg:
maxItems: 1
@@ -49,6 +50,7 @@
compatible:
enum:
- allwinner,sun20i-d1-crypto
+ - allwinner,sun50i-h616-crypto
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
index 0c85894..84d68b8 100644
--- a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -71,6 +71,10 @@
- const: iahb
- const: venci
+ power-domains:
+ maxItems: 1
+ description: phandle to the associated power domain
+
resets:
minItems: 3
@@ -129,6 +133,7 @@
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
clock-names = "isfr", "iahb", "venci";
+ power-domains = <&pd_vpu>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/Bindings/display/bridge/synopsys,dw-hdmi.yaml b/dts/upstream/Bindings/display/bridge/synopsys,dw-hdmi.yaml
index 4b7e54a..3348138 100644
--- a/dts/upstream/Bindings/display/bridge/synopsys,dw-hdmi.yaml
+++ b/dts/upstream/Bindings/display/bridge/synopsys,dw-hdmi.yaml
@@ -45,6 +45,19 @@
- const: isfr
additionalItems: true
+ ddc-i2c-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ deprecated: true
+ description:
+ The HDMI DDC bus can be connected to either a system I2C master or the
+ functionally-reduced I2C master contained in the DWC HDMI. When connected
+ to a system I2C master this property contains a phandle to that I2C
+ master controller.
+
+ This property is deprecated, the system I2C master controller should
+ be referenced through the ddc-i2c-bus property of the HDMI connector
+ node.
+
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml b/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml
index ae894d9..2ad0cd6 100644
--- a/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml
+++ b/dts/upstream/Bindings/display/bridge/toshiba,tc358767.yaml
@@ -25,8 +25,8 @@
reg:
enum:
- - 0x68
- 0x0f
+ - 0x68
description: |
i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
diff --git a/dts/upstream/Bindings/display/imx/fsl,imx6-hdmi.yaml b/dts/upstream/Bindings/display/imx/fsl,imx6-hdmi.yaml
index 7979cf0..180c4b5 100644
--- a/dts/upstream/Bindings/display/imx/fsl,imx6-hdmi.yaml
+++ b/dts/upstream/Bindings/display/imx/fsl,imx6-hdmi.yaml
@@ -31,14 +31,6 @@
clock-names:
maxItems: 2
- ddc-i2c-bus:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- The HDMI DDC bus can be connected to either a system I2C master or the
- functionally-reduced I2C master contained in the DWC HDMI. When connected
- to a system I2C master this property contains a phandle to that I2C
- master controller.
-
gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
index b4c28e9..cf24434 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
@@ -36,6 +36,7 @@
- mediatek,mt8188-disp-aal
- mediatek,mt8192-disp-aal
- mediatek,mt8195-disp-aal
+ - mediatek,mt8365-disp-aal
- const: mediatek,mt8183-disp-aal
reg:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ccorr.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ccorr.yaml
index 8c2a737..9f83667 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ccorr.yaml
@@ -25,6 +25,9 @@
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
- items:
+ - const: mediatek,mt8365-disp-ccorr
+ - const: mediatek,mt8183-disp-ccorr
+ - items:
- enum:
- mediatek,mt8186-disp-ccorr
- mediatek,mt8188-disp-ccorr
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
index b886ca0..7df786b 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
@@ -40,6 +40,7 @@
- mediatek,mt8188-disp-color
- mediatek,mt8192-disp-color
- mediatek,mt8195-disp-color
+ - mediatek,mt8365-disp-color
- const: mediatek,mt8173-disp-color
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,dither.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,dither.yaml
index 1588b3f..6fceb1f 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,dither.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,dither.yaml
@@ -30,6 +30,7 @@
- mediatek,mt8188-disp-dither
- mediatek,mt8192-disp-dither
- mediatek,mt8195-disp-dither
+ - mediatek,mt8365-disp-dither
- const: mediatek,mt8183-disp-dither
reg:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,dpi.yaml
index 803c00f..5ca7679 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,dpi.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,dpi.yaml
@@ -31,6 +31,10 @@
- enum:
- mediatek,mt6795-dpi
- const: mediatek,mt8183-dpi
+ - items:
+ - enum:
+ - mediatek,mt8365-dpi
+ - const: mediatek,mt8192-dpi
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
index 8611319..a7aa8fc 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
@@ -37,6 +37,7 @@
- items:
- enum:
- mediatek,mt8195-dsi
+ - mediatek,mt8365-dsi
- const: mediatek,mt8183-dsi
reg:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,gamma.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,gamma.yaml
index b8b8e83..6823d3c 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,gamma.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,gamma.yaml
@@ -35,6 +35,7 @@
- mediatek,mt8188-disp-gamma
- mediatek,mt8192-disp-gamma
- mediatek,mt8195-disp-gamma
+ - mediatek,mt8365-disp-gamma
- const: mediatek,mt8183-disp-gamma
- items:
- enum:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
index c471a18..d55611c 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -44,6 +44,7 @@
- items:
- enum:
- mediatek,mt8186-disp-ovl
+ - mediatek,mt8365-disp-ovl
- const: mediatek,mt8192-disp-ovl
reg:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,rdma.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,rdma.yaml
index 39dbb5c..4cadb24 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,rdma.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,rdma.yaml
@@ -45,6 +45,7 @@
- enum:
- mediatek,mt8186-disp-rdma
- mediatek,mt8192-disp-rdma
+ - mediatek,mt8365-disp-rdma
- const: mediatek,mt8183-disp-rdma
reg:
diff --git a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
index 1fa28e9..b0fd96b 100644
--- a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
@@ -32,6 +32,7 @@
- qcom,sm6125-dsi-ctrl
- qcom,sm6350-dsi-ctrl
- qcom,sm6375-dsi-ctrl
+ - qcom,sm7150-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -162,6 +163,22 @@
items:
enum: [ 0, 1, 2, 3 ]
+ qcom,te-source:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Specifies the source of vsync signal from the panel used for
+ tearing elimination.
+ default: mdp_vsync_p
+ enum:
+ - mdp_vsync_p
+ - mdp_vsync_s
+ - mdp_vsync_e
+ - timer0
+ - timer1
+ - timer2
+ - timer3
+ - timer4
+
required:
- port@0
- port@1
@@ -332,6 +349,7 @@
enum:
- qcom,sc7180-dsi-ctrl
- qcom,sc7280-dsi-ctrl
+ - qcom,sm7150-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@@ -452,6 +470,7 @@
dsi0_out: endpoint {
remote-endpoint = <&sn65dsi86_in>;
data-lanes = <0 1 2 3>;
+ qcom,te-source = "mdp_vsync_e";
};
};
};
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
index 288d8ba..a55c244 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
@@ -16,6 +16,7 @@
compatible:
enum:
- qcom,dsi-phy-28nm-8226
+ - qcom,dsi-phy-28nm-8937
- qcom,dsi-phy-28nm-8960
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-hpm-fam-b
diff --git a/dts/upstream/Bindings/display/msm/gmu.yaml b/dts/upstream/Bindings/display/msm/gmu.yaml
index b383736..b1bd372 100644
--- a/dts/upstream/Bindings/display/msm/gmu.yaml
+++ b/dts/upstream/Bindings/display/msm/gmu.yaml
@@ -23,6 +23,9 @@
- items:
- pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
+ - items:
+ - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
+ - const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
reg:
@@ -225,6 +228,7 @@
- qcom,adreno-gmu-730.1
- qcom,adreno-gmu-740.1
- qcom,adreno-gmu-750.1
+ - qcom,adreno-gmu-x185.1
then:
properties:
reg:
diff --git a/dts/upstream/Bindings/display/msm/gpu.yaml b/dts/upstream/Bindings/display/msm/gpu.yaml
index 40b5c6b..6ddc72f 100644
--- a/dts/upstream/Bindings/display/msm/gpu.yaml
+++ b/dts/upstream/Bindings/display/msm/gpu.yaml
@@ -10,6 +10,18 @@
maintainers:
- Rob Clark <robdclark@gmail.com>
+# dtschema does not select nodes based on pattern+const, so add custom select
+# as a work-around:
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno
+ - amd,imageon
+ required:
+ - compatible
+
properties:
compatible:
oneOf:
@@ -17,7 +29,7 @@
The driver is parsing the compat string for Adreno to
figure out the chip-id.
items:
- - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
+ - pattern: '^qcom,adreno-[0-9a-f]{8}$'
- const: qcom,adreno
- description: |
The driver is parsing the compat string for Adreno to
@@ -32,9 +44,13 @@
- pattern: '^amd,imageon-200\.[0-1]$'
- const: amd,imageon
- clocks: true
+ clocks:
+ minItems: 2
+ maxItems: 7
- clock-names: true
+ clock-names:
+ minItems: 2
+ maxItems: 7
reg:
minItems: 1
@@ -42,7 +58,10 @@
reg-names:
minItems: 1
- maxItems: 3
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+ - const: cx_dbgc
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/msm/qcom,mdp5.yaml b/dts/upstream/Bindings/display/msm/qcom,mdp5.yaml
index 91c774f..e153f8d 100644
--- a/dts/upstream/Bindings/display/msm/qcom,mdp5.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,mdp5.yaml
@@ -25,6 +25,7 @@
- qcom,msm8226-mdp5
- qcom,msm8916-mdp5
- qcom,msm8917-mdp5
+ - qcom,msm8937-mdp5
- qcom,msm8953-mdp5
- qcom,msm8974-mdp5
- qcom,msm8976-mdp5
diff --git a/dts/upstream/Bindings/display/msm/qcom,mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,mdss.yaml
index e457654..7c6462c 100644
--- a/dts/upstream/Bindings/display/msm/qcom,mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,mdss.yaml
@@ -126,6 +126,7 @@
- qcom,dsi-phy-14nm-8953
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-8226
+ - qcom,dsi-phy-28nm-8937
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-hpm-fam-b
- qcom,dsi-phy-28nm-lp
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
index 8e8a288..e22b4c4 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -7,7 +7,7 @@
title: Qualcomm SM6375 Display MDSS
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description:
SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm7150-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sm7150-dpu.yaml
new file mode 100644
index 0000000..c79b2d4
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm7150-dpu.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM7150 Display Processing Unit (DPU)
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm7150-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi clock
+ - description: Display ahb clock
+ - description: Display rotator clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm7150-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdss_ahb_clk>,
+ <&dispcc_mdss_rot_clk>,
+ <&dispcc_mdss_mdp_lut_clk>,
+ <&dispcc_mdss_mdp_clk>,
+ <&dispcc_mdss_vsync_clk>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-344000000 {
+ opp-hz = /bits/ 64 <344000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm7150-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm7150-mdss.yaml
new file mode 100644
index 0000000..13c5d5f
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm7150-mdss.yaml
@@ -0,0 +1,458 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM7150 Display MDSS
+
+maintainers:
+ - Danila Tikhonov <danila@jiaxyga.com>
+
+description:
+ SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm7150-mdss
+
+ clocks:
+ items:
+ - description: Display ahb clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from mdp1 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+ - const: cpu-cfg
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,sm7150-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,sm7150-dp
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm7150-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm7150-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc_mdss_gdsc>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>,
+ <&gcc_disp_sf_axi_clk>,
+ <&dispcc_mdss_mdp_clk>;
+ clock-names = "iface",
+ "bus",
+ "nrt_bus",
+ "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ iommus = <&apps_smmu 0x800 0x440>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm7150-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_disp_hf_axi_clk>,
+ <&dispcc_mdss_ahb_clk>,
+ <&dispcc_mdss_rot_clk>,
+ <&dispcc_mdss_mdp_lut_clk>,
+ <&dispcc_mdss_mdp_clk>,
+ <&dispcc_mdss_vsync_clk>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_mdss_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-344000000 {
+ opp-hz = /bits/ 64 <344000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm7150-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc_mdss_byte0_clk>,
+ <&dispcc_mdss_byte0_intf_clk>,
+ <&dispcc_mdss_pclk0_clk>,
+ <&dispcc_mdss_esc0_clk>,
+ <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
+ <&dispcc_mdss_pclk0_clk_src>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+ };
+
+ dsi@ae96000 {
+ compatible = "qcom,sm7150-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae96000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc_mdss_byte1_clk>,
+ <&dispcc_mdss_byte1_intf_clk>,
+ <&dispcc_mdss_pclk1_clk>,
+ <&dispcc_mdss_esc1_clk>,
+ <&dispcc_mdss_ahb_clk>,
+ <&gcc_disp_hf_axi_clk>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc_mdss_byte1_clk_src>,
+ <&dispcc_mdss_pclk1_clk_src>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae96400 0x200>,
+ <0x0ae96600 0x280>,
+ <0x0ae96a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ vdds-supply = <&vdda_mipi_dsi1_pll>;
+ };
+
+ displayport-controller@ae90000 {
+ compatible = "qcom,sm7150-dp";
+ reg = <0xae90000 0x200>,
+ <0xae90200 0x200>,
+ <0xae90400 0xc00>,
+ <0xae91000 0x400>,
+ <0xae91400 0x400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc_mdss_ahb_clk>,
+ <&dispcc_mdss_dp_aux_clk>,
+ <&dispcc_mdss_dp_link_clk>,
+ <&dispcc_mdss_dp_link_intf_clk>,
+ <&dispcc_mdss_dp_pixel_clk>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
+ <&dispcc_mdss_dp_pixel_clk_src>;
+ assigned-clock-parents = <&dp_phy 0>,
+ <&dp_phy 1>;
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint {
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/display/panel/anbernic,rg35xx-plus-panel.yaml b/dts/upstream/Bindings/display/panel/anbernic,rg35xx-plus-panel.yaml
new file mode 100644
index 0000000..1d67492
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/anbernic,rg35xx-plus-panel.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-panel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
+
+maintainers:
+ - Ryan Walklin <ryan@testtoast.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: anbernic,rg35xx-plus-panel
+ - items:
+ - enum:
+ - anbernic,rg35xx-2024-panel
+ - anbernic,rg35xx-h-panel
+ - anbernic,rg35xx-sp-panel
+ - const: anbernic,rg35xx-plus-panel
+
+ reg:
+ maxItems: 1
+
+ spi-3wire: true
+
+required:
+ - compatible
+ - reg
+ - port
+ - power-supply
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "anbernic,rg35xx-plus-panel";
+ reg = <0>;
+
+ spi-3wire;
+ spi-max-frequency = <3125000>;
+
+ reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14
+
+ backlight = <&backlight>;
+ power-supply = <®_lcd>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&tcon_lcd0_out_lcd>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml b/dts/upstream/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
index 2399cab..dd614e0 100644
--- a/dts/upstream/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
+++ b/dts/upstream/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
@@ -7,7 +7,7 @@
title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel
maintainers:
- - Konrad Dybcio <konradybcio@gmail.com>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |+
This panel seems to only be found in the Asus Z00T
diff --git a/dts/upstream/Bindings/display/panel/boe,tv101wum-nl6.yaml b/dts/upstream/Bindings/display/panel/boe,tv101wum-nl6.yaml
index 9e603ca..7a9f49e 100644
--- a/dts/upstream/Bindings/display/panel/boe,tv101wum-nl6.yaml
+++ b/dts/upstream/Bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -32,8 +32,6 @@
- innolux,hj110iz-01a
# STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
- starry,2081101qfh032011-53g
- # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
- - starry,himax83102-j02
# STARRY ili9882t 10.51" WUXGA TFT LCD panel
- starry,ili9882t
diff --git a/dts/upstream/Bindings/display/panel/himax,hx83102.yaml b/dts/upstream/Bindings/display/panel/himax,hx83102.yaml
new file mode 100644
index 0000000..c649fb0
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/himax,hx83102.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/himax,hx83102.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Himax HX83102 MIPI-DSI LCD panel controller
+
+maintainers:
+ - Cong Yang <yangcong5@huaqin.corp-partner.google.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel
+ - boe,nv110wum-l60
+ # IVO t109nw41 11.0" WUXGA TFT LCD panel
+ - ivo,t109nw41
+ # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
+ - starry,himax83102-j02
+ - const: himax,hx83102
+
+ reg:
+ description: the virtual channel number of a DSI peripheral
+
+ enable-gpios:
+ description: a GPIO spec for the enable pin
+
+ pp1800-supply:
+ description: core voltage supply
+
+ avdd-supply:
+ description: phandle of the regulator that provides positive voltage
+
+ avee-supply:
+ description: phandle of the regulator that provides negative voltage
+
+ backlight: true
+ port: true
+ rotation: true
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "starry,himax83102-j02", "himax,hx83102";
+ reg = <0>;
+ enable-gpios = <&pio 45 0>;
+ avdd-supply = <&ppvarn_lcd>;
+ avee-supply = <&ppvarp_lcd>;
+ pp1800-supply = <&pp1800_lcd>;
+ backlight = <&backlight_lcd0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/display/panel/ilitek,ili9806e.yaml b/dts/upstream/Bindings/display/panel/ilitek,ili9806e.yaml
new file mode 100644
index 0000000..cfd7cc9
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/ilitek,ili9806e.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9806e.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9806E based MIPI-DSI panels
+
+maintainers:
+ - Michael Walle <mwalle@kernel.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ortustech,com35h3p70ulc
+ - const: ilitek,ili9806e
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+ vccio-supply: true
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vccio-supply
+ - reset-gpios
+ - backlight
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "ortustech,com35h3p70ulc", "ilitek,ili9806e";
+ reg = <0>;
+ vdd-supply = <®_vdd_panel>;
+ vccio-supply = <®_vccio_panel>;
+ reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/display/panel/jadard,jd9365da-h3.yaml b/dts/upstream/Bindings/display/panel/jadard,jd9365da-h3.yaml
index 20afdb4..3d5bede 100644
--- a/dts/upstream/Bindings/display/panel/jadard,jd9365da-h3.yaml
+++ b/dts/upstream/Bindings/display/panel/jadard,jd9365da-h3.yaml
@@ -17,6 +17,7 @@
items:
- enum:
- chongzhou,cz101b4001
+ - kingdisplay,kd101ne3-40ti
- radxa,display-10hd-ad001
- radxa,display-8hd-ad002
- const: jadard,jd9365da-h3
diff --git a/dts/upstream/Bindings/display/panel/lg,sw43408.yaml b/dts/upstream/Bindings/display/panel/lg,sw43408.yaml
index 1e08648..bbaaa78 100644
--- a/dts/upstream/Bindings/display/panel/lg,sw43408.yaml
+++ b/dts/upstream/Bindings/display/panel/lg,sw43408.yaml
@@ -21,7 +21,9 @@
items:
- const: lg,sw43408
- reg: true
+ reg:
+ maxItems: 1
+
port: true
vddi-supply: true
vpnl-supply: true
diff --git a/dts/upstream/Bindings/display/panel/panel-edp-legacy.yaml b/dts/upstream/Bindings/display/panel/panel-edp-legacy.yaml
new file mode 100644
index 0000000..b308047
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/panel-edp-legacy.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-edp-legacy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Legacy eDP panels from before the "edp-panel" compatible
+
+maintainers:
+ - Douglas Anderson <dianders@chromium.org>
+
+description: |
+ This binding file is a collection of eDP panels from before the generic
+ "edp-panel" compatible was introduced. It is kept around to support old
+ dts files. The only reason one might add a new panel here instead of using
+ the generic "edp-panel" is if it needed to be used on an eDP controller
+ that doesn't support the generic "edp-panel" compatible, but it should be
+ a strong preference to add the generic "edp-panel" compatible instead.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ # compatible must be listed in alphabetical order, ordered by compatible.
+ # The description in the comment is mandatory for each compatible.
+
+ # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
+ - auo,b101ean01
+ # AUO B116XAK01 eDP TFT LCD panel
+ - auo,b116xa01
+ # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
+ - auo,b133htn01
+ # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
+ - auo,b133xtn01
+ # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
+ - boe,nv101wxmn51
+ # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel
+ - boe,nv110wtm-n61
+ # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel
+ - boe,nv133fhm-n61
+ # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel
+ - boe,nv133fhm-n62
+ # BOE NV140FHM-N49 14.0" FHD a-Si FT panel
+ - boe,nv140fhmn49
+ # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
+ - innolux,n116bca-ea1
+ # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
+ - innolux,n116bge
+ # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
+ - innolux,n125hce-gn1
+ # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
+ - innolux,p120zdg-bf1
+ # King & Display KD116N21-30NV-A010 eDP TFT LCD panel
+ - kingdisplay,kd116n21-30nv-a010
+ # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
+ - lg,lp079qx1-sp0v
+ # LG 9.7" (2048x1536 pixels) TFT LCD panel
+ - lg,lp097qx1-spa1
+ # LG 12.0" (1920x1280 pixels) TFT LCD panel
+ - lg,lp120up1
+ # LG 12.9" (2560x1700 pixels) TFT LCD panel
+ - lg,lp129qe
+ # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel
+ - neweast,wjfh116008a
+ # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
+ - samsung,lsn122dl01-c01
+ # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel
+ - samsung,ltn140at29-301
+ # Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
+ - sharp,ld-d5116z01b
+ # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
+ - sharp,lq123p1jx31
+
+ backlight: true
+ ddc-i2c-bus: true
+ enable-gpios: true
+ panel-timing: true
+ port: true
+ power-supply: true
+ no-hpd: true
+ hpd-gpios: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - power-supply
+
+examples:
+ - |
+ panel: panel {
+ compatible = "innolux,n116bge";
+ power-supply = <&panel_regulator>;
+ backlight = <&backlight>;
+
+ panel-timing {
+ clock-frequency = <74250000>;
+ hactive = <1366>;
+ hfront-porch = <136>;
+ hback-porch = <60>;
+ hsync-len = <30>;
+ hsync-active = <0>;
+ vactive = <768>;
+ vfront-porch = <8>;
+ vback-porch = <12>;
+ vsync-len = <12>;
+ vsync-active = <0>;
+ };
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/display/panel/panel-mipi-dbi-spi.yaml b/dts/upstream/Bindings/display/panel/panel-mipi-dbi-spi.yaml
index d0ac31a..6f0290c 100644
--- a/dts/upstream/Bindings/display/panel/panel-mipi-dbi-spi.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-mipi-dbi-spi.yaml
@@ -50,6 +50,12 @@
| Command or data |
|<D7><D6><D5><D4><D3><D2><D1><D0>|
+ The standard defines one pixel format for type C: RGB111. The industry
+ however has decided to provide the type A/B interface pixel formats also on
+ the Type C interface and most common among these are RGB565 and RGB666.
+ The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
+ order. This gives each supported RGB format a BGR variant.
+
The panel resolution is specified using the panel-timing node properties
hactive (width) and vactive (height). The other mandatory panel-timing
properties should be set to zero except clock-frequency which can be
@@ -93,6 +99,28 @@
spi-3wire: true
+ format:
+ description: >
+ Pixel format in bit order as going on the wire:
+ * `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte
+ * `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte
+ * `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte
+ * `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte
+ * `r5g6b5` - RGB565, 2 bytes
+ * `b5g6r5` - BGR565, 2 bytes
+ * `r6x2g6x2b6x2` - RGB666, 3 bytes
+ * `b6x2g6x2r6x2` - BGR666, 3 bytes
+ enum:
+ - x2r1g1b1r1g1b1
+ - x2b1g1r1b1g1r1
+ - x1r1g1b1x1r1g1b1
+ - x1b1g1r1x1b1g1r1
+ - r5g6b5
+ - b5g6r5
+ - r6x2g6x2b6x2
+ - b6x2g6x2r6x2
+ default: r5g6b5
+
required:
- compatible
- reg
@@ -119,6 +147,8 @@
reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
write-only;
+ format = "r5g6b5";
+
backlight = <&backlight>;
width-mm = <35>;
diff --git a/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml b/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml
index db5acd2..9b92a05 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple-dsi.yaml
@@ -46,6 +46,8 @@
- lg,ld070wx3-sl01
# LG Corporation 5" HD TFT LCD panel
- lg,lh500wx1-sd03
+ # Lincoln LCD197 5" 1080x1920 LCD panel
+ - lincolntech,lcd197
# One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel
- osddisplays,osd101t2587-53ts
# Panasonic 10" WUXGA TFT LCD panel
diff --git a/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
index 716ece5..e78160d 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
@@ -41,6 +41,12 @@
- auo,g190ean01
# Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
- koe,tx26d202vm0bwa
+ # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200
+ - lincolntech,lcd185-101ct
+ # Microtips Technology MF-101HIEBCAF0 10.1" WUXGA (1920x1200) TFT LCD panel
+ - microtips,mf-101hiebcaf0
+ # Microtips Technology MF-103HIEB0GA0 10.25" 1920x720 TFT LCD panel
+ - microtips,mf-103hieb0ga0
# NLT Technologies, Ltd. 15.6" FHD (1920x1080) LVDS TFT LCD panel
- nlt,nl192108ac18-02d
diff --git a/dts/upstream/Bindings/display/panel/panel-simple.yaml b/dts/upstream/Bindings/display/panel/panel-simple.yaml
index 5067f5c..8a87e01 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple.yaml
@@ -41,28 +41,18 @@
- ampire,am800600p5tmqw-tb8h
# AU Optronics Corporation 10.1" WSVGA TFT LCD panel
- auo,b101aw03
- # AU Optronics Corporation 10.1" WSVGA TFT LCD panel
- - auo,b101ean01
# AU Optronics Corporation 10.1" WXGA TFT LCD panel
- auo,b101xtn01
- # AUO B116XAK01 eDP TFT LCD panel
- - auo,b116xa01
# AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel
- auo,b116xw03
- # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
- - auo,b133han05
- # AU Optronics Corporation 13.3" FHD (1920x1080) color TFT-LCD panel
- - auo,b133htn01
- # AU Optronics Corporation 13.3" WXGA (1366x768) TFT LCD panel
- - auo,b133xtn01
- # AU Optronics Corporation 14.0" FHD (1920x1080) color TFT-LCD panel
- - auo,b140han06
# AU Optronics Corporation 7.0" FHD (800 x 480) TFT LCD panel
- auo,g070vvn01
# AU Optronics Corporation 10.1" (1280x800) color TFT LCD panel
- auo,g101evn010
# AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
- auo,g104sn02
+ # AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+ - auo,g104stn01
# AU Optronics Corporation 12.1" (1280x800) TFT LCD panel
- auo,g121ean01
# AU Optronics Corporation 15.6" (1366x768) TFT LCD panel
@@ -81,16 +71,6 @@
- boe,ev121wxm-n10-1850
# BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
- boe,hv070wsa-100
- # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
- - boe,nv101wxmn51
- # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel
- - boe,nv110wtm-n61
- # BOE NV110WTM-N61 11.0" 2160x1440 TFT LCD Panel
- - boe,nv133fhm-n61
- # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel
- - boe,nv133fhm-n62
- # BOE NV140FHM-N49 14.0" FHD a-Si FT panel
- - boe,nv140fhmn49
# Crystal Clear Technology CMT430B19N00 4.3" 480x272 TFT-LCD panel
- cct,cmt430b19n00
# CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
@@ -172,8 +152,6 @@
- hannstar,hsd100pxn1
# Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel
- hit,tx23d38vm0caa
- # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel
- - ivo,m133nwf4-r0
# Innolux AT043TN24 4.3" WQVGA TFT LCD panel
- innolux,at043tn24
# Innolux AT070TN92 7.0" WQVGA TFT LCD panel
@@ -192,22 +170,12 @@
- innolux,g121x1-l03
# Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel
- innolux,g121xce-l01
- # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- - innolux,n116bca-ea1
- # Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- - innolux,n116bge
- # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
- - innolux,n125hce-gn1
# InnoLux 15.6" FHD (1920x1080) TFT LCD panel
- innolux,g156hce-l01
# InnoLux 15.6" WXGA TFT LCD panel
- innolux,n156bge-l21
- # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
- - innolux,p120zdg-bf1
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
- innolux,zj070na-01p
- # King & Display KD116N21-30NV-A010 eDP TFT LCD panel
- - kingdisplay,kd116n21-30nv-a010
# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
- koe,tx14d24vm1bpa
# Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
@@ -220,14 +188,6 @@
- lemaker,bl035-rgb-002
# LG 7" (800x480 pixels) TFT LCD panel
- lg,lb070wv8
- # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel
- - lg,lp079qx1-sp0v
- # LG 9.7" (2048x1536 pixels) TFT LCD panel
- - lg,lp097qx1-spa1
- # LG 12.0" (1920x1280 pixels) TFT LCD panel
- - lg,lp120up1
- # LG 12.9" (2560x1700 pixels) TFT LCD panel
- - lg,lp129qe
# Logic Technologies LT161010-2NHC 7" WVGA TFT Cap Touch Module
- logictechno,lt161010-2nhc
# Logic Technologies LT161010-2NHR 7" WVGA TFT Resistive Touch Module
@@ -254,8 +214,6 @@
- nec,nl4827hc19-05b
# Netron-DY E231732 7.0" WSVGA TFT LCD panel
- netron-dy,e231732
- # NewEast Optoelectronics CO., LTD WJFH116008A eDP TFT LCD panel
- - neweast,wjfh116008a
# Newhaven Display International 480 x 272 TFT LCD panel
- newhaven,nhd-4.3-480272ef-atxl
# New Vision Display 7.0" 800 RGB x 480 TFT LCD panel
@@ -280,6 +238,8 @@
- powertip,ph128800t006-zhc01
# POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel
- powertip,ph800480t013-idf02
+ # PrimeView PM070WL4 7.0" 800x480 TFT LCD panel
+ - primeview,pm070wl4
# QiaoDian XianShi Corporation 4"3 TFT LCD panel
- qiaodian,qd43003c0-40
# Shenzhen QiShenglong Industrialist Co., Ltd. Gopher 2b 4.3" 480(RGB)x272 TFT LCD panel
@@ -290,16 +250,10 @@
- rocktech,rk070er9427
# Rocktech Display Ltd. RK043FN48H 4.3" 480x272 LCD-TFT panel
- rocktech,rk043fn48h
- # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
- - samsung,atna33xc20
- # Samsung 12.2" (2560x1600 pixels) TFT LCD panel
- - samsung,lsn122dl01-c01
# Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel
- samsung,ltl101al01
# Samsung Electronics 10.1" WSVGA TFT LCD panel
- samsung,ltn101nt05
- # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel
- - samsung,ltn140at29-301
# Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel
- satoz,sat050at40h12r2
# Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel
@@ -308,18 +262,12 @@
- sharp,lq070y3dg3b
# Sharp Display Corp. LQ101K1LY04 10.07" WXGA TFT LCD panel
- sharp,lq101k1ly04
- # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
- - sharp,lq123p1jx31
- # Sharp 14" (1920x1080 pixels) TFT LCD panel
- - sharp,lq140m1jw46
# Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel
- sharp,ls020b1dd01d
# Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
- shelly,sca07010-bfn-lnn
# Starry KR070PE2T 7" WVGA TFT LCD panel
- starry,kr070pe2t
- # Starry 12.2" (1920x1200 pixels) TFT LCD panel
- - starry,kr122ea0sra
# Startek KD070WVFPA043-C069A 7" TFT LCD panel
- startek,kd070wvfpa
# Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel
diff --git a/dts/upstream/Bindings/display/panel/raydium,rm69380.yaml b/dts/upstream/Bindings/display/panel/raydium,rm69380.yaml
index b17765b..ec445ff 100644
--- a/dts/upstream/Bindings/display/panel/raydium,rm69380.yaml
+++ b/dts/upstream/Bindings/display/panel/raydium,rm69380.yaml
@@ -28,6 +28,9 @@
to work with the indicated panel. The raydium,rm69380 compatible shall
always be provided as a fallback.
+ reg:
+ maxItems: 1
+
avdd-supply:
description: Analog voltage rail
@@ -38,8 +41,6 @@
maxItems: 1
description: phandle of gpio for reset line - This should be active low
- reg: true
-
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
new file mode 100644
index 0000000..032f783
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,atna33xc20.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
+
+maintainers:
+ - Douglas Anderson <dianders@chromium.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ # Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
+ - const: samsung,atna33xc20
+ - items:
+ - enum:
+ # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
+ - samsung,atna45af01
+ # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
+ - samsung,atna45dc02
+ - const: samsung,atna33xc20
+
+ enable-gpios: true
+ port: true
+ power-supply: true
+ no-hpd: true
+ hpd-gpios: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - enable-gpios
+ - power-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2d {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2d>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+
+ vpll-supply = <&src_pp1800_s4a>;
+ vccio-supply = <&src_pp1800_s4a>;
+ vcca-supply = <&src_pp1200_l2a>;
+ vcc-supply = <&src_pp1200_l2a>;
+
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ clock-names = "refclk";
+
+ no-hpd;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ sn65dsi86_out: endpoint {
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel {
+ compatible = "samsung,atna33xc20";
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+ power-supply = <&pp3300_dx_edp>;
+ hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&sn65dsi86_out>;
+ };
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/display/panel/sharp,ld-d5116z01b.yaml b/dts/upstream/Bindings/display/panel/sharp,ld-d5116z01b.yaml
deleted file mode 100644
index fbb647e..0000000
--- a/dts/upstream/Bindings/display/panel/sharp,ld-d5116z01b.yaml
+++ /dev/null
@@ -1,30 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/panel/sharp,ld-d5116z01b.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
-
-maintainers:
- - Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
-
-allOf:
- - $ref: panel-common.yaml#
-
-properties:
- compatible:
- const: sharp,ld-d5116z01b
-
- power-supply: true
- backlight: true
- port: true
- no-hpd: true
-
-additionalProperties: false
-
-required:
- - compatible
- - power-supply
-
-...
diff --git a/dts/upstream/Bindings/display/panel/sony,td4353-jdi.yaml b/dts/upstream/Bindings/display/panel/sony,td4353-jdi.yaml
index 191b692..032a989 100644
--- a/dts/upstream/Bindings/display/panel/sony,td4353-jdi.yaml
+++ b/dts/upstream/Bindings/display/panel/sony,td4353-jdi.yaml
@@ -7,7 +7,7 @@
title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 2aac622..9d09685 100644
--- a/dts/upstream/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/dts/upstream/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -70,14 +70,6 @@
- vpll
- ref
- ddc-i2c-bus:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- The HDMI DDC bus can be connected to either a system I2C master or the
- functionally-reduced I2C master contained in the DWC HDMI. When connected
- to a system I2C master this property contains a phandle to that I2C
- master controller.
-
phys:
maxItems: 1
description: The HDMI PHY
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
index ccf79e7..ccd71c5 100644
--- a/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
+++ b/dts/upstream/Bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
@@ -15,6 +15,7 @@
items:
- enum:
- rockchip,px30-mipi-dsi
+ - rockchip,rk3128-mipi-dsi
- rockchip,rk3288-mipi-dsi
- rockchip,rk3399-mipi-dsi
- rockchip,rk3568-mipi-dsi
@@ -77,6 +78,7 @@
contains:
enum:
- rockchip,px30-mipi-dsi
+ - rockchip,rk3128-mipi-dsi
- rockchip,rk3568-mipi-dsi
- rockchip,rv1126-mipi-dsi
diff --git a/dts/upstream/Bindings/display/st,stm32mp25-lvds.yaml b/dts/upstream/Bindings/display/st,stm32mp25-lvds.yaml
new file mode 100644
index 0000000..6736f93
--- /dev/null
+++ b/dts/upstream/Bindings/display/st,stm32mp25-lvds.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
+ - Yannick Fertre <yannick.fertre@foss.st.com>
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It is composed of three sub blocks:
+ - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+ - LVDS PHY: parallelize the data and drives the LVDS data lanes
+ - LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+ - FDP-Link-I and OpenLDI (v0.95) protocols
+ - Single-Link or Dual-Link operation
+ - Single-Display or Double-Display (with the same content duplicated on both)
+ - Flexible Bit-Mapping, including JEIDA and VESA
+ - RGB888 or RGB666 output
+ - Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+ const: st,stm32mp25-lvds
+
+ "#clock-cells":
+ const: 0
+ description:
+ Provides the internal LVDS PHY clock to the framework.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: ref
+
+ resets:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ LVDS output port node, connected to a panel or bridge input port.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+
+ lvds: lvds@48060000 {
+ compatible = "st,stm32mp25-lvds";
+ reg = <0x48060000 0x2000>;
+ #clock-cells = <0>;
+ clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc LVDS_R>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/dma/fsl,imx-dma.yaml b/dts/upstream/Bindings/dma/fsl,imx-dma.yaml
new file mode 100644
index 0000000..902a11f
--- /dev/null
+++ b/dts/upstream/Bindings/dma/fsl,imx-dma.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/fsl,imx-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Direct Memory Access (DMA) Controller for i.MX
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx1-dma
+ - fsl,imx21-dma
+ - fsl,imx27-dma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: DMA complete interrupt
+ - description: DMA Error interrupt
+ minItems: 1
+
+ "#dma-cells":
+ const: 1
+
+ dma-channels:
+ const: 16
+
+ dma-requests:
+ description: Number of DMA requests supported.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#dma-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ dma-controller@10001000 {
+ compatible = "fsl,imx27-dma";
+ reg = <0x10001000 0x1000>;
+ interrupts = <32 33>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
diff --git a/dts/upstream/Bindings/dma/fsl-imx-dma.txt b/dts/upstream/Bindings/dma/fsl-imx-dma.txt
deleted file mode 100644
index 1c9929d..0000000
--- a/dts/upstream/Bindings/dma/fsl-imx-dma.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Freescale Direct Memory Access (DMA) Controller for i.MX
-
-This document will only describe differences to the generic DMA Controller and
-DMA request bindings as described in dma/dma.txt .
-
-* DMA controller
-
-Required properties:
-- compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
-- reg : Should contain DMA registers location and length
-- interrupts : First item should be DMA interrupt, second one is optional and
- should contain DMA Error interrupt
-- #dma-cells : Has to be 1. imx-dma does not support anything else.
-
-Optional properties:
-- dma-channels : Number of DMA channels supported. Should be 16.
-- #dma-channels : deprecated
-- dma-requests : Number of DMA requests supported.
-- #dma-requests : deprecated
-
-Example:
-
- dma: dma@10001000 {
- compatible = "fsl,imx27-dma";
- reg = <0x10001000 0x1000>;
- interrupts = <32 33>;
- #dma-cells = <1>;
- dma-channels = <16>;
- };
-
-
-* DMA client
-
-Clients have to specify the DMA requests with phandles in a list.
-
-Required properties:
-- dmas: List of one or more DMA request specifiers. One DMA request specifier
- consists of a phandle to the DMA controller followed by the integer
- specifying the request line.
-- dma-names: List of string identifiers for the DMA requests. For the correct
- names, have a look at the specific client driver.
-
-Example:
-
- sdhci1: sdhci@10013000 {
- ...
- dmas = <&dma 7>;
- dma-names = "rx-tx";
- ...
- };
diff --git a/dts/upstream/Bindings/dma/fsl-qdma.txt b/dts/upstream/Bindings/dma/fsl-qdma.txt
deleted file mode 100644
index da371c4..0000000
--- a/dts/upstream/Bindings/dma/fsl-qdma.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-NXP Layerscape SoC qDMA Controller
-==================================
-
-This device follows the generic DMA bindings defined in dma/dma.txt.
-
-Required properties:
-
-- compatible: Must be one of
- "fsl,ls1021a-qdma": for LS1021A Board
- "fsl,ls1028a-qdma": for LS1028A Board
- "fsl,ls1043a-qdma": for ls1043A Board
- "fsl,ls1046a-qdma": for ls1046A Board
-- reg: Should contain the register's base address and length.
-- interrupts: Should contain a reference to the interrupt used by this
- device.
-- interrupt-names: Should contain interrupt names:
- "qdma-queue0": the block0 interrupt
- "qdma-queue1": the block1 interrupt
- "qdma-queue2": the block2 interrupt
- "qdma-queue3": the block3 interrupt
- "qdma-error": the error interrupt
-- fsl,dma-queues: Should contain number of queues supported.
-- dma-channels: Number of DMA channels supported
-- block-number: the virtual block number
-- block-offset: the offset of different virtual block
-- status-sizes: status queue size of per virtual block
-- queue-sizes: command queue size of per virtual block, the size number
- based on queues
-
-Optional properties:
-
-- dma-channels: Number of DMA channels supported by the controller.
-- big-endian: If present registers and hardware scatter/gather descriptors
- of the qDMA are implemented in big endian mode, otherwise in little
- mode.
-
-Examples:
-
- qdma: dma-controller@8390000 {
- compatible = "fsl,ls1021a-qdma";
- reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
- <0x0 0x8389000 0x0 0x1000>, /* Status regs */
- <0x0 0x838a000 0x0 0x2000>; /* Block regs */
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "qdma-error",
- "qdma-queue0", "qdma-queue1";
- dma-channels = <8>;
- block-number = <2>;
- block-offset = <0x1000>;
- fsl,dma-queues = <2>;
- status-sizes = <64>;
- queue-sizes = <64 64>;
- big-endian;
- };
-
-DMA clients must use the format described in dma/dma.txt file.
diff --git a/dts/upstream/Bindings/dma/fsl-qdma.yaml b/dts/upstream/Bindings/dma/fsl-qdma.yaml
new file mode 100644
index 0000000..1b9ebdb
--- /dev/null
+++ b/dts/upstream/Bindings/dma/fsl-qdma.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Layerscape SoC qDMA Controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1021a-qdma
+ - fsl,ls1028a-qdma
+ - fsl,ls1043a-qdma
+ - fsl,ls1046a-qdma
+
+ reg:
+ items:
+ - description: Controller regs
+ - description: Status regs
+ - description: Block regs
+
+ interrupts:
+ minItems: 2
+ maxItems: 5
+
+ interrupt-names:
+ minItems: 2
+ items:
+ - const: qdma-error
+ - const: qdma-queue0
+ - const: qdma-queue1
+ - const: qdma-queue2
+ - const: qdma-queue3
+
+ dma-channels:
+ minimum: 1
+ maximum: 64
+
+ fsl,dma-queues:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Should contain number of queues supported.
+ minimum: 1
+ maximum: 4
+
+ block-number:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: the virtual block number
+
+ block-offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: the offset of different virtual block
+
+ status-sizes:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: status queue size of per virtual block
+
+ queue-sizes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ command queue size of per virtual block, the size number
+ based on queues
+
+ big-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ If present registers and hardware scatter/gather descriptors
+ of the qDMA are implemented in big endian mode, otherwise in little
+ mode.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - fsl,dma-queues
+ - block-number
+ - block-offset
+ - status-sizes
+ - queue-sizes
+
+allOf:
+ - $ref: dma-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,ls1028a-qdma
+ - fsl,ls1043a-qdma
+ - fsl,ls1046a-qdma
+ then:
+ properties:
+ interrupts:
+ minItems: 5
+ interrupt-names:
+ minItems: 5
+ else:
+ properties:
+ interrupts:
+ maxItems: 3
+ interrupt-names:
+ maxItems: 3
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dma-controller@8390000 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x8388000 0x1000>, /* Controller regs */
+ <0x8389000 0x1000>, /* Status regs */
+ <0x838a000 0x2000>; /* Block regs */
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1";
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ block-number = <2>;
+ block-offset = <0x1000>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ fsl,dma-queues = <2>;
+ };
+
diff --git a/dts/upstream/Bindings/dma/qcom,gpi.yaml b/dts/upstream/Bindings/dma/qcom,gpi.yaml
index deb64cb..4df4e61 100644
--- a/dts/upstream/Bindings/dma/qcom,gpi.yaml
+++ b/dts/upstream/Bindings/dma/qcom,gpi.yaml
@@ -27,6 +27,7 @@
- qcom,qcm2290-gpi-dma
- qcom,qdu1000-gpi-dma
- qcom,sc7280-gpi-dma
+ - qcom,sdx75-gpi-dma
- qcom,sm6115-gpi-dma
- qcom,sm6375-gpi-dma
- qcom,sm8350-gpi-dma
diff --git a/dts/upstream/Bindings/dma/sprd,sc9860-dma.yaml b/dts/upstream/Bindings/dma/sprd,sc9860-dma.yaml
new file mode 100644
index 0000000..9464721
--- /dev/null
+++ b/dts/upstream/Bindings/dma/sprd,sc9860-dma.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC9860 DMA controller
+
+description: |
+ There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
+ DMA controller, it can or do not request the IRQ, which will save
+ system power without resuming system by DMA interrupts if AGCP DMA
+ does not request the IRQ.
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ const: sprd,sc9860-dma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: DMA enable clock
+ - description: optional ashb_eb clock, only for the AGCP DMA controller
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: enable
+ - const: ashb_eb
+
+ '#dma-cells':
+ const: 1
+
+ dma-channels:
+ const: 32
+
+ '#dma-channels':
+ const: 32
+ deprecated: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#dma-cells'
+ - dma-channels
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sprd,sc9860-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ /* AP DMA controller */
+ dma-controller@20100000 {
+ compatible = "sprd,sc9860-dma";
+ reg = <0x20100000 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apahb_gate CLK_DMA_EB>;
+ clock-names = "enable";
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ };
+
+ /* AGCP DMA controller */
+ dma-controller@41580000 {
+ compatible = "sprd,sc9860-dma";
+ reg = <0x41580000 0x4000>;
+ clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
+ <&agcp_gate CLK_AGCP_AP_ASHB_EB>;
+ clock-names = "enable", "ashb_eb";
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ };
+...
diff --git a/dts/upstream/Bindings/dma/sprd-dma.txt b/dts/upstream/Bindings/dma/sprd-dma.txt
deleted file mode 100644
index c7e9b5f..0000000
--- a/dts/upstream/Bindings/dma/sprd-dma.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-* Spreadtrum DMA controller
-
-This binding follows the generic DMA bindings defined in dma.txt.
-
-Required properties:
-- compatible: Should be "sprd,sc9860-dma".
-- reg: Should contain DMA registers location and length.
-- interrupts: Should contain one interrupt shared by all channel.
-- #dma-cells: must be <1>. Used to represent the number of integer
- cells in the dmas property of client device.
-- dma-channels : Number of DMA channels supported. Should be 32.
-- clock-names: Should contain the clock of the DMA controller.
-- clocks: Should contain a clock specifier for each entry in clock-names.
-
-Deprecated properties:
-- #dma-channels : Number of DMA channels supported. Should be 32.
-
-Example:
-
-Controller:
-apdma: dma-controller@20100000 {
- compatible = "sprd,sc9860-dma";
- reg = <0x20100000 0x4000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <32>;
- clock-names = "enable";
- clocks = <&clk_ap_ahb_gates 5>;
-};
-
-
-Client:
-DMA clients connected to the Spreadtrum DMA controller must use the format
-described in the dma.txt file, using a two-cell specifier for each channel.
-The two cells in order are:
-1. A phandle pointing to the DMA controller.
-2. The slave id.
-
-spi0: spi@70a00000{
- ...
- dma-names = "rx_chn", "tx_chn";
- dmas = <&apdma 11>, <&apdma 12>;
- ...
-};
diff --git a/dts/upstream/Bindings/dma/st,stm32-dma.yaml b/dts/upstream/Bindings/dma/st,stm32-dma.yaml
deleted file mode 100644
index ff935a0..0000000
--- a/dts/upstream/Bindings/dma/st,stm32-dma.yaml
+++ /dev/null
@@ -1,120 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: STMicroelectronics STM32 DMA Controller
-
-description: |
- The STM32 DMA is a general-purpose direct memory access controller capable of
- supporting 8 independent DMA channels. Each channel can have up to 8 requests.
- DMA clients connected to the STM32 DMA controller must use the format
- described in the dma.txt file, using a four-cell specifier for each
- channel: a phandle to the DMA controller plus the following four integer cells:
- 1. The channel id
- 2. The request line number
- 3. A 32bit mask specifying the DMA channel configuration which are device
- dependent:
- -bit 9: Peripheral Increment Address
- 0x0: no address increment between transfers
- 0x1: increment address between transfers
- -bit 10: Memory Increment Address
- 0x0: no address increment between transfers
- 0x1: increment address between transfers
- -bit 15: Peripheral Increment Offset Size
- 0x0: offset size is linked to the peripheral bus width
- 0x1: offset size is fixed to 4 (32-bit alignment)
- -bit 16-17: Priority level
- 0x0: low
- 0x1: medium
- 0x2: high
- 0x3: very high
- 4. A 32bit bitfield value specifying DMA features which are device dependent:
- -bit 0-1: DMA FIFO threshold selection
- 0x0: 1/4 full FIFO
- 0x1: 1/2 full FIFO
- 0x2: 3/4 full FIFO
- 0x3: full FIFO
- -bit 2: DMA direct mode
- 0x0: FIFO mode with threshold selectable with bit 0-1
- 0x1: Direct mode: each DMA request immediately initiates a transfer
- from/to the memory, FIFO is bypassed.
- -bit 4: alternative DMA request/acknowledge protocol
- 0x0: Use standard DMA ACK management, where ACK signal is maintained
- up to the removal of request and transfer completion
- 0x1: Use alternative DMA ACK management, where ACK de-assertion does
- not wait for the de-assertion of the REQuest, ACK is only managed
- by transfer completion. This must only be used on channels
- managing transfers for STM32 USART/UART.
-
-
-maintainers:
- - Amelie Delaunay <amelie.delaunay@foss.st.com>
-
-allOf:
- - $ref: dma-controller.yaml#
-
-properties:
- "#dma-cells":
- const: 4
-
- compatible:
- const: st,stm32-dma
-
- reg:
- maxItems: 1
-
- clocks:
- maxItems: 1
-
- interrupts:
- maxItems: 8
- description: Should contain all of the per-channel DMA
- interrupts in ascending order with respect to the
- DMA channel index.
-
- resets:
- maxItems: 1
-
- st,mem2mem:
- $ref: /schemas/types.yaml#/definitions/flag
- description: if defined, it indicates that the controller
- supports memory-to-memory transfer
-
- access-controllers:
- minItems: 1
- maxItems: 2
-
-required:
- - compatible
- - reg
- - clocks
- - interrupts
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/stm32mp1-clks.h>
- #include <dt-bindings/reset/stm32mp1-resets.h>
- dma-controller@40026400 {
- compatible = "st,stm32-dma";
- reg = <0x40026400 0x400>;
- interrupts = <56>,
- <57>,
- <58>,
- <59>,
- <60>,
- <68>,
- <69>,
- <70>;
- clocks = <&clk_hclk>;
- #dma-cells = <4>;
- st,mem2mem;
- resets = <&rcc 150>;
- dma-requests = <8>;
- };
-
-...
diff --git a/dts/upstream/Bindings/dma/st,stm32-dmamux.yaml b/dts/upstream/Bindings/dma/st,stm32-dmamux.yaml
deleted file mode 100644
index ddf82bf..0000000
--- a/dts/upstream/Bindings/dma/st,stm32-dmamux.yaml
+++ /dev/null
@@ -1,57 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: STMicroelectronics STM32 DMA MUX (DMA request router)
-
-maintainers:
- - Amelie Delaunay <amelie.delaunay@foss.st.com>
-
-allOf:
- - $ref: dma-router.yaml#
-
-properties:
- "#dma-cells":
- const: 3
-
- compatible:
- const: st,stm32h7-dmamux
-
- reg:
- maxItems: 1
-
- clocks:
- maxItems: 1
-
- resets:
- maxItems: 1
-
- access-controllers:
- minItems: 1
- maxItems: 2
-
-required:
- - compatible
- - reg
- - dma-masters
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/stm32mp1-clks.h>
- #include <dt-bindings/reset/stm32mp1-resets.h>
- dma-router@40020800 {
- compatible = "st,stm32h7-dmamux";
- reg = <0x40020800 0x3c>;
- #dma-cells = <3>;
- dma-requests = <128>;
- dma-channels = <16>;
- dma-masters = <&dma1>, <&dma2>;
- clocks = <&timer_clk>;
- };
-
-...
diff --git a/dts/upstream/Bindings/dma/st,stm32-mdma.yaml b/dts/upstream/Bindings/dma/st,stm32-mdma.yaml
deleted file mode 100644
index 3874544..0000000
--- a/dts/upstream/Bindings/dma/st,stm32-mdma.yaml
+++ /dev/null
@@ -1,106 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: STMicroelectronics STM32 MDMA Controller
-
-description: |
- The STM32 MDMA is a general-purpose direct memory access controller capable of
- supporting 64 independent DMA channels with 256 HW requests.
- DMA clients connected to the STM32 MDMA controller must use the format
- described in the dma.txt file, using a five-cell specifier for each channel:
- a phandle to the MDMA controller plus the following five integer cells:
- 1. The request line number
- 2. The priority level
- 0x0: Low
- 0x1: Medium
- 0x2: High
- 0x3: Very high
- 3. A 32bit mask specifying the DMA channel configuration
- -bit 0-1: Source increment mode
- 0x0: Source address pointer is fixed
- 0x2: Source address pointer is incremented after each data transfer
- 0x3: Source address pointer is decremented after each data transfer
- -bit 2-3: Destination increment mode
- 0x0: Destination address pointer is fixed
- 0x2: Destination address pointer is incremented after each data transfer
- 0x3: Destination address pointer is decremented after each data transfer
- -bit 8-9: Source increment offset size
- 0x0: byte (8bit)
- 0x1: half-word (16bit)
- 0x2: word (32bit)
- 0x3: double-word (64bit)
- -bit 10-11: Destination increment offset size
- 0x0: byte (8bit)
- 0x1: half-word (16bit)
- 0x2: word (32bit)
- 0x3: double-word (64bit)
- -bit 25-18: The number of bytes to be transferred in a single transfer
- (min = 1 byte, max = 128 bytes)
- -bit 29:28: Trigger Mode
- 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
- 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
- 0x2: Each MDMA request triggers a repeated block transfer
- 0x3: Each MDMA request triggers a linked list transfer
- 4. A 32bit value specifying the register to be used to acknowledge the request
- if no HW ack signal is used by the MDMA client
- 5. A 32bit mask specifying the value to be written to acknowledge the request
- if no HW ack signal is used by the MDMA client
-
-maintainers:
- - Amelie Delaunay <amelie.delaunay@foss.st.com>
-
-allOf:
- - $ref: dma-controller.yaml#
-
-properties:
- "#dma-cells":
- const: 5
-
- compatible:
- const: st,stm32h7-mdma
-
- reg:
- maxItems: 1
-
- clocks:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- resets:
- maxItems: 1
-
- st,ahb-addr-masks:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- description: Array of u32 mask to list memory devices addressed via AHB bus.
-
-required:
- - compatible
- - reg
- - clocks
- - interrupts
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/stm32mp1-clks.h>
- #include <dt-bindings/reset/stm32mp1-resets.h>
- dma-controller@52000000 {
- compatible = "st,stm32h7-mdma";
- reg = <0x52000000 0x1000>;
- interrupts = <122>;
- clocks = <&timer_clk>;
- resets = <&rcc 992>;
- #dma-cells = <5>;
- dma-channels = <16>;
- dma-requests = <32>;
- st,ahb-addr-masks = <0x20000000>, <0x00000000>;
- };
-
-...
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml
new file mode 100644
index 0000000..11a289f
--- /dev/null
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dma.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DMA Controller
+
+description: |
+ The STM32 DMA is a general-purpose direct memory access controller capable of
+ supporting 8 independent DMA channels. Each channel can have up to 8 requests.
+ DMA clients connected to the STM32 DMA controller must use the format
+ described in the dma.txt file, using a four-cell specifier for each
+ channel: a phandle to the DMA controller plus the following four integer cells:
+ 1. The channel id
+ 2. The request line number
+ 3. A 32bit mask specifying the DMA channel configuration which are device
+ dependent:
+ -bit 9: Peripheral Increment Address
+ 0x0: no address increment between transfers
+ 0x1: increment address between transfers
+ -bit 10: Memory Increment Address
+ 0x0: no address increment between transfers
+ 0x1: increment address between transfers
+ -bit 15: Peripheral Increment Offset Size
+ 0x0: offset size is linked to the peripheral bus width
+ 0x1: offset size is fixed to 4 (32-bit alignment)
+ -bit 16-17: Priority level
+ 0x0: low
+ 0x1: medium
+ 0x2: high
+ 0x3: very high
+ 4. A 32bit bitfield value specifying DMA features which are device dependent:
+ -bit 0-1: DMA FIFO threshold selection
+ 0x0: 1/4 full FIFO
+ 0x1: 1/2 full FIFO
+ 0x2: 3/4 full FIFO
+ 0x3: full FIFO
+ -bit 2: DMA direct mode
+ 0x0: FIFO mode with threshold selectable with bit 0-1
+ 0x1: Direct mode: each DMA request immediately initiates a transfer
+ from/to the memory, FIFO is bypassed.
+ -bit 4: alternative DMA request/acknowledge protocol
+ 0x0: Use standard DMA ACK management, where ACK signal is maintained
+ up to the removal of request and transfer completion
+ 0x1: Use alternative DMA ACK management, where ACK de-assertion does
+ not wait for the de-assertion of the REQuest, ACK is only managed
+ by transfer completion. This must only be used on channels
+ managing transfers for STM32 USART/UART.
+
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@foss.st.com>
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ "#dma-cells":
+ const: 4
+
+ compatible:
+ const: st,stm32-dma
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 8
+ description: Should contain all of the per-channel DMA
+ interrupts in ascending order with respect to the
+ DMA channel index.
+
+ resets:
+ maxItems: 1
+
+ st,mem2mem:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: if defined, it indicates that the controller
+ supports memory-to-memory transfer
+
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ dma-controller@40026400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40026400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&clk_hclk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ resets = <&rcc 150>;
+ dma-requests = <8>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dma3.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dma3.yaml
new file mode 100644
index 0000000..7fdc44b
--- /dev/null
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dma3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DMA3 Controller
+
+description: |
+ The STM32 DMA3 is a direct memory access controller with different features
+ depending on its hardware configuration.
+ It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
+ Performance).
+ Its hardware configuration registers allow to dynamically expose its features.
+
+ GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
+ GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
+
+ Bindings are generic for these 3 STM32 DMA3 configurations.
+
+ DMA clients connected to the STM32 DMA3 controller must use the format
+ described in "#dma-cells" property description below, using a three-cell
+ specifier for each channel.
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@foss.st.com>
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: st,stm32mp25-dma3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 4
+ maxItems: 16
+ description:
+ Should contain all of the per-channel DMA interrupts in ascending order
+ with respect to the DMA channel index.
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ "#dma-cells":
+ const: 3
+ description: |
+ Specifies the number of cells needed to provide DMA controller specific
+ information.
+ The first cell is the request line number.
+ The second cell is a 32-bit mask specifying the DMA channel requirements:
+ -bit 0-1: The priority level
+ 0x0: low priority, low weight
+ 0x1: low priority, mid weight
+ 0x2: low priority, high weight
+ 0x3: high priority
+ -bit 4-7: The FIFO requirement for queuing source/destination transfers
+ 0x0: no FIFO requirement/any channel can fit
+ 0x2: FIFO of 8 bytes (2^2+1)
+ 0x4: FIFO of 32 bytes (2^4+1)
+ 0x6: FIFO of 128 bytes (2^6+1)
+ 0x7: FIFO of 256 bytes (2^7+1)
+ The third cell is a 32-bit mask specifying the DMA transfer requirements:
+ -bit 0: The source incrementing burst
+ 0x0: fixed burst
+ 0x1: contiguously incremented burst
+ -bit 1: The source allocated port
+ 0x0: port 0 is allocated to the source transfer
+ 0x1: port 1 is allocated to the source transfer
+ -bit 4: The destination incrementing burst
+ 0x0: fixed burst
+ 0x1: contiguously incremented burst
+ -bit 5: The destination allocated port
+ 0x0: port 0 is allocated to the destination transfer
+ 0x1: port 1 is allocated to the destination transfer
+ -bit 8: The type of hardware request
+ 0x0: burst
+ 0x1: block
+ -bit 9: The control mode
+ 0x0: DMA controller control mode
+ 0x1: peripheral control mode
+ -bit 12-13: The transfer complete event mode
+ 0x0: at block level, transfer complete event is generated at the end
+ of a block
+ 0x2: at LLI level, the transfer complete event is generated at the end
+ of the LLI transfer
+ including the update of the LLI if any
+ 0x3: at channel level, the transfer complete event is generated at the
+ end of the last LLI
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ dma-controller@40400000 {
+ compatible = "st,stm32mp25-dma3";
+ reg = <0x40400000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_BUS_HPDMA1>;
+ #dma-cells = <3>;
+ };
+...
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
new file mode 100644
index 0000000..f26c914
--- /dev/null
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dmamux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DMA MUX (DMA request router)
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@foss.st.com>
+
+allOf:
+ - $ref: /schemas/dma/dma-router.yaml#
+
+properties:
+ "#dma-cells":
+ const: 3
+
+ compatible:
+ const: st,stm32h7-dmamux
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - dma-masters
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ dma-router@40020800 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x40020800 0x3c>;
+ #dma-cells = <3>;
+ dma-requests = <128>;
+ dma-channels = <16>;
+ dma-masters = <&dma1>, <&dma2>;
+ clocks = <&timer_clk>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-mdma.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-mdma.yaml
new file mode 100644
index 0000000..45fe91d
--- /dev/null
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-mdma.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 MDMA Controller
+
+description: |
+ The STM32 MDMA is a general-purpose direct memory access controller capable of
+ supporting 64 independent DMA channels with 256 HW requests.
+ DMA clients connected to the STM32 MDMA controller must use the format
+ described in the dma.txt file, using a five-cell specifier for each channel:
+ a phandle to the MDMA controller plus the following five integer cells:
+ 1. The request line number
+ 2. The priority level
+ 0x0: Low
+ 0x1: Medium
+ 0x2: High
+ 0x3: Very high
+ 3. A 32bit mask specifying the DMA channel configuration
+ -bit 0-1: Source increment mode
+ 0x0: Source address pointer is fixed
+ 0x2: Source address pointer is incremented after each data transfer
+ 0x3: Source address pointer is decremented after each data transfer
+ -bit 2-3: Destination increment mode
+ 0x0: Destination address pointer is fixed
+ 0x2: Destination address pointer is incremented after each data transfer
+ 0x3: Destination address pointer is decremented after each data transfer
+ -bit 8-9: Source increment offset size
+ 0x0: byte (8bit)
+ 0x1: half-word (16bit)
+ 0x2: word (32bit)
+ 0x3: double-word (64bit)
+ -bit 10-11: Destination increment offset size
+ 0x0: byte (8bit)
+ 0x1: half-word (16bit)
+ 0x2: word (32bit)
+ 0x3: double-word (64bit)
+ -bit 25-18: The number of bytes to be transferred in a single transfer
+ (min = 1 byte, max = 128 bytes)
+ -bit 29:28: Trigger Mode
+ 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
+ 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
+ 0x2: Each MDMA request triggers a repeated block transfer
+ 0x3: Each MDMA request triggers a linked list transfer
+ 4. A 32bit value specifying the register to be used to acknowledge the request
+ if no HW ack signal is used by the MDMA client
+ 5. A 32bit mask specifying the value to be written to acknowledge the request
+ if no HW ack signal is used by the MDMA client
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@foss.st.com>
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ "#dma-cells":
+ const: 5
+
+ compatible:
+ const: st,stm32h7-mdma
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ st,ahb-addr-masks:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Array of u32 mask to list memory devices addressed via AHB bus.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ dma-controller@52000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x52000000 0x1000>;
+ interrupts = <122>;
+ clocks = <&timer_clk>;
+ resets = <&rcc 992>;
+ #dma-cells = <5>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ st,ahb-addr-masks = <0x20000000>, <0x00000000>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/eeprom/at24.yaml b/dts/upstream/Bindings/eeprom/at24.yaml
index 3c36cd0..e396e47 100644
--- a/dts/upstream/Bindings/eeprom/at24.yaml
+++ b/dts/upstream/Bindings/eeprom/at24.yaml
@@ -18,7 +18,9 @@
properties:
compatible:
contains:
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
+ anyOf:
+ - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
+ - enum: ["microchip,24aa025e48", "microchip,24aa025e64"]
required:
- compatible
@@ -103,9 +105,6 @@
# These are special cases that don't conform to the above pattern.
# Each requires a standard at24 model as fallback.
- items:
- - const: belling,bl24c16a
- - const: atmel,24c16
- - items:
- enum:
- rohm,br24g01
- rohm,br24t01
@@ -122,16 +121,25 @@
- rohm,br24g04
- const: atmel,24c04
- items:
- - const: renesas,r1ex24016
+ - enum:
+ - belling,bl24c16a
+ - renesas,r1ex24016
- const: atmel,24c16
- items:
- const: giantec,gt24c32a
- const: atmel,24c32
- items:
+ - const: onnn,n24s64b
+ - const: atmel,24c64
+ - items:
- enum:
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
+ - items:
+ - const: microchip,24aa025e48
+ - items:
+ - const: microchip,24aa025e64
- pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st
label:
diff --git a/dts/upstream/Bindings/eeprom/at25.yaml b/dts/upstream/Bindings/eeprom/at25.yaml
index 1715b0c..c31e5e7 100644
--- a/dts/upstream/Bindings/eeprom/at25.yaml
+++ b/dts/upstream/Bindings/eeprom/at25.yaml
@@ -28,6 +28,7 @@
- anvo,anv32e61w
- atmel,at25256B
- fujitsu,mb85rs1mt
+ - fujitsu,mb85rs256
- fujitsu,mb85rs64
- microchip,at25160bn
- microchip,25lc040
diff --git a/dts/upstream/Bindings/firmware/arm,scmi.yaml b/dts/upstream/Bindings/firmware/arm,scmi.yaml
index 7de2c29..4d823f3 100644
--- a/dts/upstream/Bindings/firmware/arm,scmi.yaml
+++ b/dts/upstream/Bindings/firmware/arm,scmi.yaml
@@ -72,14 +72,17 @@
- const: tx
- const: tx_reply
- const: rx
+ - const: rx_reply
minItems: 2
mboxes:
description:
List of phandle and mailbox channel specifiers. It should contain
- exactly one, two or three mailboxes; the first one or two for transmitting
- messages ("tx") and another optional ("rx") for receiving notifications
- and delayed responses, if supported by the platform.
+ exactly one, two, three or four mailboxes; the first one or two for
+ transmitting messages ("tx") and another optional ("rx") for receiving
+ notifications and delayed responses, if supported by the platform.
+ The optional ("rx_reply") is for notifications completion interrupt,
+ if supported by the platform.
The number of mailboxes needed for transmitting messages depends on the
type of channels exposed by the specific underlying mailbox controller;
one single channel descriptor is enough if such channel is bidirectional,
@@ -92,9 +95,10 @@
2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
+ 4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels
Any other combination of mboxes and shmem is invalid.
minItems: 1
- maxItems: 3
+ maxItems: 4
shmem:
description:
@@ -251,7 +255,9 @@
type: object
allOf:
- $ref: '#/$defs/protocol-node'
- - $ref: /schemas/pinctrl/pinctrl.yaml
+ - anyOf:
+ - $ref: /schemas/pinctrl/pinctrl.yaml
+ - $ref: /schemas/firmware/nxp,imx95-scmi-pinctrl.yaml
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/firmware/cznic,turris-omnia-mcu.yaml b/dts/upstream/Bindings/firmware/cznic,turris-omnia-mcu.yaml
new file mode 100644
index 0000000..af92496
--- /dev/null
+++ b/dts/upstream/Bindings/firmware/cznic,turris-omnia-mcu.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CZ.NIC's Turris Omnia MCU
+
+maintainers:
+ - Marek Behún <kabel@kernel.org>
+
+description:
+ The MCU on Turris Omnia acts as a system controller providing additional
+ GPIOs, interrupts, watchdog, system power off and wakeup configuration.
+
+properties:
+ compatible:
+ const: cznic,turris-omnia-mcu
+
+ reg:
+ description: MCU I2C slave address
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description: |
+ The first cell specifies the interrupt number (0 to 63), the second cell
+ specifies interrupt type (which can be one of IRQ_TYPE_EDGE_RISING,
+ IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH).
+ The interrupt numbers correspond sequentially to GPIO numbers, taking the
+ GPIO banks into account:
+ IRQ number GPIO bank GPIO pin within bank
+ 0 - 15 0 0 - 15
+ 16 - 47 1 0 - 31
+ 48 - 63 2 0 - 15
+ There are several exceptions:
+ IRQ number meaning
+ 11 LED panel brightness changed by button press
+ 13 TRNG entropy ready
+ 14 ECDSA message signature computation done
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 3
+ description:
+ The first cell is bank number (0, 1 or 2), the second cell is pin number
+ within the bank (0 to 15 for banks 0 and 2, 0 to 31 for bank 1), and the
+ third cell specifies consumer flags.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system-controller@2a {
+ compatible = "cznic,turris-omnia-mcu";
+ reg = <0x2a>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_NONE>;
+
+ gpio-controller;
+ #gpio-cells = <3>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/firmware/nxp,imx95-scmi-pinctrl.yaml b/dts/upstream/Bindings/firmware/nxp,imx95-scmi-pinctrl.yaml
new file mode 100644
index 0000000..a96fc6c
--- /dev/null
+++ b/dts/upstream/Bindings/firmware/nxp,imx95-scmi-pinctrl.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2024 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/nxp,imx95-scmi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX System Control and Management Interface (SCMI) Pinctrl Protocol
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+allOf:
+ - $ref: /schemas/pinctrl/pinctrl.yaml
+
+patternProperties:
+ 'grp$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ unevaluatedProperties: false
+
+ properties:
+ fsl,pins:
+ description:
+ each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
+ mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
+ be found in <arch/arm64/boot/dts/freescale/imx95-pinfunc.h>. The last
+ integer CONFIG is the pad setting value like pull-up on this pin.
+ Please refer to i.MX95 Reference Manual for detailed CONFIG settings.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "mux_reg" indicates the offset of mux register.
+ - description: |
+ "conf_reg" indicates the offset of pad configuration register.
+ - description: |
+ "input_reg" indicates the offset of select input register.
+ - description: |
+ "mux_val" indicates the mux value to be applied.
+ - description: |
+ "input_val" indicates the select input value to be applied.
+ - description: |
+ "pad_setting" indicates the pad configuration value to be applied.
+
+ required:
+ - fsl,pins
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/firmware/qcom,scm.yaml b/dts/upstream/Bindings/firmware/qcom,scm.yaml
index 47d3d2d..2cc8377 100644
--- a/dts/upstream/Bindings/firmware/qcom,scm.yaml
+++ b/dts/upstream/Bindings/firmware/qcom,scm.yaml
@@ -93,6 +93,11 @@
protocol to handle sleeping SCM calls.
maxItems: 1
+ memory-region:
+ description:
+ Phandle to the memory region reserved for the shared memory bridge to TZ.
+ maxItems: 1
+
qcom,sdi-enabled:
description:
Indicates that the SDI (Secure Debug Image) has been enabled by TZ
@@ -193,6 +198,16 @@
then:
properties:
interrupts: false
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,scm-sa8775p
+ then:
+ properties:
+ memory-region: false
required:
- compatible
diff --git a/dts/upstream/Bindings/fsi/aspeed,ast2600-fsi-master.yaml b/dts/upstream/Bindings/fsi/aspeed,ast2600-fsi-master.yaml
new file mode 100644
index 0000000..dfcc2fa
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/aspeed,ast2600-fsi-master.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed FSI master
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ The AST2600 and later contain two identical FSI masters. They share a
+ clock and have a separate interrupt line and output pins.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-fsi-master
+ - aspeed,ast2700-fsi-master
+
+ clocks:
+ maxItems: 1
+
+ cfam-reset-gpios:
+ maxItems: 1
+ description:
+ Output GPIO pin for CFAM reset
+
+ fsi-routing-gpios:
+ maxItems: 1
+ description:
+ Output GPIO pin for setting the FSI mux (internal or cabled)
+
+ fsi-mux-gpios:
+ maxItems: 1
+ description:
+ Input GPIO pin for detecting the desired FSI mux state
+
+ interrupts:
+ maxItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - aspeed,ast2600-fsi-master
+then:
+ properties:
+ reg:
+ maxItems: 1
+else:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: OPB control registers
+ - description: FSI controller registers
+ - description: FSI link address space
+ reg-names:
+ items:
+ - const: opb
+ - const: ctrl
+ - const: fsi
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+allOf:
+ - $ref: fsi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ast2600-clock.h>
+ #include <dt-bindings/gpio/aspeed-gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ fsi-master@1e79b000 {
+ compatible = "aspeed,ast2600-fsi-master";
+ reg = <0x1e79b000 0x94>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+ };
+ };
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ fsi-master@21800000 {
+ compatible = "aspeed,ast2700-fsi-master";
+ reg = <0x0 0x21800000 0x0 0x100>,
+ <0x0 0x21000000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x1000000>;
+ reg-names = "opb", "ctrl", "fsi";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&intc 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi0_default>;
+ clocks = <&syscon 40>;
+ };
+ };
diff --git a/dts/upstream/Bindings/fsi/fsi-controller.yaml b/dts/upstream/Bindings/fsi/fsi-controller.yaml
new file mode 100644
index 0000000..ffe1919
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/fsi-controller.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/fsi-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FSI Controller Common Properties
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The
+ FSI bus is connected to a CFAM (Common FRU Access Macro) which contains
+ various engines such as I2C controllers, SPI controllers, etc.
+
+properties:
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 0
+
+ '#interrupt-cells':
+ const: 1
+
+ bus-frequency:
+ minimum: 1
+ maximum: 200000000
+
+ interrupt-controller: true
+
+ no-scan-on-init:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The FSI controller cannot scan the bus during initialization.
+
+patternProperties:
+ "cfam@[0-9a-f],[0-9a-f]":
+ type: object
+ properties:
+ chip-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Processor index, a global unique chip ID which is used to identify
+ the physical location of the chip in a system specific way.
+
+ bus-frequency:
+ minimum: 1
+ maximum: 100000000
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ required:
+ - reg
+
+ additionalProperties: true
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/fsi/fsi-master-aspeed.txt b/dts/upstream/Bindings/fsi/fsi-master-aspeed.txt
deleted file mode 100644
index 9853fef..0000000
--- a/dts/upstream/Bindings/fsi/fsi-master-aspeed.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Device-tree bindings for AST2600 FSI master
--------------------------------------------
-
-The AST2600 contains two identical FSI masters. They share a clock and have a
-separate interrupt line and output pins.
-
-Required properties:
- - compatible: "aspeed,ast2600-fsi-master"
- - reg: base address and length
- - clocks: phandle and clock number
- - interrupts: platform dependent interrupt description
- - pinctrl-0: phandle to pinctrl node
- - pinctrl-names: pinctrl state
-
-Optional properties:
- - cfam-reset-gpios: GPIO for CFAM reset
-
- - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled)
- - fsi-mux-gpios: GPIO for detecting the desired FSI mux state
-
-
-Examples:
-
- fsi-master {
- compatible = "aspeed,ast2600-fsi-master", "fsi-master";
- reg = <0x1e79b000 0x94>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fsi1_default>;
- clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
-
- fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
- fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
-
- cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
- };
diff --git a/dts/upstream/Bindings/fsi/ibm,fsi2spi.yaml b/dts/upstream/Bindings/fsi/ibm,fsi2spi.yaml
index e2ca0b0..ad5c83f 100644
--- a/dts/upstream/Bindings/fsi/ibm,fsi2spi.yaml
+++ b/dts/upstream/Bindings/fsi/ibm,fsi2spi.yaml
@@ -9,11 +9,10 @@
maintainers:
- Eddie James <eajames@linux.ibm.com>
-description: |
+description:
This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this
- node will always be a child of an FSI CFAM node; see fsi.txt for details on
- FSI slave and CFAM nodes. This FSI2SPI engine provides access to a number of
- SPI controllers.
+ node will always be a child of an FSI CFAM node. This FSI2SPI engine provides
+ access to a number of SPI controllers.
properties:
compatible:
@@ -24,6 +23,17 @@
items:
- description: FSI slave address
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^spi@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/spi/ibm,spi-fsi.yaml
+
required:
- compatible
- reg
@@ -35,4 +45,22 @@
fsi2spi@1c00 {
compatible = "ibm,fsi2spi";
reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi@0 {
+ compatible = "ibm,spi-fsi";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "atmel,at25";
+ reg = <0>;
+ address-width = <24>;
+ pagesize = <256>;
+ size = <0x80000>;
+ spi-max-frequency = <1000000>;
+ };
+ };
};
diff --git a/dts/upstream/Bindings/fsi/ibm,i2cr-fsi-master.yaml b/dts/upstream/Bindings/fsi/ibm,i2cr-fsi-master.yaml
index 442cecd..e49ace3 100644
--- a/dts/upstream/Bindings/fsi/ibm,i2cr-fsi-master.yaml
+++ b/dts/upstream/Bindings/fsi/ibm,i2cr-fsi-master.yaml
@@ -26,7 +26,10 @@
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: fsi-controller.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/fsi/ibm,p9-fsi-controller.yaml b/dts/upstream/Bindings/fsi/ibm,p9-fsi-controller.yaml
new file mode 100644
index 0000000..29ea80f
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/ibm,p9-fsi-controller.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/ibm,p9-fsi-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached FSI Hub Controller
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ The FSI Hub Controller is an FSI controller, providing a number of FSI links,
+ located on a CFAM. Therefore this node will always be a child of an FSI CFAM
+ node.
+
+properties:
+ compatible:
+ enum:
+ - ibm,p9-fsi-controller
+
+ reg:
+ items:
+ - description: FSI slave address
+
+allOf:
+ - $ref: fsi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fsi@3400 {
+ compatible = "ibm,p9-fsi-controller";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/fsi/ibm,p9-occ.txt b/dts/upstream/Bindings/fsi/ibm,p9-occ.txt
deleted file mode 100644
index e733580..0000000
--- a/dts/upstream/Bindings/fsi/ibm,p9-occ.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC)
------------------------------------------------------------------------------
-
-This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from
-a service processor. See fsi.txt for details on bindings for FSI slave and CFAM
-nodes. The OCC is not an FSI slave device itself, rather it is accessed
-through the SBE FIFO.
-
-Required properties:
- - compatible = "ibm,p9-occ" or "ibm,p10-occ"
-
-Examples:
-
- occ {
- compatible = "ibm,p9-occ";
- };
diff --git a/dts/upstream/Bindings/fsi/ibm,p9-occ.yaml b/dts/upstream/Bindings/fsi/ibm,p9-occ.yaml
new file mode 100644
index 0000000..537eac7
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/ibm,p9-occ.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/ibm,p9-occ.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached On-Chip Controller (OCC)
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ The POWER processor On-Chip Controller (OCC) helps manage power and
+ thermals for the system, accessed through the FSI-attached SBEFIFO
+ from a service processor.
+
+properties:
+ compatible:
+ enum:
+ - ibm,p9-occ
+ - ibm,p10-occ
+
+ hwmon:
+ type: object
+ $ref: /schemas/hwmon/ibm,occ-hwmon.yaml
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ occ {
+ compatible = "ibm,p9-occ";
+
+ hwmon {
+ compatible = "ibm,p9-occ-hwmon";
+ };
+ };
diff --git a/dts/upstream/Bindings/fsi/ibm,p9-sbefifo.yaml b/dts/upstream/Bindings/fsi/ibm,p9-sbefifo.yaml
new file mode 100644
index 0000000..3cd966f
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/ibm,p9-sbefifo.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/ibm,p9-sbefifo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached SBEFIFO engine
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ The SBEFIFO is an FSI CFAM engine that provides an interface to the
+ POWER processor Self Boot Engine (SBE). This node will always be a child
+ of an FSI CFAM node.
+
+properties:
+ compatible:
+ enum:
+ - ibm,p9-sbefifo
+ - ibm,odyssey-sbefifo
+
+ reg:
+ items:
+ - description: FSI slave address
+
+ occ:
+ type: object
+ $ref: ibm,p9-occ.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ fsi-slave-engine@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+
+ occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
diff --git a/dts/upstream/Bindings/fsi/ibm,p9-scom.yaml b/dts/upstream/Bindings/fsi/ibm,p9-scom.yaml
new file mode 100644
index 0000000..8cd14a7
--- /dev/null
+++ b/dts/upstream/Bindings/fsi/ibm,p9-scom.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fsi/ibm,p9-scom.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached SCOM engine
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ The SCOM engine is an interface to the POWER processor PIB (Pervasive
+ Interconnect Bus). This node will always be a child of an FSI CFAM node.
+
+properties:
+ compatible:
+ enum:
+ - ibm,p9-scom
+ - ibm,i2cr-scom
+
+ reg:
+ items:
+ - description: FSI slave address
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ scom@1000 {
+ compatible = "ibm,p9-scom";
+ reg = <0x1000 0x400>;
+ };
diff --git a/dts/upstream/Bindings/fuse/renesas,rcar-efuse.yaml b/dts/upstream/Bindings/fuse/renesas,rcar-efuse.yaml
new file mode 100644
index 0000000..d7e2892
--- /dev/null
+++ b/dts/upstream/Bindings/fuse/renesas,rcar-efuse.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/renesas,rcar-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: R-Car E-FUSE connected to PFC
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The E-FUSE is a type of non-volatile memory, which is accessible through the
+ Pin Function Controller (PFC) on some R-Car Gen4 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a779a0-efuse # R-Car V3U
+ - renesas,r8a779f0-efuse # R-Car S4-8
+
+ reg:
+ maxItems: 1
+ description: PFC System Group Fuse Control and Monitor register block
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+ #include <dt-bindings/power/r8a779a0-sysc.h>
+
+ fuse: fuse@e6078800 {
+ compatible = "renesas,r8a779a0-efuse";
+ reg = <0xe6078800 0x100>;
+ clocks = <&cpg CPG_MOD 916>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ };
diff --git a/dts/upstream/Bindings/fuse/renesas,rcar-otp.yaml b/dts/upstream/Bindings/fuse/renesas,rcar-otp.yaml
new file mode 100644
index 0000000..d74872a
--- /dev/null
+++ b/dts/upstream/Bindings/fuse/renesas,rcar-otp.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: R-Car E-FUSE connected to OTP_MEM
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The E-FUSE is a type of non-volatile memory, which is accessible through the
+ One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a779g0-otp # R-CarV4H
+ - renesas,r8a779h0-otp # R-CarV4M
+
+ reg:
+ items:
+ - description: OTP_MEM_0
+ - description: OTP_MEM_1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ otp: otp@e61be000 {
+ compatible = "renesas,r8a779g0-otp";
+ reg = <0xe61be000 0x1000>, <0xe61bf000 0x1000>;
+ };
diff --git a/dts/upstream/Bindings/gpio/aspeed,sgpio.yaml b/dts/upstream/Bindings/gpio/aspeed,sgpio.yaml
index 46bb121..1046f03 100644
--- a/dts/upstream/Bindings/gpio/aspeed,sgpio.yaml
+++ b/dts/upstream/Bindings/gpio/aspeed,sgpio.yaml
@@ -33,6 +33,11 @@
gpio-controller: true
+ # Each SGPIO is represented as a pair of input and output GPIOs
+ gpio-line-names:
+ minItems: 160
+ maxItems: 256
+
'#gpio-cells':
const: 2
@@ -41,6 +46,9 @@
interrupt-controller: true
+ '#interrupt-cells':
+ const: 2
+
clocks:
maxItems: 1
@@ -55,6 +63,7 @@
- '#gpio-cells'
- interrupts
- interrupt-controller
+ - '#interrupt-cells'
- ngpios
- clocks
- bus-frequency
@@ -72,6 +81,7 @@
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
+ #interrupt-cells = <2>;
ngpios = <80>;
bus-frequency = <12000000>;
};
diff --git a/dts/upstream/Bindings/gpio/atmel,at91rm9200-gpio.yaml b/dts/upstream/Bindings/gpio/atmel,at91rm9200-gpio.yaml
new file mode 100644
index 0000000..3dd7093
--- /dev/null
+++ b/dts/upstream/Bindings/gpio/atmel,at91rm9200-gpio.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/atmel,at91rm9200-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip GPIO controller (PIO)
+
+maintainers:
+ - Manikandan Muralidharan <manikandan.m@microchip.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - atmel,at91sam9x5-gpio
+ - microchip,sam9x60-gpio
+ - const: atmel,at91rm9200-gpio
+ - items:
+ - enum:
+ - microchip,sam9x7-gpio
+ - const: microchip,sam9x60-gpio
+ - const: atmel,at91rm9200-gpio
+ - items:
+ - const: atmel,at91rm9200-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ gpio-controller: true
+ gpio-line-names: true
+
+ "#gpio-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-lines":
+ description:
+ Number of gpio, 32 by default if absent
+ maxItems: 1
+ default: 32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - gpio-controller
+ - "#gpio-cells"
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+...
diff --git a/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
new file mode 100644
index 0000000..84fd822
--- /dev/null
+++ b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/fsl,qoriq-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,mpc5121-gpio
+ - fsl,mpc5125-gpio
+ - fsl,mpc8349-gpio
+ - fsl,mpc8572-gpio
+ - fsl,mpc8610-gpio
+ - fsl,pq3-gpio
+ - items:
+ - enum:
+ - fsl,ls1021a-gpio
+ - fsl,ls1028a-gpio
+ - fsl,ls1043a-gpio
+ - fsl,ls1046a-gpio
+ - fsl,ls1088a-gpio
+ - fsl,ls2080a-gpio
+ - const: fsl,qoriq-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 32
+
+ little-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ GPIO registers are used as little endian. If not
+ present registers are used as big endian by default.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@1100 {
+ compatible = "fsl,mpc5125-gpio";
+ reg = <0x1100 0x080>;
+ interrupts = <78 0x8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ gpio@2300000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x2300000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/dts/upstream/Bindings/gpio/fsl-imx-gpio.yaml b/dts/upstream/Bindings/gpio/fsl-imx-gpio.yaml
index 918776d..e1fc8bb 100644
--- a/dts/upstream/Bindings/gpio/fsl-imx-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/fsl-imx-gpio.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX/MXC GPIO controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/gpio/gpio-mpc8xxx.txt b/dts/upstream/Bindings/gpio/gpio-mpc8xxx.txt
deleted file mode 100644
index cd28e93..0000000
--- a/dts/upstream/Bindings/gpio/gpio-mpc8xxx.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
-
-Required properties:
-- compatible : Should be "fsl,<soc>-gpio"
- The following <soc>s are known to be supported:
- mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
- ls1021a, ls1043a, ls2080a, ls1028a, ls1088a.
-- reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all 32 pins.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
-
-Optional properties:
-- little-endian : GPIO registers are used as little endian. If not
- present registers are used as big endian by default.
-
-Example of gpio-controller node for a mpc5125 SoC:
-
-gpio0: gpio@1100 {
- compatible = "fsl,mpc5125-gpio";
- #gpio-cells = <2>;
- reg = <0x1100 0x080>;
- interrupts = <78 0x8>;
-};
-
-Example of gpio-controller node for a ls2080a SoC:
-
-gpio0: gpio@2300000 {
- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
- reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <0 36 0x4>; /* Level high type */
- gpio-controller;
- little-endian;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
-};
-
-
-Example of gpio-controller node for a ls1028a/ls1088a SoC:
-
-gpio1: gpio@2300000 {
- compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
- reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
-};
diff --git a/dts/upstream/Bindings/gpio/gpio-mxs.yaml b/dts/upstream/Bindings/gpio/gpio-mxs.yaml
index dfa1133..8ff5436 100644
--- a/dts/upstream/Bindings/gpio/gpio-mxs.yaml
+++ b/dts/upstream/Bindings/gpio/gpio-mxs.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Anson Huang <Anson.Huang@nxp.com>
description: |
The Freescale MXS GPIO controller is part of MXS PIN controller.
diff --git a/dts/upstream/Bindings/gpio/gpio-pca95xx.yaml b/dts/upstream/Bindings/gpio/gpio-pca95xx.yaml
index 99febb8..51e8390 100644
--- a/dts/upstream/Bindings/gpio/gpio-pca95xx.yaml
+++ b/dts/upstream/Bindings/gpio/gpio-pca95xx.yaml
@@ -66,6 +66,7 @@
- ti,tca6408
- ti,tca6416
- ti,tca6424
+ - ti,tca9535
- ti,tca9538
- ti,tca9539
- ti,tca9554
diff --git a/dts/upstream/Bindings/gpio/gpio-vf610.yaml b/dts/upstream/Bindings/gpio/gpio-vf610.yaml
index a27f929..cabda2e 100644
--- a/dts/upstream/Bindings/gpio/gpio-vf610.yaml
+++ b/dts/upstream/Bindings/gpio/gpio-vf610.yaml
@@ -51,6 +51,10 @@
gpio-controller: true
+ gpio-line-names:
+ minItems: 1
+ maxItems: 32
+
clocks:
items:
- description: SoC GPIO clock
diff --git a/dts/upstream/Bindings/gpio/gpio-zevio.txt b/dts/upstream/Bindings/gpio/gpio-zevio.txt
deleted file mode 100644
index a37bd9a..0000000
--- a/dts/upstream/Bindings/gpio/gpio-zevio.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Zevio GPIO controller
-
-Required properties:
-- compatible: Should be "lsi,zevio-gpio"
-- reg: Address and length of the register set for the device
-- #gpio-cells: Should be two. The first cell is the pin number and the
- second cell is used to specify optional parameters (currently unused).
-- gpio-controller: Marks the device node as a GPIO controller.
-
-Example:
- gpio: gpio@90000000 {
- compatible = "lsi,zevio-gpio";
- reg = <0x90000000 0x1000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
diff --git a/dts/upstream/Bindings/gpio/gpio_atmel.txt b/dts/upstream/Bindings/gpio/gpio_atmel.txt
deleted file mode 100644
index 29416f9..0000000
--- a/dts/upstream/Bindings/gpio/gpio_atmel.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Atmel GPIO controller (PIO)
-
-Required properties:
-- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
-- reg: Should contain GPIO controller registers location and length
-- interrupts: Should be the port interrupt shared by all the pins.
-- #gpio-cells: Should be two. The first cell is the pin number and
- the second cell is used to specify optional parameters to declare if the GPIO
- is active high or low. See gpio.txt.
-- gpio-controller: Marks the device node as a GPIO controller.
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells: Should be two. The first cell is the pin number and the
- second cell is used to specify irq type flags, see the two cell description
- in interrupt-controller/interrupts.txt for details.
-
-optional properties:
-- #gpio-lines: Number of gpio if absent 32.
-
-
-Example:
- pioA: gpio@fffff200 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff200 0x100>;
- interrupts = <2 4>;
- #gpio-cells = <2>;
- gpio-controller;
- #gpio-lines = <19>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
diff --git a/dts/upstream/Bindings/gpio/lsi,zevio-gpio.yaml b/dts/upstream/Bindings/gpio/lsi,zevio-gpio.yaml
new file mode 100644
index 0000000..e9e201a
--- /dev/null
+++ b/dts/upstream/Bindings/gpio/lsi,zevio-gpio.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/lsi,zevio-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Zevio GPIO controller
+
+maintainers:
+ - Pratik Farkase <pratikfarkase94@gmail.com>
+
+properties:
+ compatible:
+ items:
+ - const: lsi,zevio-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ gpio@90000000 {
+ compatible = "lsi,zevio-gpio";
+ reg = <0x90000000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml b/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml
index e796a1f..278399a 100644
--- a/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml
@@ -34,6 +34,7 @@
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
- items:
- enum:
+ - mediatek,mt8188-mali
- mediatek,mt8192-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
@@ -195,7 +196,9 @@
properties:
compatible:
contains:
- const: mediatek,mt8183b-mali
+ enum:
+ - mediatek,mt8183b-mali
+ - mediatek,mt8188-mali
then:
properties:
power-domains:
diff --git a/dts/upstream/Bindings/hwmon/g762.txt b/dts/upstream/Bindings/hwmon/g762.txt
deleted file mode 100644
index 6d154c4..0000000
--- a/dts/upstream/Bindings/hwmon/g762.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-GMT G762/G763 PWM Fan controller
-
-Required node properties:
-
- - "compatible": must be either "gmt,g762" or "gmt,g763"
- - "reg": I2C bus address of the device
- - "clocks": a fixed clock providing input clock frequency
- on CLK pin of the chip.
-
-Optional properties:
-
- - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3.
- The higher the more.
-
- - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty)
- and 1 (negative duty).
-
- - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2.
-
-If an optional property is not set in .dts file, then current value is kept
-unmodified (e.g. u-boot installed value).
-
-Additional information on operational parameters for the device is available
-in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available
-at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
-
-Example g762 node:
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- g762_clk: fixedclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <8192>;
- }
- }
-
- g762: g762@3e {
- compatible = "gmt,g762";
- reg = <0x3e>;
- clocks = <&g762_clk>
- fan_gear_mode = <0>; /* chip default */
- fan_startv = <1>; /* chip default */
- pwm_polarity = <0>; /* chip default */
- };
diff --git a/dts/upstream/Bindings/hwmon/gmt,g762.yaml b/dts/upstream/Bindings/hwmon/gmt,g762.yaml
new file mode 100644
index 0000000..8e1bffd
--- /dev/null
+++ b/dts/upstream/Bindings/hwmon/gmt,g762.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/gmt,g762.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GMT G761/G762/G763 PWM Fan controller
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: |
+ GMT G761/G762/G763 PWM Fan controller.
+
+ G761 supports an internal-clock hence the clocks property is optional.
+ If not defined, internal-clock will be used. (31KHz is the clock of
+ the internal crystal oscillator)
+
+ If an optional property is not set in DT, then current value is kept
+ unmodified (e.g. bootloader installed value).
+
+ Additional information on operational parameters for the device is available
+ in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available
+ at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
+
+properties:
+ compatible:
+ enum:
+ - gmt,g761
+ - gmt,g762
+ - gmt,g763
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: a fixed clock providing input clock frequency on CLK
+ pin of the chip.
+ maxItems: 1
+
+ fan_startv:
+ description: Fan startup voltage step
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ pwm_polarity:
+ description: PWM polarity (positive or negative duty)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ fan_gear_mode:
+ description: FAN gear mode. Configure High speed fan setting factor
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+required:
+ - compatible
+ - reg
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - gmt,g762
+ - gmt,g763
+then:
+ required:
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ g762@3e {
+ compatible = "gmt,g762";
+ reg = <0x3e>;
+ clocks = <&g762_clk>;
+ fan_gear_mode = <0>;
+ fan_startv = <1>;
+ pwm_polarity = <0>;
+ };
+
+ g761@1e {
+ compatible = "gmt,g761";
+ reg = <0x1e>;
+ fan_gear_mode = <0>;
+ fan_startv = <1>;
+ pwm_polarity = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/hwmon/maxim,max6639.yaml b/dts/upstream/Bindings/hwmon/maxim,max6639.yaml
new file mode 100644
index 0000000..4f5837a
--- /dev/null
+++ b/dts/upstream/Bindings/hwmon/maxim,max6639.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/maxim,max6639.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim max6639
+
+maintainers:
+ - Naresh Solanki <naresh.solanki@9elements.com>
+
+description: |
+ The MAX6639 is a 2-channel temperature monitor with dual, automatic, PWM
+ fan-speed controller. It monitors its own temperature and one external
+ diode-connected transistor or the temperatures of two external diode-connected
+ transistors, typically available in CPUs, FPGAs, or GPUs.
+
+ Datasheets:
+ https://datasheets.maximintegrated.com/en/ds/MAX6639-MAX6639F.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,max6639
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#pwm-cells':
+ const: 3
+
+required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^fan@[0-1]$":
+ type: object
+ description:
+ Represents the two fans and their specific configuration.
+
+ $ref: fan-common.yaml#
+
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description:
+ The fan number.
+
+ required:
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan1: fan-controller@10 {
+ compatible = "maxim,max6639";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <3>;
+
+ fan@0 {
+ reg = <0x0>;
+ pulses-per-revolution = <2>;
+ max-rpm = <4000>;
+ target-rpm = <1000>;
+ pwms = <&fan1 0 25000 0>;
+ };
+
+ fan@1 {
+ reg = <0x1>;
+ pulses-per-revolution = <2>;
+ max-rpm = <8000>;
+ pwms = <&fan1 1 25000 0>;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/hwmon/ti,ina2xx.yaml b/dts/upstream/Bindings/hwmon/ti,ina2xx.yaml
index df86c2c..6ae9617 100644
--- a/dts/upstream/Bindings/hwmon/ti,ina2xx.yaml
+++ b/dts/upstream/Bindings/hwmon/ti,ina2xx.yaml
@@ -66,6 +66,14 @@
description: phandle to the regulator that provides the VS supply typically
in range from 2.7 V to 5.5 V.
+ ti,alert-polarity-active-high:
+ description: Alert pin is asserted based on the value of Alert polarity Bit
+ of Mask/Enable register. Default value is Normal (0 which maps to
+ active-low open collector). The other value is Inverted
+ (1 which maps to active-high open collector). Specify this property to set
+ the alert polarity to active-high.
+ $ref: /schemas/types.yaml#/definitions/flag
+
required:
- compatible
- reg
@@ -88,5 +96,6 @@
label = "vdd_3v0";
shunt-resistor = <1000>;
vs-supply = <&vdd_3v0>;
+ ti,alert-polarity-active-high;
};
};
diff --git a/dts/upstream/Bindings/hwmon/ti,tmp108.yaml b/dts/upstream/Bindings/hwmon/ti,tmp108.yaml
index 8b5307c..0ad10d4 100644
--- a/dts/upstream/Bindings/hwmon/ti,tmp108.yaml
+++ b/dts/upstream/Bindings/hwmon/ti,tmp108.yaml
@@ -9,6 +9,14 @@
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
+description: |
+ The TMP108 is a digital-output temperature sensor with a
+ dynamically-programmable limit window, and under- and overtemperature
+ alert functions.
+
+ Datasheets:
+ https://www.ti.com/product/TMP108
+
properties:
compatible:
enum:
@@ -24,6 +32,9 @@
"#thermal-sensor-cells":
const: 0
+ vcc-supply:
+ description: phandle to the regulator that provides the V+ supply
+
required:
- compatible
- reg
@@ -45,6 +56,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tmp_alrt>;
+ vcc-supply = <&supply>;
#thermal-sensor-cells = <0>;
};
};
diff --git a/dts/upstream/Bindings/i2c/amlogic,meson6-i2c.yaml b/dts/upstream/Bindings/i2c/amlogic,meson6-i2c.yaml
index 26bed55..c4cc8af 100644
--- a/dts/upstream/Bindings/i2c/amlogic,meson6-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/amlogic,meson6-i2c.yaml
@@ -30,6 +30,9 @@
clocks:
minItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/i2c/atmel,at91sam-i2c.yaml b/dts/upstream/Bindings/i2c/atmel,at91sam-i2c.yaml
index b2d19cf..e61cdb5 100644
--- a/dts/upstream/Bindings/i2c/atmel,at91sam-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/atmel,at91sam-i2c.yaml
@@ -26,6 +26,7 @@
- microchip,sam9x60-i2c
- items:
- enum:
+ - microchip,sama7d65-i2c
- microchip,sama7g5-i2c
- microchip,sam9x7-i2c
- const: microchip,sam9x60-i2c
@@ -36,12 +37,6 @@
interrupts:
maxItems: 1
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 0
-
clocks:
maxItems: 1
@@ -72,8 +67,6 @@
- compatible
- reg
- interrupts
- - "#address-cells"
- - "#size-cells"
- clocks
allOf:
@@ -86,6 +79,7 @@
- atmel,sama5d4-i2c
- atmel,sama5d2-i2c
- microchip,sam9x60-i2c
+ - microchip,sama7d65-i2c
- microchip,sama7g5-i2c
then:
properties:
diff --git a/dts/upstream/Bindings/i2c/brcm,brcmstb-i2c.yaml b/dts/upstream/Bindings/i2c/brcm,brcmstb-i2c.yaml
index 7070c04..ac9ddf2 100644
--- a/dts/upstream/Bindings/i2c/brcm,brcmstb-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/brcm,brcmstb-i2c.yaml
@@ -76,21 +76,21 @@
examples:
- |
- bsca: i2c@f0406200 {
- clock-frequency = <390000>;
- compatible = "brcm,brcmstb-i2c";
- interrupt-parent = <&irq0_intc>;
- reg = <0xf0406200 0x58>;
- interrupts = <0x18>;
- interrupt-names = "upg_bsca";
- };
+ bsca: i2c@f0406200 {
+ compatible = "brcm,brcmstb-i2c";
+ reg = <0xf0406200 0x58>;
+ clock-frequency = <390000>;
+ interrupt-parent = <&irq0_intc>;
+ interrupts = <0x18>;
+ interrupt-names = "upg_bsca";
+ };
- |
- ddc0: i2c@7ef04500 {
- compatible = "brcm,bcm2711-hdmi-i2c";
- reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
- reg-names = "bsc", "auto-i2c";
- clock-frequency = <390000>;
- };
+ ddc0: i2c@7ef04500 {
+ compatible = "brcm,bcm2711-hdmi-i2c";
+ reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
+ reg-names = "bsc", "auto-i2c";
+ clock-frequency = <390000>;
+ };
...
diff --git a/dts/upstream/Bindings/i2c/i2c-demux-pinctrl.yaml b/dts/upstream/Bindings/i2c/i2c-demux-pinctrl.yaml
index b813f6d..1eaf00b 100644
--- a/dts/upstream/Bindings/i2c/i2c-demux-pinctrl.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-demux-pinctrl.yaml
@@ -109,65 +109,65 @@
// Example for a bus to be demuxed. It contains various I2C clients for
// HDMI, so the bus is named "i2c-hdmi":
i2chdmi: i2c-mux3 {
- compatible = "i2c-demux-pinctrl";
- i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
- i2c-bus-name = "i2c-hdmi";
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- };
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
- composite-in@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep0>;
- };
- };
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep0>;
+ };
};
+ };
- hdmi@39 {
- compatible = "adi,adv7511w";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&cec_clock>;
- clock-names = "cec";
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
- avdd-supply = <&fixedregulator1v8>;
- dvdd-supply = <&fixedregulator1v8>;
- pvdd-supply = <&fixedregulator1v8>;
- dvdd-3v-supply = <&fixedregulator3v3>;
- bgvdd-supply = <&fixedregulator1v8>;
+ avdd-supply = <&fixedregulator1v8>;
+ dvdd-supply = <&fixedregulator1v8>;
+ pvdd-supply = <&fixedregulator1v8>;
+ dvdd-3v-supply = <&fixedregulator3v3>;
+ bgvdd-supply = <&fixedregulator1v8>;
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- port@0 {
- reg = <0>;
- adv7511_in: endpoint {
- remote-endpoint = <&lvds0_out>;
- };
- };
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_con_out>;
- };
- };
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
};
+ };
};
+ };
};
diff --git a/dts/upstream/Bindings/i2c/i2c-fsi.txt b/dts/upstream/Bindings/i2c/i2c-fsi.txt
deleted file mode 100644
index b1be2ce..0000000
--- a/dts/upstream/Bindings/i2c/i2c-fsi.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Device-tree bindings for FSI-attached I2C master and busses
------------------------------------------------------------
-
-Required properties:
- - compatible = "ibm,i2c-fsi";
- - reg = < address size >; : The FSI CFAM address and address
- space size.
- - #address-cells = <1>; : Number of address cells in child
- nodes.
- - #size-cells = <0>; : Number of size cells in child nodes.
- - child nodes : Nodes to describe busses off the I2C
- master.
-
-Child node required properties:
- - reg = < port number > : The port number on the I2C master.
-
-Child node optional properties:
- - child nodes : Nodes to describe devices on the I2C
- bus.
-
-Examples:
-
- i2c@1800 {
- compatible = "ibm,i2c-fsi";
- reg = < 0x1800 0x400 >;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c-bus@0 {
- reg = <0>;
- };
-
- i2c-bus@1 {
- reg = <1>;
-
- eeprom@50 {
- compatible = "vendor,dev-name";
- };
- };
- };
diff --git a/dts/upstream/Bindings/i2c/i2c-imx-lpi2c.yaml b/dts/upstream/Bindings/i2c/i2c-imx-lpi2c.yaml
index 54d500b..1dcb9c7 100644
--- a/dts/upstream/Bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-imx-lpi2c.yaml
@@ -7,7 +7,9 @@
title: Freescale Low Power Inter IC (LPI2C) for i.MX
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
diff --git a/dts/upstream/Bindings/i2c/i2c-lpc2k.txt b/dts/upstream/Bindings/i2c/i2c-lpc2k.txt
deleted file mode 100644
index 4101aa6..0000000
--- a/dts/upstream/Bindings/i2c/i2c-lpc2k.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-NXP I2C controller for LPC2xxx/178x/18xx/43xx
-
-Required properties:
- - compatible: must be "nxp,lpc1788-i2c"
- - reg: physical address and length of the device registers
- - interrupts: a single interrupt specifier
- - clocks: clock for the device
- - #address-cells: should be <1>
- - #size-cells: should be <0>
-
-Optional properties:
-- clock-frequency: the desired I2C bus clock frequency in Hz; in
- absence of this property the default value is used (100 kHz).
-
-Example:
-i2c0: i2c@400a1000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400a1000 0x1000>;
- interrupts = <18>;
- clocks = <&ccu1 CLK_APB1_I2C0>;
- #address-cells = <1>;
- #size-cells = <0>;
-};
-
-&i2c0 {
- clock-frequency = <400000>;
-
- lm75@48 {
- compatible = "nxp,lm75";
- reg = <0x48>;
- };
-};
-
diff --git a/dts/upstream/Bindings/i2c/i2c-mux-gpio.yaml b/dts/upstream/Bindings/i2c/i2c-mux-gpio.yaml
index f34cc7a..4a93d1f 100644
--- a/dts/upstream/Bindings/i2c/i2c-mux-gpio.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-mux-gpio.yaml
@@ -57,6 +57,9 @@
last value used.
$ref: /schemas/types.yaml#/definitions/uint32
+ settle-time-us:
+ description: Delay to wait before doing any transfer when a new bus gets selected.
+
allOf:
- $ref: i2c-mux.yaml
diff --git a/dts/upstream/Bindings/i2c/ibm,i2c-fsi.yaml b/dts/upstream/Bindings/i2c/ibm,i2c-fsi.yaml
new file mode 100644
index 0000000..40ea829
--- /dev/null
+++ b/dts/upstream/Bindings/i2c/ibm,i2c-fsi.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/ibm,i2c-fsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached I2C controller
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ This I2C controller is an FSI CFAM engine, providing access to a number of
+ I2C busses. Therefore this node will always be a child of an FSI CFAM node.
+
+properties:
+ compatible:
+ enum:
+ - ibm,i2c-fsi
+
+ reg:
+ items:
+ - description: FSI slave address
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^i2c-bus@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+ allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c@1800 {
+ compatible = "ibm,i2c-fsi";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-bus@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c-bus@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/i2c/nvidia,tegra20-i2c.yaml b/dts/upstream/Bindings/i2c/nvidia,tegra20-i2c.yaml
index 424a4fc..92fbc1a 100644
--- a/dts/upstream/Bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/nvidia,tegra20-i2c.yaml
@@ -87,12 +87,6 @@
interrupts:
maxItems: 1
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
clocks:
minItems: 1
maxItems: 2
diff --git a/dts/upstream/Bindings/i2c/nxp,lpc1788-i2c.yaml b/dts/upstream/Bindings/i2c/nxp,lpc1788-i2c.yaml
new file mode 100644
index 0000000..9a1b95c
--- /dev/null
+++ b/dts/upstream/Bindings/i2c/nxp,lpc1788-i2c.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nxp,lpc1788-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP I2C controller for LPC2xxx/178x/18xx/43xx
+
+maintainers:
+ - Vladimir Zapolskiy <vz@mleia.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: nxp,lpc1788-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: the desired I2C bus clock frequency in Hz
+ default: 100000
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/lpc18xx-ccu.h"
+
+ i2c@400a1000 {
+ compatible = "nxp,lpc1788-i2c";
+ reg = <0x400a1000 0x1000>;
+ interrupts = <18>;
+ clocks = <&ccu1 CLK_APB1_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
index daf4e71..c33ae7b 100644
--- a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
+++ b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
@@ -31,6 +31,8 @@
- qcom,sm6350-cci
- qcom,sm8250-cci
- qcom,sm8450-cci
+ - qcom,sm8550-cci
+ - qcom,sm8650-cci
- const: qcom,msm8996-cci # CCI v2
"#address-cells":
@@ -195,6 +197,24 @@
- const: cpas_ahb
- const: cci
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8550-cci
+ - qcom,sm8650-cci
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: cpas_ahb
+ - const: cci
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/i2c/renesas,iic-emev2.yaml b/dts/upstream/Bindings/i2c/renesas,iic-emev2.yaml
index 17c1102..551cfa6 100644
--- a/dts/upstream/Bindings/i2c/renesas,iic-emev2.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,iic-emev2.yaml
@@ -44,11 +44,11 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
iic0: i2c@e0070000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-emev2";
- reg = <0xe0070000 0x28>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
- clocks = <&iic0_sclk>;
- clock-names = "sclk";
+ compatible = "renesas,iic-emev2";
+ reg = <0xe0070000 0x28>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&iic0_sclk>;
+ clock-names = "sclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
diff --git a/dts/upstream/Bindings/i2c/renesas,rcar-i2c.yaml b/dts/upstream/Bindings/i2c/renesas,rcar-i2c.yaml
index 51b220d..6cc60c3 100644
--- a/dts/upstream/Bindings/i2c/renesas,rcar-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,rcar-i2c.yaml
@@ -153,14 +153,14 @@
#include <dt-bindings/power/r8a7791-sysc.h>
i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0xe6508000 0x40>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <400000>;
- clocks = <&cpg CPG_MOD 931>;
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
- resets = <&cpg 931>;
- i2c-scl-internal-delay-ns = <6>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0xe6508000 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
diff --git a/dts/upstream/Bindings/i2c/renesas,riic.yaml b/dts/upstream/Bindings/i2c/renesas,riic.yaml
index 91ecf17..7993fe4 100644
--- a/dts/upstream/Bindings/i2c/renesas,riic.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,riic.yaml
@@ -97,21 +97,21 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c0: i2c@fcfee000 {
- compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
- reg = <0xfcfee000 0x44>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
- "tmoi";
- clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
- clock-frequency = <100000>;
- power-domains = <&cpg_clocks>;
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfee000 0x44>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
+ "tmoi";
+ clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
diff --git a/dts/upstream/Bindings/i2c/renesas,rmobile-iic.yaml b/dts/upstream/Bindings/i2c/renesas,rmobile-iic.yaml
index 04e4ffd..ec5222a 100644
--- a/dts/upstream/Bindings/i2c/renesas,rmobile-iic.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,rmobile-iic.yaml
@@ -134,16 +134,16 @@
#include <dt-bindings/power/r8a7790-sysc.h>
iic0: i2c@e6500000 {
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0xe6500000 0x425>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 318>;
- clock-frequency = <400000>;
- dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>;
- dma-names = "tx", "rx", "tx", "rx";
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 318>;
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0xe6500000 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-frequency = <400000>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
diff --git a/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml b/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
index 1303502..bbc5684 100644
--- a/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
@@ -26,9 +26,6 @@
- samsung,exynos850-i2c
- const: samsung,s3c2440-i2c
- '#address-cells':
- const: 1
-
clocks:
maxItems: 1
@@ -73,9 +70,6 @@
$ref: /schemas/types.yaml#/definitions/phandle
description: Pandle to syscon used to control the system registers.
- '#size-cells':
- const: 0
-
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml b/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml
index d9293c5..60035a7 100644
--- a/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/snps,designware-i2c.yaml
@@ -33,6 +33,10 @@
- const: snps,designware-i2c
- description: Baikal-T1 SoC System I2C controller
const: baikal,bt1-sys-i2c
+ - description: T-HEAD TH1520 SoCs I2C controller
+ items:
+ - const: thead,th1520-i2c
+ - const: snps,designware-i2c
reg:
minItems: 1
diff --git a/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml b/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
index 8fd8be7..457bb07 100644
--- a/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
@@ -145,31 +145,31 @@
#include <dt-bindings/mfd/stm32f7-rcc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
//Example 1 (with st,stm32f4-i2c compatible)
- i2c@40005400 {
- compatible = "st,stm32f4-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005400 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc 277>;
- clocks = <&rcc 0 149>;
- };
+ i2c@40005400 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc 277>;
+ clocks = <&rcc 0 149>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- |
#include <dt-bindings/mfd/stm32f7-rcc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
//Example 2 (with st,stm32f7-i2c compatible)
- i2c@40005800 {
- compatible = "st,stm32f7-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40005800 0x400>;
- interrupts = <31>,
- <32>;
- resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
- clocks = <&rcc 1 CLK_I2C1>;
- };
+ i2c@40005800 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x40005800 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+ clocks = <&rcc 1 CLK_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- |
#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -178,16 +178,16 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
- i2c@40013000 {
- compatible = "st,stm32mp15-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x40013000 0x400>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc I2C2_K>;
- resets = <&rcc I2C2_R>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- st,syscfg-fmp = <&syscfg 0x4 0x2>;
- };
+ i2c@40013000 {
+ compatible = "st,stm32mp15-i2c";
+ reg = <0x40013000 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C2_K>;
+ resets = <&rcc I2C2_R>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/i2c/ti,omap4-i2c.yaml b/dts/upstream/Bindings/i2c/ti,omap4-i2c.yaml
index 781108a..8c2e35f 100644
--- a/dts/upstream/Bindings/i2c/ti,omap4-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/ti,omap4-i2c.yaml
@@ -37,16 +37,8 @@
clock-names:
const: fck
- clock-frequency: true
-
power-domains: true
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 0
-
ti,hwmods:
description:
Must be "i2c<n>", n being the instance number (1-based).
@@ -55,38 +47,34 @@
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
-# subnode's properties
-patternProperties:
- "@[0-9a-f]+$":
- type: object
- description:
- Flash device uses the below defined properties in the subnode.
-
required:
- compatible
- reg
- interrupts
-additionalProperties: false
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
-if:
- properties:
- compatible:
- enum:
- - ti,omap2420-i2c
- - ti,omap2430-i2c
- - ti,omap3-i2c
- - ti,omap4-i2c
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap2420-i2c
+ - ti,omap2430-i2c
+ - ti,omap3-i2c
+ - ti,omap4-i2c
-then:
- properties:
- ti,hwmods:
- items:
- - pattern: "^i2c([1-9])$"
+ then:
+ properties:
+ ti,hwmods:
+ items:
+ - pattern: "^i2c([1-9])$"
-else:
- properties:
- ti,hwmods: false
+ else:
+ properties:
+ ti,hwmods: false
+
+unevaluatedProperties: false
examples:
- |
@@ -94,9 +82,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
main_i2c0: i2c@2000000 {
- compatible = "ti,j721e-i2c", "ti,omap4-i2c";
- reg = <0x2000000 0x100>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x2000000 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/i3c/i3c.yaml b/dts/upstream/Bindings/i3c/i3c.yaml
index 113957e..e25fa72 100644
--- a/dts/upstream/Bindings/i3c/i3c.yaml
+++ b/dts/upstream/Bindings/i3c/i3c.yaml
@@ -91,6 +91,7 @@
- const: 0
- description: |
Shall encode the I3C LVR (Legacy Virtual Register):
+ See include/dt-bindings/i3c/i3c.h
bit[31:8]: unused/ignored
bit[7:5]: I2C device index. Possible values:
* 0: I2C device has a 50 ns spike filter
@@ -153,6 +154,8 @@
examples:
- |
+ #include <dt-bindings/i3c/i3c.h>
+
i3c@d040000 {
compatible = "cdns,i3c-master";
clocks = <&coreclock>, <&i3csysclock>;
@@ -166,7 +169,7 @@
/* I2C device. */
eeprom@57 {
compatible = "atmel,24c01";
- reg = <0x57 0x0 0x10>;
+ reg = <0x57 0x0 (I2C_FM | I2C_FILTER)>;
pagesize = <0x8>;
};
diff --git a/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml b/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml
index c0e805e..4fc13e3 100644
--- a/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml
+++ b/dts/upstream/Bindings/i3c/snps,dw-i3c-master.yaml
@@ -20,7 +20,16 @@
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: Core clock
+ - description: APB clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: apb
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/adc/adc.yaml b/dts/upstream/Bindings/iio/adc/adc.yaml
index 36775f8..8e7835c 100644
--- a/dts/upstream/Bindings/iio/adc/adc.yaml
+++ b/dts/upstream/Bindings/iio/adc/adc.yaml
@@ -38,6 +38,25 @@
The first value specifies the positive input pin, the second
specifies the negative input pin.
+ single-channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ When devices combine single-ended and differential channels, allow the
+ channel for a single element to be specified, independent of reg (as for
+ differential channels). If this and diff-channels are not present reg
+ shall be used instead.
+
+ common-mode-channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some ADCs have differential input pins that can be used to measure
+ single-ended or pseudo-differential inputs. This property can be used
+ in addition to single-channel to signal software that this channel is
+ not differential but still specify two inputs.
+
+ The input pair is specified by setting single-channel to the positive
+ input pin and common-mode-channel to the negative pin.
+
settling-time-us:
description:
Time between enabling the channel and first stable readings.
@@ -50,4 +69,15 @@
device design and can interact with other characteristics such as
settling time.
+anyOf:
+ - oneOf:
+ - required:
+ - reg
+ - diff-channels
+ - required:
+ - reg
+ - single-channel
+ - required:
+ - reg
+
additionalProperties: true
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
index ea6cfcd..17c5d39 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
@@ -19,7 +19,18 @@
primarily for measurement of signals close to DC but also delivers
outstanding performance with input bandwidths out to ~10kHz.
+ Analog Devices AD411x ADC's:
+ The AD411X family encompasses a series of low power, low noise, 24-bit,
+ sigma-delta analog-to-digital converters that offer a versatile range of
+ specifications. They integrate an analog front end suitable for processing
+ fully differential/single-ended and bipolar voltage inputs.
+
Datasheets for supported chips:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4111.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4112.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4114.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4115.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD4116.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-2.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7172-4.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7173-8.pdf
@@ -31,6 +42,11 @@
properties:
compatible:
enum:
+ - adi,ad4111
+ - adi,ad4112
+ - adi,ad4114
+ - adi,ad4115
+ - adi,ad4116
- adi,ad7172-2
- adi,ad7172-4
- adi,ad7173-8
@@ -129,10 +145,56 @@
maximum: 15
diff-channels:
+ description: |
+ This property is used for defining the inputs of a differential
+ voltage channel. The first value is the positive input and the second
+ value is the negative input of the channel.
+
+ Family AD411x supports a dedicated VINCOM voltage input.
+ To select it set the second channel to 16.
+ (VIN2, VINCOM) -> diff-channels = <2 16>
+
+ There are special values that can be selected besides the voltage
+ analog inputs:
+ 21: REF+
+ 22: REF−
+
+ Supported only by AD7172-2, AD7172-4, AD7175-2, AD7175-8, AD7177-2,
+ must be paired together and can be used to monitor the power supply
+ of the ADC:
+ 19: ((AVDD1 − AVSS)/5)+
+ 20: ((AVDD1 − AVSS)/5)−
+
items:
minimum: 0
maximum: 31
+ single-channel:
+ description: |
+ This property is used for defining a current channel or the positive
+ input of a voltage channel (single-ended or pseudo-differential).
+
+ Models AD4111 and AD4112 support current channels.
+ Example: (IIN2+, IIN2−) -> single-channel = <2>
+ To correctly configure a current channel set the "adi,current-channel"
+ property to true.
+
+ To configure a single-ended/pseudo-differential channel set the
+ "common-mode-channel" property to the desired negative voltage input.
+
+ When used as a voltage channel, special inputs are valid as well.
+ minimum: 0
+ maximum: 31
+
+ common-mode-channel:
+ description:
+ This property is used for defining the negative input of a
+ single-ended or pseudo-differential voltage channel.
+
+ Special inputs are valid as well.
+ minimum: 0
+ maximum: 31
+
adi,reference-select:
description: |
Select the reference source to use when converting on
@@ -154,9 +216,31 @@
- avdd
default: refout-avss
+ adi,current-channel:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Signal that the selected inputs are current channels.
+ Only available on AD4111 and AD4112.
+
required:
- reg
- - diff-channels
+
+ allOf:
+ - oneOf:
+ - required: [single-channel]
+ properties:
+ diff-channels: false
+ - required: [diff-channels]
+ properties:
+ single-channel: false
+ adi,current-channel: false
+ common-mode-channel: false
+
+ - if:
+ required: [common-mode-channel]
+ then:
+ properties:
+ adi,current-channel: false
required:
- compatible
@@ -166,7 +250,6 @@
- $ref: /schemas/spi/spi-peripheral-props.yaml#
# Only ad7172-4, ad7173-8 and ad7175-8 support vref2
- # Other models have [0-3] channel registers
- if:
properties:
compatible:
@@ -187,6 +270,37 @@
- vref
- refout-avss
- avdd
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad4114
+ - adi,ad4115
+ - adi,ad4116
+ - adi,ad7173-8
+ - adi,ad7175-8
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]$":
+ properties:
+ reg:
+ maximum: 15
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7172-2
+ - adi,ad7175-2
+ - adi,ad7176-2
+ - adi,ad7177-2
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]$":
+ properties:
reg:
maximum: 3
@@ -211,6 +325,34 @@
- adi,reference-select
- if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad4111
+ - adi,ad4112
+ - adi,ad4114
+ - adi,ad4115
+ - adi,ad4116
+ then:
+ properties:
+ avdd2-supply: false
+
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ enum:
+ - adi,ad4111
+ - adi,ad4112
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]$":
+ properties:
+ adi,current-channel: false
+
+ - if:
anyOf:
- required: [clock-names]
- required: [clocks]
@@ -221,6 +363,7 @@
unevaluatedProperties: false
examples:
+ # Example AD7173-8 with external reference connected to REF+/REF-:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -277,3 +420,50 @@
};
};
};
+
+ # Example AD4111 with current channel and single-ended channel:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad4111";
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "rdy";
+ interrupt-parent = <&gpio>;
+ spi-max-frequency = <5000000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ bipolar;
+ diff-channels = <4 5>;
+ };
+
+ // Single ended channel VIN2/VINCOM
+ channel@1 {
+ reg = <1>;
+ bipolar;
+ single-channel = <2>;
+ common-mode-channel = <16>;
+ };
+
+ // Current channel IN2+/IN2-
+ channel@2 {
+ reg = <2>;
+ single-channel = <2>;
+ adi,current-channel;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
index 16def29..190889c 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
@@ -21,8 +21,15 @@
- adi,ad7190
- adi,ad7192
- adi,ad7193
+ - adi,ad7194
- adi,ad7195
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
reg:
maxItems: 1
@@ -41,6 +48,11 @@
interrupts:
maxItems: 1
+ aincom-supply:
+ description: |
+ AINCOM voltage supply. Analog inputs AINx are referenced to this input
+ when configured for pseudo-differential operation.
+
dvdd-supply:
description: DVdd voltage supply
@@ -84,6 +96,41 @@
description: see Documentation/devicetree/bindings/iio/adc/adc.yaml
type: boolean
+patternProperties:
+ "^channel@[0-9a-f]+$":
+ type: object
+ $ref: adc.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: The channel index.
+ minimum: 0
+ maximum: 271
+
+ diff-channels:
+ description:
+ Both inputs can be connected to pins AIN1 to AIN16 by choosing the
+ appropriate value from 1 to 16.
+ items:
+ minimum: 1
+ maximum: 16
+
+ single-channel:
+ description:
+ Positive input can be connected to pins AIN1 to AIN16 by choosing the
+ appropriate value from 1 to 16. Negative input is connected to AINCOM.
+ minimum: 1
+ maximum: 16
+
+ oneOf:
+ - required:
+ - reg
+ - diff-channels
+ - required:
+ - reg
+ - single-channel
+
required:
- compatible
- reg
@@ -98,6 +145,17 @@
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - adi,ad7190
+ - adi,ad7192
+ - adi,ad7193
+ - adi,ad7195
+ then:
+ patternProperties:
+ "^channel@[0-9a-f]+$": false
unevaluatedProperties: false
@@ -117,6 +175,7 @@
clock-names = "mclk";
interrupts = <25 0x2>;
interrupt-parent = <&gpio>;
+ aincom-supply = <&aincom>;
dvdd-supply = <&dvdd>;
avdd-supply = <&avdd>;
vref-supply = <&vref>;
@@ -127,3 +186,38 @@
adi,burnout-currents-enable;
};
};
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7194";
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ spi-cpha;
+ clocks = <&ad7192_mclk>;
+ clock-names = "mclk";
+ interrupts = <25 0x2>;
+ interrupt-parent = <&gpio>;
+ aincom-supply = <&aincom>;
+ dvdd-supply = <&dvdd>;
+ avdd-supply = <&avdd>;
+ vref-supply = <&vref>;
+
+ channel@0 {
+ reg = <0>;
+ diff-channels = <1 6>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ single-channel = <1>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml
new file mode 100644
index 0000000..899b777
--- /dev/null
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7380.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7380.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices Simultaneous Sampling Analog to Digital Converters
+
+maintainers:
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+ - Nuno Sá <nuno.sa@analog.com>
+
+description: |
+ * https://www.analog.com/en/products/ad7380.html
+ * https://www.analog.com/en/products/ad7381.html
+ * https://www.analog.com/en/products/ad7383.html
+ * https://www.analog.com/en/products/ad7384.html
+ * https://www.analog.com/en/products/ad7380-4.html
+ * https://www.analog.com/en/products/ad7381-4.html
+ * https://www.analog.com/en/products/ad7383-4.html
+ * https://www.analog.com/en/products/ad7384-4.html
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7380
+ - adi,ad7381
+ - adi,ad7383
+ - adi,ad7384
+ - adi,ad7380-4
+ - adi,ad7381-4
+ - adi,ad7383-4
+ - adi,ad7384-4
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 80000000
+ spi-cpol: true
+ spi-cpha: true
+
+ vcc-supply:
+ description: A 3V to 3.6V supply that powers the chip.
+
+ vlogic-supply:
+ description:
+ A 1.65V to 3.6V supply for the logic pins.
+
+ refio-supply:
+ description:
+ A 2.5V to 3.3V supply for the external reference voltage. When omitted,
+ the internal 2.5V reference is used.
+
+ aina-supply:
+ description:
+ The common mode voltage supply for the AINA- pin on pseudo-differential
+ chips.
+
+ ainb-supply:
+ description:
+ The common mode voltage supply for the AINB- pin on pseudo-differential
+ chips.
+
+ ainc-supply:
+ description:
+ The common mode voltage supply for the AINC- pin on pseudo-differential
+ chips.
+
+ aind-supply:
+ description:
+ The common mode voltage supply for the AIND- pin on pseudo-differential
+ chips.
+
+ interrupts:
+ description:
+ When the device is using 1-wire mode, this property is used to optionally
+ specify the ALERT interrupt.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - vcc-supply
+ - vlogic-supply
+
+unevaluatedProperties: false
+
+allOf:
+ # pseudo-differential chips require common mode voltage supplies,
+ # true differential chips don't use them
+ - if:
+ properties:
+ compatible:
+ enum:
+ - adi,ad7383
+ - adi,ad7384
+ - adi,ad7383-4
+ - adi,ad7384-4
+ then:
+ required:
+ - aina-supply
+ - ainb-supply
+ else:
+ properties:
+ aina-supply: false
+ ainb-supply: false
+ - if:
+ properties:
+ compatible:
+ enum:
+ - adi,ad7383-4
+ - adi,ad7384-4
+ then:
+ required:
+ - ainc-supply
+ - aind-supply
+ else:
+ properties:
+ ainc-supply: false
+ aind-supply: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7380";
+ reg = <0>;
+
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <80000000>;
+
+ interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio0>;
+
+ vcc-supply = <&supply_3_3V>;
+ vlogic-supply = <&supply_3_3V>;
+ refio-supply = <&supply_2_5V>;
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
index 7fa46df..00fdaed 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
@@ -11,6 +11,7 @@
description: |
Analog Devices AD7606 Simultaneous Sampling ADC
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
@@ -19,9 +20,9 @@
compatible:
enum:
- adi,ad7605-4
- - adi,ad7606-8
- - adi,ad7606-6
- adi,ad7606-4
+ - adi,ad7606-6
+ - adi,ad7606-8 # Referred to as AD7606 (without -8) in the datasheet
- adi,ad7606b
- adi,ad7616
diff --git a/dts/upstream/Bindings/iio/adc/amlogic,meson-saradc.yaml b/dts/upstream/Bindings/iio/adc/amlogic,meson-saradc.yaml
index 7e8328e..f748f3a 100644
--- a/dts/upstream/Bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/dts/upstream/Bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -66,6 +66,9 @@
nvmem-cell-names:
const: temperature_calib
+ power-domains:
+ maxItems: 1
+
allOf:
- if:
properties:
diff --git a/dts/upstream/Bindings/iio/adc/mediatek,mt6359-auxadc.yaml b/dts/upstream/Bindings/iio/adc/mediatek,mt6359-auxadc.yaml
new file mode 100644
index 0000000..6497c41
--- /dev/null
+++ b/dts/upstream/Bindings/iio/adc/mediatek,mt6359-auxadc.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/mediatek,mt6359-auxadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT6350 series PMIC AUXADC
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+ in some MediaTek PMICs, performing various PMIC related measurements
+ such as battery and PMIC internal voltage regulators temperatures,
+ accessory detection resistance (usually, for a 3.5mm audio jack)
+ other than voltages for various PMIC internal components.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt6357-auxadc
+ - mediatek,mt6358-auxadc
+ - mediatek,mt6359-auxadc
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+additionalProperties: false
diff --git a/dts/upstream/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/dts/upstream/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index c1b1324..2722eda 100644
--- a/dts/upstream/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/dts/upstream/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -246,6 +246,10 @@
From common IIO binding. Used to pipe external sigma delta
modulator or internal ADC output to DFSDM channel.
+ port:
+ $ref: /schemas/sound/audio-graph-port.yaml#
+ unevaluatedProperties: false
+
required:
- compatible
- "#sound-dai-cells"
diff --git a/dts/upstream/Bindings/iio/adc/ti,ads1015.yaml b/dts/upstream/Bindings/iio/adc/ti,ads1015.yaml
index d605999..718f633 100644
--- a/dts/upstream/Bindings/iio/adc/ti,ads1015.yaml
+++ b/dts/upstream/Bindings/iio/adc/ti,ads1015.yaml
@@ -18,6 +18,7 @@
enum:
- ti,ads1015
- ti,ads1115
+ - ti,tla2021
- ti,tla2024
reg:
diff --git a/dts/upstream/Bindings/iio/adc/ti,ads1119.yaml b/dts/upstream/Bindings/iio/adc/ti,ads1119.yaml
new file mode 100644
index 0000000..ba6850a
--- /dev/null
+++ b/dts/upstream/Bindings/iio/adc/ti,ads1119.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1119.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS1119 ADC
+
+maintainers:
+ - João Paulo Gonçalves <jpaulo.silvagoncalves@gmail.com>
+
+description:
+ The TI ADS1119 is a precision 16-bit ADC over I2C that offers single-ended and
+ differential measurements using a multiplexed input. It features a programmable
+ gain, a programmable sample rate, an internal oscillator and voltage reference,
+ and a 50/60Hz rejection filter.
+
+properties:
+ compatible:
+ const: ti,ads1119
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ avdd-supply: true
+ dvdd-supply: true
+
+ vref-supply:
+ description:
+ ADC external reference voltage (VREF).
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - avdd-supply
+ - dvdd-supply
+
+patternProperties:
+ "^channel@([0-6])$":
+ $ref: adc.yaml
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 6
+
+ diff-channels:
+ description:
+ Differential input channels AIN0-AIN1, AIN2-AIN3 and AIN1-AIN2.
+ oneOf:
+ - items:
+ - const: 0
+ - const: 1
+ - items:
+ - const: 2
+ - const: 3
+ - items:
+ - const: 1
+ - const: 2
+
+ single-channel:
+ description:
+ Single-ended input channels AIN0, AIN1, AIN2 and AIN3.
+ minimum: 0
+ maximum: 3
+
+ oneOf:
+ - required:
+ - diff-channels
+ - required:
+ - single-channel
+
+ required:
+ - reg
+
+ unevaluatedProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@40 {
+ compatible = "ti,ads1119";
+ reg = <0x40>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ avdd-supply = <®_avdd_ads1119>;
+ dvdd-supply = <®_dvdd_ads1119>;
+ vref-supply = <®_vref_ads1119>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@0 {
+ reg = <0>;
+ single-channel = <0>;
+ };
+
+ channel@1 {
+ reg = <1>;
+ diff-channels = <0 1>;
+ };
+
+ channel@2 {
+ reg = <2>;
+ single-channel = <3>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ single-channel = <1>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ single-channel = <2>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ diff-channels = <1 2>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ diff-channels = <2 3>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/chemical/sciosense,ens160.yaml b/dts/upstream/Bindings/iio/chemical/sciosense,ens160.yaml
new file mode 100644
index 0000000..267033a
--- /dev/null
+++ b/dts/upstream/Bindings/iio/chemical/sciosense,ens160.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/chemical/sciosense,ens160.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ScioSense ENS160 multi-gas sensor
+
+maintainers:
+ - Gustavo Silva <gustavograzs@gmail.com>
+
+description: |
+ Digital Multi-Gas Sensor for Monitoring Indoor Air Quality.
+
+ Datasheet:
+ https://www.sciosense.com/wp-content/uploads/2023/12/ENS160-Datasheet.pdf
+
+properties:
+ compatible:
+ enum:
+ - sciosense,ens160
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply: true
+ vddio-supply: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gas-sensor@52 {
+ compatible = "sciosense,ens160";
+ reg = <0x52>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gas-sensor@0 {
+ compatible = "sciosense,ens160";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/iio/dac/adi,ad3552r.yaml b/dts/upstream/Bindings/iio/dac/adi,ad3552r.yaml
index 8265d70..fc8b97f 100644
--- a/dts/upstream/Bindings/iio/dac/adi,ad3552r.yaml
+++ b/dts/upstream/Bindings/iio/dac/adi,ad3552r.yaml
@@ -13,13 +13,17 @@
description: |
Bindings for the Analog Devices AD3552R DAC device and similar.
Datasheet can be found here:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad3541r.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3542r.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad3551r.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3552r.pdf
properties:
compatible:
enum:
+ - adi,ad3541r
- adi,ad3542r
+ - adi,ad3551r
- adi,ad3552r
reg:
@@ -92,13 +96,13 @@
maximum: 511
minimum: -511
- adi,gain-scaling-p-inv-log2:
- description: GainP = 1 / ( 2 ^ adi,gain-scaling-p-inv-log2)
+ adi,gain-scaling-p:
+ description: GainP = 1 / ( 2 ^ adi,gain-scaling-p)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
- adi,gain-scaling-n-inv-log2:
- description: GainN = 1 / ( 2 ^ adi,gain-scaling-n-inv-log2)
+ adi,gain-scaling-n:
+ description: GainN = 1 / ( 2 ^ adi,gain-scaling-n)
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
@@ -107,8 +111,8 @@
required:
- adi,gain-offset
- - adi,gain-scaling-p-inv-log2
- - adi,gain-scaling-n-inv-log2
+ - adi,gain-scaling-p
+ - adi,gain-scaling-n
- adi,rfb-ohms
required:
@@ -128,7 +132,9 @@
properties:
compatible:
contains:
- const: adi,ad3542r
+ enum:
+ - adi,ad3541r
+ - adi,ad3542r
then:
patternProperties:
"^channel@([0-1])$":
@@ -158,7 +164,9 @@
properties:
compatible:
contains:
- const: adi,ad3552r
+ enum:
+ - adi,ad3551r
+ - adi,ad3552r
then:
patternProperties:
"^channel@([0-1])$":
@@ -182,6 +190,21 @@
- const: -10000000
- const: 10000000
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad3541r
+ - adi,ad3551r
+ then:
+ properties:
+ channel@1: false
+ channel@0:
+ properties:
+ reg:
+ const: 0
+
required:
- compatible
- reg
@@ -208,8 +231,8 @@
reg = <1>;
custom-output-range-config {
adi,gain-offset = <5>;
- adi,gain-scaling-p-inv-log2 = <1>;
- adi,gain-scaling-n-inv-log2 = <2>;
+ adi,gain-scaling-p = <1>;
+ adi,gain-scaling-n = <2>;
adi,rfb-ohms = <1>;
};
};
diff --git a/dts/upstream/Bindings/iio/frequency/adi,adf4350.yaml b/dts/upstream/Bindings/iio/frequency/adi,adf4350.yaml
index 43cbf27..d1d1311 100644
--- a/dts/upstream/Bindings/iio/frequency/adi,adf4350.yaml
+++ b/dts/upstream/Bindings/iio/frequency/adi,adf4350.yaml
@@ -28,6 +28,12 @@
clock-names:
const: clkin
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
gpios:
maxItems: 1
description: Lock detect GPIO.
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
index 9b7ad60..9d185f7 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
@@ -30,12 +30,19 @@
- adi,adis16467-2
- adi,adis16467-3
- adi,adis16500
+ - adi,adis16501
- adi,adis16505-1
- adi,adis16505-2
- adi,adis16505-3
- adi,adis16507-1
- adi,adis16507-2
- adi,adis16507-3
+ - adi,adis16575-2
+ - adi,adis16575-3
+ - adi,adis16576-2
+ - adi,adis16576-3
+ - adi,adis16577-2
+ - adi,adis16577-3
reg:
maxItems: 1
@@ -90,12 +97,19 @@
contains:
enum:
- adi,adis16500
+ - adi,adis16501
- adi,adis16505-1
- adi,adis16505-2
- adi,adis16505-3
- adi,adis16507-1
- adi,adis16507-2
- adi,adis16507-3
+ - adi,adis16575-2
+ - adi,adis16575-3
+ - adi,adis16576-2
+ - adi,adis16576-3
+ - adi,adis16577-2
+ - adi,adis16577-3
then:
properties:
@@ -112,6 +126,23 @@
dependencies:
adi,sync-mode: [ clocks ]
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,adis16575-2
+ - adi,adis16575-3
+ - adi,adis16576-2
+ - adi,adis16576-3
+ - adi,adis16577-2
+ - adi,adis16577-3
+
+ then:
+ properties:
+ spi-max-frequency:
+ maximum: 15000000
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
index 56e0dc2..e3eec38 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
@@ -23,6 +23,12 @@
- adi,adis16497-1
- adi,adis16497-2
- adi,adis16497-3
+ - adi,adis16545-1
+ - adi,adis16545-2
+ - adi,adis16545-3
+ - adi,adis16547-1
+ - adi,adis16547-2
+ - adi,adis16547-3
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
index 47cfba9..3b0a2d8 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
@@ -16,7 +16,11 @@
properties:
compatible:
- const: bosch,bmi160
+ oneOf:
+ - const: bosch,bmi160
+ - items:
+ - const: bosch,bmi120
+ - const: bosch,bmi160
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml b/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml
index 91c3187..ecf2339 100644
--- a/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml
+++ b/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml
@@ -4,14 +4,19 @@
$id: http://devicetree.org/schemas/iio/light/vishay,veml6075.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Vishay VEML6075 UVA and UVB sensor
+title: Vishay VEML6075 UVA/B and VEML6040 RGBW sensors
maintainers:
- Javier Carrasco <javier.carrasco.cruz@gmail.com>
+description:
+ VEML6040 datasheet at https://www.vishay.com/docs/84276/veml6040.pdf
+
properties:
compatible:
- const: vishay,veml6075
+ enum:
+ - vishay,veml6040
+ - vishay,veml6075
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/magnetometer/fsl,mag3110.yaml b/dts/upstream/Bindings/iio/magnetometer/fsl,mag3110.yaml
index 6b54d32..fbe8c2e 100644
--- a/dts/upstream/Bindings/iio/magnetometer/fsl,mag3110.yaml
+++ b/dts/upstream/Bindings/iio/magnetometer/fsl,mag3110.yaml
@@ -7,7 +7,7 @@
title: Freescale MAG3110 magnetometer sensor
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Jonathan Cameron <jic23@kernel.org>
properties:
compatible:
diff --git a/dts/upstream/Bindings/iio/st,st-sensors.yaml b/dts/upstream/Bindings/iio/st,st-sensors.yaml
index fff7e3d..71c1ee3 100644
--- a/dts/upstream/Bindings/iio/st,st-sensors.yaml
+++ b/dts/upstream/Bindings/iio/st,st-sensors.yaml
@@ -26,6 +26,7 @@
- st,lis2dw12
- st,lis2hh12
- st,lis2dh12-accel
+ - st,lis2ds12
- st,lis302dl
- st,lis331dl-accel
- st,lis331dlh-accel
diff --git a/dts/upstream/Bindings/incomplete-devices.yaml b/dts/upstream/Bindings/incomplete-devices.yaml
new file mode 100644
index 0000000..cfc1d39
--- /dev/null
+++ b/dts/upstream/Bindings/incomplete-devices.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/incomplete-devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rejected, Legacy or Incomplete Devices
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ Some devices will not or should not get a proper Devicetree bindings, but
+ their compatibles are present in Linux drivers for various reasons.
+
+ Examples are devices using ACPI PRP0001 with non-updatable firmware/ACPI
+ tables or old PowerPC platforms without in-tree DTS.
+
+ Following list of devices is an incomplete schema with a goal to pass DT schema
+ checks on undocumented compatibles but also reject any DTS file using such
+ un-approved compatible.
+
+ Usage of any of following compatibles is not allowed in Devicetree sources,
+ even if they come from immutable firmware.
+
+properties:
+ compatible:
+ oneOf:
+ - description:
+ Rejected compatibles in Devicetree, but used in ACPI-based devices
+ with non-updatable firmware/ACPI tables (via ACPI PRP0001)
+ enum:
+ - broadcom,bcm5241
+ - ltr,ltrf216a
+
+ - description: Legacy compatibles used on Macintosh devices
+ enum:
+ - adm1030
+ - bmac+
+ - heathrow-media-bay
+ - keylargo-media-bay
+ - lm87cimt
+ - MAC,adm1030
+ - MAC,ds1775
+ - max6690
+ - ohare-media-bay
+ - ohare-swim3
+ - smu-sat
+ - swim3
+
+ - description: Legacy compatibles used on other PowerPC devices
+ enum:
+ - 1682m-rng
+ - IBM,lhca
+ - IBM,lhea
+ - IBM,lhea-ethernet
+ - mpc5200b-fec-phy
+ - mpc5200-serial
+ - mpc5200-sram
+ - ohci-be
+ - ohci-bigendian
+ - ohci-le
+
+ - description: Legacy compatibles used on SPARC devices
+ enum:
+ - bq4802
+ - ds1287
+ - isa-m5819p
+ - isa-m5823p
+ - m5819
+ - sab82532
+ - SUNW,bbc-beep
+ - SUNW,bbc-i2c
+ - SUNW,CS4231
+ - SUNW,ebus-pic16f747-env
+ - SUNW,kt-cwq
+ - SUNW,kt-mau
+ - SUNW,n2-cwq
+ - SUNW,n2-mau
+ - SUNW,niusl
+ - SUNW,smbus-beep
+ - SUNW,sun4v-console
+ - SUNW,sun4v-pci
+ - SUNW,vf-cwq
+ - SUNW,vf-mau
+
+ - description: Incomplete and/or legacy compatibles for unknown devices
+ enum:
+ - electra-cf
+ - i2cpcf,8584
+ - virtio,uml
+
+ - description: Linux kernel unit tests and sample code
+ enum:
+ - audio-graph-card2-custom-sample
+ - compat1
+ - compat2
+ - compat3
+ - linux,spi-loopback-test
+ - mailbox-test
+ - regulator-virtual-consumer
+
+ - description:
+ Devices on MIPS platform, without any DTS users. These are
+ unlikely to get converted to DT schema.
+ enum:
+ - mti,ranchu
+
+ - description:
+ Devices on PowerPC platform, without any DTS users. These are
+ unlikely to get converted to DT schema.
+ enum:
+ - fujitsu,coral
+ - fujitsu,lime
+ - fujitsu,MB86276
+ - fujitsu,MB86277
+ - fujitsu,MB86293
+ - fujitsu,MB86294
+ - fujitsu,mint
+ - ibm,axon-msic
+ - ibm,pmemory
+ - ibm,pmemory-v2
+ - ibm,power-rng
+ - ibm,ppc4xx-spi
+ - ibm,sdram-4xx-ddr2
+ - ibm,secureboot
+ - ibm,secureboot-v1
+ - ibm,secureboot-v2
+ - ibm,secvar-backend
+ - sgy,gpio-halt
+ - wrs,epld-localbus
+
+required:
+ - compatible
+ - broken-usage-of-incorrect-compatible
+
+additionalProperties: false
diff --git a/dts/upstream/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/dts/upstream/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
index c384bf0..6bdb804 100644
--- a/dts/upstream/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
+++ b/dts/upstream/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml
@@ -22,7 +22,9 @@
- const: allwinner,sun8i-a83t-r-lradc
- const: allwinner,sun50i-r329-lradc
- items:
- - const: allwinner,sun20i-d1-lradc
+ - enum:
+ - allwinner,sun50i-h616-lradc
+ - allwinner,sun20i-d1-lradc
- const: allwinner,sun50i-r329-lradc
reg:
diff --git a/dts/upstream/Bindings/input/cirrus,cs40l50.yaml b/dts/upstream/Bindings/input/cirrus,cs40l50.yaml
new file mode 100644
index 0000000..89bd068
--- /dev/null
+++ b/dts/upstream/Bindings/input/cirrus,cs40l50.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/cirrus,cs40l50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic CS40L50 Advanced Haptic Driver
+
+maintainers:
+ - James Ogletree <jogletre@opensource.cirrus.com>
+
+description:
+ CS40L50 is a haptic driver with waveform memory,
+ integrated DSP, and closed-loop algorithms.
+
+properties:
+ compatible:
+ enum:
+ - cirrus,cs40l50
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vdd-a-supply:
+ description: Power supply for internal analog circuits.
+
+ vdd-p-supply:
+ description: Power supply for always-on circuits.
+
+ vdd-io-supply:
+ description: Power supply for digital input/output.
+
+ vdd-b-supply:
+ description: Power supply for the boost converter.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - reset-gpios
+ - vdd-io-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ haptic-driver@34 {
+ compatible = "cirrus,cs40l50";
+ reg = <0x34>;
+ interrupt-parent = <&gpio>;
+ interrupts = <113 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio 112 GPIO_ACTIVE_LOW>;
+ vdd-io-supply = <&vreg>;
+ };
+ };
diff --git a/dts/upstream/Bindings/input/ti,nspire-keypad.txt b/dts/upstream/Bindings/input/ti,nspire-keypad.txt
deleted file mode 100644
index 513d94d..0000000
--- a/dts/upstream/Bindings/input/ti,nspire-keypad.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-TI-NSPIRE Keypad
-
-Required properties:
-- compatible: Compatible property value should be "ti,nspire-keypad".
-
-- reg: Physical base address of the peripheral and length of memory mapped
- region.
-
-- interrupts: The interrupt number for the peripheral.
-
-- scan-interval: How often to scan in us. Based on a APB speed of 33MHz, the
- maximum and minimum delay time is ~2000us and ~500us respectively
-
-- row-delay: How long to wait before scanning each row.
-
-- clocks: The clock this peripheral is attached to.
-
-- linux,keymap: The keymap to use
- (see Documentation/devicetree/bindings/input/matrix-keymap.txt)
-
-Optional properties:
-- active-low: Specify that the keypad is active low (i.e. logical low signifies
- a key press).
-
-Example:
-
-input {
- compatible = "ti,nspire-keypad";
- reg = <0x900E0000 0x1000>;
- interrupts = <16>;
-
- scan-interval = <1000>;
- row-delay = <200>;
-
- clocks = <&apb_pclk>;
-
- linux,keymap = <
- 0x0000001c 0x0001001c 0x00040039
- 0x0005002c 0x00060015 0x0007000b
- 0x0008000f 0x0100002d 0x01010011
- 0x0102002f 0x01030004 0x01040016
- 0x01050014 0x0106001f 0x01070002
- 0x010a006a 0x02000013 0x02010010
- 0x02020019 0x02030007 0x02040018
- 0x02050031 0x02060032 0x02070005
- 0x02080028 0x0209006c 0x03000026
- 0x03010025 0x03020024 0x0303000a
- 0x03040017 0x03050023 0x03060022
- 0x03070008 0x03080035 0x03090069
- 0x04000021 0x04010012 0x04020020
- 0x0404002e 0x04050030 0x0406001e
- 0x0407000d 0x04080037 0x04090067
- 0x05010038 0x0502000c 0x0503001b
- 0x05040034 0x0505001a 0x05060006
- 0x05080027 0x0509000e 0x050a006f
- 0x0600002b 0x0602004e 0x06030068
- 0x06040003 0x0605006d 0x06060009
- 0x06070001 0x0609000f 0x0708002a
- 0x0709001d 0x070a0033 >;
-};
diff --git a/dts/upstream/Bindings/input/ti,nspire-keypad.yaml b/dts/upstream/Bindings/input/ti,nspire-keypad.yaml
new file mode 100644
index 0000000..ed3cfff
--- /dev/null
+++ b/dts/upstream/Bindings/input/ti,nspire-keypad.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/ti,nspire-keypad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-NSPIRE Keypad
+
+maintainers:
+ - Andrew Davis <afd@ti.com>
+
+allOf:
+ - $ref: input.yaml#
+ - $ref: matrix-keymap.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,nspire-keypad
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ scan-interval:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: How often to scan in us. Based on a APB speed of 33MHz, the
+ maximum and minimum delay time is ~2000us and ~500us respectively
+
+ row-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: How long to wait between scanning each row in us.
+
+ active-low:
+ description: Specify that the keypad is active low.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - scan-interval
+ - row-delay
+ - linux,keymap
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/input/input.h>
+ keypad@900e0000 {
+ compatible = "ti,nspire-keypad";
+ reg = <0x900e0000 0x1000>;
+ interrupts = <16>;
+
+ clocks = <&apb_pclk>;
+
+ scan-interval = <1000>;
+ row-delay = <200>;
+
+ linux,keymap = <
+ MATRIX_KEY(0, 0, KEY_ENTER)
+ MATRIX_KEY(0, 1, KEY_ENTER)
+ MATRIX_KEY(0, 4, KEY_SPACE)
+ MATRIX_KEY(0, 5, KEY_Z)
+ MATRIX_KEY(0, 6, KEY_Y)
+ MATRIX_KEY(0, 7, KEY_0)
+ >;
+ };
diff --git a/dts/upstream/Bindings/input/touchscreen/ads7846.txt b/dts/upstream/Bindings/input/touchscreen/ads7846.txt
index 81f6bda..399c877 100644
--- a/dts/upstream/Bindings/input/touchscreen/ads7846.txt
+++ b/dts/upstream/Bindings/input/touchscreen/ads7846.txt
@@ -57,6 +57,7 @@
pendown-gpio (u32).
pendown-gpio GPIO handle describing the pin the !PENIRQ
line is connected to.
+ ti,hsync-gpios GPIO line to poll for hsync
wakeup-source use any event on touchscreen as wakeup event.
(Legacy property support: "linux,wakeup")
touchscreen-size-x General touchscreen binding, see [1].
diff --git a/dts/upstream/Bindings/input/touchscreen/edt-ft5x06.yaml b/dts/upstream/Bindings/input/touchscreen/edt-ft5x06.yaml
index 745e57c..51d48d4 100644
--- a/dts/upstream/Bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/edt-ft5x06.yaml
@@ -39,8 +39,10 @@
- edt,edt-ft5406
- edt,edt-ft5506
- evervision,ev-ft5726
+ - focaltech,ft5426
- focaltech,ft5452
- focaltech,ft6236
+ - focaltech,ft8201
- focaltech,ft8719
reg:
diff --git a/dts/upstream/Bindings/input/touchscreen/eeti,exc3000.yaml b/dts/upstream/Bindings/input/touchscreen/eeti,exc3000.yaml
index 9dc25d3..1c7ae05 100644
--- a/dts/upstream/Bindings/input/touchscreen/eeti,exc3000.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/eeti,exc3000.yaml
@@ -14,10 +14,14 @@
properties:
compatible:
- enum:
- - eeti,exc3000
- - eeti,exc80h60
- - eeti,exc80h84
+ oneOf:
+ - const: eeti,exc3000
+ - const: eeti,exc80h60
+ - const: eeti,exc80h84
+ - items:
+ - enum:
+ - eeti,exc81w32
+ - const: eeti,exc80h84
reg:
const: 0x2a
interrupts:
diff --git a/dts/upstream/Bindings/input/touchscreen/ektf2127.txt b/dts/upstream/Bindings/input/touchscreen/ektf2127.txt
deleted file mode 100644
index c9f2c9f..0000000
--- a/dts/upstream/Bindings/input/touchscreen/ektf2127.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Elan eKTF2127 I2C touchscreen controller
-
-Required properties:
- - compatible : "elan,ektf2127" or "elan,ektf2132"
- - reg : I2C slave address of the chip (0x40)
- - interrupts : interrupt specification for the ektf2127 interrupt
- - power-gpios : GPIO specification for the pin connected to the
- ektf2127's wake input. This needs to be driven high
- to take ektf2127 out of its low power state
-
-For additional optional properties see: touchscreen.txt
-
-Example:
-
-i2c@00000000 {
- ektf2127: touchscreen@15 {
- compatible = "elan,ektf2127";
- reg = <0x15>;
- interrupt-parent = <&pio>;
- interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>
- power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
- touchscreen-inverted-x;
- touchscreen-swapped-x-y;
- };
-};
diff --git a/dts/upstream/Bindings/input/touchscreen/elan,ektf2127.yaml b/dts/upstream/Bindings/input/touchscreen/elan,ektf2127.yaml
new file mode 100644
index 0000000..ff0ec3f
--- /dev/null
+++ b/dts/upstream/Bindings/input/touchscreen/elan,ektf2127.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/elan,ektf2127.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Elan eKTF2127 I2C touchscreen controller
+
+maintainers:
+ - Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - elan,ektf2127
+ - elan,ektf2132
+ - elan,ektf2232
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-gpios:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@15 {
+ compatible = "elan,ektf2127";
+ reg = <0x15>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>;
+ power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml b/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml
index f42b23d..f5cfacb 100644
--- a/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/himax,hx83112b.yaml
@@ -15,6 +15,7 @@
properties:
compatible:
enum:
+ - himax,hx83100a
- himax,hx83112b
reg:
diff --git a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
index 77ba280..e24cbd9 100644
--- a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
@@ -16,6 +16,7 @@
compatible:
enum:
- imagis,ist3032c
+ - imagis,ist3038
- imagis,ist3038b
- imagis,ist3038c
diff --git a/dts/upstream/Bindings/interconnect/mediatek,mt8183-emi.yaml b/dts/upstream/Bindings/interconnect/mediatek,mt8183-emi.yaml
new file mode 100644
index 0000000..017c847
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/mediatek,mt8183-emi.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek External Memory Interface (EMI) Interconnect
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description: |
+ EMI interconnect providers support system bandwidth requirements through
+ Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
+ The provider is able to communicate with the DVFSRC through Secure Monitor
+ Call (SMC).
+
+ ICC provider ICC Nodes
+ ---- ----
+ _________ |CPU | |--- |VPU |
+ _____ | |----- ---- | ----
+ | |->| DRAM | ---- | ----
+ |DRAM |->|scheduler|----- |GPU | |--- |DISP|
+ | |->| (EMI) | ---- | ----
+ |_____|->|_________|---. ----- | ----
+ /|\ `-|MMSYS|--|--- |VDEC|
+ | ----- | ----
+ | | ----
+ | change DRAM freq |--- |VENC|
+ -------- | ----
+ SMC --> | DVFSRC | | ----
+ -------- |--- |IMG |
+ | ----
+ | ----
+ |--- |CAM |
+ ----
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-emi
+ - mediatek,mt8195-emi
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#interconnect-cells'
+
+unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8953.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8953.yaml
new file mode 100644
index 0000000..732e9fa
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,msm8953.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,msm8953.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8953 Network-On-Chip interconnect
+
+maintainers:
+ - Barnabas Czeman <barnabas.czeman@mainlining.org>
+
+description: |
+ The Qualcomm MSM8953 interconnect providers support adjusting the
+ bandwidth requirements between the various NoC fabrics.
+
+ See also:
+ - dt-bindings/interconnect/qcom,msm8953.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8953-bimc
+ - qcom,msm8953-pcnoc
+ - qcom,msm8953-snoc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ '#interconnect-cells':
+ const: 2
+
+patternProperties:
+ '^interconnect-[a-z0-9\-]+$':
+ type: object
+ $ref: qcom,rpm-common.yaml#
+ unevaluatedProperties: false
+ description:
+ The interconnect providers do not have a separate QoS register space,
+ but share parent's space.
+
+ properties:
+ compatible:
+ const: qcom,msm8953-snoc-mm
+
+ required:
+ - compatible
+ - '#interconnect-cells'
+
+required:
+ - compatible
+ - reg
+ - '#interconnect-cells'
+
+allOf:
+ - $ref: qcom,rpm-common.yaml#
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8953-pcnoc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PCNOC USB3 AXI Clock.
+
+ clock-names:
+ const: pcnoc_usb3_axi
+
+ required:
+ - clocks
+ - clock-names
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8953.h>
+
+ snoc: interconnect@580000 {
+ compatible = "qcom,msm8953-snoc";
+ reg = <0x580000 0x16080>;
+
+ #interconnect-cells = <2>;
+
+ snoc_mm: interconnect-snoc {
+ compatible = "qcom,msm8953-snoc-mm";
+
+ #interconnect-cells = <2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
index 05067e1..2cd1f55 100644
--- a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -35,6 +35,7 @@
- qcom,sm8250-cpu-bwmon
- qcom,sm8550-cpu-bwmon
- qcom,sm8650-cpu-bwmon
+ - qcom,x1e80100-cpu-bwmon
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
@@ -44,6 +45,7 @@
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
- qcom,sm8650-llcc-bwmon
+ - qcom,x1e80100-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon # BWMON v5
- const: qcom,sdm845-llcc-bwmon # BWMON v5
@@ -72,7 +74,6 @@
- interconnects
- interrupts
- operating-points-v2
- - opp-table
- reg
additionalProperties: false
diff --git a/dts/upstream/Bindings/interconnect/qcom,sc7280-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sc7280-rpmh.yaml
index b135597..7821079 100644
--- a/dts/upstream/Bindings/interconnect/qcom,sc7280-rpmh.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,sc7280-rpmh.yaml
@@ -8,7 +8,7 @@
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
@@ -35,6 +35,10 @@
reg:
maxItems: 1
+ clocks:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
@@ -53,10 +57,50 @@
required:
- reg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-aggre2-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-aggre1-noc
+ - qcom,sc7280-aggre2-noc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/clock/qcom,gcc-sc7280.h>
interconnect {
compatible = "qcom,sc7280-clk-virt";
#interconnect-cells = <2>;
@@ -68,4 +112,13 @@
compatible = "qcom,sc7280-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ interconnect@16e0000 {
+ reg = <0x016e0000 0x1c080>;
+ compatible = "qcom,sc7280-aggre1-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
diff --git a/dts/upstream/Bindings/interconnect/qcom,sc8280xp-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sc8280xp-rpmh.yaml
index 6c2da03..100c686 100644
--- a/dts/upstream/Bindings/interconnect/qcom,sc8280xp-rpmh.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,sc8280xp-rpmh.yaml
@@ -8,7 +8,7 @@
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
diff --git a/dts/upstream/Bindings/interconnect/qcom,sm8450-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sm8450-rpmh.yaml
index 3cff7e6..300640a 100644
--- a/dts/upstream/Bindings/interconnect/qcom,sm8450-rpmh.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,sm8450-rpmh.yaml
@@ -8,7 +8,7 @@
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml b/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml
index 20ad4ad..aae676b 100644
--- a/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/fsl,irqsteer.yaml
@@ -14,7 +14,10 @@
oneOf:
- const: fsl,imx-irqsteer
- items:
- - const: fsl,imx8m-irqsteer
+ - enum:
+ - fsl,imx8m-irqsteer
+ - fsl,imx8mp-irqsteer
+ - fsl,imx8qxp-irqsteer
- const: fsl,imx-irqsteer
reg:
@@ -42,6 +45,9 @@
clock-names:
const: ipg
+ power-domains:
+ maxItems: 1
+
interrupt-controller: true
"#interrupt-cells":
@@ -70,6 +76,21 @@
- fsl,channel
- fsl,num-irqs
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mp-irqsteer
+ - fsl,imx8qxp-irqsteer
+ then:
+ required:
+ - power-domains
+ else:
+ properties:
+ power-domains: false
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,ls-extirq.yaml b/dts/upstream/Bindings/interrupt-controller/fsl,ls-extirq.yaml
index 887e565..199b34f 100644
--- a/dts/upstream/Bindings/interrupt-controller/fsl,ls-extirq.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/fsl,ls-extirq.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Li Yang <leoyang.li@nxp.com>
description: |
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,ls-msi.yaml b/dts/upstream/Bindings/interrupt-controller/fsl,ls-msi.yaml
new file mode 100644
index 0000000..9ba8d4d
--- /dev/null
+++ b/dts/upstream/Bindings/interrupt-controller/fsl,ls-msi.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Layerscape SCFG PCIe MSI controller
+
+description: |
+ This interrupt controller hardware is a second level interrupt controller that
+ is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+ platforms. If interrupt-parent is not provided, the default parent interrupt
+ controller will be used.
+
+ Each PCIe node needs to have property msi-parent that points to
+ MSI controller node
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1012a-msi
+ - fsl,ls1021a-msi
+ - fsl,ls1043a-msi
+ - fsl,ls1043a-v1.1-msi
+ - fsl,ls1046a-msi
+
+ reg:
+ maxItems: 1
+
+ '#msi-cells':
+ const: 1
+
+ interrupts:
+ items:
+ - description: Shared MSI interrupt group 0
+ - description: Shared MSI interrupt group 1
+ - description: Shared MSI interrupt group 2
+ - description: Shared MSI interrupt group 3
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - msi-controller
+ - interrupts
+
+allOf:
+ - $ref: msi-controller.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,ls1046a-msi
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ interrupt-controller@1571000 {
+ compatible = "fsl,ls1043a-msi";
+ reg = <0x1571000 0x8>;
+ msi-controller;
+ #msi-cells = <1>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/upstream/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/dts/upstream/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
deleted file mode 100644
index 454ce04..0000000
--- a/dts/upstream/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Freescale Layerscape SCFG PCIe MSI controller
-
-Required properties:
-
-- compatible: should be "fsl,<soc-name>-msi" to identify
- Layerscape PCIe MSI controller block such as:
- "fsl,ls1021a-msi"
- "fsl,ls1043a-msi"
- "fsl,ls1046a-msi"
- "fsl,ls1043a-v1.1-msi"
- "fsl,ls1012a-msi"
-- msi-controller: indicates that this is a PCIe MSI controller node
-- reg: physical base address of the controller and length of memory mapped.
-- interrupts: an interrupt to the parent interrupt controller.
-
-This interrupt controller hardware is a second level interrupt controller that
-is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
-platforms. If interrupt-parent is not provided, the default parent interrupt
-controller will be used.
-Each PCIe node needs to have property msi-parent that points to
-MSI controller node
-
-Examples:
-
- msi1: msi-controller@1571000 {
- compatible = "fsl,ls1043a-msi";
- reg = <0x0 0x1571000 0x0 0x8>,
- msi-controller;
- interrupts = <0 116 0x4>;
- };
diff --git a/dts/upstream/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt b/dts/upstream/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
deleted file mode 100644
index 5fc0313..0000000
--- a/dts/upstream/Bindings/interrupt-controller/marvell,armada-370-xp-mpic.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Marvell Armada 370, 375, 38x, XP Interrupt Controller
------------------------------------------------------
-
-Required properties:
-- compatible: Should be "marvell,mpic"
-- interrupt-controller: Identifies the node as an interrupt controller.
-- msi-controller: Identifies the node as an PCI Message Signaled
- Interrupt controller.
-- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
- The cell is the IRQ number
-
-- reg: Should contain PMIC registers location and length. First pair
- for the main interrupt registers, second pair for the per-CPU
- interrupt registers. For this last pair, to be compliant with SMP
- support, the "virtual" must be use (For the record, these registers
- automatically map to the interrupt controller registers of the
- current CPU)
-
-Optional properties:
-
-- interrupts: If defined, then it indicates that this MPIC is
- connected as a slave to another interrupt controller. This is
- typically the case on Armada 375 and Armada 38x, where the MPIC is
- connected as a slave to the Cortex-A9 GIC. The provided interrupt
- indicate to which GIC interrupt the MPIC output is connected.
-
-Example:
-
- mpic: interrupt-controller@d0020000 {
- compatible = "marvell,mpic";
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
- msi-controller;
- reg = <0xd0020a00 0x1d0>,
- <0xd0021070 0x58>;
- };
diff --git a/dts/upstream/Bindings/interrupt-controller/marvell,mpic.yaml b/dts/upstream/Bindings/interrupt-controller/marvell,mpic.yaml
new file mode 100644
index 0000000..616a41c
--- /dev/null
+++ b/dts/upstream/Bindings/interrupt-controller/marvell,mpic.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
+
+maintainers:
+ - Marek Behún <kabel@kernel.org>
+
+description: |
+ The top-level interrupt controller on Marvell Armada 370 and XP. On these
+ platforms it also provides inter-processor interrupts.
+
+ On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
+
+ Provides MSI handling for the PCIe controllers.
+
+properties:
+ compatible:
+ const: marvell,mpic
+
+ reg:
+ items:
+ - description: main registers
+ - description: per-cpu registers
+
+ interrupts:
+ items:
+ - description: |
+ Parent interrupt on platforms where MPIC is not the top-level
+ interrupt controller.
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+ msi-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - msi-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ interrupt-controller@20a00 {
+ compatible = "marvell,mpic";
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ msi-controller;
+ };
diff --git a/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
new file mode 100644
index 0000000..b2adc71
--- /dev/null
+++ b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966x outband interrupt controller
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ The Microchip LAN966x outband interrupt controller (OIC) maps the internal
+ interrupt sources of the LAN966x device to an external interrupt.
+ When the LAN966x device is used as a PCI device, the external interrupt is
+ routed to the PCI interrupt.
+
+properties:
+ compatible:
+ const: microchip,lan966x-oic
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - interrupts
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@e00c0120 {
+ compatible = "microchip,lan966x-oic";
+ reg = <0xe00c0120 0x190>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <0>;
+ interrupt-parent = <&intc>;
+ };
+...
diff --git a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
index 4bdc832..985fa10 100644
--- a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -30,6 +30,7 @@
- qcom,sa8775p-pdc
- qcom,sc7180-pdc
- qcom,sc7280-pdc
+ - qcom,sc8180x-pdc
- qcom,sc8280xp-pdc
- qcom,sdm670-pdc
- qcom,sdm845-pdc
diff --git a/dts/upstream/Bindings/interrupt-controller/realtek,rtl-intc.yaml b/dts/upstream/Bindings/interrupt-controller/realtek,rtl-intc.yaml
index fb55937..833a01c 100644
--- a/dts/upstream/Bindings/interrupt-controller/realtek,rtl-intc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/realtek,rtl-intc.yaml
@@ -25,6 +25,7 @@
- items:
- enum:
- realtek,rtl8380-intc
+ - realtek,rtl9300-intc
- const: realtek,rtl-intc
- const: realtek,rtl-intc
deprecated: true
@@ -35,7 +36,10 @@
const: 1
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: vpe0 registers
+ - description: vpe1 registers
interrupts:
minItems: 1
@@ -71,6 +75,20 @@
else:
required:
- interrupts
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: realtek,rtl9300-intc
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
additionalProperties: false
diff --git a/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index daef4ee..44b6ae5 100644
--- a/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -21,13 +21,16 @@
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g043u-irqc # RZ/G2UL
- - renesas,r9a07g044-irqc # RZ/G2{L,LC}
- - renesas,r9a07g054-irqc # RZ/V2L
- - renesas,r9a08g045-irqc # RZ/G3S
- - const: renesas,rzg2l-irqc
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g043u-irqc # RZ/G2UL
+ - renesas,r9a07g044-irqc # RZ/G2{L,LC}
+ - renesas,r9a07g054-irqc # RZ/V2L
+ - renesas,r9a08g045-irqc # RZ/G3S
+ - const: renesas,rzg2l-irqc
+
+ - const: renesas,r9a07g043f-irqc # RZ/Five
'#interrupt-cells':
description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
diff --git a/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.txt b/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.txt
deleted file mode 100644
index 265b223..0000000
--- a/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-RISC-V Hart-Level Interrupt Controller (HLIC)
----------------------------------------------
-
-RISC-V cores include Control Status Registers (CSRs) which are local to each
-CPU core (HART in RISC-V terminology) and can be read or written by software.
-Some of these CSRs are used to control local interrupts connected to the core.
-Every interrupt is ultimately routed through a hart's HLIC before it
-interrupts that hart.
-
-The RISC-V supervisor ISA manual specifies three interrupt sources that are
-attached to every HLIC: software interrupts, the timer interrupt, and external
-interrupts. Software interrupts are used to send IPIs between cores. The
-timer interrupt comes from an architecturally mandated real-time timer that is
-controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
-interrupts connect all other device interrupts to the HLIC, which are routed
-via the platform-level interrupt controller (PLIC).
-
-All RISC-V systems that conform to the supervisor ISA specification are
-required to have a HLIC with these three interrupt sources present. Since the
-interrupt map is defined by the ISA it's not listed in the HLIC's device tree
-entry, though external interrupt controllers (like the PLIC, for example) will
-need to define how their interrupts map to the relevant HLICs. This means
-a PLIC interrupt property will typically list the HLICs for all present HARTs
-in the system.
-
-Required properties:
-- compatible : "riscv,cpu-intc"
-- #interrupt-cells : should be <1>. The interrupt sources are defined by the
- RISC-V supervisor ISA manual, with only the following three interrupts being
- defined for supervisor mode:
- - Source 1 is the supervisor software interrupt, which can be sent by an SBI
- call and is reserved for use by software.
- - Source 5 is the supervisor timer interrupt, which can be configured by
- SBI calls and implements a one-shot timer.
- - Source 9 is the supervisor external interrupt, which chains to all other
- device interrupts.
-- interrupt-controller : Identifies the node as an interrupt controller
-
-Furthermore, this interrupt-controller MUST be embedded inside the cpu
-definition of the hart whose CSRs control these local interrupts.
-
-An example device tree entry for a HLIC is show below.
-
- cpu1: cpu@1 {
- compatible = "riscv";
- ...
- cpu1-intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
- interrupt-controller;
- };
- };
diff --git a/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.yaml b/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.yaml
new file mode 100644
index 0000000..83256cc
--- /dev/null
+++ b/dts/upstream/Bindings/interrupt-controller/riscv,cpu-intc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Hart-Level Interrupt Controller (HLIC)
+
+description:
+ RISC-V cores include Control Status Registers (CSRs) which are local to
+ each CPU core (HART in RISC-V terminology) and can be read or written by
+ software. Some of these CSRs are used to control local interrupts connected
+ to the core. Every interrupt is ultimately routed through a hart's HLIC
+ before it interrupts that hart.
+
+ The RISC-V supervisor ISA manual specifies three interrupt sources that are
+ attached to every HLIC namely software interrupts, the timer interrupt, and
+ external interrupts. Software interrupts are used to send IPIs between
+ cores. The timer interrupt comes from an architecturally mandated real-
+ time timer that is controlled via Supervisor Binary Interface (SBI) calls
+ and CSR reads. External interrupts connect all other device interrupts to
+ the HLIC, which are routed via the platform-level interrupt controller
+ (PLIC).
+
+ All RISC-V systems that conform to the supervisor ISA specification are
+ required to have a HLIC with these three interrupt sources present. Since
+ the interrupt map is defined by the ISA it's not listed in the HLIC's device
+ tree entry, though external interrupt controllers (like the PLIC, for
+ example) will need to define how their interrupts map to the relevant HLICs.
+ This means a PLIC interrupt property will typically list the HLICs for all
+ present HARTs in the system.
+
+maintainers:
+ - Palmer Dabbelt <palmer@dabbelt.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+ description: |
+ The interrupt sources are defined by the RISC-V supervisor ISA manual,
+ with only the following three interrupts being defined for
+ supervisor mode:
+ - Source 1 is the supervisor software interrupt, which can be sent by
+ an SBI call and is reserved for use by software.
+ - Source 5 is the supervisor timer interrupt, which can be configured
+ by SBI calls and implements a one-shot timer.
+ - Source 9 is the supervisor external interrupt, which chains to all
+ other device interrupts.
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
diff --git a/dts/upstream/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/dts/upstream/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml
index e20016f..a8409db 100644
--- a/dts/upstream/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml
+++ b/dts/upstream/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml
@@ -17,7 +17,12 @@
The content of the cell is the master ID.
compatible:
- const: allwinner,sun50i-h6-iommu
+ oneOf:
+ - const: allwinner,sun50i-h6-iommu
+ - const: allwinner,sun50i-h616-iommu
+ - items:
+ - const: allwinner,sun55i-a523-iommu
+ - const: allwinner,sun50i-h616-iommu
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iommu/arm,smmu.yaml b/dts/upstream/Bindings/iommu/arm,smmu.yaml
index 5c130cf..280b4e4 100644
--- a/dts/upstream/Bindings/iommu/arm,smmu.yaml
+++ b/dts/upstream/Bindings/iommu/arm,smmu.yaml
@@ -86,6 +86,7 @@
- qcom,qcm2290-smmu-500
- qcom,sa8775p-smmu-500
- qcom,sc7280-smmu-500
+ - qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
@@ -95,6 +96,7 @@
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
- qcom,sm8650-smmu-500
+ - qcom,x1e80100-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -415,6 +417,7 @@
compatible:
contains:
enum:
+ - qcom,sc8180x-smmu-500
- qcom,sm6350-smmu-v2
- qcom,sm7150-smmu-v2
- qcom,sm8150-smmu-500
@@ -520,6 +523,7 @@
- enum:
- qcom,sm8550-smmu-500
- qcom,sm8650-smmu-500
+ - qcom,x1e80100-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -550,14 +554,12 @@
- nvidia,smmu-500
- qcom,qdu1000-smmu-500
- qcom,sc7180-smmu-500
- - qcom,sc8180x-smmu-500
- qcom,sdm670-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- - qcom,x1e80100-smmu-500
then:
properties:
clock-names: false
diff --git a/dts/upstream/Bindings/iommu/msm,iommu-v0.txt b/dts/upstream/Bindings/iommu/msm,iommu-v0.txt
deleted file mode 100644
index 2023638..0000000
--- a/dts/upstream/Bindings/iommu/msm,iommu-v0.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-* QCOM IOMMU
-
-The MSM IOMMU is an implementation compatible with the ARM VMSA short
-descriptor page tables. It provides address translation for bus masters outside
-of the CPU, each connected to the IOMMU through a port called micro-TLB.
-
-Required Properties:
-
- - compatible: Must contain "qcom,apq8064-iommu".
- - reg: Base address and size of the IOMMU registers.
- - interrupts: Specifiers for the MMU fault interrupts. For instances that
- support secure mode two interrupts must be specified, for non-secure and
- secure mode, in that order. For instances that don't support secure mode a
- single interrupt must be specified.
- - #iommu-cells: The number of cells needed to specify the stream id. This
- is always 1.
- - qcom,ncb: The total number of context banks in the IOMMU.
- - clocks : List of clocks to be used during SMMU register access. See
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- for information about the format. For each clock specified
- here, there must be a corresponding entry in clock-names
- (see below).
-
- - clock-names : List of clock names corresponding to the clocks specified in
- the "clocks" property (above).
- Should be "smmu_pclk" for specifying the interface clock
- required for iommu's register accesses.
- Should be "smmu_clk" for specifying the functional clock
- required by iommu for bus accesses.
-
-Each bus master connected to an IOMMU must reference the IOMMU in its device
-node with the following property:
-
- - iommus: A reference to the IOMMU in multiple cells. The first cell is a
- phandle to the IOMMU and the second cell is the stream id.
- A single master device can be connected to more than one iommu
- and multiple contexts in each of the iommu. So multiple entries
- are required to list all the iommus and the stream ids that the
- master is connected to.
-
-Example: mdp iommu and its bus master
-
- mdp_port0: iommu@7500000 {
- compatible = "qcom,apq8064-iommu";
- #iommu-cells = <1>;
- clock-names =
- "smmu_pclk",
- "smmu_clk";
- clocks =
- <&mmcc SMMU_AHB_CLK>,
- <&mmcc MDP_AXI_CLK>;
- reg = <0x07500000 0x100000>;
- interrupts =
- <GIC_SPI 63 0>,
- <GIC_SPI 64 0>;
- qcom,ncb = <2>;
- };
-
- mdp: qcom,mdp@5100000 {
- compatible = "qcom,mdp";
- ...
- iommus = <&mdp_port0 0
- &mdp_port0 2>;
- };
diff --git a/dts/upstream/Bindings/iommu/qcom,apq8064-iommu.yaml b/dts/upstream/Bindings/iommu/qcom,apq8064-iommu.yaml
new file mode 100644
index 0000000..9f83f85
--- /dev/null
+++ b/dts/upstream/Bindings/iommu/qcom,apq8064-iommu.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APQ8064 IOMMU
+
+maintainers:
+ - David Heidelberg <david@ixit.cz>
+
+description:
+ The MSM IOMMU is an implementation compatible with the ARM VMSA short
+ descriptor page tables. It provides address translation for bus masters
+ outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
+
+properties:
+ compatible:
+ const: qcom,apq8064-iommu
+
+ clocks:
+ items:
+ - description: interface clock for register accesses
+ - description: functional clock for bus accesses
+
+ clock-names:
+ items:
+ - const: smmu_pclk
+ - const: iommu_clk
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Specifiers for the MMU fault interrupts.
+ minItems: 1
+ items:
+ - description: non-secure mode interrupt
+ - description: secure mode interrupt (for instances which supports it)
+
+ "#iommu-cells":
+ const: 1
+ description: Each IOMMU specifier describes a single Stream ID.
+
+ qcom,ncb:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The total number of context banks in the IOMMU.
+ minimum: 1
+ maximum: 4
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - qcom,ncb
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ iommu@7500000 {
+ compatible = "qcom,apq8064-iommu";
+ reg = <0x07500000 0x100000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk SMMU_AHB_CLK>,
+ <&clk MDP_AXI_CLK>;
+ clock-names = "smmu_pclk",
+ "iommu_clk";
+ #iommu-cells = <1>;
+ qcom,ncb = <2>;
+ };
diff --git a/dts/upstream/Bindings/iommu/qcom,iommu.yaml b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
index a74eb89..f8cebc9 100644
--- a/dts/upstream/Bindings/iommu/qcom,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Technologies legacy IOMMU implementations
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
Qualcomm "B" family devices which are not compatible with arm-smmu have
@@ -25,6 +25,7 @@
- const: qcom,msm-iommu-v1
- items:
- enum:
+ - qcom,msm8953-iommu
- qcom,msm8976-iommu
- const: qcom,msm-iommu-v2
diff --git a/dts/upstream/Bindings/leds/backlight/ti,lm3509.yaml b/dts/upstream/Bindings/leds/backlight/ti,lm3509.yaml
new file mode 100644
index 0000000..482fae7
--- /dev/null
+++ b/dts/upstream/Bindings/leds/backlight/ti,lm3509.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/ti,lm3509.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI LM3509 High Efficiency Boost for White LED's and/or OLED Displays
+
+maintainers:
+ - Patrick Gansterer <paroga@paroga.com>
+
+description:
+ The LM3509 current mode boost converter offers two separate outputs.
+ https://www.ti.com/product/LM3509
+
+properties:
+ compatible:
+ const: ti,lm3509
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reset-gpios:
+ maxItems: 1
+
+ ti,brightness-rate-of-change-us:
+ description: Brightness Rate of Change in microseconds.
+ enum: [51, 13000, 26000, 52000]
+
+ ti,oled-mode:
+ description: Enable OLED mode.
+ type: boolean
+
+patternProperties:
+ "^led@[01]$":
+ type: object
+ description: Properties for a string of connected LEDs.
+ $ref: common.yaml#
+
+ properties:
+ reg:
+ description:
+ The control register that is used to program the two current sinks.
+ The LM3509 has two registers (BMAIN and BSUB) and are represented
+ as 0 or 1 in this property. The two current sinks can be controlled
+ independently with both registers, or register BMAIN can be
+ configured to control both sinks with the led-sources property.
+ minimum: 0
+ maximum: 1
+
+ label: true
+
+ led-sources:
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
+ default-brightness:
+ minimum: 0
+ maximum: 31
+ default: 18
+
+ max-brightness:
+ minimum: 0
+ maximum: 31
+ default: 31
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight@36 {
+ compatible = "ti,lm3509";
+ reg = <0x36>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+
+ ti,oled-mode;
+ ti,brightness-rate-of-change-us = <52000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0 1>;
+ label = "lcd-backlight";
+ default-brightness = <12>;
+ max-brightness = <31>;
+ };
+ };
+ };
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight@36 {
+ compatible = "ti,lm3509";
+ reg = <0x36>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ default-brightness = <12>;
+ };
+
+ led@1 {
+ reg = <1>;
+ default-brightness = <15>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/leds/leds-lp55xx.yaml b/dts/upstream/Bindings/leds/leds-lp55xx.yaml
index e9d4514..fe8aaec 100644
--- a/dts/upstream/Bindings/leds/leds-lp55xx.yaml
+++ b/dts/upstream/Bindings/leds/leds-lp55xx.yaml
@@ -28,6 +28,7 @@
- national,lp5523
- ti,lp55231
- ti,lp5562
+ - ti,lp5569
- ti,lp8501
reg:
@@ -151,6 +152,16 @@
$ref: /schemas/types.yaml#/definitions/string
description: name of channel
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ti,lp8501
+then:
+ properties:
+ pwr-sel: false
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/leds/silergy,sy7802.yaml b/dts/upstream/Bindings/leds/silergy,sy7802.yaml
new file mode 100644
index 0000000..46b8e54
--- /dev/null
+++ b/dts/upstream/Bindings/leds/silergy,sy7802.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/silergy,sy7802.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silergy SY7802 1800mA Boost Charge Pump LED Driver
+
+maintainers:
+ - André Apitzsch <git@apitzsch.eu>
+
+description: |
+ The SY7802 is a current-regulated charge pump which can regulate two current
+ levels for Flash and Torch modes.
+
+ The SY7802 is a high-current synchronous boost converter with 2-channel
+ high side current sources. Each channel is able to deliver 900mA current.
+
+properties:
+ compatible:
+ enum:
+ - silergy,sy7802
+
+ reg:
+ maxItems: 1
+
+ enable-gpios:
+ maxItems: 1
+ description: A connection to the 'EN' pin.
+
+ flash-gpios:
+ maxItems: 1
+ description: A connection to the 'FLEN' pin.
+
+ vin-supply:
+ description: Regulator providing power to the 'VIN' pin.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^led@[0-1]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: Index of the LED.
+ minimum: 0
+ maximum: 1
+
+ led-sources:
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
+
+ required:
+ - reg
+ - led-sources
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - enable-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash-led-controller@53 {
+ compatible = "silergy,sy7802";
+ reg = <0x53>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <0>, <1>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/mailbox/mediatek,gce-props.yaml b/dts/upstream/Bindings/mailbox/mediatek,gce-props.yaml
new file mode 100644
index 0000000..c25eed46
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/mediatek,gce-props.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Global Command Engine Common Properties
+
+maintainers:
+ - Houlong Wei <houlong.wei@mediatek.com>
+
+description:
+ The Global Command Engine (GCE) is an instruction based, multi-threaded,
+ single-core command dispatcher for MediaTek hardware. The Command Queue
+ (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
+ mailbox framework. It is used to receive messages from mailbox consumers
+ and configure GCE to execute the specified instruction set in the message.
+ We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
+ driver. A device driver that uses the CMDQ driver to configure its hardware
+ registers is a mailbox consumer. The mailbox consumer can request a mailbox
+ channel corresponding to a GCE hardware thread to send a message, specifying
+ that the GCE thread to configure its hardware. The mailbox provider can also
+ reserve a mailbox channel to configure GCE hardware register by the specific
+ GCE thread. This binding defines the common GCE properties for both mailbox
+ provider and consumers.
+
+properties:
+ mediatek,gce-events:
+ description:
+ GCE has an event table in SRAM, consisting of 1024 event IDs (0~1023).
+ Each event ID has a boolean event value with the default value 0.
+ The property mediatek,gce-events is used to obtain the event IDs.
+ Some gce-events are hardware-bound and cannot be changed by software.
+ For instance, in MT8195, when VDO0_MUTEX is stream done, VDO_MUTEX will
+ send an event signal to GCE, setting the value of event ID 597 to 1.
+ Similarly, in MT8188, the value of event ID 574 will be set to 1 when
+ VOD0_MUTEX is stream done.
+ On the other hand, some gce-events are not hardware-bound and can be
+ changed by software. For example, in MT8188, we can set the value of
+ event ID 855, which is not bound to any hardware, to 1 when the driver
+ in the secure world completes a task. However, in MT8195, event ID 855
+ is already bound to VDEC_LAT1, so we need to select another event ID to
+ achieve the same purpose. This event ID can be any ID that is not bound
+ to any hardware and is not yet used in any software driver.
+ To determine if the event ID is bound to the hardware or used by a
+ software driver, refer to the GCE header
+ include/dt-bindings/gce/<chip>-gce.h of each chip.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 32
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/mailbox/qcom,cpucp-mbox.yaml b/dts/upstream/Bindings/mailbox/qcom,cpucp-mbox.yaml
new file mode 100644
index 0000000..f7342d04
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/qcom,cpucp-mbox.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
+
+maintainers:
+ - Sibi Sankar <quic_sibis@quicinc.com>
+
+description:
+ The CPUSS Control Processor (CPUCP) mailbox controller enables communication
+ between AP and CPUCP by acting as a doorbell between them.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,x1e80100-cpucp-mbox
+
+ reg:
+ items:
+ - description: CPUCP rx register region
+ - description: CPUCP tx register region
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mailbox@17430000 {
+ compatible = "qcom,x1e80100-cpucp-mbox";
+ reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/media/i2c/galaxycore,gc05a2.yaml b/dts/upstream/Bindings/media/i2c/galaxycore,gc05a2.yaml
new file mode 100644
index 0000000..0e7a7b5
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/galaxycore,gc05a2.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc05a2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GalaxyCore gc05a2 1/5" 5M Pixel MIPI CSI-2 sensor
+
+maintainers:
+ - Zhi Mao <zhi.mao@mediatek.com>
+
+description:
+ The gc05a2 is a raw image sensor with an MIPI CSI-2 image data
+ interface and CCI (I2C compatible) control bus. The output format
+ is raw Bayer.
+
+properties:
+ compatible:
+ const: galaxycore,gc05a2
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ dovdd-supply: true
+
+ avdd-supply: true
+
+ dvdd-supply: true
+
+ reset-gpios:
+ description: Reference to the GPIO connected to the RESETB pin.
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+ description:
+ Output port node, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+ - items:
+ - const: 1
+ - const: 2
+
+ link-frequencies: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - dovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@37 {
+ compatible = "galaxycore,gc05a2";
+ reg = <0x37>;
+
+ clocks = <&gc05a2_clk>;
+
+ reset-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&gc05a2_avdd>;
+ dovdd-supply = <&gc05a2_dovdd>;
+ dvdd-supply = <&gc05a2_dvdd>;
+
+ port {
+ sensor_out: endpoint {
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <448000000 224000000>;
+ remote-endpoint = <&seninf_csi_port_1_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/galaxycore,gc08a3.yaml b/dts/upstream/Bindings/media/i2c/galaxycore,gc08a3.yaml
new file mode 100644
index 0000000..51b8ece
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/galaxycore,gc08a3.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc08a3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GalaxyCore gc08a3 1/4" 8M Pixel MIPI CSI-2 sensor
+
+maintainers:
+ - Zhi Mao <zhi.mao@mediatek.com>
+
+description:
+ The gc08a3 is a raw image sensor with an MIPI CSI-2 image data
+ interface and CCI (I2C compatible) control bus. The output format
+ is raw Bayer.
+
+properties:
+ compatible:
+ const: galaxycore,gc08a3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ dovdd-supply: true
+
+ avdd-supply: true
+
+ dvdd-supply: true
+
+ reset-gpios:
+ description: Reference to the GPIO connected to the RESETB pin.
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+ description:
+ Output port node, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+ - items:
+ - const: 1
+ - const: 2
+
+ link-frequencies: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - dovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@31 {
+ compatible = "galaxycore,gc08a3";
+ reg = <0x31>;
+
+ clocks = <&gc08a3_clk>;
+
+ reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&gc08a3_avdd>;
+ dovdd-supply = <&gc08a3_dovdd>;
+ dvdd-supply = <&gc08a3_dvdd>;
+
+ port {
+ sensor_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <336000000 207000000>;
+ remote-endpoint = <&seninf_csi_port_0_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/imx258.yaml b/dts/upstream/Bindings/media/i2c/imx258.yaml
deleted file mode 100644
index 80d2422..0000000
--- a/dts/upstream/Bindings/media/i2c/imx258.yaml
+++ /dev/null
@@ -1,134 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/media/i2c/imx258.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Sony IMX258 13 Mpixel CMOS Digital Image Sensor
-
-maintainers:
- - Krzysztof Kozlowski <krzk@kernel.org>
-
-description: |-
- IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
- type stacked image sensor with a square pixel array of size 4208 x 3120. It
- is programmable through I2C interface. Image data is sent through MIPI
- CSI-2.
-
-properties:
- compatible:
- const: sony,imx258
-
- assigned-clocks: true
- assigned-clock-parents: true
- assigned-clock-rates: true
-
- clocks:
- description:
- Clock frequency from 6 to 27 MHz.
- maxItems: 1
-
- reg:
- maxItems: 1
-
- reset-gpios:
- description: |-
- Reference to the GPIO connected to the XCLR pin, if any.
-
- vana-supply:
- description:
- Analog voltage (VANA) supply, 2.7 V
-
- vdig-supply:
- description:
- Digital I/O voltage (VDIG) supply, 1.2 V
-
- vif-supply:
- description:
- Interface voltage (VIF) supply, 1.8 V
-
- # See ../video-interfaces.txt for more details
- port:
- $ref: /schemas/graph.yaml#/$defs/port-base
- additionalProperties: false
-
- properties:
- endpoint:
- $ref: /schemas/media/video-interfaces.yaml#
- unevaluatedProperties: false
-
- properties:
- data-lanes:
- oneOf:
- - items:
- - const: 1
- - const: 2
- - const: 3
- - const: 4
- - items:
- - const: 1
- - const: 2
-
- link-frequencies: true
-
- required:
- - data-lanes
- - link-frequencies
-
-required:
- - compatible
- - reg
- - port
-
-additionalProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sensor@6c {
- compatible = "sony,imx258";
- reg = <0x6c>;
- clocks = <&imx258_clk>;
-
- port {
- endpoint {
- remote-endpoint = <&csi1_ep>;
- data-lanes = <1 2 3 4>;
- link-frequencies = /bits/ 64 <320000000>;
- };
- };
- };
- };
-
- /* Oscillator on the camera board */
- imx258_clk: clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- };
-
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- sensor@6c {
- compatible = "sony,imx258";
- reg = <0x6c>;
- clocks = <&imx258_clk>;
-
- assigned-clocks = <&imx258_clk>;
- assigned-clock-rates = <19200000>;
-
- port {
- endpoint {
- remote-endpoint = <&csi1_ep>;
- data-lanes = <1 2 3 4>;
- link-frequencies = /bits/ 64 <633600000>;
- };
- };
- };
- };
diff --git a/dts/upstream/Bindings/media/i2c/maxim,max96714.yaml b/dts/upstream/Bindings/media/i2c/maxim,max96714.yaml
new file mode 100644
index 0000000..3ace50e
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/maxim,max96714.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Collabora Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/maxim,max96714.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
+
+maintainers:
+ - Julien Massot <julien.massot@collabora.com>
+
+description:
+ The MAX96714 deserializer converts GMSL2 serial inputs into MIPI
+ CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
+ simultaneously transmit bidirectional control-channel data while forward
+ video transmissions are in progress. The MAX96714 can connect to one
+ remotely located serializer using industry-standard coax or STP
+ interconnects. The device cans operate in pixel or tunnel mode. In pixel mode
+ the MAX96714 can select individual video stream, while the tunnel mode forward all
+ the MIPI data received by the serializer.
+
+ The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
+ forward direction and 187.5Mbps in the reverse direction.
+ MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
+
+properties:
+ compatible:
+ oneOf:
+ - const: maxim,max96714f
+ - items:
+ - enum:
+ - maxim,max96714
+ - const: maxim,max96714f
+
+ reg:
+ maxItems: 1
+
+ powerdown-gpios:
+ maxItems: 1
+ description:
+ Specifier for the GPIO connected to the PWDNB pin.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+ description: GMSL Input
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ description:
+ Endpoint for GMSL2-Link port.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI-2 Output port
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 5
+
+ link-frequencies:
+ maxItems: 1
+
+ required:
+ - data-lanes
+
+ required:
+ - port@1
+
+ i2c-gate:
+ $ref: /schemas/i2c/i2c-gate.yaml
+ unevaluatedProperties: false
+ description:
+ The MAX96714 will pass through and forward the I2C requests from the
+ incoming I2C bus over the GMSL2 link. Therefore it supports an i2c-gate
+ subnode to configure a serializer.
+
+ port0-poc-supply:
+ description: Regulator providing Power over Coax for the GMSL port
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/media/video-interfaces.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ deserializer@28 {
+ compatible = "maxim,max96714f";
+ reg = <0x28>;
+ powerdown-gpios = <&main_gpio0 37 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ max96714_gmsl_in: endpoint {
+ remote-endpoint = <&max96917f_gmsl_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ max96714_csi_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <400000000>;
+ remote-endpoint = <&csi_in>;
+ };
+ };
+ };
+
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ serializer@40 {
+ compatible = "maxim,max96717f";
+ reg = <0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ max96717f_csi_in: endpoint {
+ data-lanes = <1 2>;
+ lane-polarities = <1 0 1>;
+ remote-endpoint = <&sensor_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ max96917f_gmsl_out: endpoint {
+ remote-endpoint = <&max96714_gmsl_in>;
+ };
+ };
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/media/i2c/maxim,max96717.yaml b/dts/upstream/Bindings/media/i2c/maxim,max96717.yaml
new file mode 100644
index 0000000..d1e8ba6
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/maxim,max96717.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Collabora Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/maxim,max96717.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MAX96717 CSI-2 to GMSL2 Serializer
+
+maintainers:
+ - Julien Massot <julien.massot@collabora.com>
+
+description:
+ The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
+ into GMSL2 serial outputs. The device allows the GMSL2 link to
+ simultaneously transmit bidirectional control-channel data while forward
+ video transmissions are in progress. The MAX96717 can connect to one
+ remotely located deserializer using industry-standard coax or STP
+ interconnects. The device cans operate in pixel or tunnel mode. In pixel mode
+ the MAX96717 can select the MIPI datatype, while the tunnel mode forward all the MIPI
+ data received by the serializer.
+ The MAX96717 supports Reference Over Reverse (channel),
+ to generate a clock output for the sensor from the GMSL reverse channel.
+
+ The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
+ forward direction and 187.5Mbps in the reverse direction.
+ MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
+
+properties:
+ compatible:
+ oneOf:
+ - const: maxim,max96717f
+ - items:
+ - enum:
+ - maxim,max96717
+ - const: maxim,max96717f
+
+ '#gpio-cells':
+ const: 2
+ description:
+ First cell is the GPIO pin number, second cell is the flags. The GPIO pin
+ number must be in range of [0, 10].
+
+ gpio-controller: true
+
+ '#clock-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI-2 Input port
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 5
+
+ required:
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ unevaluatedProperties: false
+ description: GMSL Output port
+
+ required:
+ - port@1
+
+ i2c-gate:
+ $ref: /schemas/i2c/i2c-gate.yaml
+ unevaluatedProperties: false
+ description:
+ The MAX96717 will forward the I2C requests from the
+ incoming GMSL2 link. Therefore, it supports an i2c-gate
+ subnode to configure a sensor.
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/media/video-interfaces.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ serializer: serializer@40 {
+ compatible = "maxim,max96717f";
+ reg = <0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ max96717f_csi_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&sensor_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ max96917f_gmsl_out: endpoint {
+ remote-endpoint = <&deser_gmsl_in>;
+ };
+ };
+ };
+
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sensor@10 {
+ compatible = "st,st-vgxy61";
+ reg = <0x10>;
+ reset-gpios = <&serializer 0 GPIO_ACTIVE_LOW>;
+ clocks = <&serializer>;
+ VCORE-supply = <&v1v2>;
+ VDDIO-supply = <&v1v8>;
+ VANA-supply = <&v2v8>;
+ port {
+ sensor_out: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&max96717f_csi_in>;
+ };
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/media/i2c/sony,imx258.yaml b/dts/upstream/Bindings/media/i2c/sony,imx258.yaml
new file mode 100644
index 0000000..c978abc
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/sony,imx258.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/sony,imx258.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony IMX258 13 Mpixel CMOS Digital Image Sensor
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |-
+ IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
+ type stacked image sensor with a square pixel array of size 4208 x 3120. It
+ is programmable through I2C interface. Image data is sent through MIPI
+ CSI-2. The sensor exists in two different models, a standard variant
+ (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
+ The camera module does not expose the model through registers, so the
+ exact model needs to be specified.
+
+properties:
+ compatible:
+ enum:
+ - sony,imx258
+ - sony,imx258-pdaf
+
+ assigned-clocks: true
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+
+ clocks:
+ description:
+ Clock frequency from 6 to 27 MHz.
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ description: |-
+ Reference to the GPIO connected to the XCLR pin, if any.
+
+ vana-supply:
+ description:
+ Analog voltage (VANA) supply, 2.7 V
+
+ vdig-supply:
+ description:
+ Digital I/O voltage (VDIG) supply, 1.2 V
+
+ vif-supply:
+ description:
+ Interface voltage (VIF) supply, 1.8 V
+
+ # See ../video-interfaces.txt for more details
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ oneOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+ - items:
+ - const: 1
+ - const: 2
+
+ link-frequencies: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@6c {
+ compatible = "sony,imx258";
+ reg = <0x6c>;
+ clocks = <&imx258_clk>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&csi1_ep>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <320000000>;
+ };
+ };
+ };
+ };
+
+ /* Oscillator on the camera board */
+ imx258_clk: clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@6c {
+ compatible = "sony,imx258";
+ reg = <0x6c>;
+ clocks = <&imx258_clk>;
+
+ assigned-clocks = <&imx258_clk>;
+ assigned-clock-rates = <19200000>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&csi1_ep>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <633600000>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/media/i2c/sony,imx283.yaml b/dts/upstream/Bindings/media/i2c/sony,imx283.yaml
new file mode 100644
index 0000000..e4f49f1
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/sony,imx283.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Ideas on Board Oy
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/sony,imx283.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony IMX283 Sensor
+
+maintainers:
+ - Kieran Bingham <kieran.bingham@ideasonboard.com>
+ - Umang Jain <umang.jain@ideasonboard.com>
+
+description:
+ IMX283 sensor is a Sony CMOS active pixel digital image sensor with an active
+ array size of 5472H x 3648V. It is programmable through I2C interface. The
+ I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
+ sent through MIPI CSI-2.
+
+properties:
+ compatible:
+ const: sony,imx283
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: Clock frequency from 6 to 24 MHz.
+ maxItems: 1
+
+ vadd-supply:
+ description: Analog power supply (2.9V)
+
+ vdd1-supply:
+ description: Interface power supply (1.8V)
+
+ vdd2-supply:
+ description: Digital power supply (1.2V)
+
+ reset-gpios:
+ description: Sensor reset (XCLR) GPIO
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ anyOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ link-frequencies: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@1a {
+ compatible = "sony,imx283";
+ reg = <0x1a>;
+ clocks = <&imx283_clk>;
+
+ assigned-clocks = <&imx283_clk>;
+ assigned-clock-parents = <&imx283_clk_parent>;
+ assigned-clock-rates = <12000000>;
+
+ vadd-supply = <&camera_vadd_2v9>;
+ vdd1-supply = <&camera_vdd1_1v8>;
+ vdd2-supply = <&camera_vdd2_1v2>;
+
+ port {
+ imx283: endpoint {
+ remote-endpoint = <&cam>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <360000000>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/media/img,e5010-jpeg-enc.yaml b/dts/upstream/Bindings/media/img,e5010-jpeg-enc.yaml
new file mode 100644
index 0000000..085020c
--- /dev/null
+++ b/dts/upstream/Bindings/media/img,e5010-jpeg-enc.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/img,e5010-jpeg-enc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination E5010 JPEG Encoder
+
+maintainers:
+ - Devarsh Thakkar <devarsht@ti.com>
+
+description: |
+ The E5010 is a JPEG encoder from Imagination Technologies implemented on
+ TI's AM62A SoC. It is capable of real time encoding of YUV420 and YUV422
+ inputs to JPEG and M-JPEG. It supports baseline JPEG Encoding up to
+ 8Kx8K resolution.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: ti,am62a-jpeg-enc
+ - const: img,e5010-jpeg-enc
+ - const: img,e5010-jpeg-enc
+
+ reg:
+ items:
+ - description: The E5010 core register region
+ - description: The E5010 mmu register region
+
+ reg-names:
+ items:
+ - const: core
+ - const: mmu
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ jpeg-encoder@fd20000 {
+ compatible = "img,e5010-jpeg-enc";
+ reg = <0x00 0xfd20000 0x00 0x100>,
+ <0x00 0xfd20200 0x00 0x200>;
+ reg-names = "core", "mmu";
+ clocks = <&k3_clks 201 0>;
+ power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
index 59db830..18603f6 100644
--- a/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
@@ -23,6 +23,7 @@
oneOf:
- enum:
- mediatek,mt8183-mdp3-rdma
+ - mediatek,mt8188-mdp3-rdma
- mediatek,mt8195-mdp3-rdma
- mediatek,mt8195-vdo1-rdma
- items:
diff --git a/dts/upstream/Bindings/media/mediatek,mt7622-cir.yaml b/dts/upstream/Bindings/media/mediatek,mt7622-cir.yaml
new file mode 100644
index 0000000..c01210e
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mt7622-cir.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mt7622-cir.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Consumer Infrared Receiver on-SoC Controller
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+allOf:
+ - $ref: rc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7622-cir
+ - mediatek,mt7623-cir
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: clk
+ - const: bus
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ir@10013000 {
+ compatible = "mediatek,mt7623-cir";
+ reg = <0x10013000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX>, <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "clk", "bus";
+ linux,rc-map-name = "rc-rc6-mce";
+ };
diff --git a/dts/upstream/Bindings/media/mtk-cir.txt b/dts/upstream/Bindings/media/mtk-cir.txt
deleted file mode 100644
index 5e18087..0000000
--- a/dts/upstream/Bindings/media/mtk-cir.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Device-Tree bindings for Mediatek consumer IR controller
-found in Mediatek SoC family
-
-Required properties:
-- compatible : Should be
- "mediatek,mt7623-cir": for MT7623 SoC
- "mediatek,mt7622-cir": for MT7622 SoC
-- clocks : list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : should contain
- - "clk" entries: for MT7623 SoC
- - "clk", "bus" entries: for MT7622 SoC
-- interrupts : should contain IR IRQ number;
-- reg : should contain IO map address for IR.
-
-Optional properties:
-- linux,rc-map-name : see rc.txt file in the same directory.
-
-Example:
-
-cir: cir@10013000 {
- compatible = "mediatek,mt7623-cir";
- reg = <0 0x10013000 0 0x1000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_IRRX>;
- clock-names = "clk";
- linux,rc-map-name = "rc-rc6-mce";
-};
diff --git a/dts/upstream/Bindings/media/qcom,msm8996-venus.yaml b/dts/upstream/Bindings/media/qcom,msm8996-venus.yaml
index 3a4d817..56c1645 100644
--- a/dts/upstream/Bindings/media/qcom,msm8996-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8996-venus.yaml
@@ -18,7 +18,9 @@
properties:
compatible:
- const: qcom,msm8996-venus
+ enum:
+ - qcom,msm8996-venus
+ - qcom,msm8998-venus
power-domains:
maxItems: 1
diff --git a/dts/upstream/Bindings/media/raspberrypi,pispbe.yaml b/dts/upstream/Bindings/media/raspberrypi,pispbe.yaml
new file mode 100644
index 0000000..1fc62a1
--- /dev/null
+++ b/dts/upstream/Bindings/media/raspberrypi,pispbe.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/raspberrypi,pispbe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Raspberry Pi PiSP Image Signal Processor (ISP) Back End
+
+maintainers:
+ - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
+ - Jacopo Mondi <jacopo.mondi@ideasonboard.com>
+
+description: |
+ The Raspberry Pi PiSP Image Signal Processor (ISP) Back End is an image
+ processor that fetches images in Bayer or Grayscale format from DRAM memory
+ in tiles and produces images consumable by applications.
+
+ The full ISP documentation is available at
+ https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm2712-pispbe
+ - const: raspberrypi,pispbe
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@880000 {
+ compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe";
+ reg = <0x10 0x00880000 0x0 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&firmware_clocks 7>;
+ iommus = <&iommu2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/media/rc.yaml b/dts/upstream/Bindings/media/rc.yaml
index 7bbe580..dedc5a4 100644
--- a/dts/upstream/Bindings/media/rc.yaml
+++ b/dts/upstream/Bindings/media/rc.yaml
@@ -103,6 +103,7 @@
- rc-msi-digivox-iii
- rc-msi-tvanywhere
- rc-msi-tvanywhere-plus
+ - rc-mygica-utv3
- rc-nebula
- rc-nec-terratec-cinergy-xs
- rc-norwood
diff --git a/dts/upstream/Bindings/media/renesas,rzg2l-cru.yaml b/dts/upstream/Bindings/media/renesas,rzg2l-cru.yaml
index 1e72b88..bc12451 100644
--- a/dts/upstream/Bindings/media/renesas,rzg2l-cru.yaml
+++ b/dts/upstream/Bindings/media/renesas,rzg2l-cru.yaml
@@ -19,6 +19,7 @@
compatible:
items:
- enum:
+ - renesas,r9a07g043-cru # RZ/G2UL
- renesas,r9a07g044-cru # RZ/G2{L,LC}
- renesas,r9a07g054-cru # RZ/V2L
- const: renesas,rzg2l-cru
@@ -87,10 +88,6 @@
Input port node, describing the Image Processing module connected to the
CSI-2 receiver.
- required:
- - port@0
- - port@1
-
required:
- compatible
- reg
@@ -102,6 +99,36 @@
- reset-names
- power-domains
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a07g044-cru
+ - renesas,r9a07g054-cru
+ then:
+ properties:
+ ports:
+ required:
+ - port@0
+ - port@1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a07g043-cru
+ then:
+ properties:
+ ports:
+ properties:
+ port@0: false
+
+ required:
+ - port@1
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/media/renesas,rzg2l-csi2.yaml b/dts/upstream/Bindings/media/renesas,rzg2l-csi2.yaml
index 67eea2a..7faa12f 100644
--- a/dts/upstream/Bindings/media/renesas,rzg2l-csi2.yaml
+++ b/dts/upstream/Bindings/media/renesas,rzg2l-csi2.yaml
@@ -19,6 +19,7 @@
compatible:
items:
- enum:
+ - renesas,r9a07g043-csi2 # RZ/G2UL
- renesas,r9a07g044-csi2 # RZ/G2{L,LC}
- renesas,r9a07g054-csi2 # RZ/V2L
- const: renesas,rzg2l-csi2
diff --git a/dts/upstream/Bindings/media/rockchip-rga.yaml b/dts/upstream/Bindings/media/rockchip-rga.yaml
index ea23422..ac17cda 100644
--- a/dts/upstream/Bindings/media/rockchip-rga.yaml
+++ b/dts/upstream/Bindings/media/rockchip-rga.yaml
@@ -24,6 +24,7 @@
- enum:
- rockchip,rk3228-rga
- rockchip,rk3568-rga
+ - rockchip,rk3588-rga
- const: rockchip,rk3288-rga
reg:
diff --git a/dts/upstream/Bindings/memory-controllers/fsl/fsl,ifc.yaml b/dts/upstream/Bindings/memory-controllers/fsl/fsl,ifc.yaml
index 3be1db3..d1c3421 100644
--- a/dts/upstream/Bindings/memory-controllers/fsl/fsl,ifc.yaml
+++ b/dts/upstream/Bindings/memory-controllers/fsl/fsl,ifc.yaml
@@ -7,7 +7,7 @@
title: FSL/NXP Integrated Flash Controller
maintainers:
- - Li Yang <leoyang.li@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
description: |
NXP's integrated flash controller (IFC) is an advanced version of the
diff --git a/dts/upstream/Bindings/memory-controllers/fsl/mmdc.yaml b/dts/upstream/Bindings/memory-controllers/fsl/mmdc.yaml
index 71547ee..5447f1d 100644
--- a/dts/upstream/Bindings/memory-controllers/fsl/mmdc.yaml
+++ b/dts/upstream/Bindings/memory-controllers/fsl/mmdc.yaml
@@ -7,7 +7,9 @@
title: Freescale Multi Mode DDR controller (MMDC)
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/mfd/marvell,88pm886-a1.yaml b/dts/upstream/Bindings/mfd/marvell,88pm886-a1.yaml
new file mode 100644
index 0000000..d6a71c9
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/marvell,88pm886-a1.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/marvell,88pm886-a1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell 88PM886 PMIC core
+
+maintainers:
+ - Karel Balej <balejk@matfyz.cz>
+
+description:
+ Marvell 88PM886 is a PMIC providing several functions such as onkey,
+ regulators or battery and charger.
+
+properties:
+ compatible:
+ const: marvell,88pm886-a1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ wakeup-source: true
+
+ regulators:
+ type: object
+ additionalProperties: false
+ patternProperties:
+ "^(ldo(1[0-6]|[1-9])|buck[1-5])$":
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ description: LDO or buck regulator.
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@30 {
+ compatible = "marvell,88pm886-a1";
+ reg = <0x30>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ wakeup-source;
+
+ regulators {
+ ldo2: ldo2 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo15: ldo15 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ buck2: buck2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/mfd/mediatek,mt8195-scpsys.yaml b/dts/upstream/Bindings/mfd/mediatek,mt8195-scpsys.yaml
index c8c4812..768390b 100644
--- a/dts/upstream/Bindings/mfd/mediatek,mt8195-scpsys.yaml
+++ b/dts/upstream/Bindings/mfd/mediatek,mt8195-scpsys.yaml
@@ -22,8 +22,10 @@
- mediatek,mt8173-scpsys
- mediatek,mt8183-scpsys
- mediatek,mt8186-scpsys
+ - mediatek,mt8188-scpsys
- mediatek,mt8192-scpsys
- mediatek,mt8195-scpsys
+ - mediatek,mt8365-scpsys
- const: syscon
- const: simple-mfd
diff --git a/dts/upstream/Bindings/mfd/mfd.txt b/dts/upstream/Bindings/mfd/mfd.txt
index 336c049..b938fa2 100644
--- a/dts/upstream/Bindings/mfd/mfd.txt
+++ b/dts/upstream/Bindings/mfd/mfd.txt
@@ -17,13 +17,14 @@
Optional properties:
-- compatible : "simple-mfd" - this signifies that the operating system should
- consider all subnodes of the MFD device as separate devices akin to how
- "simple-bus" indicates when to see subnodes as children for a simple
- memory-mapped bus. For more complex devices, when the nexus driver has to
- probe registers to figure out what child devices exist etc, this should not
- be used. In the latter case the child devices will be determined by the
- operating system.
+- compatible : "simple-mfd" - this signifies that the operating system
+ should consider all subnodes of the MFD device as separate and independent
+ devices, so not needing any resources to be provided by the parent device.
+ Similarly to how "simple-bus" indicates when to see subnodes as children for
+ a simple memory-mapped bus.
+ For more complex devices, when the nexus driver has to probe registers to
+ figure out what child devices exist etc, this should not be used. In the
+ latter case the child devices will be determined by the operating system.
- ranges: Describes the address mapping relationship to the parent. Should set
the child's base address to 0, the physical address within parent's address
diff --git a/dts/upstream/Bindings/mfd/qcom,pm8008.yaml b/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
index 0c75d8b..0c6e187 100644
--- a/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
@@ -19,110 +19,136 @@
const: qcom,pm8008
reg:
- description:
- I2C slave address.
-
maxItems: 1
interrupts:
maxItems: 1
- description: Parent interrupt.
+ reset-gpios:
+ maxItems: 1
- "#interrupt-cells":
+ vdd-l1-l2-supply: true
+ vdd-l3-l4-supply: true
+ vdd-l5-supply: true
+ vdd-l6-supply: true
+ vdd-l7-supply: true
+
+ gpio-controller: true
+
+ "#gpio-cells":
const: 2
- description: |
- The first cell is the IRQ number, the second cell is the IRQ trigger
- flag. All interrupts are listed in include/dt-bindings/mfd/qcom-pm8008.h.
+ gpio-ranges:
+ maxItems: 1
interrupt-controller: true
- "#address-cells":
- const: 1
+ "#interrupt-cells":
+ const: 2
- "#size-cells":
+ "#thermal-sensor-cells":
const: 0
-patternProperties:
- "^gpio@[0-9a-f]+$":
+ pinctrl:
type: object
-
- description: |
- The GPIO peripheral. This node may be specified twice, one for each GPIO.
-
- properties:
- compatible:
- items:
- - const: qcom,pm8008-gpio
- - const: qcom,spmi-gpio
-
- reg:
- description: Peripheral address of one of the two GPIO peripherals.
- maxItems: 1
-
- gpio-controller: true
+ additionalProperties: false
+ patternProperties:
+ "-state$":
+ type: object
- gpio-ranges:
- maxItems: 1
+ allOf:
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
- interrupt-controller: true
+ properties:
+ pins:
+ items:
+ pattern: "^gpio[12]$"
- "#interrupt-cells":
- const: 2
+ function:
+ items:
+ - enum:
+ - normal
- "#gpio-cells":
- const: 2
+ required:
+ - pins
+ - function
- required:
- - compatible
- - reg
- - gpio-controller
- - interrupt-controller
- - "#gpio-cells"
- - gpio-ranges
- - "#interrupt-cells"
+ additionalProperties: false
+ regulators:
+ type: object
additionalProperties: false
+ patternProperties:
+ "^ldo[1-7]$":
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- - "#address-cells"
- - "#size-cells"
+ - vdd-l1-l2-supply
+ - vdd-l3-l4-supply
+ - vdd-l5-supply
+ - vdd-l6-supply
+ - vdd-l7-supply
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
- "#interrupt-cells"
+ - "#thermal-sensor-cells"
additionalProperties: false
examples:
- |
- #include <dt-bindings/mfd/qcom-pm8008.h>
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
- pmic@8 {
+ pm8008: pmic@8 {
compatible = "qcom,pm8008";
reg = <0x8>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
interrupt-parent = <&tlmm>;
interrupts = <32 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s8b_1p2>;
+ vdd-l3-l4-supply = <&vreg_s1b_1p8>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ pinctrl {
+ gpio-keys-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+ };
+
- pm8008_gpios: gpio@c000 {
- compatible = "qcom,pm8008-gpio", "qcom,spmi-gpio";
- reg = <0xc000>;
- gpio-controller;
- gpio-ranges = <&pm8008_gpios 0 0 2>;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ regulators {
+ ldo1 {
+ regulator-name = "vreg_l1";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
};
};
diff --git a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
index b7f01cb..a2b2fbf 100644
--- a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
@@ -75,6 +75,7 @@
- qcom,pma8084
- qcom,pmc8180
- qcom,pmc8180c
+ - qcom,pmc8380
- qcom,pmd9635
- qcom,pmi632
- qcom,pmi8950
@@ -95,6 +96,7 @@
- qcom,pmx65
- qcom,pmx75
- qcom,smb2351
+ - qcom,smb2360
- const: qcom,spmi-pmic
reg:
diff --git a/dts/upstream/Bindings/mfd/rockchip,rk809.yaml b/dts/upstream/Bindings/mfd/rockchip,rk809.yaml
deleted file mode 100644
index 839c052..0000000
--- a/dts/upstream/Bindings/mfd/rockchip,rk809.yaml
+++ /dev/null
@@ -1,288 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: RK809 Power Management Integrated Circuit
-
-maintainers:
- - Chris Zhong <zyw@rock-chips.com>
- - Zhang Qing <zhangqing@rock-chips.com>
-
-description: |
- Rockchip RK809 series PMIC. This device consists of an i2c controlled MFD
- that includes regulators, an RTC, and power button.
-
-properties:
- compatible:
- enum:
- - rockchip,rk809
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- '#clock-cells':
- description: |
- See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
- minimum: 0
- maximum: 1
-
- clock-output-names:
- description:
- From common clock binding to override the default output clock name.
-
- rockchip,system-power-controller:
- type: boolean
- deprecated: true
- description:
- Telling whether or not this PMIC is controlling the system power.
-
- system-power-controller: true
-
- wakeup-source:
- type: boolean
- description:
- Device can be used as a wakeup source.
-
- vcc1-supply:
- description:
- The input supply for DCDC_REG1.
-
- vcc2-supply:
- description:
- The input supply for DCDC_REG2.
-
- vcc3-supply:
- description:
- The input supply for DCDC_REG3.
-
- vcc4-supply:
- description:
- The input supply for DCDC_REG4.
-
- vcc5-supply:
- description:
- The input supply for LDO_REG1, LDO_REG2, and LDO_REG3.
-
- vcc6-supply:
- description:
- The input supply for LDO_REG4, LDO_REG5, and LDO_REG6.
-
- vcc7-supply:
- description:
- The input supply for LDO_REG7, LDO_REG8, and LDO_REG9.
-
- vcc8-supply:
- description:
- The input supply for SWITCH_REG1.
-
- vcc9-supply:
- description:
- The input supply for DCDC_REG5 and SWITCH_REG2.
-
- regulators:
- type: object
- patternProperties:
- "^(LDO_REG[1-9]|DCDC_REG[1-5]|SWITCH_REG[1-2])$":
- type: object
- $ref: /schemas/regulator/regulator.yaml#
- unevaluatedProperties: false
- unevaluatedProperties: false
-
-allOf:
- - if:
- properties:
- '#clock-cells':
- const: 0
-
- then:
- properties:
- clock-output-names:
- maxItems: 1
-
- else:
- properties:
- clock-output-names:
- maxItems: 2
-
-required:
- - compatible
- - reg
- - interrupts
- - "#clock-cells"
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/pinctrl/rockchip.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- rk808: pmic@1b {
- compatible = "rockchip,rk808";
- reg = <0x1b>;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
- interrupt-parent = <&gpio3>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int_l_pin>;
- rockchip,system-power-controller;
- wakeup-source;
-
- vcc1-supply = <&vcc_sysin>;
- vcc2-supply = <&vcc_sysin>;
- vcc3-supply = <&vcc_sysin>;
- vcc4-supply = <&vcc_sysin>;
- vcc6-supply = <&vcc_sysin>;
- vcc7-supply = <&vcc_sysin>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc_sysin>;
- vcc10-supply = <&vcc_sysin>;
- vcc11-supply = <&vcc_sysin>;
- vcc12-supply = <&vcc3v3_sys>;
-
- regulators {
- vdd_center: DCDC_REG1 {
- regulator-name = "vdd_center";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_cpu_l: DCDC_REG2 {
- regulator-name = "vdd_cpu_l";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vcc_1v8: vcc_wl: DCDC_REG4 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc1v8_pmupll: LDO_REG3 {
- regulator-name = "vcc1v8_pmupll";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcc_sdio: LDO_REG4 {
- regulator-name = "vcc_sdio";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcca3v0_codec: LDO_REG5 {
- regulator-name = "vcca3v0_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v5: LDO_REG6 {
- regulator-name = "vcc_1v5";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1500000>;
- };
- };
-
- vcca1v8_codec: LDO_REG7 {
- regulator-name = "vcca1v8_codec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v0: LDO_REG8 {
- regulator-name = "vcc_3v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3000000>;
- };
- };
-
- vcc3v3_s3: SWITCH_REG1 {
- regulator-name = "vcc3v3_s3";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_s0: SWITCH_REG2 {
- regulator-name = "vcc3v3_s0";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
- };
diff --git a/dts/upstream/Bindings/mfd/rockchip,rk817.yaml b/dts/upstream/Bindings/mfd/rockchip,rk817.yaml
index 8c2fd0f..2cb6d17 100644
--- a/dts/upstream/Bindings/mfd/rockchip,rk817.yaml
+++ b/dts/upstream/Bindings/mfd/rockchip,rk817.yaml
@@ -4,20 +4,21 @@
$id: http://devicetree.org/schemas/mfd/rockchip,rk817.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: RK817 Power Management Integrated Circuit
+title: RK809/RK817 Power Management Integrated Circuit
maintainers:
- Chris Zhong <zyw@rock-chips.com>
- Zhang Qing <zhangqing@rock-chips.com>
description: |
- Rockchip RK817 series PMIC. This device consists of an i2c controlled MFD
- that includes regulators, an RTC, a power button, an audio codec, and a
- battery charger manager.
+ Rockchip RK809/RK817 series PMIC. This device consists of an i2c controlled
+ MFD that includes regulators, an RTC, a power button and an audio codec.
+ The RK817 variant also provides a battery charger manager.
properties:
compatible:
enum:
+ - rockchip,rk809
- rockchip,rk817
reg:
@@ -32,6 +33,13 @@
minimum: 0
maximum: 1
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mclk
+
clock-output-names:
description:
From common clock binding to override the default output clock name.
@@ -42,6 +50,9 @@
description:
Telling whether or not this PMIC is controlling the system power.
+ '#sound-dai-cells':
+ const: 0
+
system-power-controller: true
wakeup-source:
@@ -79,41 +90,22 @@
vcc8-supply:
description:
- The input supply for BOOST.
+ The input supply for BOOST on RK817, or for SWITCH_REG2 on RK809.
vcc9-supply:
description:
- The input supply for OTG_SWITCH.
+ The input supply for OTG_SWITCH on RK817,
+ or for DCDC_REG5 and SWITCH_REG1 on RK809.
regulators:
type: object
patternProperties:
- "^(LDO_REG[1-9]|DCDC_REG[1-4]|BOOST|OTG_SWITCH)$":
- type: object
+ "^(LDO_REG[1-9]|DCDC_REG[1-5]|BOOST|OTG_SWITCH|SWITCH_REG[1-2])$":
+ $ref: /schemas/regulator/regulator.yaml
unevaluatedProperties: false
- $ref: /schemas/regulator/regulator.yaml#
- unevaluatedProperties: false
-
- clocks:
- description:
- The input clock for the audio codec.
-
- clock-names:
- description:
- The clock name for the codec clock.
- items:
- - const: mclk
-
- '#sound-dai-cells':
- description:
- Needed for the interpretation of sound dais.
- const: 0
+ additionalProperties: false
codec:
- description: |
- The child node for the codec to hold additional properties. If no
- additional properties are required for the codec, this node can be
- omitted.
type: object
additionalProperties: false
properties:
@@ -123,9 +115,6 @@
Describes if the microphone uses differential mode.
charger:
- description: |
- The child node for the charger to hold additional properties. If a
- battery is not in use, this node can be omitted.
type: object
$ref: /schemas/power/supply/power-supply.yaml
@@ -168,6 +157,7 @@
additionalProperties: false
allOf:
+ - $ref: /schemas/sound/dai-common.yaml#
- if:
properties:
'#clock-cells':
@@ -183,6 +173,22 @@
clock-output-names:
maxItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk817
+ then:
+ properties:
+ regulators:
+ patternProperties:
+ "^(DCDC_REG5|SWITCH_REG[1-2])$": false
+ else:
+ properties:
+ regulators:
+ patternProperties:
+ "^(BOOST|OTG_SWITCH)$": false
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml b/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml
new file mode 100644
index 0000000..d381125
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/rohm,bd96801-pmic.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD96801 Scalable Power Management Integrated Circuit
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description:
+ BD96801 is an automotive grade single-chip power management IC.
+ It integrates 4 buck converters and 3 LDOs with safety features like
+ over-/under voltage and over current detection and a watchdog.
+
+properties:
+ compatible:
+ const: rohm,bd96801
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ The PMIC provides intb and errb IRQ lines. The errb IRQ line is used
+ for fatal IRQs which will cause the PMIC to shut down power outputs.
+ In many systems this will shut down the SoC contolling the PMIC and
+ connecting/handling the errb can be omitted. However, there are cases
+ where the SoC is not powered by the PMIC or has a short time backup
+ energy to handle shutdown of critical hardware. In that case it may be
+ useful to connect the errb and handle errb events.
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - enum: [intb, errb]
+ - const: errb
+
+ rohm,hw-timeout-ms:
+ description:
+ Watchdog timeout value(s). First walue is timeout limit. Second value is
+ optional value for 'too early' watchdog ping if window timeout mode is
+ to be used.
+ minItems: 1
+ maxItems: 2
+
+ rohm,wdg-action:
+ description:
+ Whether the watchdog failure must turn off the regulator power outputs or
+ just toggle the INTB line.
+ enum:
+ - prstb
+ - intb-only
+
+ timeout-sec:
+ maxItems: 2
+
+ regulators:
+ $ref: /schemas/regulator/rohm,bd96801-regulator.yaml
+ description:
+ List of child nodes that specify the regulators.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic: pmic@60 {
+ reg = <0x60>;
+ compatible = "rohm,bd96801";
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "intb", "errb";
+
+ regulators {
+ buck1 {
+ regulator-name = "buck1";
+ regulator-ramp-delay = <1250>;
+ /* 0.5V min INITIAL - 150 mV tune */
+ regulator-min-microvolt = <350000>;
+ /* 3.3V + 150mV tune */
+ regulator-max-microvolt = <3450000>;
+
+ /* These can be set only when PMIC is in STBY */
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <230000>;
+ regulator-uv-error-microvolt = <230000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ buck2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <3000000>;
+ regulator-ov-error-microvolt = <18000>;
+ regulator-uv-error-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <1>;
+ };
+ buck3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <600000>;
+ regulator-ov-warn-microvolt = <18000>;
+ regulator-uv-warn-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-error-kelvin = <0>;
+ };
+ buck4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3450000>;
+
+ rohm,initial-voltage-microvolt = <600000>;
+ regulator-ov-warn-microvolt = <18000>;
+ regulator-uv-warn-microvolt = <18000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-error-kelvin = <0>;
+ };
+ ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <300000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <3300000>;
+
+ rohm,initial-voltage-microvolt = <500000>;
+ regulator-ov-error-microvolt = <36000>;
+ regulator-uv-error-microvolt = <34000>;
+ regulator-temp-protection-kelvin = <1>;
+ regulator-temp-warn-kelvin = <0>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/mfd/syscon-common.yaml b/dts/upstream/Bindings/mfd/syscon-common.yaml
new file mode 100644
index 0000000..451cbad
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/syscon-common.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/syscon-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Controller Registers R/W Common Properties
+
+description:
+ System controller node represents a register region containing a set
+ of miscellaneous registers. The registers are not cohesive enough to
+ represent as any specific type of device. The typical use-case is
+ for some other node's driver, or platform-specific code, to acquire
+ a reference to the syscon node (e.g. by phandle, node path, or
+ search using a specific compatible value), interrogate the node (or
+ associated OS driver) to determine the location of the registers,
+ and access the registers directly.
+
+maintainers:
+ - Lee Jones <lee@kernel.org>
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: syscon
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ contains:
+ const: syscon
+ minItems: 2
+ maxItems: 5 # Should be enough
+
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ description:
+ The size (in bytes) of the IO accesses that should be performed
+ on the device.
+ enum: [1, 2, 4, 8]
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: simple-mfd
+ then:
+ properties:
+ compatible:
+ minItems: 3
+ maxItems: 5
+
+additionalProperties: true
+
+examples:
+ - |
+ syscon: syscon@1c00000 {
+ compatible = "allwinner,sun8i-h3-system-controller", "syscon";
+ reg = <0x01c00000 0x1000>;
+ };
+...
diff --git a/dts/upstream/Bindings/mfd/syscon.yaml b/dts/upstream/Bindings/mfd/syscon.yaml
index 7ed12a9..9dc594e 100644
--- a/dts/upstream/Bindings/mfd/syscon.yaml
+++ b/dts/upstream/Bindings/mfd/syscon.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/mfd/syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: System Controller Registers R/W
+title: System Controller Devices
description: |
System controller node represents a register region containing a set
@@ -19,121 +19,213 @@
maintainers:
- Lee Jones <lee@kernel.org>
+# Need a select with all compatibles listed for compatibility with older
+# dtschema (<2024.02), so this will not be selected for other schemas having
+# syscon fallback.
select:
properties:
compatible:
contains:
enum:
- - syscon
-
+ - al,alpine-sysfabric-servic
+ - allwinner,sun8i-a83t-system-controller
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - altr,l3regs
+ - altr,sdr-ctl
+ - amd,pensando-elba-syscon
+ - amlogic,meson-mx-assist
+ - amlogic,meson-mx-bootrom
+ - amlogic,meson8-analog-top
+ - amlogic,meson8b-analog-top
+ - amlogic,meson8-pmu
+ - amlogic,meson8b-pmu
+ - apm,merlin-poweroff-mailbox
+ - apm,mustang-poweroff-mailbox
+ - apm,xgene-csw
+ - apm,xgene-efuse
+ - apm,xgene-mcb
+ - apm,xgene-rb
+ - apm,xgene-scu
+ - atmel,sama5d2-sfrbu
+ - atmel,sama5d3-nfc-io
+ - atmel,sama5d3-sfrbu
+ - atmel,sama5d4-sfrbu
+ - axis,artpec6-syscon
+ - brcm,cru-clkset
+ - brcm,sr-cdru
+ - brcm,sr-mhb
+ - cirrus,ep7209-syscon1
+ - cirrus,ep7209-syscon2
+ - cirrus,ep7209-syscon3
+ - cnxt,cx92755-uc
+ - freecom,fsg-cs2-system-controller
+ - fsl,imx93-aonmix-ns-syscfg
+ - fsl,imx93-wakeupmix-syscfg
+ - fsl,ls1088a-reset
+ - fsl,vf610-anatop
+ - fsl,vf610-mscm-cpucfg
+ - hisilicon,dsa-subctrl
+ - hisilicon,hi6220-sramctrl
+ - hisilicon,hip04-ppe
+ - hisilicon,pcie-sas-subctrl
+ - hisilicon,peri-subctrl
+ - hpe,gxp-sysreg
+ - loongson,ls1b-syscon
+ - loongson,ls1c-syscon
+ - lsi,axxia-syscon
+ - marvell,armada-3700-cpu-misc
+ - marvell,armada-3700-nb-pm
+ - marvell,armada-3700-avs
+ - marvell,armada-3700-usb2-host-misc
+ - marvell,dove-global-config
+ - mediatek,mt2701-pctl-a-syscfg
+ - mediatek,mt2712-pctl-a-syscfg
+ - mediatek,mt6397-pctl-pmic-syscfg
+ - mediatek,mt8135-pctl-a-syscfg
+ - mediatek,mt8135-pctl-b-syscfg
+ - mediatek,mt8173-pctl-a-syscfg
+ - mediatek,mt8365-syscfg
+ - microchip,lan966x-cpu-syscon
+ - microchip,sam9x60-sfr
+ - microchip,sama7g5-ddr3phy
+ - mscc,ocelot-cpu-syscon
+ - mstar,msc313-pmsleep
+ - nuvoton,ma35d1-sys
+ - nuvoton,wpcm450-shm
+ - rockchip,px30-qos
+ - rockchip,rk3036-qos
+ - rockchip,rk3066-qos
+ - rockchip,rk3128-qos
+ - rockchip,rk3228-qos
+ - rockchip,rk3288-qos
+ - rockchip,rk3368-qos
+ - rockchip,rk3399-qos
+ - rockchip,rk3568-qos
+ - rockchip,rk3588-qos
+ - rockchip,rv1126-qos
+ - st,spear1340-misc
+ - stericsson,nomadik-pmu
+ - starfive,jh7100-sysmain
+ - ti,am62-opp-efuse-table
+ - ti,am62-usb-phy-ctrl
+ - ti,am625-dss-oldi-io-ctrl
+ - ti,am62p-cpsw-mac-efuse
+ - ti,am654-dss-oldi-io-ctrl
+ - ti,j784s4-pcie-ctrl
+ - ti,keystone-pllctrl
required:
- compatible
properties:
compatible:
- anyOf:
- - items:
- - enum:
- - allwinner,sun8i-a83t-system-controller
- - allwinner,sun8i-h3-system-controller
- - allwinner,sun8i-v3s-system-controller
- - allwinner,sun50i-a64-system-controller
- - altr,sdr-ctl
- - amd,pensando-elba-syscon
- - apm,xgene-csw
- - apm,xgene-efuse
- - apm,xgene-mcb
- - apm,xgene-rb
- - apm,xgene-scu
- - brcm,cru-clkset
- - brcm,sr-cdru
- - brcm,sr-mhb
- - freecom,fsg-cs2-system-controller
- - fsl,imx93-aonmix-ns-syscfg
- - fsl,imx93-wakeupmix-syscfg
- - fsl,ls1088a-reset
- - hisilicon,dsa-subctrl
- - hisilicon,hi6220-sramctrl
- - hisilicon,pcie-sas-subctrl
- - hisilicon,peri-subctrl
- - hpe,gxp-sysreg
- - intel,lgm-syscon
- - loongson,ls1b-syscon
- - loongson,ls1c-syscon
- - marvell,armada-3700-cpu-misc
- - marvell,armada-3700-nb-pm
- - marvell,armada-3700-avs
- - marvell,armada-3700-usb2-host-misc
- - mediatek,mt2712-pctl-a-syscfg
- - mediatek,mt6397-pctl-pmic-syscfg
- - mediatek,mt8135-pctl-a-syscfg
- - mediatek,mt8135-pctl-b-syscfg
- - mediatek,mt8173-pctl-a-syscfg
- - mediatek,mt8365-syscfg
- - microchip,lan966x-cpu-syscon
- - microchip,sparx5-cpu-syscon
- - mstar,msc313-pmsleep
- - nuvoton,ma35d1-sys
- - nuvoton,wpcm450-shm
- - rockchip,px30-qos
- - rockchip,rk3036-qos
- - rockchip,rk3066-qos
- - rockchip,rk3128-qos
- - rockchip,rk3228-qos
- - rockchip,rk3288-qos
- - rockchip,rk3368-qos
- - rockchip,rk3399-qos
- - rockchip,rk3568-qos
- - rockchip,rk3588-qos
- - rockchip,rv1126-qos
- - starfive,jh7100-sysmain
- - ti,am62-usb-phy-ctrl
- - ti,am62p-cpsw-mac-efuse
- - ti,am654-dss-oldi-io-ctrl
- - ti,am654-serdes-ctrl
- - ti,j784s4-pcie-ctrl
-
- - const: syscon
-
- - contains:
- const: syscon
- minItems: 2
- maxItems: 5 # Should be enough
+ items:
+ - enum:
+ - al,alpine-sysfabric-service
+ - allwinner,sun8i-a83t-system-controller
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - altr,l3regs
+ - altr,sdr-ctl
+ - amd,pensando-elba-syscon
+ - amlogic,meson-mx-assist
+ - amlogic,meson-mx-bootrom
+ - amlogic,meson8-analog-top
+ - amlogic,meson8b-analog-top
+ - amlogic,meson8-pmu
+ - amlogic,meson8b-pmu
+ - apm,merlin-poweroff-mailbox
+ - apm,mustang-poweroff-mailbox
+ - apm,xgene-csw
+ - apm,xgene-efuse
+ - apm,xgene-mcb
+ - apm,xgene-rb
+ - apm,xgene-scu
+ - atmel,sama5d2-sfrbu
+ - atmel,sama5d3-nfc-io
+ - atmel,sama5d3-sfrbu
+ - atmel,sama5d4-sfrbu
+ - axis,artpec6-syscon
+ - brcm,cru-clkset
+ - brcm,sr-cdru
+ - brcm,sr-mhb
+ - cirrus,ep7209-syscon1
+ - cirrus,ep7209-syscon2
+ - cirrus,ep7209-syscon3
+ - cnxt,cx92755-uc
+ - freecom,fsg-cs2-system-controller
+ - fsl,imx93-aonmix-ns-syscfg
+ - fsl,imx93-wakeupmix-syscfg
+ - fsl,ls1088a-reset
+ - fsl,vf610-anatop
+ - fsl,vf610-mscm-cpucfg
+ - hisilicon,dsa-subctrl
+ - hisilicon,hi6220-sramctrl
+ - hisilicon,hip04-ppe
+ - hisilicon,pcie-sas-subctrl
+ - hisilicon,peri-subctrl
+ - hpe,gxp-sysreg
+ - loongson,ls1b-syscon
+ - loongson,ls1c-syscon
+ - lsi,axxia-syscon
+ - marvell,armada-3700-cpu-misc
+ - marvell,armada-3700-nb-pm
+ - marvell,armada-3700-avs
+ - marvell,armada-3700-usb2-host-misc
+ - marvell,dove-global-config
+ - mediatek,mt2701-pctl-a-syscfg
+ - mediatek,mt2712-pctl-a-syscfg
+ - mediatek,mt6397-pctl-pmic-syscfg
+ - mediatek,mt8135-pctl-a-syscfg
+ - mediatek,mt8135-pctl-b-syscfg
+ - mediatek,mt8173-pctl-a-syscfg
+ - mediatek,mt8365-syscfg
+ - microchip,lan966x-cpu-syscon
+ - microchip,sam9x60-sfr
+ - microchip,sama7g5-ddr3phy
+ - mscc,ocelot-cpu-syscon
+ - mstar,msc313-pmsleep
+ - nuvoton,ma35d1-sys
+ - nuvoton,wpcm450-shm
+ - rockchip,px30-qos
+ - rockchip,rk3036-qos
+ - rockchip,rk3066-qos
+ - rockchip,rk3128-qos
+ - rockchip,rk3228-qos
+ - rockchip,rk3288-qos
+ - rockchip,rk3368-qos
+ - rockchip,rk3399-qos
+ - rockchip,rk3568-qos
+ - rockchip,rk3588-qos
+ - rockchip,rv1126-qos
+ - st,spear1340-misc
+ - stericsson,nomadik-pmu
+ - starfive,jh7100-sysmain
+ - ti,am62-opp-efuse-table
+ - ti,am62-usb-phy-ctrl
+ - ti,am625-dss-oldi-io-ctrl
+ - ti,am62p-cpsw-mac-efuse
+ - ti,am654-dss-oldi-io-ctrl
+ - ti,j784s4-pcie-ctrl
+ - ti,keystone-pllctrl
+ - const: syscon
reg:
maxItems: 1
- reg-io-width:
- description: |
- The size (in bytes) of the IO accesses that should be performed
- on the device.
- enum: [1, 2, 4, 8]
-
resets:
maxItems: 1
-
- hwlocks:
- maxItems: 1
- description:
- Reference to a phandle of a hardware spinlock provider node.
required:
- compatible
- reg
allOf:
- - if:
- properties:
- compatible:
- contains:
- const: simple-mfd
- then:
- properties:
- compatible:
- minItems: 3
- maxItems: 5
+ - $ref: syscon-common.yaml#
-additionalProperties: true
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/mfd/ti,j721e-system-controller.yaml b/dts/upstream/Bindings/mfd/ti,j721e-system-controller.yaml
deleted file mode 100644
index e6289fb..0000000
--- a/dts/upstream/Bindings/mfd/ti,j721e-system-controller.yaml
+++ /dev/null
@@ -1,114 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: TI J721e System Controller Registers R/W
-
-description: |
- This represents the Control Module registers (CTRL_MMR0) on the SoC.
- System controller node represents a register region containing a set
- of miscellaneous registers. The registers are not cohesive enough to
- represent as any specific type of device. The typical use-case is
- for some other node's driver, or platform-specific code, to acquire
- a reference to the syscon node (e.g. by phandle, node path, or
- search using a specific compatible value), interrogate the node (or
- associated OS driver) to determine the location of the registers,
- and access the registers directly.
-
-maintainers:
- - Kishon Vijay Abraham I <kishon@ti.com>
- - Roger Quadros <rogerq@kernel.org>
-
-properties:
- compatible:
- items:
- - enum:
- - ti,j7200-system-controller
- - ti,j721e-system-controller
- - ti,j721s2-system-controller
- - const: syscon
- - const: simple-mfd
-
- reg:
- maxItems: 1
-
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 1
-
- ranges: true
-
-patternProperties:
- # Optional children
- "^mux-controller@[0-9a-f]+$":
- type: object
- description:
- This is the SERDES lane control mux.
-
- "^clock-controller@[0-9a-f]+$":
- type: object
- $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
- description:
- Clock provider for TI EHRPWM nodes.
-
- "phy@[0-9a-f]+$":
- type: object
- $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
- description:
- The phy node corresponding to the ethernet MAC.
-
- "^chipid@[0-9a-f]+$":
- type: object
- $ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
- description:
- The node corresponding to SoC chip identification.
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - ranges
-
-additionalProperties: false
-
-examples:
- - |
- scm_conf: scm-conf@100000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00100000 0x1c000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- serdes_ln_ctrl: mux-controller@4080 {
- compatible = "mmio-mux";
- reg = <0x00004080 0x50>;
-
- #mux-control-cells = <1>;
- mux-reg-masks =
- <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
- <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
- <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
- <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
- /* SERDES4 lane0/1/2/3 select */
- };
-
- clock-controller@4140 {
- compatible = "ti,am654-ehrpwm-tbclk";
- reg = <0x4140 0x18>;
- #clock-cells = <1>;
- };
-
- chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- };
- };
-...
diff --git a/dts/upstream/Bindings/mfd/ti,twl.yaml b/dts/upstream/Bindings/mfd/ti,twl.yaml
index c2357fe..e94b0fd 100644
--- a/dts/upstream/Bindings/mfd/ti,twl.yaml
+++ b/dts/upstream/Bindings/mfd/ti,twl.yaml
@@ -22,6 +22,32 @@
contains:
const: ti,twl4030
then:
+ patternProperties:
+ "^regulator-":
+ properties:
+ compatible:
+ enum:
+ - ti,twl4030-vaux1
+ - ti,twl4030-vaux2
+ - ti,twl4030-vaux3
+ - ti,twl4030-vaux4
+ - ti,twl4030-vmmc1
+ - ti,twl4030-vmmc2
+ - ti,twl4030-vpll1
+ - ti,twl4030-vpll2
+ - ti,twl4030-vsim
+ - ti,twl4030-vdac
+ - ti,twl4030-vintana2
+ - ti,twl4030-vio
+ - ti,twl4030-vdd1
+ - ti,twl4030-vdd2
+ - ti,twl4030-vintana1
+ - ti,twl4030-vintdig
+ - ti,twl4030-vusb1v5
+ - ti,twl4030-vusb1v8
+ - ti,twl4030-vusb3v1
+ ti,retain-on-reset: false
+
properties:
madc:
type: object
@@ -50,13 +76,34 @@
properties:
compatible:
const: ti,twl4030-wdt
-
- if:
properties:
compatible:
contains:
const: ti,twl6030
then:
+ patternProperties:
+ "^regulator-":
+ properties:
+ compatible:
+ enum:
+ - ti,twl6030-vaux1
+ - ti,twl6030-vaux2
+ - ti,twl6030-vaux3
+ - ti,twl6030-vmmc
+ - ti,twl6030-vpp
+ - ti,twl6030-vusim
+ - ti,twl6030-vana
+ - ti,twl6030-vcxio
+ - ti,twl6030-vdac
+ - ti,twl6030-vusb
+ - ti,twl6030-v1v8
+ - ti,twl6030-v2v1
+ - ti,twl6030-vdd1
+ - ti,twl6030-vdd2
+ - ti,twl6030-vdd3
+ regulator-initial-mode: false
+
properties:
gpadc:
type: object
@@ -69,6 +116,25 @@
contains:
const: ti,twl6032
then:
+ patternProperties:
+ "^regulator-":
+ properties:
+ compatible:
+ enum:
+ - ti,twl6032-ldo1
+ - ti,twl6032-ldo2
+ - ti,twl6032-ldo3
+ - ti,twl6032-ldo4
+ - ti,twl6032-ldo5
+ - ti,twl6032-ldo6
+ - ti,twl6032-ldo7
+ - ti,twl6032-ldoln
+ - ti,twl6032-ldousb
+ - ti,twl6032-smps3
+ - ti,twl6032-smps4
+ - ti,twl6032-vio
+ regulator-initial-mode: false
+
properties:
gpadc:
type: object
@@ -112,6 +178,27 @@
interrupts:
maxItems: 1
+patternProperties:
+ "^regulator-":
+ type: object
+ unevaluatedProperties: false
+ $ref: /schemas/regulator/regulator.yaml
+ properties:
+ compatible: true
+ regulator-initial-mode:
+ enum:
+ - 0x08 # Sleep mode, the nominal output voltage is maintained
+ # with low power consumption with low load current capability
+ - 0x0e # Active mode, the regulator can deliver its nominal output
+ # voltage with full-load current capability
+ ti,retain-on-reset:
+ description:
+ Does not turn off the supplies during warm
+ reset. Could be needed for VMMC, as TWL6030
+ reset sequence for this signal does not comply
+ with the SD specification.
+ type: boolean
+
unevaluatedProperties: false
required:
@@ -131,9 +218,85 @@
compatible = "ti,twl6030";
reg = <0x48>;
interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
+ interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <1>;
- interrupt-parent = <&gic>;
+
+ gpadc {
+ compatible = "ti,twl6030-gpadc";
+ interrupts = <6>;
+ #io-channel-cells = <1>;
+ };
+
+ rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <8>;
+ };
+
+ regulator-vaux1 {
+ compatible = "ti,twl6030-vaux1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ regulator-vmmc1 {
+ compatible = "ti,twl6030-vmmc";
+ ti,retain-on-reset;
+ };
};
};
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@48 {
+ compatible = "ti,twl4030";
+ reg = <0x48>;
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ bci {
+ compatible = "ti,twl4030-bci";
+ interrupts = <9>, <2>;
+ bci3v1-supply = <&vusb3v1>;
+ io-channels = <&twl_madc 11>;
+ io-channel-names = "vac";
+ };
+
+ twl_madc: madc {
+ compatible = "ti,twl4030-madc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+
+ pwrbutton {
+ compatible = "ti,twl4030-pwrbutton";
+ interrupts = <8>;
+ };
+
+ rtc {
+ compatible = "ti,twl4030-rtc";
+ interrupts = <11>;
+ };
+
+ regulator-vaux1 {
+ compatible = "ti,twl4030-vaux1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <0xe>;
+ };
+
+ vusb3v1: regulator-vusb3v1 {
+ compatible = "ti,twl4030-vusb3v1";
+ };
+
+ watchdog {
+ compatible = "ti,twl4030-wdt";
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/mips/brcm/soc.yaml b/dts/upstream/Bindings/mips/brcm/soc.yaml
index 975945c..0cc6344 100644
--- a/dts/upstream/Bindings/mips/brcm/soc.yaml
+++ b/dts/upstream/Bindings/mips/brcm/soc.yaml
@@ -55,6 +55,16 @@
under the "cpus" node.
$ref: /schemas/types.yaml#/definitions/uint32
+ brcm,bmips-cbr-reg:
+ description: Reference address of the CBR.
+ Some SoC suffer from a BUG where CBR(Core Base Register)
+ address might be badly or never initialized by the Bootloader
+ or reading it from co-processor registers, if the system boots
+ from secondary CPU, results in invalid address.
+ The CBR address is always the same on the SoC hence it
+ can be provided in DT to handle these broken case.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
patternProperties:
"^cpu@[0-9]$":
type: object
@@ -64,6 +74,20 @@
required:
- mips-hpt-frequency
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm6358
+ - brcm,bcm6368
+
+then:
+ properties:
+ cpus:
+ required:
+ - brcm,bmips-cbr-reg
+
additionalProperties: true
examples:
diff --git a/dts/upstream/Bindings/mips/mobileye.yaml b/dts/upstream/Bindings/mips/mobileye.yaml
index 831975f..d607445 100644
--- a/dts/upstream/Bindings/mips/mobileye.yaml
+++ b/dts/upstream/Bindings/mips/mobileye.yaml
@@ -26,6 +26,11 @@
- enum:
- mobileye,eyeq5-epm5
- const: mobileye,eyeq5
+ - description: Boards with Mobileye EyeQ6H SoC
+ items:
+ - enum:
+ - mobileye,eyeq6h-epm6
+ - const: mobileye,eyeq6h
additionalProperties: true
diff --git a/dts/upstream/Bindings/mips/mscc.txt b/dts/upstream/Bindings/mips/mscc.txt
index cc916ea..e741656 100644
--- a/dts/upstream/Bindings/mips/mscc.txt
+++ b/dts/upstream/Bindings/mips/mscc.txt
@@ -25,23 +25,6 @@
reg = <0x71070000 0x1c>;
};
-
-o CPU system control:
-
-The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
-the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
-endianness, CPU bus control, CPU status.
-
-Required properties:
-- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
-- reg : Should contain registers location and length
-
-Example:
- syscon@70000000 {
- compatible = "mscc,ocelot-cpu-syscon", "syscon";
- reg = <0x70000000 0x2c>;
- };
-
o HSIO regs:
The SoC has a few registers (HSIO) handling miscellaneous functionalities:
diff --git a/dts/upstream/Bindings/mips/realtek-rtl.yaml b/dts/upstream/Bindings/mips/realtek-rtl.yaml
index f8ac309..d337655 100644
--- a/dts/upstream/Bindings/mips/realtek-rtl.yaml
+++ b/dts/upstream/Bindings/mips/realtek-rtl.yaml
@@ -20,5 +20,9 @@
- enum:
- cisco,sg220-26
- const: realtek,rtl8382-soc
+ - items:
+ - enum:
+ - cameo,rtl9302c-2x-rtl8224-2xge
+ - const: realtek,rtl9302-soc
additionalProperties: true
diff --git a/dts/upstream/Bindings/misc/fsl,qoriq-mc.txt b/dts/upstream/Bindings/misc/fsl,qoriq-mc.txt
deleted file mode 100644
index 7b486d4..0000000
--- a/dts/upstream/Bindings/misc/fsl,qoriq-mc.txt
+++ /dev/null
@@ -1,196 +0,0 @@
-* Freescale Management Complex
-
-The Freescale Management Complex (fsl-mc) is a hardware resource
-manager that manages specialized hardware objects used in
-network-oriented packet processing applications. After the fsl-mc
-block is enabled, pools of hardware resources are available, such as
-queues, buffer pools, I/O interfaces. These resources are building
-blocks that can be used to create functional hardware objects/devices
-such as network interfaces, crypto accelerator instances, L2 switches,
-etc.
-
-For an overview of the DPAA2 architecture and fsl-mc bus see:
-Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst
-
-As described in the above overview, all DPAA2 objects in a DPRC share the
-same hardware "isolation context" and a 10-bit value called an ICID
-(isolation context id) is expressed by the hardware to identify
-the requester.
-
-The generic 'iommus' property is insufficient to describe the relationship
-between ICIDs and IOMMUs, so an iommu-map property is used to define
-the set of possible ICIDs under a root DPRC and how they map to
-an IOMMU.
-
-For generic IOMMU bindings, see
-Documentation/devicetree/bindings/iommu/iommu.txt.
-
-For arm-smmu binding, see:
-Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
-
-The MSI writes are accompanied by sideband data which is derived from the ICID.
-The msi-map property is used to associate the devices with both the ITS
-controller and the sideband data which accompanies the writes.
-
-For generic MSI bindings, see
-Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-
-For GICv3 and GIC ITS bindings, see:
-Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
-
-Required properties:
-
- - compatible
- Value type: <string>
- Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex
- compatible with this binding must have Block Revision
- Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
- the MC control register region.
-
- - reg
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies one or two regions
- defining the MC's registers:
-
- -the first region is the command portal for the
- this machine and must always be present
-
- -the second region is the MC control registers. This
- region may not be present in some scenarios, such
- as in the device tree presented to a virtual machine.
-
- - ranges
- Value type: <prop-encoded-array>
- Definition: A standard property. Defines the mapping between the child
- MC address space and the parent system address space.
-
- The MC address space is defined by 3 components:
- <region type> <offset hi> <offset lo>
-
- Valid values for region type are
- 0x0 - MC portals
- 0x1 - QBMAN portals
-
- - #address-cells
- Value type: <u32>
- Definition: Must be 3. (see definition in 'ranges' property)
-
- - #size-cells
- Value type: <u32>
- Definition: Must be 1.
-
-Sub-nodes:
-
- The fsl-mc node may optionally have dpmac sub-nodes that describe
- the relationship between the Ethernet MACs which belong to the MC
- and the Ethernet PHYs on the system board.
-
- The dpmac nodes must be under a node named "dpmacs" which contains
- the following properties:
-
- - #address-cells
- Value type: <u32>
- Definition: Must be present if dpmac sub-nodes are defined and must
- have a value of 1.
-
- - #size-cells
- Value type: <u32>
- Definition: Must be present if dpmac sub-nodes are defined and must
- have a value of 0.
-
- These nodes must have the following properties:
-
- - compatible
- Value type: <string>
- Definition: Must be "fsl,qoriq-mc-dpmac".
-
- - reg
- Value type: <prop-encoded-array>
- Definition: Specifies the id of the dpmac.
-
- - phy-handle
- Value type: <phandle>
- Definition: Specifies the phandle to the PHY device node associated
- with the this dpmac.
-Optional properties:
-
-- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
- data.
-
- The property is an arbitrary number of tuples of
- (icid-base,iommu,iommu-base,length).
-
- Any ICID i in the interval [icid-base, icid-base + length) is
- associated with the listed IOMMU, with the iommu-specifier
- (i - icid-base + iommu-base).
-
-- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
- data.
-
- The property is an arbitrary number of tuples of
- (icid-base,gic-its,msi-base,length).
-
- Any ICID in the interval [icid-base, icid-base + length) is
- associated with the listed GIC ITS, with the msi-specifier
- (i - icid-base + msi-base).
-
-Deprecated properties:
-
- - msi-parent
- Value type: <phandle>
- Definition: Describes the MSI controller node handling message
- interrupts for the MC. When there is no translation
- between the ICID and deviceID this property can be used
- to describe the MSI controller used by the devices on the
- mc-bus.
- The use of this property for mc-bus is deprecated. Please
- use msi-map.
-
-Example:
-
- smmu: iommu@5000000 {
- compatible = "arm,mmu-500";
- #iommu-cells = <1>;
- stream-match-mask = <0x7C00>;
- ...
- };
-
- gic: interrupt-controller@6000000 {
- compatible = "arm,gic-v3";
- ...
- }
- its: gic-its@6020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- ...
- };
-
- fsl_mc: fsl-mc@80c000000 {
- compatible = "fsl,qoriq-mc";
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- /* define map for ICIDs 23-64 */
- iommu-map = <23 &smmu 23 41>;
- /* define msi map for ICIDs 23-64 */
- msi-map = <23 &its 23 41>;
- #address-cells = <3>;
- #size-cells = <1>;
-
- /*
- * Region type 0x0 - MC portals
- * Region type 0x1 - QBMAN portals
- */
- ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
- 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
-
- dpmacs {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dpmac@1 {
- compatible = "fsl,qoriq-mc-dpmac";
- reg = <1>;
- phy-handle = <&mdio0_phy0>;
- }
- }
- };
diff --git a/dts/upstream/Bindings/misc/fsl,qoriq-mc.yaml b/dts/upstream/Bindings/misc/fsl,qoriq-mc.yaml
new file mode 100644
index 0000000..01b00d8
--- /dev/null
+++ b/dts/upstream/Bindings/misc/fsl,qoriq-mc.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Management Complex
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ The Freescale Management Complex (fsl-mc) is a hardware resource
+ manager that manages specialized hardware objects used in
+ network-oriented packet processing applications. After the fsl-mc
+ block is enabled, pools of hardware resources are available, such as
+ queues, buffer pools, I/O interfaces. These resources are building
+ blocks that can be used to create functional hardware objects/devices
+ such as network interfaces, crypto accelerator instances, L2 switches,
+ etc.
+
+ For an overview of the DPAA2 architecture and fsl-mc bus see:
+ Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst
+
+ As described in the above overview, all DPAA2 objects in a DPRC share the
+ same hardware "isolation context" and a 10-bit value called an ICID
+ (isolation context id) is expressed by the hardware to identify
+ the requester.
+
+ The generic 'iommus' property is insufficient to describe the relationship
+ between ICIDs and IOMMUs, so an iommu-map property is used to define
+ the set of possible ICIDs under a root DPRC and how they map to
+ an IOMMU.
+
+ For generic IOMMU bindings, see
+ Documentation/devicetree/bindings/iommu/iommu.txt.
+
+ For arm-smmu binding, see:
+ Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
+
+ The MSI writes are accompanied by sideband data which is derived from the ICID.
+ The msi-map property is used to associate the devices with both the ITS
+ controller and the sideband data which accompanies the writes.
+
+ For generic MSI bindings, see
+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+ For GICv3 and GIC ITS bindings, see:
+ Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
+
+properties:
+ compatible:
+ enum:
+ - fsl,qoriq-mc
+ description:
+ Must be "fsl,qoriq-mc". A Freescale Management Complex
+ compatible with this binding must have Block Revision
+ Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
+ the MC control register region.
+
+ reg:
+ items:
+ - description:
+ the first region is the command portal for the
+ this machine and must always be present
+
+ - description:
+ the second region is the MC control registers. This
+ region may not be present in some scenarios, such
+ as in the device tree presented to a virtual machine.
+
+ ranges:
+ description: |
+ A standard property. Defines the mapping between the child
+ MC address space and the parent system address space.
+
+ The MC address space is defined by 3 components:
+ <region type> <offset hi> <offset lo>
+
+ Valid values for region type are
+ 0x0 - MC portals
+ 0x1 - QBMAN portals
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 1
+
+ iommu-map:
+ description: |
+ Maps an ICID to an IOMMU and associated iommu-specifier
+ data.
+
+ The property is an arbitrary number of tuples of
+ (icid-base,iommu,iommu-base,length).
+
+ Any ICID i in the interval [icid-base, icid-base + length) is
+ associated with the listed IOMMU, with the iommu-specifier
+ (i - icid-base + iommu-base).
+
+ msi-map:
+ description: |
+ Maps an ICID to a GIC ITS and associated msi-specifier
+ data.
+
+ The property is an arbitrary number of tuples of
+ (icid-base,gic-its,msi-base,length).
+
+ Any ICID in the interval [icid-base, icid-base + length) is
+ associated with the listed GIC ITS, with the msi-specifier
+ (i - icid-base + msi-base).
+
+ msi-parent:
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Describes the MSI controller node handling message
+ interrupts for the MC. When there is no translation
+ between the ICID and deviceID this property can be used
+ to describe the MSI controller used by the devices on the
+ mc-bus.
+ The use of this property for mc-bus is deprecated. Please
+ use msi-map.
+
+ dma-coherent: true
+
+ dpmacs:
+ type: object
+ description:
+ The fsl-mc node may optionally have dpmac sub-nodes that describe
+ the relationship between the Ethernet MACs which belong to the MC
+ and the Ethernet PHYs on the system board.
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ '^ethernet@[a-f0-9]+$':
+ $ref: /schemas/net/fsl,qoriq-mc-dpmac.yaml
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc";
+ reg = <0x0c000000 0x40>, /* MC portal base */
+ <0x08340000 0x40000>; /* MC control reg */
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x8 0x18000000 0x8000000>;
+
+ /* define map for ICIDs 23-64 */
+ iommu-map = <23 &smmu 23 41>;
+ /* define msi map for ICIDs 23-64 */
+ msi-map = <23 &its 23 41>;
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ dpmacs {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <1>;
+ phy-handle = <&mdio0_phy0>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/misc/qemu,vcpu-stall-detector.yaml b/dts/upstream/Bindings/misc/qemu,vcpu-stall-detector.yaml
index 1aebeb6..e12d80b 100644
--- a/dts/upstream/Bindings/misc/qemu,vcpu-stall-detector.yaml
+++ b/dts/upstream/Bindings/misc/qemu,vcpu-stall-detector.yaml
@@ -29,6 +29,9 @@
Defaults to 10 if unset.
default: 10
+ interrupts:
+ maxItems: 1
+
timeout-sec:
description: |
The stall detector expiration timeout measured in seconds.
@@ -43,9 +46,12 @@
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
vmwdt@9030000 {
compatible = "qemu,vcpu-stall-detector";
reg = <0x9030000 0x10000>;
clock-frequency = <10>;
timeout-sec = <8>;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_EDGE_RISING>;
};
diff --git a/dts/upstream/Bindings/mmc/amlogic,meson-gx-mmc.yaml b/dts/upstream/Bindings/mmc/amlogic,meson-gx-mmc.yaml
index bc403ae..5764657 100644
--- a/dts/upstream/Bindings/mmc/amlogic,meson-gx-mmc.yaml
+++ b/dts/upstream/Bindings/mmc/amlogic,meson-gx-mmc.yaml
@@ -51,6 +51,9 @@
set when controller's internal DMA engine cannot access the DRAM memory,
like on the G12A dedicated SDIO controller.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
index cbd3d6c..eee6be7 100644
--- a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
+++ b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
@@ -20,6 +20,7 @@
- const: brcm,sdhci-brcmstb
- items:
- enum:
+ - brcm,bcm2712-sdhci
- brcm,bcm74165b0-sdhci
- brcm,bcm7445-sdhci
- brcm,bcm7425-sdhci
diff --git a/dts/upstream/Bindings/mmc/fsl,esdhc.yaml b/dts/upstream/Bindings/mmc/fsl,esdhc.yaml
new file mode 100644
index 0000000..b86ffb5
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/fsl,esdhc.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Enhanced Secure Digital Host Controller (eSDHC)
+
+description:
+ The Enhanced Secure Digital Host Controller provides an interface
+ for MMC, SD, and SDIO types of memory cards.
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,mpc8536-esdhc
+ - fsl,mpc8378-esdhc
+ - fsl,p2020-esdhc
+ - fsl,p4080-esdhc
+ - fsl,t1040-esdhc
+ - fsl,t4240-esdhc
+ - fsl,ls1012a-esdhc
+ - fsl,ls1028a-esdhc
+ - fsl,ls1088a-esdhc
+ - fsl,ls1043a-esdhc
+ - fsl,ls1046a-esdhc
+ - fsl,ls2080a-esdhc
+ - const: fsl,esdhc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: specifies eSDHC base clock frequency.
+
+ sdhci,wp-inverted:
+ $ref: /schemas/types.yaml#/definitions/flag
+ deprecated: true
+ description:
+ specifies that eSDHC controller reports
+ inverted write-protect state; New devices should use the generic
+ "wp-inverted" property.
+
+ sdhci,1-bit-only:
+ $ref: /schemas/types.yaml#/definitions/flag
+ deprecated: true
+ description:
+ specifies that a controller can only handle
+ 1-bit data transfers. New devices should use the generic
+ "bus-width = <1>" property.
+
+ sdhci,auto-cmd12:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ specifies that a controller can only handle auto CMD12.
+
+ voltage-ranges:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: specifies minimum slot voltage (mV).
+ - description: specifies maximum slot voltage (mV).
+ minItems: 1
+ maxItems: 8
+
+ dma-coherent: true
+
+ little-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ If the host controller is little-endian mode, specify
+ this property. The default endian mode is big-endian.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+allOf:
+ - $ref: sdhci-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mmc@2e000 {
+ compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <42 0x8>;
+ interrupt-parent = <&ipic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <100000000>;
+ voltage-ranges = <3300 3300>;
+ };
diff --git a/dts/upstream/Bindings/mmc/fsl-esdhc.txt b/dts/upstream/Bindings/mmc/fsl-esdhc.txt
deleted file mode 100644
index edb8cad..0000000
--- a/dts/upstream/Bindings/mmc/fsl-esdhc.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Freescale Enhanced Secure Digital Host Controller (eSDHC)
-
-The Enhanced Secure Digital Host Controller provides an interface
-for MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties described
-by mmc.txt and the properties used by the sdhci-esdhc driver.
-
-Required properties:
- - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
- Possible compatibles for PowerPC:
- "fsl,mpc8536-esdhc"
- "fsl,mpc8378-esdhc"
- "fsl,p2020-esdhc"
- "fsl,p4080-esdhc"
- "fsl,t1040-esdhc"
- "fsl,t4240-esdhc"
- Possible compatibles for ARM:
- "fsl,ls1012a-esdhc"
- "fsl,ls1028a-esdhc"
- "fsl,ls1088a-esdhc"
- "fsl,ls1043a-esdhc"
- "fsl,ls1046a-esdhc"
- "fsl,ls2080a-esdhc"
- - clock-frequency : specifies eSDHC base clock frequency.
-
-Optional properties:
- - sdhci,wp-inverted : specifies that eSDHC controller reports
- inverted write-protect state; New devices should use the generic
- "wp-inverted" property.
- - sdhci,1-bit-only : specifies that a controller can only handle
- 1-bit data transfers. New devices should use the generic
- "bus-width = <1>" property.
- - sdhci,auto-cmd12: specifies that a controller can only handle auto
- CMD12.
- - voltage-ranges : two cells are required, first cell specifies minimum
- slot voltage (mV), second cell specifies maximum slot voltage (mV).
- Several ranges could be specified.
- - little-endian : If the host controller is little-endian mode, specify
- this property. The default endian mode is big-endian.
-
-Example:
-
-sdhci@2e000 {
- compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- interrupts = <42 0x8>;
- interrupt-parent = <&ipic>;
- /* Filled in by U-Boot */
- clock-frequency = <0>;
- voltage-ranges = <3300 3300>;
-};
diff --git a/dts/upstream/Bindings/mmc/mmc-spi-slot.yaml b/dts/upstream/Bindings/mmc/mmc-spi-slot.yaml
index 36acc40..6e2cdac 100644
--- a/dts/upstream/Bindings/mmc/mmc-spi-slot.yaml
+++ b/dts/upstream/Bindings/mmc/mmc-spi-slot.yaml
@@ -27,17 +27,19 @@
maxItems: 1
voltage-ranges:
- $ref: /schemas/types.yaml#/definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
Two cells are required, first cell specifies minimum slot voltage (mV),
second cell specifies maximum slot voltage (mV).
items:
- - description: |
- value for minimum slot voltage in mV
- default: 3200
- - description: |
- value for maximum slot voltage in mV
- default: 3400
+ items:
+ - description: |
+ value for minimum slot voltage in mV
+ default: 3200
+ - description: |
+ value for maximum slot voltage in mV
+ default: 3400
+ maxItems: 1
gpios:
description: |
diff --git a/dts/upstream/Bindings/mmc/sdhci-msm.yaml b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
index c24c537..11979b0 100644
--- a/dts/upstream/Bindings/mmc/sdhci-msm.yaml
+++ b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
@@ -51,6 +51,7 @@
- qcom,sdm845-sdhci
- qcom,sdx55-sdhci
- qcom,sdx65-sdhci
+ - qcom,sdx75-sdhci
- qcom,sm6115-sdhci
- qcom,sm6125-sdhci
- qcom,sm6350-sdhci
diff --git a/dts/upstream/Bindings/mmc/sdhci-sprd.txt b/dts/upstream/Bindings/mmc/sdhci-sprd.txt
deleted file mode 100644
index eb7eb1b..0000000
--- a/dts/upstream/Bindings/mmc/sdhci-sprd.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Spreadtrum SDHCI controller (sdhci-sprd)
-
-The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
-for MMC, SD and SDIO types of cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-sprd driver.
-
-Required properties:
-- compatible: Should contain "sprd,sdhci-r11".
-- reg: physical base address of the controller and length.
-- interrupts: Interrupts used by the SDHCI controller.
-- clocks: Should contain phandle for the clock feeding the SDHCI controller
-- clock-names: Should contain the following:
- "sdio" - SDIO source clock (required)
- "enable" - gate clock which used for enabling/disabling the device (required)
- "2x_enable" - gate clock controlling the device for some special platforms (optional)
-
-Optional properties:
-- assigned-clocks: the same with "sdio" clock
-- assigned-clock-parents: the default parent of "sdio" clock
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin control
-- pinctrl-1: should contain uhs mode pin control
-
-PHY DLL delays are used to delay the data valid window, and align the window
-to sampling clock. PHY DLL delays can be configured by following properties,
-and each property contains 4 cells which are used to configure the clock data
-write line delay value, clock read command line delay value, clock read data
-positive edge delay value and clock read data negative edge delay value.
-Each cell's delay value unit is cycle of the PHY clock.
-
-- sprd,phy-delay-legacy: Delay value for legacy timing.
-- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
-- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
-- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
-- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
-- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
-- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
-- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
-- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
-
-Examples:
-
-sdio0: sdio@20600000 {
- compatible = "sprd,sdhci-r11";
- reg = <0 0x20600000 0 0x1000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-
- clock-names = "sdio", "enable";
- clocks = <&ap_clk CLK_EMMC_2X>,
- <&apahb_gate CLK_EMMC_EB>;
- assigned-clocks = <&ap_clk CLK_EMMC_2X>;
- assigned-clock-parents = <&rpll CLK_RPLL_390M>;
-
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sd0_pins_default>;
- pinctrl-1 = <&sd0_pins_uhs>;
-
- sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
- bus-width = <8>;
- non-removable;
- no-sdio;
- no-sd;
- cap-mmc-hw-reset;
- status = "okay";
-};
diff --git a/dts/upstream/Bindings/mmc/sprd,sdhci-r11.yaml b/dts/upstream/Bindings/mmc/sprd,sdhci-r11.yaml
new file mode 100644
index 0000000..b08081b
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/sprd,sdhci-r11.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SDHCI controller
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ const: sprd,sdhci-r11
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ items:
+ - description: SDIO source clock
+ - description: gate clock for enabling/disabling the device
+ - description: gate clock controlling the device for some special platforms (optional)
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: sdio
+ - const: enable
+ - const: 2x_enable
+
+ pinctrl-0:
+ description: default/high speed pin control
+ maxItems: 1
+
+ pinctrl-1:
+ description: UHS mode pin control
+ maxItems: 1
+
+ pinctrl-names:
+ minItems: 1
+ items:
+ - const: default
+ - const: state_uhs
+
+patternProperties:
+ "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: clock data write line delay value
+ - description: clock read command line delay value
+ - description: clock read data positive edge delay value
+ - description: clock read data negative edge delay value
+ description:
+ PHY DLL delays are used to delay the data valid window, and align
+ the window to the sampling clock. Each cell's delay value unit is
+ cycle of the PHY clock.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: sdhci-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sprd,sc9860-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mmc@50430000 {
+ compatible = "sprd,sdhci-r11";
+ reg = <0x50430000 0x1000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&aon_prediv CLK_EMMC_2X>,
+ <&apahb_gate CLK_EMMC_EB>,
+ <&aon_gate CLK_EMMC_2X_EN>;
+ clock-names = "sdio", "enable", "2x_enable";
+
+ pinctrl-0 = <&sd0_pins_default>;
+ pinctrl-1 = <&sd0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ mmc-hs400-enhanced-strobe;
+ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+
+ sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
+ sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;
+ sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;
+ sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;
+ };
+...
diff --git a/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml b/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml
index 57b6957..284f0f8 100644
--- a/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml
+++ b/dts/upstream/Bindings/mtd/amlogic,meson-nand.yaml
@@ -64,11 +64,29 @@
items:
maximum: 0
+ amlogic,boot-pages:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of pages starting from offset 0, where a special ECC
+ configuration must be used because it is accessed by the ROM
+ code. This ECC configuration uses 384 bytes data blocks.
+ Also scrambling mode is enabled for such pages.
+
+ amlogic,boot-page-step:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Interval between pages, accessed by the ROM code. For example
+ we have 8 pages [0, 7]. Pages 0,2,4,6 are accessed by the
+ ROM code, so this field will be 2 (e.g. every 2nd page). Rest
+ of pages - 1,3,5,7 are read/written without this mode.
+
unevaluatedProperties: false
dependencies:
nand-ecc-strength: [nand-ecc-step-size]
nand-ecc-step-size: [nand-ecc-strength]
+ amlogic,boot-pages: [nand-is-boot-medium, "amlogic,boot-page-step"]
+ amlogic,boot-page-step: [nand-is-boot-medium, "amlogic,boot-pages"]
required:
diff --git a/dts/upstream/Bindings/mtd/atmel-nand.txt b/dts/upstream/Bindings/mtd/atmel-nand.txt
index 4598930..e36c35b 100644
--- a/dts/upstream/Bindings/mtd/atmel-nand.txt
+++ b/dts/upstream/Bindings/mtd/atmel-nand.txt
@@ -60,15 +60,6 @@
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
block, and the second one to the PMECC_ERRLOC block.
-* SAMA5 NFC I/O bindings:
-
-SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
-operations. This interface to this logic is placed in a separate I/O range and
-should thus have its own DT node.
-
-- compatible: should be "atmel,sama5d3-nfc-io", "syscon".
-- reg: should contain the I/O range used to interact with the NFC logic.
-
Example:
nfc_io: nfc-io@70000000 {
diff --git a/dts/upstream/Bindings/mtd/gpmi-nand.yaml b/dts/upstream/Bindings/mtd/gpmi-nand.yaml
index 021c0da..f9eb186 100644
--- a/dts/upstream/Bindings/mtd/gpmi-nand.yaml
+++ b/dts/upstream/Bindings/mtd/gpmi-nand.yaml
@@ -24,6 +24,7 @@
- fsl,imx6q-gpmi-nand
- fsl,imx6sx-gpmi-nand
- fsl,imx7d-gpmi-nand
+ - fsl,imx8qxp-gpmi-nand
- items:
- enum:
- fsl,imx8mm-gpmi-nand
@@ -151,6 +152,27 @@
- const: gpmi_io
- const: gpmi_bch_apb
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ - description: SoC gpmi apb clock
+ - description: SoC gpmi bch clock
+ - description: SoC gpmi bch apb clock
+ clock-names:
+ items:
+ - const: gpmi_io
+ - const: gpmi_apb
+ - const: gpmi_bch
+ - const: gpmi_bch_apb
+
examples:
- |
nand-controller@8000c000 {
diff --git a/dts/upstream/Bindings/mtd/qcom,nandc.yaml b/dts/upstream/Bindings/mtd/qcom,nandc.yaml
index 4ada60f..35b4206 100644
--- a/dts/upstream/Bindings/mtd/qcom,nandc.yaml
+++ b/dts/upstream/Bindings/mtd/qcom,nandc.yaml
@@ -31,6 +31,18 @@
- const: core
- const: aon
+ qcom,cmd-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM command type CRCI block instance number specified for
+ the NAND controller on the given platform
+
+ qcom,data-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM data type CRCI block instance number specified for
+ the NAND controller on the given platform
+
patternProperties:
"^nand@[a-f0-9]$":
type: object
@@ -83,18 +95,6 @@
items:
- const: rxtx
- qcom,cmd-crci:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Must contain the ADM command type CRCI block instance number
- specified for the NAND controller on the given platform
-
- qcom,data-crci:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Must contain the ADM data type CRCI block instance number
- specified for the NAND controller on the given platform
-
- if:
properties:
compatible:
@@ -119,19 +119,9 @@
- const: rx
- const: cmd
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq806x-nand
+ qcom,cmd-crci: false
+ qcom,data-crci: false
- then:
- patternProperties:
- "^nand@[a-f0-9]$":
- properties:
- qcom,boot-partitions: true
- else:
patternProperties:
"^nand@[a-f0-9]$":
properties:
diff --git a/dts/upstream/Bindings/net/airoha,en7581-eth.yaml b/dts/upstream/Bindings/net/airoha,en7581-eth.yaml
new file mode 100644
index 0000000..c578637
--- /dev/null
+++ b/dts/upstream/Bindings/net/airoha,en7581-eth.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Frame Engine Ethernet controller
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ The frame engine ethernet controller can be found on Airoha SoCs.
+ These SoCs have multi-GMAC ports.
+
+properties:
+ compatible:
+ enum:
+ - airoha,en7581-eth
+
+ reg:
+ items:
+ - description: Frame engine base address
+ - description: QDMA0 base address
+ - description: QDMA1 base address
+
+ reg-names:
+ items:
+ - const: fe
+ - const: qdma0
+ - const: qdma1
+
+ interrupts:
+ items:
+ - description: QDMA lan irq0
+ - description: QDMA lan irq1
+ - description: QDMA lan irq2
+ - description: QDMA lan irq3
+ - description: QDMA wan irq0
+ - description: QDMA wan irq1
+ - description: QDMA wan irq2
+ - description: QDMA wan irq3
+ - description: FE error irq
+ - description: PDMA irq
+
+ resets:
+ maxItems: 8
+
+ reset-names:
+ items:
+ - const: fe
+ - const: pdma
+ - const: qdma
+ - const: xsi-mac
+ - const: hsi0-mac
+ - const: hsi1-mac
+ - const: hsi-mac
+ - const: xfp-mac
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^ethernet@[1-4]$":
+ type: object
+ unevaluatedProperties: false
+ $ref: ethernet-controller.yaml#
+ description:
+ Ethernet GMAC port associated to the MAC controller
+ properties:
+ compatible:
+ const: airoha,eth-mac
+
+ reg:
+ minimum: 1
+ maximum: 4
+ description: GMAC port identifier
+
+ required:
+ - reg
+ - compatible
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/en7523-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ eth: ethernet@1fb50000 {
+ compatible = "airoha,en7581-eth";
+ reg = <0 0x1fb50000 0 0x2600>,
+ <0 0x1fb54000 0 0x2000>,
+ <0 0x1fb56000 0 0x2000>;
+ reg-names = "fe", "qdma0", "qdma1";
+
+ resets = <&scuclk 44>,
+ <&scuclk 30>,
+ <&scuclk 31>,
+ <&scuclk 6>,
+ <&scuclk 15>,
+ <&scuclk 16>,
+ <&scuclk 17>,
+ <&scuclk 26>;
+ reset-names = "fe", "pdma", "qdma", "xsi-mac",
+ "hsi0-mac", "hsi1-mac", "hsi-mac",
+ "xfp-mac";
+
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mac: ethernet@1 {
+ compatible = "airoha,eth-mac";
+ reg = <1>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/arc_emac.txt b/dts/upstream/Bindings/net/arc_emac.txt
deleted file mode 100644
index c73a0e9..0000000
--- a/dts/upstream/Bindings/net/arc_emac.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Synopsys ARC EMAC 10/100 Ethernet driver (EMAC)
-
-Required properties:
-- compatible: Should be "snps,arc-emac"
-- reg: Address and length of the register set for the device
-- interrupts: Should contain the EMAC interrupts
-- max-speed: see ethernet.txt file in the same directory.
-- phy: see ethernet.txt file in the same directory.
-
-Optional properties:
-- phy-reset-gpios : Should specify the gpio for phy reset
-- phy-reset-duration : Reset duration in milliseconds. Should present
- only if property "phy-reset-gpios" is available. Missing the property
- will have the duration be 1 millisecond. Numbers greater than 1000 are
- invalid and 1 millisecond will be used instead.
-
-Clock handling:
-The clock frequency is needed to calculate and set polling period of EMAC.
-It must be provided by one of:
-- clock-frequency: CPU frequency.
-- clocks: reference to the clock supplying the EMAC.
-
-Child nodes of the driver are the individual PHY devices connected to the
-MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
-
-Examples:
-
- ethernet@c0fc2000 {
- compatible = "snps,arc-emac";
- reg = <0xc0fc2000 0x3c>;
- interrupts = <6>;
- mac-address = [ 00 11 22 33 44 55 ];
-
- clock-frequency = <80000000>;
- /* or */
- clocks = <&emac_clock>;
-
- max-speed = <100>;
- phy = <&phy0>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- phy0: ethernet-phy@0 {
- reg = <1>;
- };
- };
diff --git a/dts/upstream/Bindings/net/bluetooth/mediatek,mt7622-bluetooth.yaml b/dts/upstream/Bindings/net/bluetooth/mediatek,mt7622-bluetooth.yaml
new file mode 100644
index 0000000..3f9e692
--- /dev/null
+++ b/dts/upstream/Bindings/net/bluetooth/mediatek,mt7622-bluetooth.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/bluetooth/mediatek,mt7622-bluetooth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek SoC built-in Bluetooth
+
+description:
+ This device is a serial attached device to BTIF device and thus it must be a
+ child node of the serial node with BTIF. The dt-bindings details for BTIF
+ device can be known via Documentation/devicetree/bindings/serial/8250.yaml.
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+allOf:
+ - $ref: bluetooth-controller.yaml#
+
+properties:
+ compatible:
+ const: mediatek,mt7622-bluetooth
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ref
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - clocks
+ - clock-names
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/mt7622-power.h>
+
+ serial {
+ bluetooth {
+ compatible = "mediatek,mt7622-bluetooth";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
+ clocks = <&clk25m>;
+ clock-names = "ref";
+ };
+ };
diff --git a/dts/upstream/Bindings/net/bluetooth/nxp,88w8987-bt.yaml b/dts/upstream/Bindings/net/bluetooth/nxp,88w8987-bt.yaml
index f01a398..37a65ba 100644
--- a/dts/upstream/Bindings/net/bluetooth/nxp,88w8987-bt.yaml
+++ b/dts/upstream/Bindings/net/bluetooth/nxp,88w8987-bt.yaml
@@ -31,6 +31,9 @@
This property depends on the module vendor's
configuration.
+ firmware-name:
+ maxItems: 1
+
required:
- compatible
@@ -42,5 +45,6 @@
bluetooth {
compatible = "nxp,88w8987-bt";
fw-init-baudrate = <3000000>;
+ firmware-name = "uartuart8987_bt_v0.bin";
};
};
diff --git a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
index 055a335..68c5ed1 100644
--- a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
+++ b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
@@ -62,6 +62,9 @@
vdddig-supply:
description: VDD_DIG supply regulator handle
+ vddbtcmx-supply:
+ description: VDD_BT_CMX supply regulator handle
+
vddbtcxmx-supply:
description: VDD_BT_CXMX supply regulator handle
@@ -74,6 +77,9 @@
vddrfa1p7-supply:
description: VDD_RFA_1P7 supply regulator handle
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
vddrfa1p2-supply:
description: VDD_RFA_1P2 supply regulator handle
@@ -86,6 +92,12 @@
vddasd-supply:
description: VDD_ASD supply regulator handle
+ vddwlcx-supply:
+ description: VDD_WLCX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WLMX supply regulator handle
+
max-speed:
description: see Documentation/devicetree/bindings/serial/serial.yaml
@@ -176,14 +188,27 @@
- qcom,wcn7850-bt
then:
required:
- - enable-gpios
- - swctrl-gpios
- - vddio-supply
+ - vddrfacmn-supply
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qca6390-bt
+ then:
+ required:
+ - vddrfacmn-supply
- vddaon-supply
- - vdddig-supply
+ - vddbtcmx-supply
- vddrfa0p8-supply
- vddrfa1p2-supply
- - vddrfa1p9-supply
+ - vddrfa1p7-supply
examples:
- |
diff --git a/dts/upstream/Bindings/net/can/xilinx,can.yaml b/dts/upstream/Bindings/net/can/xilinx,can.yaml
index 8d4e5af..4083549 100644
--- a/dts/upstream/Bindings/net/can/xilinx,can.yaml
+++ b/dts/upstream/Bindings/net/can/xilinx,can.yaml
@@ -5,7 +5,7 @@
$schema: http://devicetree.org/meta-schemas/core.yaml#
title:
- Xilinx Axi CAN/Zynq CANPS controller
+ Xilinx CAN and CANFD controller
maintainers:
- Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
diff --git a/dts/upstream/Bindings/net/cdns,macb.yaml b/dts/upstream/Bindings/net/cdns,macb.yaml
index 2c71e2c..3c30dd2 100644
--- a/dts/upstream/Bindings/net/cdns,macb.yaml
+++ b/dts/upstream/Bindings/net/cdns,macb.yaml
@@ -146,6 +146,7 @@
magic-packet:
type: boolean
+ deprecated: true
description:
Indicates that the hardware supports waking up via magic packet.
diff --git a/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml b/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml
new file mode 100644
index 0000000..f3154b1
--- /dev/null
+++ b/dts/upstream/Bindings/net/dsa/lantiq,gswip.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq GSWIP Ethernet switches
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+maintainers:
+ - Hauke Mehrtens <hauke@hauke-m.de>
+
+properties:
+ compatible:
+ enum:
+ - lantiq,xrx200-gswip
+ - lantiq,xrx300-gswip
+ - lantiq,xrx330-gswip
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: switch
+ - const: mdio
+ - const: mii
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ compatible:
+ const: lantiq,xrx200-mdio
+
+ required:
+ - compatible
+
+ gphy-fw:
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ compatible:
+ items:
+ - enum:
+ - lantiq,xrx200-gphy-fw
+ - lantiq,xrx300-gphy-fw
+ - lantiq,xrx330-gphy-fw
+ - const: lantiq,gphy-fw
+
+ lantiq,rcu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the RCU syscon
+
+ patternProperties:
+ "^gphy@[0-9a-f]{1,2}$":
+ type: object
+
+ additionalProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 255
+ description:
+ Offset of the GPHY firmware register in the RCU register range
+
+ resets:
+ items:
+ - description: GPHY reset line
+
+ reset-names:
+ items:
+ - const: gphy
+
+ required:
+ - reg
+
+ required:
+ - compatible
+ - lantiq,rcu
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ switch@e108000 {
+ compatible = "lantiq,xrx200-gswip";
+ reg = <0xe108000 0x3100>, /* switch */
+ <0xe10b100 0xd8>, /* mdio */
+ <0xe10b1d8 0x130>; /* mii */
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&phy11>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&phy13>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "wan";
+ phy-mode = "rgmii";
+ phy-handle = <&phy5>;
+ };
+
+ port@6 {
+ reg = <0x6>;
+ phy-mode = "internal";
+ ethernet = <ð0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lantiq,xrx200-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <0x13>;
+ };
+ };
+
+ gphy-fw {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
+ lantiq,rcu = <&rcu0>;
+
+ gphy@20 {
+ reg = <0x20>;
+
+ resets = <&reset0 31 30>;
+ reset-names = "gphy";
+ };
+
+ gphy@68 {
+ reg = <0x68>;
+
+ resets = <&reset0 29 28>;
+ reset-names = "gphy";
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/dsa/lantiq-gswip.txt b/dts/upstream/Bindings/net/dsa/lantiq-gswip.txt
deleted file mode 100644
index 8bb1eff..0000000
--- a/dts/upstream/Bindings/net/dsa/lantiq-gswip.txt
+++ /dev/null
@@ -1,146 +0,0 @@
-Lantiq GSWIP Ethernet switches
-==================================
-
-Required properties for GSWIP core:
-
-- compatible : "lantiq,xrx200-gswip" for the embedded GSWIP in the
- xRX200 SoC
- "lantiq,xrx300-gswip" for the embedded GSWIP in the
- xRX300 SoC
- "lantiq,xrx330-gswip" for the embedded GSWIP in the
- xRX330 SoC
-- reg : memory range of the GSWIP core registers
- : memory range of the GSWIP MDIO registers
- : memory range of the GSWIP MII registers
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
-additional required and optional properties.
-
-
-Required properties for MDIO bus:
-- compatible : "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
- core of the xRX200 SoC and the PHYs connected to it.
-
-See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
-required and optional properties.
-
-
-Required properties for GPHY firmware loading:
-- compatible : "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
- "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
- "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
- for the loading of the firmware into the embedded
- GPHY core of the SoC.
-- lantiq,rcu : reference to the rcu syscon
-
-The GPHY firmware loader has a list of GPHY entries, one for each
-embedded GPHY
-
-- reg : Offset of the GPHY firmware register in the RCU
- register range
-- resets : list of resets of the embedded GPHY
-- reset-names : list of names of the resets
-
-Example:
-
-Ethernet switch on the VRX200 SoC:
-
-switch@e108000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "lantiq,xrx200-gswip";
- reg = < 0xe108000 0x3100 /* switch */
- 0xe10b100 0xd8 /* mdio */
- 0xe10b1d8 0x130 /* mii */
- >;
- dsa,member = <0 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan3";
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy11>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy13>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "rgmii";
- phy-handle = <&phy5>;
- };
-
- port@6 {
- reg = <0x6>;
- ethernet = <ð0>;
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "lantiq,xrx200-mdio";
- reg = <0>;
-
- phy0: ethernet-phy@0 {
- reg = <0x0>;
- };
- phy1: ethernet-phy@1 {
- reg = <0x1>;
- };
- phy5: ethernet-phy@5 {
- reg = <0x5>;
- };
- phy11: ethernet-phy@11 {
- reg = <0x11>;
- };
- phy13: ethernet-phy@13 {
- reg = <0x13>;
- };
- };
-
- gphy-fw {
- compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
- lantiq,rcu = <&rcu0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gphy@20 {
- reg = <0x20>;
-
- resets = <&reset0 31 30>;
- reset-names = "gphy";
- };
-
- gphy@68 {
- reg = <0x68>;
-
- resets = <&reset0 29 28>;
- reset-names = "gphy";
- };
- };
-};
diff --git a/dts/upstream/Bindings/net/dsa/mediatek,mt7530.yaml b/dts/upstream/Bindings/net/dsa/mediatek,mt7530.yaml
index 1c24441..7e405ad 100644
--- a/dts/upstream/Bindings/net/dsa/mediatek,mt7530.yaml
+++ b/dts/upstream/Bindings/net/dsa/mediatek,mt7530.yaml
@@ -22,16 +22,16 @@
The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's
- memory map rather than using MDIO. The switch got an internally connected 10G
+ memory map rather than using MDIO. The switch has an internally connected 10G
CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.
- MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
+ The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs
and the switch registers are directly mapped into SoC's memory map rather than
using MDIO. The DSA driver currently doesn't support MT7620 variants.
There is only the standalone version of MT7531.
- Port 5 on MT7530 has got various ways of configuration:
+ Port 5 on MT7530 supports various configurations:
- Port 5 can be used as a CPU port.
diff --git a/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.txt b/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.txt
deleted file mode 100644
index 258bef4..0000000
--- a/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-Vitesse VSC73xx Switches
-========================
-
-This defines device tree bindings for the Vitesse VSC73xx switch chips.
-The Vitesse company has been acquired by Microsemi and Microsemi has
-been acquired Microchip but retains this vendor branding.
-
-The currently supported switch chips are:
-Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
-Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
-Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
-Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
-
-This switch could have two different management interface.
-
-If SPI interface is used, the device tree node is an SPI device so it must
-reside inside a SPI bus device tree node, see spi/spi-bus.txt
-
-When the chip is connected to a parallel memory bus and work in memory-mapped
-I/O mode, a platform device is used to represent the vsc73xx. In this case it
-must reside inside a platform bus device tree node.
-
-Required properties:
-
-- compatible: must be exactly one of:
- "vitesse,vsc7385"
- "vitesse,vsc7388"
- "vitesse,vsc7395"
- "vitesse,vsc7398"
-- gpio-controller: indicates that this switch is also a GPIO controller,
- see gpio/gpio.txt
-- #gpio-cells: this must be set to <2> and indicates that we are a twocell
- GPIO controller, see gpio/gpio.txt
-
-Optional properties:
-
-- reset-gpios: a handle to a GPIO line that can issue reset of the chip.
- It should be tagged as active low.
-
-Required subnodes:
-
-See net/dsa/dsa.txt for a list of additional required and optional properties
-and subnodes of DSA switches.
-
-Examples:
-
-SPI:
-switch@0 {
- compatible = "vitesse,vsc7395";
- reg = <0>;
- /* Specified for 2.5 MHz or below */
- spi-max-frequency = <2500000>;
- gpio-controller;
- #gpio-cells = <2>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
- port@1 {
- reg = <1>;
- label = "lan2";
- };
- port@2 {
- reg = <2>;
- label = "lan3";
- };
- port@3 {
- reg = <3>;
- label = "lan4";
- };
- vsc: port@6 {
- reg = <6>;
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- };
-};
-
-Platform:
-switch@2,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "vitesse,vsc7385";
- reg = <0x2 0x0 0x20000>;
- reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
- port@1 {
- reg = <1>;
- label = "lan2";
- };
- port@2 {
- reg = <2>;
- label = "lan3";
- };
- port@3 {
- reg = <3>;
- label = "lan4";
- };
- vsc: port@6 {
- reg = <6>;
- ethernet = <&enet0>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- };
-
-};
diff --git a/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml b/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml
new file mode 100644
index 0000000..b99d7a6
--- /dev/null
+++ b/dts/upstream/Bindings/net/dsa/vitesse,vsc73xx.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/vitesse,vsc73xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Vitesse VSC73xx DSA Switches
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+ The Vitesse DSA Switches were produced in the early-to-mid 2000s.
+
+ The Vitesse company has been acquired by Microsemi and Microsemi has
+ been acquired Microchip but the new owner retains this vendor branding.
+
+ The currently supported switch chips are
+ Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
+ Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
+ Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
+ Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
+
+ This switch can use one of two different management interfaces.
+
+ If SPI interface is used, the device tree node is an SPI device so it must
+ reside inside a SPI bus device tree node, see spi/spi-bus.txt
+
+ When the chip is connected to a parallel memory bus and work in memory-mapped
+ I/O mode, a platform device is used to represent the vsc73xx. In this case it
+ must reside inside a platform bus device tree node.
+
+properties:
+ compatible:
+ enum:
+ - vitesse,vsc7385
+ - vitesse,vsc7388
+ - vitesse,vsc7395
+ - vitesse,vsc7398
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+ "#gpio-cells":
+ const: 2
+
+ reset-gpios:
+ description: GPIO to be used to reset the whole device
+ maxItems: 1
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+# This checks if reg is a chipselect so the device is on an SPI
+# bus, the if-clause will fail if reg is a tuple such as for a
+# platform device.
+if:
+ properties:
+ reg:
+ minimum: 0
+ maximum: 256
+then:
+ $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@0 {
+ compatible = "vitesse,vsc7395";
+ reg = <0>;
+ spi-max-frequency = <2500000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ ethernet-port@6 {
+ reg = <6>;
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+
+ bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ethernet-switch@10000000 {
+ compatible = "vitesse,vsc7385";
+ reg = <0x10000000 0x20000>;
+ reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ ethernet-port@6 {
+ reg = <6>;
+ ethernet = <&enet0>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/ethernet-controller.yaml b/dts/upstream/Bindings/net/ethernet-controller.yaml
index b2785b0..45819b2 100644
--- a/dts/upstream/Bindings/net/ethernet-controller.yaml
+++ b/dts/upstream/Bindings/net/ethernet-controller.yaml
@@ -103,6 +103,7 @@
- usxgmii
- 10gbase-r
- 25gbase-r
+ - 10g-qxgmii
phy-mode:
$ref: "#/properties/phy-connection-type"
diff --git a/dts/upstream/Bindings/net/ethernet-phy.yaml b/dts/upstream/Bindings/net/ethernet-phy.yaml
index 8fb2a6e..d9b6274 100644
--- a/dts/upstream/Bindings/net/ethernet-phy.yaml
+++ b/dts/upstream/Bindings/net/ethernet-phy.yaml
@@ -93,6 +93,14 @@
the turn around line low at end of the control phase of the
MDIO transaction.
+ brr-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ If set, indicates the network cable interface is an alternative one as
+ defined in the BroadR-Reach link mode specification under 1BR-100 and
+ 1BR-10 names. The PHY must be configured to operate in BroadR-Reach mode
+ by software.
+
clocks:
maxItems: 1
description:
diff --git a/dts/upstream/Bindings/net/fsl,enetc-ierb.yaml b/dts/upstream/Bindings/net/fsl,enetc-ierb.yaml
new file mode 100644
index 0000000..c8a6543
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,enetc-ierb.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,enetc-ierb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Integrated Endpoint Register Block
+
+description:
+ The fsl_enetc driver can probe on the Integrated Endpoint Register Block,
+ which preconfigures the FIFO limits for the ENETC ports.
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+ - Vladimir Oltean <vladimir.oltean@nxp.com>
+ - Wei Fang <wei.fang@nxp.com>
+ - Claudiu Manoil <claudiu.manoil@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-enetc-ierb
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ endpoint-config@f0800000 {
+ compatible = "fsl,ls1028a-enetc-ierb";
+ reg = <0xf0800000 0x10000>;
+ };
diff --git a/dts/upstream/Bindings/net/fsl,enetc-mdio.yaml b/dts/upstream/Bindings/net/fsl,enetc-mdio.yaml
new file mode 100644
index 0000000..c1dd6aa
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,enetc-mdio.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,enetc-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ENETC external MDIO PCIe endpoint device
+
+description:
+ NETC provides an external master MDIO interface (EMDIO) for managing external
+ devices (PHYs). EMDIO supports both Clause 22 and 45 protocols. And the EMDIO
+ provides a means for different software modules to share a single set of MDIO
+ signals to access their PHYs.
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+ - Vladimir Oltean <vladimir.oltean@nxp.com>
+ - Wei Fang <wei.fang@nxp.com>
+ - Claudiu Manoil <claudiu.manoil@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - pci1957,ee01
+ - const: fsl,enetc-mdio
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: mdio.yaml
+ - $ref: /schemas/pci/pci-device.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pcie{
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ mdio@0,3 {
+ compatible = "pci1957,ee01", "fsl,enetc-mdio";
+ reg = <0x000300 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/fsl,enetc.yaml b/dts/upstream/Bindings/net/fsl,enetc.yaml
new file mode 100644
index 0000000..e152c93
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,enetc.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,enetc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The NIC functionality of NXP NETC
+
+description:
+ The NIC functionality in NETC is known as EtherNET Controller (ENETC). ENETC
+ supports virtualization/isolation based on PCIe Single Root IO Virtualization
+ (SR-IOV), advanced QoS with 8 traffic classes and 4 drop resilience levels,
+ and a full range of TSN standards and NIC offload capabilities
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+ - Vladimir Oltean <vladimir.oltean@nxp.com>
+ - Wei Fang <wei.fang@nxp.com>
+ - Claudiu Manoil <claudiu.manoil@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - pci1957,e100
+ - const: fsl,enetc
+
+ reg:
+ maxItems: 1
+
+ mdio:
+ $ref: mdio.yaml
+ unevaluatedProperties: false
+ description: Optional child node for ENETC instance, otherwise use NETC EMDIO.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: /schemas/pci/pci-device.yaml
+ - $ref: ethernet-controller.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pcie {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ethernet@0,0 {
+ compatible = "pci1957,e100", "fsl,enetc";
+ reg = <0x000000 0 0 0 0>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/fsl,fman-mdio.yaml b/dts/upstream/Bindings/net/fsl,fman-mdio.yaml
new file mode 100644
index 0000000..6b2c0aa
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,fman-mdio.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Frame Manager MDIO Device
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: FMan MDIO Node.
+ The MDIO is a bus to which the PHY devices are connected.
+
+properties:
+ compatible:
+ enum:
+ - fsl,fman-mdio
+ - fsl,fman-xmdio
+ - fsl,fman-memac-mdio
+ description:
+ Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
+ Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
+ Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
+ FMan v3.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: A reference to the input clock of the controller
+ from which the MDC frequency is derived.
+
+ interrupts:
+ maxItems: 1
+
+ fsl,fman-internal-mdio:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Fman has internal MDIO for internal PCS(Physical
+ Coding Sublayer) PHYs and external MDIO for external PHYs.
+ The settings and programming routines for internal/external
+ MDIO are different. Must be included for internal MDIO.
+
+ fsl,erratum-a009885:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Indicates the presence of the A009885
+ erratum describing that the contents of MDIO_DATA may
+ become corrupt unless it is read within 16 MDC cycles
+ of MDIO_CFG[BSY] being cleared, when performing an
+ MDIO read operation.
+
+ fsl,erratum-a011043:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicates the presence of the A011043 erratum
+ describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
+ set when reading internal PCS registers. MDIO reads to
+ internal PCS registers may result in having the
+ MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
+ read data (MDIO_DATA[MDIO_DATA]) is correct.
+ Software may get false read error when reading internal
+ PCS registers through MDIO. As a workaround, all internal
+ MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
+
+ For internal PHY device on internal mdio bus, a PHY node should be created.
+ See the definition of the PHY node in booting-without-of.txt for an
+ example of how to define a PHY (Internal PHY has no interrupt line).
+ - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
+ - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
+ The PCS PHY address should correspond to the value of the appropriate
+ MDEV_PORT.
+
+ little-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ IP block is little-endian mode. The default endian mode is big-endian.
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: mdio.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio@f1000 {
+ compatible = "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+ interrupts = <101 2 0 0>;
+ };
+
+ - |
+ mdio@e3120 {
+ compatible = "fsl,fman-mdio";
+ reg = <0xe3120 0xee0>;
+ fsl,fman-internal-mdio;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tbi-phy@8 {
+ reg = <0x8>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ - |
+ mdio@f1000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0xf1000 0x1000>;
+ fsl,fman-internal-mdio;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcsphy6: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+
diff --git a/dts/upstream/Bindings/net/fsl,fman-muram.yaml b/dts/upstream/Bindings/net/fsl,fman-muram.yaml
new file mode 100644
index 0000000..aa71acc
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,fman-muram.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,fman-muram.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Frame Manager MURAM Device
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ FMan Internal memory - shared between all the FMan modules.
+ It contains data structures that are common and written to or read by
+ the modules.
+
+ FMan internal memory is split into the following parts:
+ Packet buffering (Tx/Rx FIFOs)
+ Frames internal context
+
+properties:
+ compatible:
+ enum:
+ - fsl,fman-muram
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ muram@0 {
+ compatible = "fsl,fman-muram";
+ reg = <0x0 0x28000>;
+ };
diff --git a/dts/upstream/Bindings/net/fsl,fman-port.yaml b/dts/upstream/Bindings/net/fsl,fman-port.yaml
new file mode 100644
index 0000000..9de4453
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,fman-port.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Frame Manager Port Device
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ The Frame Manager (FMan) supports several types of hardware ports:
+ Ethernet receiver (RX)
+ Ethernet transmitter (TX)
+ Offline/Host command (O/H)
+
+properties:
+ compatible:
+ enum:
+ - fsl,fman-v2-port-oh
+ - fsl,fman-v2-port-rx
+ - fsl,fman-v2-port-tx
+ - fsl,fman-v3-port-oh
+ - fsl,fman-v3-port-rx
+ - fsl,fman-v3-port-tx
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Specifies the hardware port id.
+ Each hardware port on the FMan has its own hardware PortID.
+ Super set of all hardware Port IDs available at FMan Reference
+ Manual under "FMan Hardware Ports in Freescale Devices" table.
+
+ Each hardware port is assigned a 4KB, port-specific page in
+ the FMan hardware port memory region (which is part of the
+ FMan memory map). The first 4 KB in the FMan hardware ports
+ memory region is used for what are called common registers.
+ The subsequent 63 4KB pages are allocated to the hardware
+ ports.
+ The page of a specific port is determined by the cell-index.
+
+ reg:
+ items:
+ - description: There is one reg region describing the port
+ configuration registers.
+
+ fsl,fman-10g-port:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: The default port rate is 1G.
+ If this property exists, the port is s 10G port.
+
+ fsl,fman-best-effort-port:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: The default port rate is 1G.
+ Can be defined only if 10G-support is set.
+ This property marks a best-effort 10G port (10G port that
+ may not be capable of line rate).
+
+required:
+ - compatible
+ - reg
+ - cell-index
+
+additionalProperties: false
+
+examples:
+ - |
+ port@a8000 {
+ compatible = "fsl,fman-v2-port-tx";
+ reg = <0xa8000 0x1000>;
+ cell-index = <0x28>;
+ };
+
diff --git a/dts/upstream/Bindings/net/fsl,fman.yaml b/dts/upstream/Bindings/net/fsl,fman.yaml
new file mode 100644
index 0000000..9bbf39e
--- /dev/null
+++ b/dts/upstream/Bindings/net/fsl,fman.yaml
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,fman.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Frame Manager Device
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
+ etc.) the FMan node will have child nodes for each of them.
+
+properties:
+ compatible:
+ enum:
+ - fsl,fman
+ description:
+ FMan version can be determined via FM_IP_REV_1 register in the
+ FMan block. The offset is 0xc4 from the beginning of the
+ Frame Processing Manager memory map (0xc3000 from the
+ beginning of the FMan node).
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specifies the index of the FMan unit.
+
+ The cell-index value may be used by the SoC, to identify the
+ FMan unit in the SoC memory map. In the table below,
+ there's a description of the cell-index use in each SoC:
+
+ - P1023:
+ register[bit] FMan unit cell-index
+ ============================================================
+ DEVDISR[1] 1 0
+
+ - P2041, P3041, P4080 P5020, P5040:
+ register[bit] FMan unit cell-index
+ ============================================================
+ DCFG_DEVDISR2[6] 1 0
+ DCFG_DEVDISR2[14] 2 1
+ (Second FM available only in P4080 and P5040)
+
+ - B4860, T1040, T2080, T4240:
+ register[bit] FMan unit cell-index
+ ============================================================
+ DCFG_CCSR_DEVDISR2[24] 1 0
+ DCFG_CCSR_DEVDISR2[25] 2 1
+ (Second FM available only in T4240)
+
+ DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
+ the specific SoC "Device Configuration/Pin Control" Memory
+ Map.
+
+ reg:
+ items:
+ - description: BMI configuration registers.
+ - description: QMI configuration registers.
+ - description: DMA configuration registers.
+ - description: FPM configuration registers.
+ - description: FMan controller configuration registers.
+ minItems: 1
+
+ ranges: true
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: fmanclk
+
+ interrupts:
+ items:
+ - description: The first element is associated with the event interrupts.
+ - description: the second element is associated with the error interrupts.
+
+ dma-coherent: true
+
+ ptimer-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: see ptp/fsl,ptp.yaml
+
+ fsl,qman-channel-range:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ Specifies the range of the available dedicated
+ channels in the FMan. The first cell specifies the beginning
+ of the range and the second cell specifies the number of
+ channels
+ items:
+ - description: The first cell specifies the beginning of the range.
+ - description: |
+ The second cell specifies the number of channels.
+ Further information available at:
+ "Work Queue (WQ) Channel Assignments in the QMan" section
+ in DPAA Reference Manual.
+
+ fsl,qman:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: See soc/fsl/qman.txt
+
+ fsl,bman:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: See soc/fsl/bman.txt
+
+ fsl,erratum-a050385:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: A boolean property. Indicates the presence of the
+ erratum A050385 which indicates that DMA transactions that are
+ split can result in a FMan lock.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ '^muram@[a-f0-9]+$':
+ $ref: fsl,fman-muram.yaml
+
+ '^port@[a-f0-9]+$':
+ $ref: fsl,fman-port.yaml
+
+ '^ethernet@[a-f0-9]+$':
+ $ref: fsl,fman-dtsec.yaml
+
+ '^mdio@[a-f0-9]+$':
+ $ref: fsl,fman-mdio.yaml
+
+ '^phc@[a-f0-9]+$':
+ $ref: /schemas/ptp/fsl,ptp.yaml
+
+required:
+ - compatible
+ - cell-index
+ - reg
+ - ranges
+ - clocks
+ - clock-names
+ - interrupts
+ - fsl,qman-channel-range
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ fman@400000 {
+ compatible = "fsl,fman";
+ reg = <0x400000 0x100000>;
+ ranges = <0 0x400000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ clocks = <&fman_clk>;
+ clock-names = "fmanclk";
+ interrupts = <96 IRQ_TYPE_EDGE_FALLING>,
+ <16 IRQ_TYPE_EDGE_FALLING>;
+ fsl,qman-channel-range = <0x40 0xc>;
+
+ muram@0 {
+ compatible = "fsl,fman-muram";
+ reg = <0x0 0x28000>;
+ };
+
+ port@81000 {
+ cell-index = <1>;
+ compatible = "fsl,fman-v2-port-oh";
+ reg = <0x81000 0x1000>;
+ };
+
+ fman1_rx_0x8: port@88000 {
+ cell-index = <0x8>;
+ compatible = "fsl,fman-v2-port-rx";
+ reg = <0x88000 0x1000>;
+ };
+
+ fman1_tx_0x28: port@a8000 {
+ cell-index = <0x28>;
+ compatible = "fsl,fman-v2-port-tx";
+ reg = <0xa8000 0x1000>;
+ };
+
+ ethernet@e0000 {
+ compatible = "fsl,fman-dtsec";
+ cell-index = <0>;
+ reg = <0xe0000 0x1000>;
+ ptp-timer = <&ptp_timer>;
+ fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
+ tbi-handle = <&tbi5>;
+ };
+
+ ptp_timer: phc@fe000 {
+ compatible = "fsl,fman-ptp-timer";
+ reg = <0xfe000 0x1000>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ mdio@f1000 {
+ compatible = "fsl,fman-xmdio";
+ reg = <0xf1000 0x1000>;
+ interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
diff --git a/dts/upstream/Bindings/net/fsl,qoriq-mc-dpmac.yaml b/dts/upstream/Bindings/net/fsl,qoriq-mc-dpmac.yaml
index a1b71b3..42f9843 100644
--- a/dts/upstream/Bindings/net/fsl,qoriq-mc-dpmac.yaml
+++ b/dts/upstream/Bindings/net/fsl,qoriq-mc-dpmac.yaml
@@ -38,6 +38,10 @@
managed: true
+ phys:
+ description: A reference to the SerDes lane(s)
+ maxItems: 1
+
required:
- reg
diff --git a/dts/upstream/Bindings/net/fsl-enetc.txt b/dts/upstream/Bindings/net/fsl-enetc.txt
deleted file mode 100644
index 9b9a3f1..0000000
--- a/dts/upstream/Bindings/net/fsl-enetc.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-* ENETC ethernet device tree bindings
-
-Depending on board design and ENETC port type (internal or
-external) there are two supported link modes specified by
-below device tree bindings.
-
-Required properties:
-
-- reg : Specifies PCIe Device Number and Function
- Number of the ENETC endpoint device, according
- to parent node bindings.
-- compatible : Should be "fsl,enetc".
-
-1. The ENETC external port is connected to a MDIO configurable phy
-
-1.1. Using the local ENETC Port MDIO interface
-
-In this case, the ENETC node should include a "mdio" sub-node
-that in turn should contain the "ethernet-phy" node describing the
-external phy. Below properties are required, their bindings
-already defined in Documentation/devicetree/bindings/net/ethernet.txt or
-Documentation/devicetree/bindings/net/phy.txt.
-
-Required:
-
-- phy-handle : Phandle to a PHY on the MDIO bus.
- Defined in ethernet.txt.
-
-- phy-connection-type : Defined in ethernet.txt.
-
-- mdio : "mdio" node, defined in mdio.txt.
-
-- ethernet-phy : "ethernet-phy" node, defined in phy.txt.
-
-Example:
-
- ethernet@0,0 {
- compatible = "fsl,enetc";
- reg = <0x000000 0 0 0 0>;
- phy-handle = <&sgmii_phy0>;
- phy-connection-type = "sgmii";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- sgmii_phy0: ethernet-phy@2 {
- reg = <0x2>;
- };
- };
- };
-
-1.2. Using the central MDIO PCIe endpoint device
-
-In this case, the mdio node should be defined as another PCIe
-endpoint node, at the same level with the ENETC port nodes.
-
-Required properties:
-
-- reg : Specifies PCIe Device Number and Function
- Number of the ENETC endpoint device, according
- to parent node bindings.
-- compatible : Should be "fsl,enetc-mdio".
-
-The remaining required mdio bus properties are standard, their bindings
-already defined in Documentation/devicetree/bindings/net/mdio.txt.
-
-Example:
-
- ethernet@0,0 {
- compatible = "fsl,enetc";
- reg = <0x000000 0 0 0 0>;
- phy-handle = <&sgmii_phy0>;
- phy-connection-type = "sgmii";
- };
-
- mdio@0,3 {
- compatible = "fsl,enetc-mdio";
- reg = <0x000300 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- sgmii_phy0: ethernet-phy@2 {
- reg = <0x2>;
- };
- };
-
-2. The ENETC port is an internal port or has a fixed-link external
-connection
-
-In this case, the ENETC port node defines a fixed link connection,
-as specified by Documentation/devicetree/bindings/net/fixed-link.txt.
-
-Required:
-
-- fixed-link : "fixed-link" node, defined in "fixed-link.txt".
-
-Example:
- ethernet@0,2 {
- compatible = "fsl,enetc";
- reg = <0x000200 0 0 0 0>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
-* Integrated Endpoint Register Block bindings
-
-Optionally, the fsl_enetc driver can probe on the Integrated Endpoint Register
-Block, which preconfigures the FIFO limits for the ENETC ports. This is a node
-with the following properties:
-
-- reg : Specifies the address in the SoC memory space.
-- compatible : Must be "fsl,ls1028a-enetc-ierb".
-
-Example:
- ierb@1f0800000 {
- compatible = "fsl,ls1028a-enetc-ierb";
- reg = <0x01 0xf0800000 0x0 0x10000>;
- };
diff --git a/dts/upstream/Bindings/net/fsl-fman.txt b/dts/upstream/Bindings/net/fsl-fman.txt
deleted file mode 100644
index bda4b41..0000000
--- a/dts/upstream/Bindings/net/fsl-fman.txt
+++ /dev/null
@@ -1,548 +0,0 @@
-=============================================================================
-Freescale Frame Manager Device Bindings
-
-CONTENTS
- - FMan Node
- - FMan Port Node
- - FMan MURAM Node
- - FMan dTSEC/XGEC/mEMAC Node
- - FMan IEEE 1588 Node
- - FMan MDIO Node
- - Example
-
-=============================================================================
-FMan Node
-
-DESCRIPTION
-
-Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
-etc.) the FMan node will have child nodes for each of them.
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: Must include "fsl,fman"
- FMan version can be determined via FM_IP_REV_1 register in the
- FMan block. The offset is 0xc4 from the beginning of the
- Frame Processing Manager memory map (0xc3000 from the
- beginning of the FMan node).
-
-- cell-index
- Usage: required
- Value type: <u32>
- Definition: Specifies the index of the FMan unit.
-
- The cell-index value may be used by the SoC, to identify the
- FMan unit in the SoC memory map. In the table below,
- there's a description of the cell-index use in each SoC:
-
- - P1023:
- register[bit] FMan unit cell-index
- ============================================================
- DEVDISR[1] 1 0
-
- - P2041, P3041, P4080 P5020, P5040:
- register[bit] FMan unit cell-index
- ============================================================
- DCFG_DEVDISR2[6] 1 0
- DCFG_DEVDISR2[14] 2 1
- (Second FM available only in P4080 and P5040)
-
- - B4860, T1040, T2080, T4240:
- register[bit] FMan unit cell-index
- ============================================================
- DCFG_CCSR_DEVDISR2[24] 1 0
- DCFG_CCSR_DEVDISR2[25] 2 1
- (Second FM available only in T4240)
-
- DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
- the specific SoC "Device Configuration/Pin Control" Memory
- Map.
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the offset of the
- following configuration registers:
- - BMI configuration registers.
- - QMI configuration registers.
- - DMA configuration registers.
- - FPM configuration registers.
- - FMan controller configuration registers.
-
-- ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property.
-
-- clocks
- Usage: required
- Value type: <prop-encoded-array>
- Definition: phandle for the fman input clock.
-
-- clock-names
- usage: required
- Value type: <stringlist>
- Definition: "fmanclk" for the fman input clock.
-
-- interrupts
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A pair of IRQs are specified in this property.
- The first element is associated with the event interrupts and
- the second element is associated with the error interrupts.
-
-- fsl,qman-channel-range
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Specifies the range of the available dedicated
- channels in the FMan. The first cell specifies the beginning
- of the range and the second cell specifies the number of
- channels.
- Further information available at:
- "Work Queue (WQ) Channel Assignments in the QMan" section
- in DPAA Reference Manual.
-
-- fsl,qman
-- fsl,bman
- Usage: required
- Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
-
-- fsl,erratum-a050385
- Usage: optional
- Value type: boolean
- Definition: A boolean property. Indicates the presence of the
- erratum A050385 which indicates that DMA transactions that are
- split can result in a FMan lock.
-
-=============================================================================
-FMan MURAM Node
-
-DESCRIPTION
-
-FMan Internal memory - shared between all the FMan modules.
-It contains data structures that are common and written to or read by
-the modules.
-FMan internal memory is split into the following parts:
- Packet buffering (Tx/Rx FIFOs)
- Frames internal context
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: Must include "fsl,fman-muram"
-
-- ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property.
- Specifies the multi-user memory offset and the size within
- the FMan.
-
-EXAMPLE
-
-muram@0 {
- compatible = "fsl,fman-muram";
- ranges = <0 0x000000 0x28000>;
-};
-
-=============================================================================
-FMan Port Node
-
-DESCRIPTION
-
-The Frame Manager (FMan) supports several types of hardware ports:
- Ethernet receiver (RX)
- Ethernet transmitter (TX)
- Offline/Host command (O/H)
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: A standard property.
- Must include one of the following:
- - "fsl,fman-v2-port-oh" for FManV2 OH ports
- - "fsl,fman-v2-port-rx" for FManV2 RX ports
- - "fsl,fman-v2-port-tx" for FManV2 TX ports
- - "fsl,fman-v3-port-oh" for FManV3 OH ports
- - "fsl,fman-v3-port-rx" for FManV3 RX ports
- - "fsl,fman-v3-port-tx" for FManV3 TX ports
-
-- cell-index
- Usage: required
- Value type: <u32>
- Definition: Specifies the hardware port id.
- Each hardware port on the FMan has its own hardware PortID.
- Super set of all hardware Port IDs available at FMan Reference
- Manual under "FMan Hardware Ports in Freescale Devices" table.
-
- Each hardware port is assigned a 4KB, port-specific page in
- the FMan hardware port memory region (which is part of the
- FMan memory map). The first 4 KB in the FMan hardware ports
- memory region is used for what are called common registers.
- The subsequent 63 4KB pages are allocated to the hardware
- ports.
- The page of a specific port is determined by the cell-index.
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: There is one reg region describing the port
- configuration registers.
-
-- fsl,fman-10g-port
- Usage: optional
- Value type: boolean
- Definition: The default port rate is 1G.
- If this property exists, the port is s 10G port.
-
-- fsl,fman-best-effort-port
- Usage: optional
- Value type: boolean
- Definition: Can be defined only if 10G-support is set.
- This property marks a best-effort 10G port (10G port that
- may not be capable of line rate).
-
-EXAMPLE
-
-port@a8000 {
- cell-index = <0x28>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xa8000 0x1000>;
-};
-
-port@88000 {
- cell-index = <0x8>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x88000 0x1000>;
-};
-
-port@81000 {
- cell-index = <0x1>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x81000 0x1000>;
-};
-
-=============================================================================
-FMan dTSEC/XGEC/mEMAC Node
-
-Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
-
-============================================================================
-FMan IEEE 1588 Node
-
-Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
-
-=============================================================================
-FMan MDIO Node
-
-DESCRIPTION
-
-The MDIO is a bus to which the PHY devices are connected.
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: A standard property.
- Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
- Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
- Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
- FMan v3.
-
-- reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property.
-
-- clocks
- Usage: optional
- Value type: <phandle>
- Definition: A reference to the input clock of the controller
- from which the MDC frequency is derived.
-
-- clock-frequency
- Usage: optional
- Value type: <u32>
- Definition: Specifies the external MDC frequency, in Hertz, to
- be used. Requires that the input clock is specified in the
- "clocks" property. See also: mdio.yaml.
-
-- suppress-preamble
- Usage: optional
- Value type: <boolean>
- Definition: Disable generation of preamble bits. See also:
- mdio.yaml.
-
-- interrupts
- Usage: required for external MDIO
- Value type: <prop-encoded-array>
- Definition: Event interrupt of external MDIO controller.
-
-- fsl,fman-internal-mdio
- Usage: required for internal MDIO
- Value type: boolean
- Definition: Fman has internal MDIO for internal PCS(Physical
- Coding Sublayer) PHYs and external MDIO for external PHYs.
- The settings and programming routines for internal/external
- MDIO are different. Must be included for internal MDIO.
-
-- fsl,erratum-a009885
- Usage: optional
- Value type: <boolean>
- Definition: Indicates the presence of the A009885
- erratum describing that the contents of MDIO_DATA may
- become corrupt unless it is read within 16 MDC cycles
- of MDIO_CFG[BSY] being cleared, when performing an
- MDIO read operation.
-
-- fsl,erratum-a011043
- Usage: optional
- Value type: <boolean>
- Definition: Indicates the presence of the A011043 erratum
- describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
- set when reading internal PCS registers. MDIO reads to
- internal PCS registers may result in having the
- MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
- read data (MDIO_DATA[MDIO_DATA]) is correct.
- Software may get false read error when reading internal
- PCS registers through MDIO. As a workaround, all internal
- MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
-
-For internal PHY device on internal mdio bus, a PHY node should be created.
-See the definition of the PHY node in booting-without-of.txt for an
-example of how to define a PHY (Internal PHY has no interrupt line).
-- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
-- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
- The PCS PHY address should correspond to the value of the appropriate
- MDEV_PORT.
-
-EXAMPLE
-
-Example for FMan v2 external MDIO:
-
-mdio@f1000 {
- compatible = "fsl,fman-xmdio";
- reg = <0xf1000 0x1000>;
- interrupts = <101 2 0 0>;
-};
-
-Example for FMan v2 internal MDIO:
-
-mdio@e3120 {
- compatible = "fsl,fman-mdio";
- reg = <0xe3120 0xee0>;
- fsl,fman-internal-mdio;
-
- tbi1: tbi-phy@8 {
- reg = <0x8>;
- device_type = "tbi-phy";
- };
-};
-
-Example for FMan v3 internal MDIO:
-
-mdio@f1000 {
- compatible = "fsl,fman-memac-mdio";
- reg = <0xf1000 0x1000>;
- fsl,fman-internal-mdio;
-
- pcsphy6: ethernet-phy@0 {
- reg = <0x0>;
- };
-};
-
-=============================================================================
-Example
-
-fman@400000 {
- #address-cells = <1>;
- #size-cells = <1>;
- cell-index = <1>;
- compatible = "fsl,fman"
- ranges = <0 0x400000 0x100000>;
- reg = <0x400000 0x100000>;
- clocks = <&fman_clk>;
- clock-names = "fmanclk";
- interrupts = <
- 96 2 0 0
- 16 2 1 1>;
- fsl,qman-channel-range = <0x40 0xc>;
-
- muram@0 {
- compatible = "fsl,fman-muram";
- reg = <0x0 0x28000>;
- };
-
- port@81000 {
- cell-index = <1>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x81000 0x1000>;
- };
-
- port@82000 {
- cell-index = <2>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x82000 0x1000>;
- };
-
- port@83000 {
- cell-index = <3>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x83000 0x1000>;
- };
-
- port@84000 {
- cell-index = <4>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x84000 0x1000>;
- };
-
- port@85000 {
- cell-index = <5>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x85000 0x1000>;
- };
-
- port@86000 {
- cell-index = <6>;
- compatible = "fsl,fman-v2-port-oh";
- reg = <0x86000 0x1000>;
- };
-
- fman1_rx_0x8: port@88000 {
- cell-index = <0x8>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x88000 0x1000>;
- };
-
- fman1_rx_0x9: port@89000 {
- cell-index = <0x9>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x89000 0x1000>;
- };
-
- fman1_rx_0xa: port@8a000 {
- cell-index = <0xa>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x8a000 0x1000>;
- };
-
- fman1_rx_0xb: port@8b000 {
- cell-index = <0xb>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x8b000 0x1000>;
- };
-
- fman1_rx_0xc: port@8c000 {
- cell-index = <0xc>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x8c000 0x1000>;
- };
-
- fman1_rx_0x10: port@90000 {
- cell-index = <0x10>;
- compatible = "fsl,fman-v2-port-rx";
- reg = <0x90000 0x1000>;
- };
-
- fman1_tx_0x28: port@a8000 {
- cell-index = <0x28>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xa8000 0x1000>;
- };
-
- fman1_tx_0x29: port@a9000 {
- cell-index = <0x29>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xa9000 0x1000>;
- };
-
- fman1_tx_0x2a: port@aa000 {
- cell-index = <0x2a>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xaa000 0x1000>;
- };
-
- fman1_tx_0x2b: port@ab000 {
- cell-index = <0x2b>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xab000 0x1000>;
- };
-
- fman1_tx_0x2c: port@ac0000 {
- cell-index = <0x2c>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xac000 0x1000>;
- };
-
- fman1_tx_0x30: port@b0000 {
- cell-index = <0x30>;
- compatible = "fsl,fman-v2-port-tx";
- reg = <0xb0000 0x1000>;
- };
-
- ethernet@e0000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <0>;
- reg = <0xe0000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
- tbi-handle = <&tbi5>;
- };
-
- ethernet@e2000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <1>;
- reg = <0xe2000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
- tbi-handle = <&tbi6>;
- };
-
- ethernet@e4000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <2>;
- reg = <0xe4000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
- tbi-handle = <&tbi7>;
- };
-
- ethernet@e6000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <3>;
- reg = <0xe6000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
- tbi-handle = <&tbi8>;
- };
-
- ethernet@e8000 {
- compatible = "fsl,fman-dtsec";
- cell-index = <4>;
- reg = <0xf0000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
- tbi-handle = <&tbi9>;
-
- ethernet@f0000 {
- cell-index = <8>;
- compatible = "fsl,fman-xgec";
- reg = <0xf0000 0x1000>;
- fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
- };
-
- ptp-timer@fe000 {
- compatible = "fsl,fman-ptp-timer";
- reg = <0xfe000 0x1000>;
- };
-
- mdio@f1000 {
- compatible = "fsl,fman-xmdio";
- reg = <0xf1000 0x1000>;
- interrupts = <101 2 0 0>;
- };
-};
diff --git a/dts/upstream/Bindings/net/fsl-tsec-phy.txt b/dts/upstream/Bindings/net/fsl-tsec-phy.txt
index 047bdf7..9c9668c 100644
--- a/dts/upstream/Bindings/net/fsl-tsec-phy.txt
+++ b/dts/upstream/Bindings/net/fsl-tsec-phy.txt
@@ -86,4 +86,4 @@
* Gianfar PTP clock nodes
-Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
+Refer to Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
diff --git a/dts/upstream/Bindings/net/hisilicon-hip04-net.txt b/dts/upstream/Bindings/net/hisilicon-hip04-net.txt
index 464c0da..c09eec6 100644
--- a/dts/upstream/Bindings/net/hisilicon-hip04-net.txt
+++ b/dts/upstream/Bindings/net/hisilicon-hip04-net.txt
@@ -19,16 +19,6 @@
[1] Documentation/devicetree/bindings/net/ethernet.txt
-* Ethernet ppe node:
-Control rx & tx fifos of all ethernet controllers.
-Have 2048 recv channels shared by all ethernet controllers, only if no overlap.
-Each controller's recv channel start from channel * number (RX_DESC_NUM).
-
-Required properties:
-- compatible: "hisilicon,hip04-ppe", "syscon".
-- reg: address and length of the register set for the device.
-
-
* MDIO bus node:
Required properties:
diff --git a/dts/upstream/Bindings/net/mediatek,net.yaml b/dts/upstream/Bindings/net/mediatek,net.yaml
index 3202dc7..686b5c2 100644
--- a/dts/upstream/Bindings/net/mediatek,net.yaml
+++ b/dts/upstream/Bindings/net/mediatek,net.yaml
@@ -68,6 +68,17 @@
Phandle to the syscon node that handles the path from GMAC to
PHY variants.
+ mediatek,pcie-mirror:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the mediatek pcie-mirror controller.
+
+ mediatek,pctl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon node that handles the ports slew rate and
+ driver current.
+
mediatek,sgmiisys:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
@@ -131,15 +142,12 @@
mediatek,infracfg: false
- mediatek,pctl:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- Phandle to the syscon node that handles the ports slew rate and
- driver current.
-
mediatek,wed: false
mediatek,wed-pcie: false
+ else:
+ properties:
+ mediatek,pctl: false
- if:
properties:
@@ -201,12 +209,10 @@
minItems: 1
maxItems: 1
- mediatek,pcie-mirror:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
- Phandle to the mediatek pcie-mirror controller.
-
mediatek,wed-pcie: false
+ else:
+ properties:
+ mediatek,pcie-mirror: false
- if:
properties:
diff --git a/dts/upstream/Bindings/net/mediatek-bluetooth.txt b/dts/upstream/Bindings/net/mediatek-bluetooth.txt
index 9ef5bac..988c726 100644
--- a/dts/upstream/Bindings/net/mediatek-bluetooth.txt
+++ b/dts/upstream/Bindings/net/mediatek-bluetooth.txt
@@ -1,39 +1,3 @@
-MediaTek SoC built-in Bluetooth Devices
-==================================
-
-This device is a serial attached device to BTIF device and thus it must be a
-child node of the serial node with BTIF. The dt-bindings details for BTIF
-device can be known via Documentation/devicetree/bindings/serial/8250.yaml.
-
-Required properties:
-
-- compatible: Must be
- "mediatek,mt7622-bluetooth": for MT7622 SoC
-- clocks: Should be the clock specifiers corresponding to the entry in
- clock-names property.
-- clock-names: Should contain "ref" entries.
-- power-domains: Phandle to the power domain that the device is part of
-
-Example:
-
- btif: serial@1100c000 {
- compatible = "mediatek,mt7622-btif",
- "mediatek,mtk-btif";
- reg = <0 0x1100c000 0 0x1000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_BTIF_PD>;
- clock-names = "main";
- reg-shift = <2>;
- reg-io-width = <4>;
-
- bluetooth {
- compatible = "mediatek,mt7622-bluetooth";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
- clocks = <&clk25m>;
- clock-names = "ref";
- };
- };
-
MediaTek UART based Bluetooth Devices
==================================
diff --git a/dts/upstream/Bindings/net/mscc,miim.yaml b/dts/upstream/Bindings/net/mscc,miim.yaml
index 5b292e7..792f26b 100644
--- a/dts/upstream/Bindings/net/mscc,miim.yaml
+++ b/dts/upstream/Bindings/net/mscc,miim.yaml
@@ -38,6 +38,16 @@
clock-frequency: true
+ resets:
+ items:
+ - description:
+ Reset shared with all blocks attached to the Switch Core Register
+ Bus (CSR) including VRAP slave.
+
+ reset-names:
+ items:
+ - const: switch
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/net/nxp,tja11xx.yaml b/dts/upstream/Bindings/net/nxp,tja11xx.yaml
index 85bfa45..a754a61 100644
--- a/dts/upstream/Bindings/net/nxp,tja11xx.yaml
+++ b/dts/upstream/Bindings/net/nxp,tja11xx.yaml
@@ -14,8 +14,53 @@
description:
Bindings for NXP TJA11xx automotive PHYs
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-id0180.dc40
+ - ethernet-phy-id0180.dc41
+ - ethernet-phy-id0180.dc48
+ - ethernet-phy-id0180.dd00
+ - ethernet-phy-id0180.dd01
+ - ethernet-phy-id0180.dd02
+ - ethernet-phy-id0180.dc80
+ - ethernet-phy-id0180.dc82
+ - ethernet-phy-id001b.b010
+ - ethernet-phy-id001b.b013
+ - ethernet-phy-id001b.b030
+ - ethernet-phy-id001b.b031
+
allOf:
- $ref: ethernet-phy.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id0180.dc40
+ - ethernet-phy-id0180.dc41
+ - ethernet-phy-id0180.dc48
+ - ethernet-phy-id0180.dd00
+ - ethernet-phy-id0180.dd01
+ - ethernet-phy-id0180.dd02
+
+ then:
+ properties:
+ nxp,rmii-refclk-in:
+ type: boolean
+ description: |
+ The REF_CLK is provided for both transmitted and received data
+ in RMII mode. This clock signal is provided by the PHY and is
+ typically derived from an external 25MHz crystal. Alternatively,
+ a 50MHz clock signal generated by an external oscillator can be
+ connected to pin REF_CLK. A third option is to connect a 25MHz
+ clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
+ as input or output according to the actual circuit connection.
+ If present, indicates that the REF_CLK will be configured as
+ interface reference clock input when RMII mode enabled.
+ If not present, the REF_CLK will be configured as interface
+ reference clock output when RMII mode enabled.
+ Only supported on TJA1100 and TJA1101.
patternProperties:
"^ethernet-phy@[0-9a-f]+$":
@@ -32,22 +77,6 @@
description:
The ID number for the child PHY. Should be +1 of parent PHY.
- nxp,rmii-refclk-in:
- type: boolean
- description: |
- The REF_CLK is provided for both transmitted and received data
- in RMII mode. This clock signal is provided by the PHY and is
- typically derived from an external 25MHz crystal. Alternatively,
- a 50MHz clock signal generated by an external oscillator can be
- connected to pin REF_CLK. A third option is to connect a 25MHz
- clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
- as input or output according to the actual circuit connection.
- If present, indicates that the REF_CLK will be configured as
- interface reference clock input when RMII mode enabled.
- If not present, the REF_CLK will be configured as interface
- reference clock output when RMII mode enabled.
- Only supported on TJA1100 and TJA1101.
-
required:
- reg
@@ -60,6 +89,7 @@
#size-cells = <0>;
tja1101_phy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-id0180.dc40";
reg = <0x4>;
nxp,rmii-refclk-in;
};
diff --git a/dts/upstream/Bindings/net/pcs/snps,dw-xpcs.yaml b/dts/upstream/Bindings/net/pcs/snps,dw-xpcs.yaml
new file mode 100644
index 0000000..e77eec9
--- /dev/null
+++ b/dts/upstream/Bindings/net/pcs/snps,dw-xpcs.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare Ethernet PCS
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description:
+ Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface
+ between Media Access Control and Physical Medium Attachment Sublayer through
+ the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
+ controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
+ optionally synthesized with a vendor-specific interface connected to
+ Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
+ general it can be used to communicate with any compatible PHY.
+
+ The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
+ by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped
+ right to the system IO memory space.
+
+properties:
+ compatible:
+ oneOf:
+ - description: Synopsys DesignWare XPCS with none or unknown PMA
+ const: snps,dw-xpcs
+ - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
+ const: snps,dw-xpcs-gen1-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA
+ const: snps,dw-xpcs-gen2-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA
+ const: snps,dw-xpcs-gen2-6g
+ - description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA
+ const: snps,dw-xpcs-gen4-3g
+ - description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA
+ const: snps,dw-xpcs-gen4-6g
+ - description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA
+ const: snps,dw-xpcs-gen5-10g
+ - description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA
+ const: snps,dw-xpcs-gen5-12g
+
+ reg:
+ items:
+ - description:
+ In case of the MDIO management interface this just a 5-bits ID
+ of the MDIO bus device. If DW XPCS CSRs space is accessed over the
+ MCI or APB3 management interfaces, then the space mapping can be
+ either 'direct' or 'indirect'. In the former case all Clause 45
+ registers are contiguously mapped within the address space
+ MMD '[20:16]', Reg '[15:0]'. In the later case the space is divided
+ to the multiple 256 register sets. There is a special viewport CSR
+ which is responsible for the set selection. The upper part of
+ the CSR address MMD+REG[20:8] is supposed to be written in there
+ so the corresponding subset would be mapped to the lowest 255 CSRs.
+
+ reg-names:
+ items:
+ - enum: [ direct, indirect ]
+
+ reg-io-width:
+ description:
+ The way the CSRs are mapped to the memory is platform depended. Since
+ each Clause 45 CSR is of 16-bits wide the access instructions must be
+ two bytes aligned at least.
+ default: 2
+ enum: [ 2, 4 ]
+
+ interrupts:
+ description:
+ System interface interrupt output (sbd_intr_o) indicating Clause 73/37
+ auto-negotiation events':' Page received, AN is completed or incompatible
+ link partner.
+ maxItems: 1
+
+ clocks:
+ description:
+ The MCI and APB3 interfaces are supposed to be equipped with a clock
+ source connected to the clk_csr_i line.
+
+ PCS/PMA layer can be clocked by an internal reference clock source
+ (phyN_core_refclk) or by an externally connected (phyN_pad_refclk) clock
+ generator. Both clocks can be supplied at a time.
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ oneOf:
+ - minItems: 1
+ items: # MDIO
+ - enum: [core, pad]
+ - const: pad
+ - minItems: 1
+ items: # MCI or APB
+ - const: csr
+ - enum: [core, pad]
+ - const: pad
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ ethernet-pcs@1f05d000 {
+ compatible = "snps,dw-xpcs";
+ reg = <0x1f05d000 0x1000>;
+ reg-names = "indirect";
+
+ reg-io-width = <4>;
+
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&ccu_pclk>, <&ccu_core>, <&ccu_pad>;
+ clock-names = "csr", "core", "pad";
+ };
+ - |
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-pcs@0 {
+ compatible = "snps,dw-xpcs";
+ reg = <0>;
+
+ clocks = <&ccu_core>, <&ccu_pad>;
+ clock-names = "core", "pad";
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/net/realtek,rtl82xx.yaml b/dts/upstream/Bindings/net/realtek,rtl82xx.yaml
index bb94a23..d248a08 100644
--- a/dts/upstream/Bindings/net/realtek,rtl82xx.yaml
+++ b/dts/upstream/Bindings/net/realtek,rtl82xx.yaml
@@ -14,10 +14,32 @@
description:
Bindings for Realtek RTL82xx PHYs
-allOf:
- - $ref: ethernet-phy.yaml#
-
properties:
+ compatible:
+ enum:
+ - ethernet-phy-id001c.c800
+ - ethernet-phy-id001c.c816
+ - ethernet-phy-id001c.c838
+ - ethernet-phy-id001c.c840
+ - ethernet-phy-id001c.c848
+ - ethernet-phy-id001c.c849
+ - ethernet-phy-id001c.c84a
+ - ethernet-phy-id001c.c862
+ - ethernet-phy-id001c.c878
+ - ethernet-phy-id001c.c880
+ - ethernet-phy-id001c.c910
+ - ethernet-phy-id001c.c912
+ - ethernet-phy-id001c.c913
+ - ethernet-phy-id001c.c914
+ - ethernet-phy-id001c.c915
+ - ethernet-phy-id001c.c916
+ - ethernet-phy-id001c.c942
+ - ethernet-phy-id001c.c961
+ - ethernet-phy-id001c.cad0
+ - ethernet-phy-id001c.cb00
+
+ leds: true
+
realtek,clkout-disable:
type: boolean
description:
@@ -31,6 +53,18 @@
unevaluatedProperties: false
+allOf:
+ - $ref: ethernet-phy.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: ethernet-phy-id001c.c916
+ then:
+ properties:
+ leds: false
+
examples:
- |
mdio {
diff --git a/dts/upstream/Bindings/net/snps,dwmac.yaml b/dts/upstream/Bindings/net/snps,dwmac.yaml
index 21cc27e..3eb65e6 100644
--- a/dts/upstream/Bindings/net/snps,dwmac.yaml
+++ b/dts/upstream/Bindings/net/snps,dwmac.yaml
@@ -76,6 +76,7 @@
- rockchip,rk3128-gmac
- rockchip,rk3228-gmac
- rockchip,rk3288-gmac
+ - rockchip,rk3308-gmac
- rockchip,rk3328-gmac
- rockchip,rk3366-gmac
- rockchip,rk3368-gmac
@@ -435,6 +436,32 @@
description:
Use Address-Aligned Beats
+ snps,pbl:
+ description:
+ Programmable Burst Length (tx and rx)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 16, 32]
+
+ snps,txpbl:
+ description:
+ Tx Programmable Burst Length. If set, DMA tx will use this
+ value rather than snps,pbl.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 16, 32]
+
+ snps,rxpbl:
+ description:
+ Rx Programmable Burst Length. If set, DMA rx will use this
+ value rather than snps,pbl.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8, 16, 32]
+
+ snps,no-pbl-x8:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
+ rev < 3.50, don\'t multiply the values by 4.
+
snps,fixed-burst:
$ref: /schemas/types.yaml#/definitions/flag
description:
@@ -485,6 +512,12 @@
description:
Frequency division factor for MDC clock.
+ snps,tso:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enables the TSO feature otherwise it will be managed by MAC HW capability
+ register.
+
mdio:
$ref: mdio.yaml#
unevaluatedProperties: false
@@ -568,95 +601,38 @@
- if:
properties:
compatible:
- contains:
- enum:
- - allwinner,sun7i-a20-gmac
- - allwinner,sun8i-a83t-emac
- - allwinner,sun8i-h3-emac
- - allwinner,sun8i-r40-gmac
- - allwinner,sun8i-v3s-emac
- - allwinner,sun50i-a64-emac
- - ingenic,jz4775-mac
- - ingenic,x1000-mac
- - ingenic,x1600-mac
- - ingenic,x1830-mac
- - ingenic,x2000-mac
- - qcom,sa8775p-ethqos
- - qcom,sc8280xp-ethqos
- - snps,dwmac-3.50a
- - snps,dwmac-4.10a
- - snps,dwmac-4.20a
- - snps,dwmac-5.20
- - snps,dwxgmac
- - snps,dwxgmac-2.10
- - st,spear600-gmac
-
- then:
- properties:
- snps,pbl:
- description:
- Programmable Burst Length (tx and rx)
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4, 8, 16, 32]
-
- snps,txpbl:
- description:
- Tx Programmable Burst Length. If set, DMA tx will use this
- value rather than snps,pbl.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4, 8, 16, 32]
-
- snps,rxpbl:
- description:
- Rx Programmable Burst Length. If set, DMA rx will use this
- value rather than snps,pbl.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 4, 8, 16, 32]
-
- snps,no-pbl-x8:
- $ref: /schemas/types.yaml#/definitions/flag
- description:
- Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
- rev < 3.50, don\'t multiply the values by 4.
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - allwinner,sun7i-a20-gmac
- - allwinner,sun8i-a83t-emac
- - allwinner,sun8i-h3-emac
- - allwinner,sun8i-r40-gmac
- - allwinner,sun8i-v3s-emac
- - allwinner,sun50i-a64-emac
- - loongson,ls2k-dwmac
- - loongson,ls7a-dwmac
- - ingenic,jz4775-mac
- - ingenic,x1000-mac
- - ingenic,x1600-mac
- - ingenic,x1830-mac
- - ingenic,x2000-mac
- - qcom,qcs404-ethqos
- - qcom,sa8775p-ethqos
- - qcom,sc8280xp-ethqos
- - qcom,sm8150-ethqos
- - snps,dwmac-4.00
- - snps,dwmac-4.10a
- - snps,dwmac-4.20a
- - snps,dwmac-5.10a
- - snps,dwmac-5.20
- - snps,dwxgmac
- - snps,dwxgmac-2.10
- - st,spear600-gmac
+ not:
+ contains:
+ enum:
+ - allwinner,sun7i-a20-gmac
+ - allwinner,sun8i-a83t-emac
+ - allwinner,sun8i-h3-emac
+ - allwinner,sun8i-r40-gmac
+ - allwinner,sun8i-v3s-emac
+ - allwinner,sun50i-a64-emac
+ - loongson,ls2k-dwmac
+ - loongson,ls7a-dwmac
+ - ingenic,jz4775-mac
+ - ingenic,x1000-mac
+ - ingenic,x1600-mac
+ - ingenic,x1830-mac
+ - ingenic,x2000-mac
+ - qcom,qcs404-ethqos
+ - qcom,sa8775p-ethqos
+ - qcom,sc8280xp-ethqos
+ - qcom,sm8150-ethqos
+ - snps,dwmac-4.00
+ - snps,dwmac-4.10a
+ - snps,dwmac-4.20a
+ - snps,dwmac-5.10a
+ - snps,dwmac-5.20
+ - snps,dwxgmac
+ - snps,dwxgmac-2.10
+ - st,spear600-gmac
then:
properties:
- snps,tso:
- $ref: /schemas/types.yaml#/definitions/flag
- description:
- Enables the TSO feature otherwise it will be managed by
- MAC HW capability register.
+ snps,tso: false
additionalProperties: true
diff --git a/dts/upstream/Bindings/net/stm32-dwmac.yaml b/dts/upstream/Bindings/net/stm32-dwmac.yaml
index 7ccf756..bf23838 100644
--- a/dts/upstream/Bindings/net/stm32-dwmac.yaml
+++ b/dts/upstream/Bindings/net/stm32-dwmac.yaml
@@ -22,18 +22,22 @@
enum:
- st,stm32-dwmac
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
+ - st,stm32mp25-dwmac
required:
- compatible
-allOf:
- - $ref: snps,dwmac.yaml#
-
properties:
compatible:
oneOf:
- items:
- enum:
+ - st,stm32mp25-dwmac
+ - const: snps,dwmac-5.20
+ - items:
+ - enum:
- st,stm32mp1-dwmac
+ - st,stm32mp13-dwmac
- const: snps,dwmac-4.20a
- items:
- enum:
@@ -75,12 +79,15 @@
st,syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - items:
+ - minItems: 2
+ items:
- description: phandle to the syscon node which encompases the glue register
- description: offset of the control register
+ - description: field to set mask in register
description:
Should be phandle/offset pair. The phandle to the syscon node which
- encompases the glue register, and the offset of the control register
+ encompases the glue register, the offset of the control register and
+ the mask to set bitfield in control register
st,ext-phyclk:
description:
@@ -112,12 +119,40 @@
unevaluatedProperties: false
+allOf:
+ - $ref: snps,dwmac.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32-dwmac
+ - st,stm32mp1-dwmac
+ - st,stm32mp25-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp13-dwmac
+ then:
+ properties:
+ st,syscon:
+ items:
+ minItems: 3
+ maxItems: 3
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
- #include <dt-bindings/reset/stm32mp1-resets.h>
- #include <dt-bindings/mfd/stm32h7-rcc.h>
//Example 1
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
diff --git a/dts/upstream/Bindings/net/ti,icss-iep.yaml b/dts/upstream/Bindings/net/ti,icss-iep.yaml
index f5c22d6..e36e3a6 100644
--- a/dts/upstream/Bindings/net/ti,icss-iep.yaml
+++ b/dts/upstream/Bindings/net/ti,icss-iep.yaml
@@ -28,6 +28,15 @@
maxItems: 1
description: phandle to the IEP source clock
+ interrupts:
+ maxItems: 1
+ description:
+ Interrupt specifier for capture/compare IRQ.
+
+ interrupt-names:
+ items:
+ - const: iep_cap_cmp
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/net/ti,icssg-prueth.yaml b/dts/upstream/Bindings/net/ti,icssg-prueth.yaml
index e253fa7..c296e57 100644
--- a/dts/upstream/Bindings/net/ti,icssg-prueth.yaml
+++ b/dts/upstream/Bindings/net/ti,icssg-prueth.yaml
@@ -55,6 +55,14 @@
description:
phandle to MII_RT module's syscon regmap
+ ti,pa-stats:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to PA_STATS module's syscon regmap. PA_STATS is a set of
+ registers where different statistics related to ICSSG, are dumped by
+ ICSSG firmware. PA_STATS module's syscon regmap will help the device to
+ access/read/write those statistics.
+
ti,iep:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 2
@@ -194,6 +202,7 @@
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ti,mii-g-rt = <&icssg2_mii_g_rt>;
+ ti,pa-stats = <&icssg2_pa_stats>;
ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
interrupt-parent = <&icssg2_intc>;
interrupts = <24 0 2>, <25 1 3>;
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
index 5c4498b..070c4c9 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
@@ -128,6 +128,11 @@
Whether to skip executing an SCM call that reassigns the memory
region ownership.
+ qcom,no-msa-ready-indicator:
+ type: boolean
+ description:
+ Don't wait for MSA_READY indicator to complete init.
+
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: State bits used by the AP to signal the WLAN Q6.
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
index 41d0237..8675d7d 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
@@ -17,6 +17,7 @@
properties:
compatible:
enum:
+ - pci17cb,1101 # QCA6390
- pci17cb,1103 # WCN6855
reg:
@@ -28,10 +29,55 @@
string to uniquely identify variant of the calibration data for designs
with colliding bus and device ids
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WL_CX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WL_MX supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+
+ vddpcie0p9-supply:
+ description: VDD_PCIE_0P9 supply regulator handle
+
+ vddpcie1p8-supply:
+ description: VDD_PCIE_1P8 supply regulator handle
+
required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: pci17cb,1101
+ then:
+ required:
+ - vddrfacmn-supply
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p7-supply
+ - vddpcie0p9-supply
+ - vddpcie1p8-supply
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
index a2d55bf..ff5763d 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
@@ -265,15 +265,6 @@
examples:
- |
-
- q6v5_wcss: remoteproc@cd00000 {
- compatible = "qcom,ipq8074-wcss-pil";
- reg = <0xcd00000 0x4040>,
- <0x4ab000 0x20>;
- reg-names = "qdsp6",
- "rmb";
- };
-
wifi0: wifi@c000000 {
compatible = "qcom,ipq8074-wifi";
reg = <0xc000000 0x2000000>;
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
new file mode 100644
index 0000000..1b58840
--- /dev/null
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 Linaro Limited
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies ath12k wireless devices (PCIe)
+
+maintainers:
+ - Jeff Johnson <quic_jjohnson@quicinc.com>
+ - Kalle Valo <kvalo@kernel.org>
+
+description:
+ Qualcomm Technologies IEEE 802.11be PCIe devices.
+
+properties:
+ compatible:
+ enum:
+ - pci17cb,1107 # WCN7850
+
+ reg:
+ maxItems: 1
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WLCX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WLMX supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
+ vddpcie0p9-supply:
+ description: VDD_PCIE_0P9 supply regulator handle
+
+ vddpcie1p8-supply:
+ description: VDD_PCIE_1P8 supply regulator handle
+
+required:
+ - compatible
+ - reg
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfacmn-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+ - vddpcie0p9-supply
+ - vddpcie1p8-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ pcie {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bus-range = <0x01 0xff>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/xlnx,gmii-to-rgmii.yaml b/dts/upstream/Bindings/net/xlnx,gmii-to-rgmii.yaml
index 0f781da..eb803dd 100644
--- a/dts/upstream/Bindings/net/xlnx,gmii-to-rgmii.yaml
+++ b/dts/upstream/Bindings/net/xlnx,gmii-to-rgmii.yaml
@@ -31,6 +31,10 @@
phy-handle:
$ref: ethernet-controller.yaml#/properties/phy-handle
+ clocks:
+ items:
+ - description: 200/375 MHz free-running clock is used as input clock.
+
required:
- compatible
- reg
@@ -51,5 +55,6 @@
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <8>;
phy-handle = <&phy>;
+ clocks = <&dummy>;
};
};
diff --git a/dts/upstream/Bindings/nvmem/amlogic,meson-gxbb-efuse.yaml b/dts/upstream/Bindings/nvmem/amlogic,meson-gxbb-efuse.yaml
index 9801fe6..99ddc9a 100644
--- a/dts/upstream/Bindings/nvmem/amlogic,meson-gxbb-efuse.yaml
+++ b/dts/upstream/Bindings/nvmem/amlogic,meson-gxbb-efuse.yaml
@@ -28,6 +28,9 @@
description: phandle to the secure-monitor node
$ref: /schemas/types.yaml#/definitions/phandle
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- clocks
diff --git a/dts/upstream/Bindings/nvmem/imx-iim.yaml b/dts/upstream/Bindings/nvmem/imx-iim.yaml
index e9d9d8d..bb37d72 100644
--- a/dts/upstream/Bindings/nvmem/imx-iim.yaml
+++ b/dts/upstream/Bindings/nvmem/imx-iim.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX IC Identification Module (IIM)
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
description: |
This binding represents the IC Identification Module (IIM) found on
diff --git a/dts/upstream/Bindings/nvmem/imx-ocotp.yaml b/dts/upstream/Bindings/nvmem/imx-ocotp.yaml
index be13144..e21c06e 100644
--- a/dts/upstream/Bindings/nvmem/imx-ocotp.yaml
+++ b/dts/upstream/Bindings/nvmem/imx-ocotp.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX On-Chip OTP Controller (OCOTP)
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
description: |
This binding represents the on-chip eFuse OTP controller found on
diff --git a/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml b/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml
index cf5f9e2..32b8c1e 100644
--- a/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml
+++ b/dts/upstream/Bindings/nvmem/mediatek,efuse.yaml
@@ -28,7 +28,9 @@
- enum:
- mediatek,mt7622-efuse
- mediatek,mt7623-efuse
+ - mediatek,mt7981-efuse
- mediatek,mt7986-efuse
+ - mediatek,mt7988-efuse
- mediatek,mt8173-efuse
- mediatek,mt8183-efuse
- mediatek,mt8186-efuse
diff --git a/dts/upstream/Bindings/nvmem/mxs-ocotp.yaml b/dts/upstream/Bindings/nvmem/mxs-ocotp.yaml
index d9287be..95121dd 100644
--- a/dts/upstream/Bindings/nvmem/mxs-ocotp.yaml
+++ b/dts/upstream/Bindings/nvmem/mxs-ocotp.yaml
@@ -7,7 +7,9 @@
title: On-Chip OTP Memory for Freescale i.MX23/i.MX28
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: nvmem.yaml#
diff --git a/dts/upstream/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/dts/upstream/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml
index 917c40d..1cbe44a 100644
--- a/dts/upstream/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml
+++ b/dts/upstream/Bindings/nvmem/xlnx,zynqmp-nvmem.yaml
@@ -28,7 +28,7 @@
examples:
- |
- nvmem {
+ soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
nvmem-layout {
compatible = "fixed-layout";
diff --git a/dts/upstream/Bindings/pci/host-generic-pci.yaml b/dts/upstream/Bindings/pci/host-generic-pci.yaml
index 3484e0b..bcfbaf5 100644
--- a/dts/upstream/Bindings/pci/host-generic-pci.yaml
+++ b/dts/upstream/Bindings/pci/host-generic-pci.yaml
@@ -110,6 +110,12 @@
iommu-map-mask: true
msi-parent: true
+ ats-supported:
+ description:
+ Indicates that a PCIe host controller supports ATS, and can handle Memory
+ Requests with Address Type (AT).
+ type: boolean
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/pci/mediatek,mt7621-pcie.yaml b/dts/upstream/Bindings/pci/mediatek,mt7621-pcie.yaml
index 6fba421..c416088 100644
--- a/dts/upstream/Bindings/pci/mediatek,mt7621-pcie.yaml
+++ b/dts/upstream/Bindings/pci/mediatek,mt7621-pcie.yaml
@@ -13,6 +13,35 @@
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
+ MT7621 PCIe HOST Topology
+
+ .-------.
+ | |
+ | CPU |
+ | |
+ '-------'
+ |
+ |
+ |
+ v
+ .------------------.
+ .-----------| HOST/PCI Bridge |------------.
+ | '------------------' | Type1
+ BUS0 | | | Access
+ v v v On Bus0
+ .-------------. .-------------. .-------------.
+ | VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
+ | BUS0 | | BUS0 | | BUS0 |
+ | DEV0 | | DEV1 | | DEV2 |
+ '-------------' '-------------' '-------------'
+ Type0 | Type0 | Type0 |
+ Access BUS1 | Access BUS2| Access BUS3|
+ On Bus1 v On Bus2 v On Bus3 v
+ .----------. .----------. .----------.
+ | Device 0 | | Device 0 | | Device 0 |
+ | Func 0 | | Func 0 | | Func 0 |
+ '----------' '----------' '----------'
+
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
diff --git a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
index 5d7aec5..612633b 100644
--- a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
+++ b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
@@ -10,21 +10,13 @@
- Daire McNamara <daire.mcnamara@microchip.com>
allOf:
- - $ref: /schemas/pci/pci-host-bridge.yaml#
+ - $ref: plda,xpressrich3-axi-common.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
const: microchip,pcie-host-1.0 # PolarFire
- reg:
- maxItems: 2
-
- reg-names:
- items:
- - const: cfg
- - const: apb
-
clocks:
description:
Fabric Interface Controllers, FICs, are the interface between the FPGA
@@ -52,18 +44,6 @@
items:
pattern: '^fic[0-3]$'
- interrupts:
- minItems: 1
- items:
- - description: PCIe host controller
- - description: builtin MSI controller
-
- interrupt-names:
- minItems: 1
- items:
- - const: pcie
- - const: msi
-
ranges:
minItems: 1
maxItems: 3
@@ -72,39 +52,6 @@
minItems: 1
maxItems: 6
- msi-controller:
- description: Identifies the node as an MSI controller.
-
- msi-parent:
- description: MSI controller the device is capable of using.
-
- interrupt-controller:
- type: object
- properties:
- '#address-cells':
- const: 0
-
- '#interrupt-cells':
- const: 1
-
- interrupt-controller: true
-
- required:
- - '#address-cells'
- - '#interrupt-cells'
- - interrupt-controller
-
- additionalProperties: false
-
-required:
- - reg
- - reg-names
- - "#interrupt-cells"
- - interrupts
- - interrupt-map-mask
- - interrupt-map
- - msi-controller
-
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml b/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml
new file mode 100644
index 0000000..7a57a80
--- /dev/null
+++ b/dts/upstream/Bindings/pci/plda,xpressrich3-axi-common.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PLDA XpressRICH PCIe host common properties
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+ - Kevin Xie <kevin.xie@starfivetech.com>
+
+description:
+ Generic PLDA XpressRICH PCIe host common properties.
+
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+
+properties:
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: cfg
+ - const: apb
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: PCIe host controller
+ - description: builtin MSI controller
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: pcie
+ - const: msi
+
+ msi-controller:
+ description: Identifies the node as an MSI controller.
+
+ msi-parent:
+ description: MSI controller the device is capable of using.
+
+ interrupt-controller:
+ type: object
+ properties:
+ '#address-cells':
+ const: 0
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ required:
+ - '#address-cells'
+ - '#interrupt-cells'
+ - interrupt-controller
+
+ additionalProperties: false
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - msi-controller
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml b/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml
index a223ce0..46802f7 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@
compatible:
oneOf:
- enum:
+ - qcom,sa8775p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
@@ -20,6 +21,7 @@
- const: qcom,sdx55-pcie-ep
reg:
+ minItems: 6
items:
- description: Qualcomm-specific PARF configuration registers
- description: DesignWare PCIe registers
@@ -27,8 +29,10 @@
- description: Address Translation Unit (ATU) registers
- description: Memory region used to map remote RC address space
- description: BAR memory region
+ - description: DMA register space
reg-names:
+ minItems: 6
items:
- const: parf
- const: dbi
@@ -36,13 +40,14 @@
- const: atu
- const: addr_space
- const: mmio
+ - const: dma
clocks:
- minItems: 7
+ minItems: 5
maxItems: 8
clock-names:
- minItems: 7
+ minItems: 5
maxItems: 8
qcom,perst-regs:
@@ -57,14 +62,18 @@
- description: Perst separation enable offset
interrupts:
+ minItems: 2
items:
- description: PCIe Global interrupt
- description: PCIe Doorbell interrupt
+ - description: DMA interrupt
interrupt-names:
+ minItems: 2
items:
- const: global
- const: doorbell
+ - const: dma
reset-gpios:
description: GPIO used as PERST# input signal
@@ -125,6 +134,10 @@
- qcom,sdx55-pcie-ep
then:
properties:
+ reg:
+ maxItems: 6
+ reg-names:
+ maxItems: 6
clocks:
items:
- description: PCIe Auxiliary clock
@@ -143,6 +156,10 @@
- const: slave_q2a
- const: sleep
- const: ref
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
- if:
properties:
@@ -152,6 +169,10 @@
- qcom,sm8450-pcie-ep
then:
properties:
+ reg:
+ maxItems: 6
+ reg-names:
+ maxItems: 6
clocks:
items:
- description: PCIe Auxiliary clock
@@ -172,6 +193,45 @@
- const: ref
- const: ddrss_sf_tbu
- const: aggre_noc_axi
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-pcie-ep
+ then:
+ properties:
+ reg:
+ minItems: 7
+ maxItems: 7
+ reg-names:
+ minItems: 7
+ maxItems: 7
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml
index 1496d69..d8c0afa 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8450.yaml
@@ -69,6 +69,10 @@
- const: msi6
- const: msi7
+ operating-points-v2: true
+ opp-table:
+ type: object
+
resets:
maxItems: 1
diff --git a/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml b/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml
index 1074310..a9db0a2 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie-x1e80100.yaml
@@ -19,11 +19,10 @@
const: qcom,pcie-x1e80100
reg:
- minItems: 5
+ minItems: 6
maxItems: 6
reg-names:
- minItems: 5
items:
- const: parf # Qualcomm specific registers
- const: dbi # DesignWare PCIe registers
diff --git a/dts/upstream/Bindings/pci/rockchip-dw-pcie-common.yaml b/dts/upstream/Bindings/pci/rockchip-dw-pcie-common.yaml
new file mode 100644
index 0000000..cc9adfc
--- /dev/null
+++ b/dts/upstream/Bindings/pci/rockchip-dw-pcie-common.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
+
+maintainers:
+ - Shawn Lin <shawn.lin@rock-chips.com>
+ - Simon Xue <xxm@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |+
+ Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
+ SoCs.
+
+properties:
+ clocks:
+ minItems: 5
+ items:
+ - description: AHB clock for PCIe master
+ - description: AHB clock for PCIe slave
+ - description: AHB clock for PCIe dbi
+ - description: APB clock for PCIe
+ - description: Auxiliary clock for PCIe
+ - description: PIPE clock
+ - description: Reference clock for PCIe
+
+ clock-names:
+ minItems: 5
+ items:
+ - const: aclk_mst
+ - const: aclk_slv
+ - const: aclk_dbi
+ - const: pclk
+ - const: aux
+ - const: pipe
+ - const: ref
+
+ interrupts:
+ minItems: 5
+ items:
+ - description:
+ Combined system interrupt, which is used to signal the following
+ interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
+ hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
+ edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
+ - description:
+ Combined PM interrupt, which is used to signal the following
+ interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
+ linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
+ linkst_out_l0s, pm_dstate_update
+ - description:
+ Combined message interrupt, which is used to signal the following
+ interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
+ pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
+ - description:
+ Combined legacy interrupt, which is used to signal the following
+ interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
+ tx_intd
+ - description:
+ Combined error interrupt, which is used to signal the following
+ interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
+ tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
+ nf_err_rx, f_err_rx, radm_qoverflow
+ - description:
+ eDMA write channel 0 interrupt
+ - description:
+ eDMA write channel 1 interrupt
+ - description:
+ eDMA read channel 0 interrupt
+ - description:
+ eDMA read channel 1 interrupt
+
+ interrupt-names:
+ minItems: 5
+ items:
+ - const: sys
+ - const: pmc
+ - const: msg
+ - const: legacy
+ - const: err
+ - const: dma0
+ - const: dma1
+ - const: dma2
+ - const: dma3
+
+ num-lanes: true
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie-phy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ oneOf:
+ - const: pipe
+ - items:
+ - const: pwr
+ - const: pipe
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - num-lanes
+ - phys
+ - phy-names
+ - power-domains
+ - resets
+ - reset-names
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/pci/rockchip-dw-pcie-ep.yaml b/dts/upstream/Bindings/pci/rockchip-dw-pcie-ep.yaml
new file mode 100644
index 0000000..f2d1137
--- /dev/null
+++ b/dts/upstream/Bindings/pci/rockchip-dw-pcie-ep.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
+
+maintainers:
+ - Niklas Cassel <cassel@kernel.org>
+
+description: |+
+ RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ snps,dw-pcie-ep.yaml.
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-pcie-ep
+ - rockchip,rk3588-pcie-ep
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers
+ - description: Data Bus Interface (DBI) shadow registers
+ - description: Rockchip designed configuration registers
+ - description: Memory region used to map remote RC address space
+ - description: Internal Address Translation Unit (iATU) registers
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: apb
+ - const: addr_space
+ - const: atu
+
+required:
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie3x4_ep: pcie-ep@fe150000 {
+ compatible = "rockchip,rk3588-pcie-ep";
+ reg = <0xa 0x40000000 0x0 0x00100000>,
+ <0xa 0x40100000 0x0 0x00100000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x9 0x00000000 0x0 0x40000000>,
+ <0xa 0x40300000 0x0 0x00100000>;
+ reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+ "dma0", "dma1", "dma2", "dma3";
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
index 5f71921..550d8a6 100644
--- a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
+++ b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: DesignWare based PCIe controller on Rockchip SoCs
+title: DesignWare based PCIe Root Complex controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
@@ -12,12 +12,13 @@
- Heiko Stuebner <heiko@sntech.de>
description: |+
- RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
+ RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
snps,dw-pcie.yaml.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
properties:
compatible:
@@ -40,61 +41,6 @@
- const: apb
- const: config
- clocks:
- minItems: 5
- items:
- - description: AHB clock for PCIe master
- - description: AHB clock for PCIe slave
- - description: AHB clock for PCIe dbi
- - description: APB clock for PCIe
- - description: Auxiliary clock for PCIe
- - description: PIPE clock
- - description: Reference clock for PCIe
-
- clock-names:
- minItems: 5
- items:
- - const: aclk_mst
- - const: aclk_slv
- - const: aclk_dbi
- - const: pclk
- - const: aux
- - const: pipe
- - const: ref
-
- interrupts:
- items:
- - description:
- Combined system interrupt, which is used to signal the following
- interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
- hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
- edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
- - description:
- Combined PM interrupt, which is used to signal the following
- interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
- linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
- linkst_out_l0s, pm_dstate_update
- - description:
- Combined message interrupt, which is used to signal the following
- interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
- pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- - description:
- Combined legacy interrupt, which is used to signal the following
- interrupts - inta, intb, intc, intd
- - description:
- Combined error interrupt, which is used to signal the following
- interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
- tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
- nf_err_rx, f_err_rx, radm_qoverflow
-
- interrupt-names:
- items:
- - const: sys
- - const: pmc
- - const: msg
- - const: legacy
- - const: err
-
legacy-interrupt-controller:
description: Interrupt controller node for handling legacy PCI interrupts.
type: object
@@ -119,47 +65,14 @@
msi-map: true
- num-lanes: true
-
- phys:
- maxItems: 1
-
- phy-names:
- const: pcie-phy
-
- power-domains:
- maxItems: 1
-
ranges:
minItems: 2
maxItems: 3
- resets:
- minItems: 1
- maxItems: 2
-
- reset-names:
- oneOf:
- - const: pipe
- - items:
- - const: pwr
- - const: pipe
-
vpcie3v3-supply: true
required:
- - compatible
- - reg
- - reg-names
- - clocks
- - clock-names
- msi-map
- - num-lanes
- - phys
- - phy-names
- - power-domains
- - resets
- - reset-names
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/pci/snps,dw-pcie-ep.yaml b/dts/upstream/Bindings/pci/snps,dw-pcie-ep.yaml
index bbdb01d..f474b9e 100644
--- a/dts/upstream/Bindings/pci/snps,dw-pcie-ep.yaml
+++ b/dts/upstream/Bindings/pci/snps,dw-pcie-ep.yaml
@@ -100,7 +100,7 @@
for new bindings.
oneOf:
- description: See native 'elbi/app' CSR region for details.
- enum: [ link, appl ]
+ enum: [ apb, link, appl ]
- description: See native 'atu' CSR region for details.
enum: [ atu_dma ]
allOf:
@@ -152,11 +152,20 @@
events basis.
const: app
- description:
+ Interrupts triggered when the controller itself (in Endpoint mode)
+ has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to
+ the upstream device.
+ pattern: "^tx_int(a|b|c|d)$"
+ - description:
+ Combined interrupt signal raised when the controller has sent an
+ Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details.
+ const: legacy
+ - description:
Vendor-specific IRQ names. Consider using the generic names above
for new bindings.
oneOf:
- description: See native "app" IRQ for details
- enum: [ intr ]
+ enum: [ intr, sys, pmc, msg, err ]
max-functions:
maximum: 32
diff --git a/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml b/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml
new file mode 100644
index 0000000..67151aa
--- /dev/null
+++ b/dts/upstream/Bindings/pci/starfive,jh7110-pcie.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PCIe host controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+
+allOf:
+ - $ref: plda,xpressrich3-axi-common.yaml#
+
+properties:
+ compatible:
+ const: starfive,jh7110-pcie
+
+ clocks:
+ items:
+ - description: NOC bus clock
+ - description: Transport layer clock
+ - description: AXI MST0 clock
+ - description: APB clock
+
+ clock-names:
+ items:
+ - const: noc
+ - const: tl
+ - const: axi_mst0
+ - const: apb
+
+ resets:
+ items:
+ - description: AXI MST0 reset
+ - description: AXI SLAVE0 reset
+ - description: AXI SLAVE reset
+ - description: PCIE BRIDGE reset
+ - description: PCIE CORE reset
+ - description: PCIE APB reset
+
+ reset-names:
+ items:
+ - const: mst0
+ - const: slv0
+ - const: slv
+ - const: brg
+ - const: core
+ - const: apb
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ The phandle to System Register Controller syscon node.
+
+ perst-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ phys:
+ description:
+ Specified PHY is attached to PCIe controller.
+ maxItems: 1
+
+required:
+ - clocks
+ - resets
+ - starfive,stg-syscon
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@940000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x9 0x40000000 0x0 0x10000000>,
+ <0x0 0x2b000000 0x0 0x1000000>;
+ reg-names = "cfg", "apb";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ starfive,stg-syscon = <&stg_syscon>;
+ bus-range = <0x0 0xff>;
+ interrupt-parent = <&plic>;
+ interrupts = <56>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+ msi-controller;
+ clocks = <&syscrg 86>,
+ <&stgcrg 10>,
+ <&stgcrg 8>,
+ <&stgcrg 9>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ resets = <&stgcrg 11>,
+ <&stgcrg 12>,
+ <&stgcrg 13>,
+ <&stgcrg 14>,
+ <&stgcrg 15>,
+ <&stgcrg 16>;
+ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
+ phys = <&pciephy0>;
+
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
index 4770ce0..989fb0f 100644
--- a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
+++ b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
@@ -92,7 +92,7 @@
<0 0 0 3 &pcie_intc_0 2>,
<0 0 0 4 &pcie_intc_0 3>;
bus-range = <0x00 0xff>;
- ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
+ ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
msi-map = <0x0 &its_gic 0x0 0x10000>;
reg = <0x0 0xfca10000 0x0 0x1000>,
diff --git a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
index 6c96a42..37e8b98 100644
--- a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
+++ b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
@@ -30,6 +30,9 @@
- items:
- const: fsl,imx8dxl-ddr-pmu
- const: fsl,imx8-ddr-pmu
+ - items:
+ - const: fsl,imx95-ddr-pmu
+ - const: fsl,imx93-ddr-pmu
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/phy/airoha,en7581-pcie-phy.yaml b/dts/upstream/Bindings/phy/airoha,en7581-pcie-phy.yaml
new file mode 100644
index 0000000..98fcb1b
--- /dev/null
+++ b/dts/upstream/Bindings/phy/airoha,en7581-pcie-phy.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 PCI-Express PHY
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
+
+properties:
+ compatible:
+ const: airoha,en7581-pcie-phy
+
+ reg:
+ items:
+ - description: PCIE analog base address
+ - description: PCIE lane0 base address
+ - description: PCIE lane1 base address
+ - description: PCIE lane0 detection time base address
+ - description: PCIE lane1 detection time base address
+ - description: PCIE Rx AEQ base address
+
+ reg-names:
+ items:
+ - const: csr-2l
+ - const: pma0
+ - const: pma1
+ - const: p0-xr-dtime
+ - const: p1-xr-dtime
+ - const: rx-aeq
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@11e80000 {
+ compatible = "airoha,en7581-pcie-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x1fa5a000 0x0 0xfff>,
+ <0x0 0x1fa5b000 0x0 0xfff>,
+ <0x0 0x1fa5c000 0x0 0xfff>,
+ <0x0 0x1fc10044 0x0 0x4>,
+ <0x0 0x1fc30044 0x0 0x4>,
+ <0x0 0x1fc15030 0x0 0x104>;
+ reg-names = "csr-2l", "pma0", "pma1",
+ "p0-xr-dtime", "p1-xr-dtime",
+ "rx-aeq";
+ };
+ };
diff --git a/dts/upstream/Bindings/phy/amlogic,g12a-usb2-phy.yaml b/dts/upstream/Bindings/phy/amlogic,g12a-usb2-phy.yaml
index 0031fb6..1a0c436 100644
--- a/dts/upstream/Bindings/phy/amlogic,g12a-usb2-phy.yaml
+++ b/dts/upstream/Bindings/phy/amlogic,g12a-usb2-phy.yaml
@@ -41,6 +41,9 @@
Phandle to a regulator that provides power to the PHY. This
regulator will be managed during the PHY power on/off sequence.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/phy/fsl,imx8qm-hsio.yaml b/dts/upstream/Bindings/phy/fsl,imx8qm-hsio.yaml
new file mode 100644
index 0000000..147bbfd
--- /dev/null
+++ b/dts/upstream/Bindings/phy/fsl,imx8qm-hsio.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
+
+maintainers:
+ - Richard Zhu <hongxing.zhu@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-hsio
+ - fsl,imx8qxp-hsio
+ reg:
+ items:
+ - description: Base address and length of the PHY block
+ - description: HSIO control and status registers(CSR) of the PHY
+ - description: HSIO CSR of the controller bound to the PHY
+ - description: HSIO CSR for MISC
+
+ reg-names:
+ items:
+ - const: reg
+ - const: phy
+ - const: ctrl
+ - const: misc
+
+ "#phy-cells":
+ const: 3
+ description:
+ The first defines lane index.
+ The second defines the type of the PHY refer to the include phy.h.
+ The third defines the controller index, indicated which controller
+ is bound to the lane.
+
+ clocks:
+ minItems: 5
+ maxItems: 14
+
+ clock-names:
+ minItems: 5
+ maxItems: 14
+
+ fsl,hsio-cfg:
+ description: |
+ Specifies the use case of the HSIO module in the hardware design.
+ Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
+ confiured as following three use cases.
+ +---------------------------------------+
+ | | i.MX8QM |
+ |------------------|--------------------|
+ | | Lane0| Lane1| Lane2|
+ |------------------|------|------|------|
+ | pciea-x2-sata | PCIEA| PCIEA| SATA |
+ |------------------|------|------|------|
+ | pciea-x2-pcieb | PCIEA| PCIEA| PCIEB|
+ |------------------|------|------|------|
+ | pciea-pcieb-sata | PCIEA| PCIEB| SATA |
+ +---------------------------------------+
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
+ default: pciea-pcieb-sata
+
+ fsl,refclk-pad-mode:
+ description:
+ Specifies the mode of the refclk pad used. INPUT(PHY refclock is
+ provided externally via the refclk pad) or OUTPUT(PHY refclock is
+ derived from SoC internal source and provided on the refclk pad).
+ This property not exists means unused(PHY refclock is derived from
+ SoC internal source).
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ input, output, unused ]
+ default: unused
+
+ power-domains:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - fsl,hsio-cfg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-hsio
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pclk0
+ - const: apb_pclk0
+ - const: phy0_crr
+ - const: ctl0_crr
+ - const: misc_crr
+ power-domains:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-hsio
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: pclk0
+ - const: pclk1
+ - const: apb_pclk0
+ - const: apb_pclk1
+ - const: pclk2
+ - const: epcs_tx
+ - const: epcs_rx
+ - const: apb_pclk2
+ - const: phy0_crr
+ - const: phy1_crr
+ - const: ctl0_crr
+ - const: ctl1_crr
+ - const: ctl2_crr
+ - const: misc_crr
+ power-domains:
+ minItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-clock.h>
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/phy/phy-imx8-pcie.h>
+
+ phy@5f1a0000 {
+ compatible = "fsl,imx8qxp-hsio";
+ reg = <0x5f1a0000 0x10000>,
+ <0x5f120000 0x10000>,
+ <0x5f140000 0x10000>,
+ <0x5f160000 0x10000>;
+ reg-names = "reg", "phy", "ctrl", "misc";
+ clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
+ <&phyx1_lpcg IMX_LPCG_CLK_4>,
+ <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
+ <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
+ <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
+ power-domains = <&pd IMX_SC_R_SERDES_1>;
+ #phy-cells = <3>;
+ fsl,hsio-cfg = "pciea-pcieb-sata";
+ fsl,refclk-pad-mode = "input";
+ };
+...
diff --git a/dts/upstream/Bindings/phy/marvell,armada-cp110-utmi-phy.yaml b/dts/upstream/Bindings/phy/marvell,armada-cp110-utmi-phy.yaml
index 9ce7b4c..2ef02aa 100644
--- a/dts/upstream/Bindings/phy/marvell,armada-cp110-utmi-phy.yaml
+++ b/dts/upstream/Bindings/phy/marvell,armada-cp110-utmi-phy.yaml
@@ -41,6 +41,12 @@
Phandle to the system controller node
$ref: /schemas/types.yaml#/definitions/phandle
+ swap-dx-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Specifies the ports which will swap the differential-pair (D+/D-),
+ default is not-swapped.
+
# Required child nodes:
patternProperties:
diff --git a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 634cec5..58ce2d9 100644
--- a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -19,6 +19,8 @@
- qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
+ - qcom,ipq9574-qmp-gen3x1-pcie-phy
+ - qcom,ipq9574-qmp-gen3x2-pcie-phy
reg:
items:
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 16634f7..03dbd02 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -91,8 +91,7 @@
"#clock-cells": true
clock-output-names:
- minItems: 1
- maxItems: 2
+ maxItems: 1
"#phy-cells":
const: 0
@@ -222,14 +221,10 @@
- qcom,sm8650-qmp-gen4x2-pcie-phy
then:
properties:
- clock-output-names:
- minItems: 2
"#clock-cells":
const: 1
else:
properties:
- clock-output-names:
- maxItems: 1
"#clock-cells":
const: 0
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index 325585b..0e0b6ca 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -20,8 +20,9 @@
- qcom,ipq8074-qmp-usb3-phy
- qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- - com,qdu1000-qmp-usb3-uni-phy
+ - qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
@@ -112,6 +113,7 @@
enum:
- qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
@@ -152,6 +154,7 @@
contains:
enum:
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,x1e80100-qmp-usb3-uni-phy
then:
diff --git a/dts/upstream/Bindings/phy/qcom,usb-hs-phy.yaml b/dts/upstream/Bindings/phy/qcom,usb-hs-phy.yaml
index f042d6a..e03b516 100644
--- a/dts/upstream/Bindings/phy/qcom,usb-hs-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,usb-hs-phy.yaml
@@ -15,6 +15,7 @@
contains:
enum:
- qcom,usb-hs-phy-apq8064
+ - qcom,usb-hs-phy-msm8660
- qcom,usb-hs-phy-msm8960
then:
properties:
@@ -41,6 +42,7 @@
- enum:
- qcom,usb-hs-phy-apq8064
- qcom,usb-hs-phy-msm8226
+ - qcom,usb-hs-phy-msm8660
- qcom,usb-hs-phy-msm8916
- qcom,usb-hs-phy-msm8960
- qcom,usb-hs-phy-msm8974
diff --git a/dts/upstream/Bindings/phy/rockchip,rk3399-emmc-phy.yaml b/dts/upstream/Bindings/phy/rockchip,rk3399-emmc-phy.yaml
new file mode 100644
index 0000000..3e3729b
--- /dev/null
+++ b/dts/upstream/Bindings/phy/rockchip,rk3399-emmc-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,rk3399-emmc-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip EMMC PHY
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ const: rockchip,rk3399-emmc-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: emmcclk
+
+ drive-impedance-ohm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Specifies the drive impedance in Ohm.
+ enum: [33, 40, 50, 66, 100]
+ default: 50
+
+ rockchip,enable-strobe-pulldown:
+ type: boolean
+ description: |
+ Enable internal pull-down for the strobe
+ line. If not set, pull-down is not used.
+
+ rockchip,output-tapdelay-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Specifies the phyctrl_otapdlysec register.
+ default: 0x4
+ maximum: 0xf
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@f780 {
+ compatible = "rockchip,rk3399-emmc-phy";
+ reg = <0xf780 0x20>;
+ clocks = <&sdhci>;
+ clock-names = "emmcclk";
+ drive-impedance-ohm = <50>;
+ #phy-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/phy/rockchip-emmc-phy.txt b/dts/upstream/Bindings/phy/rockchip-emmc-phy.txt
deleted file mode 100644
index 57d28c0..0000000
--- a/dts/upstream/Bindings/phy/rockchip-emmc-phy.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Rockchip EMMC PHY
------------------------
-
-Required properties:
- - compatible: rockchip,rk3399-emmc-phy
- - #phy-cells: must be 0
- - reg: PHY register address offset and length in "general
- register files"
-
-Optional properties:
- - clock-names: Should contain "emmcclk". Although this is listed as optional
- (because most boards can get basic functionality without having
- access to it), it is strongly suggested.
- See ../clock/clock-bindings.txt for details.
- - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
- - drive-impedance-ohm: Specifies the drive impedance in Ohm.
- Possible values are 33, 40, 50, 66 and 100.
- If not set, the default value of 50 will be applied.
- - rockchip,enable-strobe-pulldown: Enable internal pull-down for the strobe
- line. If not set, pull-down is not used.
- - rockchip,output-tapdelay-select: Specifies the phyctrl_otapdlysec register.
- If not set, the register defaults to 0x4.
- Maximum value 0xf.
-
-Example:
-
-
-grf: syscon@ff770000 {
- compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
-
-...
-
- emmcphy: phy@f780 {
- compatible = "rockchip,rk3399-emmc-phy";
- reg = <0xf780 0x20>;
- clocks = <&sdhci>;
- clock-names = "emmcclk";
- drive-impedance-ohm = <50>;
- #phy-cells = <0>;
- };
-};
diff --git a/dts/upstream/Bindings/phy/samsung,usb3-drd-phy.yaml b/dts/upstream/Bindings/phy/samsung,usb3-drd-phy.yaml
index 452e584..16321cd 100644
--- a/dts/upstream/Bindings/phy/samsung,usb3-drd-phy.yaml
+++ b/dts/upstream/Bindings/phy/samsung,usb3-drd-phy.yaml
@@ -25,6 +25,7 @@
properties:
compatible:
enum:
+ - google,gs101-usb31drd-phy
- samsung,exynos5250-usbdrd-phy
- samsung,exynos5420-usbdrd-phy
- samsung,exynos5433-usbdrd-phy
@@ -57,7 +58,15 @@
the OF graph bindings specified.
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: phy
+ - const: pcs
+ - const: pma
samsung,pmu-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -72,6 +81,19 @@
description:
VBUS Boost 5V power source.
+ pll-supply:
+ description: Power supply for the USB PLL.
+ dvdd-usb20-supply:
+ description: DVDD power supply for the USB 2.0 phy.
+ vddh-usb20-supply:
+ description: VDDh power supply for the USB 2.0 phy.
+ vdd33-usb20-supply:
+ description: 3.3V power supply for the USB 2.0 phy.
+ vdda-usbdp-supply:
+ description: VDDa power supply for the USB DP phy.
+ vddh-usbdp-supply:
+ description: VDDh power supply for the USB DP phy.
+
required:
- compatible
- clocks
@@ -85,6 +107,40 @@
properties:
compatible:
contains:
+ const: google,gs101-usb31drd-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Gate of main PHY clock
+ - description: Gate of PHY reference clock
+ - description: Gate of control interface AXI clock
+ - description: Gate of control interface APB clock
+ - description: Gate of SCL APB clock
+ clock-names:
+ items:
+ - const: phy
+ - const: ref
+ - const: ctrl_aclk
+ - const: ctrl_pclk
+ - const: scl_pclk
+ reg:
+ minItems: 3
+ reg-names:
+ minItems: 3
+ required:
+ - reg-names
+ - pll-supply
+ - dvdd-usb20-supply
+ - vddh-usb20-supply
+ - vdd33-usb20-supply
+ - vdda-usbdp-supply
+ - vddh-usbdp-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
enum:
- samsung,exynos5433-usbdrd-phy
- samsung,exynos7-usbdrd-phy
@@ -100,7 +156,20 @@
- const: phy_utmi
- const: phy_pipe
- const: itp
- else:
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos5250-usbdrd-phy
+ - samsung,exynos5420-usbdrd-phy
+ - samsung,exynos850-usbdrd-phy
+ then:
properties:
clocks:
minItems: 2
@@ -109,6 +178,10 @@
items:
- const: phy
- const: ref
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
additionalProperties: false
diff --git a/dts/upstream/Bindings/phy/starfive,jh7110-dphy-tx.yaml b/dts/upstream/Bindings/phy/starfive,jh7110-dphy-tx.yaml
new file mode 100644
index 0000000..4a06a26
--- /dev/null
+++ b/dts/upstream/Bindings/phy/starfive,jh7110-dphy-tx.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SoC MIPI D-PHY Tx Controller
+
+maintainers:
+ - Keith Zhao <keith.zhao@starfivetech.com>
+ - Shengyang Chen <shengyang.chen@starfivetech.com>
+
+description:
+ The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
+ DSI data.
+
+properties:
+ compatible:
+ const: starfive,jh7110-dphy-tx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: txesc
+
+ resets:
+ items:
+ - description: MIPITX_DPHY_SYS reset
+
+ reset-names:
+ items:
+ - const: sys
+
+ power-domains:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@295e0000 {
+ compatible = "starfive,jh7110-dphy-tx";
+ reg = <0x295e0000 0x10000>;
+ clocks = <&voutcrg 14>;
+ clock-names = "txesc";
+ resets = <&syscrg 10>;
+ reset-names = "sys";
+ power-domains = <&aon_syscon 0>;
+ #phy-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
index 37c0a74..23ed9a8 100644
--- a/dts/upstream/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
@@ -35,22 +35,159 @@
patternProperties:
"^function|groups$":
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
- EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
- GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
- I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
- MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
- NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
- NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
- PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
- RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
- RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
- SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
- SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
- TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
- VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
+ enum:
+ - ACPI
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - BMCINT
+ - DDCCLK
+ - DDCDAT
+ - EXTRST
+ - FLACK
+ - FLBUSY
+ - FLWP
+ - GPID
+ - GPID0
+ - GPID2
+ - GPID4
+ - GPID6
+ - GPIE0
+ - GPIE2
+ - GPIE4
+ - GPIE6
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - LPCPD
+ - LPCPME
+ - LPCRST
+ - LPCSMI
+ - MAC1LINK
+ - MAC2LINK
+ - MDIO1
+ - MDIO2
+ - NCTS1
+ - NCTS2
+ - NCTS3
+ - NCTS4
+ - NDCD1
+ - NDCD2
+ - NDCD3
+ - NDCD4
+ - NDSR1
+ - NDSR2
+ - NDSR3
+ - NDSR4
+ - NDTR1
+ - NDTR2
+ - NDTR3
+ - NDTR4
+ - NDTS4
+ - NRI1
+ - NRI2
+ - NRI3
+ - NRI4
+ - NRTS1
+ - NRTS2
+ - NRTS3
+ - OSCCLK
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - RGMII1
+ - RGMII2
+ - RMII1
+ - RMII2
+ - ROM16
+ - ROM8
+ - ROMCS1
+ - ROMCS2
+ - ROMCS3
+ - ROMCS4
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD4
+ - SALT1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SD1
+ - SD2
+ - SGPMCK
+ - SGPMI
+ - SGPMLD
+ - SGPMO
+ - SGPSCK
+ - SGPSI0
+ - SGPSI1
+ - SGPSLD
+ - SIOONCTRL
+ - SIOPBI
+ - SIOPBO
+ - SIOPWREQ
+ - SIOPWRGD
+ - SIOS3
+ - SIOS5
+ - SIOSCI
+ - SPI1
+ - SPI1DEBUG
+ - SPI1PASSTHRU
+ - SPICS1
+ - TIMER3
+ - TIMER4
+ - TIMER5
+ - TIMER6
+ - TIMER7
+ - TIMER8
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD4
+ - UART6
+ - USB11D1
+ - USB11H2
+ - USB2D1
+ - USB2H1
+ - USBCKI
+ - VGABIOS_ROM
+ - VGAHS
+ - VGAVS
+ - VPI18
+ - VPI24
+ - VPI30
+ - VPO12
+ - VPO24
+ - WDTRST1
+ - WDTRST2
allOf:
- $ref: pinctrl.yaml#
diff --git a/dts/upstream/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
index 863da5d..35bd0e1 100644
--- a/dts/upstream/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
@@ -35,7 +35,7 @@
description: |
A cell of phandles to external controller nodes:
0: compatible with "aspeed,ast2500-gfx", "syscon"
- 1: compatible with "aspeed,ast2500-lhc", "syscon"
+ 1: compatible with "aspeed,ast2500-lpc", "syscon"
additionalProperties:
$ref: pinmux-node.yaml#
@@ -47,24 +47,174 @@
patternProperties:
"^function|groups$":
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
- ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
- GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
- I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
- LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
- MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
- NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
- NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
- PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
- RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
- SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
- SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
- SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
- TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
- USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
- VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
+ enum:
+ - ACPI
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - BMCINT
+ - DDCCLK
+ - DDCDAT
+ - ESPI
+ - FWSPICS1
+ - FWSPICS2
+ - GPID0
+ - GPID2
+ - GPID4
+ - GPID6
+ - GPIE0
+ - GPIE2
+ - GPIE4
+ - GPIE6
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - LAD0
+ - LAD1
+ - LAD2
+ - LAD3
+ - LCLK
+ - LFRAME
+ - LPCHC
+ - LPCPD
+ - LPCPLUS
+ - LPCPME
+ - LPCRST
+ - LPCSMI
+ - LSIRQ
+ - MAC1LINK
+ - MAC2LINK
+ - MDIO1
+ - MDIO2
+ - NCTS1
+ - NCTS2
+ - NCTS3
+ - NCTS4
+ - NDCD1
+ - NDCD2
+ - NDCD3
+ - NDCD4
+ - NDSR1
+ - NDSR2
+ - NDSR3
+ - NDSR4
+ - NDTR1
+ - NDTR2
+ - NDTR3
+ - NDTR4
+ - NRI1
+ - NRI2
+ - NRI3
+ - NRI4
+ - NRTS1
+ - NRTS2
+ - NRTS3
+ - NRTS4
+ - OSCCLK
+ - PEWAKE
+ - PNOR
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - RGMII1
+ - RGMII2
+ - RMII1
+ - RMII2
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD4
+ - SALT1
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SCL1
+ - SCL2
+ - SD1
+ - SD2
+ - SDA1
+ - SDA2
+ - SGPM
+ - SGPS1
+ - SGPS2
+ - SIOONCTRL
+ - SIOPBI
+ - SIOPBO
+ - SIOPWREQ
+ - SIOPWRGD
+ - SIOS3
+ - SIOS5
+ - SIOSCI
+ - SPI1
+ - SPI1CS1
+ - SPI1DEBUG
+ - SPI1PASSTHRU
+ - SPI2CK
+ - SPI2CS0
+ - SPI2CS1
+ - SPI2MISO
+ - SPI2MOSI
+ - TIMER3
+ - TIMER4
+ - TIMER5
+ - TIMER6
+ - TIMER7
+ - TIMER8
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD4
+ - UART6
+ - USB11BHID
+ - USB2AD
+ - USB2AH
+ - USB2BD
+ - USB2BH
+ - USBCKI
+ - VGABIOSROM
+ - VGAHS
+ - VGAVS
+ - VPI24
+ - VPO
+ - WDTRST1
+ - WDTRST2
allOf:
- $ref: pinctrl.yaml#
diff --git a/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index 612464a..80974c4 100644
--- a/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -19,6 +19,11 @@
Refer to the bindings described in
Documentation/devicetree/bindings/mfd/syscon.yaml
+ Note: According to the NCSI specification, the reference clock output pin
+ (RMIIXRCLKO) is not required on the management controller side. To optimize
+ pin usage, add "NCSI" pin groups that are equivalent to the RMII pin groups,
+ but without the RMIIXRCLKO pin.
+
properties:
compatible:
const: aspeed,ast2600-pinctrl
@@ -29,56 +34,469 @@
properties:
function:
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
- ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
- FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
- GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
- GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
- I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
- I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
- MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
- NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
- NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
- NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
- PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
- PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
- RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
- SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
- SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
- SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
- TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
- THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
- UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
- USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
+ enum:
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - BMCINT
+ - EMMC
+ - ESPI
+ - ESPIALT
+ - FSI1
+ - FSI2
+ - FWQSPI
+ - FWSPIABR
+ - FWSPID
+ - FWSPIWP
+ - GPIT0
+ - GPIT1
+ - GPIT2
+ - GPIT3
+ - GPIT4
+ - GPIT5
+ - GPIT6
+ - GPIT7
+ - GPIU0
+ - GPIU1
+ - GPIU2
+ - GPIU3
+ - GPIU4
+ - GPIU5
+ - GPIU6
+ - GPIU7
+ - I2C1
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I2C16
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I3C1
+ - I3C2
+ - I3C3
+ - I3C4
+ - I3C5
+ - I3C6
+ - JTAGM
+ - LHPD
+ - LHSIRQ
+ - LPC
+ - LPCHC
+ - LPCPD
+ - LPCPME
+ - LPCSMI
+ - LSIRQ
+ - MACLINK1
+ - MACLINK2
+ - MACLINK3
+ - MACLINK4
+ - MDIO1
+ - MDIO2
+ - MDIO3
+ - MDIO4
+ - NCTS1
+ - NCTS2
+ - NCTS3
+ - NCTS4
+ - NDCD1
+ - NDCD2
+ - NDCD3
+ - NDCD4
+ - NDSR1
+ - NDSR2
+ - NDSR3
+ - NDSR4
+ - NDTR1
+ - NDTR2
+ - NDTR3
+ - NDTR4
+ - NRI1
+ - NRI2
+ - NRI3
+ - NRI4
+ - NRTS1
+ - NRTS2
+ - NRTS3
+ - NRTS4
+ - OSCCLK
+ - PEWAKE
+ - PWM0
+ - PWM1
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - RGMII1
+ - RGMII2
+ - RGMII3
+ - RGMII4
+ - RMII1
+ - RMII2
+ - RMII3
+ - RMII4
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD4
+ - SALT1
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SALT16
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SD1
+ - SD2
+ - SGPM1
+ - SGPM2
+ - SGPS1
+ - SGPS2
+ - SIOONCTRL
+ - SIOPBI
+ - SIOPBO
+ - SIOPWREQ
+ - SIOPWRGD
+ - SIOS3
+ - SIOS5
+ - SIOSCI
+ - SPI1
+ - SPI1ABR
+ - SPI1CS1
+ - SPI1WP
+ - SPI2
+ - SPI2CS1
+ - SPI2CS2
+ - TACH0
+ - TACH1
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD4
+ - UART10
+ - UART11
+ - UART12
+ - UART13
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - USB11BHID
+ - USB2AD
+ - USB2AH
+ - USB2AHP
+ - USB2BD
+ - USB2BH
+ - USBAD
+ - USBADP
+ - VB
+ - VGAHS
+ - VGAVS
+ - WDTRST1
+ - WDTRST2
+ - WDTRST3
+ - WDTRST4
groups:
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
- ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
- EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
- GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
- GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
- I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
- I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
- LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
- MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
- NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
- NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
- OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
- PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
- PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
- QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
- RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
- SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
- SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
- SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
- SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
- SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
- TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
- TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
- TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
- UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
- WDTRST3, WDTRST4]
+ enum:
+ - ADC0
+ - ADC1
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - BMCINT
+ - EMMCG1
+ - EMMCG4
+ - EMMCG8
+ - ESPI
+ - ESPIALT
+ - FSI1
+ - FSI2
+ - FWQSPI
+ - FWSPIABR
+ - FWSPID
+ - FWSPIWP
+ - GPIT0
+ - GPIT1
+ - GPIT2
+ - GPIT3
+ - GPIT4
+ - GPIT5
+ - GPIT6
+ - GPIT7
+ - GPIU0
+ - GPIU1
+ - GPIU2
+ - GPIU3
+ - GPIU4
+ - GPIU5
+ - GPIU6
+ - GPIU7
+ - HVI3C3
+ - HVI3C4
+ - I2C1
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I2C16
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I3C1
+ - I3C2
+ - I3C3
+ - I3C4
+ - I3C5
+ - I3C6
+ - JTAGM
+ - LHPD
+ - LHSIRQ
+ - LPC
+ - LPCHC
+ - LPCPD
+ - LPCPME
+ - LPCSMI
+ - LSIRQ
+ - MACLINK1
+ - MACLINK2
+ - MACLINK3
+ - MACLINK4
+ - MDIO1
+ - MDIO2
+ - MDIO3
+ - MDIO4
+ - NCSI3
+ - NCSI4
+ - NCTS1
+ - NCTS2
+ - NCTS3
+ - NCTS4
+ - NDCD1
+ - NDCD2
+ - NDCD3
+ - NDCD4
+ - NDSR1
+ - NDSR2
+ - NDSR3
+ - NDSR4
+ - NDTR1
+ - NDTR2
+ - NDTR3
+ - NDTR4
+ - NRI1
+ - NRI2
+ - NRI3
+ - NRI4
+ - NRTS1
+ - NRTS2
+ - NRTS3
+ - NRTS4
+ - OSCCLK
+ - PEWAKE
+ - PWM0
+ - PWM1
+ - PWM10G0
+ - PWM10G1
+ - PWM11G0
+ - PWM11G1
+ - PWM12G0
+ - PWM12G1
+ - PWM13G0
+ - PWM13G1
+ - PWM14G0
+ - PWM14G1
+ - PWM15G0
+ - PWM15G1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8G0
+ - PWM8G1
+ - PWM9G0
+ - PWM9G1
+ - QSPI1
+ - QSPI2
+ - RGMII1
+ - RGMII2
+ - RGMII3
+ - RGMII4
+ - RMII1
+ - RMII2
+ - RMII3
+ - RMII4
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD4
+ - SALT1
+ - SALT10G0
+ - SALT10G1
+ - SALT11G0
+ - SALT11G1
+ - SALT12G0
+ - SALT12G1
+ - SALT13G0
+ - SALT13G1
+ - SALT14G0
+ - SALT14G1
+ - SALT15G0
+ - SALT15G1
+ - SALT16G0
+ - SALT16G1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9G0
+ - SALT9G1
+ - SD1
+ - SD2
+ - SD3
+ - SGPM1
+ - SGPM2
+ - SGPS1
+ - SGPS2
+ - SIOONCTRL
+ - SIOPBI
+ - SIOPBO
+ - SIOPWREQ
+ - SIOPWRGD
+ - SIOS3
+ - SIOS5
+ - SIOSCI
+ - SPI1
+ - SPI1ABR
+ - SPI1CS1
+ - SPI1WP
+ - SPI2
+ - SPI2CS1
+ - SPI2CS2
+ - TACH0
+ - TACH1
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD4
+ - UART10
+ - UART11
+ - UART12G0
+ - UART12G1
+ - UART13G0
+ - UART13G1
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - USBA
+ - USBB
+ - VB
+ - VGAHS
+ - VGAVS
+ - WDTRST1
+ - WDTRST2
+ - WDTRST3
+ - WDTRST4
pins: true
bias-disable: true
diff --git a/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml
new file mode 100644
index 0000000..a438db8
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/fsl,imx9-pinctrl.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale IMX9 IOMUX Controller
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description:
+ Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+ for common binding part and usage.
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx91-iomuxc
+ - fsl,imx93-iomuxc
+
+ reg:
+ maxItems: 1
+
+# Client device subnode's properties
+patternProperties:
+ 'grp$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ fsl,pins:
+ description:
+ each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
+ mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
+ be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
+ integer CONFIG is the pad setting value like pull-up on this pin. Please
+ refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "mux_reg" indicates the offset of mux register.
+ - description: |
+ "conf_reg" indicates the offset of pad configuration register.
+ - description: |
+ "input_reg" indicates the offset of select input register.
+ - description: |
+ "mux_val" indicates the mux value to be applied.
+ - description: |
+ "input_val" indicates the select input value to be applied.
+ - description: |
+ "pad_setting" indicates the pad configuration value to be applied.
+
+
+ required:
+ - fsl,pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ iomuxc: pinctrl@443c0000 {
+ compatible = "fsl,imx93-iomuxc";
+ reg = <0x30330000 0x10000>;
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins =
+ <0x48 0x1f8 0x41c 0x1 0x0 0x49>,
+ <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/pinctrl/fsl,imx93-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/fsl,imx93-pinctrl.yaml
deleted file mode 100644
index 2f24051..0000000
--- a/dts/upstream/Bindings/pinctrl/fsl,imx93-pinctrl.yaml
+++ /dev/null
@@ -1,85 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale IMX93 IOMUX Controller
-
-maintainers:
- - Peng Fan <peng.fan@nxp.com>
-
-description:
- Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
- for common binding part and usage.
-
-allOf:
- - $ref: pinctrl.yaml#
-
-properties:
- compatible:
- const: fsl,imx93-iomuxc
-
- reg:
- maxItems: 1
-
-# Client device subnode's properties
-patternProperties:
- 'grp$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
-
- properties:
- fsl,pins:
- description:
- each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
- mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
- be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
- integer CONFIG is the pad setting value like pull-up on this pin. Please
- refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
- items:
- items:
- - description: |
- "mux_reg" indicates the offset of mux register.
- - description: |
- "conf_reg" indicates the offset of pad configuration register.
- - description: |
- "input_reg" indicates the offset of select input register.
- - description: |
- "mux_val" indicates the mux value to be applied.
- - description: |
- "input_val" indicates the select input value to be applied.
- - description: |
- "pad_setting" indicates the pad configuration value to be applied.
-
-
- required:
- - fsl,pins
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- # Pinmux controller node
- - |
- iomuxc: pinctrl@443c0000 {
- compatible = "fsl,imx93-iomuxc";
- reg = <0x30330000 0x10000>;
-
- pinctrl_uart3: uart3grp {
- fsl,pins =
- <0x48 0x1f8 0x41c 0x1 0x0 0x49>,
- <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
- };
- };
-
-...
diff --git a/dts/upstream/Bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
new file mode 100644
index 0000000..763a49b
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 pin control and GPIO
+
+maintainers:
+ - Shan-Chun Hung <schung@nuvoton.com>
+ - Jacky Huang <ychuang3@nuvoton.com>
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,ma35d1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ nuvoton,sys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle of the system-management node.
+
+ ranges: true
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ type: object
+ properties:
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ description:
+ The interrupt outputs to sysirq.
+ maxItems: 1
+
+ required:
+ - gpio-controller
+ - '#gpio-cells'
+ - reg
+ - clocks
+ - interrupt-controller
+ - '#interrupt-cells'
+ - interrupts
+
+ additionalProperties: false
+
+ "-grp$":
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ patternProperties:
+ "-pins$":
+ type: object
+ description:
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and input
+ schmitt.
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ nuvoton,pins:
+ description:
+ Each entry consists of 4 parameters and represents the mux and config
+ setting for one pin.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ items:
+ items:
+ - minimum: 0
+ maximum: 13
+ description:
+ Pin bank.
+ - minimum: 0
+ maximum: 15
+ description:
+ Pin bank index.
+ - minimum: 0
+ maximum: 15
+ description:
+ Mux 0 means GPIO and mux 1 to 15 means the specific device function.
+
+ power-source:
+ description: |
+ Valid arguments are described as below:
+ 0: power supply of 1.8V
+ 1: power supply of 3.3V
+ enum: [0, 1]
+
+ drive-strength-microamp:
+ oneOf:
+ - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
+ description: 1.8V I/O driving strength
+ - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ]
+ description: 3.3V I/O driving strength
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ input-schmitt-disable: true
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - nuvoton,sys
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+ pinctrl@40040000 {
+ compatible = "nuvoton,ma35d1-pinctrl";
+ reg = <0x40040000 0xc00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nuvoton,sys = <&sys>;
+ ranges = <0x0 0x40040000 0x400>;
+
+ gpio@0 {
+ reg = <0x0 0x40>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk GPA_GATE>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart-grp {
+ uart11-pins {
+ nuvoton,pins = <11 0 2>,
+ <11 1 2>,
+ <11 2 2>,
+ <11 3 2>;
+ power-source = <1>;
+ bias-disable;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
index b55d9c3..814b959 100644
--- a/dts/upstream/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
@@ -85,11 +85,12 @@
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
- scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
- spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
- smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
- spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
- hgpio5, hgpio6, hgpio7 ]
+ scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
+ smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
+ spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
+ wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
+ hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
+ bu4b, bu5, bu5b, bu6, gpo187 ]
function:
description:
@@ -109,11 +110,12 @@
smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
- scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
- spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
- smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
- spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
- hgpio5, hgpio6, hgpio7 ]
+ scipme, smi, smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c,
+ smb7d, spi1, faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2,
+ spi3cs3, nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio,
+ wdog1, wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0,
+ hgpio1, hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4,
+ bu4b, bu5, bu5b, bu6, gpo187 ]
dependencies:
groups: [ function ]
diff --git a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
index c114955..e025953 100644
--- a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
+++ b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
@@ -75,11 +75,11 @@
description: Optional list of pin base, nr pins & gpio function
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - items:
- - description: phandle of a gpio-range node
- - description: pin base
- - description: number of pins
- - description: gpio function
+ items:
+ - description: phandle of a gpio-range node
+ - description: pin base
+ - description: number of pins
+ - description: gpio function
'#gpio-range-cells':
description: No longer needed, may exist in older files for gpio-ranges
@@ -144,6 +144,13 @@
- description: drive strength mask
pinctrl-single,input-schmitt:
+ description: Optional schmitt strength configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: schmitt strength current
+ - description: schmitt strength mask
+
+ pinctrl-single,input-schmitt-enable:
description: Optional input schmitt configuration
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
diff --git a/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
index bd3cbb4..e75393b 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Technologies, Inc. MDM9607 TLMM block
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
diff --git a/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml b/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml
index 0bf2d9f..2784d32 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,pmic-gpio.yaml
@@ -56,6 +56,7 @@
- qcom,pma8084-gpio
- qcom,pmc8180-gpio
- qcom,pmc8180c-gpio
+ - qcom,pmc8380-gpio
- qcom,pmd8028-gpio
- qcom,pmi632-gpio
- qcom,pmi8950-gpio
@@ -223,6 +224,7 @@
- qcom,pm8150-gpio
- qcom,pm8350-gpio
- qcom,pmc8180-gpio
+ - qcom,pmc8380-gpio
- qcom,pmi8994-gpio
- qcom,pmm8155au-gpio
then:
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..9612e21
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM4250 SoC LPASS LPI TLMM
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm4250-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+ - description: LPASS LPI MCC registers
+
+ clocks:
+ items:
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: audio
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm4250-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm4250-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm4250-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-9]|2[0-6])$"
+
+ function:
+ enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data,
+ dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a,
+ ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws,
+ i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws,
+ qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data,
+ swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk,
+ swr_wsa_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+allOf:
+ - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ lpi_tlmm: pinctrl@a7c0000 {
+ compatible = "qcom,sm4250-lpass-lpi-pinctrl";
+ reg = <0xa7c0000 0x20000>,
+ <0xa950000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "audio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 19>;
+
+ i2s2-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "i2s2_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio12";
+ function = "i2s2_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ };
+ };
+
+ i2s2-sleep-clk-state {
+ pins = "gpio10";
+ function = "i2s2_clk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
index a4771f8..b262af6 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Technologies, Inc. SM6350 TLMM block
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
index 047f828..c11af09 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Technologies, Inc. SM6375 TLMM block
maintainers:
- - Konrad Dybcio <konrad.dybcio@somainline.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 4d5a957..56d90c8 100644
--- a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- renesas,r9a08g045-pinctrl # RZ/G3S
+ - renesas,r9a09g057-pinctrl # RZ/V2H(P)
- items:
- enum:
@@ -66,10 +67,14 @@
maxItems: 1
resets:
- items:
- - description: GPIO_RSTN signal
- - description: GPIO_PORT_RESETN signal
- - description: GPIO_SPARE_RESETN signal
+ oneOf:
+ - items:
+ - description: GPIO_RSTN signal
+ - description: GPIO_PORT_RESETN signal
+ - description: GPIO_SPARE_RESETN signal
+ - items:
+ - description: PFC main reset
+ - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins
additionalProperties:
anyOf:
@@ -79,21 +84,6 @@
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
- - if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,r9a08g045-pinctrl
- then:
- properties:
- drive-strength: false
- output-impedance-ohms: false
- slew-rate: false
- else:
- properties:
- drive-strength-microamp: false
-
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
@@ -126,6 +116,16 @@
output-high: true
output-low: true
line-name: true
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ renesas,output-impedance:
+ description:
+ Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+ property corresponds to register bit values that can be set in the PFC_IOLH_mn
+ register, which adjusts the drive strength value and is pin-dependent.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
- type: object
additionalProperties:
@@ -134,6 +134,20 @@
allOf:
- $ref: pinctrl.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-pinctrl
+ then:
+ properties:
+ resets:
+ maxItems: 2
+ else:
+ properties:
+ resets:
+ minItems: 3
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
index f13d315..ce66fd1 100644
--- a/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
@@ -42,179 +42,187 @@
$ref: pinmux-node.yaml#
properties:
+ pins:
+ description:
+ List of pins to select (either this or "groups" must be specified)
+ items:
+ pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
+
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
- enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
- ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
- gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
- mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
- qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
- spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
- spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
- spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
- spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
- spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
- spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
- spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
- spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
- spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
- spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
- spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
- spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
- spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
- spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
- spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
- spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
- sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
- sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
- sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
- sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
- sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
- sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
- sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
- sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
- sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
- sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
- sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
- sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
- sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
- sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
- sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
- sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
- sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
- sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
- sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
- sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
- sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
- sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
- nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
- nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
- can0_1_grp, can0_2_grp, can0_3_grp,
- can0_4_grp, can0_5_grp, can0_6_grp,
- can0_7_grp, can0_8_grp, can0_9_grp,
- can0_10_grp, can0_11_grp, can0_12_grp,
- can0_13_grp, can0_14_grp, can0_15_grp,
- can0_16_grp, can0_17_grp, can0_18_grp,
- can1_0_grp, can1_1_grp, can1_2_grp,
- can1_3_grp, can1_4_grp, can1_5_grp,
- can1_6_grp, can1_7_grp, can1_8_grp,
- can1_9_grp, can1_10_grp, can1_11_grp,
- can1_12_grp, can1_13_grp, can1_14_grp,
- can1_15_grp, can1_16_grp, can1_17_grp,
- can1_18_grp, can1_19_grp, uart0_0_grp,
- uart0_1_grp, uart0_2_grp, uart0_3_grp,
- uart0_4_grp, uart0_5_grp, uart0_6_grp,
- uart0_7_grp, uart0_8_grp, uart0_9_grp,
- uart0_10_grp, uart0_11_grp, uart0_12_grp,
- uart0_13_grp, uart0_14_grp, uart0_15_grp,
- uart0_16_grp, uart0_17_grp, uart0_18_grp,
- uart1_0_grp, uart1_1_grp, uart1_2_grp,
- uart1_3_grp, uart1_4_grp, uart1_5_grp,
- uart1_6_grp, uart1_7_grp, uart1_8_grp,
- uart1_9_grp, uart1_10_grp, uart1_11_grp,
- uart1_12_grp, uart1_13_grp, uart1_14_grp,
- uart1_15_grp, uart1_16_grp, uart1_17_grp,
- uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
- i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
- i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
- i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
- i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
- i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
- i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
- i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
- i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
- i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
- i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
- i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
- i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
- i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
- ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
- ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
- ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
- ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
- ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
- ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
- ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
- ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
- ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
- ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
- ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
- ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
- ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
- ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
- ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
- ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
- ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
- ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
- ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
- ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
- ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
- ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
- ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
- ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
- swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
- swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
- swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
- swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
- swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
- swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
- swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
- swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
- swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
- swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
- swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
- swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
- swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
- swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
- swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
- swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
- swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
- gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
- gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
- gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
- gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
- gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
- gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
- gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
- gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
- gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
- gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
- gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
- gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
- gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
- gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
- gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
- gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
- gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
- gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
- gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
- gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
- gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
- gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
- gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
- gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
- gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
- gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
- usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
- pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
- pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
- pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
- pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
- pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
- pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
- csu0_0_grp, csu0_1_grp, csu0_2_grp,
- csu0_3_grp, csu0_4_grp, csu0_5_grp,
- csu0_6_grp, csu0_7_grp, csu0_8_grp,
- csu0_9_grp, csu0_10_grp, csu0_11_grp,
- dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
- dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
- pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
- pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
- trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
- trace0_clk_2_grp, testscan0_0_grp]
+ anyOf:
+ - pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
+ - enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
+ ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
+ gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
+ mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
+ qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
+ spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
+ spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
+ spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
+ spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
+ spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
+ spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
+ spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
+ spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
+ spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
+ spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
+ spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
+ spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
+ spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
+ spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
+ spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
+ spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
+ sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
+ sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
+ sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
+ sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
+ sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
+ sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
+ sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
+ sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
+ sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
+ sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
+ sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
+ sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
+ sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
+ sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
+ sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
+ sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
+ sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
+ sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
+ sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
+ sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
+ sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
+ sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
+ nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
+ nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
+ can0_1_grp, can0_2_grp, can0_3_grp,
+ can0_4_grp, can0_5_grp, can0_6_grp,
+ can0_7_grp, can0_8_grp, can0_9_grp,
+ can0_10_grp, can0_11_grp, can0_12_grp,
+ can0_13_grp, can0_14_grp, can0_15_grp,
+ can0_16_grp, can0_17_grp, can0_18_grp,
+ can1_0_grp, can1_1_grp, can1_2_grp,
+ can1_3_grp, can1_4_grp, can1_5_grp,
+ can1_6_grp, can1_7_grp, can1_8_grp,
+ can1_9_grp, can1_10_grp, can1_11_grp,
+ can1_12_grp, can1_13_grp, can1_14_grp,
+ can1_15_grp, can1_16_grp, can1_17_grp,
+ can1_18_grp, can1_19_grp, uart0_0_grp,
+ uart0_1_grp, uart0_2_grp, uart0_3_grp,
+ uart0_4_grp, uart0_5_grp, uart0_6_grp,
+ uart0_7_grp, uart0_8_grp, uart0_9_grp,
+ uart0_10_grp, uart0_11_grp, uart0_12_grp,
+ uart0_13_grp, uart0_14_grp, uart0_15_grp,
+ uart0_16_grp, uart0_17_grp, uart0_18_grp,
+ uart1_0_grp, uart1_1_grp, uart1_2_grp,
+ uart1_3_grp, uart1_4_grp, uart1_5_grp,
+ uart1_6_grp, uart1_7_grp, uart1_8_grp,
+ uart1_9_grp, uart1_10_grp, uart1_11_grp,
+ uart1_12_grp, uart1_13_grp, uart1_14_grp,
+ uart1_15_grp, uart1_16_grp, uart1_17_grp,
+ uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
+ i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
+ i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
+ i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
+ i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
+ i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
+ i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
+ i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
+ i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
+ i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
+ i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
+ i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
+ i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
+ i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
+ ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
+ ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
+ ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
+ ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
+ ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
+ ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
+ ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
+ ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
+ ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
+ ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
+ ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
+ ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
+ ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
+ ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
+ ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
+ ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
+ ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
+ ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
+ ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
+ ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
+ ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
+ ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
+ ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
+ ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
+ swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
+ swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
+ swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
+ swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
+ swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
+ swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
+ swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
+ swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
+ swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
+ swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
+ swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
+ swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
+ swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
+ swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
+ swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
+ swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
+ swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
+ gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
+ gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
+ gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
+ gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
+ gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
+ gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
+ gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
+ gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
+ gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
+ gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
+ gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
+ gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
+ gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
+ gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
+ gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
+ gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
+ gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
+ gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
+ gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
+ gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
+ gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
+ gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
+ gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
+ gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
+ gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
+ gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
+ usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
+ pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
+ pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
+ pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
+ pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
+ pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
+ pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
+ csu0_0_grp, csu0_1_grp, csu0_2_grp,
+ csu0_3_grp, csu0_4_grp, csu0_5_grp,
+ csu0_6_grp, csu0_7_grp, csu0_8_grp,
+ csu0_9_grp, csu0_10_grp, csu0_11_grp,
+ dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
+ dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
+ pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
+ pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
+ trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
+ trace0_clk_2_grp, testscan0_0_grp]
maxItems: 78
function:
@@ -230,9 +238,12 @@
pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
required:
- - groups
- function
+ oneOf:
+ - required: [ groups ]
+ - required: [ pins ]
+
additionalProperties: false
'^conf':
diff --git a/dts/upstream/Bindings/platform/lenovo,yoga-c630-ec.yaml b/dts/upstream/Bindings/platform/lenovo,yoga-c630-ec.yaml
new file mode 100644
index 0000000..3180ce1
--- /dev/null
+++ b/dts/upstream/Bindings/platform/lenovo,yoga-c630-ec.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/platform/lenovo,yoga-c630-ec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lenovo Yoga C630 Embedded Controller.
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description:
+ The Qualcomm Snapdragon-based Lenovo Yoga C630 has an Embedded Controller
+ (EC) which handles things such as battery and USB Type-C. This binding
+ describes the interface, on an I2C bus, to this EC.
+
+properties:
+ compatible:
+ const: lenovo,yoga-c630-ec
+
+ reg:
+ const: 0x70
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ interrupts:
+ maxItems: 1
+
+patternProperties:
+ '^connector@[01]$':
+ $ref: /schemas/connector/usb-connector.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c1 {
+ clock-frequency = <400000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@70 {
+ compatible = "lenovo,yoga-c630-ec";
+ reg = <0x70>;
+
+ interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "source";
+ data-role = "host";
+ };
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "source";
+ data-role = "host";
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/power/amlogic,meson-sec-pwrc.yaml b/dts/upstream/Bindings/power/amlogic,meson-sec-pwrc.yaml
index dab3d92..15d7413 100644
--- a/dts/upstream/Bindings/power/amlogic,meson-sec-pwrc.yaml
+++ b/dts/upstream/Bindings/power/amlogic,meson-sec-pwrc.yaml
@@ -20,6 +20,8 @@
enum:
- amlogic,meson-a1-pwrc
- amlogic,meson-s4-pwrc
+ - amlogic,a4-pwrc
+ - amlogic,a5-pwrc
- amlogic,c3-pwrc
- amlogic,t7-pwrc
diff --git a/dts/upstream/Bindings/power/supply/maxim,max17201.yaml b/dts/upstream/Bindings/power/supply/maxim,max17201.yaml
new file mode 100644
index 0000000..fe3dd9b
--- /dev/null
+++ b/dts/upstream/Bindings/power/supply/maxim,max17201.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/maxim,max17201.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX17201 fuel gauge
+
+maintainers:
+ - Dimitri Fedrau <dima.fedrau@gmail.com>
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: maxim,max17201
+ - items:
+ - enum:
+ - maxim,max17205
+ - const: maxim,max17201
+
+ reg:
+ items:
+ - description: ModelGauge m5 registers
+ - description: Nonvolatile registers
+
+ reg-names:
+ items:
+ - const: m5
+ - const: nvmem
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fuel-gauge@36 {
+ compatible = "maxim,max17201";
+ reg = <0x36>, <0xb>;
+ reg-names = "m5", "nvmem";
+ interrupt-parent = <&gpio0>;
+ interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
diff --git a/dts/upstream/Bindings/ptp/fsl,ptp.yaml b/dts/upstream/Bindings/ptp/fsl,ptp.yaml
new file mode 100644
index 0000000..3bb8615
--- /dev/null
+++ b/dts/upstream/Bindings/ptp/fsl,ptp.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QorIQ 1588 timer based PTP clock
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,etsec-ptp
+ - fsl,fman-ptp-timer
+ - fsl,dpaa2-ptp
+ - fsl,enetc-ptp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ fsl,cksel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Timer reference clock source.
+
+ Reference clock source is determined by the value, which is holded
+ in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
+ value, which will be directly written in those bits, that is why,
+ according to reference manual, the next clock sources can be used:
+
+ For eTSEC,
+ <0> - external high precision timer reference clock (TSEC_TMR_CLK
+ input is used for this purpose);
+ <1> - eTSEC system clock;
+ <2> - eTSEC1 transmit clock;
+ <3> - RTC clock input.
+
+ For DPAA FMan,
+ <0> - external high precision timer reference clock (TMR_1588_CLK)
+ <1> - MAC system clock (1/2 FMan clock)
+ <2> - reserved
+ <3> - RTC clock oscillator
+
+ fsl,tclk-period:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Timer reference clock period in nanoseconds.
+
+ fsl,tmr-prsc:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Prescaler, divides the output clock.
+
+ fsl,tmr-add:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Frequency compensation value.
+
+ fsl,tmr-fiper1:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Fixed interval period pulse generator.
+
+ fsl,tmr-fiper2:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Fixed interval period pulse generator.
+
+ fsl,tmr-fiper3:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Fixed interval period pulse generator.
+ Supported only on DPAA2 and ENETC hardware.
+
+ fsl,max-adj:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = selected reference clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClock microseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1 = 1000000 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+ When this attribute is not used, the IEEE 1588 timer reference clock
+ will use the eTSEC system clock (for Gianfar) or the MAC system
+ clock (for DPAA).
+
+ fsl,extts-fifo:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The presence of this property indicates hardware
+ support for the external trigger stamp FIFO
+
+ little-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The presence of this property indicates the 1588 timer
+ support for the external trigger stamp FIFO.
+ IP block is little-endian mode. The default endian mode
+ is big-endian.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ phc@24e00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24e00 0xb0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&ipic>;
+ fsl,cksel = <1>;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999a4>;
+ fsl,tmr-fiper1 = <0x3b9ac9f6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
diff --git a/dts/upstream/Bindings/ptp/ptp-qoriq.txt b/dts/upstream/Bindings/ptp/ptp-qoriq.txt
deleted file mode 100644
index 743eda7..0000000
--- a/dts/upstream/Bindings/ptp/ptp-qoriq.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-* Freescale QorIQ 1588 timer based PTP clock
-
-General Properties:
-
- - compatible Should be "fsl,etsec-ptp" for eTSEC
- Should be "fsl,fman-ptp-timer" for DPAA FMan
- Should be "fsl,dpaa2-ptp" for DPAA2
- Should be "fsl,enetc-ptp" for ENETC
- - reg Offset and length of the register set for the device
- - interrupts There should be at least two interrupts. Some devices
- have as many as four PTP related interrupts.
-
-Clock Properties:
-
- - fsl,cksel Timer reference clock source.
- - fsl,tclk-period Timer reference clock period in nanoseconds.
- - fsl,tmr-prsc Prescaler, divides the output clock.
- - fsl,tmr-add Frequency compensation value.
- - fsl,tmr-fiper1 Fixed interval period pulse generator.
- - fsl,tmr-fiper2 Fixed interval period pulse generator.
- - fsl,tmr-fiper3 Fixed interval period pulse generator.
- Supported only on DPAA2 and ENETC hardware.
- - fsl,max-adj Maximum frequency adjustment in parts per billion.
- - fsl,extts-fifo The presence of this property indicates hardware
- support for the external trigger stamp FIFO.
- - little-endian The presence of this property indicates the 1588 timer
- IP block is little-endian mode. The default endian mode
- is big-endian.
-
- These properties set the operational parameters for the PTP
- clock. You must choose these carefully for the clock to work right.
- Here is how to figure good values:
-
- TimerOsc = selected reference clock MHz
- tclk_period = desired clock period nanoseconds
- NominalFreq = 1000 / tclk_period MHz
- FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
- tmr_add = ceil(2^32 / FreqDivRatio)
- OutputClock = NominalFreq / tmr_prsc MHz
- PulseWidth = 1 / OutputClock microseconds
- FiperFreq1 = desired frequency in Hz
- FiperDiv1 = 1000000 * OutputClock / FiperFreq1
- tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
- max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
-
- The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
- driver expects that tmr_fiper1 will be correctly set to produce a 1
- Pulse Per Second (PPS) signal, since this will be offered to the PPS
- subsystem to synchronize the Linux clock.
-
- Reference clock source is determined by the value, which is holded
- in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
- value, which will be directly written in those bits, that is why,
- according to reference manual, the next clock sources can be used:
-
- For eTSEC,
- <0> - external high precision timer reference clock (TSEC_TMR_CLK
- input is used for this purpose);
- <1> - eTSEC system clock;
- <2> - eTSEC1 transmit clock;
- <3> - RTC clock input.
-
- For DPAA FMan,
- <0> - external high precision timer reference clock (TMR_1588_CLK)
- <1> - MAC system clock (1/2 FMan clock)
- <2> - reserved
- <3> - RTC clock oscillator
-
- When this attribute is not used, the IEEE 1588 timer reference clock
- will use the eTSEC system clock (for Gianfar) or the MAC system
- clock (for DPAA).
-
-Example:
-
- ptp_clock@24e00 {
- compatible = "fsl,etsec-ptp";
- reg = <0x24E00 0xB0>;
- interrupts = <12 0x8 13 0x8>;
- interrupt-parent = < &ipic >;
- fsl,cksel = <1>;
- fsl,tclk-period = <10>;
- fsl,tmr-prsc = <100>;
- fsl,tmr-add = <0x999999A4>;
- fsl,tmr-fiper1 = <0x3B9AC9F6>;
- fsl,tmr-fiper2 = <0x00018696>;
- fsl,max-adj = <659999998>;
- };
diff --git a/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
new file mode 100644
index 0000000..ec6115d
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI PWM generator
+
+maintainers:
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+ - Nuno Sá <nuno.sa@analog.com>
+
+description:
+ The Analog Devices AXI PWM generator can generate PWM signals
+ with variable pulse width and period.
+
+ https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: adi,axi-pwmgen-2.00.a
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+required:
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pwm@44b00000 {
+ compatible = "adi,axi-pwmgen-2.00.a";
+ reg = <0x44b00000 0x1000>;
+ clocks = <&spi_clk>;
+ #pwm-cells = <2>;
+ };
diff --git a/dts/upstream/Bindings/pwm/atmel,at91sam-pwm.yaml b/dts/upstream/Bindings/pwm/atmel,at91sam-pwm.yaml
index 96cd6f3..d20ad27 100644
--- a/dts/upstream/Bindings/pwm/atmel,at91sam-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/atmel,at91sam-pwm.yaml
@@ -23,7 +23,9 @@
- atmel,sama5d2-pwm
- microchip,sam9x60-pwm
- items:
- - const: microchip,sama7g5-pwm
+ - enum:
+ - microchip,sama7d65-pwm
+ - microchip,sama7g5-pwm
- const: atmel,sama5d2-pwm
- items:
- const: microchip,sam9x7-pwm
diff --git a/dts/upstream/Bindings/pwm/fsl,vf610-ftm-pwm.yaml b/dts/upstream/Bindings/pwm/fsl,vf610-ftm-pwm.yaml
new file mode 100644
index 0000000..7f9f72d
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/fsl,vf610-ftm-pwm.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale FlexTimer Module (FTM) PWM controller
+
+description: |
+ The same FTM PWM device can have a different endianness on different SoCs. The
+ device tree provides a property to describing this so that an operating system
+ device driver can handle all variants of the device. Refer to the table below
+ for the endianness of the FTM PWM block as integrated into the existing SoCs:
+
+ SoC | FTM-PWM endianness
+ --------+-------------------
+ Vybrid | LE
+ LS1 | BE
+ LS2 | LE
+
+ Please see ../regmap/regmap.txt for more detail about how to specify endian
+ modes in device tree.
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,vf610-ftm-pwm
+ - fsl,imx8qm-ftm-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+ clocks:
+ minItems: 4
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: ftm_sys
+ - const: ftm_ext
+ - const: ftm_fix
+ - const: ftm_cnt_clk_en
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+ minItems: 1
+ items:
+ - const: default
+ - const: sleep
+
+ big-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Boolean property, required if the FTM PWM registers use a big-
+ endian rather than little-endian layout.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: pwm.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/vf610-clock.h>
+
+ pwm@40038000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ reg = <0x40038000 0x1000>;
+ #pwm-cells = <3>;
+ clocks = <&clks VF610_CLK_FTM0>,
+ <&clks VF610_CLK_FTM0_EXT_SEL>,
+ <&clks VF610_CLK_FTM0_FIX_SEL>,
+ <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+ clock-names = "ftm_sys", "ftm_ext", "ftm_fix", "ftm_cnt_clk_en";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_1>;
+ big-endian;
+ };
diff --git a/dts/upstream/Bindings/pwm/imx-pwm.yaml b/dts/upstream/Bindings/pwm/imx-pwm.yaml
index a84a240..0414819 100644
--- a/dts/upstream/Bindings/pwm/imx-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/imx-pwm.yaml
@@ -68,7 +68,6 @@
- reg
- clocks
- clock-names
- - interrupts
additionalProperties: false
diff --git a/dts/upstream/Bindings/pwm/imx-tpm-pwm.yaml b/dts/upstream/Bindings/pwm/imx-tpm-pwm.yaml
index 8bef9df..ac0a35b 100644
--- a/dts/upstream/Bindings/pwm/imx-tpm-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/imx-tpm-pwm.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX TPM PWM controller
maintainers:
- - Anson Huang <anson.huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
description: |
The TPM counter and period counter are shared between multiple
diff --git a/dts/upstream/Bindings/pwm/mxs-pwm.yaml b/dts/upstream/Bindings/pwm/mxs-pwm.yaml
index 8f50e23..a9d3a41 100644
--- a/dts/upstream/Bindings/pwm/mxs-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/mxs-pwm.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Anson Huang <anson.huang@nxp.com>
allOf:
- $ref: pwm.yaml#
diff --git a/dts/upstream/Bindings/pwm/pwm-fsl-ftm.txt b/dts/upstream/Bindings/pwm/pwm-fsl-ftm.txt
deleted file mode 100644
index 36532cd..0000000
--- a/dts/upstream/Bindings/pwm/pwm-fsl-ftm.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Freescale FlexTimer Module (FTM) PWM controller
-
-The same FTM PWM device can have a different endianness on different SoCs. The
-device tree provides a property to describing this so that an operating system
-device driver can handle all variants of the device. Refer to the table below
-for the endianness of the FTM PWM block as integrated into the existing SoCs:
-
- SoC | FTM-PWM endianness
- --------+-------------------
- Vybrid | LE
- LS1 | BE
- LS2 | LE
-
-Please see ../regmap/regmap.txt for more detail about how to specify endian
-modes in device tree.
-
-
-Required properties:
-- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
- compatible strings:
- - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
- - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
-- reg: Physical base address and length of the controller's registers
-- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
- the cells format.
-- clock-names: Should include the following module clock source entries:
- "ftm_sys" (module clock, also can be used as counter clock),
- "ftm_ext" (external counter clock),
- "ftm_fix" (fixed counter clock),
- "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
-- clocks: Must contain a phandle and clock specifier for each entry in
- clock-names, please see clock/clock-bindings.txt for details of the property
- values.
-- pinctrl-names: Must contain a "default" entry.
-- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
- See pinctrl/pinctrl-bindings.txt for details of the property values.
-- big-endian: Boolean property, required if the FTM PWM registers use a big-
- endian rather than little-endian layout.
-
-Example:
-
-pwm0: pwm@40038000 {
- compatible = "fsl,vf610-ftm-pwm";
- reg = <0x40038000 0x1000>;
- #pwm-cells = <3>;
- clock-names = "ftm_sys", "ftm_ext",
- "ftm_fix", "ftm_cnt_clk_en";
- clocks = <&clks VF610_CLK_FTM0>,
- <&clks VF610_CLK_FTM0_EXT_SEL>,
- <&clks VF610_CLK_FTM0_FIX_SEL>,
- <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_1>;
- big-endian;
-};
diff --git a/dts/upstream/Bindings/pwm/pwm-gpio.yaml b/dts/upstream/Bindings/pwm/pwm-gpio.yaml
new file mode 100644
index 0000000..1576c19
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/pwm-gpio.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/pwm-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic software PWM for modulating GPIOs
+
+maintainers:
+ - Stefan Wahren <wahrenst@gmx.net>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: pwm-gpio
+
+ "#pwm-cells":
+ const: 3
+ description:
+ See pwm.yaml in this directory for a description of the cells format.
+ The first cell which represents the PWM instance number must always
+ be zero.
+
+ gpios:
+ description:
+ GPIO to be modulated
+ maxItems: 1
+
+required:
+ - compatible
+ - "#pwm-cells"
+ - gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ pwm {
+ #pwm-cells = <3>;
+ compatible = "pwm-gpio";
+ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/upstream/Bindings/pwm/pwm.yaml b/dts/upstream/Bindings/pwm/pwm.yaml
index abd9fa8..f2206ec 100644
--- a/dts/upstream/Bindings/pwm/pwm.yaml
+++ b/dts/upstream/Bindings/pwm/pwm.yaml
@@ -16,8 +16,10 @@
pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"
"#pwm-cells":
- description:
- Number of cells in a PWM specifier.
+ description: |
+ Number of cells in a PWM specifier. Typically the cells represent, in
+ order: the chip-relative PWM number, the PWM period in nanoseconds and
+ optionally a number of flags (defined in <dt-bindings/pwm/pwm.h>).
required:
- "#pwm-cells"
diff --git a/dts/upstream/Bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml b/dts/upstream/Bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
new file mode 100644
index 0000000..7048286
--- /dev/null
+++ b/dts/upstream/Bindings/regulator/mediatek,mt6873-dvfsrc-regulator.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DVFSRC-controlled Regulators
+
+description:
+ The Dynamic Voltage and Frequency Scaling Resource Collector Regulators
+ are controlled with votes to the DVFSRC hardware.
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt6873-dvfsrc-regulator
+ - mediatek,mt8183-dvfsrc-regulator
+ - mediatek,mt8192-dvfsrc-regulator
+ - mediatek,mt8195-dvfsrc-regulator
+
+ dvfsrc-vcore:
+ description: DVFSRC-controlled SoC Vcore regulator
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ dvfsrc-vscp:
+ description: DVFSRC-controlled System Control Processor regulator
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+anyOf:
+ - required:
+ - dvfsrc-vcore
+ - required:
+ - dvfsrc-vscp
+
+additionalProperties: false
diff --git a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
index 6317daf..cd4aa27 100644
--- a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
@@ -16,7 +16,11 @@
properties:
compatible:
- const: mediatek,mt6315-regulator
+ oneOf:
+ - items:
+ - const: mediatek,mt6319-regulator
+ - const: mediatek,mt6315-regulator
+ - const: mediatek,mt6315-regulator
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
index 849bfa5..f8057bb 100644
--- a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
@@ -96,7 +96,6 @@
required:
- compatible
- reg
- - interrupts
- regulators
additionalProperties: false
diff --git a/dts/upstream/Bindings/regulator/qcom,qca6390-pmu.yaml b/dts/upstream/Bindings/regulator/qcom,qca6390-pmu.yaml
new file mode 100644
index 0000000..3aaa965
--- /dev/null
+++ b/dts/upstream/Bindings/regulator/qcom,qca6390-pmu.yaml
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/qcom,qca6390-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QCA6390 PMU Regulators
+
+maintainers:
+ - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+
+description:
+ The QCA6390 package contains discrete modules for WLAN and Bluetooth. They
+ are powered by the Power Management Unit (PMU) that takes inputs from the
+ host and provides LDO outputs. This document describes this module.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca6390-pmu
+ - qcom,wcn7850-pmu
+
+ vdd-supply:
+ description: VDD supply regulator handle
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vdddig-supply:
+ description: VDD_DIG supply regulator handle
+
+ vddpmu-supply:
+ description: VDD_PMU supply regulator handle
+
+ vddio1p2-supply:
+ description: VDD_IO_1P2 supply regulator handle
+
+ vddrfa0p95-supply:
+ description: VDD_RFA_0P95 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p3-supply:
+ description: VDD_RFA_1P3 supply regulator handle
+
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
+ vddrfa1p9-supply:
+ description: VDD_RFA_1P9 supply regulator handle
+
+ vddpcie1p3-supply:
+ description: VDD_PCIE_1P3 supply regulator handle
+
+ vddpcie1p9-supply:
+ description: VDD_PCIE_1P9 supply regulator handle
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ wlan-enable-gpios:
+ maxItems: 1
+ description: GPIO line enabling the ATH11K WLAN module supplied by the PMU
+
+ bt-enable-gpios:
+ maxItems: 1
+ description: GPIO line enabling the ATH11K Bluetooth module supplied by the PMU
+
+ clocks:
+ maxItems: 1
+ description: Reference clock handle
+
+ regulators:
+ type: object
+ description:
+ LDO outputs of the PMU
+
+ patternProperties:
+ "^ldo[0-9]$":
+ $ref: regulator.yaml#
+ type: object
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - regulators
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,qca6390-pmu
+ then:
+ required:
+ - vddaon-supply
+ - vddpmu-supply
+ - vddrfa0p95-supply
+ - vddrfa1p3-supply
+ - vddrfa1p9-supply
+ - vddpcie1p3-supply
+ - vddpcie1p9-supply
+ - vddio-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,wcn7850-pmu
+ then:
+ required:
+ - vdd-supply
+ - vddio-supply
+ - vddaon-supply
+ - vdddig-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ pmu {
+ compatible = "qcom,qca6390-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
+
+ vddaon-supply = <&vreg_s6a_0p95>;
+ vddpmu-supply = <&vreg_s2f_0p95>;
+ vddrfa0p95-supply = <&vreg_s2f_0p95>;
+ vddrfa1p3-supply = <&vreg_s8c_1p3>;
+ vddrfa1p9-supply = <&vreg_s5a_1p9>;
+ vddpcie1p3-supply = <&vreg_s8c_1p3>;
+ vddpcie1p9-supply = <&vreg_s5a_1p9>;
+ vddio-supply = <&vreg_s4a_1p8>;
+
+ wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p7: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p7";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/regulator/richtek,rtq2208.yaml b/dts/upstream/Bindings/regulator/richtek,rtq2208.yaml
index 609c066..87accc6 100644
--- a/dts/upstream/Bindings/regulator/richtek,rtq2208.yaml
+++ b/dts/upstream/Bindings/regulator/richtek,rtq2208.yaml
@@ -75,6 +75,12 @@
description:
regulator description for ldo[1-2].
+ properties:
+ richtek,fixed-microvolt:
+ description: |
+ This property can be used to set a fixed operating voltage that lies outside
+ the range of the regulator's adjustable mode.
+
required:
- compatible
- reg
@@ -177,6 +183,8 @@
};
};
ldo1 {
+ /* Fixed LDO VOUT */
+ richtek,fixed-microvolt = <1200000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@@ -185,7 +193,8 @@
};
};
ldo2 {
- regulator-min-microvolt = <3300000>;
+ /* Adjustable LDO VOUT */
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-mem {
diff --git a/dts/upstream/Bindings/regulator/rohm,bd96801-regulator.yaml b/dts/upstream/Bindings/regulator/rohm,bd96801-regulator.yaml
new file mode 100644
index 0000000..b3d2d7d
--- /dev/null
+++ b/dts/upstream/Bindings/regulator/rohm,bd96801-regulator.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/rohm,bd96801-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD96801 Power Management Integrated Circuit regulators
+
+maintainers:
+ - Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+
+description:
+ This module is part of the ROHM BD96801 MFD device. For more details
+ see Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml.
+
+ The regulator controller is represented as a sub-node of the PMIC node
+ on the device tree.
+
+ Regulator nodes should be named to buck_<number> and ldo_<number>.
+ The valid names for BD96801 regulator nodes are
+ buck1, buck2, buck3, buck4, ldo5, ldo6, ldo7
+
+patternProperties:
+ "^ldo[5-7]$":
+ type: object
+ description:
+ Properties for single LDO regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ rohm,initial-voltage-microvolt:
+ description:
+ Initial voltage for regulator. Voltage can be tuned +/-150 mV from
+ this value. NOTE, This can be modified via I2C only when PMIC is in
+ STBY state.
+ minimum: 300000
+ maximum: 3300000
+
+ unevaluatedProperties: false
+
+ "^buck[1-4]$":
+ type: object
+ description:
+ Properties for single BUCK regulator.
+ $ref: regulator.yaml#
+
+ properties:
+ rohm,initial-voltage-microvolt:
+ description:
+ Initial voltage for regulator. Voltage can be tuned +/-150 mV from
+ this value. NOTE, This can be modified via I2C only when PMIC is in
+ STBY state.
+ minimum: 500000
+ maximum: 3300000
+
+ rohm,keep-on-stby:
+ description:
+ Keep the regulator powered when PMIC transitions to STBY state.
+ type: boolean
+
+ unevaluatedProperties: false
+
+additionalProperties: false
diff --git a/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.txt b/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.txt
deleted file mode 100644
index 63dc078..0000000
--- a/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-Spreadtrum SC2731 Voltage regulators
-
-The SC2731 integrates low-voltage and low quiescent current DCDC/LDO.
-14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have
-their own bypass (power-down) control signals. External tantalum or MLCC
-ceramic capacitors are recommended to use with these LDOs.
-
-Required properties:
- - compatible: should be "sprd,sc27xx-regulator".
-
-List of regulators provided by this controller. It is named according to
-its regulator type, BUCK_<name> and LDO_<name>. The definition for each
-of these nodes is defined using the standard binding for regulators at
-Documentation/devicetree/bindings/regulator/regulator.txt.
-
-The valid names for regulators are:
-BUCK:
- BUCK_CPU0, BUCK_CPU1, BUCK_RF
-LDO:
- LDO_CAMA0, LDO_CAMA1, LDO_CAMMOT, LDO_VLDO, LDO_EMMCCORE, LDO_SDCORE,
- LDO_SDIO, LDO_WIFIPA, LDO_USB33, LDO_CAMD0, LDO_CAMD1, LDO_CON,
- LDO_CAMIO, LDO_SRAM
-
-Example:
- regulators {
- compatible = "sprd,sc27xx-regulator";
-
- vddarm0: BUCK_CPU0 {
- regulator-name = "vddarm0";
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1996875>;
- regulator-ramp-delay = <25000>;
- regulator-always-on;
- };
-
- vddcama0: LDO_CAMA0 {
- regulator-name = "vddcama0";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3750000>;
- regulator-enable-ramp-delay = <100>;
- };
- ...
- };
diff --git a/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.yaml b/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.yaml
new file mode 100644
index 0000000..ffb2924
--- /dev/null
+++ b/dts/upstream/Bindings/regulator/sprd,sc2731-regulator.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/sprd,sc2731-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC2731 Power Management IC regulators
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+description: |
+ The SC2731 integrates low-voltage and low quiescent current DCDC/LDO.
+ 14 LDO and 3 DCDCs are designed for external use. All DCDCs/LDOs have
+ their own bypass (power-down) control signals. It is recommended to use
+ external tantalum or MLCC ceramic capacitors with these LDOs.
+ Valid names for the regulators are:
+ BUCK:
+ BUCK_CPU0, BUCK_CPU1, BUCK_RF
+ LDO:
+ LDO_CAMA0, LDO_CAMA1, LDO_CAMD0, LDO_CAMD1, LDO_CAMIO, LDO_CAMMOT,
+ LDO_CON, LDO_EMMCCORE, LDO_SDCORE, LDO_SDIO, LDO_SRAM, LDO_USB33,
+ LDO_VLDO, LDO_WIFIPA
+
+properties:
+ compatible:
+ const: sprd,sc2731-regulator
+
+patternProperties:
+ "^BUCK_(CPU[0-1]|RF)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+ "^LDO_(CAM(A0|A1|D0|D1|IO|MOT)|CON|EMMCCORE|SD(CORE|IO)|SRAM|USB33|VLDO|WIFIPA)$":
+ type: object
+ $ref: regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ regulators {
+ compatible = "sprd,sc2731-regulator";
+
+ BUCK_CPU0 {
+ regulator-name = "vddarm0";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1996875>;
+ regulator-ramp-delay = <25000>;
+ regulator-always-on;
+ };
+
+ LDO_CAMA0 {
+ regulator-name = "vddcama0";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3750000>;
+ regulator-enable-ramp-delay = <100>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/regulator/st,stm32mp1-pwr-reg.yaml b/dts/upstream/Bindings/regulator/st,stm32mp1-pwr-reg.yaml
index c9586d2..3cb2dad 100644
--- a/dts/upstream/Bindings/regulator/st,stm32mp1-pwr-reg.yaml
+++ b/dts/upstream/Bindings/regulator/st,stm32mp1-pwr-reg.yaml
@@ -11,7 +11,12 @@
properties:
compatible:
- const: st,stm32mp1,pwr-reg
+ oneOf:
+ - items:
+ - const: st,stm32mp1,pwr-reg
+ - items:
+ - const: st,stm32mp13-pwr-reg
+ - const: st,stm32mp1,pwr-reg
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/regulator/ti,tps65132.yaml b/dts/upstream/Bindings/regulator/ti,tps65132.yaml
index 6a6d1a3..873d927 100644
--- a/dts/upstream/Bindings/regulator/ti,tps65132.yaml
+++ b/dts/upstream/Bindings/regulator/ti,tps65132.yaml
@@ -23,6 +23,8 @@
reg:
maxItems: 1
+ vin-supply: true
+
patternProperties:
"^out[pn]$":
type: object
@@ -65,6 +67,7 @@
regulator@3e {
compatible = "ti,tps65132";
reg = <0x3e>;
+ vin-supply = <&supply>;
outp {
regulator-name = "outp";
diff --git a/dts/upstream/Bindings/regulator/twl-regulator.txt b/dts/upstream/Bindings/regulator/twl-regulator.txt
deleted file mode 100644
index 549f804..0000000
--- a/dts/upstream/Bindings/regulator/twl-regulator.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-TWL family of regulators
-
-Required properties:
-For twl6030 regulators/LDOs
-- compatible:
- - "ti,twl6030-vaux1" for VAUX1 LDO
- - "ti,twl6030-vaux2" for VAUX2 LDO
- - "ti,twl6030-vaux3" for VAUX3 LDO
- - "ti,twl6030-vmmc" for VMMC LDO
- - "ti,twl6030-vpp" for VPP LDO
- - "ti,twl6030-vusim" for VUSIM LDO
- - "ti,twl6030-vana" for VANA LDO
- - "ti,twl6030-vcxio" for VCXIO LDO
- - "ti,twl6030-vdac" for VDAC LDO
- - "ti,twl6030-vusb" for VUSB LDO
- - "ti,twl6030-v1v8" for V1V8 LDO
- - "ti,twl6030-v2v1" for V2V1 LDO
- - "ti,twl6030-vdd1" for VDD1 SMPS
- - "ti,twl6030-vdd2" for VDD2 SMPS
- - "ti,twl6030-vdd3" for VDD3 SMPS
-For twl6032 regulators/LDOs
-- compatible:
- - "ti,twl6032-ldo1" for LDO1 LDO
- - "ti,twl6032-ldo2" for LDO2 LDO
- - "ti,twl6032-ldo3" for LDO3 LDO
- - "ti,twl6032-ldo4" for LDO4 LDO
- - "ti,twl6032-ldo5" for LDO5 LDO
- - "ti,twl6032-ldo6" for LDO6 LDO
- - "ti,twl6032-ldo7" for LDO7 LDO
- - "ti,twl6032-ldoln" for LDOLN LDO
- - "ti,twl6032-ldousb" for LDOUSB LDO
- - "ti,twl6032-smps3" for SMPS3 SMPS
- - "ti,twl6032-smps4" for SMPS4 SMPS
- - "ti,twl6032-vio" for VIO SMPS
-For twl4030 regulators/LDOs
-- compatible:
- - "ti,twl4030-vaux1" for VAUX1 LDO
- - "ti,twl4030-vaux2" for VAUX2 LDO
- - "ti,twl5030-vaux2" for VAUX2 LDO
- - "ti,twl4030-vaux3" for VAUX3 LDO
- - "ti,twl4030-vaux4" for VAUX4 LDO
- - "ti,twl4030-vmmc1" for VMMC1 LDO
- - "ti,twl4030-vmmc2" for VMMC2 LDO
- - "ti,twl4030-vpll1" for VPLL1 LDO
- - "ti,twl4030-vpll2" for VPLL2 LDO
- - "ti,twl4030-vsim" for VSIM LDO
- - "ti,twl4030-vdac" for VDAC LDO
- - "ti,twl4030-vintana2" for VINTANA2 LDO
- - "ti,twl4030-vio" for VIO LDO
- - "ti,twl4030-vdd1" for VDD1 SMPS
- - "ti,twl4030-vdd2" for VDD2 SMPS
- - "ti,twl4030-vintana1" for VINTANA1 LDO
- - "ti,twl4030-vintdig" for VINTDIG LDO
- - "ti,twl4030-vusb1v5" for VUSB1V5 LDO
- - "ti,twl4030-vusb1v8" for VUSB1V8 LDO
- - "ti,twl4030-vusb3v1" for VUSB3V1 LDO
-
-Optional properties:
-- Any optional property defined in bindings/regulator/regulator.txt
-For twl4030 regulators/LDOs:
- - regulator-initial-mode:
- - 0x08 - Sleep mode, the nominal output voltage is maintained with low power
- consumption with low load current capability.
- - 0x0e - Active mode, the regulator can deliver its nominal output voltage
- with full-load current capability.
-
-Example:
-
- xyz: regulator@0 {
- compatible = "ti,twl6030-vaux1";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- };
-
-For twl6030 regulators/LDOs:
-
- - ti,retain-on-reset: Does not turn off the supplies during warm
- reset. Could be needed for VMMC, as TWL6030
- reset sequence for this signal does not comply
- with the SD specification.
diff --git a/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml b/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
index df36e29..57d75ac 100644
--- a/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
+++ b/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
@@ -59,6 +59,7 @@
maxItems: 32
power-domains:
+ minItems: 2
maxItems: 8
fsl,auto-boot:
@@ -99,6 +100,20 @@
properties:
fsl,iomuxc-gpr: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-cm4
+ - fsl,imx8qm-cm4
+ then:
+ required:
+ - power-domains
+ else:
+ properties:
+ power-domains: false
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/remoteproc/qcom,rpm-proc.yaml b/dts/upstream/Bindings/remoteproc/qcom,rpm-proc.yaml
index 7afafde..61cf4fe 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,rpm-proc.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,rpm-proc.yaml
@@ -8,7 +8,7 @@
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
- Stephan Gerhold <stephan@gerhold.net>
description: |
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
new file mode 100644
index 0000000..7fe401a
--- /dev/null
+++ b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8775p Peripheral Authentication Service
+
+maintainers:
+ - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+
+description:
+ Qualcomm SA8775p SoC Peripheral Authentication Service loads and boots firmware
+ on the Qualcomm DSP Hexagon cores.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-adsp-pas
+ - qcom,sa8775p-cdsp0-pas
+ - qcom,sa8775p-cdsp1-pas
+ - qcom,sa8775p-gpdsp0-pas
+ - qcom,sa8775p-gpdsp1-pas
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM.
+
+ firmware-name:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ items:
+ - description: Firmware name of the Hexagon core
+
+ memory-region:
+ items:
+ - description: Memory region for main Firmware authentication
+
+ interrupts:
+ maxItems: 5
+
+ interrupt-names:
+ maxItems: 5
+
+required:
+ - compatible
+ - reg
+ - memory-region
+
+allOf:
+ - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-adsp-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: LCX power domain
+ - description: LMX power domain
+ power-domain-names:
+ items:
+ - const: lcx
+ - const: lmx
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-cdsp0-pas
+ - qcom,sa8775p-cdsp1-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MXC power domain
+ - description: NSP0 power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mxc
+ - const: nsp
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sa8775p-gpdsp0-pas
+ - qcom,sa8775p-gpdsp1-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MXC power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mxc
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/mailbox/qcom-ipcc.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ remoteproc@30000000 {
+ compatible = "qcom,sa8775p-adsp-pas";
+ reg = <0x30000000 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>, <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+ memory-region = <&pil_adsp_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/remoteproc/ti,k3-dsp-rproc.yaml b/dts/upstream/Bindings/remoteproc/ti,k3-dsp-rproc.yaml
index 9768db86..b51bb86 100644
--- a/dts/upstream/Bindings/remoteproc/ti,k3-dsp-rproc.yaml
+++ b/dts/upstream/Bindings/remoteproc/ti,k3-dsp-rproc.yaml
@@ -25,9 +25,6 @@
host processor (Arm CorePac) to perform the device management of the remote
processor and to communicate with the remote processor.
-allOf:
- - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
-
properties:
compatible:
enum:
@@ -89,41 +86,57 @@
should be defined as per the generic bindings in,
Documentation/devicetree/bindings/sram/sram.yaml
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j721e-c66-dsp
+ then:
+ properties:
+ reg:
+ items:
+ - description: Address and Size of the L2 SRAM internal memory region
+ - description: Address and Size of the L1 PRAM internal memory region
+ - description: Address and Size of the L1 DRAM internal memory region
+ reg-names:
+ items:
+ - const: l2sram
+ - const: l1pram
+ - const: l1dram
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j721e-c71-dsp
+ - ti,j721s2-c71-dsp
+ then:
+ properties:
+ reg:
+ items:
+ - description: Address and Size of the L2 SRAM internal memory region
+ - description: Address and Size of the L1 DRAM internal memory region
+ reg-names:
+ items:
+ - const: l2sram
+ - const: l1dram
+
-if:
- properties:
- compatible:
- enum:
- - ti,j721e-c66-dsp
-then:
- properties:
- reg:
- items:
- - description: Address and Size of the L2 SRAM internal memory region
- - description: Address and Size of the L1 PRAM internal memory region
- - description: Address and Size of the L1 DRAM internal memory region
- reg-names:
- items:
- - const: l2sram
- - const: l1pram
- - const: l1dram
-else:
- if:
- properties:
- compatible:
- enum:
- - ti,am62a-c7xv-dsp
- - ti,j721e-c71-dsp
- - ti,j721s2-c71-dsp
- then:
- properties:
- reg:
- items:
- - description: Address and Size of the L2 SRAM internal memory region
- - description: Address and Size of the L1 DRAM internal memory region
- reg-names:
- items:
- - const: l2sram
- - const: l1dram
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am62a-c7xv-dsp
+ then:
+ properties:
+ reg:
+ items:
+ - description: Address and Size of the L2 SRAM internal memory region
+ reg-names:
+ items:
+ - const: l2sram
+
+ - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
required:
- compatible
diff --git a/dts/upstream/Bindings/reset/nuvoton,ma35d1-reset.yaml b/dts/upstream/Bindings/reset/nuvoton,ma35d1-reset.yaml
index 34c5c1c..3ce7dce 100644
--- a/dts/upstream/Bindings/reset/nuvoton,ma35d1-reset.yaml
+++ b/dts/upstream/Bindings/reset/nuvoton,ma35d1-reset.yaml
@@ -18,6 +18,7 @@
compatible:
items:
- const: nuvoton,ma35d1-reset
+ - const: syscon
reg:
maxItems: 1
@@ -37,7 +38,7 @@
- |
system-management@40460000 {
- compatible = "nuvoton,ma35d1-reset";
+ compatible = "nuvoton,ma35d1-reset", "syscon";
reg = <0x40460000 0x200>;
#reset-cells = <1>;
};
diff --git a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
index 03c1861..b0b20af 100644
--- a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
+++ b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -42,6 +42,12 @@
0 = Port 1 Phy reset
1 = Port 2 Phy reset
+ regulator-vbus:
+ type: object
+ description: USB VBUS regulator
+ $ref: /schemas/regulator/regulator.yaml#
+ unevaluatedProperties: false
+
required:
- compatible
- reg
@@ -49,6 +55,7 @@
- resets
- power-domains
- '#reset-cells'
+ - regulator-vbus
additionalProperties: false
@@ -64,4 +71,7 @@
resets = <&cpg R9A07G044_USB_PRESETN>;
power-domains = <&cpg>;
#reset-cells = <1>;
+ regulator-vbus {
+ regulator-name = "vbus";
+ };
};
diff --git a/dts/upstream/Bindings/reset/ti,sci-reset.yaml b/dts/upstream/Bindings/reset/ti,sci-reset.yaml
index e10eb98..1db08ce 100644
--- a/dts/upstream/Bindings/reset/ti,sci-reset.yaml
+++ b/dts/upstream/Bindings/reset/ti,sci-reset.yaml
@@ -37,7 +37,7 @@
The second cell should contain the reset mask corresponding to the device
used by system controller.
- Please see http://processors.wiki.ti.com/index.php/TISCI for
+ Please see https://software-dl.ti.com/tisci/esd/latest/index.html for
protocol documentation for the values to be used for different devices.
diff --git a/dts/upstream/Bindings/riscv/cpus.yaml b/dts/upstream/Bindings/riscv/cpus.yaml
index d87dd50..8edc826 100644
--- a/dts/upstream/Bindings/riscv/cpus.yaml
+++ b/dts/upstream/Bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@
- sifive,u74
- sifive,u74-mc
- thead,c906
+ - thead,c908
- thead,c910
- thead,c920
- const: riscv
@@ -102,26 +103,7 @@
interrupt-controller:
type: object
- additionalProperties: false
- description: Describes the CPU's local interrupt controller
-
- properties:
- '#interrupt-cells':
- const: 1
-
- compatible:
- oneOf:
- - items:
- - const: andestech,cpu-intc
- - const: riscv,cpu-intc
- - const: riscv,cpu-intc
-
- interrupt-controller: true
-
- required:
- - '#interrupt-cells'
- - compatible
- - interrupt-controller
+ $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#
cpu-idle-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
diff --git a/dts/upstream/Bindings/riscv/extensions.yaml b/dts/upstream/Bindings/riscv/extensions.yaml
index 468c646..a06dbc6 100644
--- a/dts/upstream/Bindings/riscv/extensions.yaml
+++ b/dts/upstream/Bindings/riscv/extensions.yaml
@@ -177,6 +177,13 @@
is supported as ratified at commit 5059e0ca641c ("update to
ratified") of the riscv-zacas.
+ - const: zawrs
+ description: |
+ The Zawrs extension for entering a low-power state or for trapping
+ to a hypervisor while waiting on a store to a memory location, as
+ ratified in commit 98918c844281 ("Merge pull request #1217 from
+ riscv/zawrs") of riscv-isa-manual.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
@@ -220,6 +227,43 @@
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zca
+ description: |
+ The Zca extension part of Zc* standard extensions for code size
+ reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
+ RV64 as it contains no instructions") of riscv-code-size-reduction,
+ merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
+ of zc.adoc to src tree.").
+
+ - const: zcb
+ description: |
+ The Zcb extension part of Zc* standard extensions for code size
+ reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
+ RV64 as it contains no instructions") of riscv-code-size-reduction,
+ merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
+ of zc.adoc to src tree.").
+
+ - const: zcd
+ description: |
+ The Zcd extension part of Zc* standard extensions for code size
+ reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
+ RV64 as it contains no instructions") of riscv-code-size-reduction,
+ merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
+ of zc.adoc to src tree.").
+
+ - const: zcf
+ description: |
+ The Zcf extension part of Zc* standard extensions for code size
+ reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
+ RV64 as it contains no instructions") of riscv-code-size-reduction,
+ merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
+ of zc.adoc to src tree.").
+
+ - const: zcmop
+ description:
+ The standard Zcmop extension version 1.0, as ratified in commit
+ c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
+
- const: zfa
description:
The standard Zfa extension for additional floating point
@@ -363,6 +407,11 @@
ratified in the 20191213 version of the unprivileged ISA
specification.
+ - const: zimop
+ description:
+ The standard Zimop extension version 1.0, as ratified in commit
+ 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
+
- const: ztso
description:
The standard Ztso extension for total store ordering, as ratified
@@ -381,6 +430,36 @@
instructions, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: zve32f
+ description:
+ The standard Zve32f extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve32x
+ description:
+ The standard Zve32x extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64d
+ description:
+ The standard Zve64d extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64f
+ description:
+ The standard Zve64f extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
+ - const: zve64x
+ description:
+ The standard Zve64x extension for embedded processors, as ratified
+ in commit 6f702a2 ("Vector extensions are now ratified") of
+ riscv-v-spec.
+
- const: zvfh
description:
The standard Zvfh extension for vectored half-precision
@@ -484,5 +563,58 @@
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ allOf:
+ # Zcb depends on Zca
+ - if:
+ contains:
+ const: zcb
+ then:
+ contains:
+ const: zca
+ # Zcd depends on Zca and D
+ - if:
+ contains:
+ const: zcd
+ then:
+ allOf:
+ - contains:
+ const: zca
+ - contains:
+ const: d
+ # Zcf depends on Zca and F
+ - if:
+ contains:
+ const: zcf
+ then:
+ allOf:
+ - contains:
+ const: zca
+ - contains:
+ const: f
+ # Zcmop depends on Zca
+ - if:
+ contains:
+ const: zcmop
+ then:
+ contains:
+ const: zca
+
+allOf:
+ # Zcf extension does not exist on rv64
+ - if:
+ properties:
+ riscv,isa-extensions:
+ contains:
+ const: zcf
+ riscv,isa-base:
+ contains:
+ const: rv64i
+ then:
+ properties:
+ riscv,isa-extensions:
+ not:
+ contains:
+ const: zcf
+
additionalProperties: true
...
diff --git a/dts/upstream/Bindings/riscv/microchip.yaml b/dts/upstream/Bindings/riscv/microchip.yaml
index 4a29c89..78ce76a 100644
--- a/dts/upstream/Bindings/riscv/microchip.yaml
+++ b/dts/upstream/Bindings/riscv/microchip.yaml
@@ -29,6 +29,7 @@
- enum:
- aldec,tysom-m-mpfs250t-rev2
- aries,m100pfsevp
+ - beagle,beaglev-fire
- microchip,mpfs-sev-kit
- sundance,polarberry
- const: microchip,mpfs
diff --git a/dts/upstream/Bindings/riscv/starfive.yaml b/dts/upstream/Bindings/riscv/starfive.yaml
index b672f85..4d5c857 100644
--- a/dts/upstream/Bindings/riscv/starfive.yaml
+++ b/dts/upstream/Bindings/riscv/starfive.yaml
@@ -27,6 +27,7 @@
- items:
- enum:
- milkv,mars
+ - pine64,star64
- starfive,visionfive-2-v1.2a
- starfive,visionfive-2-v1.3b
- const: starfive,jh7110
diff --git a/dts/upstream/Bindings/rng/amlogic,meson-rng.yaml b/dts/upstream/Bindings/rng/amlogic,meson-rng.yaml
index afa52af..f03b87e 100644
--- a/dts/upstream/Bindings/rng/amlogic,meson-rng.yaml
+++ b/dts/upstream/Bindings/rng/amlogic,meson-rng.yaml
@@ -26,6 +26,9 @@
items:
- const: core
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml b/dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml
index 765d9f9..1a71935 100644
--- a/dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml
+++ b/dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml
@@ -12,14 +12,17 @@
properties:
compatible:
- const: samsung,exynos5250-trng
+ enum:
+ - samsung,exynos5250-trng
+ - samsung,exynos850-trng
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clock-names:
- items:
- - const: secss
+ minItems: 1
+ maxItems: 2
reg:
maxItems: 1
@@ -30,6 +33,35 @@
- clock-names
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-trng
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SSS (Security Sub System) operating clock
+ - description: SSS (Security Sub System) bus clock
+
+ clock-names:
+ items:
+ - const: secss
+ - const: pclk
+
+ else:
+ properties:
+ clocks:
+ items:
+ - description: SSS (Security Sub System) operating clock
+
+ clock-names:
+ items:
+ - const: secss
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/rtc/fsl,ls-ftm-alarm.yaml b/dts/upstream/Bindings/rtc/fsl,ls-ftm-alarm.yaml
new file mode 100644
index 0000000..388102a
--- /dev/null
+++ b/dts/upstream/Bindings/rtc/fsl,ls-ftm-alarm.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/fsl,ls-ftm-alarm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale FlexTimer Module (FTM) Alarm
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1012a-ftm-alarm
+ - fsl,ls1021a-ftm-alarm
+ - fsl,ls1028a-ftm-alarm
+ - fsl,ls1043a-ftm-alarm
+ - fsl,ls1046a-ftm-alarm
+ - fsl,ls1088a-ftm-alarm
+ - fsl,ls208xa-ftm-alarm
+ - fsl,lx2160a-ftm-alarm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,rcpm-wakeup:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to rcpm node
+ - description: bit mask of IPPDEXPCR0
+ - description: bit mask of IPPDEXPCR1
+ - description: bit mask of IPPDEXPCR2
+ - description: bit mask of IPPDEXPCR3
+ - description: bit mask of IPPDEXPCR4
+ - description: bit mask of IPPDEXPCR5
+ - description: bit mask of IPPDEXPCR6
+ minItems: 1
+ description:
+ phandle to rcpm node, Please refer
+ Documentation/devicetree/bindings/soc/fsl/rcpm.txt
+
+ big-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ If the host controller is big-endian mode, specify this property.
+ The default endian mode is little-endian.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - fsl,rcpm-wakeup
+
+allOf:
+ - $ref: rtc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtc@2800000 {
+ compatible = "fsl,ls1088a-ftm-alarm";
+ reg = <0x2800000 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/upstream/Bindings/rtc/rtc-fsl-ftm-alarm.txt b/dts/upstream/Bindings/rtc/rtc-fsl-ftm-alarm.txt
deleted file mode 100644
index fffac74..0000000
--- a/dts/upstream/Bindings/rtc/rtc-fsl-ftm-alarm.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Freescale FlexTimer Module (FTM) Alarm
-
-Required properties:
-- compatible : Should be "fsl,<chip>-ftm-alarm", the
- supported chips include
- "fsl,ls1012a-ftm-alarm"
- "fsl,ls1021a-ftm-alarm"
- "fsl,ls1028a-ftm-alarm"
- "fsl,ls1043a-ftm-alarm"
- "fsl,ls1046a-ftm-alarm"
- "fsl,ls1088a-ftm-alarm"
- "fsl,ls208xa-ftm-alarm"
- "fsl,lx2160a-ftm-alarm"
-- reg : Specifies base physical address and size of the register sets for the
- FlexTimer Module.
-- interrupts : Should be the FlexTimer Module interrupt.
-- fsl,rcpm-wakeup property and rcpm node : Please refer
- Documentation/devicetree/bindings/soc/fsl/rcpm.txt
-
-Optional properties:
-- big-endian: If the host controller is big-endian mode, specify this property.
- The default endian mode is little-endian.
-
-Example:
-rcpm: rcpm@1e34040 {
- compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
- reg = <0x0 0x1e34040 0x0 0x18>;
- #fsl,rcpm-wakeup-cells = <6>;
-};
-
-ftm_alarm0: timer@2800000 {
- compatible = "fsl,ls1088a-ftm-alarm";
- reg = <0x0 0x2800000 0x0 0x10000>;
- fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
- interrupts = <0 44 4>;
-};
diff --git a/dts/upstream/Bindings/rtc/st,stm32-rtc.yaml b/dts/upstream/Bindings/rtc/st,stm32-rtc.yaml
index 4703083..7a0fab7 100644
--- a/dts/upstream/Bindings/rtc/st,stm32-rtc.yaml
+++ b/dts/upstream/Bindings/rtc/st,stm32-rtc.yaml
@@ -15,6 +15,7 @@
- st,stm32-rtc
- st,stm32h7-rtc
- st,stm32mp1-rtc
+ - st,stm32mp25-rtc
reg:
maxItems: 1
@@ -90,7 +91,9 @@
properties:
compatible:
contains:
- const: st,stm32mp1-rtc
+ enum:
+ - st,stm32mp1-rtc
+ - st,stm32mp25-rtc
then:
properties:
diff --git a/dts/upstream/Bindings/serial/mediatek,uart.yaml b/dts/upstream/Bindings/serial/mediatek,uart.yaml
index 303d02c..ff61ffd 100644
--- a/dts/upstream/Bindings/serial/mediatek,uart.yaml
+++ b/dts/upstream/Bindings/serial/mediatek,uart.yaml
@@ -37,6 +37,7 @@
- mediatek,mt7623-uart
- mediatek,mt7629-uart
- mediatek,mt7986-uart
+ - mediatek,mt7988-uart
- mediatek,mt8127-uart
- mediatek,mt8135-uart
- mediatek,mt8173-uart
diff --git a/dts/upstream/Bindings/serial/mrvl,pxa-ssp.txt b/dts/upstream/Bindings/serial/mrvl,pxa-ssp.txt
deleted file mode 100644
index d10cc06..0000000
--- a/dts/upstream/Bindings/serial/mrvl,pxa-ssp.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-Device tree bindings for Marvell PXA SSP ports
-
-Required properties:
-
- - compatible: Must be one of
- mrvl,pxa25x-ssp
- mvrl,pxa25x-nssp
- mrvl,pxa27x-ssp
- mrvl,pxa3xx-ssp
- mvrl,pxa168-ssp
- mrvl,pxa910-ssp
- mrvl,ce4100-ssp
-
- - reg: The memory base
- - dmas: Two dma phandles, one for rx, one for tx
- - dma-names: Must be "rx", "tx"
-
-
-Example for PXA3xx:
-
- ssp0: ssp@41000000 {
- compatible = "mrvl,pxa3xx-ssp";
- reg = <0x41000000 0x40>;
- ssp-id = <1>;
- interrupts = <24>;
- clock-names = "pxa27x-ssp.0";
- dmas = <&dma 13
- &dma 14>;
- dma-names = "rx", "tx";
- };
-
- ssp1: ssp@41700000 {
- compatible = "mrvl,pxa3xx-ssp";
- reg = <0x41700000 0x40>;
- ssp-id = <2>;
- interrupts = <16>;
- clock-names = "pxa27x-ssp.1";
- dmas = <&dma 15
- &dma 16>;
- dma-names = "rx", "tx";
- };
-
- ssp2: ssp@41900000 {
- compatibl3 = "mrvl,pxa3xx-ssp";
- reg = <0x41900000 0x40>;
- ssp-id = <3>;
- interrupts = <0>;
- clock-names = "pxa27x-ssp.2";
- dmas = <&dma 66
- &dma 67>;
- dma-names = "rx", "tx";
- };
-
- ssp3: ssp@41a00000 {
- compatible = "mrvl,pxa3xx-ssp";
- reg = <0x41a00000 0x40>;
- ssp-id = <4>;
- interrupts = <13>;
- clock-names = "pxa27x-ssp.3";
- dmas = <&dma 2
- &dma 3>;
- dma-names = "rx", "tx";
- };
-
diff --git a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
index 5dec15b..8887148 100644
--- a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
+++ b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
@@ -28,6 +28,9 @@
clocks:
maxItems: 1
+ reset-gpios:
+ maxItems: 1
+
clock-frequency:
description:
When there is no clock provider visible to the platform, this
@@ -91,6 +94,7 @@
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -120,6 +124,7 @@
compatible = "nxp,sc16is752";
reg = <0x54>;
clocks = <&clk20m>;
+ reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */
diff --git a/dts/upstream/Bindings/serial/renesas,scif.yaml b/dts/upstream/Bindings/serial/renesas,scif.yaml
index f3a3eb2..afc7c05 100644
--- a/dts/upstream/Bindings/serial/renesas,scif.yaml
+++ b/dts/upstream/Bindings/serial/renesas,scif.yaml
@@ -9,9 +9,6 @@
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
@@ -83,6 +80,8 @@
- renesas,scif-r9a08g045 # RZ/G3S
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
+ - const: renesas,scif-r9a09g057 # RZ/V2H(P)
+
reg:
maxItems: 1
@@ -95,28 +94,25 @@
- description: Receive buffer full interrupt
- description: Transmit buffer empty interrupt
- description: Break interrupt
- - items:
- - description: Error interrupt
- - description: Receive buffer full interrupt
- - description: Transmit buffer empty interrupt
- - description: Break interrupt
- description: Data Ready interrupt
- description: Transmit End interrupt
+ - description: Transmit End/Data Ready interrupt
+ - description: Receive buffer full interrupt (EDGE trigger)
+ - description: Transmit buffer empty interrupt (EDGE trigger)
+ minItems: 4
interrupt-names:
- oneOf:
- - items:
- - const: eri
- - const: rxi
- - const: txi
- - const: bri
- - items:
- - const: eri
- - const: rxi
- - const: txi
- - const: bri
- - const: dri
- - const: tei
+ minItems: 4
+ items:
+ - const: eri
+ - const: rxi
+ - const: txi
+ - const: bri
+ - const: dri
+ - const: tei
+ - const: tei-dri
+ - const: rxi-edge
+ - const: txi-edge
clocks:
minItems: 1
@@ -161,18 +157,92 @@
- clock-names
- power-domains
-if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,rcar-gen2-scif
- - renesas,rcar-gen3-scif
- - renesas,rcar-gen4-scif
- - renesas,scif-r9a07g044
-then:
- required:
- - resets
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-scif
+ - renesas,rcar-gen3-scif
+ - renesas,rcar-gen4-scif
+ - renesas,scif-r9a07g044
+ - renesas,scif-r9a09g057
+ then:
+ required:
+ - resets
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen1-scif
+ - renesas,rcar-gen2-scif
+ - renesas,rcar-gen3-scif
+ - renesas,rcar-gen4-scif
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+
+ interrupt-names: false
+ else:
+ required:
+ - interrupt-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,scif-r7s72100
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+ interrupt-names:
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,scif-r7s9210
+ - renesas,scif-r9a07g044
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
+ interrupt-names:
+ minItems: 6
+ maxItems: 6
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,scif-r9a09g057
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ interrupts:
+ minItems: 9
+
+ interrupt-names:
+ minItems: 9
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
index 1001d2a..4cdb0dc 100644
--- a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
+++ b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
@@ -13,6 +13,20 @@
- $ref: serial.yaml#
- $ref: rs485.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jh7110-uart
+ then:
+ properties:
+ resets:
+ minItems: 2
+ else:
+ properties:
+ resets:
+ maxItems: 1
+
properties:
compatible:
oneOf:
@@ -48,6 +62,7 @@
- enum:
- starfive,jh7100-hsuart
- starfive,jh7100-uart
+ - starfive,jh7110-uart
- const: snps,dw-apb-uart
- const: snps,dw-apb-uart
@@ -82,7 +97,8 @@
type: boolean
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reg-shift: true
diff --git a/dts/upstream/Bindings/serial/via,vt8500-uart.yaml b/dts/upstream/Bindings/serial/via,vt8500-uart.yaml
new file mode 100644
index 0000000..9c68192
--- /dev/null
+++ b/dts/upstream/Bindings/serial/via,vt8500-uart.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/via,vt8500-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VIA VT8500 and WonderMedia WM8xxx UART Controller
+
+maintainers:
+ - Alexey Charkov <alchark@gmail.com>
+
+allOf:
+ - $ref: serial.yaml
+
+properties:
+ compatible:
+ enum:
+ - via,vt8500-uart # up to WM8850/WM8950
+ - wm,wm8880-uart # for WM8880 and later
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - interrupts
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial@d8200000 {
+ compatible = "via,vt8500-uart";
+ reg = <0xd8200000 0x1040>;
+ interrupts = <32>;
+ clocks = <&clkuart0>;
+ };
diff --git a/dts/upstream/Bindings/serial/vt8500-uart.txt b/dts/upstream/Bindings/serial/vt8500-uart.txt
deleted file mode 100644
index 2b64e61..0000000
--- a/dts/upstream/Bindings/serial/vt8500-uart.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* VIA VT8500 and WonderMedia WM8xxx UART Controller
-
-Required properties:
-- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
- including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
-
-- reg: base physical address of the controller and length of memory mapped
- region.
-
-- interrupts: hardware interrupt number
-
-- clocks: shall be the input parent clock phandle for the clock. This should
- be the 24Mhz reference clock.
-
-Aliases may be defined to ensure the correct ordering of the uarts.
-
-Example:
- aliases {
- serial0 = &uart0;
- };
-
- uart0: serial@d8200000 {
- compatible = "via,vt8500-uart";
- reg = <0xd8200000 0x1040>;
- interrupts = <32>;
- clocks = <&clkuart0>;
- };
diff --git a/dts/upstream/Bindings/soc/fsl/bman-portals.txt b/dts/upstream/Bindings/soc/fsl/bman-portals.txt
deleted file mode 100644
index 2a00e14..0000000
--- a/dts/upstream/Bindings/soc/fsl/bman-portals.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-QorIQ DPAA Buffer Manager Portals Device Tree Binding
-
-Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
-
-CONTENTS
-
- - BMan Portal
- - Example
-
-BMan Portal Node
-
-Portals are memory mapped interfaces to BMan that allow low-latency, lock-less
-interaction by software running on processor cores, accelerators and network
-interfaces with the BMan
-
-PROPERTIES
-
-- compatible
- Usage: Required
- Value type: <stringlist>
- Definition: Must include "fsl,bman-portal-<hardware revision>"
- May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
-
-- reg
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Two regions. The first is the cache-enabled region of
- the portal. The second is the cache-inhibited region of
- the portal
-
-- interrupts
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Standard property
-
-EXAMPLE
-
-The example below shows a (P4080) BMan portals container/bus node with two portals
-
- bman-portals@ff4000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0xf 0xf4000000 0x200000>;
-
- bman-portal@0 {
- compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
- reg = <0x0 0x4000>, <0x100000 0x1000>;
- interrupts = <105 2 0 0>;
- };
- bman-portal@4000 {
- compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
- reg = <0x4000 0x4000>, <0x101000 0x1000>;
- interrupts = <107 2 0 0>;
- };
- };
diff --git a/dts/upstream/Bindings/soc/fsl/bman.txt b/dts/upstream/Bindings/soc/fsl/bman.txt
deleted file mode 100644
index 48eed14..0000000
--- a/dts/upstream/Bindings/soc/fsl/bman.txt
+++ /dev/null
@@ -1,137 +0,0 @@
-QorIQ DPAA Buffer Manager Device Tree Bindings
-
-Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
-
-CONTENTS
-
- - BMan Node
- - BMan Private Memory Node
- - Example
-
-BMan Node
-
-The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
-BMan supports hardware allocation and deallocation of buffers belonging to pools
-originally created by software with configurable depletion thresholds. This
-binding covers the CCSR space programming model
-
-PROPERTIES
-
-- compatible
- Usage: Required
- Value type: <stringlist>
- Definition: Must include "fsl,bman"
- May include "fsl,<SoC>-bman"
-
-- reg
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Registers region within the CCSR address space
-
-The BMan revision information is located in the BMAN_IP_REV_1/2 registers which
-are located at offsets 0xbf8 and 0xbfc
-
-- interrupts
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Standard property. The error interrupt
-
-- fsl,bman-portals
- Usage: Required
- Value type: <phandle>
- Definition: Phandle to this BMan instance's portals
-
-- fsl,liodn
- Usage: See pamu.txt
- Value type: <prop-encoded-array>
- Definition: PAMU property used for static LIODN assignment
-
-- fsl,iommu-parent
- Usage: See pamu.txt
- Value type: <phandle>
- Definition: PAMU property used for dynamic LIODN assignment
-
- For additional details about the PAMU/LIODN binding(s) see pamu.txt
-
-Devices connected to a BMan instance via Direct Connect Portals (DCP) must link
-to the respective BMan instance
-
-- fsl,bman
- Usage: Required
- Value type: <prop-encoded-array>
- Description: List of phandle and DCP index pairs, to the BMan instance
- to which this device is connected via the DCP
-
-BMan Private Memory Node
-
-BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
-a node under the /reserved-memory node.
-
-The BMan FBPR memory node must be named "bman-fbpr"
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: PPC platforms: Must include "fsl,bman-fbpr"
- ARM platforms: Must include "shared-dma-pool"
- as well as the "no-map" property
-
-The following constraints are relevant to the FBPR private memory:
- - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
- 16 GiB
- - The alignment must be a muliptle of the memory size
-
-The size of the FBPR must be chosen by observing the hardware features configured
-via the Reset Configuration Word (RCW) and that are relevant to a specific board
-(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports,
-etc.). The size configured in the DT must reflect the hardware capabilities and
-not the specific needs of an application
-
-For additional details about reserved memory regions see reserved-memory.txt
-
-EXAMPLE
-
-The example below shows a BMan FBPR dynamic allocation memory node
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- bman_fbpr: bman-fbpr {
- compatible = "shared-mem-pool";
- size = <0 0x1000000>;
- alignment = <0 0x1000000>;
- no-map;
- };
- };
-
-The example below shows a (P4080) BMan CCSR-space node
-
- bportals: bman-portals@ff4000000 {
- ...
- };
-
- crypto@300000 {
- ...
- fsl,bman = <&bman, 2>;
- ...
- };
-
- bman: bman@31a000 {
- compatible = "fsl,bman";
- reg = <0x31a000 0x1000>;
- interrupts = <16 2 1 2>;
- fsl,liodn = <0x17>;
- fsl,bman-portals = <&bportals>;
- memory-region = <&bman_fbpr>;
- };
-
- fman@400000 {
- ...
- fsl,bman = <&bman, 0>;
- ...
- };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml
new file mode 100644
index 0000000..53b07d4
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine module Firmware Node
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ This node defines a firmware binary that is embedded in the device tree, for
+ the purpose of passing the firmware from bootloader to the kernel, or from
+ the hypervisor to the guest.
+
+ The firmware node itself contains the firmware binary contents, a compatible
+ property, and any firmware-specific properties. The node should be placed
+ inside a QE node that needs it. Doing so eliminates the need for a
+ fsl,firmware-phandle property. Other QE nodes that need the same firmware
+ should define an fsl,firmware-phandle property that points to the firmware node
+ in the first QE node.
+
+ The fsl,firmware property can be specified in the DTS (possibly using incbin)
+ or can be inserted by the boot loader at boot time.
+
+properties:
+ compatible:
+ enum:
+ - fsl,qe-firmware
+
+ fsl,firmware:
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ description:
+ A standard property. This property contains the firmware binary "blob".
+
+required:
+ - compatible
+ - fsl,firmware
+
+additionalProperties: false
+
+examples:
+ - |
+ qe-firmware {
+ compatible = "fsl,qe-firmware";
+ fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml
new file mode 100644
index 0000000..8267ad0
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine module Interrupt Controller (IC)
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,qe-ic
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: QE interrupt
+ - description: QE critical
+ - description: QE error
+ minItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <95 2 0 0 94 2 0 0>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml
new file mode 100644
index 0000000..cf0f38d
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine Multi-User RAM (MURAM)
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: Multi-User RAM (MURAM)
+
+properties:
+ compatible:
+ items:
+ - const: fsl,qe-muram
+ - const: fsl,cpm-muram
+
+ ranges:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [host, slave]
+
+
+patternProperties:
+ '^data\-only@[a-f0-9]+$':
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: fsl,qe-muram-data
+ - const: fsl,cpm-muram-data
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ muram@10000 {
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0 0x00010000 0x0000c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ data-only@0{
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0 0xc000>;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml
new file mode 100644
index 0000000..8e58ab5
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine module Serial Interface Block (SI)
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ The SI manages the routing of eight TDM lines to the QE block serial drivers,
+ the MCC and the UCCs, for receive and transmit.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,ls1043-qe-si
+ - const: fsl,t1040-qe-si
+ - enum:
+ - fsl,t1040-qe-si
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ si@700 {
+ compatible = "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml
new file mode 100644
index 0000000..cc4ed48
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM)
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ store the routing entries of SI
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,ls1043-qe-siram
+ - const: fsl,t1040-qe-siram
+ - const: fsl,t1040-qe-siram
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ siram@1000 {
+ compatible = "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe.yaml b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe.yaml
new file mode 100644
index 0000000..89cdf5e
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/cpm_qe/fsl,qe.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale QUICC Engine module (QE)
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ This represents qe module that is installed on PowerQUICC II Pro.
+
+ NOTE: This is an interim binding; it should be updated to fit
+ in with the CPM binding later in this document.
+
+ Basically, it is a bus of devices, that could act more or less
+ as a complete entity (UCC, USB etc ). All of them should be siblings on
+ the "root" qe node, using the common properties from there.
+ The description below applies to the qe of MPC8360 and
+ more nodes and properties would be extended in the future.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,qe
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ maxItems: 1
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [QE, CPM, CPM2]
+
+ bus-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: the clock frequency for QUICC Engine.
+
+ fsl,qe-num-riscs:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: define how many RISC engines the QE has.
+
+ fsl,qe-snums:
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ maxItems: 28
+ description:
+ defining the array of serial number (SNUM) values for the virtual
+ threads.
+
+ fsl,firmware-phandle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ required only if there is no fsl,qe-firmware child node
+
+ Points to a firmware node (see "QE Firmware Node" below)
+ that contains the firmware that should be uploaded for this QE.
+ The compatible property for the firmware node should say,
+ "fsl,qe-firmware".
+
+ brg-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ the internal clock source frequency for baud-rate
+ generators in Hz.
+
+ fsl,qe-num-snums:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+ description: |
+ define how many serial number(SNUM) the QE can use
+ for the threads. Use fsl,qe-snums instead to not only specify the
+ number of snums, but also their values.
+
+patternProperties:
+ '^muram@[a-f0-9]+$':
+ $ref: fsl,qe-muram.yaml
+
+ '^interrupt-controller@[a-f0-9]+$':
+ $ref: fsl,qe-ic.yaml
+
+ '^si@[a-f0-9]+$':
+ $ref: fsl,qe-si.yaml
+
+ '^siram@[a-f0-9]+$':
+ $ref: fsl,qe-siram.yaml
+
+required:
+ - compatible
+ - reg
+ - bus-frequency
+
+allOf:
+ - $ref: /schemas/simple-bus.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ qe-bus@e0100000 {
+ compatible = "fsl,qe", "simple-bus";
+ reg = <0xe0100000 0x480>;
+ ranges = <0 0xe0100000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ brg-frequency = <0>;
+ bus-frequency = <0x179a7b00>;
+ fsl,qe-snums = /bits/ 8 <
+ 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d
+ 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89
+ 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9
+ 0xd8 0xd9 0xe8 0xe9>;
+
+ interrupt-controller@80 {
+ compatible = "fsl,qe-ic";
+ reg = <0x80 0x80>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <95 2 0 0 94 2 0 0>;
+ };
+
+ si@700 {
+ compatible = "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram@1000 {
+ compatible = "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ muram@10000 {
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0 0x00010000 0x0000c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ data-only@0{
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0 0xc000>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/cpm_qe/qe.txt b/dts/upstream/Bindings/soc/fsl/cpm_qe/qe.txt
deleted file mode 100644
index 05ec2a8..0000000
--- a/dts/upstream/Bindings/soc/fsl/cpm_qe/qe.txt
+++ /dev/null
@@ -1,178 +0,0 @@
-* Freescale QUICC Engine module (QE)
-This represents qe module that is installed on PowerQUICC II Pro.
-
-NOTE: This is an interim binding; it should be updated to fit
-in with the CPM binding later in this document.
-
-Basically, it is a bus of devices, that could act more or less
-as a complete entity (UCC, USB etc ). All of them should be siblings on
-the "root" qe node, using the common properties from there.
-The description below applies to the qe of MPC8360 and
-more nodes and properties would be extended in the future.
-
-i) Root QE device
-
-Required properties:
-- compatible : should be "fsl,qe";
-- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
-- reg : offset and length of the device registers.
-- bus-frequency : the clock frequency for QUICC Engine.
-- fsl,qe-num-riscs: define how many RISC engines the QE has.
-- fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
- defining the array of serial number (SNUM) values for the virtual
- threads.
-
-Optional properties:
-- fsl,firmware-phandle:
- Usage: required only if there is no fsl,qe-firmware child node
- Value type: <phandle>
- Definition: Points to a firmware node (see "QE Firmware Node" below)
- that contains the firmware that should be uploaded for this QE.
- The compatible property for the firmware node should say,
- "fsl,qe-firmware".
-
-Recommended properties
-- brg-frequency : the internal clock source frequency for baud-rate
- generators in Hz.
-
-Deprecated properties
-- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
- for the threads. Use fsl,qe-snums instead to not only specify the
- number of snums, but also their values.
-
-Example:
- qe@e0100000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- compatible = "fsl,qe";
- ranges = <0 e0100000 00100000>;
- reg = <e0100000 480>;
- brg-frequency = <0>;
- bus-frequency = <179A7B00>;
- fsl,qe-snums = /bits/ 8 <
- 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
- 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
- 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
- 0xD8 0xD9 0xE8 0xE9>;
- }
-
-* Multi-User RAM (MURAM)
-
-Required properties:
-- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
-- mode : the could be "host" or "slave".
-- ranges : Should be defined as specified in 1) to describe the
- translation of MURAM addresses.
-- data-only : sub-node which defines the address area under MURAM
- bus that can be allocated as data/parameter
-
-Example:
-
- muram@10000 {
- compatible = "fsl,qe-muram", "fsl,cpm-muram";
- ranges = <0 00010000 0000c000>;
-
- data-only@0{
- compatible = "fsl,qe-muram-data",
- "fsl,cpm-muram-data";
- reg = <0 c000>;
- };
- };
-
-* Interrupt Controller (IC)
-
-Required properties:
-- compatible : should be "fsl,qe-ic".
-- reg : Address range of IC register set.
-- interrupts : interrupts generated by the device.
-- interrupt-controller : this device is a interrupt controller.
-
-Example:
-
- qeic: interrupt-controller@80 {
- interrupt-controller;
- compatible = "fsl,qe-ic";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- reg = <0x80 0x80>;
- interrupts = <95 2 0 0 94 2 0 0>;
- };
-
-* Serial Interface Block (SI)
-
-The SI manages the routing of eight TDM lines to the QE block serial drivers
-, the MCC and the UCCs, for receive and transmit.
-
-Required properties:
-- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain
- "fsl,t1040-qe-si".
-- reg : Address range of SI register set.
-
-Example:
-
- si1: si@700 {
- compatible = "fsl,t1040-qe-si";
- reg = <0x700 0x80>;
- };
-
-* Serial Interface Block RAM(SIRAM)
-
-store the routing entries of SI
-
-Required properties:
-- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain
- "fsl,t1040-qe-siram".
-- reg : Address range of SI RAM.
-
-Example:
-
- siram1: siram@1000 {
- compatible = "fsl,t1040-qe-siram";
- reg = <0x1000 0x800>;
- };
-
-* QE Firmware Node
-
-This node defines a firmware binary that is embedded in the device tree, for
-the purpose of passing the firmware from bootloader to the kernel, or from
-the hypervisor to the guest.
-
-The firmware node itself contains the firmware binary contents, a compatible
-property, and any firmware-specific properties. The node should be placed
-inside a QE node that needs it. Doing so eliminates the need for a
-fsl,firmware-phandle property. Other QE nodes that need the same firmware
-should define an fsl,firmware-phandle property that points to the firmware node
-in the first QE node.
-
-The fsl,firmware property can be specified in the DTS (possibly using incbin)
-or can be inserted by the boot loader at boot time.
-
-Required properties:
- - compatible
- Usage: required
- Value type: <string>
- Definition: A standard property. Specify a string that indicates what
- kind of firmware it is. For QE, this should be "fsl,qe-firmware".
-
- - fsl,firmware
- Usage: required
- Value type: <prop-encoded-array>, encoded as an array of bytes
- Definition: A standard property. This property contains the firmware
- binary "blob".
-
-Example:
- qe1@e0080000 {
- compatible = "fsl,qe";
- qe_firmware:qe-firmware {
- compatible = "fsl,qe-firmware";
- fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
- };
- ...
- };
-
- qe2@e0090000 {
- compatible = "fsl,qe";
- fsl,firmware-phandle = <&qe_firmware>;
- ...
- };
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,bman-portal.yaml b/dts/upstream/Bindings/soc/fsl/fsl,bman-portal.yaml
new file mode 100644
index 0000000..8dce75b
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,bman-portal.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/fsl,bman-portal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QorIQ DPAA Queue Manager Portals
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ QorIQ DPAA Buffer Manager Portal
+
+ Portals are memory mapped interfaces to BMan that allow low-latency, lock-less
+ interaction by software running on processor cores, accelerators and network
+ interfaces with the BMan
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,bman-portal
+ - items:
+ - enum:
+ - fsl,bman-portal-1.0.0
+ - fsl,ls1043a-bmap-portal
+ - fsl,ls1046a-bmap-portal
+ - const: fsl,bman-portal
+ reg:
+ items:
+ - description: the cache-enabled region of the portal
+ - description: the cache-inhibited region of the portal
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
+ reg = <0x0 0x4000>, <0x100000 0x1000>;
+ interrupts = <105 IRQ_TYPE_EDGE_FALLING 0 0>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,bman.yaml b/dts/upstream/Bindings/soc/fsl/fsl,bman.yaml
new file mode 100644
index 0000000..e6f4682
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,bman.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/fsl,bman.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QorIQ DPAA Buffer Manager
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
+ BMan supports hardware allocation and deallocation of buffers belonging to
+ pools originally created by software with configurable depletion thresholds.
+ This binding covers the CCSR space programming model
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,bman
+ - items:
+ - enum:
+ - fsl,ls1043a-bman
+ - fsl,ls1046a-bman
+ - const: fsl,bman
+
+ reg:
+ items:
+ - description: |
+ Registers region within the CCSR address space
+
+ The BMan revision information is located in the BMAN_IP_REV_1/2
+ registers which are located at offsets 0xbf8 and 0xbfc
+
+ interrupts:
+ items:
+ - description: The error interrupt
+
+ memory-region:
+ minItems: 1
+ maxItems: 2
+ description:
+ List of phandles referencing the BMan private memory
+ nodes (described below). The bman-fqd node must be
+ first followed by bman-pfdr node. Only used on ARM
+
+ Devices connected to a BMan instance via Direct Connect Portals (DCP) must link
+ to the respective BMan instance
+
+ fsl,bman-portals:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: ref fsl,bman-port.yaml
+
+ fsl,liodn:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ See pamu.txt, PAMU property used for static LIODN assignment
+
+ fsl,iommu-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ See pamu.txt, PAMU property used for dynamic LIODN assignment
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ bman@31a000 {
+ compatible = "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 2>;
+ fsl,liodn = <0x17>;
+ fsl,bman-portals = <&bportals>;
+ memory-region = <&bman_fbpr>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/dts/upstream/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml
index ce1a650..3fb0534 100644
--- a/dts/upstream/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml
+++ b/dts/upstream/Bindings/soc/fsl/fsl,layerscape-dcfg.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Li Yang <leoyang.li@nxp.com>
description: |
DCFG is the device configuration unit, that provides general purpose
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,layerscape-scfg.yaml b/dts/upstream/Bindings/soc/fsl/fsl,layerscape-scfg.yaml
index a6a511b..2a456c8 100644
--- a/dts/upstream/Bindings/soc/fsl/fsl,layerscape-scfg.yaml
+++ b/dts/upstream/Bindings/soc/fsl/fsl,layerscape-scfg.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Li Yang <leoyang.li@nxp.com>
description: |
SCFG is the supplemental configuration unit, that provides SoC specific
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,ls1028a-reset.yaml b/dts/upstream/Bindings/soc/fsl/fsl,ls1028a-reset.yaml
new file mode 100644
index 0000000..31295be
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,ls1028a-reset.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Layerscape Reset Registers Module
+
+maintainers:
+ - Frank Li
+
+description:
+ Reset Module includes chip reset, service processor control and Reset Control
+ Word (RCW) status.
+
+properties:
+ $nodename:
+ pattern: "^syscon@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - fsl,ls1028a-reset
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ little-endian: true
+
+ reboot:
+ $ref: /schemas/power/reset/syscon-reboot.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reboot
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@1e60000 {
+ compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd";
+ reg = <0x1e60000 0x10000>;
+ little-endian;
+
+ reboot {
+ compatible = "syscon-reboot";
+ offset = <0>;
+ mask = <0x02>;
+ };
+ };
+
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,qman-fqd.yaml b/dts/upstream/Bindings/soc/fsl/fsl,qman-fqd.yaml
new file mode 100644
index 0000000..de0b4ae
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,qman-fqd.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-fqd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QMan Private Memory Nodes
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ QMan requires two contiguous range of physical memory used for the backing store
+ for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
+ This memory is reserved/allocated as a node under the /reserved-memory node.
+
+ BMan requires a contiguous range of physical memory used for the backing store
+ for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+ a node under the /reserved-memory node.
+
+ The QMan FQD memory node must be named "qman-fqd"
+ The QMan PFDR memory node must be named "qman-pfdr"
+ The BMan FBPR memory node must be named "bman-fbpr"
+
+ The following constraints are relevant to the FQD and PFDR private memory:
+ - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
+ 1 GiB
+ - The alignment must be a muliptle of the memory size
+
+ The size of the FQD and PFDP must be chosen by observing the hardware features
+ configured via the Reset Configuration Word (RCW) and that are relevant to a
+ specific board (e.g. number of MAC(s) pinned-out, number of offline/host command
+ FMan ports, etc.). The size configured in the DT must reflect the hardware
+ capabilities and not the specific needs of an application
+
+ For additional details about reserved memory regions see
+ reserved-memory/reserved-memory.yaml in dtschema project.
+
+properties:
+ $nodename:
+ pattern: '^(qman-fqd|qman-pfdr|bman-fbpr)+$'
+
+ compatible:
+ enum:
+ - fsl,qman-fqd
+ - fsl,qman-pfdr
+ - fsl,bman-fbpr
+
+required:
+ - compatible
+
+allOf:
+ - $ref: reserved-memory.yaml
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ qman-fqd {
+ compatible = "shared-dma-pool";
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ no-map;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,qman-portal.yaml b/dts/upstream/Bindings/soc/fsl/fsl,qman-portal.yaml
new file mode 100644
index 0000000..1701618
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,qman-portal.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QorIQ DPAA Queue Manager Portals
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
+ interaction by software running on processor cores, accelerators and network
+ interfaces with the QMan
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,qman-portal
+ - items:
+ - enum:
+ - fsl,ls1043-qman-portal
+ - fsl,ls1046-qman-portal
+ - fsl,qman-portal-1.2.0
+ - const: fsl,qman-portal
+
+ reg:
+ items:
+ - description: the cache-enabled region of the portal
+ - description: the cache-inhibited region of the portal
+
+ interrupts:
+ maxItems: 1
+
+ fsl,liodn:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: See pamu.txt. Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
+ (FLIODN)
+
+ fsl,iommu-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: See pamu.txt.
+
+ fsl,qman-channel-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: qman channel id.
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The hardware index of the channel. This can also be
+ determined by dividing any of the channel's 8 work queue
+ IDs by 8
+
+ In addition to these properties the qman-portals should have sub-nodes to
+ represent the HW devices/portals that are connected to the software portal
+ described here
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+patternProperties:
+ '^(fman0|fman1|pme|crypto)+$':
+ type: object
+ properties:
+ fsl,liodn:
+ description: See pamu.txt, PAMU property used for static LIODN assignment
+
+ fsl,iommu-parent:
+ description: See pamu.txt, PAMU property used for dynamic LIODN assignment
+
+ dev-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle to the particular hardware device that this
+ portal is connected to.
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ qman-portal@0 {
+ compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
+ reg = <0 0x4000>, <0x100000 0x1000>;
+ interrupts = <104 IRQ_TYPE_EDGE_FALLING 0 0>;
+ fsl,liodn = <1 2>;
+ fsl,qman-channel-id = <0>;
+
+ fman0 {
+ fsl,liodn = <0x21>;
+ dev-handle = <&fman0>;
+ };
+
+ fman1 {
+ fsl,liodn = <0xa1>;
+ dev-handle = <&fman1>;
+ };
+
+ crypto {
+ fsl,liodn = <0x41 0x66>;
+ dev-handle = <&crypto>;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/fsl,qman.yaml b/dts/upstream/Bindings/soc/fsl/fsl,qman.yaml
new file mode 100644
index 0000000..501f06e
--- /dev/null
+++ b/dts/upstream/Bindings/soc/fsl/fsl,qman.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/fsl/fsl,qman.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QorIQ DPAA Queue Manager
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description:
+ The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
+ supports queuing and QoS scheduling of frames to CPUs, network interfaces and
+ DPAA logic modules, maintains packet ordering within flows. Besides providing
+ flow-level queuing, is also responsible for congestion management functions such
+ as RED/WRED, congestion notifications and tail discards. This binding covers the
+ CCSR space programming model
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,qman
+ - items:
+ - enum:
+ - fsl,ls1043a-qman
+ - fsl,ls1046a-qman
+ - const: fsl,qman
+ reg:
+ items:
+ - description: |
+ Registers region within the CCSR address space
+
+ The QMan revision information is located in the QMAN_IP_REV_1/2
+ registers which are located at offsets 0xbf8 and 0xbfc
+
+ interrupts:
+ items:
+ - description: The error interrupt
+
+ fsl,qman-portals:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: ref fsl,qman-port.yaml
+
+ fsl,liodn:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ See pamu.txt, PAMU property used for static LIODN assignment
+
+ fsl,iommu-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ See pamu.txt, PAMU property used for dynamic LIODN assignment
+
+ clocks:
+ maxItems: 1
+ description:
+ Reference input clock. Its frequency is half of the platform clock
+
+ memory-region:
+ maxItems: 2
+ description:
+ List of phandles referencing the QMan private memory nodes (described
+ below). The qman-fqd node must be first followed by qman-pfdr node.
+ Only used on ARM Devices connected to a QMan instance via Direct Connect
+ Portals (DCP) must link to the respective QMan instance.
+
+ fsl,qman:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ List of phandle and DCP index pairs, to the QMan instance
+ to which this device is connected via the DCP
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ qman: qman@318000 {
+ compatible = "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 3>;
+ fsl,liodn = <0x16>;
+ fsl,qman-portals = <&qportals>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+ clocks = <&platform_pll 1>;
+ };
diff --git a/dts/upstream/Bindings/soc/fsl/qman-portals.txt b/dts/upstream/Bindings/soc/fsl/qman-portals.txt
deleted file mode 100644
index 5a34f3a..0000000
--- a/dts/upstream/Bindings/soc/fsl/qman-portals.txt
+++ /dev/null
@@ -1,134 +0,0 @@
-QorIQ DPAA Queue Manager Portals Device Tree Binding
-
-Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
-
-CONTENTS
-
- - QMan Portal
- - Example
-
-QMan Portal Node
-
-Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
-interaction by software running on processor cores, accelerators and network
-interfaces with the QMan
-
-PROPERTIES
-
-- compatible
- Usage: Required
- Value type: <stringlist>
- Definition: Must include "fsl,qman-portal-<hardware revision>"
- May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
-
-- reg
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Two regions. The first is the cache-enabled region of
- the portal. The second is the cache-inhibited region of
- the portal
-
-- interrupts
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Standard property
-
-- fsl,liodn
- Usage: See pamu.txt
- Value type: <prop-encoded-array>
- Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
- (FLIODN)
-
-- fsl,iommu-parent
- Usage: See pamu.txt
- Value type: <phandle>
- Definition: PAMU property used for dynamic LIODN assignment
-
- For additional details about the PAMU/LIODN binding(s) see pamu.txt
-
-- cell-index
- Usage: Required
- Value type: <u32>
- Definition: The hardware index of the channel. This can also be
- determined by dividing any of the channel's 8 work queue
- IDs by 8
-
-In addition to these properties the qman-portals should have sub-nodes to
-represent the HW devices/portals that are connected to the software portal
-described here
-
-The currently supported sub-nodes are:
- * fman0
- * fman1
- * pme
- * crypto
-
-These subnodes should have the following properties:
-
-- fsl,liodn
- Usage: See pamu.txt
- Value type: <prop-encoded-array>
- Definition: PAMU property used for static LIODN assignment
-
-- fsl,iommu-parent
- Usage: See pamu.txt
- Value type: <phandle>
- Definition: PAMU property used for dynamic LIODN assignment
-
-- dev-handle
- Usage: Required
- Value type: <phandle>
- Definition: The phandle to the particular hardware device that this
- portal is connected to.
-
-EXAMPLE
-
-The example below shows a (P4080) QMan portals container/bus node with two portals
-
- qman-portals@ff4200000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0 0xf 0xf4200000 0x200000>;
-
- qman-portal@0 {
- compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
- reg = <0 0x4000>, <0x100000 0x1000>;
- interrupts = <104 2 0 0>;
- fsl,liodn = <1 2>;
- fsl,qman-channel-id = <0>;
-
- fman0 {
- fsl,liodn = <0x21>;
- dev-handle = <&fman0>;
- };
- fman1 {
- fsl,liodn = <0xa1>;
- dev-handle = <&fman1>;
- };
- crypto {
- fsl,liodn = <0x41 0x66>;
- dev-handle = <&crypto>;
- };
- };
- qman-portal@4000 {
- compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
- reg = <0x4000 0x4000>, <0x101000 0x1000>;
- interrupts = <106 2 0 0>;
- fsl,liodn = <3 4>;
- cell-index = <1>;
-
- fman0 {
- fsl,liodn = <0x22>;
- dev-handle = <&fman0>;
- };
- fman1 {
- fsl,liodn = <0xa2>;
- dev-handle = <&fman1>;
- };
- crypto {
- fsl,liodn = <0x42 0x67>;
- dev-handle = <&crypto>;
- };
- };
- };
diff --git a/dts/upstream/Bindings/soc/fsl/qman.txt b/dts/upstream/Bindings/soc/fsl/qman.txt
deleted file mode 100644
index ee96afd..0000000
--- a/dts/upstream/Bindings/soc/fsl/qman.txt
+++ /dev/null
@@ -1,187 +0,0 @@
-QorIQ DPAA Queue Manager Device Tree Binding
-
-Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
-
-CONTENTS
-
- - QMan Node
- - QMan Private Memory Nodes
- - Example
-
-QMan Node
-
-The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
-supports queuing and QoS scheduling of frames to CPUs, network interfaces and
-DPAA logic modules, maintains packet ordering within flows. Besides providing
-flow-level queuing, is also responsible for congestion management functions such
-as RED/WRED, congestion notifications and tail discards. This binding covers the
-CCSR space programming model
-
-PROPERTIES
-
-- compatible
- Usage: Required
- Value type: <stringlist>
- Definition: Must include "fsl,qman"
- May include "fsl,<SoC>-qman"
-
-- reg
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Registers region within the CCSR address space
-
-The QMan revision information is located in the QMAN_IP_REV_1/2 registers which
-are located at offsets 0xbf8 and 0xbfc
-
-- interrupts
- Usage: Required
- Value type: <prop-encoded-array>
- Definition: Standard property. The error interrupt
-
-- fsl,qman-portals
- Usage: Required
- Value type: <phandle>
- Definition: Phandle to this QMan instance's portals
-
-- fsl,liodn
- Usage: See pamu.txt
- Value type: <prop-encoded-array>
- Definition: PAMU property used for static LIODN assignment
-
-- fsl,iommu-parent
- Usage: See pamu.txt
- Value type: <phandle>
- Definition: PAMU property used for dynamic LIODN assignment
-
- For additional details about the PAMU/LIODN binding(s) see pamu.txt
-
-- clocks
- Usage: See clock-bindings.txt and qoriq-clock.txt
- Value type: <prop-encoded-array>
- Definition: Reference input clock. Its frequency is half of the
- platform clock
-- memory-regions
- Usage: Required for ARM
- Value type: <phandle array>
- Definition: List of phandles referencing the QMan private memory
- nodes (described below). The qman-fqd node must be
- first followed by qman-pfdr node. Only used on ARM
-
-Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
-to the respective QMan instance
-
-- fsl,qman
- Usage: Required
- Value type: <prop-encoded-array>
- Description: List of phandle and DCP index pairs, to the QMan instance
- to which this device is connected via the DCP
-
-QMan Private Memory Nodes
-
-QMan requires two contiguous range of physical memory used for the backing store
-for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
-This memory is reserved/allocated as a node under the /reserved-memory node.
-
-For additional details about reserved memory regions see reserved-memory.txt
-
-The QMan FQD memory node must be named "qman-fqd"
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: PPC platforms: Must include "fsl,qman-fqd"
- ARM platforms: Must include "shared-dma-pool"
- as well as the "no-map" property
-
-The QMan PFDR memory node must be named "qman-pfdr"
-
-PROPERTIES
-
-- compatible
- Usage: required
- Value type: <stringlist>
- Definition: PPC platforms: Must include "fsl,qman-pfdr"
- ARM platforms: Must include "shared-dma-pool"
- as well as the "no-map" property
-
-The following constraints are relevant to the FQD and PFDR private memory:
- - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
- 1 GiB
- - The alignment must be a muliptle of the memory size
-
-The size of the FQD and PFDP must be chosen by observing the hardware features
-configured via the Reset Configuration Word (RCW) and that are relevant to a
-specific board (e.g. number of MAC(s) pinned-out, number of offline/host command
-FMan ports, etc.). The size configured in the DT must reflect the hardware
-capabilities and not the specific needs of an application
-
-For additional details about reserved memory regions see reserved-memory.txt
-
-EXAMPLE
-
-The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- qman_fqd: qman-fqd {
- compatible = "shared-dma-pool";
- size = <0 0x400000>;
- alignment = <0 0x400000>;
- no-map;
- };
- qman_pfdr: qman-pfdr {
- compatible = "shared-dma-pool";
- size = <0 0x2000000>;
- alignment = <0 0x2000000>;
- no-map;
- };
- };
-
-The example below shows a (P4080) QMan CCSR-space node
-
- qportals: qman-portals@ff4200000 {
- ...
- };
-
- clockgen: global-utilities@e1000 {
- ...
- sysclk: sysclk {
- ...
- };
- ...
- platform_pll: platform-pll@c00 {
- #clock-cells = <1>;
- reg = <0xc00 0x4>;
- compatible = "fsl,qoriq-platform-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "platform-pll", "platform-pll-div2";
- };
- ...
- };
-
- crypto@300000 {
- ...
- fsl,qman = <&qman, 2>;
- ...
- };
-
- qman: qman@318000 {
- compatible = "fsl,qman";
- reg = <0x318000 0x1000>;
- interrupts = <16 2 1 3>
- fsl,liodn = <0x16>;
- fsl,qman-portals = <&qportals>;
- memory-region = <&qman_fqd &qman_pfdr>;
- clocks = <&platform_pll 1>;
- };
-
- fman@400000 {
- ...
- fsl,qman = <&qman, 0>;
- ...
- };
diff --git a/dts/upstream/Bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml b/dts/upstream/Bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml
new file mode 100644
index 0000000..5c77c49
--- /dev/null
+++ b/dts/upstream/Bindings/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kirin 960 USB OTG Battery Charging Syscon
+
+maintainers:
+ - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi3660-usb3-otg-bc
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ usb-phy:
+ $ref: /schemas/phy/hisilicon,hi3660-usb3.yaml
+ description: USB Phy node
+
+required:
+ - compatible
+ - reg
+ - usb-phy
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@ff200000 {
+ compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd";
+ reg = <0xff200000 0x1000>;
+
+ usb-phy {
+ compatible = "hisilicon,hi3660-usb-phy";
+ #phy-cells = <0>;
+ hisilicon,pericrg-syscon = <&crg_ctrl>;
+ hisilicon,pctrl-syscon = <&pctrl>;
+ hisilicon,eye-diagram-param = <0x22466e4>;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/intel/intel,lgm-syscon.yaml b/dts/upstream/Bindings/soc/intel/intel,lgm-syscon.yaml
new file mode 100644
index 0000000..6951d55
--- /dev/null
+++ b/dts/upstream/Bindings/soc/intel/intel,lgm-syscon.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/intel/intel,lgm-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain(LGM) Syscon
+
+maintainers:
+ - Chuanhua Lei <lchuanhua@maxlinear.com>
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+properties:
+ compatible:
+ items:
+ - const: intel,lgm-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+patternProperties:
+ "^emmc-phy@[0-9a-f]+$":
+ $ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ chiptop@e0200000 {
+ compatible = "intel,lgm-syscon", "syscon";
+ reg = <0xe0200000 0x100>;
+ ranges = <0x0 0xe0200000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ emmc-phy@a8 {
+ compatible = "intel,lgm-emmc-phy";
+ reg = <0x00a8 0x10>;
+ clocks = <&emmc>;
+ #phy-cells = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml b/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml
index ba2014a..a10326a 100644
--- a/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/dts/upstream/Bindings/soc/mediatek/mediatek,mutex.yaml
@@ -33,6 +33,7 @@
- mediatek,mt8186-disp-mutex
- mediatek,mt8186-mdp3-mutex
- mediatek,mt8188-disp-mutex
+ - mediatek,mt8188-vpp-mutex
- mediatek,mt8192-disp-mutex
- mediatek,mt8195-disp-mutex
- mediatek,mt8195-vpp-mutex
diff --git a/dts/upstream/Bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml b/dts/upstream/Bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml
new file mode 100644
index 0000000..1f0b542
--- /dev/null
+++ b/dts/upstream/Bindings/soc/microchip/microchip,sparx5-cpu-syscon.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 CPU Syscon
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+properties:
+ compatible:
+ items:
+ - const: microchip,sparx5-cpu-syscon
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ mux-controller:
+ $ref: /schemas/mux/reg-mux.yaml#
+
+required:
+ - compatible
+ - reg
+ - mux-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x6 0x00000000 0xd0>;
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x88 0xf0>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/dts/upstream/Bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
new file mode 100644
index 0000000..f7e606d
--- /dev/null
+++ b/dts/upstream/Bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
@@ -0,0 +1,374 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ SoC system controller
+
+maintainers:
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+description:
+ OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
+ resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
+ instance. EyeQ6H hosts seven instances.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mobileye,eyeq5-olb
+ - mobileye,eyeq6l-olb
+ - mobileye,eyeq6h-acc-olb
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ - mobileye,eyeq6h-south-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ description:
+ First cell is domain and optional if compatible has a single reset domain.
+ Second cell is reset index inside that domain.
+ enum: [ 1, 2 ]
+
+ '#clock-cells':
+ description:
+ Cell is clock index. Optional if compatible has a single clock.
+ enum: [ 0, 1 ]
+
+ clocks:
+ maxItems: 1
+ description:
+ Input parent clock to all PLLs. Expected to be the main crystal.
+
+ clock-names:
+ const: ref
+
+patternProperties:
+ '-pins?$':
+ type: object
+ description: Pin muxing configuration.
+ $ref: /schemas/pinctrl/pinmux-node.yaml#
+ additionalProperties: false
+ properties:
+ pins: true
+ function:
+ enum: [gpio,
+ # Bank A
+ timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
+ spi1, refclk0,
+ # Bank B
+ timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ required:
+ - pins
+ - function
+ allOf:
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ pins:
+ items: # PA0 - PA28, PB0 - PB22
+ pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
+ - if:
+ properties:
+ function:
+ const: timer0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA0, PA1]
+ - if:
+ properties:
+ function:
+ const: timer1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA2, PA3]
+ - if:
+ properties:
+ function:
+ const: timer2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA4, PA5]
+ - if:
+ properties:
+ function:
+ const: timer5
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA6, PA7, PA8, PA9]
+ - if:
+ properties:
+ function:
+ const: uart0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA10, PA11]
+ - if:
+ properties:
+ function:
+ const: uart1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA12, PA13]
+ - if:
+ properties:
+ function:
+ const: can0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA14, PA15]
+ - if:
+ properties:
+ function:
+ const: can1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA16, PA17]
+ - if:
+ properties:
+ function:
+ const: spi0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA18, PA19, PA20, PA21, PA22]
+ - if:
+ properties:
+ function:
+ const: spi1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA23, PA24, PA25, PA26, PA27]
+ - if:
+ properties:
+ function:
+ const: refclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA28]
+ - if:
+ properties:
+ function:
+ const: timer3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB0, PB1]
+ - if:
+ properties:
+ function:
+ const: timer4
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB2, PB3]
+ - if:
+ properties:
+ function:
+ const: timer6
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB4, PB5, PB6, PB7]
+ - if:
+ properties:
+ function:
+ const: uart2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB8, PB9]
+ - if:
+ properties:
+ function:
+ const: can2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB10, PB11]
+ - if:
+ properties:
+ function:
+ const: spi2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB12, PB13, PB14, PB15, PB16]
+ - if:
+ properties:
+ function:
+ const: spi3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB17, PB18, PB19, PB20, PB21]
+ - if:
+ properties:
+ function:
+ const: mclk0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PB22]
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ # Compatibles exposing a single reset domain.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-acc-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 1
+ required:
+ - '#reset-cells'
+
+ # Compatibles exposing two reset domains.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq5-olb
+ - mobileye,eyeq6l-olb
+ then:
+ properties:
+ '#reset-cells':
+ const: 2
+ required:
+ - '#reset-cells'
+
+ # Compatibles not exposing resets.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-south-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ then:
+ properties:
+ '#reset-cells': false
+
+ # Compatibles exposing a single clock.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mobileye,eyeq6h-central-olb
+ - mobileye,eyeq6h-east-olb
+ - mobileye,eyeq6h-west-olb
+ - mobileye,eyeq6h-ddr0-olb
+ - mobileye,eyeq6h-ddr1-olb
+ then:
+ properties:
+ '#clock-cells':
+ const: 0
+ else:
+ properties:
+ '#clock-cells':
+ const: 1
+
+ # Only EyeQ5 has pinctrl in OLB.
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: mobileye,eyeq5-olb
+ then:
+ patternProperties:
+ '-pins?$': false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon";
+ reg = <0 0xe00000 0x0 0x400>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+ };
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@d2003000 {
+ compatible = "mobileye,eyeq6h-acc-olb", "syscon";
+ reg = <0x0 0xd2003000 0x0 0x1000>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
index b4478f4..7afdb60 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -31,6 +31,7 @@
- qcom,sc7280-aoss-qmp
- qcom,sc8180x-aoss-qmp
- qcom,sc8280xp-aoss-qmp
+ - qcom,sdx75-aoss-qmp
- qcom,sdm845-aoss-qmp
- qcom,sm6350-aoss-qmp
- qcom,sm8150-aoss-qmp
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,rpm-master-stats.yaml b/dts/upstream/Bindings/soc/qcom/qcom,rpm-master-stats.yaml
index 9410404..ad2dcc3 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,rpm-master-stats.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,rpm-master-stats.yaml
@@ -7,7 +7,7 @@
title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
maintainers:
- - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
description: |
The Qualcomm RPM (Resource Power Manager) architecture includes a concept
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml b/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml
index 5850052..141d666 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,smp2p.yaml
@@ -41,6 +41,7 @@
description:
Three entries specifying the outgoing ipc bit used for signaling the
remote end of the smp2p edge.
+ deprecated: true
qcom,local-pid:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -128,7 +129,7 @@
compatible = "qcom,smp2p";
qcom,smem = <431>, <451>;
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml b/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml
index db67cf0..4900215 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,smsm.yaml
@@ -33,6 +33,14 @@
specifier of the column in the subscription matrix representing the local
processor.
+ mboxes:
+ minItems: 1
+ maxItems: 5
+ description:
+ Reference to the mailbox representing the outgoing doorbell in APCS for
+ this client. Each entry represents the N:th remote processor by index
+ (0-indexed).
+
'#size-cells':
const: 0
@@ -47,6 +55,7 @@
description:
Three entries specifying the outgoing ipc bit used for signaling the N:th
remote processor.
+ deprecated: true
"@[0-9a-f]$":
type: object
@@ -98,15 +107,18 @@
- '#address-cells'
- '#size-cells'
-anyOf:
- - required:
- - qcom,ipc-1
+oneOf:
- required:
- - qcom,ipc-2
- - required:
- - qcom,ipc-3
- - required:
- - qcom,ipc-4
+ - mboxes
+ - anyOf:
+ - required:
+ - qcom,ipc-1
+ - required:
+ - qcom,ipc-2
+ - required:
+ - qcom,ipc-3
+ - required:
+ - qcom,ipc-4
additionalProperties: false
@@ -122,7 +134,7 @@
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <0>, <0>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
diff --git a/dts/upstream/Bindings/soc/rockchip/grf.yaml b/dts/upstream/Bindings/soc/rockchip/grf.yaml
index 79798c7..35b20e5 100644
--- a/dts/upstream/Bindings/soc/rockchip/grf.yaml
+++ b/dts/upstream/Bindings/soc/rockchip/grf.yaml
@@ -31,10 +31,16 @@
- rockchip,rk3588-pcie3-pipe-grf
- rockchip,rk3588-usb-grf
- rockchip,rk3588-usbdpphy-grf
- - rockchip,rk3588-vo-grf
+ - rockchip,rk3588-vo0-grf
+ - rockchip,rk3588-vo1-grf
- rockchip,rk3588-vop-grf
- rockchip,rv1108-usbgrf
- const: syscon
+ - items:
+ - const: rockchip,rk3588-vo-grf
+ - const: syscon
+ deprecated: true
+ description: Use rockchip,rk3588-vo{0,1}-grf instead.
- items:
- enum:
- rockchip,px30-grf
@@ -176,9 +182,10 @@
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
patternProperties:
- "phy@[0-9a-f]+$":
- description:
- Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+ "^phy@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/phy/rockchip,rk3399-emmc-phy.yaml#
+ unevaluatedProperties: false
- if:
properties:
@@ -261,6 +268,8 @@
contains:
enum:
- rockchip,rk3588-vo-grf
+ - rockchip,rk3588-vo0-grf
+ - rockchip,rk3588-vo1-grf
then:
required:
@@ -292,6 +301,15 @@
#phy-cells = <0>;
};
+ phy@f780 {
+ compatible = "rockchip,rk3399-emmc-phy";
+ reg = <0xf780 0x20>;
+ clocks = <&sdhci>;
+ clock-names = "emmcclk";
+ drive-impedance-ohm = <50>;
+ #phy-cells = <0>;
+ };
+
u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
diff --git a/dts/upstream/Bindings/soc/sprd/sprd,sc9863a-glbregs.yaml b/dts/upstream/Bindings/soc/sprd/sprd,sc9863a-glbregs.yaml
new file mode 100644
index 0000000..49add56
--- /dev/null
+++ b/dts/upstream/Bindings/soc/sprd/sprd,sc9863a-glbregs.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/sprd/sprd,sc9863a-glbregs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SC9863A Syscon
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ items:
+ - const: sprd,sc9863a-glbregs
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+patternProperties:
+ "@[0-9a-f]+$":
+ $ref: /schemas/clock/sprd,sc9863a-clk.yaml
+ description: Clock controllers
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@20e00000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
+ reg = <0x20e00000 0x4000>;
+ ranges = <0 0x20e00000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ apahb_gate: apahb-gate@0 {
+ compatible = "sprd,sc9863a-apahb-gate";
+ reg = <0x0 0x1020>;
+ #clock-cells = <1>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/soc/sti/st,sti-syscon.yaml b/dts/upstream/Bindings/soc/sti/st,sti-syscon.yaml
index 5f97d9f..fc933d7 100644
--- a/dts/upstream/Bindings/soc/sti/st,sti-syscon.yaml
+++ b/dts/upstream/Bindings/soc/sti/st,sti-syscon.yaml
@@ -30,6 +30,15 @@
reg:
maxItems: 1
+ sti-sasg-codec:
+ description: STi internal audio codec
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: st,stih407-sas-codec
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/soc/ti/sci-pm-domain.yaml b/dts/upstream/Bindings/soc/ti/sci-pm-domain.yaml
index a750035..b6da720 100644
--- a/dts/upstream/Bindings/soc/ti/sci-pm-domain.yaml
+++ b/dts/upstream/Bindings/soc/ti/sci-pm-domain.yaml
@@ -40,7 +40,7 @@
TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts.
Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions.
- Please see http://processors.wiki.ti.com/index.php/TISCI for
+ Please see https://software-dl.ti.com/tisci/esd/latest/index.html for
protocol documentation for the values to be used for different devices.
additionalProperties: false
diff --git a/dts/upstream/Bindings/soc/ti/ti,am654-serdes-ctrl.yaml b/dts/upstream/Bindings/soc/ti/ti,am654-serdes-ctrl.yaml
new file mode 100644
index 0000000..a10a3b8
--- /dev/null
+++ b/dts/upstream/Bindings/soc/ti/ti,am654-serdes-ctrl.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments AM654 Serdes Control Syscon
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+properties:
+ compatible:
+ items:
+ - const: ti,am654-serdes-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ mux-controller:
+ $ref: /schemas/mux/reg-mux.yaml#
+
+required:
+ - compatible
+ - reg
+ - mux-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ clock@4080 {
+ compatible = "ti,am654-serdes-ctrl", "syscon";
+ reg = <0x4080 0x4>;
+
+ mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x3>; /* lane select */
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/ti/ti,j721e-system-controller.yaml b/dts/upstream/Bindings/soc/ti/ti,j721e-system-controller.yaml
new file mode 100644
index 0000000..378e9cc
--- /dev/null
+++ b/dts/upstream/Bindings/soc/ti/ti,j721e-system-controller.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI J721e System Controller Registers R/W
+
+description: |
+ This represents the Control Module registers (CTRL_MMR0) on the SoC.
+ System controller node represents a register region containing a set
+ of miscellaneous registers. The registers are not cohesive enough to
+ represent as any specific type of device. The typical use-case is
+ for some other node's driver, or platform-specific code, to acquire
+ a reference to the syscon node (e.g. by phandle, node path, or
+ search using a specific compatible value), interrogate the node (or
+ associated OS driver) to determine the location of the registers,
+ and access the registers directly.
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@kernel.org>
+ - Roger Quadros <rogerq@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ti,j7200-system-controller
+ - ti,j721e-system-controller
+ - ti,j721s2-system-controller
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ # Optional children
+ "^mux-controller@[0-9a-f]+$":
+ type: object
+ description:
+ This is the SERDES lane control mux.
+
+ "^clock-controller@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
+ description:
+ Clock provider for TI EHRPWM nodes.
+
+ "phy@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
+ description:
+ The phy node corresponding to the ethernet MAC.
+
+ "^chipid@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
+ description:
+ The node corresponding to SoC chip identification.
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ scm_conf: scm-conf@100000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00100000 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x50>;
+
+ #mux-control-cells = <1>;
+ mux-reg-masks =
+ <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
+ };
+
+ clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/sound/ak4104.txt b/dts/upstream/Bindings/sound/ak4104.txt
deleted file mode 100644
index ae5f7f0..0000000
--- a/dts/upstream/Bindings/sound/ak4104.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-AK4104 S/PDIF transmitter
-
-This device supports SPI mode only.
-
-Required properties:
-
- - compatible : "asahi-kasei,ak4104"
-
- - reg : The chip select number on the SPI bus
-
- - vdd-supply : A regulator node, providing 2.7V - 3.6V
-
-Optional properties:
-
- - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
- deasserted before communication to the device starts.
-
-Example:
-
-spdif: ak4104@0 {
- compatible = "asahi-kasei,ak4104";
- reg = <0>;
- spi-max-frequency = <5000000>;
- vdd-supply = <&vdd_3v3_reg>;
-};
diff --git a/dts/upstream/Bindings/sound/ak4375.yaml b/dts/upstream/Bindings/sound/ak4375.yaml
deleted file mode 100644
index 587598e..0000000
--- a/dts/upstream/Bindings/sound/ak4375.yaml
+++ /dev/null
@@ -1,60 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/ak4375.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: AK4375 DAC and headphones amplifier
-
-maintainers:
- - Vincent Knecht <vincent.knecht@mailoo.org>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- const: asahi-kasei,ak4375
-
- reg:
- maxItems: 1
-
- '#sound-dai-cells':
- const: 0
-
- avdd-supply:
- description: regulator phandle for the AVDD power supply.
-
- tvdd-supply:
- description: regulator phandle for the TVDD power supply.
-
- pdn-gpios:
- description: optional GPIO to set the PDN pin.
-
-required:
- - compatible
- - reg
- - '#sound-dai-cells'
- - avdd-supply
- - tvdd-supply
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- headphones: audio-codec@10 {
- compatible = "asahi-kasei,ak4375";
- reg = <0x10>;
- avdd-supply = <®_headphones_avdd>;
- tvdd-supply = <&pm8916_l6>;
- pdn-gpios = <&msmgpio 114 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&headphones_pdn_default>;
- #sound-dai-cells = <0>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/ak4554.txt b/dts/upstream/Bindings/sound/ak4554.txt
deleted file mode 100644
index 934fa02..0000000
--- a/dts/upstream/Bindings/sound/ak4554.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-AK4554 ADC/DAC
-
-Required properties:
-
- - compatible : "asahi-kasei,ak4554"
-
-Example:
-
-ak4554-adc-dac {
- compatible = "asahi-kasei,ak4554";
-};
diff --git a/dts/upstream/Bindings/sound/ak4613.yaml b/dts/upstream/Bindings/sound/ak4613.yaml
deleted file mode 100644
index 75e1341..0000000
--- a/dts/upstream/Bindings/sound/ak4613.yaml
+++ /dev/null
@@ -1,59 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/ak4613.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: AK4613 I2C transmitter
-
-maintainers:
- - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- const: asahi-kasei,ak4613
-
- reg:
- maxItems: 1
-
- clocks:
- maxItems: 1
-
- "#sound-dai-cells":
- const: 0
-
- ports:
- $ref: audio-graph-port.yaml#/definitions/ports
-
- port:
- $ref: audio-graph-port.yaml#
- unevaluatedProperties: false
-
-patternProperties:
- "^asahi-kasei,in[1-2]-single-end$":
- description: Input Pin 1 - 2.
- $ref: /schemas/types.yaml#/definitions/flag
-
- "^asahi-kasei,out[1-6]-single-end$":
- description: Output Pin 1 - 6.
- $ref: /schemas/types.yaml#/definitions/flag
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- ak4613: codec@10 {
- compatible = "asahi-kasei,ak4613";
- reg = <0x10>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/ak4642.yaml b/dts/upstream/Bindings/sound/ak4642.yaml
deleted file mode 100644
index 437fe5d..0000000
--- a/dts/upstream/Bindings/sound/ak4642.yaml
+++ /dev/null
@@ -1,59 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/ak4642.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: AK4642 I2C transmitter
-
-maintainers:
- - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- enum:
- - asahi-kasei,ak4642
- - asahi-kasei,ak4643
- - asahi-kasei,ak4648
-
- reg:
- maxItems: 1
-
- "#clock-cells":
- const: 0
- "#sound-dai-cells":
- const: 0
-
- clocks:
- maxItems: 1
-
- clock-frequency:
- description: common clock binding; frequency of MCKO
-
- clock-output-names:
- description: common clock name
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- ak4643: codec@12 {
- compatible = "asahi-kasei,ak4643";
- #sound-dai-cells = <0>;
- reg = <0x12>;
- #clock-cells = <0>;
- clocks = <&audio_clock>;
- clock-frequency = <12288000>;
- clock-output-names = "ak4643_mcko";
- };
- };
diff --git a/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.txt b/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.txt
deleted file mode 100644
index 4e8cd7e..0000000
--- a/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Amlogic HDMI Tx control glue
-
-Required properties:
-- compatible: "amlogic,g12a-tohdmitx" or
- "amlogic,sm1-tohdmitx"
-- reg: physical base address of the controller and length of memory
- mapped region.
-- #sound-dai-cells: should be 1.
-- resets: phandle to the dedicated reset line of the hdmitx glue.
-
-Example on the S905X2 SoC:
-
-tohdmitx: audio-controller@744 {
- compatible = "amlogic,g12a-tohdmitx";
- reg = <0x0 0x744 0x0 0x4>;
- #sound-dai-cells = <1>;
- resets = <&clkc_audio AUD_RESET_TOHDMITX>;
-};
-
-Example of an 'amlogic,axg-sound-card':
-
-sound {
- compatible = "amlogic,axg-sound-card";
-
-[...]
-
- dai-link-x {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
-
- codec-1 {
- sound-dai = <&external_dac>;
- };
- };
-
- dai-link-y {
- sound-dai = <&tdmif_c>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
- };
- };
-
- dai-link-z {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
-};
diff --git a/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.yaml b/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.yaml
new file mode 100644
index 0000000..b4b7847
--- /dev/null
+++ b/dts/upstream/Bindings/sound/amlogic,g12a-tohdmitx.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/amlogic,g12a-tohdmitx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic G12a HDMI TX Control Glue
+
+maintainers:
+ - Jerome Brunet <jbrunet@baylibre.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ $nodename:
+ pattern: "^audio-controller@.*"
+
+ compatible:
+ oneOf:
+ - items:
+ - const: amlogic,g12a-tohdmitx
+ - items:
+ - enum:
+ - amlogic,sm1-tohdmitx
+ - const: amlogic,g12a-tohdmitx
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - resets
+ - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
+
+ tohdmitx: audio-controller@744 {
+ compatible = "amlogic,g12a-tohdmitx";
+ reg = <0x744 0x4>;
+ resets = <&clkc_audio AUD_RESET_TOHDMITX>;
+ #sound-dai-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/sound/amlogic,gx-sound-card.yaml b/dts/upstream/Bindings/sound/amlogic,gx-sound-card.yaml
index d4277d3..0ecdaf7 100644
--- a/dts/upstream/Bindings/sound/amlogic,gx-sound-card.yaml
+++ b/dts/upstream/Bindings/sound/amlogic,gx-sound-card.yaml
@@ -23,7 +23,6 @@
audio-widgets:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
- minItems: 2
description: |-
A list off component DAPM widget. Each entry is a pair of strings,
the first being the widget type, the second being the widget name
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4104.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4104.yaml
new file mode 100644
index 0000000..86f6061
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4104.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4104.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4104 S/PDIF transmitter
+
+allOf:
+ - $ref: dai-common.yaml#
+
+maintainers:
+ - Daniel Mack <github@zonque.org>
+ - Xiaxi Shen <shenxiaxi26@gmail.com>
+
+properties:
+ compatible:
+ const: asahi-kasei,ak4104
+
+ reg:
+ description: Chip select number on the SPI bus
+ maxItems: 1
+
+ vdd-supply:
+ description: A regulator node providing between 2.7V and 3.6V.
+
+ reset-gpios:
+ maxItems: 1
+ description: Optional GPIO spec for the reset pin, deasserted
+ before communication starts.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@0 {
+ compatible = "asahi-kasei,ak4104";
+ reg = <0>;
+ vdd-supply = <&vdd_3v3_reg>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4375.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4375.yaml
new file mode 100644
index 0000000..bc07fcb
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4375.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4375.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4375 DAC and headphones amplifier
+
+maintainers:
+ - Vincent Knecht <vincent.knecht@mailoo.org>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: asahi-kasei,ak4375
+
+ reg:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 0
+
+ avdd-supply:
+ description: regulator phandle for the AVDD power supply.
+
+ tvdd-supply:
+ description: regulator phandle for the TVDD power supply.
+
+ pdn-gpios:
+ description: optional GPIO to set the PDN pin.
+
+required:
+ - compatible
+ - reg
+ - '#sound-dai-cells'
+ - avdd-supply
+ - tvdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ headphones: audio-codec@10 {
+ compatible = "asahi-kasei,ak4375";
+ reg = <0x10>;
+ avdd-supply = <®_headphones_avdd>;
+ tvdd-supply = <&pm8916_l6>;
+ pdn-gpios = <&msmgpio 114 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&headphones_pdn_default>;
+ #sound-dai-cells = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4554.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4554.yaml
new file mode 100644
index 0000000..c77d85d
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4554.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4554.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4554 sound codec
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ - Liam Girdwood <lgirdwood@gmail.com>
+ - Mark Brown <broonie@kernel.org>
+
+properties:
+ compatible:
+ const: asahi-kasei,ak4554
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ codec {
+ compatible = "asahi-kasei,ak4554";
+ };
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4613.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4613.yaml
new file mode 100644
index 0000000..b49a6cf
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4613.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4613.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4613 I2C transmitter
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: asahi-kasei,ak4613
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ ports:
+ $ref: audio-graph-port.yaml#/definitions/ports
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+patternProperties:
+ "^asahi-kasei,in[1-2]-single-end$":
+ description: Input Pin 1 - 2.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ "^asahi-kasei,out[1-6]-single-end$":
+ description: Output Pin 1 - 6.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ reg = <0x10>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4619.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4619.yaml
new file mode 100644
index 0000000..d412531
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4619.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4619.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4619 I2C transmitter
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ - Khanh Le <khanh.le.xr@renesas.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: asahi-kasei,ak4619
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mclk
+
+ "#sound-dai-cells":
+ const: 0
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@10 {
+ compatible = "asahi-kasei,ak4619";
+ reg = <0x10>;
+
+ clocks = <&rcar_sound>;
+ clock-names = "mclk";
+
+ #sound-dai-cells = <0>;
+ port {
+ ak4619_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/asahi-kasei,ak4642.yaml b/dts/upstream/Bindings/sound/asahi-kasei,ak4642.yaml
new file mode 100644
index 0000000..fc03f03
--- /dev/null
+++ b/dts/upstream/Bindings/sound/asahi-kasei,ak4642.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/asahi-kasei,ak4642.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AK4642 I2C transmitter
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - asahi-kasei,ak4642
+ - asahi-kasei,ak4643
+ - asahi-kasei,ak4648
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+ "#sound-dai-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: common clock binding; frequency of MCKO
+
+ clock-output-names:
+ description: common clock name
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ak4643: codec@12 {
+ compatible = "asahi-kasei,ak4643";
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ #clock-cells = <0>;
+ clocks = <&audio_clock>;
+ clock-frequency = <12288000>;
+ clock-output-names = "ak4643_mcko";
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/audio-graph-card2.yaml b/dts/upstream/Bindings/sound/audio-graph-card2.yaml
index d3ce4de..f943f90 100644
--- a/dts/upstream/Bindings/sound/audio-graph-card2.yaml
+++ b/dts/upstream/Bindings/sound/audio-graph-card2.yaml
@@ -23,6 +23,11 @@
Each entry is a pair of strings, the first being the
connection's sink, the second being the connection's source.
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ aux-devs:
+ description: |
+ List of phandles pointing to auxiliary devices, such
+ as amplifiers, to be added to the sound card.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
multi:
type: object
description: Multi-CPU/Codec node
diff --git a/dts/upstream/Bindings/sound/audio-graph-port.yaml b/dts/upstream/Bindings/sound/audio-graph-port.yaml
index 28b27e7..d1cbfc5 100644
--- a/dts/upstream/Bindings/sound/audio-graph-port.yaml
+++ b/dts/upstream/Bindings/sound/audio-graph-port.yaml
@@ -25,6 +25,15 @@
capture-only:
description: port connection used only for capture
$ref: /schemas/types.yaml#/definitions/flag
+ link-trigger-order:
+ description: trigger order for both start/stop
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ link-trigger-order-start:
+ description: trigger order for start
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ link-trigger-order-stop:
+ description: trigger order for stop
+ $ref: /schemas/types.yaml#/definitions/uint32-array
endpoint-base:
allOf:
diff --git a/dts/upstream/Bindings/sound/cirrus,cs4270.yaml b/dts/upstream/Bindings/sound/cirrus,cs4270.yaml
new file mode 100644
index 0000000..336e117
--- /dev/null
+++ b/dts/upstream/Bindings/sound/cirrus,cs4270.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cirrus,cs4270.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic CS4270 audio CODEC
+
+maintainers:
+ - patches@opensource.cirrus.com
+
+description:
+ The CS4270 is a stereo audio codec. The driver for this device currently only
+ supports I2C.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: cirrus,cs4270
+
+ reg:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 0
+
+ reset-gpios:
+ description:
+ This pin will be deasserted before communication to the codec starts.
+ maxItems: 1
+
+ va-supply:
+ description: Analog power supply.
+
+ vd-supply:
+ description: Digital power supply.
+
+ vlc-supply:
+ description: Serial Control Port power supply.
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@48 {
+ compatible = "cirrus,cs4270";
+ reg = <0x48>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml b/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml
new file mode 100644
index 0000000..725b47e
--- /dev/null
+++ b/dts/upstream/Bindings/sound/cirrus,cs42xx8.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cirrus,cs42xx8.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic CS42448/CS42888 audio CODEC
+
+maintainers:
+ - patches@opensource.cirrus.com
+
+properties:
+ compatible:
+ enum:
+ - cirrus,cs42448
+ - cirrus,cs42888
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ const: mclk
+
+ VA-supply:
+ description: Analog power supply.
+
+ VD-supply:
+ description: Digital power supply.
+
+ VLC-supply:
+ description: Control port power supply
+
+ VLS-supply:
+ description: Serial port interface power supply.
+
+ reset-gpios:
+ description: This pin is connected to the chip's RESET pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: cirrus,cs42888
+then:
+ required:
+ - VA-supply
+ - VD-supply
+ - VLC-supply
+ - VLS-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@48 {
+ compatible = "cirrus,cs42888";
+ reg = <0x48>;
+ clocks = <&codec_mclk 0>;
+ clock-names = "mclk";
+ VA-supply = <®_audio>;
+ VD-supply = <®_audio>;
+ VLS-supply = <®_audio>;
+ VLC-supply = <®_audio>;
+ reset-gpios = <&gpio 1>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/cirrus,cs530x.yaml b/dts/upstream/Bindings/sound/cirrus,cs530x.yaml
new file mode 100644
index 0000000..9582eb8
--- /dev/null
+++ b/dts/upstream/Bindings/sound/cirrus,cs530x.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cirrus,cs530x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cirrus Logic cs530x family of audio ADCs
+
+maintainers:
+ - Paul Handrigan <paulha@opensource.cirrus.com>
+ - patches@opensource.cirrus.com
+
+description:
+ The CS530X devices are a family of high performance audio ADCs.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - cirrus,cs5302
+ - cirrus,cs5304
+ - cirrus,cs5308
+
+ reg:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vdd-a-supply:
+ description: Analog power supply
+
+ vdd-io-supply:
+ description: Digital IO power supply
+
+ cirrus,in-hiz-pin12:
+ description:
+ Sets input channels one and two to high impedance.
+ type: boolean
+
+ cirrus,in-hiz-pin34:
+ description:
+ Sets input channels three and four to high impedance.
+ type: boolean
+
+ cirrus,in-hiz-pin56:
+ description:
+ Sets input channels five and six to high impedance.
+ type: boolean
+
+ cirrus,in-hiz-pin78:
+ description:
+ Sets input channels seven and eight to high impedance.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cs5304: adc@48 {
+ compatible = "cirrus,cs5304";
+ reg = <0x48>;
+ #sound-dai-cells = <1>;
+ reset-gpios = <&gpio 110 GPIO_ACTIVE_LOW>;
+ vdd-a-supply = <&vreg>;
+ vdd-io-supply = <&vreg>;
+ cirrus,in-hiz-pin34;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/cs4270.txt b/dts/upstream/Bindings/sound/cs4270.txt
deleted file mode 100644
index c33770e..0000000
--- a/dts/upstream/Bindings/sound/cs4270.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-CS4270 audio CODEC
-
-The driver for this device currently only supports I2C.
-
-Required properties:
-
- - compatible : "cirrus,cs4270"
-
- - reg : the I2C address of the device for I2C
-
-Optional properties:
-
- - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
- deasserted before communication to the codec starts.
-
-Example:
-
-codec: cs4270@48 {
- compatible = "cirrus,cs4270";
- reg = <0x48>;
-};
diff --git a/dts/upstream/Bindings/sound/cs42xx8.txt b/dts/upstream/Bindings/sound/cs42xx8.txt
deleted file mode 100644
index bbfe393..0000000
--- a/dts/upstream/Bindings/sound/cs42xx8.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-CS42448/CS42888 audio CODEC
-
-Required properties:
-
- - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888"
-
- - reg : the I2C address of the device for I2C
-
- - clocks : a list of phandles + clock-specifiers, one for each entry in
- clock-names
-
- - clock-names : must contain "mclk"
-
- - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device,
- as covered in Documentation/devicetree/bindings/regulator/regulator.txt
-
-Optional properties:
-
- - reset-gpios : a GPIO spec to define which pin is connected to the chip's
- !RESET pin
-
-Example:
-
-cs42888: codec@48 {
- compatible = "cirrus,cs42888";
- reg = <0x48>;
- clocks = <&codec_mclk 0>;
- clock-names = "mclk";
- VA-supply = <®_audio>;
- VD-supply = <®_audio>;
- VLS-supply = <®_audio>;
- VLC-supply = <®_audio>;
- reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>;
-};
diff --git a/dts/upstream/Bindings/sound/everest,es7134.txt b/dts/upstream/Bindings/sound/everest,es7134.txt
deleted file mode 100644
index 0916660..0000000
--- a/dts/upstream/Bindings/sound/everest,es7134.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-ES7134 i2s DA converter
-
-Required properties:
-- compatible : "everest,es7134" or
- "everest,es7144" or
- "everest,es7154"
-- VDD-supply : regulator phandle for the VDD supply
-- PVDD-supply: regulator phandle for the PVDD supply for the es7154
-
-Example:
-
-i2s_codec: external-codec {
- compatible = "everest,es7134";
- VDD-supply = <&vcc_5v>;
-};
diff --git a/dts/upstream/Bindings/sound/everest,es71x4.yaml b/dts/upstream/Bindings/sound/everest,es71x4.yaml
new file mode 100644
index 0000000..fd1b328
--- /dev/null
+++ b/dts/upstream/Bindings/sound/everest,es71x4.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es71x4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES7134/7144/7154 2 channels I2S analog to digital converter
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - everest,es7134
+ - everest,es7144
+ - everest,es7154
+
+ VDD-supply: true
+ PVDD-supply: true
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - VDD-supply
+
+allOf:
+ - $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - everest,es7134
+ - everest,es7144
+ then:
+ properties:
+ PVDD-supply: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - everest,es7154
+ then:
+ required:
+ - PVDD-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ codec {
+ compatible = "everest,es7134";
+ #sound-dai-cells = <0>;
+ VDD-supply = <&vdd_supply>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/everest,es7241.txt b/dts/upstream/Bindings/sound/everest,es7241.txt
deleted file mode 100644
index 28f82cf..0000000
--- a/dts/upstream/Bindings/sound/everest,es7241.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-ES7241 i2s AD converter
-
-Required properties:
-- compatible : "everest,es7241"
-- VDDP-supply: regulator phandle for the VDDA supply
-- VDDA-supply: regulator phandle for the VDDP supply
-- VDDD-supply: regulator phandle for the VDDD supply
-
-Optional properties:
-- reset-gpios: gpio connected to the reset pin
-- m0-gpios : gpio connected to the m0 pin
-- m1-gpios : gpio connected to the m1 pin
-- everest,sdout-pull-down:
- Format used by the serial interface is controlled by pulling
- the sdout. If the sdout is pulled down, leftj format is used.
- If this property is not provided, sdout is assumed to pulled
- up and i2s format is used
-
-Example:
-
-linein: audio-codec@2 {
- #sound-dai-cells = <0>;
- compatible = "everest,es7241";
- VDDA-supply = <&vcc_3v3>;
- VDDP-supply = <&vcc_3v3>;
- VDDD-supply = <&vcc_3v3>;
- reset-gpios = <&gpio GPIOH_42>;
-};
diff --git a/dts/upstream/Bindings/sound/everest,es7241.yaml b/dts/upstream/Bindings/sound/everest,es7241.yaml
new file mode 100644
index 0000000..f179af7
--- /dev/null
+++ b/dts/upstream/Bindings/sound/everest,es7241.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es7241.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES7241 2 channels I2S analog to digital converter
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - everest,es7241
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to the reset pin
+
+ m0-gpios:
+ maxItems: 1
+ description: GPIO connected to the m0 pin
+
+ m1-gpios:
+ maxItems: 1
+ description: GPIO connected to the m0 pin
+
+ everest,sdout-pull-down:
+ type: boolean
+ description:
+ Format used by the serial interface is controlled by pulling
+ the sdout. If the sdout is pulled down, leftj format is used.
+ If this property is not provided, sdout is assumed to pulled
+ up and i2s format is used
+
+ VDDP-supply: true
+ VDDA-supply: true
+ VDDD-supply: true
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - VDDP-supply
+ - VDDA-supply
+ - VDDD-supply
+
+allOf:
+ - $ref: dai-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ codec {
+ compatible = "everest,es7241";
+ #sound-dai-cells = <0>;
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ VDDP-supply = <&vddp_supply>;
+ VDDA-supply = <&vdda_supply>;
+ VDDD-supply = <&vddd_supply>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/everest,es8316.yaml b/dts/upstream/Bindings/sound/everest,es8316.yaml
index b6079b3..214f135 100644
--- a/dts/upstream/Bindings/sound/everest,es8316.yaml
+++ b/dts/upstream/Bindings/sound/everest,es8316.yaml
@@ -4,18 +4,21 @@
$id: http://devicetree.org/schemas/sound/everest,es8316.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Everest ES8316 audio CODEC
+title: Everest ES8311 and ES8316 audio CODECs
maintainers:
- Daniel Drake <drake@endlessm.com>
- Katsuhiro Suzuki <katsuhiro@katsuster.net>
+ - Matteo Martelli <matteomartelli3@gmail.com>
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
- const: everest,es8316
+ enum:
+ - everest,es8311
+ - everest,es8316
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/sound/fsl,imx-audio-spdif.yaml b/dts/upstream/Bindings/sound/fsl,imx-audio-spdif.yaml
deleted file mode 100644
index 5fc543d..0000000
--- a/dts/upstream/Bindings/sound/fsl,imx-audio-spdif.yaml
+++ /dev/null
@@ -1,66 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/fsl,imx-audio-spdif.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale i.MX audio complex with S/PDIF transceiver
-
-maintainers:
- - Shengjiu Wang <shengjiu.wang@nxp.com>
-
-properties:
- compatible:
- oneOf:
- - items:
- - enum:
- - fsl,imx-sabreauto-spdif
- - fsl,imx6sx-sdb-spdif
- - const: fsl,imx-audio-spdif
- - enum:
- - fsl,imx-audio-spdif
-
- model:
- $ref: /schemas/types.yaml#/definitions/string
- description: User specified audio sound card name
-
- spdif-controller:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: The phandle of the i.MX S/PDIF controller
-
- spdif-out:
- type: boolean
- description:
- If present, the transmitting function of S/PDIF will be enabled,
- indicating there's a physical S/PDIF out connector or jack on the
- board or it's connecting to some other IP block, such as an HDMI
- encoder or display-controller.
-
- spdif-in:
- type: boolean
- description:
- If present, the receiving function of S/PDIF will be enabled,
- indicating there is a physical S/PDIF in connector/jack on the board.
-
-required:
- - compatible
- - model
- - spdif-controller
-
-anyOf:
- - required:
- - spdif-in
- - required:
- - spdif-out
-
-additionalProperties: false
-
-examples:
- - |
- sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
- spdif-controller = <&spdif>;
- spdif-out;
- spdif-in;
- };
diff --git a/dts/upstream/Bindings/sound/fsl,mqs.yaml b/dts/upstream/Bindings/sound/fsl,mqs.yaml
index 8b33353..030ccc1 100644
--- a/dts/upstream/Bindings/sound/fsl,mqs.yaml
+++ b/dts/upstream/Bindings/sound/fsl,mqs.yaml
@@ -23,6 +23,8 @@
- fsl,imx8qm-mqs
- fsl,imx8qxp-mqs
- fsl,imx93-mqs
+ - fsl,imx95-aonmix-mqs
+ - fsl,imx95-netcmix-mqs
clocks:
minItems: 1
diff --git a/dts/upstream/Bindings/sound/fsl,qmc-audio.yaml b/dts/upstream/Bindings/sound/fsl,qmc-audio.yaml
index b522ed7..a23e491 100644
--- a/dts/upstream/Bindings/sound/fsl,qmc-audio.yaml
+++ b/dts/upstream/Bindings/sound/fsl,qmc-audio.yaml
@@ -12,7 +12,9 @@
description: |
The QMC audio is an ASoC component which uses QMC (QUICC Multichannel
Controller) channels to transfer the audio data.
- It provides as many DAI as the number of QMC channel used.
+ It provides several DAIs. For each DAI, the DAI is working in interleaved mode
+ if only one QMC channel is used by the DAI or it is working in non-interleaved
+ mode if several QMC channels are used by the DAI.
allOf:
- $ref: dai-common.yaml#
@@ -45,12 +47,19 @@
fsl,qmc-chan:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - items:
- - description: phandle to QMC node
- - description: Channel number
+ items:
+ - description: phandle to QMC node
+ - description: Channel number
+ minItems: 1
description:
- Should be a phandle/number pair. The phandle to QMC node and the QMC
- channel to use for this DAI.
+ Should be a phandle/number pair list. The list of phandle to QMC node
+ and the QMC channel pair to use for this DAI.
+ If only one phandle/number pair is provided, this DAI works in
+ interleaved mode, i.e. audio channels for this DAI are interleaved in
+ the QMC channel. If more than one pair is provided, this DAI works
+ in non-interleave mode. In that case the first audio channel uses the
+ the first QMC channel, the second audio channel uses the second QMC
+ channel, etc...
required:
- reg
@@ -79,6 +88,11 @@
reg = <17>;
fsl,qmc-chan = <&qmc 17>;
};
+ dai@18 {
+ reg = <18>;
+ /* Non-interleaved mode */
+ fsl,qmc-chan = <&qmc 18>, <&qmc 19>;
+ };
};
sound {
@@ -115,4 +129,19 @@
dai-tdm-slot-rx-mask = <0 0 1 0 1 0 1 0 1>;
};
};
+ simple-audio-card,dai-link@2 {
+ reg = <2>;
+ format = "dsp_b";
+ cpu {
+ sound-dai = <&audio_controller 18>;
+ };
+ codec {
+ sound-dai = <&codec3>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <8>;
+ /* TS 9, 10 */
+ dai-tdm-slot-tx-mask = <0 0 0 0 0 0 0 0 0 1 1>;
+ dai-tdm-slot-rx-mask = <0 0 0 0 0 0 0 0 0 1 1>;
+ };
+ };
};
diff --git a/dts/upstream/Bindings/sound/fsl,rpmsg.yaml b/dts/upstream/Bindings/sound/fsl,rpmsg.yaml
index 188f38b..3d5d435 100644
--- a/dts/upstream/Bindings/sound/fsl,rpmsg.yaml
+++ b/dts/upstream/Bindings/sound/fsl,rpmsg.yaml
@@ -29,6 +29,7 @@
- fsl,imx8mp-rpmsg-audio
- fsl,imx8ulp-rpmsg-audio
- fsl,imx93-rpmsg-audio
+ - fsl,imx95-rpmsg-audio
clocks:
items:
diff --git a/dts/upstream/Bindings/sound/fsl,sgtl5000.yaml b/dts/upstream/Bindings/sound/fsl,sgtl5000.yaml
new file mode 100644
index 0000000..c6ab1ca
--- /dev/null
+++ b/dts/upstream/Bindings/sound/fsl,sgtl5000.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,sgtl5000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SGTL5000 Stereo Codec
+
+maintainers:
+ - Fabio Estevam <festevam@gmail.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: fsl,sgtl5000
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+
+ clocks:
+ items:
+ - description: the clock provider of SYS_MCLK
+
+ VDDA-supply:
+ description: the regulator provider of VDDA
+
+ VDDIO-supply:
+ description: the regulator provider of VDDIO
+
+ VDDD-supply:
+ description: the regulator provider of VDDD
+
+ micbias-resistor-k-ohms:
+ description: The bias resistor to be used in kOhms. The resistor can take
+ values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
+ mentioned or if the value is unknown, then micbias resistor is set to
+ 4k.
+ enum: [ 0, 2, 4, 8 ]
+
+ micbias-voltage-m-volts:
+ description: The bias voltage to be used in mVolts. The voltage can take
+ values from 1.25V to 3V by 250mV steps. If this node is not mentioned
+ or the value is unknown, then the value is set to 1.25V.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 ]
+
+ lrclk-strength:
+ description: |
+ The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
+ table below:
+
+ VDDIO 1.8V 2.5V 3.3V
+ 0 = Disable
+ 1 = 1.66 mA 2.87 mA 4.02 mA
+ 2 = 3.33 mA 5.74 mA 8.03 mA
+ 3 = 4.99 mA 8.61 mA 12.05 mA
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3 ]
+
+ sclk-strength:
+ description: |
+ The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
+ table below:
+
+ VDDIO 1.8V 2.5V 3.3V
+ 0 = Disable
+ 1 = 1.66 mA 2.87 mA 4.02 mA
+ 2 = 3.33 mA 5.74 mA 8.03 mA
+ 3 = 4.99 mA 8.61 mA 12.05 mA
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3 ]
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+ - clocks
+ - VDDA-supply
+ - VDDIO-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clks 150>;
+ micbias-resistor-k-ohms = <2>;
+ micbias-voltage-m-volts = <2250>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/sound/fsl,xcvr.yaml b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
index 0eb0c1b..5e28010 100644
--- a/dts/upstream/Bindings/sound/fsl,xcvr.yaml
+++ b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
@@ -22,6 +22,7 @@
enum:
- fsl,imx8mp-xcvr
- fsl,imx93-xcvr
+ - fsl,imx95-xcvr
reg:
items:
@@ -41,6 +42,7 @@
items:
- description: WAKEUPMIX Audio XCVR Interrupt 1
- description: WAKEUPMIX Audio XCVR Interrupt 2
+ - description: SPDIF wakeup interrupt from PHY
minItems: 1
clocks:
@@ -49,6 +51,9 @@
- description: PHY clock
- description: SPBA clock
- description: PLL clock
+ - description: PLL clock source for 8kHz series
+ - description: PLL clock source for 11kHz series
+ minItems: 4
clock-names:
items:
@@ -56,6 +61,9 @@
- const: phy
- const: spba
- const: pll_ipg
+ - const: pll8k
+ - const: pll11k
+ minItems: 4
dmas:
items:
@@ -79,15 +87,25 @@
- clock-names
- dmas
- dma-names
- - resets
allOf:
+ - $ref: dai-common.yaml#
- if:
properties:
compatible:
contains:
+ const: fsl,imx8mp-xcvr
+ then:
+ required:
+ - resets
+
+ - if:
+ properties:
+ compatible:
+ contains:
enum:
- fsl,imx93-xcvr
+ - fsl,imx95-xcvr
then:
properties:
interrupts:
@@ -96,9 +114,24 @@
else:
properties:
interrupts:
- maxItems: 1
+ minItems: 3
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mp-xcvr
+ - fsl,imx93-xcvr
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ maxItems: 4
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -113,7 +146,9 @@
<0x30cc0c00 0x080>,
<0x30cc0e00 0x080>;
reg-names = "ram", "regs", "rxfifo", "txfifo";
- interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
diff --git a/dts/upstream/Bindings/sound/fsl-asoc-card.yaml b/dts/upstream/Bindings/sound/fsl-asoc-card.yaml
index 9922664..92aa47e 100644
--- a/dts/upstream/Bindings/sound/fsl-asoc-card.yaml
+++ b/dts/upstream/Bindings/sound/fsl-asoc-card.yaml
@@ -67,6 +67,11 @@
- fsl,imx-audio-wm8962
- items:
- enum:
+ - fsl,imx-sabreauto-spdif
+ - fsl,imx6sx-sdb-spdif
+ - const: fsl,imx-audio-spdif
+ - items:
+ - enum:
- fsl,imx-audio-ac97
- fsl,imx-audio-cs42888
- fsl,imx-audio-cs427x
@@ -81,6 +86,7 @@
- fsl,imx-audio-wm8960
- fsl,imx-audio-wm8962
- fsl,imx-audio-wm8958
+ - fsl,imx-audio-spdif
model:
$ref: /schemas/types.yaml#/definitions/string
@@ -93,8 +99,15 @@
need to add ASRC support via DPCM.
audio-codec:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: The phandle of an audio codec
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The phandle of an audio codec.
+ With "fsl,imx-audio-spdif", either SPDIF audio codec spdif_transmitter,
+ spdif_receiver or both.
+ minItems: 1
+ maxItems: 2
+ items:
+ maxItems: 1
audio-cpu:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -150,8 +163,10 @@
description: dai-link uses bit clock inversion.
mclk-id:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: main clock id, specific for each card configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Main clock id for each codec, specific for each card configuration.
+ minItems: 1
+ maxItems: 2
mux-int-port:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -167,6 +182,27 @@
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of an CPU DAI controller
+ spdif-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ deprecated: true
+ description: The phandle of an S/PDIF CPU DAI controller.
+
+ spdif-out:
+ type: boolean
+ deprecated: true
+ description: |
+ If present, the transmitting function of S/PDIF will be enabled,
+ indicating there's a physical S/PDIF out connector or jack on the
+ board or it's connecting to some other IP block, such as an HDMI
+ encoder or display-controller.
+
+ spdif-in:
+ type: boolean
+ deprecated: true
+ description: |
+ If present, the receiving function of S/PDIF will be enabled,
+ indicating there is a physical S/PDIF in connector/jack on the board.
+
required:
- compatible
- model
@@ -195,3 +231,12 @@
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
};
+
+ - |
+ sound-spdif-asrc {
+ compatible = "fsl,imx-audio-spdif";
+ model = "spdif-asrc-audio";
+ audio-cpu = <&spdif>;
+ audio-asrc = <&easrc>;
+ audio-codec = <&spdifdit>, <&spdifdir>;
+ };
diff --git a/dts/upstream/Bindings/sound/linux,spdif-dit.yaml b/dts/upstream/Bindings/sound/linux,spdif-dit.yaml
deleted file mode 100644
index fe5f075..0000000
--- a/dts/upstream/Bindings/sound/linux,spdif-dit.yaml
+++ /dev/null
@@ -1,37 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/linux,spdif-dit.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Dummy SPDIF Transmitter
-
-maintainers:
- - Mark Brown <broonie@kernel.org>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- const: linux,spdif-dit
-
- "#sound-dai-cells":
- const: 0
-
- sound-name-prefix: true
-
-required:
- - "#sound-dai-cells"
- - compatible
-
-additionalProperties: false
-
-examples:
- - |
- spdif-out {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dit";
- };
-
-...
diff --git a/dts/upstream/Bindings/sound/linux,spdif.yaml b/dts/upstream/Bindings/sound/linux,spdif.yaml
new file mode 100644
index 0000000..0f4893e
--- /dev/null
+++ b/dts/upstream/Bindings/sound/linux,spdif.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/linux,spdif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dummy SPDIF Transmitter/Receiver
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - linux,spdif-dit
+ - linux,spdif-dir
+
+ "#sound-dai-cells":
+ const: 0
+
+ sound-name-prefix: true
+
+required:
+ - "#sound-dai-cells"
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/maxim,max98088.txt b/dts/upstream/Bindings/sound/maxim,max98088.txt
deleted file mode 100644
index da764d9..0000000
--- a/dts/upstream/Bindings/sound/maxim,max98088.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-MAX98088 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible: "maxim,max98088" or "maxim,max98089".
-- reg: The I2C address of the device.
-
-Optional properties:
-
-- clocks: the clock provider of MCLK, see ../clock/clock-bindings.txt section
- "consumer" for more information.
-- clock-names: must be set to "mclk"
-
-Example:
-
-max98089: codec@10 {
- compatible = "maxim,max98089";
- reg = <0x10>;
- clocks = <&clks IMX6QDL_CLK_CKO2>;
- clock-names = "mclk";
-};
diff --git a/dts/upstream/Bindings/sound/maxim,max98088.yaml b/dts/upstream/Bindings/sound/maxim,max98088.yaml
new file mode 100644
index 0000000..e4a2967
--- /dev/null
+++ b/dts/upstream/Bindings/sound/maxim,max98088.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/maxim,max98088.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MAX98088 audio CODEC
+
+maintainers:
+ - Abdulrasaq Lawani <abdulrasaqolawani@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - maxim,max98088
+ - maxim,max98089
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: master clock
+
+ clock-names:
+ items:
+ - const: mclk
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ audio-codec@10 {
+ compatible = "maxim,max98089";
+ reg = <0x10>;
+ clocks = <&clks 0>;
+ clock-names = "mclk";
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/mscc,zl38060.yaml b/dts/upstream/Bindings/sound/mscc,zl38060.yaml
new file mode 100644
index 0000000..994313f
--- /dev/null
+++ b/dts/upstream/Bindings/sound/mscc,zl38060.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mscc,zl38060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZL38060 Connected Home Audio Processor from Microsemi.
+
+description: |
+ The ZL38060 is a "Connected Home Audio Processor" from Microsemi,
+ which consists of a Digital Signal Processor (DSP), several Digital
+ Audio Interfaces (DAIs), analog outputs, and a block of 14 GPIOs.
+
+maintainers:
+ - Jaroslav Kysela <perex@perex.cz>
+ - Takashi Iwai <tiwai@suse.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: mscc,zl38060
+
+ reg:
+ description:
+ SPI device address.
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 24000000
+
+ reset-gpios:
+ description:
+ A GPIO line handling reset of the chip. As the line is active low,
+ it should be marked GPIO_ACTIVE_LOW (see ../gpio/gpio.txt)
+ maxItems: 1
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#gpio-cells'
+ - gpio-controller
+ - '#sound-dai-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec: zl38060@0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ #sound-dai-cells = <0>;
+ compatible = "mscc,zl38060";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/nuvoton,nau8824.yaml b/dts/upstream/Bindings/sound/nuvoton,nau8824.yaml
index 3dbf438..232dc16 100644
--- a/dts/upstream/Bindings/sound/nuvoton,nau8824.yaml
+++ b/dts/upstream/Bindings/sound/nuvoton,nau8824.yaml
@@ -23,6 +23,14 @@
'#sound-dai-cells':
const: 0
+ clocks:
+ items:
+ - description: The phandle of the master clock to the CODEC
+
+ clock-names:
+ items:
+ - const: mclk
+
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/sound/nxp,lpc3220-i2s.yaml b/dts/upstream/Bindings/sound/nxp,lpc3220-i2s.yaml
new file mode 100644
index 0000000..40a0877
--- /dev/null
+++ b/dts/upstream/Bindings/sound/nxp,lpc3220-i2s.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nxp,lpc3220-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC32XX I2S Controller
+
+description:
+ The I2S controller in LPC32XX SoCs, ASoC DAI.
+
+maintainers:
+ - J.M.B. Downing <jonathan.downing@nautel.com>
+ - Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - nxp,lpc3220-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input clock of the peripheral.
+
+ dmas:
+ items:
+ - description: RX DMA Channel
+ - description: TX DMA Channel
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - dmas
+ - dma-names
+ - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc32xx-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2s@20094000 {
+ compatible = "nxp,lpc3220-i2s";
+ reg = <0x20094000 0x1000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_I2S0>;
+ dmas = <&dma 0 1>, <&dma 13 1>;
+ dma-names = "rx", "tx";
+ #sound-dai-cells = <0>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/omap-mcpdm.txt b/dts/upstream/Bindings/sound/omap-mcpdm.txt
deleted file mode 100644
index ff98a0c..0000000
--- a/dts/upstream/Bindings/sound/omap-mcpdm.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* Texas Instruments OMAP4+ McPDM
-
-Required properties:
-- compatible: "ti,omap4-mcpdm"
-- reg: Register location and size as an array:
- <MPU access base address, size>,
- <L3 interconnect address, size>;
-- interrupts: Interrupt number for McPDM
-- ti,hwmods: Name of the hwmod associated to the McPDM
-- clocks: phandle for the pdmclk provider, likely <&twl6040>
-- clock-names: Must be "pdmclk"
-
-Example:
-
-mcpdm: mcpdm@40132000 {
- compatible = "ti,omap4-mcpdm";
- reg = <0x40132000 0x7f>, /* MPU private access */
- <0x49032000 0x7f>; /* L3 Interconnect */
- interrupts = <0 112 0x4>;
- interrupt-parent = <&gic>;
- ti,hwmods = "mcpdm";
-};
-
-In board DTS file the pdmclk needs to be added:
-
-&mcpdm {
- clocks = <&twl6040>;
- clock-names = "pdmclk";
- status = "okay";
-};
diff --git a/dts/upstream/Bindings/sound/pcm512x.txt b/dts/upstream/Bindings/sound/pcm512x.txt
index 77006a4..47878a6 100644
--- a/dts/upstream/Bindings/sound/pcm512x.txt
+++ b/dts/upstream/Bindings/sound/pcm512x.txt
@@ -6,7 +6,7 @@
Required properties:
- compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141",
- "ti,pcm5142", "ti,tas5754" or "ti,tas5756"
+ "ti,pcm5142", "ti,pcm5242", "ti,tas5754" or "ti,tas5756"
- reg : the I2C address of the device for I2C, the chip select
number for SPI.
diff --git a/dts/upstream/Bindings/sound/qcom,apq8096.txt b/dts/upstream/Bindings/sound/qcom,apq8096.txt
deleted file mode 100644
index e1b9fa8..0000000
--- a/dts/upstream/Bindings/sound/qcom,apq8096.txt
+++ /dev/null
@@ -1,128 +0,0 @@
-* Qualcomm Technologies APQ8096 ASoC sound card driver
-
-This binding describes the APQ8096 sound card, which uses qdsp for audio.
-
-- compatible:
- Usage: required
- Value type: <stringlist>
- Definition: must be "qcom,apq8096-sndcard"
-
-- audio-routing:
- Usage: Optional
- Value type: <stringlist>
- Definition: A list of the connections between audio components.
- Each entry is a pair of strings, the first being the
- connection's sink, the second being the connection's
- source. Valid names could be power supplies, MicBias
- of codec and the jacks on the board:
- Valid names include:
-
- Board Connectors:
- "Headphone Left"
- "Headphone Right"
- "Earphone"
- "Line Out1"
- "Line Out2"
- "Line Out3"
- "Line Out4"
- "Analog Mic1"
- "Analog Mic2"
- "Analog Mic3"
- "Analog Mic4"
- "Analog Mic5"
- "Analog Mic6"
- "Digital Mic2"
- "Digital Mic3"
-
- Audio pins and MicBias on WCD9335 Codec:
- "MIC_BIAS1"
- "MIC_BIAS2"
- "MIC_BIAS3"
- "MIC_BIAS4"
- "AMIC1"
- "AMIC2"
- "AMIC3"
- "AMIC4"
- "AMIC5"
- "AMIC6"
- "AMIC6"
- "DMIC1"
- "DMIC2"
- "DMIC3"
-
-- model:
- Usage: required
- Value type: <stringlist>
- Definition: The user-visible name of this sound card.
-
-- aux-devs
- Usage: optional
- Value type: <array of phandles>
- Definition: A list of phandles for auxiliary devices (e.g. analog
- amplifiers) that do not appear directly within the DAI
- links. Should be connected to another audio component
- using "audio-routing".
-
-= dailinks
-Each subnode of sndcard represents either a dailink, and subnodes of each
-dailinks would be cpu/codec/platform dais.
-
-- link-name:
- Usage: required
- Value type: <string>
- Definition: User friendly name for dai link
-
-= CPU, PLATFORM, CODEC dais subnodes
-- cpu:
- Usage: required
- Value type: <subnode>
- Definition: cpu dai sub-node
-
-- codec:
- Usage: Optional
- Value type: <subnode>
- Definition: codec dai sub-node
-
-- platform:
- Usage: Optional
- Value type: <subnode>
- Definition: platform dai sub-node
-
-- sound-dai:
- Usage: required
- Value type: <phandle with arguments>
- Definition: dai phandle/s and port of CPU/CODEC/PLATFORM node.
-
-Obsolete:
- qcom,model: String for soundcard name (Use model instead)
- qcom,audio-routing: A list of the connections between audio components.
- (Use audio-routing instead)
-
-Example:
-
-audio {
- compatible = "qcom,apq8096-sndcard";
- model = "DB820c";
-
- mm1-dai-link {
- link-name = "MultiMedia1";
- cpu {
- sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
- };
- };
-
- hdmi-dai-link {
- link-name = "HDMI Playback";
- cpu {
- sound-dai = <&q6afe HDMI_RX>;
- };
-
- platform {
- sound-dai = <&q6adm>;
- };
-
- codec {
- sound-dai = <&hdmi 0>;
- };
- };
-};
diff --git a/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital-codec.yaml b/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital-codec.yaml
new file mode 100644
index 0000000..a899c4e
--- /dev/null
+++ b/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital-codec.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,msm8916-wcd-digital-codec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8916 WCD Digital Audio Codec
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ The digital WCD audio codec found on Qualcomm MSM8916 LPASS.
+
+properties:
+ compatible:
+ const: qcom,msm8916-wcd-digital-codec
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: ahbix-clk
+ - const: mclk
+
+ '#sound-dai-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#sound-dai-cells'
+
+allOf:
+ - $ref: dai-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8916.h>
+ audio-codec@771c000 {
+ compatible = "qcom,msm8916-wcd-digital-codec";
+ reg = <0x0771c000 0x400>;
+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+ <&gcc GCC_CODEC_DIGCODEC_CLK>;
+ clock-names = "ahbix-clk", "mclk";
+ #sound-dai-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital.txt b/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital.txt
deleted file mode 100644
index 1c8e4cb..0000000
--- a/dts/upstream/Bindings/sound/qcom,msm8916-wcd-digital.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-msm8916 digital audio CODEC
-
-## Bindings for codec core in lpass:
-
-Required properties
- - compatible = "qcom,msm8916-wcd-digital-codec";
- - reg: address space for lpass codec.
- - clocks: Handle to mclk and ahbclk
- - clock-names: should be "mclk", "ahbix-clk".
-
-Example:
-
-audio-codec@771c000{
- compatible = "qcom,msm8916-wcd-digital-codec";
- reg = <0x0771c000 0x400>;
- clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
- <&gcc GCC_CODEC_DIGCODEC_CLK>;
- clock-names = "ahbix-clk", "mclk";
- #sound-dai-cells = <1>;
-};
diff --git a/dts/upstream/Bindings/sound/qcom,sm8250.yaml b/dts/upstream/Bindings/sound/qcom,sm8250.yaml
index b2e15eb..c9076dc 100644
--- a/dts/upstream/Bindings/sound/qcom,sm8250.yaml
+++ b/dts/upstream/Bindings/sound/qcom,sm8250.yaml
@@ -28,6 +28,7 @@
- const: qcom,sm8450-sndcard
- enum:
- qcom,apq8016-sbc-sndcard
+ - qcom,apq8096-sndcard
- qcom,msm8916-qdsp6-sndcard
- qcom,qcm6490-idp-sndcard
- qcom,qcs6490-rb3gen2-sndcard
diff --git a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
index beb0ff0..a65b1d1 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
@@ -199,10 +199,11 @@
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
codec@1,0{
compatible = "slim217,250";
reg = <1 0>;
- reset-gpios = <&tlmm 64 0>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&wcd9340_ifd>;
#sound-dai-cells = <1>;
interrupt-parent = <&tlmm>;
diff --git a/dts/upstream/Bindings/sound/qcom,wcd937x-sdw.yaml b/dts/upstream/Bindings/sound/qcom,wcd937x-sdw.yaml
new file mode 100644
index 0000000..d3cf8f5
--- /dev/null
+++ b/dts/upstream/Bindings/sound/qcom,wcd937x-sdw.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SoundWire Slave devices on WCD9370/WCD9375
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire slave devices. This bindings is for the
+ slave devices.
+
+properties:
+ compatible:
+ const: sdw20217010a00
+
+ reg:
+ maxItems: 1
+
+ qcom,tx-port-mapping:
+ description: |
+ Specifies static port mapping between device and host tx ports.
+ In the order of the device port index which are adc1_port, adc23_port,
+ dmic03_mbhc_port, dmic46_port.
+ Supports maximum 4 tx soundwire ports.
+
+ WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
+ WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
+ WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
+ WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
+
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 4
+ maxItems: 4
+ items:
+ enum: [1, 2, 3, 4]
+
+ qcom,rx-port-mapping:
+ description: |
+ Specifies static port mapping between device and host rx ports.
+ In the order of device port index which are hph_port, clsh_port,
+ comp_port, lo_port, dsd port.
+ Supports maximum 5 rx soundwire ports.
+
+ WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
+ WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
+ WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
+ WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
+ WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
+
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 5
+ maxItems: 5
+ items:
+ enum: [1, 2, 3, 4, 5]
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soundwire@3210000 {
+ reg = <0x03210000 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ wcd937x_rx: codec@0,4 {
+ compatible = "sdw20217010a00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+ };
+
+ soundwire@3230000 {
+ reg = <0x03230000 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ wcd937x_tx: codec@0,3 {
+ compatible = "sdw20217010a00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/qcom,wcd937x.yaml b/dts/upstream/Bindings/sound/qcom,wcd937x.yaml
new file mode 100644
index 0000000..f942037
--- /dev/null
+++ b/dts/upstream/Bindings/sound/qcom,wcd937x.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd937x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCD9370/WCD9375 Audio Codec
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire slave devices.
+
+allOf:
+ - $ref: dai-common.yaml#
+ - $ref: qcom,wcd93xx-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,wcd9370-codec
+ - items:
+ - const: qcom,wcd9375-codec
+ - const: qcom,wcd9370-codec
+
+ vdd-px-supply:
+ description: A reference to the 1.8V I/O supply
+
+required:
+ - compatible
+ - vdd-px-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ codec {
+ compatible = "qcom,wcd9370-codec";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&wcd_reset_n>;
+ pinctrl-1 = <&wcd_reset_n_sleep>;
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
+ vdd-buck-supply = <&vreg_l17b_1p8>;
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-px-supply = <&vreg_l18b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob>;
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,rx-device = <&wcd937x_rx>;
+ qcom,tx-device = <&wcd937x_tx>;
+ #sound-dai-cells = <1>;
+ };
+
+ /* ... */
+
+ soundwire@3210000 {
+ reg = <0x03210000 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ wcd937x_rx: codec@0,4 {
+ compatible = "sdw20217010a00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+ };
+
+ soundwire@3230000 {
+ reg = <0x03230000 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ wcd937x_tx: codec@0,3 {
+ compatible = "sdw20217010a00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <1 2 3 4>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/sound/qcom,wcd938x.yaml b/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
index cf6c378..1053135 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
@@ -34,9 +34,10 @@
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
codec {
compatible = "qcom,wcd9380-codec";
- reset-gpios = <&tlmm 32 0>;
+ reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <1>;
qcom,tx-device = <&wcd938x_tx>;
qcom,rx-device = <&wcd938x_rx>;
diff --git a/dts/upstream/Bindings/sound/qcom,wcd939x.yaml b/dts/upstream/Bindings/sound/qcom,wcd939x.yaml
index 6e76f6a..c69291f 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd939x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd939x.yaml
@@ -52,10 +52,10 @@
examples:
- |
- #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
codec {
compatible = "qcom,wcd9390-codec";
- reset-gpios = <&tlmm 32 IRQ_TYPE_NONE>;
+ reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <1>;
qcom,tx-device = <&wcd939x_tx>;
qcom,rx-device = <&wcd939x_rx>;
diff --git a/dts/upstream/Bindings/sound/qcom,wsa883x.yaml b/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
index 8e462cd..14d312f 100644
--- a/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
@@ -32,6 +32,14 @@
vdd-supply:
description: VDD Supply for the Codec
+ qcom,port-mapping:
+ description: |
+ Specifies static port mapping between slave and master ports.
+ In the order of slave port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 4
+ maxItems: 4
+
'#thermal-sensor-cells':
const: 0
diff --git a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
index 22798d2..83e0360 100644
--- a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
@@ -32,6 +32,14 @@
description: Powerdown/Shutdown line to use (pin SD_N)
maxItems: 1
+ qcom,port-mapping:
+ description: |
+ Specifies static port mapping between slave and master ports.
+ In the order of slave port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 6
+ maxItems: 6
+
'#sound-dai-cells':
const: 0
diff --git a/dts/upstream/Bindings/sound/realtek,rt1019.yaml b/dts/upstream/Bindings/sound/realtek,rt1019.yaml
new file mode 100644
index 0000000..adf5e38
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt1019.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt1019.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT1019 Mono Class-D Audio Amplifier
+
+maintainers:
+ - jack.yu@realtek.com
+
+properties:
+ compatible:
+ const: realtek,rt1019
+
+ reg:
+ maxItems: 1
+ description: I2C address of the device.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rt1019: codec@28 {
+ compatible = "realtek,rt1019";
+ reg = <0x28>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5514.yaml b/dts/upstream/Bindings/sound/realtek,rt5514.yaml
new file mode 100644
index 0000000..7fbf773
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5514.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5514.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT5514 audio CODEC
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+description: |
+ This device supports both I2C and SPI.
+
+ Pins on the device (for linking into audio routes) for I2C:
+ * DMIC1L
+ * DMIC1R
+ * DMIC2L
+ * DMIC2R
+ * AMICL
+ * AMICR
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: realtek,rt5514
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Master clock to the CODEC
+
+ clock-names:
+ items:
+ - const: mclk
+
+ interrupts:
+ maxItems: 1
+ description: The interrupt number to the cpu.
+
+ realtek,dmic-init-delay-ms:
+ description: Set the DMIC initial delay (ms) to wait it ready for I2C.
+
+ spi-max-frequency: true
+
+ wakeup-source:
+ type: boolean
+ description: Flag to indicate this device can wake system (suspend/resume).
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@57 {
+ compatible = "realtek,rt5514";
+ reg = <0x57>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5631.yaml b/dts/upstream/Bindings/sound/realtek,rt5631.yaml
new file mode 100644
index 0000000..747a731
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5631.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5631.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ALC5631/RT5631 audio CODEC
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+description: |
+ This device supports I2C only.
+
+ Pins on the device (for linking into audio routes):
+ * SPK_OUT_R_P
+ * SPK_OUT_R_N
+ * SPK_OUT_L_P
+ * SPK_OUT_L_N
+ * HP_OUT_L
+ * HP_OUT_R
+ * AUX_OUT2_LP
+ * AUX_OUT2_RN
+ * AUX_OUT1_LP
+ * AUX_OUT1_RN
+ * AUX_IN_L_JD
+ * AUX_IN_R_JD
+ * MONO_IN_P
+ * MONO_IN_N
+ * MIC1_P
+ * MIC1_N
+ * MIC2_P
+ * MIC2_N
+ * MONO_OUT_P
+ * MONO_OUT_N
+ * MICBIAS1
+ * MICBIAS2
+
+properties:
+ compatible:
+ enum:
+ - realtek,alc5631
+ - realtek,rt5631
+
+ reg:
+ maxItems: 1
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec@1a {
+ compatible = "realtek,alc5631";
+ reg = <0x1a>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5645.yaml b/dts/upstream/Bindings/sound/realtek,rt5645.yaml
new file mode 100644
index 0000000..13f09f1
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5645.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5645.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT5650/RT5645 audio CODEC
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+description: |
+ This device supports I2C only.
+
+ Pins on the device (for linking into audio routes) for RT5645/RT5650:
+ * DMIC L1
+ * DMIC R1
+ * DMIC L2
+ * DMIC R2
+ * IN1P
+ * IN1N
+ * IN2P
+ * IN2N
+ * Haptic Generator
+ * HPOL
+ * HPOR
+ * LOUTL
+ * LOUTR
+ * PDM1L
+ * PDM1R
+ * SPOL
+ * SPOR
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - realtek,rt5645
+ - realtek,rt5650
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: The CODEC's interrupt output.
+
+ avdd-supply:
+ description: Power supply for AVDD, providing 1.8V.
+
+ cpvdd-supply:
+ description: Power supply for CPVDD, providing 3.5V.
+
+ hp-detect-gpios:
+ description:
+ A GPIO spec for the external headphone detect pin. If jd-mode = 0, we
+ will get the JD status by getting the value of hp-detect-gpios.
+ maxItems: 1
+
+ cbj-sleeve-gpios:
+ description:
+ A GPIO spec to control the external combo jack circuit to tie the
+ sleeve/ring2 contacts to the ground or floating. It could avoid some
+ electric noise from the active speaker jacks.
+ maxItems: 1
+
+ realtek,in2-differential:
+ description:
+ Indicate MIC2 input are differential, rather than single-ended.
+ type: boolean
+
+ realtek,dmic1-data-pin:
+ description: Specify which pin to be used as DMIC1 data pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # dmic1 is not used
+ - 1 # using IN2P pin as dmic1 data pin
+ - 2 # using GPIO6 pin as dmic1 data pin
+ - 3 # using GPIO10 pin as dmic1 data pin
+ - 4 # using GPIO12 pin as dmic1 data pin
+
+ realtek,dmic2-data-pin:
+ description: Specify which pin to be used as DMIC2 data pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # dmic2 is not used
+ - 1 # using IN2N pin as dmic2 data pin
+ - 2 # using GPIO5 pin as dmic2 data pin
+ - 3 # using GPIO11 pin as dmic2 data pin
+
+ realtek,jd-mode:
+ description: The JD mode of rt5645/rt5650.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # rt5645/rt5650 JD function is not used
+ - 1 # Mode-0 (VDD=3.3V), two port jack detection
+ - 2 # Mode-1 (VDD=3.3V), one port jack detection
+ - 3 # Mode-2 (VDD=1.8V), one port jack detection
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - avdd-supply
+ - cpvdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1a {
+ compatible = "realtek,rt5650";
+ reg = <0x1a>;
+ hp-detect-gpios = <&gpio 19 0>;
+ cbj-sleeve-gpios = <&gpio 20 0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ avdd-supply = <&avdd_reg>;
+ cpvdd-supply = <&cpvdd_supply>;
+ realtek,jd-mode = <3>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5659.yaml b/dts/upstream/Bindings/sound/realtek,rt5659.yaml
new file mode 100644
index 0000000..1100ffd
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5659.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5659.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT5659/RT5658 audio CODEC
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+description: |
+ This device supports I2C only.
+
+ Pins on the device (for linking into audio routes) for RT5659/RT5658:
+ * DMIC L1
+ * DMIC R1
+ * DMIC L2
+ * DMIC R2
+ * IN1P
+ * IN1N
+ * IN2P
+ * IN2N
+ * IN3P
+ * IN3N
+ * IN4P
+ * IN4N
+ * HPOL
+ * HPOR
+ * SPOL
+ * SPOR
+ * LOUTL
+ * LOUTR
+ * MONOOUT
+ * PDML
+ * PDMR
+ * SPDIF
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - realtek,rt5659
+ - realtek,rt5658
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+ realtek,dmic1-data-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # dmic1 is not used
+ - 1 # using IN2N pin as dmic1 data pin
+ - 2 # using GPIO5 pin as dmic1 data pin
+ - 3 # using GPIO9 pin as dmic1 data pin
+ - 4 # using GPIO11 pin as dmic1 data pin
+ description: Specify which pin to be used as DMIC1 data pin.
+ default: 0
+
+ realtek,dmic2-data-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # dmic2 is not used
+ - 1 # using IN2P pin as dmic2 data pin
+ - 2 # using GPIO6 pin as dmic2 data pin
+ - 3 # using GPIO10 pin as dmic2 data pin
+ - 4 # using GPIO12 pin as dmic2 data pin
+ description: Specify which pin to be used as DMIC2 data pin.
+ default: 0
+
+ realtek,jd-src:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # No JD is used
+ - 1 # using JD3 as JD source
+ - 2 # JD source for Intel HDA header
+ description: Specify which JD source be used.
+ default: 0
+
+ realtek,ldo1-en-gpios:
+ maxItems: 1
+ description: CODEC's LDO1_EN pin.
+
+ realtek,reset-gpios:
+ maxItems: 1
+ description: CODEC's RESET pin.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1b {
+ compatible = "realtek,rt5659";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ realtek,ldo1-en-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5677.yaml b/dts/upstream/Bindings/sound/realtek,rt5677.yaml
new file mode 100644
index 0000000..9ce23e5
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5677.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5677.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RT5677 audio CODEC
+
+maintainers:
+ - Animesh Agarwal <animeshagarwal28@gmail.com>
+
+description: |
+ This device supports I2C only.
+
+ Pins on the device (for linking into audio routes):
+ * IN1P
+ * IN1N
+ * IN2P
+ * IN2N
+ * MICBIAS1
+ * DMIC1
+ * DMIC2
+ * DMIC3
+ * DMIC4
+ * LOUT1
+ * LOUT2
+ * LOUT3
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: realtek,rt5677
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ realtek,pow-ldo2-gpio:
+ maxItems: 1
+ description: CODEC's POW_LDO2 pin.
+
+ realtek,reset-gpio:
+ maxItems: 1
+ description: CODEC's RESET pin. Active low.
+
+ realtek,gpio-config:
+ description: |
+ Array of six 8bit elements that configures GPIO.
+ 0 - floating (reset value)
+ 1 - pull down
+ 2 - pull up
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 6
+ maxItems: 6
+ items:
+ maximum: 2
+
+ realtek,jd1-gpio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # OFF
+ - 1 # GPIO1 for jd1.
+ - 2 # GPIO2 for jd1.
+ - 3 # GPIO3 for jd1.
+ description: Configures GPIO Mic Jack detection 1.
+
+ realtek,jd2-gpio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # OFF
+ - 1 # GPIO4 for jd2.
+ - 2 # GPIO5 for jd2.
+ - 3 # GPIO6 for jd2.
+ description: Configures GPIO Mic Jack detection 2.
+
+ realtek,jd3-gpio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # OFF
+ - 1 # GPIO4 for jd3.
+ - 2 # GPIO5 for jd3.
+ - 3 # GPIO6 for jd3.
+ description: Configures GPIO Mic Jack detection 3.
+
+patternProperties:
+ '^realtek,in[1-2]-differential$':
+ type: boolean
+ description: Indicate MIC1/2 input are differential, rather than
+ single-ended.
+
+ '^realtek,lout[1-3]-differential$':
+ type: boolean
+ description: Indicate LOUT1/2/3 outputs are differential, rather than
+ single-ended.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - gpio-controller
+ - '#gpio-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@2c {
+ compatible = "realtek,rt5677";
+ reg = <0x2c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ realtek,pow-ldo2-gpio = <&gpio 3 GPIO_ACTIVE_HIGH>;
+ realtek,reset-gpio = <&gpio 3 GPIO_ACTIVE_LOW>;
+ realtek,in1-differential;
+ realtek,gpio-config = <0 0 0 0 0 2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/rt1019.yaml b/dts/upstream/Bindings/sound/rt1019.yaml
deleted file mode 100644
index 3d5a91a..0000000
--- a/dts/upstream/Bindings/sound/rt1019.yaml
+++ /dev/null
@@ -1,35 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/rt1019.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: RT1019 Mono Class-D Audio Amplifier
-
-maintainers:
- - jack.yu@realtek.com
-
-properties:
- compatible:
- const: realtek,rt1019
-
- reg:
- maxItems: 1
- description: I2C address of the device.
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- rt1019: codec@28 {
- compatible = "realtek,rt1019";
- reg = <0x28>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/rt5514.txt b/dts/upstream/Bindings/sound/rt5514.txt
deleted file mode 100644
index d2cc171..0000000
--- a/dts/upstream/Bindings/sound/rt5514.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-RT5514 audio CODEC
-
-This device supports both I2C and SPI.
-
-Required properties:
-
-- compatible : "realtek,rt5514".
-
-- reg : the I2C address of the device for I2C, the chip select
- number for SPI.
-
-Optional properties:
-
-- clocks: The phandle of the master clock to the CODEC
-- clock-names: Should be "mclk"
-
-- interrupts: The interrupt number to the cpu. The interrupt specifier format
- depends on the interrupt controller.
-
-- realtek,dmic-init-delay-ms
- Set the DMIC initial delay (ms) to wait it ready for I2C.
-
-Pins on the device (for linking into audio routes) for I2C:
-
- * DMIC1L
- * DMIC1R
- * DMIC2L
- * DMIC2R
- * AMICL
- * AMICR
-
-Example:
-
-rt5514: codec@57 {
- compatible = "realtek,rt5514";
- reg = <0x57>;
-};
diff --git a/dts/upstream/Bindings/sound/rt5631.txt b/dts/upstream/Bindings/sound/rt5631.txt
deleted file mode 100644
index 56bc852..0000000
--- a/dts/upstream/Bindings/sound/rt5631.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-ALC5631/RT5631 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
- - compatible : "realtek,alc5631" or "realtek,rt5631"
-
- - reg : the I2C address of the device.
-
-Pins on the device (for linking into audio routes):
-
- * SPK_OUT_R_P
- * SPK_OUT_R_N
- * SPK_OUT_L_P
- * SPK_OUT_L_N
- * HP_OUT_L
- * HP_OUT_R
- * AUX_OUT2_LP
- * AUX_OUT2_RN
- * AUX_OUT1_LP
- * AUX_OUT1_RN
- * AUX_IN_L_JD
- * AUX_IN_R_JD
- * MONO_IN_P
- * MONO_IN_N
- * MIC1_P
- * MIC1_N
- * MIC2_P
- * MIC2_N
- * MONO_OUT_P
- * MONO_OUT_N
- * MICBIAS1
- * MICBIAS2
-
-Example:
-
-alc5631: audio-codec@1a {
- compatible = "realtek,alc5631";
- reg = <0x1a>;
-};
-
-or
-
-rt5631: audio-codec@1a {
- compatible = "realtek,rt5631";
- reg = <0x1a>;
-};
diff --git a/dts/upstream/Bindings/sound/rt5645.txt b/dts/upstream/Bindings/sound/rt5645.txt
deleted file mode 100644
index c1fa379..0000000
--- a/dts/upstream/Bindings/sound/rt5645.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-RT5650/RT5645 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : One of "realtek,rt5645" or "realtek,rt5650".
-
-- reg : The I2C address of the device.
-
-- interrupts : The CODEC's interrupt output.
-
-- avdd-supply: Power supply for AVDD, providing 1.8V.
-
-- cpvdd-supply: Power supply for CPVDD, providing 3.5V.
-
-Optional properties:
-
-- hp-detect-gpios:
- a GPIO spec for the external headphone detect pin. If jd-mode = 0,
- we will get the JD status by getting the value of hp-detect-gpios.
-
-- cbj-sleeve-gpios:
- a GPIO spec to control the external combo jack circuit to tie the sleeve/ring2
- contacts to the ground or floating. It could avoid some electric noise from the
- active speaker jacks.
-
-- realtek,in2-differential
- Boolean. Indicate MIC2 input are differential, rather than single-ended.
-
-- realtek,dmic1-data-pin
- 0: dmic1 is not used
- 1: using IN2P pin as dmic1 data pin
- 2: using GPIO6 pin as dmic1 data pin
- 3: using GPIO10 pin as dmic1 data pin
- 4: using GPIO12 pin as dmic1 data pin
-
-- realtek,dmic2-data-pin
- 0: dmic2 is not used
- 1: using IN2N pin as dmic2 data pin
- 2: using GPIO5 pin as dmic2 data pin
- 3: using GPIO11 pin as dmic2 data pin
-
--- realtek,jd-mode : The JD mode of rt5645/rt5650
- 0 : rt5645/rt5650 JD function is not used
- 1 : Mode-0 (VDD=3.3V), two port jack detection
- 2 : Mode-1 (VDD=3.3V), one port jack detection
- 3 : Mode-2 (VDD=1.8V), one port jack detection
-
-Pins on the device (for linking into audio routes) for RT5645/RT5650:
-
- * DMIC L1
- * DMIC R1
- * DMIC L2
- * DMIC R2
- * IN1P
- * IN1N
- * IN2P
- * IN2N
- * Haptic Generator
- * HPOL
- * HPOR
- * LOUTL
- * LOUTR
- * PDM1L
- * PDM1R
- * SPOL
- * SPOR
-
-Example:
-
-codec: rt5650@1a {
- compatible = "realtek,rt5650";
- reg = <0x1a>;
- hp-detect-gpios = <&gpio 19 0>;
- cbj-sleeve-gpios = <&gpio 20 0>;
- interrupt-parent = <&gpio>;
- interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
- realtek,dmic-en = "true";
- realtek,en-jd-func = "true";
- realtek,jd-mode = <3>;
-};
diff --git a/dts/upstream/Bindings/sound/rt5659.txt b/dts/upstream/Bindings/sound/rt5659.txt
deleted file mode 100644
index 8f3f62c..0000000
--- a/dts/upstream/Bindings/sound/rt5659.txt
+++ /dev/null
@@ -1,89 +0,0 @@
-RT5659/RT5658 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : One of "realtek,rt5659" or "realtek,rt5658".
-
-- reg : The I2C address of the device.
-
-- interrupts : The CODEC's interrupt output.
-
-Optional properties:
-
-- clocks: The phandle of the master clock to the CODEC
-- clock-names: Should be "mclk"
-
-- realtek,in1-differential
-- realtek,in3-differential
-- realtek,in4-differential
- Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
-
-- realtek,dmic1-data-pin
- 0: dmic1 is not used
- 1: using IN2N pin as dmic1 data pin
- 2: using GPIO5 pin as dmic1 data pin
- 3: using GPIO9 pin as dmic1 data pin
- 4: using GPIO11 pin as dmic1 data pin
-
-- realtek,dmic2-data-pin
- 0: dmic2 is not used
- 1: using IN2P pin as dmic2 data pin
- 2: using GPIO6 pin as dmic2 data pin
- 3: using GPIO10 pin as dmic2 data pin
- 4: using GPIO12 pin as dmic2 data pin
-
-- realtek,jd-src
- 0: No JD is used
- 1: using JD3 as JD source
- 2: JD source for Intel HDA header
-
-- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
-- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
-
-- sound-name-prefix: Please refer to dai-common.yaml
-
-- ports: A Codec may have a single or multiple I2S interfaces. These
- interfaces on Codec side can be described under 'ports' or 'port'.
- When the SoC or host device is connected to multiple interfaces of
- the Codec, the connectivity can be described using 'ports' property.
- If a single interface is used, then 'port' can be used. The usage
- depends on the platform or board design.
- Please refer to Documentation/devicetree/bindings/graph.txt
-
-Pins on the device (for linking into audio routes) for RT5659/RT5658:
-
- * DMIC L1
- * DMIC R1
- * DMIC L2
- * DMIC R2
- * IN1P
- * IN1N
- * IN2P
- * IN2N
- * IN3P
- * IN3N
- * IN4P
- * IN4N
- * HPOL
- * HPOR
- * SPOL
- * SPOR
- * LOUTL
- * LOUTR
- * MONOOUT
- * PDML
- * PDMR
- * SPDIF
-
-Example:
-
-rt5659 {
- compatible = "realtek,rt5659";
- reg = <0x1b>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
- realtek,ldo1-en-gpios =
- <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
-};
diff --git a/dts/upstream/Bindings/sound/rt5677.txt b/dts/upstream/Bindings/sound/rt5677.txt
deleted file mode 100644
index da24300..0000000
--- a/dts/upstream/Bindings/sound/rt5677.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-RT5677 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : "realtek,rt5677".
-
-- reg : The I2C address of the device.
-
-- interrupts : The CODEC's interrupt output.
-
-- gpio-controller : Indicates this device is a GPIO controller.
-
-- #gpio-cells : Should be two. The first cell is the pin number and the
- second cell is used to specify optional parameters (currently unused).
-
-Optional properties:
-
-- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
-- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
-
-- realtek,in1-differential
-- realtek,in2-differential
-- realtek,lout1-differential
-- realtek,lout2-differential
-- realtek,lout3-differential
- Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential,
- rather than single-ended.
-
-- realtek,gpio-config
- Array of six 8bit elements that configures GPIO.
- 0 - floating (reset value)
- 1 - pull down
- 2 - pull up
-
-- realtek,jd1-gpio
- Configures GPIO Mic Jack detection 1.
- Select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively.
-
-- realtek,jd2-gpio
-- realtek,jd3-gpio
- Configures GPIO Mic Jack detection 2 and 3.
- Select 0 ~ 3 as OFF, GPIO4, GPIO5 and GPIO6 respectively.
-
-Pins on the device (for linking into audio routes):
-
- * IN1P
- * IN1N
- * IN2P
- * IN2N
- * MICBIAS1
- * DMIC1
- * DMIC2
- * DMIC3
- * DMIC4
- * LOUT1
- * LOUT2
- * LOUT3
-
-Example:
-
-rt5677 {
- compatible = "realtek,rt5677";
- reg = <0x2c>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- realtek,pow-ldo2-gpio =
- <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
- realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
- realtek,in1-differential = "true";
- realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */
- realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */
-};
diff --git a/dts/upstream/Bindings/sound/samsung,midas-audio.yaml b/dts/upstream/Bindings/sound/samsung,midas-audio.yaml
index 6ec80f5..69ddfd4 100644
--- a/dts/upstream/Bindings/sound/samsung,midas-audio.yaml
+++ b/dts/upstream/Bindings/sound/samsung,midas-audio.yaml
@@ -53,6 +53,9 @@
submic-bias-supply:
description: Supply for the micbias on the Sub microphone
+ headset-mic-bias-supply:
+ description: Supply for the micbias on the Headset microphone
+
fm-sel-gpios:
maxItems: 1
description: GPIO pin for FM selection
@@ -61,6 +64,36 @@
maxItems: 1
description: GPIO pin for line out selection
+ headset-detect-gpios:
+ maxItems: 1
+ description: GPIO for detection of headset insertion
+
+ headset-key-gpios:
+ maxItems: 1
+ description: GPIO for detection of headset key press
+
+ io-channels:
+ maxItems: 1
+ description: IO channel to read micbias voltage for headset detection
+
+ io-channel-names:
+ const: headset-detect
+
+ samsung,headset-4pole-threshold-microvolt:
+ minItems: 2
+ maxItems: 2
+ description:
+ Array containing minimum and maximum IO channel value for 4-pole
+ (with microphone/button) headsets. If the IO channel value is
+ outside of this range, a 3-pole headset is assumed.
+
+ samsung,headset-button-threshold-microvolt:
+ minItems: 3
+ maxItems: 3
+ description: |
+ Array of minimum (inclusive) IO channel values for headset button
+ detection, in order: "Media", "Volume Up" and "Volume Down".
+
required:
- compatible
- cpu
diff --git a/dts/upstream/Bindings/sound/sgtl5000.yaml b/dts/upstream/Bindings/sound/sgtl5000.yaml
deleted file mode 100644
index 1353c05..0000000
--- a/dts/upstream/Bindings/sound/sgtl5000.yaml
+++ /dev/null
@@ -1,113 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/sgtl5000.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale SGTL5000 Stereo Codec
-
-maintainers:
- - Fabio Estevam <festevam@gmail.com>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- const: fsl,sgtl5000
-
- reg:
- maxItems: 1
-
- "#sound-dai-cells":
- const: 0
-
- assigned-clock-parents: true
- assigned-clock-rates: true
- assigned-clocks: true
-
- clocks:
- items:
- - description: the clock provider of SYS_MCLK
-
- VDDA-supply:
- description: the regulator provider of VDDA
-
- VDDIO-supply:
- description: the regulator provider of VDDIO
-
- VDDD-supply:
- description: the regulator provider of VDDD
-
- micbias-resistor-k-ohms:
- description: The bias resistor to be used in kOhms. The resistor can take
- values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
- mentioned or if the value is unknown, then micbias resistor is set to
- 4k.
- enum: [ 0, 2, 4, 8 ]
-
- micbias-voltage-m-volts:
- description: The bias voltage to be used in mVolts. The voltage can take
- values from 1.25V to 3V by 250mV steps. If this node is not mentioned
- or the value is unknown, then the value is set to 1.25V.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 ]
-
- lrclk-strength:
- description: |
- The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
- table below:
-
- VDDIO 1.8V 2.5V 3.3V
- 0 = Disable
- 1 = 1.66 mA 2.87 mA 4.02 mA
- 2 = 3.33 mA 5.74 mA 8.03 mA
- 3 = 4.99 mA 8.61 mA 12.05 mA
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
-
- sclk-strength:
- description: |
- The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
- table below:
-
- VDDIO 1.8V 2.5V 3.3V
- 0 = Disable
- 1 = 1.66 mA 2.87 mA 4.02 mA
- 2 = 3.33 mA 5.74 mA 8.03 mA
- 3 = 4.99 mA 8.61 mA 12.05 mA
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 0, 1, 2, 3 ]
-
- port:
- $ref: audio-graph-port.yaml#
- unevaluatedProperties: false
-
-required:
- - compatible
- - reg
- - "#sound-dai-cells"
- - clocks
- - VDDA-supply
- - VDDIO-supply
-
-unevaluatedProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- codec@a {
- compatible = "fsl,sgtl5000";
- reg = <0x0a>;
- #sound-dai-cells = <0>;
- clocks = <&clks 150>;
- micbias-resistor-k-ohms = <2>;
- micbias-voltage-m-volts = <2250>;
- VDDA-supply = <®_3p3v>;
- VDDIO-supply = <®_3p3v>;
- };
- };
-...
diff --git a/dts/upstream/Bindings/sound/simple-audio-mux.yaml b/dts/upstream/Bindings/sound/simple-audio-mux.yaml
index 9f319ca..194ac1d 100644
--- a/dts/upstream/Bindings/sound/simple-audio-mux.yaml
+++ b/dts/upstream/Bindings/sound/simple-audio-mux.yaml
@@ -24,6 +24,11 @@
description: |
GPIOs used to select the input line.
+ state-labels:
+ description: State of input line. default is "Input 1", "Input 2"
+ $ref: /schemas/types.yaml#/definitions/string-array
+ maxItems: 2
+
sound-name-prefix: true
required:
@@ -37,4 +42,5 @@
mux {
compatible = "simple-audio-mux";
mux-gpios = <&gpio 3 0>;
+ state-labels = "Label_A", "Label_B";
};
diff --git a/dts/upstream/Bindings/sound/spdif-receiver.txt b/dts/upstream/Bindings/sound/spdif-receiver.txt
deleted file mode 100644
index 80f807b..0000000
--- a/dts/upstream/Bindings/sound/spdif-receiver.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Device-Tree bindings for dummy spdif receiver
-
-Required properties:
- - compatible: should be "linux,spdif-dir".
-
-Example node:
-
- codec: spdif-receiver {
- compatible = "linux,spdif-dir";
- };
diff --git a/dts/upstream/Bindings/sound/tas2562.yaml b/dts/upstream/Bindings/sound/tas2562.yaml
deleted file mode 100644
index d28c102..0000000
--- a/dts/upstream/Bindings/sound/tas2562.yaml
+++ /dev/null
@@ -1,81 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2019 Texas Instruments Incorporated
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/tas2562.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Texas Instruments TAS2562 Smart PA
-
-maintainers:
- - Andrew Davis <afd@ti.com>
-
-description: |
- The TAS2562 is a mono, digital input Class-D audio amplifier optimized for
- efficiently driving high peak power into small loudspeakers.
- Integrated speaker voltage and current sense provides for
- real time monitoring of loudspeaker behavior.
-
- Specifications about the audio amplifier can be found at:
- https://www.ti.com/lit/gpn/tas2562
- https://www.ti.com/lit/gpn/tas2564
- https://www.ti.com/lit/gpn/tas2110
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- enum:
- - ti,tas2562
- - ti,tas2564
- - ti,tas2110
-
- reg:
- maxItems: 1
- description: |
- I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
-
- shut-down-gpios:
- maxItems: 1
- description: GPIO used to control the state of the device.
- deprecated: true
-
- shutdown-gpios:
- maxItems: 1
- description: GPIO used to control the state of the device.
-
- interrupts:
- maxItems: 1
-
- ti,imon-slot-no:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: TDM TX current sense time slot.
-
- '#sound-dai-cells':
- # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
- # compatibility but is deprecated.
- enum: [0, 1]
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- codec: codec@4c {
- compatible = "ti,tas2562";
- reg = <0x4c>;
- #sound-dai-cells = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <14>;
- shutdown-gpios = <&gpio1 15 0>;
- ti,imon-slot-no = <0>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/tas2770.yaml b/dts/upstream/Bindings/sound/tas2770.yaml
deleted file mode 100644
index be2536e..0000000
--- a/dts/upstream/Bindings/sound/tas2770.yaml
+++ /dev/null
@@ -1,87 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2019-20 Texas Instruments Incorporated
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/tas2770.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Texas Instruments TAS2770 Smart PA
-
-maintainers:
- - Shi Fu <shifu0704@thundersoft.com>
-
-description: |
- The TAS2770 is a mono, digital input Class-D audio amplifier optimized for
- efficiently driving high peak power into small loudspeakers.
- Integrated speaker voltage and current sense provides for
- real time monitoring of loudspeaker behavior.
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- enum:
- - ti,tas2770
-
- reg:
- maxItems: 1
- description: |
- I2C address of the device can be between 0x41 to 0x48.
-
- reset-gpio:
- maxItems: 1
- description: GPIO used to reset the device.
-
- shutdown-gpios:
- maxItems: 1
- description: GPIO used to control the state of the device.
-
- interrupts:
- maxItems: 1
-
- ti,imon-slot-no:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: TDM TX current sense time slot.
-
- ti,vmon-slot-no:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: TDM TX voltage sense time slot.
-
- ti,asi-format:
- deprecated: true
- $ref: /schemas/types.yaml#/definitions/uint32
- description: Sets TDM RX capture edge.
- enum:
- - 0 # Rising edge
- - 1 # Falling edge
-
- '#sound-dai-cells':
- # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
- # compatibility but is deprecated.
- enum: [0, 1]
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- codec: codec@41 {
- compatible = "ti,tas2770";
- reg = <0x41>;
- #sound-dai-cells = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <14>;
- reset-gpio = <&gpio1 15 0>;
- shutdown-gpios = <&gpio1 14 0>;
- ti,imon-slot-no = <0>;
- ti,vmon-slot-no = <2>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/tas27xx.yaml b/dts/upstream/Bindings/sound/tas27xx.yaml
deleted file mode 100644
index f2d878f..0000000
--- a/dts/upstream/Bindings/sound/tas27xx.yaml
+++ /dev/null
@@ -1,82 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020-2022 Texas Instruments Incorporated
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/tas27xx.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Texas Instruments TAS2764/TAS2780 Smart PA
-
-maintainers:
- - Shenghao Ding <shenghao-ding@ti.com>
-
-description: |
- The TAS2764/TAS2780 is a mono, digital input Class-D audio amplifier
- optimized for efficiently driving high peak power into small
- loudspeakers. Integrated speaker voltage and current sense provides
- for real time monitoring of loudspeaker behavior.
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- enum:
- - ti,tas2764
- - ti,tas2780
-
- reg:
- maxItems: 1
- description: |
- I2C address of the device can be between 0x38 to 0x45.
-
- reset-gpios:
- maxItems: 1
- description: GPIO used to reset the device.
-
- shutdown-gpios:
- maxItems: 1
- description: GPIO used to control the state of the device.
-
- interrupts:
- maxItems: 1
-
- ti,imon-slot-no:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: TDM TX current sense time slot.
-
- ti,vmon-slot-no:
- $ref: /schemas/types.yaml#/definitions/uint32
- description: TDM TX voltage sense time slot.
-
- '#sound-dai-cells':
- # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
- # compatibility but is deprecated.
- enum: [0, 1]
-
-required:
- - compatible
- - reg
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- codec: codec@38 {
- compatible = "ti,tas2764";
- reg = <0x38>;
- #sound-dai-cells = <0>;
- interrupt-parent = <&gpio1>;
- interrupts = <14>;
- reset-gpios = <&gpio1 15 0>;
- shutdown-gpios = <&gpio1 15 0>;
- ti,imon-slot-no = <0>;
- ti,vmon-slot-no = <2>;
- };
- };
-
-...
diff --git a/dts/upstream/Bindings/sound/tas571x.txt b/dts/upstream/Bindings/sound/tas571x.txt
deleted file mode 100644
index 1addc75..0000000
--- a/dts/upstream/Bindings/sound/tas571x.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Texas Instruments TAS5711/TAS5717/TAS5719/TAS5721 stereo power amplifiers
-
-The codec is controlled through an I2C interface. It also has two other
-signals that can be wired up to GPIOs: reset (strongly recommended), and
-powerdown (optional).
-
-Required properties:
-
-- compatible: should be one of the following:
- - "ti,tas5707"
- - "ti,tas5711",
- - "ti,tas5717",
- - "ti,tas5719",
- - "ti,tas5721"
- - "ti,tas5733"
-- reg: The I2C address of the device
-- #sound-dai-cells: must be equal to 0
-
-Optional properties:
-
-- reset-gpios: GPIO specifier for the TAS571x's active low reset line
-- pdn-gpios: GPIO specifier for the TAS571x's active low powerdown line
-- clocks: clock phandle for the MCLK input
-- clock-names: should be "mclk"
-- AVDD-supply: regulator phandle for the AVDD supply (all chips)
-- DVDD-supply: regulator phandle for the DVDD supply (all chips)
-- HPVDD-supply: regulator phandle for the HPVDD supply (5717/5719)
-- PVDD_AB-supply: regulator phandle for the PVDD_AB supply (5717/5719)
-- PVDD_CD-supply: regulator phandle for the PVDD_CD supply (5717/5719)
-- PVDD_A-supply: regulator phandle for the PVDD_A supply (5711)
-- PVDD_B-supply: regulator phandle for the PVDD_B supply (5711)
-- PVDD_C-supply: regulator phandle for the PVDD_C supply (5711)
-- PVDD_D-supply: regulator phandle for the PVDD_D supply (5711)
-- DRVDD-supply: regulator phandle for the DRVDD supply (5721)
-- PVDD-supply: regulator phandle for the PVDD supply (5721)
-
-Example:
-
- tas5717: audio-codec@2a {
- compatible = "ti,tas5717";
- reg = <0x2a>;
- #sound-dai-cells = <0>;
-
- reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- pdn-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
-
- clocks = <&clk_core CLK_I2S>;
- clock-names = "mclk";
- };
diff --git a/dts/upstream/Bindings/sound/tas5805m.yaml b/dts/upstream/Bindings/sound/tas5805m.yaml
deleted file mode 100644
index 12c4197..0000000
--- a/dts/upstream/Bindings/sound/tas5805m.yaml
+++ /dev/null
@@ -1,57 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/tas5805m.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: TAS5805M audio amplifier
-
-maintainers:
- - Daniel Beer <daniel.beer@igorinstitute.com>
-
-description: |
- The TAS5805M is a class D audio amplifier with a built-in DSP.
-
-properties:
- compatible:
- enum:
- - ti,tas5805m
-
- reg:
- maxItems: 1
- description: |
- I2C address of the amplifier. See the datasheet for possible values.
-
- pvdd-supply:
- description: |
- Regulator for audio power supply (PVDD in the datasheet).
-
- pdn-gpios:
- description: |
- Power-down control GPIO (PDN pin in the datasheet).
-
- ti,dsp-config-name:
- description: |
- The name of the DSP configuration that should be loaded for this
- instance. Configuration blobs are sequences of register writes
- generated from TI's PPC3 tool.
- $ref: /schemas/types.yaml#/definitions/string
-
-additionalProperties: false
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- tas5805m: tas5805m@2c {
- reg = <0x2c>;
- compatible = "ti,tas5805m";
-
- pvdd-supply = <&audiopwr>;
- pdn-gpios = <&tlmm 160 0>;
-
- ti,dsp-config-name = "mono_pbtl_48khz";
- };
- };
-...
diff --git a/dts/upstream/Bindings/sound/ti,omap4-mcpdm.yaml b/dts/upstream/Bindings/sound/ti,omap4-mcpdm.yaml
new file mode 100644
index 0000000..cdea0a0
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,omap4-mcpdm.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,omap4-mcpdm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OMAP McPDM
+
+maintainers:
+ - Misael Lopez Cruz <misael.lopez@ti.com>
+
+description:
+ OMAP ALSA SoC DAI driver using McPDM port used by TWL6040
+
+properties:
+ compatible:
+ const: ti,omap4-mcpdm
+
+ reg:
+ items:
+ - description: MPU access base address
+ - description: L3 interconnect address
+
+ reg-names:
+ items:
+ - const: mpu
+ - const: dma
+
+ interrupts:
+ maxItems: 1
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: up_link
+ - const: dn_link
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pdmclk
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - dmas
+ - dma-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ mcpdm@0 {
+ compatible = "ti,omap4-mcpdm";
+ reg = <0x0 0x7f>, /* MPU private access */
+ <0x49032000 0x7f>; /* L3 Interconnect */
+ reg-names = "mpu", "dma";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ dmas = <&sdma 65>, <&sdma 66>;
+ dma-names = "up_link", "dn_link";
+ clocks = <&twl6040>;
+ clock-names = "pdmclk";
+ };
diff --git a/dts/upstream/Bindings/sound/ti,tas2562.yaml b/dts/upstream/Bindings/sound/ti,tas2562.yaml
new file mode 100644
index 0000000..8bc3b0c
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tas2562.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas2562.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TAS2562 Smart PA
+
+maintainers:
+ - Andrew Davis <afd@ti.com>
+
+description: |
+ The TAS2562 is a mono, digital input Class-D audio amplifier optimized for
+ efficiently driving high peak power into small loudspeakers.
+ Integrated speaker voltage and current sense provides for
+ real time monitoring of loudspeaker behavior.
+
+ Specifications about the audio amplifier can be found at:
+ https://www.ti.com/lit/gpn/tas2562
+ https://www.ti.com/lit/gpn/tas2564
+ https://www.ti.com/lit/gpn/tas2110
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,tas2562
+ - ti,tas2564
+ - ti,tas2110
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
+
+ shut-down-gpios:
+ maxItems: 1
+ description: GPIO used to control the state of the device.
+ deprecated: true
+
+ shutdown-gpios:
+ maxItems: 1
+ description: GPIO used to control the state of the device.
+
+ interrupts:
+ maxItems: 1
+
+ ti,imon-slot-no:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TDM TX current sense time slot.
+
+ '#sound-dai-cells':
+ # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
+ # compatibility but is deprecated.
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@4c {
+ compatible = "ti,tas2562";
+ reg = <0x4c>;
+ #sound-dai-cells = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14>;
+ shutdown-gpios = <&gpio1 15 0>;
+ ti,imon-slot-no = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/ti,tas2770.yaml b/dts/upstream/Bindings/sound/ti,tas2770.yaml
new file mode 100644
index 0000000..362c2e6
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tas2770.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019-20 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas2770.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TAS2770 Smart PA
+
+maintainers:
+ - Shi Fu <shifu0704@thundersoft.com>
+
+description: |
+ The TAS2770 is a mono, digital input Class-D audio amplifier optimized for
+ efficiently driving high peak power into small loudspeakers.
+ Integrated speaker voltage and current sense provides for
+ real time monitoring of loudspeaker behavior.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,tas2770
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C address of the device can be between 0x41 to 0x48.
+
+ reset-gpio:
+ maxItems: 1
+ description: GPIO used to reset the device.
+
+ shutdown-gpios:
+ maxItems: 1
+ description: GPIO used to control the state of the device.
+
+ interrupts:
+ maxItems: 1
+
+ ti,imon-slot-no:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TDM TX current sense time slot.
+
+ ti,vmon-slot-no:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TDM TX voltage sense time slot.
+
+ ti,asi-format:
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Sets TDM RX capture edge.
+ enum:
+ - 0 # Rising edge
+ - 1 # Falling edge
+
+ '#sound-dai-cells':
+ # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
+ # compatibility but is deprecated.
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@41 {
+ compatible = "ti,tas2770";
+ reg = <0x41>;
+ #sound-dai-cells = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14>;
+ reset-gpio = <&gpio1 15 0>;
+ shutdown-gpios = <&gpio1 14 0>;
+ ti,imon-slot-no = <0>;
+ ti,vmon-slot-no = <2>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/ti,tas27xx.yaml b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
new file mode 100644
index 0000000..530bc39
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020-2022 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas27xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TAS2764/TAS2780 Smart PA
+
+maintainers:
+ - Shenghao Ding <shenghao-ding@ti.com>
+
+description: |
+ The TAS2764/TAS2780 is a mono, digital input Class-D audio amplifier
+ optimized for efficiently driving high peak power into small
+ loudspeakers. Integrated speaker voltage and current sense provides
+ for real time monitoring of loudspeaker behavior.
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,tas2764
+ - ti,tas2780
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C address of the device can be between 0x38 to 0x45.
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO used to reset the device.
+
+ shutdown-gpios:
+ maxItems: 1
+ description: GPIO used to control the state of the device.
+
+ interrupts:
+ maxItems: 1
+
+ ti,imon-slot-no:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TDM TX current sense time slot.
+
+ ti,vmon-slot-no:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TDM TX voltage sense time slot.
+
+ '#sound-dai-cells':
+ # The codec has a single DAI, the #sound-dai-cells=<1>; case is left in for backward
+ # compatibility but is deprecated.
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@38 {
+ compatible = "ti,tas2764";
+ reg = <0x38>;
+ #sound-dai-cells = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14>;
+ reset-gpios = <&gpio1 15 0>;
+ shutdown-gpios = <&gpio1 15 0>;
+ ti,imon-slot-no = <0>;
+ ti,vmon-slot-no = <2>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/ti,tas57xx.yaml b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
new file mode 100644
index 0000000..2f91723
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas57xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TAS5711/TAS5717/TAS5719/TAS5721 stereo power amplifiers
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - ti,tas5707
+ - ti,tas5711
+ - ti,tas5717
+ - ti,tas5719
+ - ti,tas5721
+ - ti,tas5733
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO for the active low reset line
+
+ pdn-gpios:
+ maxItems: 1
+ description: GPIO for the active low powerdown line
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+ AVDD-supply: true
+ DVDD-supply: true
+ HPVDD-supply: true
+ PVDD_AB-supply: true
+ PVDD_CD-supply: true
+ PVDD_A-supply: true
+ PVDD_B-supply: true
+ PVDD_C-supply: true
+ PVDD_D-supply: true
+ DRVDD-supply: true
+ PVDD-supply: true
+
+ '#sound-dai-cells':
+ const: 0
+
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#sound-dai-cells'
+
+allOf:
+ - $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,tas5717
+ - ti,tas5719
+ then:
+ properties:
+ PVDD_A-supply: false
+ PVDD_B-supply: false
+ PVDD_C-supply: false
+ PVDD_D-supply: false
+ DRVDD-supply: false
+ PVDD-supply: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,tas5711
+ then:
+ properties:
+ HPVDD-supply: false
+ PVDD_AB-supply: false
+ PVDD_CD-supply: false
+ DRVDD-supply: false
+ PVDD-supply: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,tas5721
+ then:
+ properties:
+ HPVDD-supply: false
+ PVDD_AB-supply: false
+ PVDD_CD-supply: false
+ PVDD_A-supply: false
+ PVDD_B-supply: false
+ PVDD_C-supply: false
+ PVDD_D-supply: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@2a {
+ compatible = "ti,tas5717";
+ reg = <0x2a>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&gpio1 15 0>;
+ pdn-gpios = <&gpio1 15 0>;
+ AVDD-supply = <&avdd_supply>;
+ DVDD-supply = <&dvdd_supply>;
+ HPVDD-supply = <&hpvdd_supply>;
+ PVDD_AB-supply = <&pvdd_ab_supply>;
+ PVDD_CD-supply = <&pvdd_cd_supply>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/sound/ti,tas5805m.yaml b/dts/upstream/Bindings/sound/ti,tas5805m.yaml
new file mode 100644
index 0000000..c2c2835
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tas5805m.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tas5805m.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TAS5805M audio amplifier
+
+maintainers:
+ - Daniel Beer <daniel.beer@igorinstitute.com>
+
+description: |
+ The TAS5805M is a class D audio amplifier with a built-in DSP.
+
+properties:
+ compatible:
+ enum:
+ - ti,tas5805m
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C address of the amplifier. See the datasheet for possible values.
+
+ pvdd-supply:
+ description: |
+ Regulator for audio power supply (PVDD in the datasheet).
+
+ pdn-gpios:
+ description: |
+ Power-down control GPIO (PDN pin in the datasheet).
+
+ ti,dsp-config-name:
+ description: |
+ The name of the DSP configuration that should be loaded for this
+ instance. Configuration blobs are sequences of register writes
+ generated from TI's PPC3 tool.
+ $ref: /schemas/types.yaml#/definitions/string
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ tas5805m: tas5805m@2c {
+ reg = <0x2c>;
+ compatible = "ti,tas5805m";
+
+ pvdd-supply = <&audiopwr>;
+ pdn-gpios = <&tlmm 160 0>;
+
+ ti,dsp-config-name = "mono_pbtl_48khz";
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/sound/ti,tlv320adc3xxx.yaml b/dts/upstream/Bindings/sound/ti,tlv320adc3xxx.yaml
index ede14ca..66b7665 100644
--- a/dts/upstream/Bindings/sound/ti,tlv320adc3xxx.yaml
+++ b/dts/upstream/Bindings/sound/ti,tlv320adc3xxx.yaml
@@ -58,8 +58,8 @@
description: |
Configuration for DMDIN/GPIO1 pin.
- When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
- ALSA control "GPIOx Output" to appear, as a switch control.
+ When ADC3XXX_GPIO_GPO is selected, the pin may be controlled via the
+ GPIO framework, as pin number 0 on the device.
ti,dmclk-gpio2:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -76,12 +76,32 @@
description: |
Configuration for DMCLK/GPIO2 pin.
- When ADC3XXX_GPIO_GPO is configured, this causes corresponding the
- ALSA control "GPIOx Output" to appear, as a switch control.
+ When ADC3XXX_GPIO_GPO is selected, the pin may be controlled via the
+ GPIO framework, as pin number 1 on the device.
Note that there is currently no support for reading the GPIO pins as
inputs.
+ ti,micbias1-gpo:
+ type: boolean
+ description: |
+ When set, the MICBIAS1 pin may be controlled via the GPIO framework,
+ as pin number 3 on the device.
+
+ In this mode, when the pin is activated, it will be set to the voltage
+ specified by the ti,micbias1-vg property. When deactivated, the pin will
+ float.
+
+ ti,micbias2-gpo:
+ type: boolean
+ description: |
+ When set, the MICBIAS2 pin may be controlled via the GPIO framework,
+ as pin number 4 on the device.
+
+ In this mode, when the pin is activated, it will be set to the voltage
+ specified by the ti,micbias2-vg property. When deactivated, the pin will
+ float.
+
ti,micbias1-vg:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
@@ -104,6 +124,10 @@
description: |
Mic bias voltage output on MICBIAS2 pin
+dependencies:
+ ti,micbias1-gpo: ['ti,micbias1-vg']
+ ti,micbias2-gpo: ['ti,micbias2-vg']
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/sound/ti,tlv320adcx140.yaml b/dts/upstream/Bindings/sound/ti,tlv320adcx140.yaml
new file mode 100644
index 0000000..876fa97
--- /dev/null
+++ b/dts/upstream/Bindings/sound/ti,tlv320adcx140.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# Copyright (C) 2019 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,tlv320adcx140.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
+
+maintainers:
+ - Andrew Davis <afd@ti.com>
+
+description: |
+ The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
+ PDM microphones recording), high-performance audio, analog-to-digital
+ converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
+ family supports line and microphone Inputs, and offers a programmable
+ microphone bias or supply voltage generation.
+
+ Specifications can be found at:
+ https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
+ https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
+ https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,tlv320adc3140
+ - ti,tlv320adc5140
+ - ti,tlv320adc6140
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
+
+ reset-gpios:
+ maxItems: 1
+ description: |
+ GPIO used for hardware reset.
+
+ areg-supply:
+ description: |
+ Regulator with AVDD at 3.3V. If not defined then the internal regulator
+ is enabled.
+
+ ti,mic-bias-source:
+ description: |
+ Indicates the source for MIC Bias.
+ 0 - Mic bias is set to VREF
+ 1 - Mic bias is set to VREF × 1.096
+ 6 - Mic bias is set to AVDD
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 6]
+
+ ti,vref-source:
+ description: |
+ Indicates the source for MIC Bias.
+ 0 - Set VREF to 2.75V
+ 1 - Set VREF to 2.5V
+ 2 - Set VREF to 1.375V
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ ti,pdm-edge-select:
+ description: |
+ Defines the PDMCLK sampling edge configuration for the PDM inputs. This
+ array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
+
+ 0 - (default) Odd channel is latched on the negative edge and even
+ channel is latched on the positive edge.
+ 1 - Odd channel is latched on the positive edge and even channel is
+ latched on the negative edge.
+
+ PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
+ PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
+ PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
+ PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
+
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 4
+ items:
+ maximum: 1
+ default: [0, 0, 0, 0]
+
+ ti,gpi-config:
+ description: |
+ Defines the configuration for the general purpose input pins (GPI).
+ The array is defined as <GPI1 GPI2 GPI3 GPI4>.
+
+ 0 - (default) disabled
+ 1 - GPIX is configured as a general-purpose input (GPI)
+ 2 - GPIX is configured as a master clock input (MCLK)
+ 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
+ 4 - GPIX is configured as a PDM data input for channel 1 and channel
+ (PDMDIN1)
+ 5 - GPIX is configured as a PDM data input for channel 3 and channel
+ (PDMDIN2)
+ 6 - GPIX is configured as a PDM data input for channel 5 and channel
+ (PDMDIN3)
+ 7 - GPIX is configured as a PDM data input for channel 7 and channel
+ (PDMDIN4)
+
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 4
+ items:
+ maximum: 7
+ default: [0, 0, 0, 0]
+
+ ti,gpio-config:
+ description: |
+ Defines the configuration and output drive for the General Purpose
+ Input and Output pin (GPIO1). Its value is a pair, the first value is for
+ the configuration type and the second value is for the output drive
+ type. The array is defined as <GPIO1_CFG GPIO1_DRV>
+
+ configuration for the GPIO pin can be one of the following:
+ 0 - disabled
+ 1 - GPIO1 is configured as a general-purpose output (GPO)
+ 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
+ 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
+ 4 - GPIO1 is configured as a PDM clock output (PDMCLK)
+ 8 - GPIO1 is configured as an input to control when MICBIAS turns on or
+ off (MICBIAS_EN)
+ 9 - GPIO1 is configured as a general-purpose input (GPI)
+ 10 - GPIO1 is configured as a master clock input (MCLK)
+ 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
+ 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
+ (PDMDIN1)
+ 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
+ (PDMDIN2)
+ 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
+ (PDMDIN3)
+ 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
+ (PDMDIN4)
+
+ output drive type for the GPIO pin can be one of the following:
+ 0 - Hi-Z output
+ 1 - Drive active low and active high
+ 2 - (default) Drive active low and weak high
+ 3 - Drive active low and Hi-Z
+ 4 - Drive weak low and active high
+ 5 - Drive Hi-Z and active high
+
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+ items:
+ maximum: 15
+ default: [2, 2]
+
+ ti,asi-tx-drive:
+ type: boolean
+ description: |
+ When set the device will set the Tx ASI output to a Hi-Z state for unused
+ data cycles. Default is to drive the output low on unused ASI cycles.
+
+patternProperties:
+ '^ti,gpo-config-[1-4]$':
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Defines the configuration and output driver for the general purpose
+ output pins (GPO). These values are pairs, the first value is for the
+ configuration type and the second value is for the output drive type.
+ The array is defined as <GPO_CFG GPO_DRV>
+
+ GPO output configuration can be one of the following:
+
+ 0 - (default) disabled
+ 1 - GPOX is configured as a general-purpose output (GPO)
+ 2 - GPOX is configured as a device interrupt output (IRQ)
+ 3 - GPOX is configured as a secondary ASI output (SDOUT2)
+ 4 - GPOX is configured as a PDM clock output (PDMCLK)
+
+ GPO output drive configuration for the GPO pins can be one of the following:
+
+ 0d - (default) Hi-Z output
+ 1d - Drive active low and active high
+ 2d - Drive active low and weak high
+ 3d - Drive active low and Hi-Z
+ 4d - Drive weak low and active high
+ 5d - Drive Hi-Z and active high
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ codec: codec@4c {
+ compatible = "ti,tlv320adc5140";
+ reg = <0x4c>;
+ ti,mic-bias-source = <6>;
+ ti,pdm-edge-select = <0 1 0 1>;
+ ti,gpi-config = <4 5 6 7>;
+ ti,gpio-config = <10 2>;
+ ti,gpo-config-1 = <0 0>;
+ ti,gpo-config-2 = <0 0>;
+ reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/tlv320adcx140.yaml b/dts/upstream/Bindings/sound/tlv320adcx140.yaml
deleted file mode 100644
index f3274bc..0000000
--- a/dts/upstream/Bindings/sound/tlv320adcx140.yaml
+++ /dev/null
@@ -1,209 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
-# Copyright (C) 2019 Texas Instruments Incorporated
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
-
-maintainers:
- - Andrew Davis <afd@ti.com>
-
-description: |
- The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
- PDM microphones recording), high-performance audio, analog-to-digital
- converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
- family supports line and microphone Inputs, and offers a programmable
- microphone bias or supply voltage generation.
-
- Specifications can be found at:
- https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
- https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
- https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
-
-properties:
- compatible:
- enum:
- - ti,tlv320adc3140
- - ti,tlv320adc5140
- - ti,tlv320adc6140
-
- reg:
- maxItems: 1
- description: |
- I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
-
- reset-gpios:
- maxItems: 1
- description: |
- GPIO used for hardware reset.
-
- areg-supply:
- description: |
- Regulator with AVDD at 3.3V. If not defined then the internal regulator
- is enabled.
-
- ti,mic-bias-source:
- description: |
- Indicates the source for MIC Bias.
- 0 - Mic bias is set to VREF
- 1 - Mic bias is set to VREF × 1.096
- 6 - Mic bias is set to AVDD
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 6]
-
- ti,vref-source:
- description: |
- Indicates the source for MIC Bias.
- 0 - Set VREF to 2.75V
- 1 - Set VREF to 2.5V
- 2 - Set VREF to 1.375V
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1, 2]
-
- ti,pdm-edge-select:
- description: |
- Defines the PDMCLK sampling edge configuration for the PDM inputs. This
- array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
-
- 0 - (default) Odd channel is latched on the negative edge and even
- channel is latched on the positive edge.
- 1 - Odd channel is latched on the positive edge and even channel is
- latched on the negative edge.
-
- PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
- PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
- PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
- PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
-
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
- maxItems: 4
- items:
- maximum: 1
- default: [0, 0, 0, 0]
-
- ti,gpi-config:
- description: |
- Defines the configuration for the general purpose input pins (GPI).
- The array is defined as <GPI1 GPI2 GPI3 GPI4>.
-
- 0 - (default) disabled
- 1 - GPIX is configured as a general-purpose input (GPI)
- 2 - GPIX is configured as a master clock input (MCLK)
- 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
- 4 - GPIX is configured as a PDM data input for channel 1 and channel
- (PDMDIN1)
- 5 - GPIX is configured as a PDM data input for channel 3 and channel
- (PDMDIN2)
- 6 - GPIX is configured as a PDM data input for channel 5 and channel
- (PDMDIN3)
- 7 - GPIX is configured as a PDM data input for channel 7 and channel
- (PDMDIN4)
-
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
- maxItems: 4
- items:
- maximum: 7
- default: [0, 0, 0, 0]
-
- ti,gpio-config:
- description: |
- Defines the configuration and output drive for the General Purpose
- Input and Output pin (GPIO1). Its value is a pair, the first value is for
- the configuration type and the second value is for the output drive
- type. The array is defined as <GPIO1_CFG GPIO1_DRV>
-
- configuration for the GPIO pin can be one of the following:
- 0 - disabled
- 1 - GPIO1 is configured as a general-purpose output (GPO)
- 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
- 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
- 4 - GPIO1 is configured as a PDM clock output (PDMCLK)
- 8 - GPIO1 is configured as an input to control when MICBIAS turns on or
- off (MICBIAS_EN)
- 9 - GPIO1 is configured as a general-purpose input (GPI)
- 10 - GPIO1 is configured as a master clock input (MCLK)
- 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
- 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
- (PDMDIN1)
- 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
- (PDMDIN2)
- 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
- (PDMDIN3)
- 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
- (PDMDIN4)
-
- output drive type for the GPIO pin can be one of the following:
- 0 - Hi-Z output
- 1 - Drive active low and active high
- 2 - (default) Drive active low and weak high
- 3 - Drive active low and Hi-Z
- 4 - Drive weak low and active high
- 5 - Drive Hi-Z and active high
-
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 2
- maxItems: 2
- items:
- maximum: 15
- default: [2, 2]
-
- ti,asi-tx-drive:
- type: boolean
- description: |
- When set the device will set the Tx ASI output to a Hi-Z state for unused
- data cycles. Default is to drive the output low on unused ASI cycles.
-
-patternProperties:
- '^ti,gpo-config-[1-4]$':
- $ref: /schemas/types.yaml#/definitions/uint32-array
- description: |
- Defines the configuration and output driver for the general purpose
- output pins (GPO). These values are pairs, the first value is for the
- configuration type and the second value is for the output drive type.
- The array is defined as <GPO_CFG GPO_DRV>
-
- GPO output configuration can be one of the following:
-
- 0 - (default) disabled
- 1 - GPOX is configured as a general-purpose output (GPO)
- 2 - GPOX is configured as a device interrupt output (IRQ)
- 3 - GPOX is configured as a secondary ASI output (SDOUT2)
- 4 - GPOX is configured as a PDM clock output (PDMCLK)
-
- GPO output drive configuration for the GPO pins can be one of the following:
-
- 0d - (default) Hi-Z output
- 1d - Drive active low and active high
- 2d - Drive active low and weak high
- 3d - Drive active low and Hi-Z
- 4d - Drive weak low and active high
- 5d - Drive Hi-Z and active high
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- codec: codec@4c {
- compatible = "ti,tlv320adc5140";
- reg = <0x4c>;
- ti,mic-bias-source = <6>;
- ti,pdm-edge-select = <0 1 0 1>;
- ti,gpi-config = <4 5 6 7>;
- ti,gpio-config = <10 2>;
- ti,gpo-config-1 = <0 0>;
- ti,gpo-config-2 = <0 0>;
- reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/wlf,wm8750.yaml b/dts/upstream/Bindings/sound/wlf,wm8750.yaml
new file mode 100644
index 0000000..96859e3
--- /dev/null
+++ b/dts/upstream/Bindings/sound/wlf,wm8750.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/wlf,wm8750.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WM8750 and WM8987 audio CODECs
+
+description: |
+ These devices support both I2C and SPI (configured with pin strapping
+ on the board).
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - wlf,wm8750
+ - wlf,wm8987
+
+ reg:
+ description:
+ The I2C address of the device for I2C, the chip select number for SPI
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1a {
+ compatible = "wlf,wm8750";
+ reg = <0x1a>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/wlf,wm8782.yaml b/dts/upstream/Bindings/sound/wlf,wm8782.yaml
new file mode 100644
index 0000000..d0bbdc9
--- /dev/null
+++ b/dts/upstream/Bindings/sound/wlf,wm8782.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/wlf,wm8782.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Wolfson Microelectromics WM8782 audio CODEC
+
+maintainers:
+ - patches@opensource.cirrus.com
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: wlf,wm8782
+
+ Vdda-supply:
+ description: Regulator for the analog power supply (2.7V - 5.5V)
+
+ Vdd-supply:
+ description: Regulator for the digital power supply (2.7V - 3.6V)
+
+ wlf,fsampen:
+ description: FSAMPEN pin value, 0 for low, 1 for high, 2 for disconnected.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - Vdda-supply
+ - Vdd-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ wm8782: codec {
+ compatible = "wlf,wm8782";
+ Vdda-supply = <&vdda_supply>;
+ Vdd-supply = <&vdd_supply>;
+ wlf,fsampen = <2>;
+ };
diff --git a/dts/upstream/Bindings/sound/wlf,wm8804.yaml b/dts/upstream/Bindings/sound/wlf,wm8804.yaml
new file mode 100644
index 0000000..3c06017
--- /dev/null
+++ b/dts/upstream/Bindings/sound/wlf,wm8804.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/wlf,wm8804.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WM8804 audio codec
+
+description: |
+ This device supports both I2C and SPI (configured with pin strapping on the
+ board).
+
+maintainers:
+ - patches@opensource.cirrus.com
+
+properties:
+ compatible:
+ const: wlf,wm8804
+
+ reg:
+ description:
+ The I2C address of the device for I2C, the chip select number for SPI.
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ PVDD-supply:
+ description: PLL core supply
+
+ DVDD-supply:
+ description: Digital core supply
+
+ wlf,reset-gpio:
+ description: A GPIO specifier for the GPIO controlling the reset pin.
+ maxItems: 1
+
+required:
+ - reg
+ - compatible
+ - PVDD-supply
+ - DVDD-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1a {
+ compatible = "wlf,wm8804";
+ reg = <0x1a>;
+ PVDD-supply = <&pvdd_reg>;
+ DVDD-supply = <&dvdd_reg>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/wm8750.yaml b/dts/upstream/Bindings/sound/wm8750.yaml
deleted file mode 100644
index 24246ac..0000000
--- a/dts/upstream/Bindings/sound/wm8750.yaml
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/wm8750.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: WM8750 and WM8987 audio CODECs
-
-description: |
- These devices support both I2C and SPI (configured with pin strapping
- on the board).
-
-maintainers:
- - Mark Brown <broonie@kernel.org>
-
-properties:
- compatible:
- enum:
- - wlf,wm8750
- - wlf,wm8987
-
- reg:
- description:
- The I2C address of the device for I2C, the chip select number for SPI
- maxItems: 1
-
-additionalProperties: false
-
-required:
- - reg
-
-examples:
- - |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- codec@1a {
- compatible = "wlf,wm8750";
- reg = <0x1a>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/wm8782.txt b/dts/upstream/Bindings/sound/wm8782.txt
deleted file mode 100644
index 1a28f32..0000000
--- a/dts/upstream/Bindings/sound/wm8782.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-WM8782 stereo ADC
-
-This device does not have any control interface or reset pins.
-
-Required properties:
-
- - compatible : "wlf,wm8782"
- - Vdda-supply : phandle to a regulator for the analog power supply (2.7V - 5.5V)
- - Vdd-supply : phandle to a regulator for the digital power supply (2.7V - 3.6V)
-
-Optional properties:
-
- - wlf,fsampen:
- FSAMPEN pin value, 0 for low, 1 for high, 2 for disconnected.
- Defaults to 0 if left unspecified.
-
-Example:
-
-wm8782: stereo-adc {
- compatible = "wlf,wm8782";
- Vdda-supply = <&vdda_supply>;
- Vdd-supply = <&vdd_supply>;
- wlf,fsampen = <2>; /* 192KHz */
-};
diff --git a/dts/upstream/Bindings/sound/wm8804.txt b/dts/upstream/Bindings/sound/wm8804.txt
deleted file mode 100644
index 2c1641c..0000000
--- a/dts/upstream/Bindings/sound/wm8804.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-WM8804 audio CODEC
-
-This device supports both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
- - compatible : "wlf,wm8804"
-
- - reg : the I2C address of the device for I2C, the chip select
- number for SPI.
-
- - PVDD-supply, DVDD-supply : Power supplies for the device, as covered
- in Documentation/devicetree/bindings/regulator/regulator.txt
-
-Optional properties:
-
- - wlf,reset-gpio: A GPIO specifier for the GPIO controlling the reset pin
-
-Example:
-
-wm8804: codec@1a {
- compatible = "wlf,wm8804";
- reg = <0x1a>;
-};
diff --git a/dts/upstream/Bindings/sound/zl38060.yaml b/dts/upstream/Bindings/sound/zl38060.yaml
deleted file mode 100644
index 8bd201e..0000000
--- a/dts/upstream/Bindings/sound/zl38060.yaml
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/sound/zl38060.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ZL38060 Connected Home Audio Processor from Microsemi.
-
-description: |
- The ZL38060 is a "Connected Home Audio Processor" from Microsemi,
- which consists of a Digital Signal Processor (DSP), several Digital
- Audio Interfaces (DAIs), analog outputs, and a block of 14 GPIOs.
-
-maintainers:
- - Jaroslav Kysela <perex@perex.cz>
- - Takashi Iwai <tiwai@suse.com>
-
-allOf:
- - $ref: dai-common.yaml#
-
-properties:
- compatible:
- const: mscc,zl38060
-
- reg:
- description:
- SPI device address.
- maxItems: 1
-
- spi-max-frequency:
- maximum: 24000000
-
- reset-gpios:
- description:
- A GPIO line handling reset of the chip. As the line is active low,
- it should be marked GPIO_ACTIVE_LOW (see ../gpio/gpio.txt)
- maxItems: 1
-
- '#gpio-cells':
- const: 2
-
- gpio-controller: true
-
- '#sound-dai-cells':
- const: 0
-
-required:
- - compatible
- - reg
- - '#gpio-cells'
- - gpio-controller
- - '#sound-dai-cells'
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
-
- codec: zl38060@0 {
- gpio-controller;
- #gpio-cells = <2>;
- #sound-dai-cells = <0>;
- compatible = "mscc,zl38060";
- reg = <0>;
- spi-max-frequency = <12000000>;
- reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- };
- };
diff --git a/dts/upstream/Bindings/spi/amlogic,a1-spifc.yaml b/dts/upstream/Bindings/spi/amlogic,a1-spifc.yaml
index ea47d30..043879b 100644
--- a/dts/upstream/Bindings/spi/amlogic,a1-spifc.yaml
+++ b/dts/upstream/Bindings/spi/amlogic,a1-spifc.yaml
@@ -23,6 +23,9 @@
clocks:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/spi/atmel,at91rm9200-spi.yaml b/dts/upstream/Bindings/spi/atmel,at91rm9200-spi.yaml
index 32e7c14..d297729 100644
--- a/dts/upstream/Bindings/spi/atmel,at91rm9200-spi.yaml
+++ b/dts/upstream/Bindings/spi/atmel,at91rm9200-spi.yaml
@@ -18,10 +18,10 @@
oneOf:
- const: atmel,at91rm9200-spi
- items:
- - const: microchip,sam9x60-spi
- - const: atmel,at91rm9200-spi
- - items:
- - const: microchip,sam9x7-spi
+ - enum:
+ - microchip,sam9x60-spi
+ - microchip,sam9x7-spi
+ - microchip,sama7d65-spi
- const: atmel,at91rm9200-spi
reg:
diff --git a/dts/upstream/Bindings/spi/brcm,bcm2835-spi.txt b/dts/upstream/Bindings/spi/brcm,bcm2835-spi.txt
deleted file mode 100644
index 3d55dd6..0000000
--- a/dts/upstream/Bindings/spi/brcm,bcm2835-spi.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Broadcom BCM2835 SPI0 controller
-
-The BCM2835 contains two forms of SPI master controller, one known simply as
-SPI0, and the other known as the "Universal SPI Master"; part of the
-auxiliary block. This binding applies to the SPI0 controller.
-
-Required properties:
-- compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or
- "brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211.
-- reg: Should contain register location and length.
-- interrupts: Should contain interrupt.
-- clocks: The clock feeding the SPI controller.
-
-Example:
-
-spi@20204000 {
- compatible = "brcm,bcm2835-spi";
- reg = <0x7e204000 0x1000>;
- interrupts = <2 22>;
- clocks = <&clk_spi>;
- #address-cells = <1>;
- #size-cells = <0>;
-};
diff --git a/dts/upstream/Bindings/spi/brcm,bcm2835-spi.yaml b/dts/upstream/Bindings/spi/brcm,bcm2835-spi.yaml
new file mode 100644
index 0000000..94da687
--- /dev/null
+++ b/dts/upstream/Bindings/spi/brcm,bcm2835-spi.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm2835-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 SPI0 controller
+
+maintainers:
+ - Florian Fainelli <florian.fainelli@broadcom.com>
+ - Kanak Shilledar <kanakshilledar111@protonmail.com>
+ - Stefan Wahren <wahrenst@gmx.net>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-spi
+ - brcm,bcm2711-spi
+ - brcm,bcm7211-spi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@20204000 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204000 0x1000>;
+ interrupts = <2 22>;
+ clocks = <&clk_spi>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/spi/fsl,dspi-peripheral-props.yaml b/dts/upstream/Bindings/spi/fsl,dspi-peripheral-props.yaml
new file mode 100644
index 0000000..9b62b75
--- /dev/null
+++ b/dts/upstream/Bindings/spi/fsl,dspi-peripheral-props.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,dspi-peripheral-props.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Peripheral-specific properties for Freescale DSPI controller
+
+maintainers:
+ - Vladimir Oltean <olteanv@gmail.com>
+
+description:
+ See spi-peripheral-props.yaml for more info.
+
+properties:
+ fsl,spi-cs-sck-delay:
+ deprecated: true
+ description:
+ Delay in nanoseconds between activating chip select and the start of
+ clock signal, at the start of a transfer.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ fsl,spi-sck-cs-delay:
+ deprecated: true
+ description:
+ Delay in nanoseconds between stopping the clock signal and
+ deactivating chip select, at the end of a transfer.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/spi/fsl,dspi.yaml b/dts/upstream/Bindings/spi/fsl,dspi.yaml
new file mode 100644
index 0000000..7ca8fce
--- /dev/null
+++ b/dts/upstream/Bindings/spi/fsl,dspi.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Freescale DSPI controller
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,vf610-dspi
+ - fsl,ls1021a-v1.0-dspi
+ - fsl,ls1012a-dspi
+ - fsl,ls1028a-dspi
+ - fsl,ls1043a-dspi
+ - fsl,ls1046a-dspi
+ - fsl,ls1088a-dspi
+ - fsl,ls2080a-dspi
+ - fsl,ls2085a-dspi
+ - fsl,lx2160a-dspi
+ - items:
+ - enum:
+ - fsl,ls1012a-dspi
+ - fsl,ls1028a-dspi
+ - fsl,ls1043a-dspi
+ - fsl,ls1046a-dspi
+ - fsl,ls1088a-dspi
+ - const: fsl,ls1021a-v1.0-dspi
+ - items:
+ - const: fsl,ls2080a-dspi
+ - const: fsl,ls2085a-dspi
+ - items:
+ - const: fsl,lx2160a-dspi
+ - const: fsl,ls2085a-dspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: dspi
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for TX
+ - description: DMA controller phandle and request line for RX
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ spi-num-chipselects:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The number of the chip native chipselect signals.
+ cs-gpios don't count against this number.
+
+ big-endian: true
+
+ bus-num:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: SoC-specific identifier for the SPI controller.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - spi-num-chipselects
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/vf610-clock.h>
+
+ spi@4002c000 {
+ compatible = "fsl,vf610-dspi";
+ reg = <0x4002c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_DSPI0>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dspi0_1>;
+ big-endian;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ spi-cs-setup-delay-ns = <100>;
+ spi-cs-hold-delay-ns = <50>;
+ };
+ };
diff --git a/dts/upstream/Bindings/spi/ibm,spi-fsi.yaml b/dts/upstream/Bindings/spi/ibm,spi-fsi.yaml
new file mode 100644
index 0000000..d7fec4c
--- /dev/null
+++ b/dts/upstream/Bindings/spi/ibm,spi-fsi.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/ibm,spi-fsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM FSI-attached SPI Controller
+
+maintainers:
+ - Eddie James <eajames@linux.ibm.com>
+
+description:
+ A SPI controller found on IBM Power processors, accessed over FSI from a
+ service processor. This node will always be a child node of an ibm,fsi2spi
+ node.
+
+properties:
+ compatible:
+ enum:
+ - ibm,spi-fsi
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi@0 {
+ compatible = "ibm,spi-fsi";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "atmel,at25";
+ reg = <0>;
+ size = <0x80000>;
+ address-width = <24>;
+ pagesize = <256>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/spi/marvell,mmp2-ssp.yaml b/dts/upstream/Bindings/spi/marvell,mmp2-ssp.yaml
index 5f4f6b5..0a1bada 100644
--- a/dts/upstream/Bindings/spi/marvell,mmp2-ssp.yaml
+++ b/dts/upstream/Bindings/spi/marvell,mmp2-ssp.yaml
@@ -10,12 +10,17 @@
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
-allOf:
- - $ref: spi-controller.yaml#
-
properties:
compatible:
- const: marvell,mmp2-ssp
+ enum:
+ - marvell,mmp2-ssp
+ - mrvl,ce4100-ssp
+ - mvrl,pxa168-ssp
+ - mrvl,pxa25x-ssp
+ - mvrl,pxa25x-nssp
+ - mrvl,pxa27x-ssp
+ - mrvl,pxa3xx-ssp
+ - mrvl,pxa910-ssp
interrupts:
maxItems: 1
@@ -26,6 +31,16 @@
clocks:
maxItems: 1
+ dmas:
+ items:
+ - description: Receive DMA
+ - description: Transmit DMA
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
ready-gpios:
description: |
GPIO used to signal a SPI master that the FIFO is filled and we're
@@ -41,6 +56,18 @@
dependencies:
ready-gpios: [ spi-slave ]
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: marvell,mmp2-ssp
+ then:
+ properties:
+ dmas: false
+ dma-names: false
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml b/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml
index 74a817c..ffa8d1b 100644
--- a/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml
+++ b/dts/upstream/Bindings/spi/microchip,mpfs-spi.yaml
@@ -13,9 +13,6 @@
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
-allOf:
- - $ref: spi-controller.yaml#
-
properties:
compatible:
oneOf:
@@ -43,6 +40,32 @@
- interrupts
- clocks
+allOf:
+ - $ref: spi-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-spi
+ then:
+ properties:
+ num-cs:
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mpfs-spi
+ not:
+ required:
+ - cs-gpios
+ then:
+ properties:
+ num-cs:
+ maximum: 1
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
index fde3776..bccd00a 100644
--- a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
+++ b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
@@ -88,6 +88,10 @@
- renesas,r9a06g032-spi # RZ/N1D
- renesas,r9a06g033-spi # RZ/N1S
- const: renesas,rzn1-spi # RZ/N1
+ - description: T-HEAD TH1520 SoC SPI Controller
+ items:
+ - const: thead,th1520-spi
+ - const: snps,dw-apb-ssi
reg:
minItems: 1
diff --git a/dts/upstream/Bindings/spi/spi-cadence.yaml b/dts/upstream/Bindings/spi/spi-cadence.yaml
index d4b61b0..8de96ab 100644
--- a/dts/upstream/Bindings/spi/spi-cadence.yaml
+++ b/dts/upstream/Bindings/spi/spi-cadence.yaml
@@ -55,6 +55,13 @@
label:
description: Descriptive name of the SPI controller.
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: spi
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/spi/spi-fsl-dspi.txt b/dts/upstream/Bindings/spi/spi-fsl-dspi.txt
deleted file mode 100644
index 30a79da..0000000
--- a/dts/upstream/Bindings/spi/spi-fsl-dspi.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-ARM Freescale DSPI controller
-
-Required properties:
-- compatible : must be one of:
- "fsl,vf610-dspi",
- "fsl,ls1021a-v1.0-dspi",
- "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
- "fsl,ls1028a-dspi",
- "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
- "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
- "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
- "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
- "fsl,ls2085a-dspi",
- "fsl,lx2160a-dspi",
-- reg : Offset and length of the register set for the device
-- interrupts : Should contain SPI controller interrupt
-- clocks: from common clock binding: handle to dspi clock.
-- clock-names: from common clock binding: Shall be "dspi".
-- pinctrl-0: pin control group to be used for this controller.
-- pinctrl-names: must contain a "default" entry.
-- spi-num-chipselects : the number of the chipselect signals.
-
-Optional property:
-- big-endian: If present the dspi device's registers are implemented
- in big endian mode.
-- bus-num : the slave chip chipselect signal number.
-
-Optional SPI slave node properties:
-- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
- select and the start of clock signal, at the start of a transfer.
-- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
- signal and deactivating chip select, at the end of a transfer.
-
-Example:
-
-dspi0@4002c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,vf610-dspi";
- reg = <0x4002c000 0x1000>;
- interrupts = <0 67 0x04>;
- clocks = <&clks VF610_CLK_DSPI0>;
- clock-names = "dspi";
- spi-num-chipselects = <5>;
- bus-num = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dspi0_1>;
- big-endian;
-
- sflash: at26df081a@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "atmel,at26df081a";
- spi-max-frequency = <16000000>;
- spi-cpol;
- spi-cpha;
- reg = <0>;
- linux,modalias = "m25p80";
- modal = "at26df081a";
- fsl,spi-cs-sck-delay = <100>;
- fsl,spi-sck-cs-delay = <50>;
- };
-};
-
-
diff --git a/dts/upstream/Bindings/spi/spi-fsl-lpspi.yaml b/dts/upstream/Bindings/spi/spi-fsl-lpspi.yaml
index 2ff1742..ed1d4aa 100644
--- a/dts/upstream/Bindings/spi/spi-fsl-lpspi.yaml
+++ b/dts/upstream/Bindings/spi/spi-fsl-lpspi.yaml
@@ -7,7 +7,9 @@
title: Freescale Low Power SPI (LPSPI) for i.MX
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
diff --git a/dts/upstream/Bindings/spi/spi-peripheral-props.yaml b/dts/upstream/Bindings/spi/spi-peripheral-props.yaml
index 15938f8..0bb443b 100644
--- a/dts/upstream/Bindings/spi/spi-peripheral-props.yaml
+++ b/dts/upstream/Bindings/spi/spi-peripheral-props.yaml
@@ -122,6 +122,7 @@
allOf:
- $ref: arm,pl022-peripheral-props.yaml#
- $ref: cdns,qspi-nor-peripheral-props.yaml#
+ - $ref: fsl,dspi-peripheral-props.yaml#
- $ref: samsung,spi-peripheral-props.yaml#
- $ref: nvidia,tegra210-quad-peripheral-props.yaml#
diff --git a/dts/upstream/Bindings/spi/st,stm32-spi.yaml b/dts/upstream/Bindings/spi/st,stm32-spi.yaml
index a55c863..76e43c0 100644
--- a/dts/upstream/Bindings/spi/st,stm32-spi.yaml
+++ b/dts/upstream/Bindings/spi/st,stm32-spi.yaml
@@ -42,7 +42,7 @@
dmas:
description: |
DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
- the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml.
+ the STM32 DMA controllers bindings Documentation/devicetree/bindings/dma/stm32/*.yaml.
items:
- description: rx DMA channel
- description: tx DMA channel
diff --git a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
index cf07b8f..d932270 100644
--- a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
+++ b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
@@ -56,6 +56,9 @@
ranges: true
patternProperties:
+ "^regulators@[0-9a-f]+$":
+ $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
+
"^sram@[a-f0-9]+":
$ref: /schemas/sram/sram.yaml#
unevaluatedProperties: false
@@ -130,3 +133,28 @@
};
};
};
+
+ - |
+ syscon@3000000 {
+ compatible = "allwinner,sun20i-d1-system-control";
+ reg = <0x3000000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ regulators@3000150 {
+ compatible = "allwinner,sun20i-d1-system-ldos";
+ reg = <0x3000150 0x4>;
+
+ reg_ldoa: ldoa {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_ldob: ldob {
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/sram/qcom,imem.yaml b/dts/upstream/Bindings/sram/qcom,imem.yaml
index 8025a85..faef3d6 100644
--- a/dts/upstream/Bindings/sram/qcom,imem.yaml
+++ b/dts/upstream/Bindings/sram/qcom,imem.yaml
@@ -22,6 +22,7 @@
- qcom,msm8974-imem
- qcom,qcs404-imem
- qcom,qdu1000-imem
+ - qcom,sa8775p-imem
- qcom,sc7180-imem
- qcom,sc7280-imem
- qcom,sdm630-imem
diff --git a/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
index 6b3aea6..dad8de9 100644
--- a/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+++ b/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
@@ -10,6 +10,8 @@
- Vasily Khoruzhick <anarsoul@gmail.com>
- Yangtao Li <tiny.windzz@gmail.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -55,7 +57,6 @@
maxItems: 1
description: phandle to device controlling temperate offset SYS_CFG register
- # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details
"#thermal-sensor-cells":
enum:
- 0
@@ -135,9 +136,8 @@
- compatible
- reg
- interrupts
- - '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/amlogic,thermal.yaml b/dts/upstream/Bindings/thermal/amlogic,thermal.yaml
index 01fccdf..725303e 100644
--- a/dts/upstream/Bindings/thermal/amlogic,thermal.yaml
+++ b/dts/upstream/Bindings/thermal/amlogic,thermal.yaml
@@ -11,6 +11,8 @@
description: Binding for Amlogic Thermal
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
oneOf:
@@ -44,17 +46,17 @@
- clocks
- amlogic,ao-secure
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- cpu_temp: temperature-sensor@ff634800 {
- compatible = "amlogic,g12a-cpu-thermal",
- "amlogic,g12a-thermal";
- reg = <0xff634800 0x50>;
- interrupts = <0x0 0x24 0x0>;
- clocks = <&clk 164>;
- #thermal-sensor-cells = <0>;
- amlogic,ao-secure = <&sec_AO>;
- };
+ temperature-sensor@ff634800 {
+ compatible = "amlogic,g12a-cpu-thermal",
+ "amlogic,g12a-thermal";
+ reg = <0xff634800 0x50>;
+ interrupts = <0x0 0x24 0x0>;
+ clocks = <&clk 164>;
+ #thermal-sensor-cells = <0>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
...
diff --git a/dts/upstream/Bindings/thermal/brcm,avs-ro-thermal.yaml b/dts/upstream/Bindings/thermal/brcm,avs-ro-thermal.yaml
index 89a2c32..29a9844 100644
--- a/dts/upstream/Bindings/thermal/brcm,avs-ro-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/brcm,avs-ro-thermal.yaml
@@ -19,30 +19,30 @@
Refer to the bindings described in
Documentation/devicetree/bindings/mfd/syscon.yaml
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: brcm,bcm2711-thermal
- # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details
"#thermal-sensor-cells":
const: 0
required:
- compatible
- - '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- avs-monitor@7d5d2000 {
- compatible = "brcm,bcm2711-avs-monitor",
- "syscon", "simple-mfd";
- reg = <0x7d5d2000 0xf00>;
+ avs-monitor@7d5d2000 {
+ compatible = "brcm,bcm2711-avs-monitor",
+ "syscon", "simple-mfd";
+ reg = <0x7d5d2000 0xf00>;
- thermal: thermal {
- compatible = "brcm,bcm2711-thermal";
- #thermal-sensor-cells = <0>;
- };
+ thermal: thermal {
+ compatible = "brcm,bcm2711-thermal";
+ #thermal-sensor-cells = <0>;
};
+ };
...
diff --git a/dts/upstream/Bindings/thermal/brcm,avs-tmon.yaml b/dts/upstream/Bindings/thermal/brcm,avs-tmon.yaml
index 267a0f4..081486b 100644
--- a/dts/upstream/Bindings/thermal/brcm,avs-tmon.yaml
+++ b/dts/upstream/Bindings/thermal/brcm,avs-tmon.yaml
@@ -42,15 +42,14 @@
required:
- compatible
- reg
- - "#thermal-sensor-cells"
examples:
- |
- thermal@f04d1500 {
- compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
- reg = <0xf04d1500 0x28>;
- interrupts = <0x6>;
- interrupt-names = "tmon";
- interrupt-parent = <&avs_host_l2_intc>;
- #thermal-sensor-cells = <0>;
- };
+ thermal@f04d1500 {
+ compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
+ reg = <0xf04d1500 0x28>;
+ interrupts = <0x6>;
+ interrupt-names = "tmon";
+ interrupt-parent = <&avs_host_l2_intc>;
+ #thermal-sensor-cells = <0>;
+ };
diff --git a/dts/upstream/Bindings/thermal/brcm,bcm2835-thermal.yaml b/dts/upstream/Bindings/thermal/brcm,bcm2835-thermal.yaml
index 2b6026d..ddf0f20 100644
--- a/dts/upstream/Bindings/thermal/brcm,bcm2835-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/brcm,bcm2835-thermal.yaml
@@ -34,7 +34,6 @@
- compatible
- reg
- clocks
- - '#thermal-sensor-cells'
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/fsl,scu-thermal.yaml b/dts/upstream/Bindings/thermal/fsl,scu-thermal.yaml
index e02d04d..ceef318 100644
--- a/dts/upstream/Bindings/thermal/fsl,scu-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/fsl,scu-thermal.yaml
@@ -28,7 +28,6 @@
required:
- compatible
- - '#thermal-sensor-cells'
additionalProperties: false
diff --git a/dts/upstream/Bindings/thermal/generic-adc-thermal.yaml b/dts/upstream/Bindings/thermal/generic-adc-thermal.yaml
index f1fc3b0..12e6418 100644
--- a/dts/upstream/Bindings/thermal/generic-adc-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/generic-adc-thermal.yaml
@@ -15,6 +15,8 @@
sensor resistor. The voltage read across the sensor is mapped to
temperature using voltage-temperature lookup table.
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: generic-adc-thermal
@@ -44,11 +46,10 @@
required:
- compatible
- - '#thermal-sensor-cells'
- io-channels
- io-channel-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/hisilicon,tsensor.yaml b/dts/upstream/Bindings/thermal/hisilicon,tsensor.yaml
new file mode 100644
index 0000000..11aca2b
--- /dev/null
+++ b/dts/upstream/Bindings/thermal/hisilicon,tsensor.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/hisilicon,tsensor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Temperature Sensor on HiSilicon SoCs
+
+maintainers:
+ - Abdulrasaq Lawani <abdulrasaqolawani@gmail.com>
+
+allOf:
+ - $ref: thermal-sensor.yaml
+
+properties:
+ compatible:
+ enum:
+ - hisilicon,tsensor
+ - hisilicon,hi3660-tsensor
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: thermal_clk
+
+ interrupts:
+ maxItems: 1
+
+ '#thermal-sensor-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#thermal-sensor-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/hi6220-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ temperature-sensor@f7030700 {
+ compatible = "hisilicon,tsensor";
+ reg = <0xf7030700 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_ctrl HI6220_TSENSOR_CLK>;
+ clock-names = "thermal_clk";
+ #thermal-sensor-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/thermal/hisilicon-thermal.txt b/dts/upstream/Bindings/thermal/hisilicon-thermal.txt
deleted file mode 100644
index 4b19d80..0000000
--- a/dts/upstream/Bindings/thermal/hisilicon-thermal.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Temperature Sensor on hisilicon SoCs
-
-** Required properties :
-
-- compatible: "hisilicon,tsensor".
-- reg: physical base address of thermal sensor and length of memory mapped
- region.
-- interrupt: The interrupt number to the cpu. Defines the interrupt used
- by /SOCTHERM/tsensor.
-- clock-names: Input clock name, should be 'thermal_clk'.
-- clocks: phandles for clock specified in "clock-names" property.
-- #thermal-sensor-cells: Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
-
-Example :
-
-for Hi6220:
- tsensor: tsensor@0,f7030700 {
- compatible = "hisilicon,tsensor";
- reg = <0x0 0xf7030700 0x0 0x1000>;
- interrupts = <0 7 0x4>;
- clocks = <&sys_ctrl HI6220_TSENSOR_CLK>;
- clock-names = "thermal_clk";
- #thermal-sensor-cells = <1>;
- }
-
-for Hi3660:
- tsensor: tsensor@fff30000 {
- compatible = "hisilicon,hi3660-tsensor";
- reg = <0x0 0xfff30000 0x0 0x1000>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- #thermal-sensor-cells = <1>;
- };
diff --git a/dts/upstream/Bindings/thermal/imx-thermal.yaml b/dts/upstream/Bindings/thermal/imx-thermal.yaml
index 808d987..3375605 100644
--- a/dts/upstream/Bindings/thermal/imx-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/imx-thermal.yaml
@@ -8,7 +8,6 @@
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- - Anson Huang <Anson.Huang@nxp.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/thermal/imx8mm-thermal.yaml b/dts/upstream/Bindings/thermal/imx8mm-thermal.yaml
index d2c1e45..bef0e95 100644
--- a/dts/upstream/Bindings/thermal/imx8mm-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/imx8mm-thermal.yaml
@@ -7,7 +7,9 @@
title: NXP i.MX8M Mini Thermal
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
description: |
i.MX8MM has TMU IP to allow temperature measurement, there are
@@ -16,6 +18,8 @@
for i.MX8MM which has ONLY 1 sensor, v2 is for i.MX8MP which has
2 sensors.
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
oneOf:
@@ -51,9 +55,8 @@
- compatible
- reg
- clocks
- - '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml b/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
index ca81c8a..79e691b 100644
--- a/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
@@ -38,7 +38,6 @@
- compatible
- reg
- interrupts
- - '#thermal-sensor-cells'
if:
properties:
diff --git a/dts/upstream/Bindings/thermal/mediatek,lvts-thermal.yaml b/dts/upstream/Bindings/thermal/mediatek,lvts-thermal.yaml
index 331cf4e..0259cd3 100644
--- a/dts/upstream/Bindings/thermal/mediatek,lvts-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/mediatek,lvts-thermal.yaml
@@ -99,7 +99,6 @@
- resets
- nvmem-cells
- nvmem-cell-names
- - "#thermal-sensor-cells"
additionalProperties: false
diff --git a/dts/upstream/Bindings/thermal/nvidia,tegra124-soctherm.yaml b/dts/upstream/Bindings/thermal/nvidia,tegra124-soctherm.yaml
index b0237d2..19bb1f3 100644
--- a/dts/upstream/Bindings/thermal/nvidia,tegra124-soctherm.yaml
+++ b/dts/upstream/Bindings/thermal/nvidia,tegra124-soctherm.yaml
@@ -197,7 +197,6 @@
- clock-names
- resets
- reset-names
- - "#thermal-sensor-cells"
allOf:
- $ref: thermal-sensor.yaml
diff --git a/dts/upstream/Bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/dts/upstream/Bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
index c91fd07..978b9e6 100644
--- a/dts/upstream/Bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml
@@ -20,11 +20,7 @@
node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
BPMP binding.
- This node represents a thermal sensor. See
-
- Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
-
- for details of the core thermal binding.
+$ref: thermal-sensor.yaml#
properties:
compatible:
@@ -33,10 +29,6 @@
- nvidia,tegra194-bpmp-thermal
'#thermal-sensor-cells':
- $ref: /schemas/types.yaml#/definitions/uint32
- description: Number of cells needed in the phandle specifier to
- identify a given sensor. Must be 1 and the single cell specifies
- the sensor index.
const: 1
-additionalProperties: false
+unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/thermal/nvidia,tegra30-tsensor.yaml b/dts/upstream/Bindings/thermal/nvidia,tegra30-tsensor.yaml
index a35da25..63a29a1 100644
--- a/dts/upstream/Bindings/thermal/nvidia,tegra30-tsensor.yaml
+++ b/dts/upstream/Bindings/thermal/nvidia,tegra30-tsensor.yaml
@@ -27,6 +27,8 @@
TSENSOR has two channels which monitor two different spots of the SoC.
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: nvidia,tegra30-tsensor
@@ -46,19 +48,14 @@
"#thermal-sensor-cells":
const: 1
- assigned-clock-parents: true
- assigned-clock-rates: true
- assigned-clocks: true
-
required:
- compatible
- reg
- clocks
- resets
- interrupts
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/qcom,spmi-temp-alarm.yaml b/dts/upstream/Bindings/thermal/qcom,spmi-temp-alarm.yaml
index 5f08b6e..30b2215 100644
--- a/dts/upstream/Bindings/thermal/qcom,spmi-temp-alarm.yaml
+++ b/dts/upstream/Bindings/thermal/qcom,spmi-temp-alarm.yaml
@@ -42,7 +42,6 @@
- compatible
- reg
- interrupts
- - '#thermal-sensor-cells'
additionalProperties: false
diff --git a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
index 7541e27..bfad813 100644
--- a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
@@ -8,6 +8,8 @@
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: qcom,spmi-adc-tm-hc
@@ -20,9 +22,6 @@
"#thermal-sensor-cells":
const: 1
- description:
- Number of cells required to uniquely identify the thermal sensors. Since
- we have multiple sensors this is set to 1
"#address-cells":
const: 1
@@ -106,9 +105,8 @@
- interrupts
- "#address-cells"
- "#size-cells"
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
index d9d2657..4470a59 100644
--- a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -8,6 +8,8 @@
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -23,9 +25,6 @@
"#thermal-sensor-cells":
const: 1
- description:
- Number of cells required to uniquely identify the thermal sensors. Since
- we have multiple sensors this is set to 1
"#address-cells":
const: 1
@@ -159,9 +158,8 @@
- interrupts
- "#address-cells"
- "#size-cells"
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/qcom-tsens.yaml b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
index 99d9c52..72048c5 100644
--- a/dts/upstream/Bindings/thermal/qcom-tsens.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
@@ -67,6 +67,7 @@
- qcom,sm8450-tsens
- qcom,sm8550-tsens
- qcom,sm8650-tsens
+ - qcom,x1e80100-tsens
- const: qcom,tsens-v2
- description: v2 of TSENS with combined interrupt
@@ -217,18 +218,16 @@
"#thermal-sensor-cells":
const: 1
- description:
- Number of cells required to uniquely identify the thermal sensors. Since
- we have multiple sensors this is set to 1
required:
- compatible
- interrupts
- interrupt-names
- - "#thermal-sensor-cells"
- "#qcom,sensors"
allOf:
+ - $ref: thermal-sensor.yaml#
+
- if:
properties:
compatible:
@@ -292,27 +291,21 @@
required:
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
- // Example msm9860 based SoC (ipq8064):
- gcc: clock-controller {
+ thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
- /* ... */
-
- tsens: thermal-sensor {
- compatible = "qcom,ipq8064-tsens";
-
- nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
- nvmem-cell-names = "calib", "calib_backup";
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
- #qcom,sensors = <11>;
- #thermal-sensor-cells = <1>;
- };
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
};
- |
@@ -349,66 +342,66 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (legacy: for pre v1 IP):
tsens1: thermal-sensor@4a9000 {
- compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
- reg = <0x4a9000 0x1000>, /* TM */
- <0x4a8000 0x1000>; /* SROT */
+ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
- nvmem-cell-names = "calib", "calib_sel";
+ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
+ nvmem-cell-names = "calib", "calib_sel";
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
- #qcom,sensors = <5>;
- #thermal-sensor-cells = <1>;
+ #qcom,sensors = <5>;
+ #thermal-sensor-cells = <1>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 2 (for any platform containing v1 of the TSENS IP):
tsens2: thermal-sensor@4a9000 {
- compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
- reg = <0x004a9000 0x1000>, /* TM */
- <0x004a8000 0x1000>; /* SROT */
+ compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
+ reg = <0x004a9000 0x1000>, /* TM */
+ <0x004a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_caldata>;
- nvmem-cell-names = "calib";
+ nvmem-cells = <&tsens_caldata>;
+ nvmem-cell-names = "calib";
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow";
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
- #qcom,sensors = <10>;
- #thermal-sensor-cells = <1>;
+ #qcom,sensors = <10>;
+ #thermal-sensor-cells = <1>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 3 (for any platform containing v2 of the TSENS IP):
tsens3: thermal-sensor@c263000 {
- compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
- reg = <0xc263000 0x1ff>,
- <0xc222000 0x1ff>;
+ compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
+ reg = <0xc263000 0x1ff>,
+ <0xc222000 0x1ff>;
- interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "uplow", "critical";
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
- #qcom,sensors = <13>;
- #thermal-sensor-cells = <1>;
+ #qcom,sensors = <13>;
+ #thermal-sensor-cells = <1>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 4 (for any IPQ8074 based SoC-s):
tsens4: thermal-sensor@4a9000 {
- compatible = "qcom,ipq8074-tsens";
- reg = <0x4a9000 0x1000>,
- <0x4a8000 0x1000>;
+ compatible = "qcom,ipq8074-tsens";
+ reg = <0x4a9000 0x1000>,
+ <0x4a8000 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "combined";
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
- #qcom,sensors = <16>;
- #thermal-sensor-cells = <1>;
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
};
...
diff --git a/dts/upstream/Bindings/thermal/qoriq-thermal.yaml b/dts/upstream/Bindings/thermal/qoriq-thermal.yaml
index d155d67..aa756da 100644
--- a/dts/upstream/Bindings/thermal/qoriq-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/qoriq-thermal.yaml
@@ -7,7 +7,11 @@
title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
+
+$ref: thermal-sensor.yaml#
properties:
compatible:
@@ -68,9 +72,8 @@
- interrupts
- fsl,tmu-range
- fsl,tmu-calibration
- - '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/rcar-gen3-thermal.yaml b/dts/upstream/Bindings/thermal/rcar-gen3-thermal.yaml
index 6a81cb6..b6657d6 100644
--- a/dts/upstream/Bindings/thermal/rcar-gen3-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/rcar-gen3-thermal.yaml
@@ -15,6 +15,8 @@
maintainers:
- Niklas Söderlund <niklas.soderlund@ragnatech.se>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -57,7 +59,6 @@
- clocks
- power-domains
- resets
- - "#thermal-sensor-cells"
if:
properties:
@@ -96,7 +97,7 @@
required:
- interrupts
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -105,33 +106,33 @@
#include <dt-bindings/power/r8a7795-sysc.h>
tsc: thermal@e6198000 {
- compatible = "renesas,r8a7795-thermal";
- reg = <0xe6198000 0x100>,
- <0xe61a0000 0x100>,
- <0xe61a8000 0x100>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <1>;
+ compatible = "renesas,r8a7795-thermal";
+ reg = <0xe6198000 0x100>,
+ <0xe61a0000 0x100>,
+ <0xe61a8000 0x100>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
- sensor_thermal: sensor-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsc 0>;
+ sensor_thermal: sensor-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsc 0>;
- trips {
- sensor1_crit: sensor1-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
+ trips {
+ sensor1_crit: sensor1-crit {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
};
+ };
};
- |
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
@@ -139,14 +140,14 @@
#include <dt-bindings/power/r8a779a0-sysc.h>
tsc_r8a779a0: thermal@e6190000 {
- compatible = "renesas,r8a779a0-thermal";
- reg = <0xe6190000 0x200>,
- <0xe6198000 0x200>,
- <0xe61a0000 0x200>,
- <0xe61a8000 0x200>,
- <0xe61b0000 0x200>;
- clocks = <&cpg CPG_MOD 919>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
- resets = <&cpg 919>;
- #thermal-sensor-cells = <1>;
+ compatible = "renesas,r8a779a0-thermal";
+ reg = <0xe6190000 0x200>,
+ <0xe6198000 0x200>,
+ <0xe61a0000 0x200>,
+ <0xe61a8000 0x200>,
+ <0xe61b0000 0x200>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ #thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/Bindings/thermal/rcar-thermal.yaml b/dts/upstream/Bindings/thermal/rcar-thermal.yaml
index 119998d..221a58d 100644
--- a/dts/upstream/Bindings/thermal/rcar-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/rcar-thermal.yaml
@@ -98,8 +98,8 @@
# Example (non interrupt support)
- |
thermal@ffc48000 {
- compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
- reg = <0xffc48000 0x38>;
+ compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
+ reg = <0xffc48000 0x38>;
};
# Example (interrupt support)
@@ -109,12 +109,12 @@
#include <dt-bindings/interrupt-controller/irq.h>
thermal@e61f0000 {
- compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
- reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>,
- <0xe61f0200 0x38>, <0xe61f0300 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
- power-domains = <&pd_c5>;
+ compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
+ reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>,
+ <0xe61f0200 0x38>, <0xe61f0300 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
+ power-domains = <&pd_c5>;
};
# Example (with thermal-zone)
@@ -124,32 +124,32 @@
#include <dt-bindings/power/r8a7790-sysc.h>
thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7790",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 522>;
- power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
- resets = <&cpg 522>;
- #thermal-sensor-cells = <0>;
+ compatible = "renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
};
thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
- thermal-sensors = <&thermal>;
+ thermal-sensors = <&thermal>;
- trips {
- cpu-crit {
- temperature = <115000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
};
+ };
};
diff --git a/dts/upstream/Bindings/thermal/rockchip-thermal.yaml b/dts/upstream/Bindings/thermal/rockchip-thermal.yaml
index 55f8ec0..b717ea8 100644
--- a/dts/upstream/Bindings/thermal/rockchip-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/rockchip-thermal.yaml
@@ -9,6 +9,8 @@
maintainers:
- Heiko Stuebner <heiko@sntech.de>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -76,9 +78,8 @@
- clocks
- clock-names
- resets
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/rzg2l-thermal.yaml b/dts/upstream/Bindings/thermal/rzg2l-thermal.yaml
index 03f4b92..136589f 100644
--- a/dts/upstream/Bindings/thermal/rzg2l-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/rzg2l-thermal.yaml
@@ -13,6 +13,8 @@
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
items:
@@ -43,36 +45,35 @@
- clocks
- power-domains
- resets
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
tsu: thermal@10059400 {
- compatible = "renesas,r9a07g044-tsu",
- "renesas,rzg2l-tsu";
- reg = <0x10059400 0x400>;
- clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
- resets = <&cpg R9A07G044_TSU_PRESETN>;
- power-domains = <&cpg>;
- #thermal-sensor-cells = <1>;
+ compatible = "renesas,r9a07g044-tsu",
+ "renesas,rzg2l-tsu";
+ reg = <0x10059400 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
+ resets = <&cpg R9A07G044_TSU_PRESETN>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&tsu 0>;
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsu 0>;
- trips {
- sensor_crit: sensor-crit {
- temperature = <125000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
+ trips {
+ sensor_crit: sensor-crit {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
+ };
};
diff --git a/dts/upstream/Bindings/thermal/samsung,exynos-thermal.yaml b/dts/upstream/Bindings/thermal/samsung,exynos-thermal.yaml
index 1344df7..29a08b0 100644
--- a/dts/upstream/Bindings/thermal/samsung,exynos-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/samsung,exynos-thermal.yaml
@@ -61,7 +61,8 @@
TRIMINFO at 0x10068000 contains data for TMU channel 2
minItems: 1
- '#thermal-sensor-cells': true
+ '#thermal-sensor-cells':
+ const: 0
vtmu-supply:
description: The regulator node supplying voltage to TMU.
diff --git a/dts/upstream/Bindings/thermal/socionext,uniphier-thermal.yaml b/dts/upstream/Bindings/thermal/socionext,uniphier-thermal.yaml
index 6f97582..8210b70 100644
--- a/dts/upstream/Bindings/thermal/socionext,uniphier-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/socionext,uniphier-thermal.yaml
@@ -14,6 +14,8 @@
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -38,9 +40,8 @@
required:
- compatible
- interrupts
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/sprd-thermal.yaml b/dts/upstream/Bindings/thermal/sprd-thermal.yaml
index 76aaa00..afa551f 100644
--- a/dts/upstream/Bindings/thermal/sprd-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/sprd-thermal.yaml
@@ -11,6 +11,8 @@
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: sprd,ums512-thermal
@@ -77,35 +79,34 @@
- clock-names
- nvmem-cells
- nvmem-cell-names
- - "#thermal-sensor-cells"
- "#address-cells"
- "#size-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- ap_thm0: thermal@32200000 {
- compatible = "sprd,ums512-thermal";
- reg = <0x32200000 0x10000>;
- clock-names = "enable";
- clocks = <&aonapb_gate 32>;
- #thermal-sensor-cells = <1>;
- nvmem-cells = <&thm0_sign>, <&thm0_ratio>;
- nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal";
- #address-cells = <1>;
- #size-cells = <0>;
+ thermal@32200000 {
+ compatible = "sprd,ums512-thermal";
+ reg = <0x32200000 0x10000>;
+ clock-names = "enable";
+ clocks = <&aonapb_gate 32>;
+ #thermal-sensor-cells = <1>;
+ nvmem-cells = <&thm0_sign>, <&thm0_ratio>;
+ nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal";
+ #address-cells = <1>;
+ #size-cells = <0>;
- prometheus-sensor@0 {
- reg = <0>;
- nvmem-cells = <&thm0_sen0>;
- nvmem-cell-names = "sen_delta_cal";
- };
+ prometheus-sensor@0 {
+ reg = <0>;
+ nvmem-cells = <&thm0_sen0>;
+ nvmem-cell-names = "sen_delta_cal";
+ };
- ank-sensor@1 {
- reg = <1>;
- nvmem-cells = <&thm0_sen1>;
- nvmem-cell-names = "sen_delta_cal";
- };
+ ank-sensor@1 {
+ reg = <1>;
+ nvmem-cells = <&thm0_sen1>;
+ nvmem-cell-names = "sen_delta_cal";
};
+ };
...
diff --git a/dts/upstream/Bindings/thermal/st,stm32-thermal.yaml b/dts/upstream/Bindings/thermal/st,stm32-thermal.yaml
index ab04308..1c01a80 100644
--- a/dts/upstream/Bindings/thermal/st,stm32-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/st,stm32-thermal.yaml
@@ -9,6 +9,8 @@
maintainers:
- Pascal Paillet <p.paillet@foss.st.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: st,stm32-thermal
@@ -30,14 +32,13 @@
const: 0
required:
- - "#thermal-sensor-cells"
- compatible
- reg
- interrupts
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/thermal/thermal-zones.yaml b/dts/upstream/Bindings/thermal/thermal-zones.yaml
index 68398e7..0f435be 100644
--- a/dts/upstream/Bindings/thermal/thermal-zones.yaml
+++ b/dts/upstream/Bindings/thermal/thermal-zones.yaml
@@ -49,7 +49,10 @@
to take when the temperature crosses those thresholds.
patternProperties:
- "^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$":
+ # Node name is limited in size due to Linux kernel requirements - 19
+ # characters in total (see THERMAL_NAME_LENGTH, including terminating NUL
+ # byte):
+ "^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$":
type: object
description:
Each thermal zone node contains information about how frequently it
@@ -229,7 +232,6 @@
required:
- thermal-sensors
- - trips
additionalProperties: false
diff --git a/dts/upstream/Bindings/thermal/ti,am654-thermal.yaml b/dts/upstream/Bindings/thermal/ti,am654-thermal.yaml
index 7ed0abe..c123d90 100644
--- a/dts/upstream/Bindings/thermal/ti,am654-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/ti,am654-thermal.yaml
@@ -9,6 +9,8 @@
maintainers:
- Keerthy <j-keerthy@ti.com>
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
const: ti,am654-vtm
@@ -26,9 +28,8 @@
- compatible
- reg
- power-domains
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -46,11 +47,11 @@
thermal-sensors = <&vtm0 0>;
trips {
- mpu0_crit: mpu0_crit {
- temperature = <125000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
+ mpu0_crit: mpu0_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
};
};
...
diff --git a/dts/upstream/Bindings/thermal/ti,j72xx-thermal.yaml b/dts/upstream/Bindings/thermal/ti,j72xx-thermal.yaml
index 171b362..82b77b9 100644
--- a/dts/upstream/Bindings/thermal/ti,j72xx-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/ti,j72xx-thermal.yaml
@@ -22,6 +22,8 @@
Temp(C) = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \
(-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01)
+$ref: thermal-sensor.yaml#
+
properties:
compatible:
enum:
@@ -64,9 +66,8 @@
- compatible
- reg
- power-domains
- - "#thermal-sensor-cells"
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/timer/realtek,otto-timer.yaml b/dts/upstream/Bindings/timer/realtek,otto-timer.yaml
new file mode 100644
index 0000000..7b6ec2c
--- /dev/null
+++ b/dts/upstream/Bindings/timer/realtek,otto-timer.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/realtek,otto-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek Otto SoCs Timer/Counter
+
+description:
+ Realtek SoCs support a number of timers/counters. These are used
+ as a per CPU clock event generator and an overall CPU clocksource.
+
+maintainers:
+ - Chris Packham <chris.packham@alliedtelesis.co.nz>
+
+properties:
+ $nodename:
+ pattern: "^timer@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - realtek,rtl9302-timer
+ - const: realtek,otto-timer
+
+ reg:
+ items:
+ - description: timer0 registers
+ - description: timer1 registers
+ - description: timer2 registers
+ - description: timer3 registers
+ - description: timer4 registers
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: timer0 interrupt
+ - description: timer1 interrupt
+ - description: timer2 interrupt
+ - description: timer3 interrupt
+ - description: timer4 interrupt
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@3200 {
+ compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
+ reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
+ <0x3230 0x10>, <0x3240 0x10>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <7>, <8>, <9>, <10>, <11>;
+ clocks = <&lx_clk>;
+ };
diff --git a/dts/upstream/Bindings/timer/renesas,tmu.yaml b/dts/upstream/Bindings/timer/renesas,tmu.yaml
index 360a5cf..75b0e7c 100644
--- a/dts/upstream/Bindings/timer/renesas,tmu.yaml
+++ b/dts/upstream/Bindings/timer/renesas,tmu.yaml
@@ -21,13 +21,24 @@
compatible:
items:
- enum:
+ - renesas,tmu-r8a73a4 # R-Mobile APE6
- renesas,tmu-r8a7740 # R-Mobile A1
+ - renesas,tmu-r8a7742 # RZ/G1H
+ - renesas,tmu-r8a7743 # RZ/G1M
+ - renesas,tmu-r8a7744 # RZ/G1N
+ - renesas,tmu-r8a7745 # RZ/G1E
+ - renesas,tmu-r8a77470 # RZ/G1C
- renesas,tmu-r8a774a1 # RZ/G2M
- renesas,tmu-r8a774b1 # RZ/G2N
- renesas,tmu-r8a774c0 # RZ/G2E
- renesas,tmu-r8a774e1 # RZ/G2H
- renesas,tmu-r8a7778 # R-Car M1A
- renesas,tmu-r8a7779 # R-Car H1
+ - renesas,tmu-r8a7790 # R-Car H2
+ - renesas,tmu-r8a7791 # R-Car M2-W
+ - renesas,tmu-r8a7792 # R-Car V2H
+ - renesas,tmu-r8a7793 # R-Car M2-N
+ - renesas,tmu-r8a7794 # R-Car E2
- renesas,tmu-r8a7795 # R-Car H3
- renesas,tmu-r8a7796 # R-Car M3-W
- renesas,tmu-r8a77961 # R-Car M3-W+
@@ -84,6 +95,7 @@
- compatible
- reg
- interrupts
+ - interrupt-names
- clocks
- clock-names
- power-domains
@@ -94,6 +106,7 @@
compatible:
contains:
enum:
+ - renesas,tmu-r8a73a4
- renesas,tmu-r8a7740
- renesas,tmu-r8a7778
- renesas,tmu-r8a7779
diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml
index fced6f2..b42d43d 100644
--- a/dts/upstream/Bindings/timer/sifive,clint.yaml
+++ b/dts/upstream/Bindings/timer/sifive,clint.yaml
@@ -40,6 +40,7 @@
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
+ - sophgo,sg2002-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:
diff --git a/dts/upstream/Bindings/timer/sprd,sc9860-timer.yaml b/dts/upstream/Bindings/timer/sprd,sc9860-timer.yaml
new file mode 100644
index 0000000..62c6da8
--- /dev/null
+++ b/dts/upstream/Bindings/timer/sprd,sc9860-timer.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/sprd,sc9860-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC9860 timer
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+description:
+ The Spreadtrum SC9860 platform provides 3 general-purpose timers.
+ These timers can support 32bit or 64bit counter, as well as supporting
+ period mode or one-shot mode, and they can be a wakeup source
+ during deep sleep.
+
+properties:
+ compatible:
+ enum:
+ - sprd,sc9860-timer
+ - sprd,sc9860-suspend-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9860-timer
+ then:
+ required:
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ timer@40050000 {
+ compatible = "sprd,sc9860-timer";
+ reg = <0 0x40050000 0 0x20>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_32k>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/timer/spreadtrum,sprd-timer.txt b/dts/upstream/Bindings/timer/spreadtrum,sprd-timer.txt
deleted file mode 100644
index 6d97e7d..0000000
--- a/dts/upstream/Bindings/timer/spreadtrum,sprd-timer.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Spreadtrum timers
-
-The Spreadtrum SC9860 platform provides 3 general-purpose timers.
-These timers can support 32bit or 64bit counter, as well as supporting
-period mode or one-shot mode, and they are can be wakeup source
-during deep sleep.
-
-Required properties:
-- compatible: should be "sprd,sc9860-timer" for SC9860 platform.
-- reg: The register address of the timer device.
-- interrupts: Should contain the interrupt for the timer device.
-- clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock).
-
-Example:
- timer@40050000 {
- compatible = "sprd,sc9860-timer";
- reg = <0 0x40050000 0 0x20>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ext_32k>;
- };
diff --git a/dts/upstream/Bindings/trivial-devices.yaml b/dts/upstream/Bindings/trivial-devices.yaml
index 0a41945..7913ca9 100644
--- a/dts/upstream/Bindings/trivial-devices.yaml
+++ b/dts/upstream/Bindings/trivial-devices.yaml
@@ -168,6 +168,8 @@
- isil,isl69269
# Intersil ISL76682 Ambient Light Sensor
- isil,isl76682
+ # JEDEC JESD300 (SPD5118) Hub and Serial Presence Detect
+ - jedec,spd5118
# Linear Technology LTC2488
- lineartechnology,ltc2488
# 5 Bit Programmable, Pulse-Width Modulator
@@ -286,14 +288,22 @@
- mps,mp2857
# Monolithic Power Systems Inc. multi-phase controller mp2888
- mps,mp2888
+ # Monolithic Power Systems Inc. multi-phase controller mp2891
+ - mps,mp2891
# Monolithic Power Systems Inc. multi-phase controller mp2971
- mps,mp2971
# Monolithic Power Systems Inc. multi-phase controller mp2973
- mps,mp2973
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
+ # Monolithic Power Systems Inc. multi-phase controller mp2993
+ - mps,mp2993
+ # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5920
+ - mps,mp5920
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
- mps,mp5990
+ # Monolithic Power Systems Inc. digital step-down converter mp9941
+ - mps,mp9941
# Monolithic Power Systems Inc. synchronous step-down converter mpq8785
- mps,mpq8785
# Temperature sensor with integrated fan control
@@ -318,7 +328,9 @@
- renesas,hs3001
# Renesas ISL29501 time-of-flight sensor
- renesas,isl29501
- # Rohm DH2228FV
+ # Rohm BH2228FV 8 channel DAC
+ - rohm,bh2228fv
+ # Rohm DH2228FV - This device does not exist, use rohm,bh2228fv instead.
- rohm,dh2228fv
# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
- samsung,24ad0xd1
@@ -354,6 +366,8 @@
- sparkfun,qwiic-joystick
# i2c serial eeprom (24cxx)
- st,24c256
+ # Sierra Wireless mangOH Green SPI IoT interface
+ - swir,mangoh-iotport-spi
# Ambient Light Sensor with SMBUS/Two Wire Serial Interface
- taos,tsl2550
# Temperature Monitoring and Fan Control
diff --git a/dts/upstream/Bindings/ufs/qcom,ufs.yaml b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
index cd3680d..25a5ede 100644
--- a/dts/upstream/Bindings/ufs/qcom,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
@@ -46,11 +46,11 @@
clocks:
minItems: 7
- maxItems: 11
+ maxItems: 9
clock-names:
minItems: 7
- maxItems: 11
+ maxItems: 9
dma-coherent: true
@@ -217,16 +217,14 @@
then:
properties:
clocks:
- minItems: 11
- maxItems: 11
+ minItems: 9
+ maxItems: 9
clock-names:
items:
- - const: core_clk_src
- const: core_clk
- const: bus_clk
- const: bus_aggr_clk
- const: iface_clk
- - const: core_clk_unipro_src
- const: core_clk_unipro
- const: core_clk_ice
- const: ref_clk
@@ -287,7 +285,7 @@
maxItems: 2
clocks:
minItems: 7
- maxItems: 11
+ maxItems: 9
unevaluatedProperties: false
diff --git a/dts/upstream/Bindings/usb/cdns,usb3.yaml b/dts/upstream/Bindings/usb/cdns,usb3.yaml
index 69a93a0..f454ddd 100644
--- a/dts/upstream/Bindings/usb/cdns,usb3.yaml
+++ b/dts/upstream/Bindings/usb/cdns,usb3.yaml
@@ -42,8 +42,11 @@
- const: otg
- const: wakeup
- dr_mode:
- enum: [host, otg, peripheral]
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ This port is used with the 'usb-role-switch' property to connect the
+ cdns3 to type C connector.
maximum-speed:
enum: [super-speed, high-speed, full-speed]
@@ -70,6 +73,9 @@
description: Enable resetting of PHY if Rx fail is detected
type: boolean
+dependencies:
+ port: [ usb-role-switch ]
+
required:
- compatible
- reg
@@ -77,7 +83,10 @@
- interrupts
- interrupt-names
-additionalProperties: false
+allOf:
+ - $ref: usb-drd.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/usb/dwc2.yaml b/dts/upstream/Bindings/usb/dwc2.yaml
index 4f36a22..a5f2e34 100644
--- a/dts/upstream/Bindings/usb/dwc2.yaml
+++ b/dts/upstream/Bindings/usb/dwc2.yaml
@@ -188,7 +188,7 @@
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/usb/fsl,usb2.yaml b/dts/upstream/Bindings/usb/fsl,usb2.yaml
new file mode 100644
index 0000000..caedf11
--- /dev/null
+++ b/dts/upstream/Bindings/usb/fsl,usb2.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fsl,usb2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SOC USB controllers
+
+maintainers:
+ - Frank Li <Frank.Li@nxp.com>
+
+description: |
+ The device node for a USB controller that is part of a Freescale
+ SOC is as described in the document "Open Firmware Recommended
+ Practice: Universal Serial Bus" with the following modifications
+ and additions.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl-usb2-mph
+ - fsl-usb2-dr
+ - items:
+ - enum:
+ - fsl-usb2-dr-v2.2
+ - fsl-usb2-dr-v2.5
+ - const: fsl-usb2-dr
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ phy_type:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ulpi, serial, utmi, utmi_wide]
+
+ port0:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicates port0 is connected for fsl-usb2-mph compatible controllers.
+
+ port1:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicates port1 is connected for "fsl-usb2-mph" compatible controllers.
+
+ fsl,invert-drvvbus:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ for MPC5121 USB0 only. Indicates the
+ port power polarity of internal PHY signal DRVVBUS is inverted.
+
+ fsl,invert-pwr-fault:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ for MPC5121 USB0 only. Indicates
+ the PWR_FAULT signal polarity is inverted.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - phy_type
+
+allOf:
+ - $ref: usb-drd.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ usb@22000 {
+ compatible = "fsl-usb2-mph";
+ reg = <22000 1000>;
+ interrupts = <27 IRQ_TYPE_EDGE_RISING>;
+ phy_type = "ulpi";
+ port0;
+ port1;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ usb@23000 {
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+ dr_mode = "otg";
+ phy_type = "ulpi";
+ };
diff --git a/dts/upstream/Bindings/usb/fsl-usb.txt b/dts/upstream/Bindings/usb/fsl-usb.txt
deleted file mode 100644
index 0b08b00..0000000
--- a/dts/upstream/Bindings/usb/fsl-usb.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-Freescale SOC USB controllers
-
-The device node for a USB controller that is part of a Freescale
-SOC is as described in the document "Open Firmware Recommended
-Practice : Universal Serial Bus" with the following modifications
-and additions :
-
-Required properties :
- - compatible : Should be "fsl-usb2-mph" for multi port host USB
- controllers, or "fsl-usb2-dr" for dual role USB controllers
- or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
- Wherever applicable, the IP version of the USB controller should
- also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
- - phy_type : For multi port host USB controllers, should be one of
- "ulpi", or "serial". For dual role USB controllers, should be
- one of "ulpi", "utmi", "utmi_wide", or "serial".
- - reg : Offset and length of the register set for the device
- - port0 : boolean; if defined, indicates port0 is connected for
- fsl-usb2-mph compatible controllers. Either this property or
- "port1" (or both) must be defined for "fsl-usb2-mph" compatible
- controllers.
- - port1 : boolean; if defined, indicates port1 is connected for
- fsl-usb2-mph compatible controllers. Either this property or
- "port0" (or both) must be defined for "fsl-usb2-mph" compatible
- controllers.
- - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
- controllers. Can be "host", "peripheral", or "otg". Default to
- "host" if not defined for backward compatibility.
-
-Recommended properties :
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
-
-Optional properties :
- - fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the
- port power polarity of internal PHY signal DRVVBUS is inverted.
- - fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates
- the PWR_FAULT signal polarity is inverted.
-
-Example multi port host USB controller device node :
- usb@22000 {
- compatible = "fsl-usb2-mph";
- reg = <22000 1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <700>;
- interrupts = <27 1>;
- phy_type = "ulpi";
- port0;
- port1;
- };
-
-Example dual role USB controller device node :
- usb@23000 {
- compatible = "fsl-usb2-dr";
- reg = <23000 1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <700>;
- interrupts = <26 1>;
- dr_mode = "otg";
- phy = "ulpi";
- };
-
-Example dual role USB controller device node for MPC5121ADS:
-
- usb@4000 {
- compatible = "fsl,mpc5121-usb2-dr";
- reg = <0x4000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = < &ipic >;
- interrupts = <44 0x8>;
- dr_mode = "otg";
- phy_type = "utmi_wide";
- fsl,invert-drvvbus;
- fsl,invert-pwr-fault;
- };
diff --git a/dts/upstream/Bindings/usb/genesys,gl850g.yaml b/dts/upstream/Bindings/usb/genesys,gl850g.yaml
index 37cf524..fc83336 100644
--- a/dts/upstream/Bindings/usb/genesys,gl850g.yaml
+++ b/dts/upstream/Bindings/usb/genesys,gl850g.yaml
@@ -9,9 +9,6 @@
maintainers:
- Icenowy Zheng <uwu@icenowy.me>
-allOf:
- - $ref: usb-device.yaml#
-
properties:
compatible:
enum:
@@ -27,17 +24,44 @@
vdd-supply:
description:
- the regulator that provides 3.3V core power to the hub.
+ The regulator that provides 3.3V or 5.0V core power to the hub.
peer-hub:
$ref: /schemas/types.yaml#/definitions/phandle
description:
- phandle to the peer hub on the controller.
+ For onboard hub controllers that support USB 3.x and USB 2.0 hubs
+ with shared resets and power supplies, this property is used to identify
+ the hubs with which these are shared.
required:
- compatible
- reg
+allOf:
+ - $ref: usb-device.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - usb5e3,608
+ then:
+ properties:
+ peer-hub: false
+ vdd-supply: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - usb5e3,610
+ - usb5e3,620
+ then:
+ properties:
+ peer-hub: true
+ vdd-supply: true
+
additionalProperties: false
examples:
@@ -54,3 +78,29 @@
reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>;
};
};
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ usb {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+
+ /* 3.1 hub on port 4 */
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+ };
diff --git a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
index 88e1607..8a5f837 100644
--- a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
+++ b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
@@ -22,6 +22,7 @@
- nxp,cbdtu02043
- onnn,fsusb43l10x
- pericom,pi3usb102
+ - ti,tmuxhs4212
- const: gpio-sbu-mux
enable-gpios:
@@ -44,13 +45,18 @@
required:
- compatible
- - enable-gpios
- select-gpios
- orientation-switch
- port
allOf:
- $ref: usb-switch.yaml#
+ - if:
+ required:
+ - mode-switch
+ then:
+ required:
+ - enable-gpios
additionalProperties: false
diff --git a/dts/upstream/Bindings/usb/microchip,mpfs-musb.yaml b/dts/upstream/Bindings/usb/microchip,mpfs-musb.yaml
index c5e9ce2..27b909d 100644
--- a/dts/upstream/Bindings/usb/microchip,mpfs-musb.yaml
+++ b/dts/upstream/Bindings/usb/microchip,mpfs-musb.yaml
@@ -34,6 +34,13 @@
clocks:
maxItems: 1
+ microchip,ext-vbus-drv:
+ description:
+ Some ULPI USB PHYs do not support an internal VBUS supply and driving
+ the CPEN pin requires the configuration of the UPLI_USE__EXTVBUS
+ bit in ULPI_BUSCONTROL.
+ $ref: /schemas/types.yaml#/definitions/flag
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/usb/microchip,usb2514.yaml b/dts/upstream/Bindings/usb/microchip,usb2514.yaml
index 783c275..b14e6f3 100644
--- a/dts/upstream/Bindings/usb/microchip,usb2514.yaml
+++ b/dts/upstream/Bindings/usb/microchip,usb2514.yaml
@@ -10,7 +10,7 @@
- Fabio Estevam <festevam@gmail.com>
allOf:
- - $ref: usb-hcd.yaml#
+ - $ref: usb-device.yaml#
properties:
compatible:
@@ -18,6 +18,7 @@
- usb424,2412
- usb424,2417
- usb424,2514
+ - usb424,2517
reg: true
@@ -35,6 +36,13 @@
- compatible
- reg
+patternProperties:
+ "^.*@[0-9a-f]{1,2}$":
+ description: The hard wired USB devices
+ type: object
+ $ref: /schemas/usb/usb-device.yaml
+ additionalProperties: true
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/usb/qcom,dwc3.yaml b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
index cf633d4..efde47a 100644
--- a/dts/upstream/Bindings/usb/qcom,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
@@ -30,6 +30,8 @@
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
+ - qcom,sc8180x-dwc3
+ - qcom,sc8180x-dwc3-mp
- qcom,sc8280xp-dwc3
- qcom,sc8280xp-dwc3-mp
- qcom,sdm660-dwc3
@@ -334,6 +336,8 @@
contains:
enum:
- qcom,qcm2290-dwc3
+ - qcom,sc8180x-dwc3
+ - qcom,sc8180x-dwc3-mp
- qcom,sm6115-dwc3
- qcom,sm6125-dwc3
- qcom,sm8150-dwc3
@@ -448,6 +452,7 @@
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
+ - qcom,sc8180x-dwc3
- qcom,sc8280xp-dwc3
- qcom,sdm670-dwc3
- qcom,sdm845-dwc3
@@ -480,6 +485,30 @@
compatible:
contains:
enum:
+ - qcom,sc8180x-dwc3-mp
+ then:
+ properties:
+ interrupts:
+ minItems: 10
+ maxItems: 10
+ interrupt-names:
+ items:
+ - const: pwr_event_1
+ - const: pwr_event_2
+ - const: hs_phy_1
+ - const: hs_phy_2
+ - const: dp_hs_phy_1
+ - const: dm_hs_phy_1
+ - const: dp_hs_phy_2
+ - const: dm_hs_phy_2
+ - const: ss_phy_1
+ - const: ss_phy_2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sc8280xp-dwc3-mp
then:
properties:
diff --git a/dts/upstream/Bindings/vendor-prefixes.yaml b/dts/upstream/Bindings/vendor-prefixes.yaml
index fbf47f0..a70ce43 100644
--- a/dts/upstream/Bindings/vendor-prefixes.yaml
+++ b/dts/upstream/Bindings/vendor-prefixes.yaml
@@ -246,6 +246,8 @@
description: CALAO Systems SAS
"^calxeda,.*":
description: Calxeda
+ "^cameo,.*":
+ description: Cameo Communications, Inc
"^canaan,.*":
description: Canaan, Inc.
"^caninos,.*":
@@ -338,6 +340,8 @@
description: Czech Technical University in Prague
"^cubietech,.*":
description: Cubietech, Ltd.
+ "^cudy,.*":
+ description: Shenzhen Cudy Technology Co., Ltd.
"^cui,.*":
description: CUI Devices
"^cypress,.*":
@@ -394,6 +398,8 @@
description: DPTechnics
"^dragino,.*":
description: Dragino Technology Co., Limited
+ "^dream,.*":
+ description: Dream Property GmbH
"^ds,.*":
description: DaSheng, Inc.
"^dserve,.*":
@@ -820,6 +826,8 @@
description: Lichee Pi
"^linaro,.*":
description: Linaro Limited
+ "^lincolntech,.*":
+ description: Lincoln Technology Solutions
"^lineartechnology,.*":
description: Linear Technology
"^linksprite,.*":
@@ -924,6 +932,8 @@
description: Microsoft Corporation
"^microsys,.*":
description: MicroSys Electronics GmbH
+ "^microtips,.*":
+ description: Microtips Technology USA
"^mikroe,.*":
description: MikroElektronika d.o.o.
"^mikrotik,.*":
@@ -995,6 +1005,8 @@
description: MYIR Tech Limited
"^national,.*":
description: National Semiconductor
+ "^neardi,.*":
+ description: Shanghai Neardi Technology Co., Ltd.
"^nec,.*":
description: NEC LCD Technologies, Ltd.
"^neonode,.*":
@@ -1082,6 +1094,8 @@
description: OpenPandora GmbH
"^openrisc,.*":
description: OpenRISC.io
+ "^openwrt,.*":
+ description: OpenWrt
"^option,.*":
description: Option NV
"^oranth,.*":
@@ -1160,6 +1174,8 @@
description: PowerVR (deprecated, use img)
"^powkiddy,.*":
description: Powkiddy
+ "^primeview,.*":
+ description: Prime View International (PVI)
"^primux,.*":
description: Primux Trading, S.L.
"^probox2,.*":
@@ -1254,6 +1270,10 @@
description: Smart Battery System
"^schindler,.*":
description: Schindler
+ "^schneider,.*":
+ description: Schneider Electric
+ "^sciosense,.*":
+ description: ScioSense B.V.
"^seagate,.*":
description: Seagate Technology PLC
"^seeed,.*":
diff --git a/dts/upstream/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml b/dts/upstream/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
index 69845ec..d0eff1e 100644
--- a/dts/upstream/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
@@ -21,6 +21,7 @@
- amlogic,t7-wdt
- items:
- enum:
+ - amlogic,a4-wdt
- amlogic,c3-wdt
- amlogic,s4-wdt
- const: amlogic,t7-wdt
diff --git a/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml b/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
index c8f6981..64619ba 100644
--- a/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
+++ b/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
@@ -28,7 +28,7 @@
Add this property to disable the watchdog during suspend.
Only use this option if you can't use the watchdog automatic suspend
function during a suspend (see register CONTROL_B).
-
+
dlg,wdt-sd:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
diff --git a/dts/upstream/Bindings/watchdog/fsl-imx-wdt.yaml b/dts/upstream/Bindings/watchdog/fsl-imx-wdt.yaml
index 181f0cc..36b836d 100644
--- a/dts/upstream/Bindings/watchdog/fsl-imx-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/fsl-imx-wdt.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX Watchdog Timer (WDT) Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/watchdog/fsl-imx7ulp-wdt.yaml b/dts/upstream/Bindings/watchdog/fsl-imx7ulp-wdt.yaml
index 9c50766..a09686b 100644
--- a/dts/upstream/Bindings/watchdog/fsl-imx7ulp-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/fsl-imx7ulp-wdt.yaml
@@ -7,7 +7,9 @@
title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller
maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
+ - Shawn Guo <shawnguo@kernel.org>
+ - Sascha Hauer <s.hauer@pengutronix.de>
+ - Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: watchdog.yaml#
diff --git a/dts/upstream/Bindings/watchdog/img,pdc-wdt.yaml b/dts/upstream/Bindings/watchdog/img,pdc-wdt.yaml
new file mode 100644
index 0000000..a88a273
--- /dev/null
+++ b/dts/upstream/Bindings/watchdog/img,pdc-wdt.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/img,pdc-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
+
+maintainers:
+ - Shresth Prasad <shresthprasad7@gmail.com>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ enum:
+ - img,pdc-wdt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: watchdog counter clock
+ - description: register interface clock
+
+ clock-names:
+ items:
+ - const: wdt
+ - const: sys
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ watchdog@18102100 {
+ compatible = "img,pdc-wdt";
+ reg = <0x18102100 0x100>;
+ clocks = <&pdc_wdt_clk>, <&sys_clk>;
+ clock-names = "wdt", "sys";
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/dts/upstream/Bindings/watchdog/imgpdc-wdt.txt b/dts/upstream/Bindings/watchdog/imgpdc-wdt.txt
deleted file mode 100644
index b2fa11f..0000000
--- a/dts/upstream/Bindings/watchdog/imgpdc-wdt.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-*ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
-
-Required properties:
-- compatible : Should be "img,pdc-wdt"
-- reg : Should contain WDT registers location and length
-- clocks: Must contain an entry for each entry in clock-names.
-- clock-names: Should contain "wdt" and "sys"; the watchdog counter
- clock and register interface clock respectively.
-- interrupts : Should contain WDT interrupt
-
-Examples:
-
-watchdog@18102100 {
- compatible = "img,pdc-wdt";
- reg = <0x18102100 0x100>;
- clocks = <&pdc_wdt_clk>, <&sys_clk>;
- clock-names = "wdt", "sys";
- interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
-};
diff --git a/dts/upstream/Bindings/watchdog/renesas,wdt.yaml b/dts/upstream/Bindings/watchdog/renesas,wdt.yaml
index ffb17ad..eba454d 100644
--- a/dts/upstream/Bindings/watchdog/renesas,wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/renesas,wdt.yaml
@@ -29,6 +29,7 @@
- renesas,r9a07g043-wdt # RZ/G2UL and RZ/Five
- renesas,r9a07g044-wdt # RZ/G2{L,LC}
- renesas,r9a07g054-wdt # RZ/V2L
+ - renesas,r9a08g045-wdt # RZ/G3S
- const: renesas,rzg2l-wdt
- items:
diff --git a/dts/upstream/include/dt-bindings/arm/qcom,ids.h b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
index d040033..d6c9e94 100644
--- a/dts/upstream/include/dt-bindings/arm/qcom,ids.h
+++ b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
@@ -175,6 +175,7 @@
#define QCOM_ID_SDA630 327
#define QCOM_ID_MSM8905 331
#define QCOM_ID_SDX202 333
+#define QCOM_ID_SDM670 336
#define QCOM_ID_SDM450 338
#define QCOM_ID_SM8150 339
#define QCOM_ID_SDA845 341
@@ -272,6 +273,7 @@
#define QCOM_ID_QCS8550 603
#define QCOM_ID_QCM8550 604
#define QCOM_ID_IPQ5300 624
+#define QCOM_ID_IPQ5321 650
/*
* The board type and revision information, used by Qualcomm bootloaders and
diff --git a/dts/upstream/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/dts/upstream/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
index 06f198e..2ce1a06 100644
--- a/dts/upstream/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ b/dts/upstream/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
@@ -164,5 +164,6 @@
#define CLKID_DMC_SEL 151
#define CLKID_DMC_DIV 152
#define CLKID_DMC_SEL2 153
+#define CLKID_SYS_PLL_DIV16 154
#endif /* __A1_PERIPHERALS_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/dts/upstream/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
index 2b660c0..0dfc5e7 100644
--- a/dts/upstream/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ b/dts/upstream/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
@@ -21,5 +21,6 @@
#define CLKID_FCLK_DIV5 8
#define CLKID_FCLK_DIV7 9
#define CLKID_HIFI_PLL 10
+#define CLKID_SYS_PLL 11
#endif /* __A1_PLL_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h b/dts/upstream/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
new file mode 100644
index 0000000..d115c74
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_XTAL_CLKIN 0
+#define CLKID_RTC_32K_DIV 1
+#define CLKID_RTC_32K_MUX 2
+#define CLKID_RTC_32K 3
+#define CLKID_RTC_CLK 4
+#define CLKID_SYS_RESET_CTRL 5
+#define CLKID_SYS_PWR_CTRL 6
+#define CLKID_SYS_PAD_CTRL 7
+#define CLKID_SYS_CTRL 8
+#define CLKID_SYS_TS_PLL 9
+#define CLKID_SYS_DEV_ARB 10
+#define CLKID_SYS_MMC_PCLK 11
+#define CLKID_SYS_CPU_CTRL 12
+#define CLKID_SYS_JTAG_CTRL 13
+#define CLKID_SYS_IR_CTRL 14
+#define CLKID_SYS_IRQ_CTRL 15
+#define CLKID_SYS_MSR_CLK 16
+#define CLKID_SYS_ROM 17
+#define CLKID_SYS_UART_F 18
+#define CLKID_SYS_CPU_ARB 19
+#define CLKID_SYS_RSA 20
+#define CLKID_SYS_SAR_ADC 21
+#define CLKID_SYS_STARTUP 22
+#define CLKID_SYS_SECURE 23
+#define CLKID_SYS_SPIFC 24
+#define CLKID_SYS_NNA 25
+#define CLKID_SYS_ETH_MAC 26
+#define CLKID_SYS_GIC 27
+#define CLKID_SYS_RAMA 28
+#define CLKID_SYS_BIG_NIC 29
+#define CLKID_SYS_RAMB 30
+#define CLKID_SYS_AUDIO_PCLK 31
+#define CLKID_SYS_PWM_KL 32
+#define CLKID_SYS_PWM_IJ 33
+#define CLKID_SYS_USB 34
+#define CLKID_SYS_SD_EMMC_A 35
+#define CLKID_SYS_SD_EMMC_C 36
+#define CLKID_SYS_PWM_AB 37
+#define CLKID_SYS_PWM_CD 38
+#define CLKID_SYS_PWM_EF 39
+#define CLKID_SYS_PWM_GH 40
+#define CLKID_SYS_SPICC_1 41
+#define CLKID_SYS_SPICC_0 42
+#define CLKID_SYS_UART_A 43
+#define CLKID_SYS_UART_B 44
+#define CLKID_SYS_UART_C 45
+#define CLKID_SYS_UART_D 46
+#define CLKID_SYS_UART_E 47
+#define CLKID_SYS_I2C_M_A 48
+#define CLKID_SYS_I2C_M_B 49
+#define CLKID_SYS_I2C_M_C 50
+#define CLKID_SYS_I2C_M_D 51
+#define CLKID_SYS_I2S_S_A 52
+#define CLKID_SYS_RTC 53
+#define CLKID_SYS_GE2D 54
+#define CLKID_SYS_ISP 55
+#define CLKID_SYS_GPV_ISP_NIC 56
+#define CLKID_SYS_GPV_CVE_NIC 57
+#define CLKID_SYS_MIPI_DSI_HOST 58
+#define CLKID_SYS_MIPI_DSI_PHY 59
+#define CLKID_SYS_ETH_PHY 60
+#define CLKID_SYS_ACODEC 61
+#define CLKID_SYS_DWAP 62
+#define CLKID_SYS_DOS 63
+#define CLKID_SYS_CVE 64
+#define CLKID_SYS_VOUT 65
+#define CLKID_SYS_VC9000E 66
+#define CLKID_SYS_PWM_MN 67
+#define CLKID_SYS_SD_EMMC_B 68
+#define CLKID_AXI_SYS_NIC 69
+#define CLKID_AXI_ISP_NIC 70
+#define CLKID_AXI_CVE_NIC 71
+#define CLKID_AXI_RAMB 72
+#define CLKID_AXI_RAMA 73
+#define CLKID_AXI_CPU_DMC 74
+#define CLKID_AXI_NIC 75
+#define CLKID_AXI_DMA 76
+#define CLKID_AXI_MUX_NIC 77
+#define CLKID_AXI_CVE 78
+#define CLKID_AXI_DEV1_DMC 79
+#define CLKID_AXI_DEV0_DMC 80
+#define CLKID_AXI_DSP_DMC 81
+#define CLKID_12_24M_IN 82
+#define CLKID_12M_24M 83
+#define CLKID_FCLK_25M_DIV 84
+#define CLKID_FCLK_25M 85
+#define CLKID_GEN_SEL 86
+#define CLKID_GEN_DIV 87
+#define CLKID_GEN 88
+#define CLKID_SARADC_SEL 89
+#define CLKID_SARADC_DIV 90
+#define CLKID_SARADC 91
+#define CLKID_PWM_A_SEL 92
+#define CLKID_PWM_A_DIV 93
+#define CLKID_PWM_A 94
+#define CLKID_PWM_B_SEL 95
+#define CLKID_PWM_B_DIV 96
+#define CLKID_PWM_B 97
+#define CLKID_PWM_C_SEL 98
+#define CLKID_PWM_C_DIV 99
+#define CLKID_PWM_C 100
+#define CLKID_PWM_D_SEL 101
+#define CLKID_PWM_D_DIV 102
+#define CLKID_PWM_D 103
+#define CLKID_PWM_E_SEL 104
+#define CLKID_PWM_E_DIV 105
+#define CLKID_PWM_E 106
+#define CLKID_PWM_F_SEL 107
+#define CLKID_PWM_F_DIV 108
+#define CLKID_PWM_F 109
+#define CLKID_PWM_G_SEL 110
+#define CLKID_PWM_G_DIV 111
+#define CLKID_PWM_G 112
+#define CLKID_PWM_H_SEL 113
+#define CLKID_PWM_H_DIV 114
+#define CLKID_PWM_H 115
+#define CLKID_PWM_I_SEL 116
+#define CLKID_PWM_I_DIV 117
+#define CLKID_PWM_I 118
+#define CLKID_PWM_J_SEL 119
+#define CLKID_PWM_J_DIV 120
+#define CLKID_PWM_J 121
+#define CLKID_PWM_K_SEL 122
+#define CLKID_PWM_K_DIV 123
+#define CLKID_PWM_K 124
+#define CLKID_PWM_L_SEL 125
+#define CLKID_PWM_L_DIV 126
+#define CLKID_PWM_L 127
+#define CLKID_PWM_M_SEL 128
+#define CLKID_PWM_M_DIV 129
+#define CLKID_PWM_M 130
+#define CLKID_PWM_N_SEL 131
+#define CLKID_PWM_N_DIV 132
+#define CLKID_PWM_N 133
+#define CLKID_SPICC_A_SEL 134
+#define CLKID_SPICC_A_DIV 135
+#define CLKID_SPICC_A 136
+#define CLKID_SPICC_B_SEL 137
+#define CLKID_SPICC_B_DIV 138
+#define CLKID_SPICC_B 139
+#define CLKID_SPIFC_SEL 140
+#define CLKID_SPIFC_DIV 141
+#define CLKID_SPIFC 142
+#define CLKID_SD_EMMC_A_SEL 143
+#define CLKID_SD_EMMC_A_DIV 144
+#define CLKID_SD_EMMC_A 145
+#define CLKID_SD_EMMC_B_SEL 146
+#define CLKID_SD_EMMC_B_DIV 147
+#define CLKID_SD_EMMC_B 148
+#define CLKID_SD_EMMC_C_SEL 149
+#define CLKID_SD_EMMC_C_DIV 150
+#define CLKID_SD_EMMC_C 151
+#define CLKID_TS_DIV 152
+#define CLKID_TS 153
+#define CLKID_ETH_125M_DIV 154
+#define CLKID_ETH_125M 155
+#define CLKID_ETH_RMII_DIV 156
+#define CLKID_ETH_RMII 157
+#define CLKID_MIPI_DSI_MEAS_SEL 158
+#define CLKID_MIPI_DSI_MEAS_DIV 159
+#define CLKID_MIPI_DSI_MEAS 160
+#define CLKID_DSI_PHY_SEL 161
+#define CLKID_DSI_PHY_DIV 162
+#define CLKID_DSI_PHY 163
+#define CLKID_VOUT_MCLK_SEL 164
+#define CLKID_VOUT_MCLK_DIV 165
+#define CLKID_VOUT_MCLK 166
+#define CLKID_VOUT_ENC_SEL 167
+#define CLKID_VOUT_ENC_DIV 168
+#define CLKID_VOUT_ENC 169
+#define CLKID_HCODEC_0_SEL 170
+#define CLKID_HCODEC_0_DIV 171
+#define CLKID_HCODEC_0 172
+#define CLKID_HCODEC_1_SEL 173
+#define CLKID_HCODEC_1_DIV 174
+#define CLKID_HCODEC_1 175
+#define CLKID_HCODEC 176
+#define CLKID_VC9000E_ACLK_SEL 177
+#define CLKID_VC9000E_ACLK_DIV 178
+#define CLKID_VC9000E_ACLK 179
+#define CLKID_VC9000E_CORE_SEL 180
+#define CLKID_VC9000E_CORE_DIV 181
+#define CLKID_VC9000E_CORE 182
+#define CLKID_CSI_PHY0_SEL 183
+#define CLKID_CSI_PHY0_DIV 184
+#define CLKID_CSI_PHY0 185
+#define CLKID_DEWARPA_SEL 186
+#define CLKID_DEWARPA_DIV 187
+#define CLKID_DEWARPA 188
+#define CLKID_ISP0_SEL 189
+#define CLKID_ISP0_DIV 190
+#define CLKID_ISP0 191
+#define CLKID_NNA_CORE_SEL 192
+#define CLKID_NNA_CORE_DIV 193
+#define CLKID_NNA_CORE 194
+#define CLKID_GE2D_SEL 195
+#define CLKID_GE2D_DIV 196
+#define CLKID_GE2D 197
+#define CLKID_VAPB_SEL 198
+#define CLKID_VAPB_DIV 199
+#define CLKID_VAPB 200
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/dts/upstream/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
new file mode 100644
index 0000000..fcdc558
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+
+#define CLKID_FCLK_50M_EN 0
+#define CLKID_FCLK_50M 1
+#define CLKID_FCLK_DIV2_DIV 2
+#define CLKID_FCLK_DIV2 3
+#define CLKID_FCLK_DIV2P5_DIV 4
+#define CLKID_FCLK_DIV2P5 5
+#define CLKID_FCLK_DIV3_DIV 6
+#define CLKID_FCLK_DIV3 7
+#define CLKID_FCLK_DIV4_DIV 8
+#define CLKID_FCLK_DIV4 9
+#define CLKID_FCLK_DIV5_DIV 10
+#define CLKID_FCLK_DIV5 11
+#define CLKID_FCLK_DIV7_DIV 12
+#define CLKID_FCLK_DIV7 13
+#define CLKID_GP0_PLL_DCO 14
+#define CLKID_GP0_PLL 15
+#define CLKID_HIFI_PLL_DCO 16
+#define CLKID_HIFI_PLL 17
+#define CLKID_MCLK_PLL_DCO 18
+#define CLKID_MCLK_PLL_OD 19
+#define CLKID_MCLK_PLL 20
+#define CLKID_MCLK0_SEL 21
+#define CLKID_MCLK0_SEL_EN 22
+#define CLKID_MCLK0_DIV 23
+#define CLKID_MCLK0 24
+#define CLKID_MCLK1_SEL 25
+#define CLKID_MCLK1_SEL_EN 26
+#define CLKID_MCLK1_DIV 27
+#define CLKID_MCLK1 28
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h b/dts/upstream/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h
new file mode 100644
index 0000000..663c9b3
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/amlogic,c3-scmi-clkc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@amlogic.com>
+ */
+
+#ifndef __AMLOGIC_C3_SCMI_CLKC_H
+#define __AMLOGIC_C3_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC 0
+#define CLKID_DDR_PHY 1
+#define CLKID_TOP_PLL_OSC 2
+#define CLKID_USB_PLL_OSC 3
+#define CLKID_MIPIISP_VOUT 4
+#define CLKID_MCLK_PLL_OSC 5
+#define CLKID_USB_CTRL 6
+#define CLKID_ETH_PLL_OSC 7
+#define CLKID_OSC 8
+#define CLKID_SYS_CLK 9
+#define CLKID_AXI_CLK 10
+#define CLKID_CPU_CLK 11
+#define CLKID_FIXED_PLL_OSC 12
+#define CLKID_GP1_PLL_OSC 13
+#define CLKID_SYS_PLL_DIV16 14
+#define CLKID_CPU_CLK_DIV16 15
+
+#endif /* __AMLOGIC_C3_SCMI_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 08fd3a3..52123c5 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -216,4 +216,8 @@
#define GCC_CRYPTO_AHB_CLK 207
#define GCC_USB0_PIPE_CLK 208
#define GCC_USB0_SLEEP_CLK 209
+#define GCC_PCIE0_PIPE_CLK 210
+#define GCC_PCIE1_PIPE_CLK 211
+#define GCC_PCIE2_PIPE_CLK 212
+#define GCC_PCIE3_PIPE_CLK 213
#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qca8k-nsscc.h b/dts/upstream/include/dt-bindings/clock/qcom,qca8k-nsscc.h
new file mode 100644
index 0000000..0ac3e4c
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qca8k-nsscc.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
+#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
+
+#define NSS_CC_SWITCH_CORE_CLK_SRC 0
+#define NSS_CC_SWITCH_CORE_CLK 1
+#define NSS_CC_APB_BRIDGE_CLK 2
+#define NSS_CC_MAC0_TX_CLK_SRC 3
+#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4
+#define NSS_CC_MAC0_TX_CLK 5
+#define NSS_CC_MAC0_TX_SRDS1_CLK 6
+#define NSS_CC_MAC0_RX_CLK_SRC 7
+#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8
+#define NSS_CC_MAC0_RX_CLK 9
+#define NSS_CC_MAC0_RX_SRDS1_CLK 10
+#define NSS_CC_MAC1_TX_CLK_SRC 11
+#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13
+#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14
+#define NSS_CC_MAC1_TX_CLK 15
+#define NSS_CC_MAC1_GEPHY0_TX_CLK 16
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17
+#define NSS_CC_MAC1_RX_CLK_SRC 18
+#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20
+#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21
+#define NSS_CC_MAC1_RX_CLK 22
+#define NSS_CC_MAC1_GEPHY0_RX_CLK 23
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24
+#define NSS_CC_MAC2_TX_CLK_SRC 25
+#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27
+#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28
+#define NSS_CC_MAC2_TX_CLK 29
+#define NSS_CC_MAC2_GEPHY1_TX_CLK 30
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31
+#define NSS_CC_MAC2_RX_CLK_SRC 32
+#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34
+#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35
+#define NSS_CC_MAC2_RX_CLK 36
+#define NSS_CC_MAC2_GEPHY1_RX_CLK 37
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38
+#define NSS_CC_MAC3_TX_CLK_SRC 39
+#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41
+#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42
+#define NSS_CC_MAC3_TX_CLK 43
+#define NSS_CC_MAC3_GEPHY2_TX_CLK 44
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45
+#define NSS_CC_MAC3_RX_CLK_SRC 46
+#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48
+#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49
+#define NSS_CC_MAC3_RX_CLK 50
+#define NSS_CC_MAC3_GEPHY2_RX_CLK 51
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52
+#define NSS_CC_MAC4_TX_CLK_SRC 53
+#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55
+#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56
+#define NSS_CC_MAC4_TX_CLK 57
+#define NSS_CC_MAC4_GEPHY3_TX_CLK 58
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59
+#define NSS_CC_MAC4_RX_CLK_SRC 60
+#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62
+#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63
+#define NSS_CC_MAC4_RX_CLK 64
+#define NSS_CC_MAC4_GEPHY3_RX_CLK 65
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66
+#define NSS_CC_MAC5_TX_CLK_SRC 67
+#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68
+#define NSS_CC_MAC5_TX_SRDS0_CLK 69
+#define NSS_CC_MAC5_TX_CLK 70
+#define NSS_CC_MAC5_RX_CLK_SRC 71
+#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72
+#define NSS_CC_MAC5_RX_SRDS0_CLK 73
+#define NSS_CC_MAC5_RX_CLK 74
+#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75
+#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76
+#define NSS_CC_AHB_CLK_SRC 77
+#define NSS_CC_AHB_CLK 78
+#define NSS_CC_SEC_CTRL_AHB_CLK 79
+#define NSS_CC_TLMM_CLK 80
+#define NSS_CC_TLMM_AHB_CLK 81
+#define NSS_CC_CNOC_AHB_CLK 82
+#define NSS_CC_MDIO_AHB_CLK 83
+#define NSS_CC_MDIO_MASTER_AHB_CLK 84
+#define NSS_CC_SYS_CLK_SRC 85
+#define NSS_CC_SRDS0_SYS_CLK 86
+#define NSS_CC_SRDS1_SYS_CLK 87
+#define NSS_CC_GEPHY0_SYS_CLK 88
+#define NSS_CC_GEPHY1_SYS_CLK 89
+#define NSS_CC_GEPHY2_SYS_CLK 90
+#define NSS_CC_GEPHY3_SYS_CLK 91
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcm2290-gpucc.h
new file mode 100644
index 0000000..7c76dd0
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcm2290-gpucc.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_GFX3D_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+#define GPU_CC_GX_GFX3D_CLK 8
+#define GPU_CC_GX_GFX3D_CLK_SRC 9
+#define GPU_CC_PLL0 10
+#define GPU_CC_SLEEP_CLK 11
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12
+
+/* Resets */
+#define GPU_GX_BCR 0
+
+/* GDSCs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm7150-camcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-camcc.h
new file mode 100644
index 0000000..ce73ef0
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-camcc.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_CAMCC_SM7150_H
+
+/* Hardware clocks */
+#define CAMCC_PLL0_OUT_EVEN 0
+#define CAMCC_PLL0_OUT_ODD 1
+#define CAMCC_PLL1_OUT_EVEN 2
+#define CAMCC_PLL2_OUT_EARLY 3
+#define CAMCC_PLL3_OUT_EVEN 4
+#define CAMCC_PLL4_OUT_EVEN 5
+
+/* CAMCC clock registers */
+#define CAMCC_PLL0 6
+#define CAMCC_PLL1 7
+#define CAMCC_PLL2 8
+#define CAMCC_PLL2_OUT_AUX 9
+#define CAMCC_PLL2_OUT_MAIN 10
+#define CAMCC_PLL3 11
+#define CAMCC_PLL4 12
+#define CAMCC_BPS_AHB_CLK 13
+#define CAMCC_BPS_AREG_CLK 14
+#define CAMCC_BPS_AXI_CLK 15
+#define CAMCC_BPS_CLK 16
+#define CAMCC_BPS_CLK_SRC 17
+#define CAMCC_CAMNOC_AXI_CLK 18
+#define CAMCC_CAMNOC_AXI_CLK_SRC 19
+#define CAMCC_CAMNOC_DCD_XO_CLK 20
+#define CAMCC_CCI_0_CLK 21
+#define CAMCC_CCI_0_CLK_SRC 22
+#define CAMCC_CCI_1_CLK 23
+#define CAMCC_CCI_1_CLK_SRC 24
+#define CAMCC_CORE_AHB_CLK 25
+#define CAMCC_CPAS_AHB_CLK 26
+#define CAMCC_CPHY_RX_CLK_SRC 27
+#define CAMCC_CSI0PHYTIMER_CLK 28
+#define CAMCC_CSI0PHYTIMER_CLK_SRC 29
+#define CAMCC_CSI1PHYTIMER_CLK 30
+#define CAMCC_CSI1PHYTIMER_CLK_SRC 31
+#define CAMCC_CSI2PHYTIMER_CLK 32
+#define CAMCC_CSI2PHYTIMER_CLK_SRC 33
+#define CAMCC_CSI3PHYTIMER_CLK 34
+#define CAMCC_CSI3PHYTIMER_CLK_SRC 35
+#define CAMCC_CSIPHY0_CLK 36
+#define CAMCC_CSIPHY1_CLK 37
+#define CAMCC_CSIPHY2_CLK 38
+#define CAMCC_CSIPHY3_CLK 39
+#define CAMCC_FAST_AHB_CLK_SRC 40
+#define CAMCC_FD_CORE_CLK 41
+#define CAMCC_FD_CORE_CLK_SRC 42
+#define CAMCC_FD_CORE_UAR_CLK 43
+#define CAMCC_ICP_AHB_CLK 44
+#define CAMCC_ICP_CLK 45
+#define CAMCC_ICP_CLK_SRC 46
+#define CAMCC_IFE_0_AXI_CLK 47
+#define CAMCC_IFE_0_CLK 48
+#define CAMCC_IFE_0_CLK_SRC 49
+#define CAMCC_IFE_0_CPHY_RX_CLK 50
+#define CAMCC_IFE_0_CSID_CLK 51
+#define CAMCC_IFE_0_CSID_CLK_SRC 52
+#define CAMCC_IFE_0_DSP_CLK 53
+#define CAMCC_IFE_1_AXI_CLK 54
+#define CAMCC_IFE_1_CLK 55
+#define CAMCC_IFE_1_CLK_SRC 56
+#define CAMCC_IFE_1_CPHY_RX_CLK 57
+#define CAMCC_IFE_1_CSID_CLK 58
+#define CAMCC_IFE_1_CSID_CLK_SRC 59
+#define CAMCC_IFE_1_DSP_CLK 60
+#define CAMCC_IFE_LITE_CLK 61
+#define CAMCC_IFE_LITE_CLK_SRC 62
+#define CAMCC_IFE_LITE_CPHY_RX_CLK 63
+#define CAMCC_IFE_LITE_CSID_CLK 64
+#define CAMCC_IFE_LITE_CSID_CLK_SRC 65
+#define CAMCC_IPE_0_AHB_CLK 66
+#define CAMCC_IPE_0_AREG_CLK 67
+#define CAMCC_IPE_0_AXI_CLK 68
+#define CAMCC_IPE_0_CLK 69
+#define CAMCC_IPE_0_CLK_SRC 70
+#define CAMCC_IPE_1_AHB_CLK 71
+#define CAMCC_IPE_1_AREG_CLK 72
+#define CAMCC_IPE_1_AXI_CLK 73
+#define CAMCC_IPE_1_CLK 74
+#define CAMCC_JPEG_CLK 75
+#define CAMCC_JPEG_CLK_SRC 76
+#define CAMCC_LRME_CLK 77
+#define CAMCC_LRME_CLK_SRC 78
+#define CAMCC_MCLK0_CLK 79
+#define CAMCC_MCLK0_CLK_SRC 80
+#define CAMCC_MCLK1_CLK 81
+#define CAMCC_MCLK1_CLK_SRC 82
+#define CAMCC_MCLK2_CLK 83
+#define CAMCC_MCLK2_CLK_SRC 84
+#define CAMCC_MCLK3_CLK 85
+#define CAMCC_MCLK3_CLK_SRC 86
+#define CAMCC_SLEEP_CLK 87
+#define CAMCC_SLEEP_CLK_SRC 88
+#define CAMCC_SLOW_AHB_CLK_SRC 89
+#define CAMCC_XO_CLK_SRC 90
+
+/* CAMCC GDSCRs */
+#define BPS_GDSC 0
+#define IFE_0_GDSC 1
+#define IFE_1_GDSC 2
+#define IPE_0_GDSC 3
+#define IPE_1_GDSC 4
+#define TITAN_TOP_GDSC 5
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h
new file mode 100644
index 0000000..fc1fefe
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-dispcc.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H
+
+/* DISPCC clock registers */
+#define DISPCC_PLL0 0
+#define DISPCC_MDSS_AHB_CLK 1
+#define DISPCC_MDSS_AHB_CLK_SRC 2
+#define DISPCC_MDSS_BYTE0_CLK 3
+#define DISPCC_MDSS_BYTE0_CLK_SRC 4
+#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5
+#define DISPCC_MDSS_BYTE0_INTF_CLK 6
+#define DISPCC_MDSS_BYTE1_CLK 7
+#define DISPCC_MDSS_BYTE1_CLK_SRC 8
+#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9
+#define DISPCC_MDSS_BYTE1_INTF_CLK 10
+#define DISPCC_MDSS_DP_AUX_CLK 11
+#define DISPCC_MDSS_DP_AUX_CLK_SRC 12
+#define DISPCC_MDSS_DP_CRYPTO_CLK 13
+#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14
+#define DISPCC_MDSS_DP_LINK_CLK 15
+#define DISPCC_MDSS_DP_LINK_CLK_SRC 16
+#define DISPCC_MDSS_DP_LINK_INTF_CLK 17
+#define DISPCC_MDSS_DP_PIXEL1_CLK 18
+#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19
+#define DISPCC_MDSS_DP_PIXEL_CLK 20
+#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21
+#define DISPCC_MDSS_ESC0_CLK 22
+#define DISPCC_MDSS_ESC0_CLK_SRC 23
+#define DISPCC_MDSS_ESC1_CLK 24
+#define DISPCC_MDSS_ESC1_CLK_SRC 25
+#define DISPCC_MDSS_MDP_CLK 26
+#define DISPCC_MDSS_MDP_CLK_SRC 27
+#define DISPCC_MDSS_MDP_LUT_CLK 28
+#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29
+#define DISPCC_MDSS_PCLK0_CLK 30
+#define DISPCC_MDSS_PCLK0_CLK_SRC 31
+#define DISPCC_MDSS_PCLK1_CLK 32
+#define DISPCC_MDSS_PCLK1_CLK_SRC 33
+#define DISPCC_MDSS_ROT_CLK 34
+#define DISPCC_MDSS_ROT_CLK_SRC 35
+#define DISPCC_MDSS_RSCC_AHB_CLK 36
+#define DISPCC_MDSS_RSCC_VSYNC_CLK 37
+#define DISPCC_MDSS_VSYNC_CLK 38
+#define DISPCC_MDSS_VSYNC_CLK_SRC 39
+#define DISPCC_XO_CLK_SRC 40
+#define DISPCC_SLEEP_CLK 41
+#define DISPCC_SLEEP_CLK_SRC 42
+
+/* DISPCC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm7150-videocc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-videocc.h
new file mode 100644
index 0000000..d86e0fb
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm7150-videocc.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEOCC_SM7150_H
+
+#define VIDEOCC_PLL0 0
+#define VIDEOCC_IRIS_AHB_CLK 1
+#define VIDEOCC_IRIS_CLK_SRC 2
+#define VIDEOCC_MVS0_AXI_CLK 3
+#define VIDEOCC_MVS0_CORE_CLK 4
+#define VIDEOCC_MVS1_AXI_CLK 5
+#define VIDEOCC_MVS1_CORE_CLK 6
+#define VIDEOCC_MVSC_CORE_CLK 7
+#define VIDEOCC_MVSC_CTL_AXI_CLK 8
+#define VIDEOCC_VENUS_AHB_CLK 9
+#define VIDEOCC_XO_CLK 10
+#define VIDEOCC_XO_CLK_SRC 11
+
+/* VIDEOCC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+#define VCODEC1_GDSC 2
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-camcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-camcc.h
new file mode 100644
index 0000000..df73bf3
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-camcc.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_CLK 1
+#define CAM_CC_BPS_CLK_SRC 2
+#define CAM_CC_BPS_FAST_AHB_CLK 3
+#define CAM_CC_BPS_SHIFT_CLK 4
+#define CAM_CC_CAMNOC_AXI_NRT_CLK 5
+#define CAM_CC_CAMNOC_AXI_RT_CLK 6
+#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7
+#define CAM_CC_CAMNOC_DCD_XO_CLK 8
+#define CAM_CC_CAMNOC_XO_CLK 9
+#define CAM_CC_CCI_0_CLK 10
+#define CAM_CC_CCI_0_CLK_SRC 11
+#define CAM_CC_CCI_1_CLK 12
+#define CAM_CC_CCI_1_CLK_SRC 13
+#define CAM_CC_CCI_2_CLK 14
+#define CAM_CC_CCI_2_CLK_SRC 15
+#define CAM_CC_CORE_AHB_CLK 16
+#define CAM_CC_CPAS_AHB_CLK 17
+#define CAM_CC_CPAS_BPS_CLK 18
+#define CAM_CC_CPAS_CRE_CLK 19
+#define CAM_CC_CPAS_FAST_AHB_CLK 20
+#define CAM_CC_CPAS_IFE_0_CLK 21
+#define CAM_CC_CPAS_IFE_1_CLK 22
+#define CAM_CC_CPAS_IFE_2_CLK 23
+#define CAM_CC_CPAS_IFE_LITE_CLK 24
+#define CAM_CC_CPAS_IPE_NPS_CLK 25
+#define CAM_CC_CPAS_SBI_CLK 26
+#define CAM_CC_CPAS_SFE_0_CLK 27
+#define CAM_CC_CPAS_SFE_1_CLK 28
+#define CAM_CC_CPAS_SFE_2_CLK 29
+#define CAM_CC_CPHY_RX_CLK_SRC 30
+#define CAM_CC_CRE_AHB_CLK 31
+#define CAM_CC_CRE_CLK 32
+#define CAM_CC_CRE_CLK_SRC 33
+#define CAM_CC_CSI0PHYTIMER_CLK 34
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35
+#define CAM_CC_CSI1PHYTIMER_CLK 36
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37
+#define CAM_CC_CSI2PHYTIMER_CLK 38
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39
+#define CAM_CC_CSI3PHYTIMER_CLK 40
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41
+#define CAM_CC_CSI4PHYTIMER_CLK 42
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43
+#define CAM_CC_CSI5PHYTIMER_CLK 44
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45
+#define CAM_CC_CSI6PHYTIMER_CLK 46
+#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47
+#define CAM_CC_CSI7PHYTIMER_CLK 48
+#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49
+#define CAM_CC_CSID_CLK 50
+#define CAM_CC_CSID_CLK_SRC 51
+#define CAM_CC_CSID_CSIPHY_RX_CLK 52
+#define CAM_CC_CSIPHY0_CLK 53
+#define CAM_CC_CSIPHY1_CLK 54
+#define CAM_CC_CSIPHY2_CLK 55
+#define CAM_CC_CSIPHY3_CLK 56
+#define CAM_CC_CSIPHY4_CLK 57
+#define CAM_CC_CSIPHY5_CLK 58
+#define CAM_CC_CSIPHY6_CLK 59
+#define CAM_CC_CSIPHY7_CLK 60
+#define CAM_CC_DRV_AHB_CLK 61
+#define CAM_CC_DRV_XO_CLK 62
+#define CAM_CC_FAST_AHB_CLK_SRC 63
+#define CAM_CC_GDSC_CLK 64
+#define CAM_CC_ICP_AHB_CLK 65
+#define CAM_CC_ICP_CLK 66
+#define CAM_CC_ICP_CLK_SRC 67
+#define CAM_CC_IFE_0_CLK 68
+#define CAM_CC_IFE_0_CLK_SRC 69
+#define CAM_CC_IFE_0_FAST_AHB_CLK 70
+#define CAM_CC_IFE_0_SHIFT_CLK 71
+#define CAM_CC_IFE_1_CLK 72
+#define CAM_CC_IFE_1_CLK_SRC 73
+#define CAM_CC_IFE_1_FAST_AHB_CLK 74
+#define CAM_CC_IFE_1_SHIFT_CLK 75
+#define CAM_CC_IFE_2_CLK 76
+#define CAM_CC_IFE_2_CLK_SRC 77
+#define CAM_CC_IFE_2_FAST_AHB_CLK 78
+#define CAM_CC_IFE_2_SHIFT_CLK 79
+#define CAM_CC_IFE_LITE_AHB_CLK 80
+#define CAM_CC_IFE_LITE_CLK 81
+#define CAM_CC_IFE_LITE_CLK_SRC 82
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83
+#define CAM_CC_IFE_LITE_CSID_CLK 84
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85
+#define CAM_CC_IPE_NPS_AHB_CLK 86
+#define CAM_CC_IPE_NPS_CLK 87
+#define CAM_CC_IPE_NPS_CLK_SRC 88
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89
+#define CAM_CC_IPE_PPS_CLK 90
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91
+#define CAM_CC_IPE_SHIFT_CLK 92
+#define CAM_CC_JPEG_1_CLK 93
+#define CAM_CC_JPEG_CLK 94
+#define CAM_CC_JPEG_CLK_SRC 95
+#define CAM_CC_MCLK0_CLK 96
+#define CAM_CC_MCLK0_CLK_SRC 97
+#define CAM_CC_MCLK1_CLK 98
+#define CAM_CC_MCLK1_CLK_SRC 99
+#define CAM_CC_MCLK2_CLK 100
+#define CAM_CC_MCLK2_CLK_SRC 101
+#define CAM_CC_MCLK3_CLK 102
+#define CAM_CC_MCLK3_CLK_SRC 103
+#define CAM_CC_MCLK4_CLK 104
+#define CAM_CC_MCLK4_CLK_SRC 105
+#define CAM_CC_MCLK5_CLK 106
+#define CAM_CC_MCLK5_CLK_SRC 107
+#define CAM_CC_MCLK6_CLK 108
+#define CAM_CC_MCLK6_CLK_SRC 109
+#define CAM_CC_MCLK7_CLK 110
+#define CAM_CC_MCLK7_CLK_SRC 111
+#define CAM_CC_PLL0 112
+#define CAM_CC_PLL0_OUT_EVEN 113
+#define CAM_CC_PLL0_OUT_ODD 114
+#define CAM_CC_PLL1 115
+#define CAM_CC_PLL1_OUT_EVEN 116
+#define CAM_CC_PLL2 117
+#define CAM_CC_PLL3 118
+#define CAM_CC_PLL3_OUT_EVEN 119
+#define CAM_CC_PLL4 120
+#define CAM_CC_PLL4_OUT_EVEN 121
+#define CAM_CC_PLL5 122
+#define CAM_CC_PLL5_OUT_EVEN 123
+#define CAM_CC_PLL6 124
+#define CAM_CC_PLL6_OUT_EVEN 125
+#define CAM_CC_PLL7 126
+#define CAM_CC_PLL7_OUT_EVEN 127
+#define CAM_CC_PLL8 128
+#define CAM_CC_PLL8_OUT_EVEN 129
+#define CAM_CC_PLL9 130
+#define CAM_CC_PLL9_OUT_EVEN 131
+#define CAM_CC_PLL9_OUT_ODD 132
+#define CAM_CC_PLL10 133
+#define CAM_CC_PLL10_OUT_EVEN 134
+#define CAM_CC_QDSS_DEBUG_CLK 135
+#define CAM_CC_QDSS_DEBUG_CLK_SRC 136
+#define CAM_CC_QDSS_DEBUG_XO_CLK 137
+#define CAM_CC_SBI_CLK 138
+#define CAM_CC_SBI_FAST_AHB_CLK 139
+#define CAM_CC_SBI_SHIFT_CLK 140
+#define CAM_CC_SFE_0_CLK 141
+#define CAM_CC_SFE_0_CLK_SRC 142
+#define CAM_CC_SFE_0_FAST_AHB_CLK 143
+#define CAM_CC_SFE_0_SHIFT_CLK 144
+#define CAM_CC_SFE_1_CLK 145
+#define CAM_CC_SFE_1_CLK_SRC 146
+#define CAM_CC_SFE_1_FAST_AHB_CLK 147
+#define CAM_CC_SFE_1_SHIFT_CLK 148
+#define CAM_CC_SFE_2_CLK 149
+#define CAM_CC_SFE_2_CLK_SRC 150
+#define CAM_CC_SFE_2_FAST_AHB_CLK 151
+#define CAM_CC_SFE_2_SHIFT_CLK 152
+#define CAM_CC_SLEEP_CLK 153
+#define CAM_CC_SLEEP_CLK_SRC 154
+#define CAM_CC_SLOW_AHB_CLK_SRC 155
+#define CAM_CC_TITAN_TOP_SHIFT_CLK 156
+#define CAM_CC_XO_CLK_SRC 157
+
+/* CAM_CC power domains */
+#define CAM_CC_TITAN_TOP_GDSC 0
+#define CAM_CC_BPS_GDSC 1
+#define CAM_CC_IFE_0_GDSC 2
+#define CAM_CC_IFE_1_GDSC 3
+#define CAM_CC_IFE_2_GDSC 4
+#define CAM_CC_IPE_0_GDSC 5
+#define CAM_CC_SBI_GDSC 6
+#define CAM_CC_SFE_0_GDSC 7
+#define CAM_CC_SFE_1_GDSC 8
+#define CAM_CC_SFE_2_GDSC 9
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_DRV_BCR 1
+#define CAM_CC_ICP_BCR 2
+#define CAM_CC_IFE_0_BCR 3
+#define CAM_CC_IFE_1_BCR 4
+#define CAM_CC_IFE_2_BCR 5
+#define CAM_CC_IPE_0_BCR 6
+#define CAM_CC_QDSS_DEBUG_BCR 7
+#define CAM_CC_SBI_BCR 8
+#define CAM_CC_SFE_0_BCR 9
+#define CAM_CC_SFE_1_BCR 10
+#define CAM_CC_SFE_2_BCR 11
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-videocc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-videocc.h
new file mode 100644
index 0000000..4e3c2d8
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H
+
+#include "qcom,sm8450-videocc.h"
+
+/* SM8650 introduces below new clocks and resets compared to SM8450 */
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_SHIFT_CLK 12
+#define VIDEO_CC_MVS0C_SHIFT_CLK 13
+#define VIDEO_CC_MVS1_SHIFT_CLK 14
+#define VIDEO_CC_MVS1C_SHIFT_CLK 15
+#define VIDEO_CC_XO_CLK_SRC 16
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_XO_CLK_ARES 7
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7779-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7779-clock.h
index 342a60b..e39acdc 100644
--- a/dts/upstream/include/dt-bindings/clock/r8a7779-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/r8a7779-clock.h
@@ -57,5 +57,4 @@
#define R8A7779_CLK_MMC1 30
#define R8A7779_CLK_MMC0 31
-
#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7790-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7790-clock.h
deleted file mode 100644
index c92ff1e..0000000
--- a/dts/upstream/include/dt-bindings/clock/r8a7790-clock.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2013 Ideas On Board SPRL
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
-#define __DT_BINDINGS_CLOCK_R8A7790_H__
-
-/* CPG */
-#define R8A7790_CLK_MAIN 0
-#define R8A7790_CLK_PLL0 1
-#define R8A7790_CLK_PLL1 2
-#define R8A7790_CLK_PLL3 3
-#define R8A7790_CLK_LB 4
-#define R8A7790_CLK_QSPI 5
-#define R8A7790_CLK_SDH 6
-#define R8A7790_CLK_SD0 7
-#define R8A7790_CLK_SD1 8
-#define R8A7790_CLK_Z 9
-#define R8A7790_CLK_RCAN 10
-#define R8A7790_CLK_ADSP 11
-
-/* MSTP0 */
-#define R8A7790_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7790_CLK_VCP1 0
-#define R8A7790_CLK_VCP0 1
-#define R8A7790_CLK_VPC1 2
-#define R8A7790_CLK_VPC0 3
-#define R8A7790_CLK_JPU 6
-#define R8A7790_CLK_SSP1 9
-#define R8A7790_CLK_TMU1 11
-#define R8A7790_CLK_3DG 12
-#define R8A7790_CLK_2DDMAC 15
-#define R8A7790_CLK_FDP1_2 17
-#define R8A7790_CLK_FDP1_1 18
-#define R8A7790_CLK_FDP1_0 19
-#define R8A7790_CLK_TMU3 21
-#define R8A7790_CLK_TMU2 22
-#define R8A7790_CLK_CMT0 24
-#define R8A7790_CLK_TMU0 25
-#define R8A7790_CLK_VSP1_DU1 27
-#define R8A7790_CLK_VSP1_DU0 28
-#define R8A7790_CLK_VSP1_R 30
-#define R8A7790_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7790_CLK_SCIFA2 2
-#define R8A7790_CLK_SCIFA1 3
-#define R8A7790_CLK_SCIFA0 4
-#define R8A7790_CLK_MSIOF2 5
-#define R8A7790_CLK_SCIFB0 6
-#define R8A7790_CLK_SCIFB1 7
-#define R8A7790_CLK_MSIOF1 8
-#define R8A7790_CLK_MSIOF3 15
-#define R8A7790_CLK_SCIFB2 16
-#define R8A7790_CLK_SYS_DMAC1 18
-#define R8A7790_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7790_CLK_IIC2 0
-#define R8A7790_CLK_TPU0 4
-#define R8A7790_CLK_MMCIF1 5
-#define R8A7790_CLK_SCIF2 10
-#define R8A7790_CLK_SDHI3 11
-#define R8A7790_CLK_SDHI2 12
-#define R8A7790_CLK_SDHI1 13
-#define R8A7790_CLK_SDHI0 14
-#define R8A7790_CLK_MMCIF0 15
-#define R8A7790_CLK_IIC0 18
-#define R8A7790_CLK_PCIEC 19
-#define R8A7790_CLK_IIC1 23
-#define R8A7790_CLK_SSUSB 28
-#define R8A7790_CLK_CMT1 29
-#define R8A7790_CLK_USBDMAC0 30
-#define R8A7790_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7790_CLK_IRQC 7
-#define R8A7790_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7790_CLK_AUDIO_DMAC1 1
-#define R8A7790_CLK_AUDIO_DMAC0 2
-#define R8A7790_CLK_ADSP_MOD 6
-#define R8A7790_CLK_THERMAL 22
-#define R8A7790_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7790_CLK_EHCI 3
-#define R8A7790_CLK_HSUSB 4
-#define R8A7790_CLK_HSCIF1 16
-#define R8A7790_CLK_HSCIF0 17
-#define R8A7790_CLK_SCIF1 20
-#define R8A7790_CLK_SCIF0 21
-#define R8A7790_CLK_DU2 22
-#define R8A7790_CLK_DU1 23
-#define R8A7790_CLK_DU0 24
-#define R8A7790_CLK_LVDS1 25
-#define R8A7790_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7790_CLK_MLB 2
-#define R8A7790_CLK_VIN3 8
-#define R8A7790_CLK_VIN2 9
-#define R8A7790_CLK_VIN1 10
-#define R8A7790_CLK_VIN0 11
-#define R8A7790_CLK_ETHERAVB 12
-#define R8A7790_CLK_ETHER 13
-#define R8A7790_CLK_SATA1 14
-#define R8A7790_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7790_CLK_GPIO5 7
-#define R8A7790_CLK_GPIO4 8
-#define R8A7790_CLK_GPIO3 9
-#define R8A7790_CLK_GPIO2 10
-#define R8A7790_CLK_GPIO1 11
-#define R8A7790_CLK_GPIO0 12
-#define R8A7790_CLK_RCAN1 15
-#define R8A7790_CLK_RCAN0 16
-#define R8A7790_CLK_QSPI_MOD 17
-#define R8A7790_CLK_IICDVFS 26
-#define R8A7790_CLK_I2C3 28
-#define R8A7790_CLK_I2C2 29
-#define R8A7790_CLK_I2C1 30
-#define R8A7790_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7790_CLK_SSI_ALL 5
-#define R8A7790_CLK_SSI9 6
-#define R8A7790_CLK_SSI8 7
-#define R8A7790_CLK_SSI7 8
-#define R8A7790_CLK_SSI6 9
-#define R8A7790_CLK_SSI5 10
-#define R8A7790_CLK_SSI4 11
-#define R8A7790_CLK_SSI3 12
-#define R8A7790_CLK_SSI2 13
-#define R8A7790_CLK_SSI1 14
-#define R8A7790_CLK_SSI0 15
-#define R8A7790_CLK_SCU_ALL 17
-#define R8A7790_CLK_SCU_DVC1 18
-#define R8A7790_CLK_SCU_DVC0 19
-#define R8A7790_CLK_SCU_CTU1_MIX1 20
-#define R8A7790_CLK_SCU_CTU0_MIX0 21
-#define R8A7790_CLK_SCU_SRC9 22
-#define R8A7790_CLK_SCU_SRC8 23
-#define R8A7790_CLK_SCU_SRC7 24
-#define R8A7790_CLK_SCU_SRC6 25
-#define R8A7790_CLK_SCU_SRC5 26
-#define R8A7790_CLK_SCU_SRC4 27
-#define R8A7790_CLK_SCU_SRC3 28
-#define R8A7790_CLK_SCU_SRC2 29
-#define R8A7790_CLK_SCU_SRC1 30
-#define R8A7790_CLK_SCU_SRC0 31
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7791-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7791-clock.h
deleted file mode 100644
index bb4f18b..0000000
--- a/dts/upstream/include/dt-bindings/clock/r8a7791-clock.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2013 Ideas On Board SPRL
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
-#define __DT_BINDINGS_CLOCK_R8A7791_H__
-
-/* CPG */
-#define R8A7791_CLK_MAIN 0
-#define R8A7791_CLK_PLL0 1
-#define R8A7791_CLK_PLL1 2
-#define R8A7791_CLK_PLL3 3
-#define R8A7791_CLK_LB 4
-#define R8A7791_CLK_QSPI 5
-#define R8A7791_CLK_SDH 6
-#define R8A7791_CLK_SD0 7
-#define R8A7791_CLK_Z 8
-#define R8A7791_CLK_RCAN 9
-#define R8A7791_CLK_ADSP 10
-
-/* MSTP0 */
-#define R8A7791_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7791_CLK_VCP0 1
-#define R8A7791_CLK_VPC0 3
-#define R8A7791_CLK_JPU 6
-#define R8A7791_CLK_SSP1 9
-#define R8A7791_CLK_TMU1 11
-#define R8A7791_CLK_3DG 12
-#define R8A7791_CLK_2DDMAC 15
-#define R8A7791_CLK_FDP1_1 18
-#define R8A7791_CLK_FDP1_0 19
-#define R8A7791_CLK_TMU3 21
-#define R8A7791_CLK_TMU2 22
-#define R8A7791_CLK_CMT0 24
-#define R8A7791_CLK_TMU0 25
-#define R8A7791_CLK_VSP1_DU1 27
-#define R8A7791_CLK_VSP1_DU0 28
-#define R8A7791_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7791_CLK_SCIFA2 2
-#define R8A7791_CLK_SCIFA1 3
-#define R8A7791_CLK_SCIFA0 4
-#define R8A7791_CLK_MSIOF2 5
-#define R8A7791_CLK_SCIFB0 6
-#define R8A7791_CLK_SCIFB1 7
-#define R8A7791_CLK_MSIOF1 8
-#define R8A7791_CLK_SCIFB2 16
-#define R8A7791_CLK_SYS_DMAC1 18
-#define R8A7791_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7791_CLK_TPU0 4
-#define R8A7791_CLK_SDHI2 11
-#define R8A7791_CLK_SDHI1 12
-#define R8A7791_CLK_SDHI0 14
-#define R8A7791_CLK_MMCIF0 15
-#define R8A7791_CLK_IIC0 18
-#define R8A7791_CLK_PCIEC 19
-#define R8A7791_CLK_IIC1 23
-#define R8A7791_CLK_SSUSB 28
-#define R8A7791_CLK_CMT1 29
-#define R8A7791_CLK_USBDMAC0 30
-#define R8A7791_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7791_CLK_IRQC 7
-#define R8A7791_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7791_CLK_AUDIO_DMAC1 1
-#define R8A7791_CLK_AUDIO_DMAC0 2
-#define R8A7791_CLK_ADSP_MOD 6
-#define R8A7791_CLK_THERMAL 22
-#define R8A7791_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7791_CLK_EHCI 3
-#define R8A7791_CLK_HSUSB 4
-#define R8A7791_CLK_HSCIF2 13
-#define R8A7791_CLK_SCIF5 14
-#define R8A7791_CLK_SCIF4 15
-#define R8A7791_CLK_HSCIF1 16
-#define R8A7791_CLK_HSCIF0 17
-#define R8A7791_CLK_SCIF3 18
-#define R8A7791_CLK_SCIF2 19
-#define R8A7791_CLK_SCIF1 20
-#define R8A7791_CLK_SCIF0 21
-#define R8A7791_CLK_DU1 23
-#define R8A7791_CLK_DU0 24
-#define R8A7791_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7791_CLK_IPMMU_SGX 0
-#define R8A7791_CLK_MLB 2
-#define R8A7791_CLK_VIN2 9
-#define R8A7791_CLK_VIN1 10
-#define R8A7791_CLK_VIN0 11
-#define R8A7791_CLK_ETHERAVB 12
-#define R8A7791_CLK_ETHER 13
-#define R8A7791_CLK_SATA1 14
-#define R8A7791_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7791_CLK_GYROADC 1
-#define R8A7791_CLK_GPIO7 4
-#define R8A7791_CLK_GPIO6 5
-#define R8A7791_CLK_GPIO5 7
-#define R8A7791_CLK_GPIO4 8
-#define R8A7791_CLK_GPIO3 9
-#define R8A7791_CLK_GPIO2 10
-#define R8A7791_CLK_GPIO1 11
-#define R8A7791_CLK_GPIO0 12
-#define R8A7791_CLK_RCAN1 15
-#define R8A7791_CLK_RCAN0 16
-#define R8A7791_CLK_QSPI_MOD 17
-#define R8A7791_CLK_I2C5 25
-#define R8A7791_CLK_IICDVFS 26
-#define R8A7791_CLK_I2C4 27
-#define R8A7791_CLK_I2C3 28
-#define R8A7791_CLK_I2C2 29
-#define R8A7791_CLK_I2C1 30
-#define R8A7791_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7791_CLK_SSI_ALL 5
-#define R8A7791_CLK_SSI9 6
-#define R8A7791_CLK_SSI8 7
-#define R8A7791_CLK_SSI7 8
-#define R8A7791_CLK_SSI6 9
-#define R8A7791_CLK_SSI5 10
-#define R8A7791_CLK_SSI4 11
-#define R8A7791_CLK_SSI3 12
-#define R8A7791_CLK_SSI2 13
-#define R8A7791_CLK_SSI1 14
-#define R8A7791_CLK_SSI0 15
-#define R8A7791_CLK_SCU_ALL 17
-#define R8A7791_CLK_SCU_DVC1 18
-#define R8A7791_CLK_SCU_DVC0 19
-#define R8A7791_CLK_SCU_CTU1_MIX1 20
-#define R8A7791_CLK_SCU_CTU0_MIX0 21
-#define R8A7791_CLK_SCU_SRC9 22
-#define R8A7791_CLK_SCU_SRC8 23
-#define R8A7791_CLK_SCU_SRC7 24
-#define R8A7791_CLK_SCU_SRC6 25
-#define R8A7791_CLK_SCU_SRC5 26
-#define R8A7791_CLK_SCU_SRC4 27
-#define R8A7791_CLK_SCU_SRC3 28
-#define R8A7791_CLK_SCU_SRC2 29
-#define R8A7791_CLK_SCU_SRC1 30
-#define R8A7791_CLK_SCU_SRC0 31
-
-/* MSTP11 */
-#define R8A7791_CLK_SCIFA3 6
-#define R8A7791_CLK_SCIFA4 7
-#define R8A7791_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7792-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7792-clock.h
deleted file mode 100644
index 2948d9ce..0000000
--- a/dts/upstream/include/dt-bindings/clock/r8a7792-clock.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
-#define __DT_BINDINGS_CLOCK_R8A7792_H__
-
-/* CPG */
-#define R8A7792_CLK_MAIN 0
-#define R8A7792_CLK_PLL0 1
-#define R8A7792_CLK_PLL1 2
-#define R8A7792_CLK_PLL3 3
-#define R8A7792_CLK_LB 4
-#define R8A7792_CLK_QSPI 5
-
-/* MSTP0 */
-#define R8A7792_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7792_CLK_JPU 6
-#define R8A7792_CLK_TMU1 11
-#define R8A7792_CLK_TMU3 21
-#define R8A7792_CLK_TMU2 22
-#define R8A7792_CLK_CMT0 24
-#define R8A7792_CLK_TMU0 25
-#define R8A7792_CLK_VSP1DU1 27
-#define R8A7792_CLK_VSP1DU0 28
-#define R8A7792_CLK_VSP1_SY 31
-
-/* MSTP2 */
-#define R8A7792_CLK_MSIOF1 8
-#define R8A7792_CLK_SYS_DMAC1 18
-#define R8A7792_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7792_CLK_TPU0 4
-#define R8A7792_CLK_SDHI0 14
-#define R8A7792_CLK_CMT1 29
-
-/* MSTP4 */
-#define R8A7792_CLK_IRQC 7
-#define R8A7792_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7792_CLK_AUDIO_DMAC0 2
-#define R8A7792_CLK_THERMAL 22
-#define R8A7792_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7792_CLK_HSCIF1 16
-#define R8A7792_CLK_HSCIF0 17
-#define R8A7792_CLK_SCIF3 18
-#define R8A7792_CLK_SCIF2 19
-#define R8A7792_CLK_SCIF1 20
-#define R8A7792_CLK_SCIF0 21
-#define R8A7792_CLK_DU1 23
-#define R8A7792_CLK_DU0 24
-
-/* MSTP8 */
-#define R8A7792_CLK_VIN5 4
-#define R8A7792_CLK_VIN4 5
-#define R8A7792_CLK_VIN3 8
-#define R8A7792_CLK_VIN2 9
-#define R8A7792_CLK_VIN1 10
-#define R8A7792_CLK_VIN0 11
-#define R8A7792_CLK_ETHERAVB 12
-
-/* MSTP9 */
-#define R8A7792_CLK_GPIO7 4
-#define R8A7792_CLK_GPIO6 5
-#define R8A7792_CLK_GPIO5 7
-#define R8A7792_CLK_GPIO4 8
-#define R8A7792_CLK_GPIO3 9
-#define R8A7792_CLK_GPIO2 10
-#define R8A7792_CLK_GPIO1 11
-#define R8A7792_CLK_GPIO0 12
-#define R8A7792_CLK_GPIO11 13
-#define R8A7792_CLK_GPIO10 14
-#define R8A7792_CLK_CAN1 15
-#define R8A7792_CLK_CAN0 16
-#define R8A7792_CLK_QSPI_MOD 17
-#define R8A7792_CLK_GPIO9 19
-#define R8A7792_CLK_GPIO8 21
-#define R8A7792_CLK_I2C5 25
-#define R8A7792_CLK_IICDVFS 26
-#define R8A7792_CLK_I2C4 27
-#define R8A7792_CLK_I2C3 28
-#define R8A7792_CLK_I2C2 29
-#define R8A7792_CLK_I2C1 30
-#define R8A7792_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7792_CLK_SSI_ALL 5
-#define R8A7792_CLK_SSI4 11
-#define R8A7792_CLK_SSI3 12
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7793-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7793-clock.h
deleted file mode 100644
index 49c66d8..0000000
--- a/dts/upstream/include/dt-bindings/clock/r8a7793-clock.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0
- *
- * r8a7793 clock definition
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
-#define __DT_BINDINGS_CLOCK_R8A7793_H__
-
-/* CPG */
-#define R8A7793_CLK_MAIN 0
-#define R8A7793_CLK_PLL0 1
-#define R8A7793_CLK_PLL1 2
-#define R8A7793_CLK_PLL3 3
-#define R8A7793_CLK_LB 4
-#define R8A7793_CLK_QSPI 5
-#define R8A7793_CLK_SDH 6
-#define R8A7793_CLK_SD0 7
-#define R8A7793_CLK_Z 8
-#define R8A7793_CLK_RCAN 9
-#define R8A7793_CLK_ADSP 10
-
-/* MSTP0 */
-#define R8A7793_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7793_CLK_VCP0 1
-#define R8A7793_CLK_VPC0 3
-#define R8A7793_CLK_SSP1 9
-#define R8A7793_CLK_TMU1 11
-#define R8A7793_CLK_3DG 12
-#define R8A7793_CLK_2DDMAC 15
-#define R8A7793_CLK_FDP1_1 18
-#define R8A7793_CLK_FDP1_0 19
-#define R8A7793_CLK_TMU3 21
-#define R8A7793_CLK_TMU2 22
-#define R8A7793_CLK_CMT0 24
-#define R8A7793_CLK_TMU0 25
-#define R8A7793_CLK_VSP1_DU1 27
-#define R8A7793_CLK_VSP1_DU0 28
-#define R8A7793_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7793_CLK_SCIFA2 2
-#define R8A7793_CLK_SCIFA1 3
-#define R8A7793_CLK_SCIFA0 4
-#define R8A7793_CLK_MSIOF2 5
-#define R8A7793_CLK_SCIFB0 6
-#define R8A7793_CLK_SCIFB1 7
-#define R8A7793_CLK_MSIOF1 8
-#define R8A7793_CLK_SCIFB2 16
-#define R8A7793_CLK_SYS_DMAC1 18
-#define R8A7793_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7793_CLK_TPU0 4
-#define R8A7793_CLK_SDHI2 11
-#define R8A7793_CLK_SDHI1 12
-#define R8A7793_CLK_SDHI0 14
-#define R8A7793_CLK_MMCIF0 15
-#define R8A7793_CLK_IIC0 18
-#define R8A7793_CLK_PCIEC 19
-#define R8A7793_CLK_IIC1 23
-#define R8A7793_CLK_SSUSB 28
-#define R8A7793_CLK_CMT1 29
-#define R8A7793_CLK_USBDMAC0 30
-#define R8A7793_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7793_CLK_IRQC 7
-#define R8A7793_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7793_CLK_AUDIO_DMAC1 1
-#define R8A7793_CLK_AUDIO_DMAC0 2
-#define R8A7793_CLK_ADSP_MOD 6
-#define R8A7793_CLK_THERMAL 22
-#define R8A7793_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7793_CLK_EHCI 3
-#define R8A7793_CLK_HSUSB 4
-#define R8A7793_CLK_HSCIF2 13
-#define R8A7793_CLK_SCIF5 14
-#define R8A7793_CLK_SCIF4 15
-#define R8A7793_CLK_HSCIF1 16
-#define R8A7793_CLK_HSCIF0 17
-#define R8A7793_CLK_SCIF3 18
-#define R8A7793_CLK_SCIF2 19
-#define R8A7793_CLK_SCIF1 20
-#define R8A7793_CLK_SCIF0 21
-#define R8A7793_CLK_DU1 23
-#define R8A7793_CLK_DU0 24
-#define R8A7793_CLK_LVDS0 26
-
-/* MSTP8 */
-#define R8A7793_CLK_IPMMU_SGX 0
-#define R8A7793_CLK_VIN2 9
-#define R8A7793_CLK_VIN1 10
-#define R8A7793_CLK_VIN0 11
-#define R8A7793_CLK_ETHER 13
-#define R8A7793_CLK_SATA1 14
-#define R8A7793_CLK_SATA0 15
-
-/* MSTP9 */
-#define R8A7793_CLK_GPIO7 4
-#define R8A7793_CLK_GPIO6 5
-#define R8A7793_CLK_GPIO5 7
-#define R8A7793_CLK_GPIO4 8
-#define R8A7793_CLK_GPIO3 9
-#define R8A7793_CLK_GPIO2 10
-#define R8A7793_CLK_GPIO1 11
-#define R8A7793_CLK_GPIO0 12
-#define R8A7793_CLK_RCAN1 15
-#define R8A7793_CLK_RCAN0 16
-#define R8A7793_CLK_QSPI_MOD 17
-#define R8A7793_CLK_I2C5 25
-#define R8A7793_CLK_IICDVFS 26
-#define R8A7793_CLK_I2C4 27
-#define R8A7793_CLK_I2C3 28
-#define R8A7793_CLK_I2C2 29
-#define R8A7793_CLK_I2C1 30
-#define R8A7793_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7793_CLK_SSI_ALL 5
-#define R8A7793_CLK_SSI9 6
-#define R8A7793_CLK_SSI8 7
-#define R8A7793_CLK_SSI7 8
-#define R8A7793_CLK_SSI6 9
-#define R8A7793_CLK_SSI5 10
-#define R8A7793_CLK_SSI4 11
-#define R8A7793_CLK_SSI3 12
-#define R8A7793_CLK_SSI2 13
-#define R8A7793_CLK_SSI1 14
-#define R8A7793_CLK_SSI0 15
-#define R8A7793_CLK_SCU_ALL 17
-#define R8A7793_CLK_SCU_DVC1 18
-#define R8A7793_CLK_SCU_DVC0 19
-#define R8A7793_CLK_SCU_CTU1_MIX1 20
-#define R8A7793_CLK_SCU_CTU0_MIX0 21
-#define R8A7793_CLK_SCU_SRC9 22
-#define R8A7793_CLK_SCU_SRC8 23
-#define R8A7793_CLK_SCU_SRC7 24
-#define R8A7793_CLK_SCU_SRC6 25
-#define R8A7793_CLK_SCU_SRC5 26
-#define R8A7793_CLK_SCU_SRC4 27
-#define R8A7793_CLK_SCU_SRC3 28
-#define R8A7793_CLK_SCU_SRC2 29
-#define R8A7793_CLK_SCU_SRC1 30
-#define R8A7793_CLK_SCU_SRC0 31
-
-/* MSTP11 */
-#define R8A7793_CLK_SCIFA3 6
-#define R8A7793_CLK_SCIFA4 7
-#define R8A7793_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/r8a7794-clock.h b/dts/upstream/include/dt-bindings/clock/r8a7794-clock.h
deleted file mode 100644
index 649f005..0000000
--- a/dts/upstream/include/dt-bindings/clock/r8a7794-clock.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2014 Renesas Electronics Corporation
- * Copyright 2013 Ideas On Board SPRL
- */
-
-#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
-#define __DT_BINDINGS_CLOCK_R8A7794_H__
-
-/* CPG */
-#define R8A7794_CLK_MAIN 0
-#define R8A7794_CLK_PLL0 1
-#define R8A7794_CLK_PLL1 2
-#define R8A7794_CLK_PLL3 3
-#define R8A7794_CLK_LB 4
-#define R8A7794_CLK_QSPI 5
-#define R8A7794_CLK_SDH 6
-#define R8A7794_CLK_SD0 7
-#define R8A7794_CLK_RCAN 8
-
-/* MSTP0 */
-#define R8A7794_CLK_MSIOF0 0
-
-/* MSTP1 */
-#define R8A7794_CLK_VCP0 1
-#define R8A7794_CLK_VPC0 3
-#define R8A7794_CLK_TMU1 11
-#define R8A7794_CLK_3DG 12
-#define R8A7794_CLK_2DDMAC 15
-#define R8A7794_CLK_FDP1_0 19
-#define R8A7794_CLK_TMU3 21
-#define R8A7794_CLK_TMU2 22
-#define R8A7794_CLK_CMT0 24
-#define R8A7794_CLK_TMU0 25
-#define R8A7794_CLK_VSP1_DU0 28
-#define R8A7794_CLK_VSP1_S 31
-
-/* MSTP2 */
-#define R8A7794_CLK_SCIFA2 2
-#define R8A7794_CLK_SCIFA1 3
-#define R8A7794_CLK_SCIFA0 4
-#define R8A7794_CLK_MSIOF2 5
-#define R8A7794_CLK_SCIFB0 6
-#define R8A7794_CLK_SCIFB1 7
-#define R8A7794_CLK_MSIOF1 8
-#define R8A7794_CLK_SCIFB2 16
-#define R8A7794_CLK_SYS_DMAC1 18
-#define R8A7794_CLK_SYS_DMAC0 19
-
-/* MSTP3 */
-#define R8A7794_CLK_SDHI2 11
-#define R8A7794_CLK_SDHI1 12
-#define R8A7794_CLK_SDHI0 14
-#define R8A7794_CLK_MMCIF0 15
-#define R8A7794_CLK_IIC0 18
-#define R8A7794_CLK_IIC1 23
-#define R8A7794_CLK_CMT1 29
-#define R8A7794_CLK_USBDMAC0 30
-#define R8A7794_CLK_USBDMAC1 31
-
-/* MSTP4 */
-#define R8A7794_CLK_IRQC 7
-#define R8A7794_CLK_INTC_SYS 8
-
-/* MSTP5 */
-#define R8A7794_CLK_AUDIO_DMAC0 2
-#define R8A7794_CLK_PWM 23
-
-/* MSTP7 */
-#define R8A7794_CLK_EHCI 3
-#define R8A7794_CLK_HSUSB 4
-#define R8A7794_CLK_HSCIF2 13
-#define R8A7794_CLK_SCIF5 14
-#define R8A7794_CLK_SCIF4 15
-#define R8A7794_CLK_HSCIF1 16
-#define R8A7794_CLK_HSCIF0 17
-#define R8A7794_CLK_SCIF3 18
-#define R8A7794_CLK_SCIF2 19
-#define R8A7794_CLK_SCIF1 20
-#define R8A7794_CLK_SCIF0 21
-#define R8A7794_CLK_DU1 23
-#define R8A7794_CLK_DU0 24
-
-/* MSTP8 */
-#define R8A7794_CLK_VIN1 10
-#define R8A7794_CLK_VIN0 11
-#define R8A7794_CLK_ETHERAVB 12
-#define R8A7794_CLK_ETHER 13
-
-/* MSTP9 */
-#define R8A7794_CLK_GPIO6 5
-#define R8A7794_CLK_GPIO5 7
-#define R8A7794_CLK_GPIO4 8
-#define R8A7794_CLK_GPIO3 9
-#define R8A7794_CLK_GPIO2 10
-#define R8A7794_CLK_GPIO1 11
-#define R8A7794_CLK_GPIO0 12
-#define R8A7794_CLK_RCAN1 15
-#define R8A7794_CLK_RCAN0 16
-#define R8A7794_CLK_QSPI_MOD 17
-#define R8A7794_CLK_I2C5 25
-#define R8A7794_CLK_I2C4 27
-#define R8A7794_CLK_I2C3 28
-#define R8A7794_CLK_I2C2 29
-#define R8A7794_CLK_I2C1 30
-#define R8A7794_CLK_I2C0 31
-
-/* MSTP10 */
-#define R8A7794_CLK_SSI_ALL 5
-#define R8A7794_CLK_SSI9 6
-#define R8A7794_CLK_SSI8 7
-#define R8A7794_CLK_SSI7 8
-#define R8A7794_CLK_SSI6 9
-#define R8A7794_CLK_SSI5 10
-#define R8A7794_CLK_SSI4 11
-#define R8A7794_CLK_SSI3 12
-#define R8A7794_CLK_SSI2 13
-#define R8A7794_CLK_SSI1 14
-#define R8A7794_CLK_SSI0 15
-#define R8A7794_CLK_SCU_ALL 17
-#define R8A7794_CLK_SCU_DVC1 18
-#define R8A7794_CLK_SCU_DVC0 19
-#define R8A7794_CLK_SCU_CTU1_MIX1 20
-#define R8A7794_CLK_SCU_CTU0_MIX0 21
-#define R8A7794_CLK_SCU_SRC6 25
-#define R8A7794_CLK_SCU_SRC5 26
-#define R8A7794_CLK_SCU_SRC4 27
-#define R8A7794_CLK_SCU_SRC3 28
-#define R8A7794_CLK_SCU_SRC2 29
-#define R8A7794_CLK_SCU_SRC1 30
-
-/* MSTP11 */
-#define R8A7794_CLK_SCIFA3 6
-#define R8A7794_CLK_SCIFA4 7
-#define R8A7794_CLK_SCIFA5 8
-
-#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/rk3128-cru.h b/dts/upstream/include/dt-bindings/clock/rk3128-cru.h
index 6a47825..b609fcf 100644
--- a/dts/upstream/include/dt-bindings/clock/rk3128-cru.h
+++ b/dts/upstream/include/dt-bindings/clock/rk3128-cru.h
@@ -116,6 +116,7 @@
#define PCLK_GMAC 367
#define PCLK_PMU_PRE 368
#define PCLK_SIM_CARD 369
+#define PCLK_MIPIPHY 370
/* hclk gates */
#define HCLK_SPDIF 440
@@ -143,8 +144,7 @@
#define HCLK_TSP 475
#define HCLK_CRYPTO 476
#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
+#define HCLK_SFC 479
/* soft-reset indices */
#define SRST_CORE0_PO 0
diff --git a/dts/upstream/include/dt-bindings/clock/rk3188-cru-common.h b/dts/upstream/include/dt-bindings/clock/rk3188-cru-common.h
index afad906..01e14ab 100644
--- a/dts/upstream/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/dts/upstream/include/dt-bindings/clock/rk3188-cru-common.h
@@ -132,8 +132,6 @@
#define HCLK_VDPU 472
#define HCLK_HDMI 473
-#define CLK_NR_CLKS (HCLK_HDMI + 1)
-
/* soft-reset indices */
#define SRST_MCORE 2
#define SRST_CORE0 3
diff --git a/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-clkgen.h b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
new file mode 100644
index 0000000..84f7857
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-clkgen.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__
+
+#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
+#define DIV_CLK_MPLL_AXI_DDR_0 1
+#define DIV_CLK_FPLL_DDR01_1 2
+#define DIV_CLK_FPLL_DDR23_1 3
+#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4
+#define DIV_CLK_FPLL_50M_A53 5
+#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6
+#define DIV_CLK_FPLL_UART_500M 7
+#define DIV_CLK_FPLL_AHB_LPC 8
+#define DIV_CLK_FPLL_EFUSE 9
+#define DIV_CLK_FPLL_TX_ETH0 10
+#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11
+#define DIV_CLK_FPLL_REF_ETH0 12
+#define DIV_CLK_FPLL_EMMC 13
+#define DIV_CLK_FPLL_SD 14
+#define DIV_CLK_FPLL_TOP_AXI0 15
+#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16
+#define DIV_CLK_FPLL_AXI_DDR_1 17
+#define DIV_CLK_FPLL_DIV_TIMER1 18
+#define DIV_CLK_FPLL_DIV_TIMER2 19
+#define DIV_CLK_FPLL_DIV_TIMER3 20
+#define DIV_CLK_FPLL_DIV_TIMER4 21
+#define DIV_CLK_FPLL_DIV_TIMER5 22
+#define DIV_CLK_FPLL_DIV_TIMER6 23
+#define DIV_CLK_FPLL_DIV_TIMER7 24
+#define DIV_CLK_FPLL_DIV_TIMER8 25
+#define DIV_CLK_FPLL_100K_EMMC 26
+#define DIV_CLK_FPLL_100K_SD 27
+#define DIV_CLK_FPLL_GPIO_DB 28
+#define DIV_CLK_DPLL0_DDR01_0 29
+#define DIV_CLK_DPLL1_DDR23_0 30
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV0 31
+#define GATE_CLK_AXI_DDR_DIV0 32
+
+#define GATE_CLK_RP_CPU_NORMAL_DIV1 33
+#define GATE_CLK_A53_50M 34
+#define GATE_CLK_TOP_RP_CMN_DIV2 35
+#define GATE_CLK_HSDMA 36
+#define GATE_CLK_EMMC_100M 37
+#define GATE_CLK_SD_100M 38
+#define GATE_CLK_TX_ETH0 39
+#define GATE_CLK_PTP_REF_I_ETH0 40
+#define GATE_CLK_REF_ETH0 41
+#define GATE_CLK_UART_500M 42
+#define GATE_CLK_EFUSE 43
+
+#define GATE_CLK_AHB_LPC 44
+#define GATE_CLK_AHB_ROM 45
+#define GATE_CLK_AHB_SF 46
+
+#define GATE_CLK_APB_UART 47
+#define GATE_CLK_APB_TIMER 48
+#define GATE_CLK_APB_EFUSE 49
+#define GATE_CLK_APB_GPIO 50
+#define GATE_CLK_APB_GPIO_INTR 51
+#define GATE_CLK_APB_SPI 52
+#define GATE_CLK_APB_I2C 53
+#define GATE_CLK_APB_WDT 54
+#define GATE_CLK_APB_PWM 55
+#define GATE_CLK_APB_RTC 56
+
+#define GATE_CLK_AXI_PCIE0 57
+#define GATE_CLK_AXI_PCIE1 58
+#define GATE_CLK_SYSDMA_AXI 59
+#define GATE_CLK_AXI_DBG_I2C 60
+#define GATE_CLK_AXI_SRAM 61
+#define GATE_CLK_AXI_ETH0 62
+#define GATE_CLK_AXI_EMMC 63
+#define GATE_CLK_AXI_SD 64
+#define GATE_CLK_TOP_AXI0 65
+#define GATE_CLK_TOP_AXI_HSPERI 66
+
+#define GATE_CLK_TIMER1 67
+#define GATE_CLK_TIMER2 68
+#define GATE_CLK_TIMER3 69
+#define GATE_CLK_TIMER4 70
+#define GATE_CLK_TIMER5 71
+#define GATE_CLK_TIMER6 72
+#define GATE_CLK_TIMER7 73
+#define GATE_CLK_TIMER8 74
+#define GATE_CLK_100K_EMMC 75
+#define GATE_CLK_100K_SD 76
+#define GATE_CLK_GPIO_DB 77
+
+#define GATE_CLK_AXI_DDR_DIV1 78
+#define GATE_CLK_DDR01_DIV1 79
+#define GATE_CLK_DDR23_DIV1 80
+
+#define GATE_CLK_DDR01_DIV0 81
+#define GATE_CLK_DDR23_DIV0 82
+
+#define GATE_CLK_DDR01 83
+#define GATE_CLK_DDR23 84
+#define GATE_CLK_RP_CPU_NORMAL 85
+#define GATE_CLK_AXI_DDR 86
+
+#define MUX_CLK_DDR01 87
+#define MUX_CLK_DDR23 88
+#define MUX_CLK_RP_CPU_NORMAL 89
+#define MUX_CLK_AXI_DDR 90
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-pll.h b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-pll.h
new file mode 100644
index 0000000..2d519b3
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-pll.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_PLL_H__
+
+#define MPLL_CLK 0
+#define FPLL_CLK 1
+#define DPLL0_CLK 2
+#define DPLL1_CLK 3
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_PLL_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-rpgate.h b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-rpgate.h
new file mode 100644
index 0000000..8b4522d
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/sophgo,sg2042-rpgate.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+#define __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__
+
+#define GATE_CLK_RXU0 0
+#define GATE_CLK_RXU1 1
+#define GATE_CLK_RXU2 2
+#define GATE_CLK_RXU3 3
+#define GATE_CLK_RXU4 4
+#define GATE_CLK_RXU5 5
+#define GATE_CLK_RXU6 6
+#define GATE_CLK_RXU7 7
+#define GATE_CLK_RXU8 8
+#define GATE_CLK_RXU9 9
+#define GATE_CLK_RXU10 10
+#define GATE_CLK_RXU11 11
+#define GATE_CLK_RXU12 12
+#define GATE_CLK_RXU13 13
+#define GATE_CLK_RXU14 14
+#define GATE_CLK_RXU15 15
+#define GATE_CLK_RXU16 16
+#define GATE_CLK_RXU17 17
+#define GATE_CLK_RXU18 18
+#define GATE_CLK_RXU19 19
+#define GATE_CLK_RXU20 20
+#define GATE_CLK_RXU21 21
+#define GATE_CLK_RXU22 22
+#define GATE_CLK_RXU23 23
+#define GATE_CLK_RXU24 24
+#define GATE_CLK_RXU25 25
+#define GATE_CLK_RXU26 26
+#define GATE_CLK_RXU27 27
+#define GATE_CLK_RXU28 28
+#define GATE_CLK_RXU29 29
+#define GATE_CLK_RXU30 30
+#define GATE_CLK_RXU31 31
+#define GATE_CLK_MP0 32
+#define GATE_CLK_MP1 33
+#define GATE_CLK_MP2 34
+#define GATE_CLK_MP3 35
+#define GATE_CLK_MP4 36
+#define GATE_CLK_MP5 37
+#define GATE_CLK_MP6 38
+#define GATE_CLK_MP7 39
+#define GATE_CLK_MP8 40
+#define GATE_CLK_MP9 41
+#define GATE_CLK_MP10 42
+#define GATE_CLK_MP11 43
+#define GATE_CLK_MP12 44
+#define GATE_CLK_MP13 45
+#define GATE_CLK_MP14 46
+#define GATE_CLK_MP15 47
+
+#endif /* __DT_BINDINGS_SOPHGO_SG2042_RPGATE_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/sun50i-h616-ccu.h b/dts/upstream/include/dt-bindings/clock/sun50i-h616-ccu.h
index 6f8f01e..ebb146a 100644
--- a/dts/upstream/include/dt-bindings/clock/sun50i-h616-ccu.h
+++ b/dts/upstream/include/dt-bindings/clock/sun50i-h616-ccu.h
@@ -112,5 +112,6 @@
#define CLK_HDCP 126
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
+#define CLK_BUS_GPADC 129
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
diff --git a/dts/upstream/include/dt-bindings/clock/thead,th1520-clk-ap.h b/dts/upstream/include/dt-bindings/clock/thead,th1520-clk-ap.h
new file mode 100644
index 0000000..a199784
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
+ * Authors: Yangtao Li <frank.li@vivo.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_TH1520_H_
+#define _DT_BINDINGS_CLK_TH1520_H_
+
+#define CLK_CPU_PLL0 0
+#define CLK_CPU_PLL1 1
+#define CLK_GMAC_PLL 2
+#define CLK_VIDEO_PLL 3
+#define CLK_DPU0_PLL 4
+#define CLK_DPU1_PLL 5
+#define CLK_TEE_PLL 6
+#define CLK_C910_I0 7
+#define CLK_C910 8
+#define CLK_BROM 9
+#define CLK_BMU 10
+#define CLK_AHB2_CPUSYS_HCLK 11
+#define CLK_APB3_CPUSYS_PCLK 12
+#define CLK_AXI4_CPUSYS2_ACLK 13
+#define CLK_AON2CPU_A2X 14
+#define CLK_X2X_CPUSYS 15
+#define CLK_AXI_ACLK 16
+#define CLK_CPU2AON_X2H 17
+#define CLK_PERI_AHB_HCLK 18
+#define CLK_CPU2PERI_X2H 19
+#define CLK_PERI_APB_PCLK 20
+#define CLK_PERI2APB_PCLK 21
+#define CLK_PERISYS_APB1_HCLK 22
+#define CLK_PERISYS_APB2_HCLK 23
+#define CLK_PERISYS_APB3_HCLK 24
+#define CLK_PERISYS_APB4_HCLK 25
+#define CLK_OSC12M 26
+#define CLK_OUT1 27
+#define CLK_OUT2 28
+#define CLK_OUT3 29
+#define CLK_OUT4 30
+#define CLK_APB_PCLK 31
+#define CLK_NPU 32
+#define CLK_NPU_AXI 33
+#define CLK_VI 34
+#define CLK_VI_AHB 35
+#define CLK_VO_AXI 36
+#define CLK_VP_APB 37
+#define CLK_VP_AXI 38
+#define CLK_CPU2VP 39
+#define CLK_VENC 40
+#define CLK_DPU0 41
+#define CLK_DPU1 42
+#define CLK_EMMC_SDIO 43
+#define CLK_GMAC1 44
+#define CLK_PADCTRL1 45
+#define CLK_DSMART 46
+#define CLK_PADCTRL0 47
+#define CLK_GMAC_AXI 48
+#define CLK_GPIO3 49
+#define CLK_GMAC0 50
+#define CLK_PWM 51
+#define CLK_QSPI0 52
+#define CLK_QSPI1 53
+#define CLK_SPI 54
+#define CLK_UART0_PCLK 55
+#define CLK_UART1_PCLK 56
+#define CLK_UART2_PCLK 57
+#define CLK_UART3_PCLK 58
+#define CLK_UART4_PCLK 59
+#define CLK_UART5_PCLK 60
+#define CLK_GPIO0 61
+#define CLK_GPIO1 62
+#define CLK_GPIO2 63
+#define CLK_I2C0 64
+#define CLK_I2C1 65
+#define CLK_I2C2 66
+#define CLK_I2C3 67
+#define CLK_I2C4 68
+#define CLK_I2C5 69
+#define CLK_SPINLOCK 70
+#define CLK_DMA 71
+#define CLK_MBOX0 72
+#define CLK_MBOX1 73
+#define CLK_MBOX2 74
+#define CLK_MBOX3 75
+#define CLK_WDT0 76
+#define CLK_WDT1 77
+#define CLK_TIMER0 78
+#define CLK_TIMER1 79
+#define CLK_SRAM0 80
+#define CLK_SRAM1 81
+#define CLK_SRAM2 82
+#define CLK_SRAM3 83
+#define CLK_PLL_GMAC_100M 84
+#define CLK_UART_SCLK 85
+#endif
diff --git a/dts/upstream/include/dt-bindings/i3c/i3c.h b/dts/upstream/include/dt-bindings/i3c/i3c.h
new file mode 100644
index 0000000..3734392
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/i3c/i3c.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef _DT_BINDINGS_I3C_I3C_H
+#define _DT_BINDINGS_I3C_I3C_H
+
+#define I2C_FM (1 << 4)
+#define I2C_FM_PLUS (0 << 4)
+
+#define I2C_FILTER (0 << 5)
+#define I2C_NO_FILTER_HIGH_FREQUENCY (1 << 5)
+#define I2C_NO_FILTER_LOW_FREQUENCY (2 << 5)
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6357-auxadc.h b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6357-auxadc.h
new file mode 100644
index 0000000..03ebb1d
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6357-auxadc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
+
+/* ADC Channel Index */
+#define MT6357_AUXADC_BATADC 0
+#define MT6357_AUXADC_ISENSE 1
+#define MT6357_AUXADC_VCDT 2
+#define MT6357_AUXADC_BAT_TEMP 3
+#define MT6357_AUXADC_CHIP_TEMP 4
+#define MT6357_AUXADC_ACCDET 5
+#define MT6357_AUXADC_VDCXO 6
+#define MT6357_AUXADC_TSX_TEMP 7
+#define MT6357_AUXADC_HPOFS_CAL 8
+#define MT6357_AUXADC_DCXO_TEMP 9
+#define MT6357_AUXADC_VCORE_TEMP 10
+#define MT6357_AUXADC_VPROC_TEMP 11
+#define MT6357_AUXADC_VBAT 12
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6358-auxadc.h b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6358-auxadc.h
new file mode 100644
index 0000000..efa0839
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6358-auxadc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H
+
+/* ADC Channel Index */
+#define MT6358_AUXADC_BATADC 0
+#define MT6358_AUXADC_VCDT 1
+#define MT6358_AUXADC_BAT_TEMP 2
+#define MT6358_AUXADC_CHIP_TEMP 3
+#define MT6358_AUXADC_ACCDET 4
+#define MT6358_AUXADC_VDCXO 5
+#define MT6358_AUXADC_TSX_TEMP 6
+#define MT6358_AUXADC_HPOFS_CAL 7
+#define MT6358_AUXADC_DCXO_TEMP 8
+#define MT6358_AUXADC_VBIF 9
+#define MT6358_AUXADC_VCORE_TEMP 10
+#define MT6358_AUXADC_VPROC_TEMP 11
+#define MT6358_AUXADC_VGPU_TEMP 12
+#define MT6358_AUXADC_VBAT 13
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6359-auxadc.h b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6359-auxadc.h
new file mode 100644
index 0000000..5982639
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/iio/adc/mediatek,mt6359-auxadc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6359_AUXADC_H
+
+/* ADC Channel Index */
+#define MT6359_AUXADC_BATADC 0
+#define MT6359_AUXADC_BAT_TEMP 1
+#define MT6359_AUXADC_CHIP_TEMP 2
+#define MT6359_AUXADC_ACCDET 3
+#define MT6359_AUXADC_VDCXO 4
+#define MT6359_AUXADC_TSX_TEMP 5
+#define MT6359_AUXADC_HPOFS_CAL 6
+#define MT6359_AUXADC_DCXO_TEMP 7
+#define MT6359_AUXADC_VBIF 8
+#define MT6359_AUXADC_VCORE_TEMP 9
+#define MT6359_AUXADC_VPROC_TEMP 10
+#define MT6359_AUXADC_VGPU_TEMP 11
+#define MT6359_AUXADC_VBAT 12
+#define MT6359_AUXADC_IBAT 13
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/input/cros-ec-keyboard.h b/dts/upstream/include/dt-bindings/input/cros-ec-keyboard.h
index f0ae036..afc12f6 100644
--- a/dts/upstream/include/dt-bindings/input/cros-ec-keyboard.h
+++ b/dts/upstream/include/dt-bindings/input/cros-ec-keyboard.h
@@ -100,4 +100,108 @@
MATRIX_KEY(0x07, 0x0b, KEY_UP) \
MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
+/* No numpad */
+#define CROS_TOP_ROW_KEYMAP_V30 \
+ MATRIX_KEY(0x00, 0x01, KEY_F11) /* T11 */ \
+ MATRIX_KEY(0x00, 0x02, KEY_F1) /* T1 */ \
+ MATRIX_KEY(0x00, 0x04, KEY_F10) /* T10 */ \
+ MATRIX_KEY(0x00, 0x0b, KEY_F14) /* T14 */ \
+ MATRIX_KEY(0x00, 0x0c, KEY_F15) /* T15 */ \
+ MATRIX_KEY(0x01, 0x02, KEY_F4) /* T4 */ \
+ MATRIX_KEY(0x01, 0x04, KEY_F7) /* T7 */ \
+ MATRIX_KEY(0x01, 0x05, KEY_F12) /* T12 */ \
+ MATRIX_KEY(0x01, 0x09, KEY_F9) /* T9 */ \
+ MATRIX_KEY(0x02, 0x02, KEY_F3) /* T3 */ \
+ MATRIX_KEY(0x02, 0x04, KEY_F6) /* T6 */ \
+ MATRIX_KEY(0x02, 0x0b, KEY_F8) /* T8 */ \
+ MATRIX_KEY(0x03, 0x02, KEY_F2) /* T2 */ \
+ MATRIX_KEY(0x03, 0x05, KEY_F13) /* T13 */ \
+ MATRIX_KEY(0x04, 0x04, KEY_F5) /* T5 */
+
+#define CROS_MAIN_KEYMAP_V30 /* Keycode */ \
+ MATRIX_KEY(0x00, 0x03, KEY_B) /* 50 */ \
+ MATRIX_KEY(0x00, 0x05, KEY_N) /* 51 */ \
+ MATRIX_KEY(0x00, 0x06, KEY_RO) /* 56 (JIS) */ \
+ MATRIX_KEY(0x00, 0x08, KEY_EQUAL) /* 13 */ \
+ MATRIX_KEY(0x00, 0x09, KEY_HOME) /* 80 (Numpad) */ \
+ MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) /* 62 */ \
+ MATRIX_KEY(0x00, 0x10, KEY_FN) /* 127 */ \
+ \
+ MATRIX_KEY(0x01, 0x01, KEY_ESC) /* 110 */ \
+ MATRIX_KEY(0x01, 0x03, KEY_G) /* 35 */ \
+ MATRIX_KEY(0x01, 0x06, KEY_H) /* 36 */ \
+ MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) /* 41 */ \
+ MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) /* 15 */ \
+ MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) /* 65 (JIS) */ \
+ MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* 58 */ \
+ \
+ MATRIX_KEY(0x02, 0x01, KEY_TAB) /* 16 */ \
+ MATRIX_KEY(0x02, 0x03, KEY_T) /* 21 */ \
+ MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) /* 28 */ \
+ MATRIX_KEY(0x02, 0x06, KEY_Y) /* 22 */ \
+ MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) /* 27 */ \
+ MATRIX_KEY(0x02, 0x09, KEY_DELETE) /* 76 (Numpad) */ \
+ MATRIX_KEY(0x02, 0x0c, KEY_PAGEUP) /* 85 (Numpad) */ \
+ MATRIX_KEY(0x02, 0x011, KEY_YEN) /* 14 (JIS) */ \
+ \
+ MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) /* Launcher */ \
+ MATRIX_KEY(0x03, 0x01, KEY_GRAVE) /* 1 */ \
+ MATRIX_KEY(0x03, 0x03, KEY_5) /* 6 */ \
+ MATRIX_KEY(0x03, 0x04, KEY_S) /* 32 */ \
+ MATRIX_KEY(0x03, 0x06, KEY_MINUS) /* 12 */ \
+ MATRIX_KEY(0x03, 0x08, KEY_6) /* 7 */ \
+ MATRIX_KEY(0x03, 0x09, KEY_SLEEP) /* Lock */ \
+ MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) /* 29 */ \
+ MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) /* 63 (JIS) */ \
+ MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* 64 */ \
+ \
+ MATRIX_KEY(0x04, 0x01, KEY_A) /* 31 */ \
+ MATRIX_KEY(0x04, 0x02, KEY_D) /* 33 */ \
+ MATRIX_KEY(0x04, 0x03, KEY_F) /* 34 */ \
+ MATRIX_KEY(0x04, 0x05, KEY_K) /* 38 */ \
+ MATRIX_KEY(0x04, 0x06, KEY_J) /* 37 */ \
+ MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) /* 40 */ \
+ MATRIX_KEY(0x04, 0x09, KEY_L) /* 39 */ \
+ MATRIX_KEY(0x04, 0x0b, KEY_ENTER) /* 43 */ \
+ MATRIX_KEY(0x04, 0x0c, KEY_END) /* 81 (Numpad) */ \
+ \
+ MATRIX_KEY(0x05, 0x01, KEY_1) /* 2 */ \
+ MATRIX_KEY(0x05, 0x02, KEY_COMMA) /* 53 */ \
+ MATRIX_KEY(0x05, 0x03, KEY_DOT) /* 54 */ \
+ MATRIX_KEY(0x05, 0x04, KEY_SLASH) /* 55 */ \
+ MATRIX_KEY(0x05, 0x05, KEY_C) /* 48 */ \
+ MATRIX_KEY(0x05, 0x06, KEY_SPACE) /* 61 */ \
+ MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) /* 44 */ \
+ MATRIX_KEY(0x05, 0x08, KEY_X) /* 47 */ \
+ MATRIX_KEY(0x05, 0x09, KEY_V) /* 49 */ \
+ MATRIX_KEY(0x05, 0x0b, KEY_M) /* 52 */ \
+ MATRIX_KEY(0x05, 0x0c, KEY_PAGEDOWN) /* 86 (Numpad) */ \
+ \
+ MATRIX_KEY(0x06, 0x01, KEY_Z) /* 46 */ \
+ MATRIX_KEY(0x06, 0x02, KEY_3) /* 4 */ \
+ MATRIX_KEY(0x06, 0x03, KEY_4) /* 5 */ \
+ MATRIX_KEY(0x06, 0x04, KEY_2) /* 3 */ \
+ MATRIX_KEY(0x06, 0x05, KEY_8) /* 9 */ \
+ MATRIX_KEY(0x06, 0x06, KEY_0) /* 11 */ \
+ MATRIX_KEY(0x06, 0x08, KEY_7) /* 8 */ \
+ MATRIX_KEY(0x06, 0x09, KEY_9) /* 10 */ \
+ MATRIX_KEY(0x06, 0x0b, KEY_DOWN) /* 84 */ \
+ MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) /* 89 */ \
+ MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT) /* 60 */ \
+ MATRIX_KEY(0x06, 0x0f, KEY_ASSISTANT) /* 128 */ \
+ MATRIX_KEY(0x06, 0x11, KEY_BACKSLASH) /* 42 (JIS, ISO) */ \
+ \
+ MATRIX_KEY(0x07, 0x01, KEY_U) /* 23 */ \
+ MATRIX_KEY(0x07, 0x02, KEY_I) /* 24 */ \
+ MATRIX_KEY(0x07, 0x03, KEY_O) /* 25 */ \
+ MATRIX_KEY(0x07, 0x04, KEY_P) /* 26 */ \
+ MATRIX_KEY(0x07, 0x05, KEY_Q) /* 17 */ \
+ MATRIX_KEY(0x07, 0x06, KEY_W) /* 18 */ \
+ MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) /* 57 */ \
+ MATRIX_KEY(0x07, 0x08, KEY_E) /* 19 */ \
+ MATRIX_KEY(0x07, 0x09, KEY_R) /* 20 */ \
+ MATRIX_KEY(0x07, 0x0b, KEY_UP) /* 83 */ \
+ MATRIX_KEY(0x07, 0x0c, KEY_LEFT) /* 79 */ \
+ MATRIX_KEY(0x07, 0x11, KEY_102ND) /* 45 (ISO) */
+
#endif /* _CROS_EC_KEYBOARD_H */
diff --git a/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8183.h b/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8183.h
new file mode 100644
index 0000000..1088c35
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8183.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
+
+#define SLAVE_DDR_EMI 0
+#define MASTER_MCUSYS 1
+#define MASTER_MFG 2
+#define MASTER_MMSYS 3
+#define MASTER_MM_VPU 4
+#define MASTER_MM_DISP 5
+#define MASTER_MM_VDEC 6
+#define MASTER_MM_VENC 7
+#define MASTER_MM_CAM 8
+#define MASTER_MM_IMG 9
+#define MASTER_MM_MDP 10
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8195.h b/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8195.h
new file mode 100644
index 0000000..33e0e6c
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/mediatek,mt8195.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2024 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
+
+#define SLAVE_DDR_EMI 0
+#define MASTER_MCUSYS 1
+#define MASTER_GPUSYS 2
+#define MASTER_MMSYS 3
+#define MASTER_MM_VPU 4
+#define MASTER_MM_DISP 5
+#define MASTER_MM_VDEC 6
+#define MASTER_MM_VENC 7
+#define MASTER_MM_CAM 8
+#define MASTER_MM_IMG 9
+#define MASTER_MM_MDP 10
+#define MASTER_VPUSYS 11
+#define MASTER_VPU_0 12
+#define MASTER_VPU_1 13
+#define MASTER_MDLASYS 14
+#define MASTER_MDLA_0 15
+#define MASTER_UFS 16
+#define MASTER_PCIE_0 17
+#define MASTER_PCIE_1 18
+#define MASTER_USB 19
+#define MASTER_DBGIF 20
+#define SLAVE_HRT_DDR_EMI 21
+#define MASTER_HRT_MMSYS 22
+#define MASTER_HRT_MM_DISP 23
+#define MASTER_HRT_MM_VDEC 24
+#define MASTER_HRT_MM_VENC 25
+#define MASTER_HRT_MM_CAM 26
+#define MASTER_HRT_MM_IMG 27
+#define MASTER_HRT_MM_MDP 28
+#define MASTER_HRT_DBGIF 29
+#define MASTER_WIFI 30
+#define MASTER_BT 31
+#define MASTER_NETSYS 32
+#endif
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq9574.h b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 0000000..4201933
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define MASTER_ANOC_PCIE0 0
+#define SLAVE_ANOC_PCIE0 1
+#define MASTER_SNOC_PCIE0 2
+#define SLAVE_SNOC_PCIE0 3
+#define MASTER_ANOC_PCIE1 4
+#define SLAVE_ANOC_PCIE1 5
+#define MASTER_SNOC_PCIE1 6
+#define SLAVE_SNOC_PCIE1 7
+#define MASTER_ANOC_PCIE2 8
+#define SLAVE_ANOC_PCIE2 9
+#define MASTER_SNOC_PCIE2 10
+#define SLAVE_SNOC_PCIE2 11
+#define MASTER_ANOC_PCIE3 12
+#define SLAVE_ANOC_PCIE3 13
+#define MASTER_SNOC_PCIE3 14
+#define SLAVE_SNOC_PCIE3 15
+#define MASTER_USB 16
+#define SLAVE_USB 17
+#define MASTER_USB_AXI 18
+#define SLAVE_USB_AXI 19
+#define MASTER_NSSNOC_NSSCC 20
+#define SLAVE_NSSNOC_NSSCC 21
+#define MASTER_NSSNOC_SNOC_0 22
+#define SLAVE_NSSNOC_SNOC_0 23
+#define MASTER_NSSNOC_SNOC_1 24
+#define SLAVE_NSSNOC_SNOC_1 25
+#define MASTER_NSSNOC_PCNOC_1 26
+#define SLAVE_NSSNOC_PCNOC_1 27
+#define MASTER_NSSNOC_QOSGEN_REF 28
+#define SLAVE_NSSNOC_QOSGEN_REF 29
+#define MASTER_NSSNOC_TIMEOUT_REF 30
+#define SLAVE_NSSNOC_TIMEOUT_REF 31
+#define MASTER_NSSNOC_XO_DCD 32
+#define SLAVE_NSSNOC_XO_DCD 33
+#define MASTER_NSSNOC_ATB 34
+#define SLAVE_NSSNOC_ATB 35
+#define MASTER_MEM_NOC_NSSNOC 36
+#define SLAVE_MEM_NOC_NSSNOC 37
+#define MASTER_NSSNOC_MEMNOC 38
+#define SLAVE_NSSNOC_MEMNOC 39
+#define MASTER_NSSNOC_MEM_NOC_1 40
+#define SLAVE_NSSNOC_MEM_NOC_1 41
+
+#define MASTER_NSSNOC_PPE 0
+#define SLAVE_NSSNOC_PPE 1
+#define MASTER_NSSNOC_PPE_CFG 2
+#define SLAVE_NSSNOC_PPE_CFG 3
+#define MASTER_NSSNOC_NSS_CSR 4
+#define SLAVE_NSSNOC_NSS_CSR 5
+#define MASTER_NSSNOC_IMEM_QSB 6
+#define SLAVE_NSSNOC_IMEM_QSB 7
+#define MASTER_NSSNOC_IMEM_AHB 8
+#define SLAVE_NSSNOC_IMEM_AHB 9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,msm8953.h b/dts/upstream/include/dt-bindings/interconnect/qcom,msm8953.h
new file mode 100644
index 0000000..12564c4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,msm8953.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Qualcomm MSM8953 interconnect IDs
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H
+
+/* BIMC fabric */
+#define MAS_APPS_PROC 0
+#define MAS_OXILI 1
+#define MAS_SNOC_BIMC_0 2
+#define MAS_SNOC_BIMC_2 3
+#define MAS_SNOC_BIMC_1 4
+#define MAS_TCU_0 5
+#define SLV_EBI 6
+#define SLV_BIMC_SNOC 7
+
+/* PCNOC fabric */
+#define MAS_SPDM 0
+#define MAS_BLSP_1 1
+#define MAS_BLSP_2 2
+#define MAS_USB3 3
+#define MAS_CRYPTO 4
+#define MAS_SDCC_1 5
+#define MAS_SDCC_2 6
+#define MAS_SNOC_PCNOC 7
+#define PCNOC_M_0 8
+#define PCNOC_M_1 9
+#define PCNOC_INT_1 10
+#define PCNOC_INT_2 11
+#define PCNOC_S_0 12
+#define PCNOC_S_1 13
+#define PCNOC_S_2 14
+#define PCNOC_S_3 15
+#define PCNOC_S_4 16
+#define PCNOC_S_6 17
+#define PCNOC_S_7 18
+#define PCNOC_S_8 19
+#define PCNOC_S_9 20
+#define SLV_SPDM 21
+#define SLV_PDM 22
+#define SLV_TCSR 23
+#define SLV_SNOC_CFG 24
+#define SLV_TLMM 25
+#define SLV_MESSAGE_RAM 26
+#define SLV_BLSP_1 27
+#define SLV_BLSP_2 28
+#define SLV_PRNG 29
+#define SLV_CAMERA_SS_CFG 30
+#define SLV_DISP_SS_CFG 31
+#define SLV_VENUS_CFG 32
+#define SLV_GPU_CFG 33
+#define SLV_SDCC_1 34
+#define SLV_SDCC_2 35
+#define SLV_CRYPTO_0_CFG 36
+#define SLV_PMIC_ARB 37
+#define SLV_USB3 38
+#define SLV_IPA_CFG 39
+#define SLV_TCU 40
+#define SLV_PCNOC_SNOC 41
+
+/* SNOC fabric */
+#define MAS_QDSS_BAM 0
+#define MAS_BIMC_SNOC 1
+#define MAS_PCNOC_SNOC 2
+#define MAS_IPA 3
+#define MAS_QDSS_ETR 4
+#define QDSS_INT 5
+#define SNOC_INT_0 6
+#define SNOC_INT_1 7
+#define SNOC_INT_2 8
+#define SLV_KPSS_AHB 9
+#define SLV_WCSS 10
+#define SLV_SNOC_BIMC_1 11
+#define SLV_IMEM 12
+#define SLV_SNOC_PCNOC 13
+#define SLV_QDSS_STM 14
+#define SLV_CATS_1 15
+#define SLV_LPASS 16
+
+/* SNOC-MM fabric */
+#define MAS_JPEG 0
+#define MAS_MDP 1
+#define MAS_VENUS 2
+#define MAS_VFE0 3
+#define MAS_VFE1 4
+#define MAS_CPP 5
+#define SLV_SNOC_BIMC_0 6
+#define SLV_SNOC_BIMC_2 7
+#define SLV_CATS_0 8
+
+#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H */
diff --git a/dts/upstream/include/dt-bindings/mfd/qcom-pm8008.h b/dts/upstream/include/dt-bindings/mfd/qcom-pm8008.h
deleted file mode 100644
index eca9448..0000000
--- a/dts/upstream/include/dt-bindings/mfd/qcom-pm8008.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2021 The Linux Foundation. All rights reserved.
- */
-
-#ifndef __DT_BINDINGS_MFD_QCOM_PM8008_H
-#define __DT_BINDINGS_MFD_QCOM_PM8008_H
-
-/* PM8008 IRQ numbers */
-#define PM8008_IRQ_MISC_UVLO 0
-#define PM8008_IRQ_MISC_OVLO 1
-#define PM8008_IRQ_MISC_OTST2 2
-#define PM8008_IRQ_MISC_OTST3 3
-#define PM8008_IRQ_MISC_LDO_OCP 4
-#define PM8008_IRQ_TEMP_ALARM 5
-#define PM8008_IRQ_GPIO1 6
-#define PM8008_IRQ_GPIO2 7
-
-#endif
diff --git a/dts/upstream/include/dt-bindings/mfd/st,stpmic1.h b/dts/upstream/include/dt-bindings/mfd/st,stpmic1.h
index 321cd08..9dd15b9 100644
--- a/dts/upstream/include/dt-bindings/mfd/st,stpmic1.h
+++ b/dts/upstream/include/dt-bindings/mfd/st,stpmic1.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Philippe Peurichard <philippe.peurichard@st.com>,
diff --git a/dts/upstream/include/dt-bindings/power/amlogic,a4-pwrc.h b/dts/upstream/include/dt-bindings/power/amlogic,a4-pwrc.h
new file mode 100644
index 0000000..bd2f9c5
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/power/amlogic,a4-pwrc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Amlogic, Inc. All rights reserved
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_A4_POWER_H
+#define _DT_BINDINGS_AMLOGIC_A4_POWER_H
+
+#define PWRC_A4_AUDIO_ID 0
+#define PWRC_A4_SDIOA_ID 1
+#define PWRC_A4_EMMC_ID 2
+#define PWRC_A4_USB_COMB_ID 3
+#define PWRC_A4_ETH_ID 4
+#define PWRC_A4_VOUT_ID 5
+#define PWRC_A4_AUDIO_PDM_ID 6
+#define PWRC_A4_DMC_ID 7
+#define PWRC_A4_SYS_WRAP_ID 8
+#define PWRC_A4_AO_I2C_S_ID 9
+#define PWRC_A4_AO_UART_ID 10
+#define PWRC_A4_AO_IR_ID 11
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/power/amlogic,a5-pwrc.h b/dts/upstream/include/dt-bindings/power/amlogic,a5-pwrc.h
new file mode 100644
index 0000000..3a6f53e
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/power/amlogic,a5-pwrc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_A5_POWER_H
+#define _DT_BINDINGS_AMLOGIC_A5_POWER_H
+
+#define PWRC_A5_NNA_ID 0
+#define PWRC_A5_AUDIO_ID 1
+#define PWRC_A5_SDIOA_ID 2
+#define PWRC_A5_EMMC_ID 3
+#define PWRC_A5_USB_COMB_ID 4
+#define PWRC_A5_ETH_ID 5
+#define PWRC_A5_RSA_ID 6
+#define PWRC_A5_AUDIO_PDM_ID 7
+#define PWRC_A5_DMC_ID 8
+#define PWRC_A5_SYS_WRAP_ID 9
+#define PWRC_A5_DSPA_ID 10
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/regulator/st,stm32mp25-regulator.h b/dts/upstream/include/dt-bindings/regulator/st,stm32mp25-regulator.h
new file mode 100644
index 0000000..3c3d309
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/regulator/st,stm32mp25-regulator.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H
+#define __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H
+
+/* SCMI voltage domains identifiers */
+
+/* SOC Internal regulators */
+#define VOLTD_SCMI_VDDIO1 0
+#define VOLTD_SCMI_VDDIO2 1
+#define VOLTD_SCMI_VDDIO3 2
+#define VOLTD_SCMI_VDDIO4 3
+#define VOLTD_SCMI_VDDIO 4
+#define VOLTD_SCMI_UCPD 5
+#define VOLTD_SCMI_USB33 6
+#define VOLTD_SCMI_ADC 7
+#define VOLTD_SCMI_GPU 8
+#define VOLTD_SCMI_VREFBUF 9
+
+/* STPMIC2 regulators */
+#define VOLTD_SCMI_STPMIC2_BUCK1 10
+#define VOLTD_SCMI_STPMIC2_BUCK2 11
+#define VOLTD_SCMI_STPMIC2_BUCK3 12
+#define VOLTD_SCMI_STPMIC2_BUCK4 13
+#define VOLTD_SCMI_STPMIC2_BUCK5 14
+#define VOLTD_SCMI_STPMIC2_BUCK6 15
+#define VOLTD_SCMI_STPMIC2_BUCK7 16
+#define VOLTD_SCMI_STPMIC2_LDO1 17
+#define VOLTD_SCMI_STPMIC2_LDO2 18
+#define VOLTD_SCMI_STPMIC2_LDO3 19
+#define VOLTD_SCMI_STPMIC2_LDO4 20
+#define VOLTD_SCMI_STPMIC2_LDO5 21
+#define VOLTD_SCMI_STPMIC2_LDO6 22
+#define VOLTD_SCMI_STPMIC2_LDO7 23
+#define VOLTD_SCMI_STPMIC2_LDO8 24
+#define VOLTD_SCMI_STPMIC2_REFDDR 25
+
+/* External regulators */
+#define VOLTD_SCMI_REGU0 26
+#define VOLTD_SCMI_REGU1 27
+#define VOLTD_SCMI_REGU2 28
+#define VOLTD_SCMI_REGU3 29
+#define VOLTD_SCMI_REGU4 30
+
+#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H */
diff --git a/dts/upstream/include/dt-bindings/reset/airoha,en7581-reset.h b/dts/upstream/include/dt-bindings/reset/airoha,en7581-reset.h
new file mode 100644
index 0000000..6544a17
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/airoha,en7581-reset.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 AIROHA Inc
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
+
+/* RST_CTRL2 */
+#define EN7581_XPON_PHY_RST 0
+#define EN7581_CPU_TIMER2_RST 1
+#define EN7581_HSUART_RST 2
+#define EN7581_UART4_RST 3
+#define EN7581_UART5_RST 4
+#define EN7581_I2C2_RST 5
+#define EN7581_XSI_MAC_RST 6
+#define EN7581_XSI_PHY_RST 7
+#define EN7581_NPU_RST 8
+#define EN7581_I2S_RST 9
+#define EN7581_TRNG_RST 10
+#define EN7581_TRNG_MSTART_RST 11
+#define EN7581_DUAL_HSI0_RST 12
+#define EN7581_DUAL_HSI1_RST 13
+#define EN7581_HSI_RST 14
+#define EN7581_DUAL_HSI0_MAC_RST 15
+#define EN7581_DUAL_HSI1_MAC_RST 16
+#define EN7581_HSI_MAC_RST 17
+#define EN7581_WDMA_RST 18
+#define EN7581_WOE0_RST 19
+#define EN7581_WOE1_RST 20
+#define EN7581_HSDMA_RST 21
+#define EN7581_TDMA_RST 22
+#define EN7581_EMMC_RST 23
+#define EN7581_SOE_RST 24
+#define EN7581_PCIE2_RST 25
+#define EN7581_XFP_MAC_RST 26
+#define EN7581_USB_HOST_P1_RST 27
+#define EN7581_USB_HOST_P1_U3_PHY_RST 28
+/* RST_CTRL1 */
+#define EN7581_PCM1_ZSI_ISI_RST 29
+#define EN7581_FE_PDMA_RST 30
+#define EN7581_FE_QDMA_RST 31
+#define EN7581_PCM_SPIWP_RST 32
+#define EN7581_CRYPTO_RST 33
+#define EN7581_TIMER_RST 34
+#define EN7581_PCM1_RST 35
+#define EN7581_UART_RST 36
+#define EN7581_GPIO_RST 37
+#define EN7581_GDMA_RST 38
+#define EN7581_I2C_MASTER_RST 39
+#define EN7581_PCM2_ZSI_ISI_RST 40
+#define EN7581_SFC_RST 41
+#define EN7581_UART2_RST 42
+#define EN7581_GDMP_RST 43
+#define EN7581_FE_RST 44
+#define EN7581_USB_HOST_P0_RST 45
+#define EN7581_GSW_RST 46
+#define EN7581_SFC2_PCM_RST 47
+#define EN7581_PCIE0_RST 48
+#define EN7581_PCIE1_RST 49
+#define EN7581_CPU_TIMER_RST 50
+#define EN7581_PCIE_HB_RST 51
+#define EN7581_XPON_MAC_RST 52
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
diff --git a/dts/upstream/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/dts/upstream/include/dt-bindings/reset/qcom,qca8k-nsscc.h
new file mode 100644
index 0000000..c71167a
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/qcom,qca8k-nsscc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
+#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
+
+#define NSS_CC_SWITCH_CORE_ARES 1
+#define NSS_CC_APB_BRIDGE_ARES 2
+#define NSS_CC_MAC0_TX_ARES 3
+#define NSS_CC_MAC0_TX_SRDS1_ARES 4
+#define NSS_CC_MAC0_RX_ARES 5
+#define NSS_CC_MAC0_RX_SRDS1_ARES 6
+#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7
+#define NSS_CC_MAC1_TX_ARES 8
+#define NSS_CC_MAC1_GEPHY0_TX_ARES 9
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10
+#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11
+#define NSS_CC_MAC1_RX_ARES 12
+#define NSS_CC_MAC1_GEPHY0_RX_ARES 13
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14
+#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15
+#define NSS_CC_MAC2_TX_ARES 16
+#define NSS_CC_MAC2_GEPHY1_TX_ARES 17
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18
+#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19
+#define NSS_CC_MAC2_RX_ARES 20
+#define NSS_CC_MAC2_GEPHY1_RX_ARES 21
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22
+#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23
+#define NSS_CC_MAC3_TX_ARES 24
+#define NSS_CC_MAC3_GEPHY2_TX_ARES 25
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26
+#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27
+#define NSS_CC_MAC3_RX_ARES 28
+#define NSS_CC_MAC3_GEPHY2_RX_ARES 29
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30
+#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31
+#define NSS_CC_MAC4_TX_ARES 32
+#define NSS_CC_MAC4_GEPHY3_TX_ARES 33
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34
+#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35
+#define NSS_CC_MAC4_RX_ARES 36
+#define NSS_CC_MAC4_GEPHY3_RX_ARES 37
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38
+#define NSS_CC_MAC5_TX_ARES 39
+#define NSS_CC_MAC5_TX_SRDS0_ARES 40
+#define NSS_CC_MAC5_RX_ARES 41
+#define NSS_CC_MAC5_RX_SRDS0_ARES 42
+#define NSS_CC_AHB_ARES 43
+#define NSS_CC_SEC_CTRL_AHB_ARES 44
+#define NSS_CC_TLMM_ARES 45
+#define NSS_CC_TLMM_AHB_ARES 46
+#define NSS_CC_CNOC_AHB_ARES 47
+#define NSS_CC_MDIO_AHB_ARES 48
+#define NSS_CC_MDIO_MASTER_AHB_ARES 49
+#define NSS_CC_SRDS0_SYS_ARES 50
+#define NSS_CC_SRDS1_SYS_ARES 51
+#define NSS_CC_GEPHY0_SYS_ARES 52
+#define NSS_CC_GEPHY1_SYS_ARES 53
+#define NSS_CC_GEPHY2_SYS_ARES 54
+#define NSS_CC_GEPHY3_SYS_ARES 55
+#define NSS_CC_SEC_CTRL_ARES 56
+#define NSS_CC_SEC_CTRL_SENSE_ARES 57
+#define NSS_CC_SLEEP_ARES 58
+#define NSS_CC_DEBUG_ARES 59
+#define NSS_CC_GEPHY0_ARES 60
+#define NSS_CC_GEPHY1_ARES 61
+#define NSS_CC_GEPHY2_ARES 62
+#define NSS_CC_GEPHY3_ARES 63
+#define NSS_CC_DSP_ARES 64
+#define NSS_CC_GEPHY_FULL_ARES 65
+#define NSS_CC_GLOBAL_ARES 66
+#define NSS_CC_XPCS_ARES 67
+#endif
diff --git a/dts/upstream/include/dt-bindings/reset/sun50i-h616-ccu.h b/dts/upstream/include/dt-bindings/reset/sun50i-h616-ccu.h
index 1bd8bb0..ed177c0 100644
--- a/dts/upstream/include/dt-bindings/reset/sun50i-h616-ccu.h
+++ b/dts/upstream/include/dt-bindings/reset/sun50i-h616-ccu.h
@@ -66,5 +66,6 @@
#define RST_BUS_TVE0 57
#define RST_BUS_HDCP 58
#define RST_BUS_KEYADC 59
+#define RST_BUS_GPADC 60
#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
diff --git a/dts/upstream/include/dt-bindings/sound/audio-graph.h b/dts/upstream/include/dt-bindings/sound/audio-graph.h
new file mode 100644
index 0000000..bdb70c6
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/sound/audio-graph.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * audio-graph.h
+ *
+ * Copyright (c) 2024 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ */
+#ifndef __AUDIO_GRAPH_H
+#define __AUDIO_GRAPH_H
+
+/*
+ * used in
+ * link-trigger-order
+ * link-trigger-order-start
+ * link-trigger-order-stop
+ *
+ * default is
+ * link-trigger-order = <SND_SOC_TRIGGER_LINK
+ * SND_SOC_TRIGGER_COMPONENT
+ * SND_SOC_TRIGGER_DAI>;
+ */
+#define SND_SOC_TRIGGER_LINK 0
+#define SND_SOC_TRIGGER_COMPONENT 1
+#define SND_SOC_TRIGGER_DAI 2
+#define SND_SOC_TRIGGER_SIZE 3 /* shoud be last */
+
+#endif /* __AUDIO_GRAPH_H */
diff --git a/dts/upstream/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/dts/upstream/include/dt-bindings/thermal/mediatek,lvts-thermal.h
index bf95309..ddc7302 100644
--- a/dts/upstream/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+++ b/dts/upstream/include/dt-bindings/thermal/mediatek,lvts-thermal.h
@@ -24,7 +24,7 @@
#define MT8186_BIG_CPU1 5
#define MT8186_NNA 6
#define MT8186_ADSP 7
-#define MT8186_MFG 8
+#define MT8186_GPU 8
#define MT8188_MCU_LITTLE_CPU0 0
#define MT8188_MCU_LITTLE_CPU1 1
@@ -34,11 +34,11 @@
#define MT8188_MCU_BIG_CPU1 5
#define MT8188_AP_APU 0
-#define MT8188_AP_GPU1 1
-#define MT8188_AP_GPU2 2
-#define MT8188_AP_SOC1 3
-#define MT8188_AP_SOC2 4
-#define MT8188_AP_SOC3 5
+#define MT8188_AP_GPU0 1
+#define MT8188_AP_GPU1 2
+#define MT8188_AP_ADSP 3
+#define MT8188_AP_VDO 4
+#define MT8188_AP_INFRA 5
#define MT8188_AP_CAM1 6
#define MT8188_AP_CAM2 7
diff --git a/dts/upstream/src/arm/arm/arm-realview-eb-bbrevd.dtsi b/dts/upstream/src/arm/arm/arm-realview-eb-bbrevd.dtsi
index a79e1d1..7f62aef 100644
--- a/dts/upstream/src/arm/arm/arm-realview-eb-bbrevd.dtsi
+++ b/dts/upstream/src/arm/arm/arm-realview-eb-bbrevd.dtsi
@@ -22,7 +22,7 @@
/ {
/* Introduce a fixed regulator for the new ethernet controller */
- veth: fixedregulator@0 {
+ veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
diff --git a/dts/upstream/src/arm/arm/arm-realview-eb.dtsi b/dts/upstream/src/arm/arm/arm-realview-eb.dtsi
index fbb2258..16f784d 100644
--- a/dts/upstream/src/arm/arm/arm-realview-eb.dtsi
+++ b/dts/upstream/src/arm/arm/arm-realview-eb.dtsi
@@ -45,7 +45,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
- vmmc: fixedregulator@0 {
+ vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@@ -53,13 +53,13 @@
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@@ -67,48 +67,8 @@
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
diff --git a/dts/upstream/src/arm/arm/arm-realview-pb1176.dts b/dts/upstream/src/arm/arm/arm-realview-pb1176.dts
index d99bac0..b9b10cb 100644
--- a/dts/upstream/src/arm/arm/arm-realview-pb1176.dts
+++ b/dts/upstream/src/arm/arm/arm-realview-pb1176.dts
@@ -63,13 +63,13 @@
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@@ -77,40 +77,8 @@
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
diff --git a/dts/upstream/src/arm/arm/arm-realview-pb11mp.dts b/dts/upstream/src/arm/arm/arm-realview-pb11mp.dts
index 89103d5..ce35748 100644
--- a/dts/upstream/src/arm/arm/arm-realview-pb11mp.dts
+++ b/dts/upstream/src/arm/arm/arm-realview-pb11mp.dts
@@ -163,19 +163,19 @@
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- refclk32khz: refclk32khz {
+ refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@@ -183,48 +183,8 @@
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
diff --git a/dts/upstream/src/arm/arm/arm-realview-pbx.dtsi b/dts/upstream/src/arm/arm/arm-realview-pbx.dtsi
index ec1507c..e625403 100644
--- a/dts/upstream/src/arm/arm/arm-realview-pbx.dtsi
+++ b/dts/upstream/src/arm/arm/arm-realview-pbx.dtsi
@@ -62,19 +62,19 @@
regulator-boot-on;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- refclk32khz: refclk32khz {
+ refclk32khz: clock-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@@ -82,48 +82,8 @@
clocks = <&xtal24mhz>;
};
- mclk: mclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- kmiclk: kmiclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- sspclk: sspclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- uartclk: uartclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
- wdogclk: wdogclk@24M {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* FIXME: this actually hangs off the PLL clocks */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
diff --git a/dts/upstream/src/arm/arm/integratorap-im-pd1.dts b/dts/upstream/src/arm/arm/integratorap-im-pd1.dts
index 367850e..db13e09 100644
--- a/dts/upstream/src/arm/arm/integratorap-im-pd1.dts
+++ b/dts/upstream/src/arm/arm/integratorap-im-pd1.dts
@@ -54,7 +54,7 @@
};
/* Also used for the Smart Card Interface SCI */
- impd1_uartclk: clock@1_4 {
+ impd1_uartclk: clock-uart {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
@@ -64,7 +64,7 @@
};
/* For the SSP the clock is divided by 64 */
- impd1_sspclk: clock@1_64 {
+ impd1_sspclk: clock-ssp {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <64>;
diff --git a/dts/upstream/src/arm/arm/integratorap.dts b/dts/upstream/src/arm/arm/integratorap.dts
index d9927d3..9b6a1db 100644
--- a/dts/upstream/src/arm/arm/integratorap.dts
+++ b/dts/upstream/src/arm/arm/integratorap.dts
@@ -57,22 +57,14 @@
};
/* 24 MHz chrystal on the Integrator/AP development board */
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: pclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
- pclk: pclk@0 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&xtal24mhz>;
- };
-
/* The UART clock is 14.74 MHz divided by an ICS525 */
- uartclk: uartclk@14.74M {
+ uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
@@ -81,7 +73,7 @@
core-module@10000000 {
/* 24 MHz chrystal on the core module */
- cm24mhz: cm24mhz@24M {
+ cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
diff --git a/dts/upstream/src/arm/arm/integratorcp.dts b/dts/upstream/src/arm/arm/integratorcp.dts
index c011333..8ad1a89 100644
--- a/dts/upstream/src/arm/arm/integratorcp.dts
+++ b/dts/upstream/src/arm/arm/integratorcp.dts
@@ -47,14 +47,14 @@
*/
/* The codec chrystal operates at 24.576 MHz */
- xtal_codec: xtal24.576@24.576M {
+ xtal_codec: clock-24576000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
/* The chrystal is divided by 2 by the codec for the AACI bit clock */
- aaci_bitclk: aaci_bitclk@12.288M {
+ aaci_bitclk: clock-12288000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
@@ -63,21 +63,21 @@
};
/* This is a 25MHz chrystal on the base board */
- xtal25mhz: xtal25mhz@25M {
+ xtal25mhz: clock-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
- uartclk: uartclk@14.74M {
+ uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
};
/* Actually sysclk I think */
- pclk: pclk@0 {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
@@ -85,7 +85,7 @@
core-module@10000000 {
/* 24 MHz chrystal on the core module */
- cm24mhz: cm24mhz@24M {
+ cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -131,7 +131,7 @@
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
diff --git a/dts/upstream/src/arm/arm/mps2.dtsi b/dts/upstream/src/arm/arm/mps2.dtsi
index ce30882..e240bc8 100644
--- a/dts/upstream/src/arm/arm/mps2.dtsi
+++ b/dts/upstream/src/arm/arm/mps2.dtsi
@@ -48,37 +48,37 @@
#address-cells = <1>;
#size-cells = <1>;
- oscclk0: clk-osc0 {
+ oscclk0: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
- oscclk1: clk-osc1 {
+ oscclk1: clock-24576000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
- oscclk2: clk-osc2 {
+ oscclk2: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- cfgclk: clk-cfg {
+ cfgclk: clock-5000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <5000000>;
};
- spicfgclk: clk-spicfg {
+ spicfgclk: clock-75000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
};
- sysclk: clk-sys {
+ sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys {
compatible = "fixed-factor-clock";
clocks = <&oscclk0>;
#clock-cells = <0>;
@@ -86,7 +86,7 @@
clock-mult = <1>;
};
- audmclk: clk-audm {
+ audmclk: clk-12388000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;
@@ -94,7 +94,7 @@
clock-mult = <1>;
};
- audsclk: clk-auds {
+ audsclk: clk-3072000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;
@@ -102,38 +102,6 @@
clock-mult = <1>;
};
- spiclcd: clk-cpiclcd {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- spicon: clk-spicon {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- i2cclcd: clk-i2cclcd {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
- i2caud: clk-i2caud {
- compatible = "fixed-factor-clock";
- clocks = <&oscclk0>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
-
soc {
compatible = "simple-bus";
ranges;
diff --git a/dts/upstream/src/arm/arm/versatile-ab.dts b/dts/upstream/src/arm/arm/versatile-ab.dts
index de45aa9..635ab92 100644
--- a/dts/upstream/src/arm/arm/versatile-ab.dts
+++ b/dts/upstream/src/arm/arm/versatile-ab.dts
@@ -24,7 +24,7 @@
reg = <0x0 0x08000000>;
};
- xtal24mhz: xtal24mhz@24M {
+ xtal24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -142,14 +142,14 @@
};
/* OSC1 on AB, OSC4 on PB */
- osc1: cm_aux_osc@24M {
+ osc1: clock-osc {
#clock-cells = <0>;
compatible = "arm,versatile-cm-auxosc";
clocks = <&xtal24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
- timclk: timclk@1M {
+ timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@@ -157,7 +157,7 @@
clocks = <&xtal24mhz>;
};
- pclk: pclk@24M {
+ pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2m-rs1.dtsi b/dts/upstream/src/arm/arm/vexpress-v2m-rs1.dtsi
index 8af4b77..158b392 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2m-rs1.dtsi
+++ b/dts/upstream/src/arm/arm/vexpress-v2m-rs1.dtsi
@@ -20,7 +20,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
- v2m_fixed_3v3: fixed-regulator-0 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@@ -28,21 +28,21 @@
regulator-always-on;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2m.dtsi b/dts/upstream/src/arm/arm/vexpress-v2m.dtsi
index c5e92f6..be03f2a 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2m.dtsi
+++ b/dts/upstream/src/arm/arm/vexpress-v2m.dtsi
@@ -351,7 +351,7 @@
};
};
- v2m_fixed_3v3: fixed-regulator-0 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@@ -359,21 +359,21 @@
regulator-always-on;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -436,7 +436,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@@ -445,7 +445,7 @@
clock-output-names = "v2m:oscclk0";
};
- v2m_oscclk1: oscclk1 {
+ v2m_oscclk1: clock-controller-1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@@ -454,7 +454,7 @@
clock-output-names = "v2m:oscclk1";
};
- v2m_oscclk2: oscclk2 {
+ v2m_oscclk2: clock-controller-2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@@ -463,7 +463,7 @@
clock-output-names = "v2m:oscclk2";
};
- volt-vio {
+ regulator-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2p-ca15-tc1.dts b/dts/upstream/src/arm/arm/vexpress-v2p-ca15-tc1.dts
index 679537e..5a91e93 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2p-ca15-tc1.dts
+++ b/dts/upstream/src/arm/arm/vexpress-v2p-ca15-tc1.dts
@@ -142,7 +142,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* CPU PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@@ -151,7 +151,7 @@
clock-output-names = "oscclk0";
};
- oscclk4 {
+ clock-controller-4 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@@ -160,7 +160,7 @@
clock-output-names = "oscclk4";
};
- hdlcd_clk: oscclk5 {
+ hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
@@ -169,7 +169,7 @@
clock-output-names = "oscclk5";
};
- smbclk: oscclk6 {
+ smbclk: clock-controller-6 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
@@ -178,7 +178,7 @@
clock-output-names = "oscclk6";
};
- sys_pll: oscclk7 {
+ sys_pll: clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
@@ -187,7 +187,7 @@
clock-output-names = "oscclk7";
};
- oscclk8 {
+ clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
@@ -196,7 +196,7 @@
clock-output-names = "oscclk8";
};
- volt-cores {
+ regulator-cores {
/* CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2p-ca15_a7.dts b/dts/upstream/src/arm/arm/vexpress-v2p-ca15_a7.dts
index 511e87c..6ef23c5 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2p-ca15_a7.dts
+++ b/dts/upstream/src/arm/arm/vexpress-v2p-ca15_a7.dts
@@ -253,7 +253,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0 {
+ clock-controller-0 {
/* A15 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@@ -262,7 +262,7 @@
clock-output-names = "oscclk0";
};
- oscclk1 {
+ clock-controller-1 {
/* A15 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@@ -271,7 +271,7 @@
clock-output-names = "oscclk1";
};
- oscclk2 {
+ clock-controller-2 {
/* A7 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@@ -280,7 +280,7 @@
clock-output-names = "oscclk2";
};
- oscclk3 {
+ clock-controller-3 {
/* A7 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
@@ -289,7 +289,7 @@
clock-output-names = "oscclk3";
};
- oscclk4 {
+ clock-controller-4 {
/* External AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@@ -298,7 +298,7 @@
clock-output-names = "oscclk4";
};
- hdlcd_clk: oscclk5 {
+ hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
@@ -307,7 +307,7 @@
clock-output-names = "oscclk5";
};
- smbclk: oscclk6 {
+ smbclk: clock-controller-6 {
/* Static memory controller clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
@@ -316,7 +316,7 @@
clock-output-names = "oscclk6";
};
- oscclk7 {
+ clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
@@ -325,7 +325,7 @@
clock-output-names = "oscclk7";
};
- oscclk8 {
+ clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
@@ -334,7 +334,7 @@
clock-output-names = "oscclk8";
};
- volt-a15 {
+ regulator-a15 {
/* A15 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@@ -345,7 +345,7 @@
label = "A15 Vcore";
};
- volt-a7 {
+ regulator-a7 {
/* A7 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2p-ca5s.dts b/dts/upstream/src/arm/arm/vexpress-v2p-ca5s.dts
index ff1f9a1..e389625 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2p-ca5s.dts
+++ b/dts/upstream/src/arm/arm/vexpress-v2p-ca5s.dts
@@ -145,7 +145,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- cpu_clk: oscclk0 {
+ cpu_clk: clock-controller-0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@@ -154,7 +154,7 @@
clock-output-names = "oscclk0";
};
- axi_clk: oscclk1 {
+ axi_clk: clock-controller-1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@@ -163,7 +163,7 @@
clock-output-names = "oscclk1";
};
- oscclk2 {
+ clock-controller-2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@@ -172,7 +172,7 @@
clock-output-names = "oscclk2";
};
- hdlcd_clk: oscclk3 {
+ hdlcd_clk: clock-controller-3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
@@ -181,7 +181,7 @@
clock-output-names = "oscclk3";
};
- oscclk4 {
+ clock-controller-4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@@ -190,7 +190,7 @@
clock-output-names = "oscclk4";
};
- smbclk: oscclk5 {
+ smbclk: clock-controller-5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
diff --git a/dts/upstream/src/arm/arm/vexpress-v2p-ca9.dts b/dts/upstream/src/arm/arm/vexpress-v2p-ca9.dts
index 8bf3566..43a5a4a 100644
--- a/dts/upstream/src/arm/arm/vexpress-v2p-ca9.dts
+++ b/dts/upstream/src/arm/arm/vexpress-v2p-ca9.dts
@@ -187,7 +187,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- oscclk0: extsaxiclk {
+ oscclk0: clock-controller-0 {
/* ACLK clock to the AXI master port on the test chip */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@@ -196,7 +196,7 @@
clock-output-names = "extsaxiclk";
};
- oscclk1: clcdclk {
+ oscclk1: clock-controller-1 {
/* Reference clock for the CLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@@ -205,7 +205,7 @@
clock-output-names = "clcdclk";
};
- smbclk: oscclk2: tcrefclk {
+ smbclk: oscclk2: clock-controller-2 {
/* Reference clock for the test chip internal PLLs */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@@ -214,7 +214,7 @@
clock-output-names = "tcrefclk";
};
- volt-vd10 {
+ regulator-vd10 {
/* Test Chip internal logic voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@@ -223,7 +223,7 @@
label = "VD10";
};
- volt-vd10-s2 {
+ regulator-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
@@ -232,7 +232,7 @@
label = "VD10_S2";
};
- volt-vd10-s3 {
+ regulator-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 2>;
@@ -241,7 +241,7 @@
label = "VD10_S3";
};
- volt-vcc1v8 {
+ regulator-vcc1v8 {
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 3>;
@@ -250,7 +250,7 @@
label = "VCC1V8";
};
- volt-ddr2vtt {
+ regulator-ddr2vtt {
/* DDR2 SDRAM VTT termination voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 4>;
@@ -259,7 +259,7 @@
label = "DDR2VTT";
};
- volt-vcc3v3 {
+ regulator-vcc3v3 {
/* Local board supply for miscellaneous logic external to the Test Chip */
arm,vexpress-sysreg,func = <2 5>;
compatible = "arm,vexpress-volt";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
index 857cb26..c669ec2 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
@@ -463,7 +463,7 @@
interrupt-controller;
};
- i2c0: i2c-bus@40 {
+ i2c0: i2c@40 {
#address-cells = <1>;
#size-cells = <0>;
@@ -478,7 +478,7 @@
/* Does not need pinctrl properties */
};
- i2c1: i2c-bus@80 {
+ i2c1: i2c@80 {
#address-cells = <1>;
#size-cells = <0>;
@@ -493,7 +493,7 @@
/* Does not need pinctrl properties */
};
- i2c2: i2c-bus@c0 {
+ i2c2: i2c@c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -509,7 +509,7 @@
status = "disabled";
};
- i2c3: i2c-bus@100 {
+ i2c3: i2c@100 {
#address-cells = <1>;
#size-cells = <0>;
@@ -525,7 +525,7 @@
status = "disabled";
};
- i2c4: i2c-bus@140 {
+ i2c4: i2c@140 {
#address-cells = <1>;
#size-cells = <0>;
@@ -541,7 +541,7 @@
status = "disabled";
};
- i2c5: i2c-bus@180 {
+ i2c5: i2c@180 {
#address-cells = <1>;
#size-cells = <0>;
@@ -557,7 +557,7 @@
status = "disabled";
};
- i2c6: i2c-bus@1c0 {
+ i2c6: i2c@1c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -573,7 +573,7 @@
status = "disabled";
};
- i2c7: i2c-bus@300 {
+ i2c7: i2c@300 {
#address-cells = <1>;
#size-cells = <0>;
@@ -589,7 +589,7 @@
status = "disabled";
};
- i2c8: i2c-bus@340 {
+ i2c8: i2c@340 {
#address-cells = <1>;
#size-cells = <0>;
@@ -605,7 +605,7 @@
status = "disabled";
};
- i2c9: i2c-bus@380 {
+ i2c9: i2c@380 {
#address-cells = <1>;
#size-cells = <0>;
@@ -621,7 +621,7 @@
status = "disabled";
};
- i2c10: i2c-bus@3c0 {
+ i2c10: i2c@3c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -637,7 +637,7 @@
status = "disabled";
};
- i2c11: i2c-bus@400 {
+ i2c11: i2c@400 {
#address-cells = <1>;
#size-cells = <0>;
@@ -653,7 +653,7 @@
status = "disabled";
};
- i2c12: i2c-bus@440 {
+ i2c12: i2c@440 {
#address-cells = <1>;
#size-cells = <0>;
@@ -669,7 +669,7 @@
status = "disabled";
};
- i2c13: i2c-bus@480 {
+ i2c13: i2c@480 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
index e6f3cf3c..6e05cbc 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
@@ -592,7 +592,7 @@
interrupt-controller;
};
- i2c0: i2c-bus@40 {
+ i2c0: i2c@40 {
#address-cells = <1>;
#size-cells = <0>;
@@ -607,7 +607,7 @@
/* Does not need pinctrl properties */
};
- i2c1: i2c-bus@80 {
+ i2c1: i2c@80 {
#address-cells = <1>;
#size-cells = <0>;
@@ -622,7 +622,7 @@
/* Does not need pinctrl properties */
};
- i2c2: i2c-bus@c0 {
+ i2c2: i2c@c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -638,7 +638,7 @@
status = "disabled";
};
- i2c3: i2c-bus@100 {
+ i2c3: i2c@100 {
#address-cells = <1>;
#size-cells = <0>;
@@ -654,7 +654,7 @@
status = "disabled";
};
- i2c4: i2c-bus@140 {
+ i2c4: i2c@140 {
#address-cells = <1>;
#size-cells = <0>;
@@ -670,7 +670,7 @@
status = "disabled";
};
- i2c5: i2c-bus@180 {
+ i2c5: i2c@180 {
#address-cells = <1>;
#size-cells = <0>;
@@ -686,7 +686,7 @@
status = "disabled";
};
- i2c6: i2c-bus@1c0 {
+ i2c6: i2c@1c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -702,7 +702,7 @@
status = "disabled";
};
- i2c7: i2c-bus@300 {
+ i2c7: i2c@300 {
#address-cells = <1>;
#size-cells = <0>;
@@ -718,7 +718,7 @@
status = "disabled";
};
- i2c8: i2c-bus@340 {
+ i2c8: i2c@340 {
#address-cells = <1>;
#size-cells = <0>;
@@ -734,7 +734,7 @@
status = "disabled";
};
- i2c9: i2c-bus@380 {
+ i2c9: i2c@380 {
#address-cells = <1>;
#size-cells = <0>;
@@ -750,7 +750,7 @@
status = "disabled";
};
- i2c10: i2c-bus@3c0 {
+ i2c10: i2c@3c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -766,7 +766,7 @@
status = "disabled";
};
- i2c11: i2c-bus@400 {
+ i2c11: i2c@400 {
#address-cells = <1>;
#size-cells = <0>;
@@ -782,7 +782,7 @@
status = "disabled";
};
- i2c12: i2c-bus@440 {
+ i2c12: i2c@440 {
#address-cells = <1>;
#size-cells = <0>;
@@ -798,7 +798,7 @@
status = "disabled";
};
- i2c13: i2c-bus@480 {
+ i2c13: i2c@480 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
index 7fb4211..0c00882 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
@@ -905,7 +905,7 @@
#include "aspeed-g6-pinctrl.dtsi"
&i2c {
- i2c0: i2c-bus@80 {
+ i2c0: i2c@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80 0x80>;
@@ -919,7 +919,7 @@
status = "disabled";
};
- i2c1: i2c-bus@100 {
+ i2c1: i2c@100 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x100 0x80>;
@@ -933,7 +933,7 @@
status = "disabled";
};
- i2c2: i2c-bus@180 {
+ i2c2: i2c@180 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x180 0x80>;
@@ -947,7 +947,7 @@
status = "disabled";
};
- i2c3: i2c-bus@200 {
+ i2c3: i2c@200 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x200 0x80>;
@@ -961,7 +961,7 @@
status = "disabled";
};
- i2c4: i2c-bus@280 {
+ i2c4: i2c@280 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x280 0x80>;
@@ -975,7 +975,7 @@
status = "disabled";
};
- i2c5: i2c-bus@300 {
+ i2c5: i2c@300 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x300 0x80>;
@@ -989,7 +989,7 @@
status = "disabled";
};
- i2c6: i2c-bus@380 {
+ i2c6: i2c@380 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x380 0x80>;
@@ -1003,7 +1003,7 @@
status = "disabled";
};
- i2c7: i2c-bus@400 {
+ i2c7: i2c@400 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x400 0x80>;
@@ -1017,7 +1017,7 @@
status = "disabled";
};
- i2c8: i2c-bus@480 {
+ i2c8: i2c@480 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x480 0x80>;
@@ -1031,7 +1031,7 @@
status = "disabled";
};
- i2c9: i2c-bus@500 {
+ i2c9: i2c@500 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x500 0x80>;
@@ -1045,7 +1045,7 @@
status = "disabled";
};
- i2c10: i2c-bus@580 {
+ i2c10: i2c@580 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x580 0x80>;
@@ -1059,7 +1059,7 @@
status = "disabled";
};
- i2c11: i2c-bus@600 {
+ i2c11: i2c@600 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x600 0x80>;
@@ -1073,7 +1073,7 @@
status = "disabled";
};
- i2c12: i2c-bus@680 {
+ i2c12: i2c@680 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x680 0x80>;
@@ -1087,7 +1087,7 @@
status = "disabled";
};
- i2c13: i2c-bus@700 {
+ i2c13: i2c@700 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x700 0x80>;
@@ -1101,7 +1101,7 @@
status = "disabled";
};
- i2c14: i2c-bus@780 {
+ i2c14: i2c@780 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x780 0x80>;
@@ -1115,7 +1115,7 @@
status = "disabled";
};
- i2c15: i2c-bus@800 {
+ i2c15: i2c@800 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x800 0x80>;
diff --git a/dts/upstream/src/arm/cirrus/ep7211-edb7211.dts b/dts/upstream/src/arm/cirrus/ep7211-edb7211.dts
index 7fb532f..808cd57 100644
--- a/dts/upstream/src/arm/cirrus/ep7211-edb7211.dts
+++ b/dts/upstream/src/arm/cirrus/ep7211-edb7211.dts
@@ -30,7 +30,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: 320x240 {
+ timing0: timing-320x240 {
hactive = <320>;
hback-porch = <0>;
hfront-porch = <0>;
diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-linksys-nslu2.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-linksys-nslu2.dts
index 2eec5f6..2f7c34c 100644
--- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-linksys-nslu2.dts
@@ -90,11 +90,18 @@
timeout-ms = <5000>;
};
- gpio-beeper {
- compatible = "gpio-beeper";
+ gpio_pwm: pwm {
+ #pwm-cells = <3>;
+ compatible = "pwm-gpio";
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
+ beeper {
+ compatible = "pwm-beeper";
+ pwms = <&gpio_pwm 0 1 0>;
+ beeper-hz = <1000>;
+ };
+
soc {
bus@c4000000 {
/* The first 16MB region at CS0 on the expansion bus */
diff --git a/dts/upstream/src/arm/marvell/armada-370-xp.dtsi b/dts/upstream/src/arm/marvell/armada-370-xp.dtsi
index 0b8c2a6..954c891 100644
--- a/dts/upstream/src/arm/marvell/armada-370-xp.dtsi
+++ b/dts/upstream/src/arm/marvell/armada-370-xp.dtsi
@@ -168,7 +168,6 @@
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
- #size-cells = <1>;
interrupt-controller;
msi-controller;
};
diff --git a/dts/upstream/src/arm/marvell/armada-375.dtsi b/dts/upstream/src/arm/marvell/armada-375.dtsi
index ddc4954..99778b4 100644
--- a/dts/upstream/src/arm/marvell/armada-375.dtsi
+++ b/dts/upstream/src/arm/marvell/armada-375.dtsi
@@ -376,7 +376,6 @@
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
- #size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/armada-385-atl-x530.dts b/dts/upstream/src/arm/marvell/armada-385-atl-x530.dts
index 5a9ab84..2fb7304 100644
--- a/dts/upstream/src/arm/marvell/armada-385-atl-x530.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-atl-x530.dts
@@ -43,6 +43,17 @@
};
};
};
+
+ led-7seg {
+ compatible = "gpio-7-segment";
+ segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 1 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 2 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 3 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 4 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 5 GPIO_ACTIVE_LOW>,
+ <&led_7seg_gpio 6 GPIO_ACTIVE_LOW>;
+ };
};
&pciec {
@@ -149,7 +160,7 @@
#size-cells = <0>;
reg = <3>;
- gpio@20 {
+ led_7seg_gpio: gpio@20 {
compatible = "nxp,pca9554";
gpio-controller;
#gpio-cells = <2>;
diff --git a/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts b/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
index 7b755bb..4320289 100644
--- a/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
@@ -112,6 +112,19 @@
status = "disabled";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ front-button {
+ label = "Front Button";
+ linux,code = <KEY_VENDOR>;
+ linux,can-disable;
+ gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>;
+ /* debouncing is done by the microcontroller */
+ debounce-interval = <0>;
+ };
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
@@ -218,7 +231,22 @@
#size-cells = <0>;
reg = <0>;
+ mcu: system-controller@2a {
+ compatible = "cznic,turris-omnia-mcu";
+ reg = <0x2a>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_pins>;
+
- /* STM32F0 command interface at address 0x2a */
+ interrupt-parent = <&gpio1>;
+ interrupts = <11 IRQ_TYPE_NONE>;
+
+ gpio-controller;
+ #gpio-cells = <3>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
led-controller@2b {
compatible = "cznic,turris-omnia-leds";
@@ -501,6 +529,11 @@
};
&pinctrl {
+ mcu_pins: mcu-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+
pcawan_pins: pcawan-pins {
marvell,pins = "mpp46";
marvell,function = "gpio";
diff --git a/dts/upstream/src/arm/marvell/armada-38x.dtsi b/dts/upstream/src/arm/marvell/armada-38x.dtsi
index 446861b..1181b13 100644
--- a/dts/upstream/src/arm/marvell/armada-38x.dtsi
+++ b/dts/upstream/src/arm/marvell/armada-38x.dtsi
@@ -408,7 +408,6 @@
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
- #size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/armada-39x.dtsi b/dts/upstream/src/arm/marvell/armada-39x.dtsi
index 9d1cac4..6d05835 100644
--- a/dts/upstream/src/arm/marvell/armada-39x.dtsi
+++ b/dts/upstream/src/arm/marvell/armada-39x.dtsi
@@ -268,7 +268,6 @@
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
- #size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-blackarmor-nas220.dts b/dts/upstream/src/arm/marvell/kirkwood-blackarmor-nas220.dts
index 07fbfca..36b90c6 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-blackarmor-nas220.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-blackarmor-nas220.dts
@@ -35,13 +35,13 @@
gpio_keys {
compatible = "gpio-keys";
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_POWER>;
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
- button {
+ button-power {
label = "Power";
linux,code = <KEY_SLEEP>;
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
@@ -51,7 +51,7 @@
gpio-leds {
compatible = "gpio-leds";
- blue-power {
+ led-blue-power {
label = "nas220:blue:power";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-c200-v1.dts b/dts/upstream/src/arm/marvell/kirkwood-c200-v1.dts
index f59ff75..7e3ee64 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-c200-v1.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-c200-v1.dts
@@ -29,25 +29,25 @@
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
- usb1 {
+ button-usb1 {
label = "USB1 Button";
linux,code = <BTN_0>;
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
- usb2 {
+ button-usb2 {
label = "USB2 Button";
linux,code = <BTN_1>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-cloudbox.dts b/dts/upstream/src/arm/marvell/kirkwood-cloudbox.dts
index 448b0cd..151edcd 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-cloudbox.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-cloudbox.dts
@@ -58,10 +58,8 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ key-power {
label = "Power push button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
@@ -71,11 +69,11 @@
gpio-leds {
compatible = "gpio-leds";
- red-fail {
+ led-red-fail {
label = "cloudbox:red:fail";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
- blue-sata {
+ led-blue-sata {
label = "cloudbox:blue:sata";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-d2net.dts b/dts/upstream/src/arm/marvell/kirkwood-d2net.dts
index bd3b266..fcce873 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-d2net.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-d2net.dts
@@ -37,7 +37,7 @@
gpio-leds {
compatible = "gpio-leds";
- red-fail {
+ led-red-fail {
label = "d2net_v2:red:fail";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dir665.dts b/dts/upstream/src/arm/marvell/kirkwood-dir665.dts
index 0c0851c..2f6793f 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dir665.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-dir665.dts
@@ -137,38 +137,38 @@
gpio-leds {
compatible = "gpio-leds";
- blue-usb {
+ led-blue-usb {
label = "dir665:blue:usb";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- blue-internet {
+ led-blue-internet {
/* Can only be turned on if the Internet
* Ethernet port has Link
*/
label = "dir665:blue:internet";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
- amber-internet {
+ led-amber-internet {
label = "dir665:amber:internet";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
- blue-wifi5g {
+ led-blue-wifi5g {
label = "dir665:blue:5g";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
- blue-status {
+ led-blue-status {
label = "dir665:blue:status";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- blue-wps {
+ led-blue-wps {
label = "dir665:blue:wps";
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
};
- amber-status {
+ led-amber-status {
label = "dir665:amber:status";
gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
};
- blue-24g {
+ led-blue-24g {
label = "dir665:blue:24g";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
@@ -176,15 +176,13 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- reset {
+ button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dns320.dts b/dts/upstream/src/arm/marvell/kirkwood-dns320.dts
index d6b0f41..d8279e0 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dns320.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-dns320.dts
@@ -24,24 +24,24 @@
&pmx_led_white_usb>;
pinctrl-names = "default";
- blue-power {
+ led-blue-power {
label = "dns320:blue:power";
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- blue-usb {
+ led-blue-usb {
label = "dns320:blue:usb";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
- orange-l_hdd {
+ led-orange-l_hdd {
label = "dns320:orange:l_hdd";
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
- orange-r_hdd {
+ led-orange-r_hdd {
label = "dns320:orange:r_hdd";
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
- orange-usb {
+ led-orange-usb {
label = "dns320:orange:usb";
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dns325.dts b/dts/upstream/src/arm/marvell/kirkwood-dns325.dts
index 94d9c06..7f39619 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dns325.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-dns325.dts
@@ -24,24 +24,24 @@
&pmx_led_white_usb>;
pinctrl-names = "default";
- white-power {
+ led-white-power {
label = "dns325:white:power";
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- white-usb {
+ led-white-usb {
label = "dns325:white:usb";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
};
- red-l_hdd {
+ led-red-l_hdd {
label = "dns325:red:l_hdd";
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
};
- red-r_hdd {
+ led-red-r_hdd {
label = "dns325:red:r_hdd";
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
- red-usb {
+ led-red-usb {
label = "dns325:red:usb";
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi b/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
index 0738eb6..20bcd03 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
@@ -8,23 +8,21 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_power &pmx_button_unmount
&pmx_button_reset>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
- eject {
+ button-eject {
label = "USB unmount button";
linux,code = <KEY_EJECTCD>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dockstar.dts b/dts/upstream/src/arm/marvell/kirkwood-dockstar.dts
index 264938d..090f1e2 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dockstar.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-dockstar.dts
@@ -42,12 +42,12 @@
pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
pinctrl-names = "default";
- health {
+ led-health {
label = "status:green:health";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- fault {
+ led-fault {
label = "status:orange:fault";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts b/dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts
index 3285163..590bee3 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-dreamplug.dts
@@ -85,15 +85,15 @@
&pmx_led_wifi_ap >;
pinctrl-names = "default";
- bluetooth {
+ led-bluetooth {
label = "dreamplug:blue:bluetooth";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- wifi {
+ led-wifi {
label = "dreamplug:green:wifi";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
- wifi-ap {
+ led-wifi-ap {
label = "dreamplug:green:wifi_ap";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts b/dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts
index d4cb3cd..d5ac4e3 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-goflexnet.dts
@@ -85,44 +85,44 @@
>;
pinctrl-names = "default";
- health {
+ led-health {
label = "status:green:health";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- fault {
+ led-fault {
label = "status:orange:fault";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- left0 {
+ led-left0 {
label = "status:white:left0";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- left1 {
+ led-left1 {
label = "status:white:left1";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
- left2 {
+ led-left2 {
label = "status:white:left2";
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
- left3 {
+ led-left3 {
label = "status:white:left3";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- right0 {
+ led-right0 {
label = "status:white:right0";
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
- right1 {
+ led-right1 {
label = "status:white:right1";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
- right2 {
+ led-right2 {
label = "status:white:right2";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
- right3 {
+ led-right3 {
label = "status:white:right3";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts b/dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts
index dfb4139..d5aa8b5 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-guruplug-server-plus.dts
@@ -59,19 +59,19 @@
&pmx_led_wmode_r &pmx_led_wmode_g >;
pinctrl-names = "default";
- health-r {
+ led-health-r {
label = "guruplug:red:health";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
- health-g {
+ led-health-g {
label = "guruplug:green:health";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- wmode-r {
+ led-wmode-r {
label = "guruplug:red:wmode";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
- wmode-g {
+ led-wmode-g {
label = "guruplug:green:wmode";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ib62x0.dts b/dts/upstream/src/arm/marvell/kirkwood-ib62x0.dts
index 962a910..018c6b8 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ib62x0.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ib62x0.dts
@@ -58,17 +58,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
pinctrl-names = "default";
- copy {
+ button-copy {
label = "USB Copy";
linux,code = <KEY_COPY>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
@@ -81,16 +79,16 @@
&pmx_led_usb_transfer>;
pinctrl-names = "default";
- green-os {
+ led-green-os {
label = "ib62x0:green:os";
gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
- red-os {
+ led-red-os {
label = "ib62x0:red:os";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
};
- usb-copy {
+ led-usb-copy {
label = "ib62x0:red:usb_copy";
gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-iconnect.dts b/dts/upstream/src/arm/marvell/kirkwood-iconnect.dts
index aed2018..91b46e7 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-iconnect.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-iconnect.dts
@@ -89,32 +89,32 @@
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- power-blue {
+ led-power-blue {
label = "power:blue";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
- power-red {
+ led-power-red {
label = "power:red";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
- usb1 {
+ led-usb1 {
label = "usb1:blue";
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
- usb2 {
+ led-usb2 {
label = "usb2:blue";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- usb3 {
+ led-usb3 {
label = "usb3:blue";
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
- usb4 {
+ led-usb4 {
label = "usb4:blue";
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
};
- otb {
+ led-otb {
label = "otb:blue";
gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
};
@@ -122,18 +122,16 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
pinctrl-names = "default";
- otb {
+ button-otb {
label = "OTB Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-iomega_ix2_200.dts b/dts/upstream/src/arm/marvell/kirkwood-iomega_ix2_200.dts
index 2338f49..0393621 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-iomega_ix2_200.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-iomega_ix2_200.dts
@@ -127,44 +127,42 @@
&pmx_led_rebuild &pmx_led_health >;
pinctrl-names = "default";
- power_led {
+ led-power-led {
label = "status:white:power_led";
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
- rebuild_led {
+ led-rebuild-led {
label = "status:white:rebuild_led";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
- health_led {
+ led-health-led {
label = "status:red:health_led";
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
- backup_led {
+ led-backup-led {
label = "status:blue:backup_led";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_reset &pmx_button_power
&pmx_button_otb>;
pinctrl-names = "default";
- Power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
- Reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
- OTB {
+ button-otb {
label = "OTB Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-l-50.dts b/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
index c841eb8..974bc9d 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
@@ -97,52 +97,52 @@
leds {
compatible = "gpio-leds";
- status_green {
+ led-status-green {
label = "l-50:green:status";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
- status_red {
+ led-status-red {
label = "l-50:red:status";
gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
};
- wifi {
+ led-wifi {
label = "l-50:green:wifi";
gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
- internet_green {
+ led-internet-green {
label = "l-50:green:internet";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
};
- internet_red {
+ led-internet-red {
label = "l-50:red:internet";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
- usb1_green {
+ led-usb1-green {
label = "l-50:green:usb1";
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port3>;
};
- usb1_red {
+ led-usb1-red {
label = "l-50:red:usb1";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
- usb2_green {
+ led-usb2-green {
label = "l-50:green:usb2";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port1>;
};
- usb2_red {
+ led-usb2-red {
label = "l-50:red:usb2";
gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
};
@@ -193,7 +193,7 @@
keys {
compatible = "gpio-keys";
- factory_defaults {
+ button-factory-defaults {
label = "factory_defaults";
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-laplug.dts b/dts/upstream/src/arm/marvell/kirkwood-laplug.dts
index 8c2b540..90ea6cd 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-laplug.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-laplug.dts
@@ -51,7 +51,7 @@
gpio_keys {
compatible = "gpio-keys";
- power {
+ button-power {
label = "Power push button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
@@ -61,11 +61,11 @@
gpio-leds {
compatible = "gpio-leds";
- red-fail {
+ led-red-fail {
label = "laplug_v2:red:power";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- blue-power {
+ led-blue-power {
label = "laplug_v2:blue:power";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-linkstation.dtsi b/dts/upstream/src/arm/marvell/kirkwood-linkstation.dtsi
index b54c998..8a11d2b 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-linkstation.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-linkstation.dtsi
@@ -88,8 +88,6 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_function &pmx_power_switch
&pmx_power_auto_switch>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-linksys-viper.dts b/dts/upstream/src/arm/marvell/kirkwood-linksys-viper.dts
index 27fd6e2..8a1c38a 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-linksys-viper.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-linksys-viper.dts
@@ -33,18 +33,16 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
pinctrl-names = "default";
- wps {
+ button-wps {
label = "WPS Button";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
@@ -56,12 +54,12 @@
pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;
pinctrl-names = "default";
- white-health {
+ led-white-health {
label = "viper:white:health";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
- white-pulse {
+ led-white-pulse {
label = "viper:white:pulse";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi b/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
index f80af24..5e0b139 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
@@ -107,24 +107,22 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_function &pmx_power_switch
&pmx_power_auto_switch>;
pinctrl-names = "default";
- option {
+ button-option {
label = "Function Button";
linux,code = <KEY_OPTION>;
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
- reserved {
+ button-reserved {
label = "Power-on Switch";
linux,code = <KEY_RESERVED>;
linux,input-type = <5>;
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
- power {
+ button-power {
label = "Power-auto Switch";
linux,code = <KEY_ESC>;
linux,input-type = <5>;
@@ -139,28 +137,28 @@
&pmx_led_function_blue>;
pinctrl-names = "default";
- func_blue {
+ led-func-blue {
label = "lsxl:blue:func";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
- alarm {
+ led-alarm {
label = "lsxl:red:alarm";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
- info {
+ led-info {
label = "lsxl:amber:info";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
- power {
+ led-power {
label = "lsxl:blue:power";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- func_red {
+ led-func-red {
label = "lsxl:red:func";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-mplcec4.dts b/dts/upstream/src/arm/marvell/kirkwood-mplcec4.dts
index e87ea71..6533b49 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-mplcec4.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-mplcec4.dts
@@ -114,36 +114,36 @@
>;
pinctrl-names = "default";
- health {
+ led-health {
label = "status:green:health";
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
};
- user1o {
+ led-user1o {
label = "user1:orange";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- user1g {
+ led-user1g {
label = "user1:green";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- user0o {
+ led-user0o {
label = "user0:orange";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- user0g {
+ led-user0g {
label = "user0:green";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- misc {
+ led-misc {
label = "status:orange:misc";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
default-state = "on";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-mv88f6281gtw-ge.dts b/dts/upstream/src/arm/marvell/kirkwood-mv88f6281gtw-ge.dts
index 5a77286..e3b4178 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-mv88f6281gtw-ge.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-mv88f6281gtw-ge.dts
@@ -73,17 +73,17 @@
pinctrl-0 = <&pmx_leds &pmx_usb_led>;
pinctrl-names = "default";
- green-status {
+ led-green-status {
label = "gtw:green:Status";
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
};
- red-status {
+ led-red-status {
label = "gtw:red:Status";
gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
};
- green-usb {
+ led-green-usb {
label = "gtw:green:USB";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
@@ -91,17 +91,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_keys>;
pinctrl-names = "default";
- restart {
+ button-restart {
label = "SWR Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- wps {
+ button-wps {
label = "WPS Button";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-netxbig.dtsi b/dts/upstream/src/arm/marvell/kirkwood-netxbig.dtsi
index b573702..d4edf27 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-netxbig.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-netxbig.dtsi
@@ -53,26 +53,24 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
/*
* esc and power represent a three position rocker
* switch. Thus the conventional KEY_POWER does not fit
*/
- exc {
+ button-exc {
label = "Back power switch (on|auto)";
linux,code = <KEY_ESC>;
linux,input-type = <5>;
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
};
- power {
+ button-power {
label = "Back power switch (auto|off)";
linux,code = <KEY_1>;
linux,input-type = <5>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
- option {
+ button-option {
label = "Function button";
linux,code = <KEY_OPTION>;
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ns2-common.dtsi b/dts/upstream/src/arm/marvell/kirkwood-ns2-common.dtsi
index 51530ea..d6b615c 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ns2-common.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-ns2-common.dtsi
@@ -55,10 +55,8 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ button-power {
label = "Power push button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
@@ -68,7 +66,7 @@
gpio-leds {
compatible = "gpio-leds";
- red-fail {
+ led-red-fail {
label = "ns2:red:fail";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ns2lite.dts b/dts/upstream/src/arm/marvell/kirkwood-ns2lite.dts
index b0cb590..686bcd6 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ns2lite.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ns2lite.dts
@@ -24,7 +24,7 @@
gpio-leds {
compatible = "gpio-leds";
- blue-sata {
+ led-blue-sata {
label = "ns2:blue:sata";
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
linux,default-trigger = "disk-activity";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa310.dts b/dts/upstream/src/arm/marvell/kirkwood-nsa310.dts
index c1799a0..3555ac1 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa310.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa310.dts
@@ -87,43 +87,43 @@
&pmx_led_hdd_green &pmx_led_hdd_red>;
pinctrl-names = "default";
- green-sys {
+ led-green-sys {
label = "nsa310:green:sys";
gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
};
- red-sys {
+ led-red-sys {
label = "nsa310:red:sys";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
- green-hdd {
+ led-green-hdd {
label = "nsa310:green:hdd";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
- red-hdd {
+ led-red-hdd {
label = "nsa310:red:hdd";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- green-esata {
+ led-green-esata {
label = "nsa310:green:esata";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- red-esata {
+ led-red-esata {
label = "nsa310:red:esata";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
- green-usb {
+ led-green-usb {
label = "nsa310:green:usb";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
- red-usb {
+ led-red-usb {
label = "nsa310:red:usb";
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
};
- green-copy {
+ led-green-copy {
label = "nsa310:green:copy";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
- red-copy {
+ led-red-copy {
label = "nsa310:red:copy";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa310a.dts b/dts/upstream/src/arm/marvell/kirkwood-nsa310a.dts
index b85e314..ddf8409 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa310a.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa310a.dts
@@ -75,39 +75,39 @@
gpio-leds {
compatible = "gpio-leds";
- green-sys {
+ led-green-sys {
label = "nsa310:green:sys";
gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
};
- red-sys {
+ led-red-sys {
label = "nsa310:red:sys";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
- green-hdd {
+ led-green-hdd {
label = "nsa310:green:hdd";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
- red-hdd {
+ led-red-hdd {
label = "nsa310:red:hdd";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- green-esata {
+ led-green-esata {
label = "nsa310:green:esata";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- red-esata {
+ led-red-esata {
label = "nsa310:red:esata";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
- green-usb {
+ led-green-usb {
label = "nsa310:green:usb";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
- green-copy {
+ led-green-copy {
label = "nsa310:green:copy";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
- red-copy {
+ led-red-copy {
label = "nsa310:red:copy";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts b/dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts
index 49da633..47deb93 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa310s.dts
@@ -35,24 +35,22 @@
keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
};
- copy {
+ button-copy {
label = "Copy Button";
linux,code = <KEY_COPY>;
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa320.dts b/dts/upstream/src/arm/marvell/kirkwood-nsa320.dts
index 652405e..dd5c8ff 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa320.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa320.dts
@@ -142,39 +142,39 @@
&pmx_led_hdd1_green &pmx_led_hdd1_red>;
pinctrl-names = "default";
- green-sys {
+ led-green-sys {
label = "nsa320:green:sys";
gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
};
- orange-sys {
+ led-orange-sys {
label = "nsa320:orange:sys";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
- green-hdd1 {
+ led-green-hdd1 {
label = "nsa320:green:hdd1";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
- red-hdd1 {
+ led-red-hdd1 {
label = "nsa320:red:hdd1";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- green-hdd2 {
+ led-green-hdd2 {
label = "nsa320:green:hdd2";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- red-hdd2 {
+ led-red-hdd2 {
label = "nsa320:red:hdd2";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
- green-usb {
+ led-green-usb {
label = "nsa320:green:usb";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
- green-copy {
+ led-green-copy {
label = "nsa320:green:copy";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
- red-copy {
+ led-red-copy {
label = "nsa320:red:copy";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa325.dts b/dts/upstream/src/arm/marvell/kirkwood-nsa325.dts
index 371456d..f0786a5 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa325.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa325.dts
@@ -162,39 +162,39 @@
&pmx_led_hdd1_green &pmx_led_hdd1_red>;
pinctrl-names = "default";
- green-sys {
+ led-green-sys {
label = "nsa325:green:sys";
gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
};
- orange-sys {
+ led-orange-sys {
label = "nsa325:orange:sys";
gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};
- green-hdd1 {
+ led-green-hdd1 {
label = "nsa325:green:hdd1";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
- red-hdd1 {
+ led-red-hdd1 {
label = "nsa325:red:hdd1";
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- green-hdd2 {
+ led-green-hdd2 {
label = "nsa325:green:hdd2";
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
};
- red-hdd2 {
+ led-red-hdd2 {
label = "nsa325:red:hdd2";
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
- green-usb {
+ led-green-usb {
label = "nsa325:green:usb";
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
};
- green-copy {
+ led-green-copy {
label = "nsa325:green:copy";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
- red-copy {
+ led-red-copy {
label = "nsa325:red:copy";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi b/dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi
index ea3d365..e9bd9c5 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-nsa3x0-common.dtsi
@@ -63,22 +63,20 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
- copy {
+ button-copy {
label = "Copy Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-openblocks_a6.dts b/dts/upstream/src/arm/marvell/kirkwood-openblocks_a6.dts
index 8ea4301..20c6290 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-openblocks_a6.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-openblocks_a6.dts
@@ -115,10 +115,8 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_gpio_init>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+ button-power {
label = "Init Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-openblocks_a7.dts b/dts/upstream/src/arm/marvell/kirkwood-openblocks_a7.dts
index 946f0f4..9c438f1 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-openblocks_a7.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-openblocks_a7.dts
@@ -136,8 +136,6 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_gpio_init>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
button {
label = "Init Button";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-pogo_e02.dts b/dts/upstream/src/arm/marvell/kirkwood-pogo_e02.dts
index f9e95e5..39a5345 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-pogo_e02.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-pogo_e02.dts
@@ -33,12 +33,12 @@
gpio-leds {
compatible = "gpio-leds";
- health {
+ led-health {
label = "pogo_e02:green:health";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- fault {
+ led-fault {
label = "pogo_e02:orange:fault";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-pogoplug-series-4.dts b/dts/upstream/src/arm/marvell/kirkwood-pogoplug-series-4.dts
index 5aa4669..0e9c4cf 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-pogoplug-series-4.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-pogoplug-series-4.dts
@@ -29,12 +29,10 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_eject>;
pinctrl-names = "default";
- eject {
+ button-eject {
debounce-interval = <50>;
wakeup-source;
linux,code = <KEY_EJECTCD>;
@@ -48,12 +46,12 @@
pinctrl-0 = <&pmx_led_green &pmx_led_red>;
pinctrl-names = "default";
- health {
+ led-health {
label = "pogoplugv4:green:health";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- fault {
+ led-fault {
label = "pogoplugv4:red:fault";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-sheevaplug-esata.dts b/dts/upstream/src/arm/marvell/kirkwood-sheevaplug-esata.dts
index ae8f493..eb18527 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-sheevaplug-esata.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-sheevaplug-esata.dts
@@ -33,7 +33,7 @@
pinctrl-0 = <&pmx_led_blue>;
pinctrl-names = "default";
- health {
+ led-health {
label = "sheevaplug:blue:health";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/dts/upstream/src/arm/marvell/kirkwood-sheevaplug.dts b/dts/upstream/src/arm/marvell/kirkwood-sheevaplug.dts
index c73cc90..ce73fcf 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-sheevaplug.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-sheevaplug.dts
@@ -28,13 +28,13 @@
pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
pinctrl-names = "default";
- health {
+ led-health {
label = "sheevaplug:blue:health";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- misc {
+ led-misc {
label = "sheevaplug:red:misc";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi b/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
index 20964eb..6b7c521 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
@@ -410,7 +410,7 @@
pinctrl-0 = <&pmx_alarmled_12>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:alarm";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
@@ -424,42 +424,42 @@
&pmx_hddled_26 &pmx_hddled_27>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
};
- hdd1-amber {
+ led-hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
- hdd2-green {
+ led-hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
};
- hdd2-amber {
+ led-hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
- hdd3-green {
+ led-hdd3-green {
label = "synology:green:hdd3";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
- hdd3-amber {
+ led-hdd3-amber {
label = "synology:amber:hdd3";
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
- hdd4-green {
+ led-hdd4-green {
label = "synology:green:hdd4";
gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
};
- hdd4-amber {
+ led-hdd4-amber {
label = "synology:amber:hdd4";
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
};
@@ -471,12 +471,12 @@
pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
- hdd1-amber {
+ led-hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
@@ -488,22 +488,22 @@
pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
};
- hdd1-amber {
+ led-hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
};
- hdd2-green {
+ led-hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
};
- hdd2-amber {
+ led-hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
};
@@ -518,52 +518,52 @@
&pmx_hddled_45>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
- hdd1-amber {
+ led-hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
- hdd2-green {
+ led-hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
- hdd2-amber {
+ led-hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
- hdd3-green {
+ led-hdd3-green {
label = "synology:green:hdd3";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
- hdd3-amber {
+ led-hdd3-amber {
label = "synology:amber:hdd3";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
- hdd4-green {
+ led-hdd4-green {
label = "synology:green:hdd4";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
- hdd4-amber {
+ led-hdd4-amber {
label = "synology:amber:hdd4";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
- hdd5-green {
+ led-hdd5-green {
label = "synology:green:hdd5";
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
- hdd5-amber {
+ led-hdd5-amber {
label = "synology:amber:hdd5";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
@@ -575,22 +575,22 @@
pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
pinctrl-names = "default";
- hdd1-green {
+ led-hdd1-green {
label = "synology:green:hdd1";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
- hdd1-amber {
+ led-hdd1-amber {
label = "synology:amber:hdd1";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
- hdd2-green {
+ led-hdd2-green {
label = "synology:green:hdd2";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
- hdd2-amber {
+ led-hdd2-amber {
label = "synology:amber:hdd2";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-t5325.dts b/dts/upstream/src/arm/marvell/kirkwood-t5325.dts
index ad09332..a6e77a4 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-t5325.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-t5325.dts
@@ -156,12 +156,10 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_button_power>;
pinctrl-names = "default";
- power {
+ button-power {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ts219-6281.dts b/dts/upstream/src/arm/marvell/kirkwood-ts219-6281.dts
index 30892c1..a2e0ad4 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ts219-6281.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ts219-6281.dts
@@ -35,17 +35,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
pinctrl-names = "default";
- copy {
+ button-copy {
label = "USB Copy";
linux,code = <KEY_COPY>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ts219-6282.dts b/dts/upstream/src/arm/marvell/kirkwood-ts219-6282.dts
index aba1205..35be6bc 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ts219-6282.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ts219-6282.dts
@@ -35,17 +35,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
pinctrl-names = "default";
- copy {
+ button-copy {
label = "USB Copy";
linux,code = <KEY_COPY>;
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ts419.dtsi b/dts/upstream/src/arm/marvell/kirkwood-ts419.dtsi
index 7172368..f136059 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ts419.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-ts419.dtsi
@@ -36,17 +36,15 @@
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
pinctrl-names = "default";
- copy {
+ button-copy {
label = "USB Copy";
linux,code = <KEY_COPY>;
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
- reset {
+ button-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/mvebu-linkstation-gpio-simple.dtsi b/dts/upstream/src/arm/marvell/mvebu-linkstation-gpio-simple.dtsi
index c2d87ba..055ac75 100644
--- a/dts/upstream/src/arm/marvell/mvebu-linkstation-gpio-simple.dtsi
+++ b/dts/upstream/src/arm/marvell/mvebu-linkstation-gpio-simple.dtsi
@@ -48,8 +48,6 @@
/ {
gpio_keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-0 = <&pmx_power_switch>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/marvell/orion5x-lacie-d2-network.dts b/dts/upstream/src/arm/marvell/orion5x-lacie-d2-network.dts
index 03471d3..12a4aac 100644
--- a/dts/upstream/src/arm/marvell/orion5x-lacie-d2-network.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-lacie-d2-network.dts
@@ -35,22 +35,21 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- front_button {
+
+ button-front {
label = "Front Push Button";
linux,code = <KEY_POWER>;
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
};
- power_rocker_sw_on {
+ switch-power-rocker-sw-on {
label = "Power rocker switch (on|auto)";
linux,input-type = <5>; /* EV_SW */
linux,code = <1>; /* D2NET_SWITCH_POWER_ON */
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
};
- power_rocker_sw_off {
+ switch-power-rocker-sw-off {
label = "Power rocker switch (auto|off)";
linux,input-type = <5>; /* EV_SW */
linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */
diff --git a/dts/upstream/src/arm/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts b/dts/upstream/src/arm/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts
index f17e25a..f81acb9 100644
--- a/dts/upstream/src/arm/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -39,9 +39,8 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_power_button>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- button@1 {
+
+ button-1 {
label = "Power-on Switch";
linux,code = <KEY_POWER>;
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
@@ -53,7 +52,7 @@
pinctrl-0 = <&pmx_power_led>;
pinctrl-names = "default";
- led@1 {
+ led-1 {
label = "power:blue";
gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/orion5x-linkstation-lschl.dts b/dts/upstream/src/arm/marvell/orion5x-linkstation-lschl.dts
index ee75199..79fee04 100644
--- a/dts/upstream/src/arm/marvell/orion5x-linkstation-lschl.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-linkstation-lschl.dts
@@ -61,7 +61,7 @@
};
gpio_keys {
- func {
+ func-button {
label = "Function Button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
@@ -90,7 +90,7 @@
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
- func {
+ func-led {
label = "lschl:func:blue:top";
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/orion5x-lswsgl.dts b/dts/upstream/src/arm/marvell/orion5x-lswsgl.dts
index 2fbc17d..e0da406 100644
--- a/dts/upstream/src/arm/marvell/orion5x-lswsgl.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-lswsgl.dts
@@ -74,22 +74,21 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- func {
+
+ key-func {
label = "Function Button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
};
- power {
+ key-power {
label = "Power-on Switch";
linux,input-type = <5>; /* EV_SW */
linux,code = <KEY_RESERVED>; /* LSMINI_SW_POWER */
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
};
- autopower {
+ key-autopower {
label = "Power-auto Switch";
linux,input-type = <5>; /* EV_SW */
linux,code = <KEY_ESC>; /* LSMINI_SW_AUTOPOWER */
@@ -103,24 +102,24 @@
&pmx_led_power>;
pinctrl-names = "default";
- alarm {
+ led-alarm {
label = "lswsgl:alarm:red";
- gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
};
- info {
+ led-info {
label = "lswsgl:info:amber";
- gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};
- func {
+ led-func {
label = "lswsgl:func:blue:top";
- gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
- power {
+ led-power {
label = "lswsgl:power:blue:bottom";
- gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
diff --git a/dts/upstream/src/arm/marvell/orion5x-maxtor-shared-storage-2.dts b/dts/upstream/src/arm/marvell/orion5x-maxtor-shared-storage-2.dts
index d578599..cb1bd24 100644
--- a/dts/upstream/src/arm/marvell/orion5x-maxtor-shared-storage-2.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-maxtor-shared-storage-2.dts
@@ -35,15 +35,14 @@
compatible = "gpio-keys";
pinctrl-0 = <&pmx_buttons>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- power {
+
+ key-power {
label = "Power";
linux,code = <KEY_POWER>;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
};
- reset {
+ key-reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/orion5x-netgear-wnr854t.dts b/dts/upstream/src/arm/marvell/orion5x-netgear-wnr854t.dts
index fb203e7..d63ea15 100644
--- a/dts/upstream/src/arm/marvell/orion5x-netgear-wnr854t.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-netgear-wnr854t.dts
@@ -35,7 +35,7 @@
pinctrl-0 = <&pmx_reset_button>;
pinctrl-names = "default";
- reset {
+ key-reset {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/marvell/orion5x-rd88f5182-nas.dts b/dts/upstream/src/arm/marvell/orion5x-rd88f5182-nas.dts
index fd78aa0..75ab913 100644
--- a/dts/upstream/src/arm/marvell/orion5x-rd88f5182-nas.dts
+++ b/dts/upstream/src/arm/marvell/orion5x-rd88f5182-nas.dts
@@ -32,7 +32,7 @@
pinctrl-0 = <&pmx_debug_led>;
pinctrl-names = "default";
- led@0 {
+ led-0 {
label = "rd88f5182:cpu";
linux,default-trigger = "heartbeat";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm/mediatek/mt2701-evb.dts b/dts/upstream/src/arm/mediatek/mt2701-evb.dts
index 9c7325f..4c76366 100644
--- a/dts/upstream/src/arm/mediatek/mt2701-evb.dts
+++ b/dts/upstream/src/arm/mediatek/mt2701-evb.dts
@@ -231,7 +231,7 @@
<MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
<MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
<MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up;
};
};
diff --git a/dts/upstream/src/arm/mediatek/mt7623.dtsi b/dts/upstream/src/arm/mediatek/mt7623.dtsi
index f0b4a09..814586a 100644
--- a/dts/upstream/src/arm/mediatek/mt7623.dtsi
+++ b/dts/upstream/src/arm/mediatek/mt7623.dtsi
@@ -1143,13 +1143,13 @@
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <2>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <2>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
@@ -1167,14 +1167,14 @@
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
bias-pull-down;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
};
pins-wp {
@@ -1197,13 +1197,13 @@
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
@@ -1211,7 +1211,7 @@
nand_pins_default: nanddefault {
pins-ale {
pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -1226,13 +1226,13 @@
<MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
<MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up;
};
pins-we {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
};
diff --git a/dts/upstream/src/arm/nspire/nspire-classic.dtsi b/dts/upstream/src/arm/nspire/nspire-classic.dtsi
index a6e9cbf..0ee53d3 100644
--- a/dts/upstream/src/arm/nspire/nspire-classic.dtsi
+++ b/dts/upstream/src/arm/nspire/nspire-classic.dtsi
@@ -55,7 +55,7 @@
};
/ {
- memory {
+ memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x2000000>; /* 32 MB */
};
diff --git a/dts/upstream/src/arm/nspire/nspire-cx.dts b/dts/upstream/src/arm/nspire/nspire-cx.dts
index 29f0181..debeff0 100644
--- a/dts/upstream/src/arm/nspire/nspire-cx.dts
+++ b/dts/upstream/src/arm/nspire/nspire-cx.dts
@@ -122,7 +122,7 @@
model = "TI-NSPIRE CX";
compatible = "ti,nspire-cx";
- memory {
+ memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x4000000>; /* 64 MB */
};
diff --git a/dts/upstream/src/arm/nspire/nspire.dtsi b/dts/upstream/src/arm/nspire/nspire.dtsi
index d56fef7..95588b7 100644
--- a/dts/upstream/src/arm/nspire/nspire.dtsi
+++ b/dts/upstream/src/arm/nspire/nspire.dtsi
@@ -170,9 +170,12 @@
};
watchdog: watchdog@90060000 {
- compatible = "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x90060000 0x1000>;
interrupts = <3>;
+ clocks = <&apb_pclk>, <&apb_pclk>;
+ clock-names = "wdog_clk", "apb_pclk";
+ status = "disabled";
};
rtc: rtc@90090000 {
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-kudo.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-kudo.dts
index 5787ae9..1f07ba3 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-kudo.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-kudo.dts
@@ -525,7 +525,7 @@
};
};
- i2c-bus@4 {
+ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -537,7 +537,7 @@
};
};
- i2c-bus@5 {
+ i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
@@ -549,7 +549,7 @@
};
};
- i2c-bus@6 {
+ i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
@@ -561,7 +561,7 @@
};
};
- i2c-bus@7 {
+ i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
@@ -580,7 +580,7 @@
reg = <0x77>;
i2c-mux-idle-disconnect;
- i2c-bus@2 {
+ i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@@ -620,7 +620,7 @@
reg = <0x77>;
i2c-mux-idle-disconnect;
- i2c-bus@0 {
+ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -632,7 +632,7 @@
};
};
- i2c-bus@1 {
+ i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -691,7 +691,7 @@
reg = <0x77>;
i2c-mux-idle-disconnect;
- i2c-bus@3 {
+ i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
@@ -703,7 +703,7 @@
};
};
- i2c-bus@4 {
+ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -715,7 +715,7 @@
};
};
- i2c-bus@5 {
+ i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
@@ -726,7 +726,7 @@
reg = <0x28>;
};
};
- i2c-bus@6 {
+ i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
index baa39d0..087f4ac 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
@@ -215,43 +215,43 @@
reg = <0x70>;
i2c-mux-idle-disconnect;
- i2c_slot1a: i2c-bus@0 {
+ i2c_slot1a: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
- i2c_slot1b: i2c-bus@1 {
+ i2c_slot1b: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
- i2c_slot2a: i2c-bus@2 {
+ i2c_slot2a: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
- i2c_slot2b: i2c-bus@3 {
+ i2c_slot2b: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
- i2c_slot3: i2c-bus@4 {
+ i2c_slot3: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
- i2c_slot4: i2c-bus@5 {
+ i2c_slot4: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
- i2c_slot5: i2c-bus@6 {
+ i2c_slot5: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
@@ -265,24 +265,24 @@
#size-cells = <0>;
i2c-mux-idle-disconnect;
- i2c_m2_s1: i2c-bus@0 {
+ i2c_m2_s1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
- i2c_m2_s2: i2c-bus@1 {
+ i2c_m2_s2: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
- i2c_m2_s3: i2c-bus@2 {
+ i2c_m2_s3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
- i2c_m2_s4: i2c-bus@3 {
+ i2c_m2_s4: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
diff --git a/dts/upstream/src/arm/nxp/imx/e60k02.dtsi b/dts/upstream/src/arm/nxp/imx/e60k02.dtsi
index 13756d3..0029c12 100644
--- a/dts/upstream/src/arm/nxp/imx/e60k02.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/e60k02.dtsi
@@ -14,6 +14,10 @@
#include <dt-bindings/input/input.h>
/ {
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ };
chosen {
stdout-path = &uart1;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-apf51dev.dts b/dts/upstream/src/arm/nxp/imx/imx51-apf51dev.dts
index b61d55c..de6b760 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-apf51dev.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-apf51dev.dts
@@ -25,8 +25,8 @@
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
- lw700 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-lw700 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-babbage.dts b/dts/upstream/src/arm/nxp/imx/imx51-babbage.dts
index 16ff543..f4a47e8 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-babbage.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-babbage.dts
@@ -89,7 +89,7 @@
status = "disabled";
display-timings {
native-mode = <&timing1>;
- timing1: claawvga {
+ timing1: timing-claawvga {
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-ts4800.dts b/dts/upstream/src/arm/nxp/imx/imx51-ts4800.dts
index 2bd0761..079bd3d 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-ts4800.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-ts4800.dts
@@ -58,8 +58,8 @@
pinctrl-0 = <&pinctrl_lcd>;
display-timings {
- 800x480p60 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-800x480p60 {
clock-frequency = <30066000>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx53-m53evk.dts b/dts/upstream/src/arm/nxp/imx/imx53-m53evk.dts
index 1353d98..ba0c629 100644
--- a/dts/upstream/src/arm/nxp/imx/imx53-m53evk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx53-m53evk.dts
@@ -17,8 +17,8 @@
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
- 800x480p60 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-800x480p60 {
clock-frequency = <31500000>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx53-m53menlo.dts b/dts/upstream/src/arm/nxp/imx/imx53-m53menlo.dts
index 4d77b60..558751e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx53-m53menlo.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx53-m53menlo.dts
@@ -64,6 +64,7 @@
reg = <0>;
lvds_decoder_in: endpoint {
+ data-mapping = "jeida-18";
remote-endpoint = <&lvds0_out>;
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx53-tx53-x03x.dts b/dts/upstream/src/arm/nxp/imx/imx53-tx53-x03x.dts
index a7f7752..a02d77b 100644
--- a/dts/upstream/src/arm/nxp/imx/imx53-tx53-x03x.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx53-tx53-x03x.dts
@@ -67,7 +67,7 @@
};
display-timings {
- VGA {
+ timing-vga {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -83,7 +83,7 @@
pixelclk-active = <0>;
};
- ETV570 {
+ timing-etc570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -99,7 +99,7 @@
pixelclk-active = <0>;
};
- ET0350 {
+ timing-et0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
@@ -115,7 +115,7 @@
pixelclk-active = <0>;
};
- ET0430 {
+ timing-et0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
@@ -131,7 +131,7 @@
pixelclk-active = <1>;
};
- ET0500 {
+ timing-et0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -147,7 +147,7 @@
pixelclk-active = <0>;
};
- ET0700 { /* same as ET0500 */
+ timing-et0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -163,7 +163,7 @@
pixelclk-active = <0>;
};
- ETQ570 {
+ timing-etq570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx53-tx53-x13x.dts b/dts/upstream/src/arm/nxp/imx/imx53-tx53-x13x.dts
index 6cdf208..e10c179 100644
--- a/dts/upstream/src/arm/nxp/imx/imx53-tx53-x13x.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx53-tx53-x13x.dts
@@ -191,7 +191,7 @@
display-timings {
native-mode = <&lvds0_timing0>;
- lvds0_timing0: hsd100pxn1 {
+ lvds0_timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
@@ -207,7 +207,7 @@
pixelclk-active = <1>;
};
- lvds0_timing1: nl12880bc20 {
+ lvds0_timing1: timing-nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
@@ -233,7 +233,7 @@
display-timings {
native-mode = <&lvds1_timing0>;
- lvds1_timing0: hsd100pxn1 {
+ lvds1_timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_4.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_4.dts
index dfa6f64..c9b2ea2 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_4.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos2_4.dts
@@ -82,11 +82,10 @@
compatible = "lg,lg4573";
spi-max-frequency = <10000000>;
reg = <0>;
- power-on-delay = <10>;
display-timings {
- 480x800p57 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-480x800p57 {
clock-frequency = <27000027>;
hactive = <480>;
vactive = <800>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_4.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_4.dts
index a5ac793..9ec038f 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_4.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_4.dts
@@ -36,8 +36,8 @@
status = "okay";
display-timings {
- 480x800p60 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-480x800p60 {
clock-frequency = <30000000>;
hactive = <480>;
vactive = <800>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_7.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_7.dts
index 5a25bdb..b312983 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_7.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-aristainetos_7.dts
@@ -25,8 +25,8 @@
status = "okay";
display-timings {
- 800x480p60 {
- native-mode;
+ native-mode = <&timing0>;
+ timing0: timing-800x480p60 {
clock-frequency = <33246000>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i-ads2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i-ads2.dts
new file mode 100644
index 0000000..6a0c53f
--- /dev/null
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i-ads2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+#include "imx6qdl-kontron-samx6i-ads2.dtsi"
+
+/ {
+ model = "Kontron SMARC-sAMX6i Dual-Lite/Solo on SMARC Eval 2.0 carrier";
+ compatible = "kontron,imx6dl-samx6i-ads2", "kontron,imx6dl-samx6i", "fsl,imx6dl";
+};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i.dtsi
index a864fdb..5a9b819 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-kontron-samx6i.dtsi
@@ -7,6 +7,6 @@
#include "imx6qdl-kontron-samx6i.dtsi"
/ {
- model = "Kontron SMARC sAMX6i Dual-Lite/Solo";
+ model = "Kontron SMARC-sAMX6i Dual-Lite/Solo";
compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl";
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi
index 52a0f6e..bcf4d9c 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-yapp43-common.dtsi
@@ -274,24 +274,24 @@
led@0 {
chan-name = "R";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
+ led-cur = /bits/ 8 <0x6e>;
+ max-cur = /bits/ 8 <0xc8>;
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
chan-name = "G";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
+ led-cur = /bits/ 8 <0xbe>;
+ max-cur = /bits/ 8 <0xc8>;
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
chan-name = "B";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
+ led-cur = /bits/ 8 <0xbe>;
+ max-cur = /bits/ 8 <0xc8>;
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i-ads2.dts b/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i-ads2.dts
new file mode 100644
index 0000000..94c395c
--- /dev/null
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i-ads2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+#include "imx6qdl-kontron-samx6i-ads2.dtsi"
+
+/ {
+ model = "Kontron SMARC-sAMX6i Quad/Dual on SMARC Eval 2.0 carrier";
+ compatible = "kontron,imx6q-samx6i-ads2", "kontron,imx6q-samx6i", "fsl,imx6q";
+};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i.dtsi
index 4d6a0c3..e769634 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-kontron-samx6i.dtsi
@@ -5,31 +5,8 @@
#include "imx6q.dtsi"
#include "imx6qdl-kontron-samx6i.dtsi"
-#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Kontron SMARC sAMX6i Quad/Dual";
+ model = "Kontron SMARC-sAMX6i Quad/Dual";
compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
};
-
-/* Quad/Dual SoMs have 3 chip-select signals */
-&ecspi4 {
- cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
- <&gpio3 29 GPIO_ACTIVE_LOW>,
- <&gpio3 25 GPIO_ACTIVE_LOW>;
-};
-
-&pinctrl_ecspi4 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
-
- /* SPI4_IMX_CS2# - connected to internal flash */
- MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
- /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
- /* SPI4_CS3# - connected to SMARC SPI0_CS1# */
- MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
- >;
-};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw52xx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw52xx.dtsi
index 48ffb3e..082a2e3 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw52xx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw52xx.dtsi
@@ -485,7 +485,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw53xx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw53xx.dtsi
index 1eae438..8ec4420 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw53xx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw53xx.dtsi
@@ -482,7 +482,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw54xx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw54xx.dtsi
index c2ec857..9df9f79 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw54xx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw54xx.dtsi
@@ -529,7 +529,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi
index 7cee983..7693f92 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw560x.dtsi
@@ -584,7 +584,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi
index fbc704c..9d0836d 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5903.dtsi
@@ -486,7 +486,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: g101evn010 {
+ timing0: timing-g101evn010 {
clock-frequency = <68930000>;
hactive = <1280>;
vactive = <800>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5904.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5904.dtsi
index 0705062..f4cb9e1 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5904.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-gw5904.dtsi
@@ -551,7 +551,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi
new file mode 100644
index 0000000..b4a7924
--- /dev/null
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree include for the Kontron SMARC-sAMX6i board on a SMARC Eval
+ * 2.0 carrier (ADS2).
+ *
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sound {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line Out Jack",
+ "Microphone", "Microphone Jack",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "Line Out Jack", "LINEOUTR",
+ "Line Out Jack", "LINEOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "IN1L", "Line In Jack",
+ "IN1R", "Line In Jack",
+ "Microphone Jack", "MICBIAS",
+ "IN2L", "Microphone Jack",
+ "IN2R", "Microphone Jack";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&wm8904>;
+ };
+ };
+
+ reg_codec_mic: regulator-codec-mic {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_MIC";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_codec_1p8v: regulator-codec-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8_S0_CODEC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&audmux {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&ecspi4 {
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+ };
+};
+
+&fec {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ wm8904: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "mclk";
+ AVDD-supply = <®_codec_1p8v>;
+ CPVDD-supply = <®_codec_1p8v>;
+ DBVDD-supply = <®_codec_1p8v>;
+ DCVDD-supply = <®_codec_1p8v>;
+ MICVDD-supply = <®_codec_mic>;
+ };
+};
+
+&i2c3 {
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+&usdhc3 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i.dtsi
index 85aeebc..99b5e78 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-kontron-samx6i.dtsi
@@ -61,6 +61,18 @@
vin-supply = <®_smarc_suppy>;
};
+ reg_sdio: regulator-sdio {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_sdio>;
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <20000>;
+ };
+
reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -137,7 +149,7 @@
status = "disabled";
};
- i2c_intern: i2c-gpio-intern {
+ i2c_intern: i2c-0 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
@@ -148,7 +160,7 @@
#size-cells = <0>;
};
- i2c_lcd: i2c-gpio-lcd {
+ i2c_lcd: i2c-1 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
@@ -160,7 +172,7 @@
status = "disabled";
};
- i2c_cam: i2c-gpio-cam {
+ i2c_cam: i2c-2 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
@@ -178,7 +190,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
- audmux_ssi1 {
+ mux-ssi1 {
fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
@@ -190,7 +202,7 @@
>;
};
- audmux_adu3 {
+ mux-aud3 {
fsl,audmux-port = <MX51_AUDMUX_PORT3>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
@@ -198,7 +210,7 @@
>;
};
- audmux_ssi2 {
+ mux-ssi2 {
fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
@@ -210,7 +222,7 @@
>;
};
- audmux_adu4 {
+ mux-aud4 {
fsl,audmux-port = <MX51_AUDMUX_PORT4>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
@@ -244,7 +256,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
- <&gpio3 29 GPIO_ACTIVE_LOW>;
+ <&gpio3 29 GPIO_ACTIVE_LOW>,
+ <&gpio3 25 GPIO_ACTIVE_LOW>;
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */
@@ -259,7 +272,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-connection-type = "rgmii-id";
phy-handle = <ðphy>;
mdio {
@@ -269,7 +282,7 @@
ethphy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
- reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
};
};
@@ -356,10 +369,6 @@
regulator-always-on;
};
- /*
- * Per schematics, of all VGEN's, only VGEN5 has some
- * usage ... but even that - over DNI resistor
- */
vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
@@ -380,8 +389,7 @@
regulator-max-microvolt = <3300000>;
};
- reg_2p5v_s0: vgen5 {
- regulator-name = "V_2V5_S0";
+ vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
@@ -464,6 +472,8 @@
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
/* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ /* SPI4_CS3# - connected to SMARC SPI0_CS1# */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
>;
};
@@ -516,7 +526,7 @@
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */
>;
};
@@ -642,6 +652,12 @@
>;
};
+ pinctrl_reg_sdio: reg-sdiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* SDIO_PWR_EN */
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
@@ -694,7 +710,6 @@
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
>;
};
@@ -728,8 +743,7 @@
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
- wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
- reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
};
/* LCD_BKLT_PWM */
@@ -797,12 +811,12 @@
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_sdio>;
no-1-8-v;
};
/* SDMMC */
&usdhc4 {
- /* Internal eMMC, optional on some boards */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
@@ -811,11 +825,13 @@
non-removable;
vmmc-supply = <®_3p3v_s0>;
vqmmc-supply = <®_1p8v_s0>;
+ status = "okay";
};
&wdog1 {
/* CPLD is feeded by watchdog (hardwired) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
+ fsl,ext-reset-output;
status = "okay";
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6a.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6a.dtsi
index 238f3af..807f3c9 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6a.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6a.dtsi
@@ -22,12 +22,16 @@
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
- #address-cells = <1>;
- #size-cells = <1>;
vcc-supply = <®_mba6_3p3v>;
- mba_mac_address: mac-address@20 {
- reg = <0x20 0x6>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mba_mac_address: mac-address@20 {
+ reg = <0x20 0x6>;
+ };
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6b.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6b.dtsi
index a587bc8..789733a 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6b.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6b.dtsi
@@ -32,12 +32,16 @@
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
- #address-cells = <1>;
- #size-cells = <1>;
vcc-supply = <®_mba6_3p3v>;
- mba_mac_address: mac-address@20 {
- reg = <0x20 0x6>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mba_mac_address: mac-address@20 {
+ reg = <0x20 0x6>;
+ };
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabreauto.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabreauto.dtsi
index 6656e2e..0a3deaf 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabreauto.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabreauto.dtsi
@@ -786,7 +786,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: hsd100pxn1 {
+ timing0: timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lcd.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lcd.dtsi
index 79f2354..ded241a 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lcd.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lcd.dtsi
@@ -110,7 +110,7 @@
};
display-timings {
- VGA {
+ timing-vga {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -126,8 +126,7 @@
pixelclk-active = <0>;
};
- ETV570 {
- u-boot,panel-name = "edt,et057090dhu";
+ timing-etv570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -143,8 +142,7 @@
pixelclk-active = <0>;
};
- ET0350 {
- u-boot,panel-name = "edt,et0350g0dh6";
+ timing-et0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
@@ -160,8 +158,7 @@
pixelclk-active = <0>;
};
- ET0430 {
- u-boot,panel-name = "edt,et0430g0dh6";
+ timing-et0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
@@ -177,7 +174,7 @@
pixelclk-active = <1>;
};
- ET0500 {
+ timing-et0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -193,8 +190,7 @@
pixelclk-active = <0>;
};
- ET0700 { /* same as ET0500 */
- u-boot,panel-name = "edt,etm0700g0dh6";
+ timing-et0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -210,7 +206,7 @@
pixelclk-active = <0>;
};
- ETQ570 {
+ timing-etq570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
@@ -226,8 +222,7 @@
pixelclk-active = <0>;
};
- CoMTFT { /* same as ET0700 but with inverted pixel clock */
- u-boot,panel-name = "edt,etm0700g0edh6";
+ timing-comtft { /* same as ET0700 but with inverted pixel clock */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lvds.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lvds.dtsi
index 2ca2eb3..4eb53d5 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lvds.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-tx6-lvds.dtsi
@@ -127,8 +127,7 @@
};
display-timings {
- hsd100pxn1 {
- u-boot,panel-name = "hannstar,hsd100pxn1";
+ timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
@@ -142,7 +141,7 @@
pixelclk-active = <1>;
};
- VGA {
+ timing-vga {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -158,8 +157,7 @@
pixelclk-active = <0>;
};
- nl12880bc20 {
- u-boot,panel-name = "nlt,nl12880bc20-spwg-24";
+ timing-nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
@@ -175,8 +173,7 @@
pixelclk-active = <1>;
};
- ET0700 {
- u-boot,panel-name = "edt,etm0700g0dh6";
+ timing-et0700 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -192,8 +189,7 @@
pixelclk-active = <0>;
};
- ETV570 {
- u-boot,panel-name = "edt,et057090dhu";
+ timing-etv570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -224,7 +220,7 @@
};
display-timings {
- hsd100pxn1 {
+ timing-hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
@@ -238,7 +234,7 @@
pixelclk-active = <1>;
};
- VGA {
+ timing-vga {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -254,7 +250,7 @@
pixelclk-active = <0>;
};
- nl12880bc20 {
+ timing-nl12880bc20 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-tx6ul.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul-tx6ul.dtsi
index 1db146a..864173e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6ul-tx6ul.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6ul-tx6ul.dtsi
@@ -405,7 +405,7 @@
status = "okay";
display-timings {
- VGA {
+ timing-vga {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -421,7 +421,7 @@
pixelclk-active = <1>;
};
- ETV570 {
+ timing-etv570 {
clock-frequency = <25200000>;
hactive = <640>;
vactive = <480>;
@@ -437,7 +437,7 @@
pixelclk-active = <1>;
};
- ET0350 {
+ timing-et0350 {
clock-frequency = <6413760>;
hactive = <320>;
vactive = <240>;
@@ -453,7 +453,7 @@
pixelclk-active = <1>;
};
- ET0430 {
+ timing-et0430 {
clock-frequency = <9009000>;
hactive = <480>;
vactive = <272>;
@@ -469,7 +469,7 @@
pixelclk-active = <0>;
};
- ET0500 {
+ timing-et0500 {
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -485,7 +485,7 @@
pixelclk-active = <1>;
};
- ET0700 { /* same as ET0500 */
+ timing-et0700 { /* same as ET0500 */
clock-frequency = <33264000>;
hactive = <800>;
vactive = <480>;
@@ -501,7 +501,7 @@
pixelclk-active = <1>;
};
- ETQ570 {
+ timing-etq570 {
clock-frequency = <6596040>;
hactive = <320>;
vactive = <240>;
diff --git a/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts b/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
index 5485fe11..d38183e 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
+++ b/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
@@ -323,7 +323,6 @@
display-timings {
native-mode = <&timing5>;
timing0: timing0 {
- panel-name = "VGA";
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
@@ -340,7 +339,6 @@
};
timing1: timing1 {
- panel-name = "ETV570";
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
@@ -357,7 +355,6 @@
};
timing2: timing2 {
- panel-name = "ET0350";
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
@@ -374,7 +371,6 @@
};
timing3: timing3 {
- panel-name = "ET0430";
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
@@ -391,7 +387,6 @@
};
timing4: timing4 {
- panel-name = "ET0500", "ET0700";
clock-frequency = <33260000>;
hactive = <800>;
vactive = <480>;
@@ -408,7 +403,6 @@
};
timing5: timing5 {
- panel-name = "ETQ570";
clock-frequency = <6400000>;
hactive = <320>;
vactive = <240>;
diff --git a/dts/upstream/src/arm/qcom/msm8226-motorola-falcon.dts b/dts/upstream/src/arm/qcom/msm8226-motorola-falcon.dts
index 029e1b1..5dbca83 100644
--- a/dts/upstream/src/arm/qcom/msm8226-motorola-falcon.dts
+++ b/dts/upstream/src/arm/qcom/msm8226-motorola-falcon.dts
@@ -96,6 +96,35 @@
};
};
+&blsp1_i2c2 {
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0xc>;
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&pm8226_l19>;
+ vid-supply = <&pm8226_lvs1>;
+ pinctrl-0 = <&mag_int_default &mag_reset_default>;
+ pinctrl-names = "default";
+ };
+
+ accelerometer@19 {
+ compatible = "st,lis3dh-accel";
+ reg = <0x19>;
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_lvs1>;
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+ st,drdy-int-pin = <1>;
+ };
+};
+
&blsp1_i2c3 {
status = "okay";
@@ -321,6 +350,30 @@
};
&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio63";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+
+ mag_int_default: mag-int-default-state {
+ pins = "gpio66";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+
+ mag_reset_default: mag-reset-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
reg_lcd_default: reg-lcd-default-state {
pins = "gpio31", "gpio33";
function = "gpio";
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-milletwifi.dts b/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-milletwifi.dts
new file mode 100644
index 0000000..7d51915
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-milletwifi.dts
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com>
+ * Copyright (c) 2023, Bryant Mairs <bryant@mai.rs>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/power/summit,smb347-charger.h>
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+/delete-node/ &smem_region;
+
+/ {
+ model = "Samsung Galaxy Tab 4 8.0 Wi-Fi";
+ compatible = "samsung,milletwifi", "qcom,apq8026";
+ chassis-type = "tablet";
+
+ aliases {
+ display0 = &framebuffer0;
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ stdout-path = "display0";
+
+ framebuffer0: framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03200000 0x800000>;
+ width = <800>;
+ height = <1280>;
+ stride = <(800 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ event-hall-sensor {
+ label = "Cover";
+ gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ i2c-backlight {
+ compatible = "i2c-gpio";
+ sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-0 = <&backlight_i2c_default_state>;
+ pinctrl-names = "default";
+
+ i2c-gpio,delay-us = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ backlight@2c {
+ compatible = "ti,lp8556";
+ reg = <0x2c>;
+ enable-supply = <®_backlight_vddio>;
+
+ dev-ctrl = /bits/ 8 <0x80>;
+ init-brt = /bits/ 8 <0x3f>;
+
+ /*
+ * Change transition duration: 200ms, Change
+ * transition strength: heavy, PWM hysteresis:
+ * 1-bit w/ 8-bit resolution
+ */
+ rom-a3h {
+ rom-addr = /bits/ 8 <0xa3>;
+ rom-val = /bits/ 8 <0x5e>;
+ };
+
+ /*
+ * PWM phase configuration: 3-phase/3 drivers
+ * (0, 120deg, 240deg, -, -, -),
+ * PWM frequency: 9616Hz (10-bit)
+ */
+ rom-a5h {
+ rom-addr = /bits/ 8 <0xa5>;
+ rom-val = /bits/ 8 <0x34>;
+ };
+
+ /*
+ * Enable LED drivers 2 & 3, Boot inductor
+ * current limit: 1.5A/2.6A
+ */
+ rom-a7h {
+ rom-addr = /bits/ 8 <0xa7>;
+ rom-val = /bits/ 8 <0xfa>;
+ };
+ };
+ };
+
+ reg_backlight_vddio: regulator-backlight-vddio {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight_vddio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&backlight_vddio_default_state>;
+ pinctrl-names = "default";
+ };
+
+ reg_tsp_1p8v: regulator-tsp-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_1p8v";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&tsp_en1_default_state>;
+ pinctrl-names = "default";
+ };
+
+ reg_tsp_3p3v: regulator-tsp-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&tsp_en_default_state>;
+ pinctrl-names = "default";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ mpss_region: mpss@8400000 {
+ reg = <0x08400000 0x1f00000>;
+ no-map;
+ };
+
+ mba_region: mba@a300000 {
+ reg = <0x0a300000 0x100000>;
+ no-map;
+ };
+
+ reserved@cb00000 {
+ reg = <0x0cb00000 0x700000>;
+ no-map;
+ };
+
+ wcnss_region: wcnss@d200000 {
+ reg = <0x0d200000 0x700000>;
+ no-map;
+ };
+
+ adsp_region: adsp@d900000 {
+ reg = <0x0d900000 0x1800000>;
+ no-map;
+ };
+
+ venus@f100000 {
+ reg = <0x0f100000 0x500000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ reserved@fb00000 {
+ reg = <0x0fb00000 0x260000>;
+ no-map;
+ };
+
+ rfsa@fd60000 {
+ reg = <0x0fd60000 0x20000>;
+ no-map;
+ };
+
+ rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0fd80000 0x180000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ accelerometer@1d {
+ compatible = "st,lis2hh12";
+ reg = <0x1d>;
+
+ interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
+
+ pinctrl-0 = <&accel_int_default_state>;
+ pinctrl-names = "default";
+
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_lvs1>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ st,drdy-int-pin = <1>;
+ };
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ charger@6a {
+ compatible = "summit,smb358";
+ reg = <0x6a>;
+
+ interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&charger_int_default_state>;
+ pinctrl-names = "default";
+
+ summit,enable-usb-charging;
+ summit,enable-charge-control = <SMB3XX_CHG_ENABLE_SW>;
+ summit,fast-voltage-threshold-microvolt = <3000000>;
+ summit,chip-temperature-threshold-celsius = <130>;
+ summit,usb-current-limit-microamp = <1500000>;
+ };
+};
+
+&blsp1_i2c4 {
+ status = "okay";
+
+ muic: usb-switch@25 {
+ compatible = "siliconmitus,sm5502-muic";
+ reg = <0x25>;
+
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&muic_int_default_state>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "melfas,mms252", "melfas,mms114";
+ reg = <0x48>;
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <1280>;
+ avdd-supply = <®_tsp_3p3v>;
+ vdd-supply = <®_tsp_1p8v>;
+ linux,keycodes = <KEY_APPSELECT KEY_BACK>;
+
+ pinctrl-0 = <&tsp_int_rst_default_state>;
+ pinctrl-names = "default";
+ };
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ regulator-always-on;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&sdhc2_default_state>, <&sdc2_cd_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default_state: accel-int-default-state {
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_i2c_default_state: backlight-i2c-default-state {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ backlight_vddio_default_state: backlight-vddio-default-state {
+ pins = "gpio74";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ charger_int_default_state: charger-int-default-state {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ muic_int_default_state: muic-int-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_default_state: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en_default_state: tsp-en-default-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en1_default_state: tsp-en1-default-state {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_int_rst_default_state: tsp-int-rst-default-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&muic>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi b/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
index 11e60b7..769e151 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
@@ -666,12 +666,12 @@
qcom,controller-type = "pmic-arbiter";
};
- qfprom: qfprom@700000 {
+ qfprom: efuse@700000 {
compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+
tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
@@ -684,7 +684,6 @@
compatible = "qcom,gcc-apq8064", "syscon";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&pxo_board>,
@@ -993,7 +992,7 @@
reg = <0x1a400000 0x100>;
};
- gpu: adreno-3xx@4300000 {
+ gpu: gpu@4300000 {
compatible = "qcom,adreno-320.2", "qcom,adreno";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8084.dtsi b/dts/upstream/src/arm/qcom/qcom-apq8084.dtsi
index ca53dff..2b52e5d 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8084.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-apq8084.dtsi
@@ -245,7 +245,7 @@
reg = <0xfc190000 0x10000>;
};
- qfprom: qfprom@fc4bc000 {
+ qfprom: efuse@fc4bc000 {
compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
diff --git a/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi b/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
index 0fb65f2..56415ab 100644
--- a/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
@@ -187,7 +187,6 @@
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq4019";
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
clocks = <&xo>, <&sleep_clk>;
diff --git a/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi b/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
index f128510..da0fd75 100644
--- a/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
@@ -372,7 +372,7 @@
qcom,controller-type = "pmic-arbiter";
};
- qfprom: qfprom@700000 {
+ qfprom: efuse@700000 {
compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
@@ -519,7 +519,6 @@
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
tsens: thermal-sensor {
compatible = "qcom,ipq8064-tsens";
diff --git a/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi b/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
index 34c6099..573feb3 100644
--- a/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
@@ -102,7 +102,6 @@
gcc: clock-controller@900000 {
compatible = "qcom,gcc-mdm9615";
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi
index 525d8c6..8839b23 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi
@@ -287,6 +287,10 @@
status = "okay";
};
+&smbb {
+ status = "okay";
+};
+
&usb {
extcon = <&smbb>;
dr_mode = "peripheral";
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts b/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts
new file mode 100644
index 0000000..2ecc598
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-samsung-ms013g.dts
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &smem_region;
+
+/ {
+ model = "Samsung Galaxy Grand 2";
+ compatible = "samsung,ms013g", "qcom,msm8226";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ serial0 = &blsp1_uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_hall_sensor_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Hall Effect Sensor";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ button-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ button-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ button-home {
+ label = "Home Key";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ };
+ };
+
+ reg_motor_vdd: regulator-motor-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "motor_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 111 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&motor_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reg_vdd_tsp_a: regulator-vdd-tsp-a {
+ compatible = "regulator-fixed";
+ regulator-name = "tsp_3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&tsp_en_default>;
+ pinctrl-names = "default";
+ };
+
+ reserved-memory {
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+ };
+
+ vibrator {
+ compatible = "regulator-haptic";
+ haptic-supply = <®_motor_vdd>;
+ min-microvolt = <3300000>;
+ max-microvolt = <3300000>;
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "bosch,bma255";
+ reg = <0x18>;
+ interrupts-extended = <&tlmm 64 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_lvs1>;
+
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "zinitix,bt541";
+
+ reg = <0x20>;
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1280>;
+
+ vcca-supply = <®_vdd_tsp_a>;
+ vdd-supply = <&pm8226_lvs1>;
+
+ pinctrl-0 = <&tsp_int_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-always-on;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&sdhc2_default_state &sdhc2_cd_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio50";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio106", "gpio107", "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ motor_en_default: motor-en-default-state {
+ pins = "gpio111";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdhc2_cd_default: sdhc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_en_default: tsp-en-default-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tsp_int_default: tsp-int-default-state {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
index 270973e..b2f92ad 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
@@ -635,7 +635,7 @@
reg = <0xfc4ab000 0x4>;
};
- qfprom: qfprom@fc4bc000 {
+ qfprom: efuse@fc4bc000 {
compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x1000>;
#address-cells = <1>;
@@ -1046,7 +1046,7 @@
};
};
- gpu: adreno@fdb00000 {
+ gpu: gpu@fdb00000 {
compatible = "qcom,adreno-305.18", "qcom,adreno";
reg = <0xfdb00000 0x10000>;
reg-names = "kgsl_3d0_reg_memory";
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
index 455ba4b..a66c474 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
@@ -113,7 +113,6 @@
gcc: clock-controller@900000 {
compatible = "qcom,gcc-msm8660";
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&pxo_board>, <&cxo_board>;
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts b/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts
index 0cbe2d2..376a331 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts
@@ -29,6 +29,10 @@
height = <1280>;
stride = <(720 * 3)>;
format = "r8g8b8";
+ vsp-supply = <®_lcd_pos>;
+ vsn-supply = <®_lcd_neg>;
+ vdd-supply = <&pm8226_l28>;
+ vddio-supply = <&vddio_disp_vreg>;
};
};
@@ -51,6 +55,18 @@
};
};
+ vddio_disp_vreg: regulator-vddio-disp {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio_disp";
+ gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <300>;
+ enable-active-high;
+ regulator-boot-on;
+ vin-supply = <&pm8226_l8>;
+ pinctrl-0 = <&disp_vddio_default>;
+ pinctrl-names = "default";
+ };
+
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@@ -68,12 +84,67 @@
};
};
+&blsp1_i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0xc>;
+ interrupts-extended = <&tlmm 38 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&pm8226_l19>;
+ pinctrl-0 = <&mag_int_default &mag_reset_default>;
+ pinctrl-names = "default";
+ };
+
+ accelerometer@18 {
+ compatible = "st,lis3dh-accel";
+ reg = <0x18>;
+ interrupts-extended = <&tlmm 1 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l19>;
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+};
+
&blsp1_i2c3 {
+ clock-frequency = <400000>;
status = "okay";
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+ pinctrl-0 = <®_lcd_default>;
+ pinctrl-names = "default";
+
+ reg_lcd_pos: outp {
+ regulator-name = "outp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ regulator-active-discharge = <1>;
+ regulator-boot-on;
+ enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_lcd_neg: outn {
+ regulator-name = "outn";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ regulator-active-discharge = <1>;
+ regulator-boot-on;
+ enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
sensor@48 {
compatible = "ti,tmp108";
reg = <0x48>;
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&temp_alert_default>;
+ pinctrl-names = "default";
+ #thermal-sensor-cells = <0>;
};
};
@@ -278,6 +349,56 @@
status = "okay";
};
+&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio1";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+
+ disp_vddio_default: disp-vddio-default-state {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ mag_int_default: mag-int-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+
+ mag_reset_default: mag-reset-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ reg_lcd_default: reg-lcd-default-state {
+ pins = "gpio31", "gpio33";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ temp_alert_default: temp-alert-default-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-disable;
+ };
+};
+
&usb {
extcon = <&smbb>;
dr_mode = "peripheral";
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
index 922f9e4..ebc43c5 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
@@ -47,9 +47,9 @@
};
};
- memory {
+ memory@80000000 {
device_type = "memory";
- reg = <0x0 0x0>;
+ reg = <0x80000000 0>;
};
cpu-pmu {
@@ -129,7 +129,6 @@
gcc: clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
index 4aaae85..fdb6e22 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -182,7 +182,7 @@
status = "okay";
clock-frequency = <355000>;
- led-controller@38 {
+ backlight: led-controller@38 {
compatible = "ti,lm3630a";
status = "okay";
reg = <0x38>;
@@ -272,6 +272,8 @@
reg = <0>;
compatible = "lg,acx467akm-7";
+ backlight = <&backlight>;
+
pinctrl-names = "default";
pinctrl-0 = <&panel_pin>;
@@ -328,7 +330,7 @@
power-source = <PM8941_GPIO_S3>;
};
- otg {
+ otg-hog {
gpio-hog;
gpios = <35 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974-samsung-hlte.dts b/dts/upstream/src/arm/qcom/qcom-msm8974-samsung-hlte.dts
new file mode 100644
index 0000000..903bb4d
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974-samsung-hlte.dts
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Samsung Galaxy Note 3";
+ compatible = "samsung,hlte", "qcom,msm8974";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_3; /* SDC3 SD card slot */
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_pin_a>;
+ pinctrl-names = "default";
+
+ key-home {
+ label = "Home Key";
+ gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ touch_ldo: regulator-touch {
+ compatible = "regulator-fixed";
+ regulator-name = "touch-ldo";
+
+ gpio = <&pm8941_gpios 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+
+ pinctrl-0 = <&touch_ldo_pin>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupt-parent = <&pm8941_gpios>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8941_l10>;
+ vio-supply = <&touch_ldo>;
+
+ pinctrl-0 = <&touch_pin>;
+ pinctrl-names = "default";
+
+ syna,startup-delay-ms = <100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp2_i2c6 {
+ status = "okay";
+
+ fuelgauge@36 {
+ compatible = "maxim,max17048";
+ reg = <0x36>;
+
+ maxim,double-soc;
+ maxim,rcomp = /bits/ 8 <0x56>;
+
+ interrupt-parent = <&pm8941_gpios>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&fuelgauge_pin>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&pm8941_gpios {
+ gpio_keys_pin_a: gpio-keys-active-state {
+ pins = "gpio2", "gpio3", "gpio5";
+ function = "normal";
+ bias-pull-up;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ fuelgauge_pin: fuelgauge-int-state {
+ pins = "gpio26";
+ function = "normal";
+ bias-disable;
+ input-enable;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ touch_pin: touchscreen-int-state {
+ pins = "gpio30";
+ function = "normal";
+ bias-disable;
+ input-enable;
+ power-source = <PM8941_GPIO_S3>;
+ };
+
+ touch_ldo_pin: touchscreen-ldo-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <PM8941_GPIO_S3>;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+ };
+};
+
+&remoteproc_adsp {
+ cx-supply = <&pm8841_s2>;
+ status = "okay";
+};
+
+&remoteproc_mss {
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <815000>;
+ regulator-max-microvolt = <900000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-0 = <&sdhc1_pin_a>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhc_3 {
+ max-frequency = <100000000>;
+
+ vmmc-supply = <&pm8941_l21>;
+ vqmmc-supply = <&pm8941_l21>;
+
+ pinctrl-0 = <&sdhc3_pin_a>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&tlmm {
+ sdhc1_pin_a: sdhc1-pin-active-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <4>;
+ bias-pull-up;
+ };
+ };
+
+ sdhc3_pin_a: sdhc3-pin-active-state {
+ pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "sdc3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&usb {
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ status = "okay";
+};
+
+&usb_hs1_phy {
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
index 5651bb3..1556857 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
@@ -132,7 +132,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
@@ -219,7 +219,7 @@
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 10>;
+ mboxes = <&apcs 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
@@ -244,7 +244,7 @@
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -269,7 +269,7 @@
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -294,9 +294,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-2 = <&apcs 8 9>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -343,9 +341,11 @@
<0xf9002000 0x1000>;
};
- apcs: syscon@f9011000 {
- compatible = "syscon";
+ apcs: mailbox@f9011000 {
+ compatible = "qcom,msm8974-apcs-kpss-global",
+ "qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0xf9011000 0x1000>;
+ #mbox-cells = <1>;
};
saw_l2: power-manager@f9012000 {
@@ -757,7 +757,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 17>;
+ mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
wcnss {
@@ -1233,7 +1233,7 @@
reg = <0xfc4ab000 0x4>;
};
- qfprom: qfprom@fc4bc000 {
+ qfprom: efuse@fc4bc000 {
compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x2100>;
#address-cells = <1>;
@@ -1576,7 +1576,7 @@
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 12>;
+ mboxes = <&apcs 12>;
qcom,smd-edge = <0>;
label = "modem";
@@ -2129,7 +2129,7 @@
};
};
- gpu: adreno@fdb00000 {
+ gpu: gpu@fdb00000 {
compatible = "qcom,adreno-330.1", "qcom,adreno";
reg = <0xfdb00000 0x10000>;
reg-names = "kgsl_3d0_reg_memory";
@@ -2213,7 +2213,7 @@
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 8>;
+ mboxes = <&apcs 8>;
qcom,smd-edge = <1>;
label = "lpass";
};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-htc-m8.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-htc-m8.dts
new file mode 100644
index 0000000..b896cc1
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-htc-m8.dts
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "qcom-msm8974pro.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "HTC One (M8)";
+ compatible = "htc,m8", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ key-volume-down {
+ label = "volume_down";
+ gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <20>;
+ wakeup-source;
+ };
+
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <20>;
+ wakeup-source;
+ };
+ };
+
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ pinctrl-names = "default";
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
+};
+
+&pm8941_vib {
+ status = "okay";
+};
+
+&pronto {
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+ vddpx-supply = <&pm8941_s3>;
+
+ pinctrl-0 = <&wcnss_pin_a>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ iris {
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ qcom,remote-pid = <4>;
+ label = "pronto";
+
+ wcnss {
+ status = "okay";
+ };
+ };
+};
+
+&rpm_requests {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8841-regulators";
+
+ pm8841_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s3: s3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8841_s4: s4 {
+ regulator-min-microvolt = <815000>;
+ regulator-max-microvolt = <900000>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8941-regulators";
+
+ vdd_l1_l3-supply = <&pm8941_s1>;
+ vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+ vdd_l4_l11-supply = <&pm8941_s1>;
+ vdd_l5_l7-supply = <&pm8941_s2>;
+ vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+ vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>;
+ vdd_l9_l10_l17_l22-supply = <&vreg_boost>;
+ vdd_l13_l20_l23_l24-supply = <&vreg_boost>;
+ vdd_l21-supply = <&vreg_boost>;
+
+ pm8941_s1: s1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_s2: s2 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ regulator-boot-on;
+ };
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l3: l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8941_l4: l4 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8941_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8941_l11: l11 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8941_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ pm8941_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8941_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pm8941_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8941_l19: l19 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ regulator-boot-on;
+ };
+
+ pm8941_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-boot-on;
+ };
+
+ pm8941_l22: l22 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8941_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8941_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ regulator-boot-on;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8941_l20>;
+ vqmmc-supply = <&pm8941_s3>;
+
+ pinctrl-0 = <&sdc1_on>;
+ pinctrl-1 = <&sdc1_off>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&smbb {
+ status = "okay";
+};
+
+&tlmm {
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ sdc1_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ cmd-data-pins {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ wcnss_pin_a: wcnss-pin-active-state {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+};
+
+&usb {
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ status = "okay";
+};
+
+&usb_hs1_phy {
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x63>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts
new file mode 100644
index 0000000..2621c59
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro-sony-xperia-shinano-common.dtsi"
+
+/ {
+ model = "Sony Xperia Z3 Compact";
+ compatible = "sony,xperia-aries", "qcom,msm8974pro", "qcom,msm8974";
+ chassis-type = "handset";
+
+ gpio-keys {
+ key-camera-snapshot {
+ label = "camera_snapshot";
+ gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA>;
+ debounce-interval = <15>;
+ };
+
+ key-camera-focus {
+ label = "camera_focus";
+ gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ debounce-interval = <15>;
+ };
+ };
+};
+
+&gpio_keys_pin_a {
+ pins = "gpio2", "gpio3", "gpio4", "gpio5";
+};
+
+&smbb {
+ usb-charge-current-limit = <1500000>;
+ qcom,fast-charge-safe-current = <2100000>;
+ qcom,fast-charge-current-limit = <1800000>;
+ qcom,fast-charge-safe-voltage = <4400000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,auto-recharge-threshold-voltage = <4280000>;
+ qcom,minimum-input-voltage = <4200000>;
+
+ status = "okay";
+};
+
+&synaptics_touchscreen {
+ vio-supply = <&pm8941_s3>;
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi
index e129bb1..6af7c71 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi
@@ -380,6 +380,8 @@
pm8941_l21: l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
+ regulator-system-load = <500000>;
+ regulator-allow-set-load;
regulator-boot-on;
};
diff --git a/dts/upstream/src/arm/renesas/r8a73a4.dtsi b/dts/upstream/src/arm/renesas/r8a73a4.dtsi
index 9a2ae28..8526168 100644
--- a/dts/upstream/src/arm/renesas/r8a73a4.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a73a4.dtsi
@@ -58,6 +58,7 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
tmu0: timer@e61e0000 {
diff --git a/dts/upstream/src/arm/renesas/r8a7742.dtsi b/dts/upstream/src/arm/renesas/r8a7742.dtsi
index d55c344..3a5d6b4 100644
--- a/dts/upstream/src/arm/renesas/r8a7742.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7742.dtsi
@@ -1938,6 +1938,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7743.dtsi b/dts/upstream/src/arm/renesas/r8a7743.dtsi
index d917c0a..8833898 100644
--- a/dts/upstream/src/arm/renesas/r8a7743.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7743.dtsi
@@ -1846,6 +1846,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7744.dtsi b/dts/upstream/src/arm/renesas/r8a7744.dtsi
index 754859c..c66c110 100644
--- a/dts/upstream/src/arm/renesas/r8a7744.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7744.dtsi
@@ -1832,6 +1832,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7745.dtsi b/dts/upstream/src/arm/renesas/r8a7745.dtsi
index 1682983..6ddde36 100644
--- a/dts/upstream/src/arm/renesas/r8a7745.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7745.dtsi
@@ -1636,6 +1636,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a77470.dtsi b/dts/upstream/src/arm/renesas/r8a77470.dtsi
index 2375438..a8a1227 100644
--- a/dts/upstream/src/arm/renesas/r8a77470.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a77470.dtsi
@@ -1061,6 +1061,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7790.dtsi b/dts/upstream/src/arm/renesas/r8a7790.dtsi
index 583b74a..20e4d4c 100644
--- a/dts/upstream/src/arm/renesas/r8a7790.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7790.dtsi
@@ -2012,6 +2012,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7791.dtsi b/dts/upstream/src/arm/renesas/r8a7791.dtsi
index de08ceb..f9c9e1d 100644
--- a/dts/upstream/src/arm/renesas/r8a7791.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7791.dtsi
@@ -1938,6 +1938,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7792.dtsi b/dts/upstream/src/arm/renesas/r8a7792.dtsi
index 7defeb8..dd3bc32 100644
--- a/dts/upstream/src/arm/renesas/r8a7792.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7792.dtsi
@@ -990,5 +990,6 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm/renesas/r8a7793.dtsi b/dts/upstream/src/arm/renesas/r8a7793.dtsi
index d32a9d5..24e66dd 100644
--- a/dts/upstream/src/arm/renesas/r8a7793.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7793.dtsi
@@ -1517,6 +1517,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r8a7794.dtsi b/dts/upstream/src/arm/renesas/r8a7794.dtsi
index f37f094..8e6386a 100644
--- a/dts/upstream/src/arm/renesas/r8a7794.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7794.dtsi
@@ -1484,6 +1484,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clock - can be overridden by the board */
diff --git a/dts/upstream/src/arm/renesas/r9a06g032.dtsi b/dts/upstream/src/arm/renesas/r9a06g032.dtsi
index 45f60ee..7548291 100644
--- a/dts/upstream/src/arm/renesas/r9a06g032.dtsi
+++ b/dts/upstream/src/arm/renesas/r9a06g032.dtsi
@@ -316,6 +316,24 @@
data-width = <8>;
};
+ gmac1: ethernet@44000000 {
+ compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
+ reg = <0x44000000 0x2000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+ clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
+ clock-names = "stmmaceth";
+ power-domains = <&sysctrl>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
+ pcs-handle = <&mii_conv1>;
+ status = "disabled";
+ };
+
gmac2: ethernet@44002000 {
compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
reg = <0x44002000 0x2000>;
@@ -466,6 +484,7 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
usbphy: usb-phy {
diff --git a/dts/upstream/src/arm/rockchip/rk3036.dtsi b/dts/upstream/src/arm/rockchip/rk3036.dtsi
index 04af224..96279d1 100644
--- a/dts/upstream/src/arm/rockchip/rk3036.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3036.dtsi
@@ -402,6 +402,7 @@
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
diff --git a/dts/upstream/src/arm/rockchip/rk3066a-mk808.dts b/dts/upstream/src/arm/rockchip/rk3066a-mk808.dts
index 06790f0..4de9a45 100644
--- a/dts/upstream/src/arm/rockchip/rk3066a-mk808.dts
+++ b/dts/upstream/src/arm/rockchip/rk3066a-mk808.dts
@@ -143,6 +143,14 @@
};
};
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2s0 {
+ status = "okay";
+};
+
&mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/dts/upstream/src/arm/rockchip/rk3066a.dtsi b/dts/upstream/src/arm/rockchip/rk3066a.dtsi
index 15cbd94..3f6d494 100644
--- a/dts/upstream/src/arm/rockchip/rk3066a.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3066a.dtsi
@@ -53,6 +53,22 @@
ports = <&vop0_out>, <&vop1_out>;
};
+ hdmi_sound: hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ status = "disabled";
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+ };
+
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
@@ -880,7 +896,3 @@
&wdt {
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
-
-&emac {
- compatible = "rockchip,rk3066-emac";
-};
diff --git a/dts/upstream/src/arm/rockchip/rk3128.dtsi b/dts/upstream/src/arm/rockchip/rk3128.dtsi
index fb98873..23e6333 100644
--- a/dts/upstream/src/arm/rockchip/rk3128.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3128.dtsi
@@ -216,6 +216,8 @@
<&cru ACLK_LCDC0>,
<&cru HCLK_LCDC0>,
<&cru PCLK_MIPI>,
+ <&cru PCLK_MIPIPHY>,
+ <&cru SCLK_MIPI_24M>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru ACLK_VIO0>,
@@ -275,6 +277,43 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
+
+ vop_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_vop>;
+ };
+ };
+ };
+
+ dsi: dsi@10110000 {
+ compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x10110000 0x4000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI>;
+ clock-names = "pclk";
+ phys = <&dphy>;
+ phy-names = "dphy";
+ power-domains = <&power RK3128_PD_VIO>;
+ resets = <&cru SRST_VIO_MIPI_DSI>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in: port@0 {
+ reg = <0>;
+
+ dsi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_dsi>;
+ };
+ };
+
+ dsi_out: port@1 {
+ reg = <1>;
+ };
};
};
@@ -360,6 +399,41 @@
status = "disabled";
};
+ i2s_8ch: i2s@10200000 {
+ compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
+ reg = <0x10200000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&pdma 14>, <&pdma 15>;
+ dma-names = "tx", "rx";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif: spdif@10204000 {
+ compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif";
+ reg = <0x10204000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
+ dmas = <&pdma 13>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sfc: spi@1020c000 {
+ compatible = "rockchip,sfc";
+ reg = <0x1020c000 0x8000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru 479>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ status = "disabled";
+ };
+
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
@@ -408,6 +482,21 @@
status = "disabled";
};
+ i2s_2ch: i2s@10220000 {
+ compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
+ reg = <0x10220000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ rockchip,playback-channels = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_bus>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
nfc: nand-controller@10500000 {
compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
reg = <0x10500000 0x4000>;
@@ -477,6 +566,7 @@
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
power-domains = <&power RK3128_PD_VIO>;
+ #sound-dai-cells = <0>;
status = "disabled";
ports {
@@ -496,6 +586,18 @@
};
};
+ dphy: phy@20038000 {
+ compatible = "rockchip,rk3128-dsi-dphy";
+ reg = <0x20038000 0x4000>;
+ clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
+ clock-names = "ref", "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power RK3128_PD_VIO>;
+ resets = <&cru SRST_MIPIPHY_P>;
+ reset-names = "apb";
+ status = "disabled";
+ };
+
timer0: timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
@@ -1104,6 +1206,32 @@
};
};
+ sfc {
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>;
+ };
+
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+ <1 RK_PD1 3 &pcfg_pull_default>,
+ <1 RK_PD2 3 &pcfg_pull_default>,
+ <1 RK_PD3 3 &pcfg_pull_default>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs0: sfc-cs0 {
+ rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
+ };
+
+ sfc_cs1: sfc-cs1 {
+ rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
+ };
+ };
+
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
diff --git a/dts/upstream/src/arm/rockchip/rk3xxx.dtsi b/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
index f37137f..e6a78bc 100644
--- a/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
@@ -194,17 +194,14 @@
};
emac: ethernet@10204000 {
- compatible = "snps,arc-emac";
+ compatible = "rockchip,rk3066-emac";
reg = <0x10204000 0x3c>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-
- rockchip,grf = <&grf>;
-
clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
clock-names = "hclk", "macref";
max-speed = <100>;
phy-mode = "rmii";
-
+ rockchip,grf = <&grf>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts b/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
index 0c2396b..7707d1b 100644
--- a/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
+++ b/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
@@ -69,8 +69,7 @@
&mdio {
phy: ethernet-phy@0 {
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
+ compatible = "ethernet-phy-id001c.c916";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <ð_phy_rst>;
diff --git a/dts/upstream/src/arm/st/stih407-family.dtsi b/dts/upstream/src/arm/st/stih407-family.dtsi
index 29302e7..35a55ae 100644
--- a/dts/upstream/src/arm/st/stih407-family.dtsi
+++ b/dts/upstream/src/arm/st/stih407-family.dtsi
@@ -33,7 +33,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
@@ -52,8 +52,9 @@
clock-latency = <100000>;
cpu0-supply = <&pwm_regulator>;
st,syscfg = <&syscfg_core 0x8e0>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
@@ -66,6 +67,7 @@
1200000 0
800000 0
500000 0>;
+ #cooling-cells = <2>;
};
};
diff --git a/dts/upstream/src/arm/st/stih410.dtsi b/dts/upstream/src/arm/st/stih410.dtsi
index 29e95e9..a692318 100644
--- a/dts/upstream/src/arm/st/stih410.dtsi
+++ b/dts/upstream/src/arm/st/stih410.dtsi
@@ -270,6 +270,7 @@
clock-names = "thermal";
clocks = <&clk_sysin>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
};
cec@94a087c {
diff --git a/dts/upstream/src/arm/st/stih418.dtsi b/dts/upstream/src/arm/st/stih418.dtsi
index b35b9b7..8fb8b3a 100644
--- a/dts/upstream/src/arm/st/stih418.dtsi
+++ b/dts/upstream/src/arm/st/stih418.dtsi
@@ -6,23 +6,26 @@
#include "stih418-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
+#include <dt-bindings/thermal/thermal.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
+ #cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
+ #cooling-cells = <2>;
};
};
@@ -44,6 +47,38 @@
reset-names = "global", "port";
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <250>; /* 250ms */
+ polling-delay = <1000>; /* 1000ms */
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu_crit: cpu-crit {
+ temperature = <95000>; /* 95C */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ cpu_alert: cpu-alert {
+ temperature = <85000>; /* 85C */
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc {
rng11: rng@8a8a000 {
status = "disabled";
@@ -107,12 +142,13 @@
assigned-clock-rates = <200000000>;
};
- thermal@91a0000 {
+ thermal: thermal@91a0000 {
compatible = "st,stih407-thermal";
reg = <0x91a0000 0x28>;
clock-names = "thermal";
clocks = <&clk_sysin>;
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
};
};
};
diff --git a/dts/upstream/src/arm/st/stm32f429.dtsi b/dts/upstream/src/arm/st/stm32f429.dtsi
index 8efcda9..ad91b74 100644
--- a/dts/upstream/src/arm/st/stm32f429.dtsi
+++ b/dts/upstream/src/arm/st/stm32f429.dtsi
@@ -579,6 +579,7 @@
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
};
exti: interrupt-controller@40013c00 {
diff --git a/dts/upstream/src/arm/st/stm32mp13-pinctrl.dtsi b/dts/upstream/src/arm/st/stm32mp13-pinctrl.dtsi
index 32c5d8a..c9f588a 100644
--- a/dts/upstream/src/arm/st/stm32mp13-pinctrl.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,14 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ /omit-if-no-ref/
+ adc1_pins_a: adc1-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
+ };
+ };
+
+ /omit-if-no-ref/
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
@@ -13,6 +21,241 @@
};
};
+ /omit-if-no-ref/
+ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
+ <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
+ };
+ };
+
+ /omit-if-no-ref/
+ dcmipp_pins_a: dcmi-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ dcmipp_sleep_pins_a: dcmi-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
+ /omit-if-no-ref/
+ eth1_rgmii_pins_a: eth1-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
+ /omit-if-no-ref/
+ eth1_rmii_pins_a: eth1-rmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ /omit-if-no-ref/
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 6, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
+ /omit-if-no-ref/
+ eth2_rmii_pins_a: eth2-rmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
+ };
+ };
+
+ /omit-if-no-ref/
+ goodix_pins_a: goodix-0 {
+ /*
+ * touchscreen reset needs to be configured
+ * via the pinctrl not the driver (a pull-down resistor
+ * has been soldered onto the reset line which forces
+ * the touchscreen to reset state).
+ */
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, GPIO)>;
+ output-high;
+ bias-pull-up;
+ };
+ /*
+ * Interrupt line must have a pull-down resistor
+ * in order to freeze the i2c address at 0x5D
+ */
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 5, GPIO)>;
+ bias-pull-down;
+ };
+ };
+
+ /omit-if-no-ref/
i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
@@ -23,6 +266,7 @@
};
};
+ /omit-if-no-ref/
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
@@ -30,6 +274,7 @@
};
};
+ /omit-if-no-ref/
i2c5_pins_a: i2c5-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
@@ -40,6 +285,7 @@
};
};
+ /omit-if-no-ref/
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
@@ -47,6 +293,26 @@
};
};
+ /omit-if-no-ref/
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ /omit-if-no-ref/
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */
@@ -77,6 +343,7 @@
};
};
+ /omit-if-no-ref/
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */
@@ -104,6 +371,51 @@
};
};
+ /omit-if-no-ref/
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ /omit-if-no-ref/
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
+ /omit-if-no-ref/
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
@@ -111,6 +423,7 @@
};
};
+ /omit-if-no-ref/
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
@@ -120,12 +433,14 @@
};
};
+ /omit-if-no-ref/
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
};
};
+ /omit-if-no-ref/
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
@@ -135,12 +450,31 @@
};
};
+ /omit-if-no-ref/
pwm4_sleep_pins_a: pwm4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
};
};
+ /omit-if-no-ref/
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
+ };
+ };
+
+ /omit-if-no-ref/
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
@@ -150,12 +484,31 @@
};
};
+ /omit-if-no-ref/
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
};
};
+ /omit-if-no-ref/
+ pwm13_pins_a: pwm13-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm13_sleep_pins_a: pwm13-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
+ };
+ };
+
+ /omit-if-no-ref/
pwm14_pins_a: pwm14-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
@@ -165,12 +518,107 @@
};
};
+ /omit-if-no-ref/
pwm14_sleep_pins_a: pwm14-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
};
};
+ /omit-if-no-ref/
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1a_pins_a: sai1a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -184,6 +632,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -202,6 +651,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@@ -213,6 +663,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
@@ -222,6 +673,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@@ -235,6 +687,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@@ -253,6 +706,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
@@ -264,6 +718,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
@@ -273,6 +728,80 @@
};
};
+ /omit-if-no-ref/
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ /omit-if-no-ref/
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
+ <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ spi2_sleep_pins_a: spi2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
+ <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
+ };
+ };
+
+ /omit-if-no-ref/
+ spi3_pins_a: spi3-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
+ <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ spi3_sleep_pins_a: spi3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
+ };
+ };
+
+ /omit-if-no-ref/
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
@@ -288,6 +817,7 @@
};
};
+ /omit-if-no-ref/
spi5_sleep_pins_a: spi5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
@@ -296,6 +826,7 @@
};
};
+ /omit-if-no-ref/
stm32g0_intn_pins_a: stm32g0-intn-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
@@ -303,6 +834,7 @@
};
};
+ /omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@@ -316,6 +848,7 @@
};
};
+ /omit-if-no-ref/
uart4_idle_pins_a: uart4-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
@@ -326,6 +859,7 @@
};
};
+ /omit-if-no-ref/
uart4_sleep_pins_a: uart4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
@@ -333,6 +867,84 @@
};
};
+ /omit-if-no-ref/
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ uart4_idle_pins_b: uart4-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ uart4_sleep_pins_b: uart4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ /omit-if-no-ref/
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ uart7_idle_pins_a: uart7-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ uart7_sleep_pins_a: uart7-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
+ <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
+ };
+ };
+
+ /omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@@ -346,6 +958,7 @@
};
};
+ /omit-if-no-ref/
uart8_idle_pins_a: uart8-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
@@ -356,6 +969,7 @@
};
};
+ /omit-if-no-ref/
uart8_sleep_pins_a: uart8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
@@ -363,6 +977,7 @@
};
};
+ /omit-if-no-ref/
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
@@ -378,6 +993,7 @@
};
};
+ /omit-if-no-ref/
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
@@ -395,6 +1011,7 @@
};
};
+ /omit-if-no-ref/
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
@@ -404,6 +1021,40 @@
};
};
+ /omit-if-no-ref/
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
+ };
+ };
+
+ /omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
@@ -419,6 +1070,7 @@
};
};
+ /omit-if-no-ref/
usart2_idle_pins_a: usart2-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
@@ -436,6 +1088,7 @@
};
};
+ /omit-if-no-ref/
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
@@ -444,4 +1097,48 @@
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
};
};
+
+ /omit-if-no-ref/
+ usart2_pins_b: usart2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart2_idle_pins_b: usart2-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart2_sleep_pins_b: usart2-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
};
diff --git a/dts/upstream/src/arm/st/stm32mp131.dtsi b/dts/upstream/src/arm/st/stm32mp131.dtsi
index 6704cee..e1a764d 100644
--- a/dts/upstream/src/arm/st/stm32mp131.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp131.dtsi
@@ -979,6 +979,12 @@
ts_cal2: calib@5e {
reg = <0x5e 0x2>;
};
+ ethernet_mac1_address: mac1@e4 {
+ reg = <0xe4 0x6>;
+ };
+ ethernet_mac2_address: mac2@ea {
+ reg = <0xea 0x6>;
+ };
};
etzpc: bus@5c007000 {
@@ -1505,6 +1511,38 @@
status = "disabled";
};
+ ethernet1: ethernet@5800a000 {
+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <&exti 68 1>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH1MAC>,
+ <&rcc ETH1TX>,
+ <&rcc ETH1RX>,
+ <&rcc ETH1STP>,
+ <&rcc ETH1CK_K>;
+ st,syscon = <&syscfg 0x4 0xff0000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,tso;
+ access-controllers = <&etzpc 48>;
+ status = "disabled";
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,wr_osr_lmt = <0x7>;
+ };
+ };
+
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/st/stm32mp133.dtsi b/dts/upstream/src/arm/st/stm32mp133.dtsi
index 3e394c8..73e4700 100644
--- a/dts/upstream/src/arm/st/stm32mp133.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp133.dtsi
@@ -68,4 +68,35 @@
};
};
};
+
+ ethernet2: ethernet@5800e000 {
+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
+ reg = <0x5800e000 0x2000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc ETH2MAC>,
+ <&rcc ETH2TX>,
+ <&rcc ETH2RX>,
+ <&rcc ETH2STP>,
+ <&rcc ETH2CK_K>;
+ st,syscon = <&syscfg 0x4 0xff000000>;
+ snps,mixed-burst;
+ snps,pbl = <2>;
+ snps,axi-config = <&stmmac_axi_config_2>;
+ snps,tso;
+ access-controllers = <&etzpc 49>;
+ status = "disabled";
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,wr_osr_lmt = <0x7>;
+ };
+ };
};
diff --git a/dts/upstream/src/arm/st/stm32mp135f-dhcor-dhsbc.dts b/dts/upstream/src/arm/st/stm32mp135f-dhcor-dhsbc.dts
new file mode 100644
index 0000000..bacb70b
--- /dev/null
+++ b/dts/upstream/src/arm/st/stm32mp135f-dhcor-dhsbc.dts
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ *
+ * DHCOR STM32MP13 variant:
+ * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
+ * DHCOR PCB number: 718-100 or newer
+ * DHSBC PCB number: 719-100 or newer
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp135.dtsi"
+#include "stm32mp13xf.dtsi"
+#include "stm32mp13xx-dhcor-som.dtsi"
+
+/ {
+ model = "DH electronics STM32MP135F DHCOR DHSBC";
+ compatible = "dh,stm32mp135f-dhcor-dhsbc",
+ "dh,stm32mp135f-dhcor-som",
+ "st,stm32mp135";
+
+ aliases {
+ ethernet0 = ðernet1;
+ ethernet1 = ðernet2;
+ serial2 = &usart1;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&adc_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>;
+ vdda-supply = <&vdd_adc>;
+ vref-supply = <&vdd_adc>;
+ status = "okay";
+
+ adc1: adc@0 {
+ status = "okay";
+
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
+ * Use arbitrary margin here (e.g. 5us).
+ *
+ * The pinmux pins must be set as ANALOG, use datasheet
+ * DS13483 Table 7. STM32MP135C/F ball definitions to
+ * find out which 'pin name' maps to which 'additional
+ * functions', which lists the mapping between pin and
+ * ADC channel. In this case, PA5 maps to ADC1_INP2 and
+ * PF13 maps to ADC1_INP11 .
+ */
+ channel@2 {
+ reg = <2>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ channel@11 {
+ reg = <11>;
+ st,min-sample-time-ns = <5000>;
+ };
+
+ /* Expansion connector: INP12:pin29 */
+ channel@12 {
+ reg = <12>;
+ st,min-sample-time-ns = <5000>;
+ };
+ };
+};
+
+ðernet1 {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <ð1_rgmii_pins_a>;
+ pinctrl-1 = <ð1_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ st,ext-phyclk;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy1: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
+ interrupt-parent = <&gpiog>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+ðernet2 {
+ phy-handle = <ðphy2>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <ð2_rgmii_pins_a>;
+ pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ st,ext-phyclk;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ ethphy2: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
+ interrupt-parent = <&gpiog>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ reg = <1>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <55000>;
+ reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpioa {
+ gpio-line-names = "", "", "", "",
+ "", "DHSBC_USB_PWR_CC1", "", "",
+ "", "", "", "DHSBC_nETH1_RST",
+ "", "DHCOR_HW-CODING_0", "", "";
+};
+
+&gpiob {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "DHCOR_BT_HOST_WAKE",
+ "", "", "", "",
+ "", "DHSBC_nTPM_CS", "", "";
+};
+
+&gpioc {
+ gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpiod {
+ gpio-line-names = "", "", "", "",
+ "", "DHCOR_RAM-CODING_0", "", "",
+ "", "DHCOR_RAM-CODING_1", "", "",
+ "", "", "", "";
+};
+
+&gpioe {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "DHSBC_nTPM_RST", "", "",
+ "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", "";
+};
+
+&gpiof {
+ gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "",
+ "", "", "", "",
+ "", "", "", "",
+ "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", "";
+};
+
+&gpiog {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "",
+ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB";
+};
+
+&gpioi {
+ gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1",
+ "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT",
+ "DHSBC_BOOT0", "DHSBC_BOOT1",
+ "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS";
+};
+
+&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_b>;
+ pinctrl-1 = <&i2c5_sleep_pins_b>;
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+ status = "okay";
+};
+
+&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
+ clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>;
+ pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>;
+};
+
+&scmi_voltd {
+ status = "disabled";
+};
+
+&spi2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi2_pins_a>;
+ pinctrl-1 = <&spi2_sleep_pins_a>;
+ cs-gpios = <&gpiob 13 0>;
+ status = "okay";
+
+ st33htph: tpm@0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ };
+};
+
+&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi3_pins_a>;
+ pinctrl-1 = <&spi3_sleep_pins_a>;
+ cs-gpios = <&gpiof 3 0>;
+ status = "disabled";
+};
+
+&timers5 { /* Expansion connector: CH3:pin31 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@4 {
+ status = "okay";
+ };
+};
+
+&timers13 { /* Expansion connector: CH1:pin32 */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ pwm {
+ pinctrl-0 = <&pwm13_pins_a>;
+ pinctrl-1 = <&pwm13_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@12 {
+ status = "okay";
+ };
+};
+
+&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-1 = <&usart1_sleep_pins_b>;
+ pinctrl-2 = <&usart1_idle_pins_b>;
+ status = "okay";
+};
+
+&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_b>;
+ pinctrl-1 = <&usart2_sleep_pins_b>;
+ pinctrl-2 = <&usart2_idle_pins_b>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbh_ohci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb33d-supply = <&usb33>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ st,current-boost-microamp = <1000>;
+ st,decrease-hs-slew-rate;
+ st,tune-hs-dc-level = <2>;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <11>;
+ st,trim-hs-impedance = <2>;
+ st,tune-squelch-level = <1>;
+ st,enable-hs-rx-gain-eq;
+ st,no-hs-ftime-ctrl;
+ st,no-lsfs-sc;
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ label = "Type-C";
+ self-powered;
+ type = "micro";
+ };
+};
diff --git a/dts/upstream/src/arm/st/stm32mp135f-dk.dts b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
index 567e53a..1af335a 100644
--- a/dts/upstream/src/arm/st/stm32mp135f-dk.dts
+++ b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
@@ -19,6 +19,7 @@
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
aliases {
+ ethernet0 = ðernet1;
serial0 = &uart4;
serial1 = &usart1;
serial2 = &uart8;
@@ -29,6 +30,20 @@
stdout-path = "serial0:115200n8";
};
+ clocks {
+ clk_ext_camera: clk-ext-camera {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_mco1: clk-mco1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
@@ -141,6 +156,45 @@
status = "okay";
};
+&dcmipp {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmipp_pins_a>;
+ pinctrl-1 = <&dcmipp_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ dcmipp_0: endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ };
+ };
+};
+
+ðernet1 {
+ status = "okay";
+ pinctrl-0 = <ð1_rmii_pins_a>;
+ pinctrl-1 = <ð1_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ phy-handle = <&phy0_eth1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0_eth1: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0007.c131";
+ reg = <0>;
+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+};
+
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
@@ -201,6 +255,76 @@
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
+
+ stmipi: csi2rx@14 {
+ compatible = "st,st-mipid02";
+ reg = <0x14>;
+ clocks = <&clk_mco1>;
+ clock-names = "xclk";
+ VDDE-supply = <&scmi_v1v8_periph>;
+ VDDIN-supply = <&scmi_v1v8_periph>;
+ reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ mipid02_0: endpoint {
+ data-lanes = <1 2>;
+ lane-polarities = <0 0 0>;
+ remote-endpoint = <&gc2145_ep>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+
+ mipid02_2: endpoint {
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ remote-endpoint = <&dcmipp_0>;
+ };
+ };
+ };
+ };
+
+ gc2145: camera@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ iovdd-supply = <&scmi_v3v3_sw>;
+ avdd-supply = <&scmi_v3v3_sw>;
+ dvdd-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ status = "okay";
+
+ port {
+ gc2145_ep: endpoint {
+ remote-endpoint = <&mipid02_0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <120000000 192000000 240000000>;
+ };
+ };
+ };
+
+ goodix: goodix-ts@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&goodix_pins_a>;
+ interrupt-parent = <&gpiof>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ AVDD28-supply = <&scmi_v3v3_sw>;
+ VDDIO-supply = <&scmi_v3v3_sw>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <272>;
+ status = "okay" ;
+ };
};
&iwdg2 {
@@ -273,6 +397,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
+ /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -288,6 +413,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
+ /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */
pinctrl-0 = <&pwm4_pins_a>;
pinctrl-1 = <&pwm4_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -303,6 +429,7 @@
/delete-property/dma-names;
status = "disabled";
pwm {
+ /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
@@ -316,6 +443,7 @@
&timers14 {
status = "disabled";
pwm {
+ /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */
pinctrl-0 = <&pwm14_pins_a>;
pinctrl-1 = <&pwm14_sleep_pins_a>;
pinctrl-names = "default", "sleep";
diff --git a/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
new file mode 100644
index 0000000..ddad649
--- /dev/null
+++ b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
+#include "stm32mp13-pinctrl.dtsi"
+
+/ {
+ model = "DH electronics STM32MP13xx DHCOR SoM";
+ compatible = "dh,stm32mp131a-dhcor-som",
+ "st,stm32mp131";
+
+ aliases {
+ mmc0 = &sdmmc2;
+ mmc1 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ rtc0 = &rv3032;
+ spi0 = &qspi;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ optee@dd000000 {
+ reg = <0xdd000000 0x3000000>;
+ no-map;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <96>;
+ i2c-scl-falling-time-ns = <3>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&vin>;
+ ldo2-supply = <&vin>;
+ ldo3-supply = <&vin>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
+ ldo6-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcpu: buck1 { /* VDD_CPU_1V2 */
+ regulator-name = "vddcpu";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 { /* VDD_DDR_1V35 */
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 { /* VDD_3V3_1V8 */
+ regulator-name = "vdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vddcore: buck4 { /* VDD_CORE_1V2 */
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_adc: ldo1 { /* VDD_ADC_1V8 */
+ regulator-name = "vdd_adc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
+ regulator-name = "vdd_ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vdd_ldo3: ldo3 { /* LDO3_OUT */
+ regulator-name = "vdd_ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO3 0>;
+ };
+
+ vdd_usb: ldo4 { /* VDD_USB_3V3 */
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ };
+
+ vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
+ regulator-name = "vdd_sd2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost { /* BST_OUT_5V2 */
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c256"; /* ST M24256 */
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+
+ rv3032: rtc@51 {
+ compatible = "microcrystal,rv3032";
+ reg = <0x51>;
+ interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a
+ &qspi_bk1_sleep_pins_a
+ &qspi_cs1_sleep_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+/* Console UART */
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_b>;
+ pinctrl-1 = <&uart4_sleep_pins_b>;
+ pinctrl-2 = <&uart4_idle_pins_b>;
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+/* Bluetooth */
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_a>;
+ pinctrl-1 = <&uart7_sleep_pins_a>;
+ pinctrl-2 = <&uart7_idle_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
+ max-speed = <3000000>;
+ device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* SDIO WiFi */
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 { /* muRata 1YN */
+ reg = <1>;
+ compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpioe>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+/* eMMC */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ bus-width = <8>;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ vqmmc-supply = <&vdd>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/st/stm32mp151.dtsi b/dts/upstream/src/arm/st/stm32mp151.dtsi
index 90c5c72..4f878ec 100644
--- a/dts/upstream/src/arm/st/stm32mp151.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp151.dtsi
@@ -50,6 +50,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>;
+ arm,no-tick-in-suspend;
};
clocks {
diff --git a/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
index 306e1bc..847b360 100644
--- a/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
@@ -62,6 +62,11 @@
reset-names = "mcu_rst", "hold_boot";
};
+&optee {
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
index 956da5f..4328028 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
@@ -68,6 +68,11 @@
reset-names = "mcu_rst", "hold_boot";
};
+&optee {
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
index 8e4b0db..6f27d79 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
@@ -67,6 +67,11 @@
reset-names = "mcu_rst", "hold_boot";
};
+&optee {
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
index 72b9cab..6ae391b 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
@@ -72,6 +72,11 @@
reset-names = "mcu_rst", "hold_boot";
};
+&optee {
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts b/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
index 527c33b..36e6055 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
@@ -147,11 +147,6 @@
status = "okay";
};
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
&rtc {
status = "okay";
};
@@ -211,11 +206,3 @@
&usbphyc {
status = "okay";
};
-
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
diff --git a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
index cfaf8ad..c87fd96 100644
--- a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
@@ -379,11 +379,6 @@
};
};
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
&rtc {
status = "okay";
};
@@ -590,14 +585,6 @@
status = "okay";
};
-&usbphyc_port0 {
- phy-supply = <&vdd_usb>;
-};
-
-&usbphyc_port1 {
- phy-supply = <&vdd_usb>;
-};
-
&vrefbuf {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-osd32.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-osd32.dtsi
index aeb71c4..2022a1f 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-osd32.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-osd32.dtsi
@@ -214,3 +214,16 @@
&rng1 {
status = "okay";
};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/dts/upstream/src/arm/ti/davinci/da850-evm.dts b/dts/upstream/src/arm/ti/davinci/da850-evm.dts
index 6c59362..1f5cd35 100644
--- a/dts/upstream/src/arm/ti/davinci/da850-evm.dts
+++ b/dts/upstream/src/arm/ti/davinci/da850-evm.dts
@@ -65,7 +65,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: 480x272 {
+ timing0: timing-480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
diff --git a/dts/upstream/src/arm/ti/omap/am335x-guardian.dts b/dts/upstream/src/arm/ti/omap/am335x-guardian.dts
index 56e5d95..4b070e6 100644
--- a/dts/upstream/src/arm/ti/omap/am335x-guardian.dts
+++ b/dts/upstream/src/arm/ti/omap/am335x-guardian.dts
@@ -74,7 +74,7 @@
pinctrl-1 = <&lcd_pins_sleep>;
display-timings {
- 320x240 {
+ timing-320x240 {
hactive = <320>;
vactive = <240>;
hback-porch = <68>;
diff --git a/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts b/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts
index f38f5bf..17574d0 100644
--- a/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts
+++ b/dts/upstream/src/arm/ti/omap/am335x-pdu001.dts
@@ -67,7 +67,7 @@
};
display-timings {
- 240x320p16 {
+ timing-240x320p16 {
clock-frequency = <6500000>;
hactive = <240>;
vactive = <320>;
diff --git a/dts/upstream/src/arm/ti/omap/am335x-pepper.dts b/dts/upstream/src/arm/ti/omap/am335x-pepper.dts
index d5a4a21..e7d561a 100644
--- a/dts/upstream/src/arm/ti/omap/am335x-pepper.dts
+++ b/dts/upstream/src/arm/ti/omap/am335x-pepper.dts
@@ -202,7 +202,7 @@
};
display-timings {
native-mode = <&timing0>;
- timing0: 480x272 {
+ timing0: timing-480x272 {
clock-frequency = <18400000>;
hactive = <480>;
vactive = <272>;
diff --git a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
index eb1ec85..e6a1895 100644
--- a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
+++ b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
@@ -196,7 +196,6 @@
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
- ti,enable-id-detection;
id-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/dts/upstream/src/arm/ti/omap/omap3-n900.dts b/dts/upstream/src/arm/ti/omap/omap3-n900.dts
index 07c5b96..4bde334 100644
--- a/dts/upstream/src/arm/ti/omap/omap3-n900.dts
+++ b/dts/upstream/src/arm/ti/omap/omap3-n900.dts
@@ -781,7 +781,7 @@
mount-matrix = "-1", "0", "0",
"0", "1", "0",
- "0", "0", "1";
+ "0", "0", "-1";
};
cam1: camera@3e {
diff --git a/dts/upstream/src/arm/vt8500/vt8500-bv07.dts b/dts/upstream/src/arm/vt8500/vt8500-bv07.dts
index e9f55bd..38a2da5 100644
--- a/dts/upstream/src/arm/vt8500/vt8500-bv07.dts
+++ b/dts/upstream/src/arm/vt8500/vt8500-bv07.dts
@@ -16,7 +16,7 @@
bits-per-pixel = <16>;
display-timings {
native-mode = <&timing0>;
- timing0: 800x480 {
+ timing0: timing-800x480 {
clock-frequency = <0>; /* unused but required */
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/vt8500/vt8500.dtsi b/dts/upstream/src/arm/vt8500/vt8500.dtsi
index b7e09ef..f23cb5e 100644
--- a/dts/upstream/src/arm/vt8500/vt8500.dtsi
+++ b/dts/upstream/src/arm/vt8500/vt8500.dtsi
@@ -115,7 +115,7 @@
interrupts = <43>;
};
- uhci@d8007b00 {
+ usb@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
diff --git a/dts/upstream/src/arm/vt8500/wm8505-ref.dts b/dts/upstream/src/arm/vt8500/wm8505-ref.dts
index 2d77c08..8ce9e2e 100644
--- a/dts/upstream/src/arm/vt8500/wm8505-ref.dts
+++ b/dts/upstream/src/arm/vt8500/wm8505-ref.dts
@@ -16,7 +16,7 @@
bits-per-pixel = <32>;
display-timings {
native-mode = <&timing0>;
- timing0: 800x480 {
+ timing0: timing-800x480 {
clock-frequency = <0>; /* unused but required */
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/vt8500/wm8505.dtsi b/dts/upstream/src/arm/vt8500/wm8505.dtsi
index 168cd12..d9e1280 100644
--- a/dts/upstream/src/arm/vt8500/wm8505.dtsi
+++ b/dts/upstream/src/arm/vt8500/wm8505.dtsi
@@ -213,7 +213,7 @@
interrupts = <1>;
};
- uhci@d8007300 {
+ usb@d8007300 {
compatible = "platform-uhci";
reg = <0xd8007300 0x200>;
interrupts = <0>;
diff --git a/dts/upstream/src/arm/vt8500/wm8650-mid.dts b/dts/upstream/src/arm/vt8500/wm8650-mid.dts
index f6a4214..7977b6c 100644
--- a/dts/upstream/src/arm/vt8500/wm8650-mid.dts
+++ b/dts/upstream/src/arm/vt8500/wm8650-mid.dts
@@ -17,7 +17,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: 800x480 {
+ timing0: timing-800x480 {
clock-frequency = <0>; /* unused but required */
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/vt8500/wm8650.dtsi b/dts/upstream/src/arm/vt8500/wm8650.dtsi
index bc057b6..35d12d7 100644
--- a/dts/upstream/src/arm/vt8500/wm8650.dtsi
+++ b/dts/upstream/src/arm/vt8500/wm8650.dtsi
@@ -185,7 +185,7 @@
interrupts = <43>;
};
- uhci@d8007b00 {
+ usb@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <43>;
diff --git a/dts/upstream/src/arm/vt8500/wm8750.dtsi b/dts/upstream/src/arm/vt8500/wm8750.dtsi
index 33aeb37..b292f85 100644
--- a/dts/upstream/src/arm/vt8500/wm8750.dtsi
+++ b/dts/upstream/src/arm/vt8500/wm8750.dtsi
@@ -257,13 +257,13 @@
interrupts = <26>;
};
- uhci@d8007b00 {
+ usb@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <26>;
};
- uhci@d8008d00 {
+ usb@d8008d00 {
compatible = "platform-uhci";
reg = <0xd8008d00 0x200>;
interrupts = <26>;
diff --git a/dts/upstream/src/arm/vt8500/wm8850-w70v2.dts b/dts/upstream/src/arm/vt8500/wm8850-w70v2.dts
index c7a6fe0..5d40932 100644
--- a/dts/upstream/src/arm/vt8500/wm8850-w70v2.dts
+++ b/dts/upstream/src/arm/vt8500/wm8850-w70v2.dts
@@ -28,7 +28,7 @@
bits-per-pixel = <16>;
display-timings {
native-mode = <&timing0>;
- timing0: 800x480 {
+ timing0: timing-800x480 {
clock-frequency = <0>; /* unused but required */
hactive = <800>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/vt8500/wm8850.dtsi b/dts/upstream/src/arm/vt8500/wm8850.dtsi
index 65c9271..c61717e 100644
--- a/dts/upstream/src/arm/vt8500/wm8850.dtsi
+++ b/dts/upstream/src/arm/vt8500/wm8850.dtsi
@@ -244,13 +244,13 @@
interrupts = <26>;
};
- uhci@d8007b00 {
+ usb@d8007b00 {
compatible = "platform-uhci";
reg = <0xd8007b00 0x200>;
interrupts = <26>;
};
- uhci@d8008d00 {
+ usb@d8008d00 {
compatible = "platform-uhci";
reg = <0xd8008d00 0x200>;
interrupts = <26>;
diff --git a/dts/upstream/src/arm64/airoha/en7581-evb.dts b/dts/upstream/src/arm64/airoha/en7581-evb.dts
new file mode 100644
index 0000000..cf58e43
--- /dev/null
+++ b/dts/upstream/src/arm64/airoha/en7581-evb.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/* Bootloader installs ATF here */
+/memreserve/ 0x80000000 0x200000;
+
+#include "en7581.dtsi"
+
+/ {
+ model = "Airoha EN7581 Evaluation Board";
+ compatible = "airoha,en7581-evb", "airoha,en7581";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+};
diff --git a/dts/upstream/src/arm64/airoha/en7581.dtsi b/dts/upstream/src/arm64/airoha/en7581.dtsi
new file mode 100644
index 0000000..55eb176
--- /dev/null
+++ b/dts/upstream/src/arm64/airoha/en7581.dtsi
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ npu-binary@84000000 {
+ no-map;
+ reg = <0x0 0x84000000 0x0 0xa00000>;
+ };
+
+ npu-flag@84b0000 {
+ no-map;
+ reg = <0x0 0x84b00000 0x0 0x100000>;
+ };
+
+ npu-pkt@85000000 {
+ no-map;
+ reg = <0x0 0x85000000 0x0 0x1a00000>;
+ };
+
+ npu-phyaddr@86b00000 {
+ no-map;
+ reg = <0x0 0x86b00000 0x0 0x100000>;
+ };
+
+ npu-rxdesc@86d00000 {
+ no-map;
+ reg = <0x0 0x86d00000 0x0 0x100000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@9000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x09000000 0x0 0x20000>,
+ <0x0 0x09080000 0x0 0x80000>,
+ <0x0 0x09400000 0x0 0x2000>,
+ <0x0 0x09500000 0x0 0x2000>,
+ <0x0 0x09600000 0x0 0x20000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ uart1: serial@1fbf0000 {
+ compatible = "ns16550";
+ reg = <0x0 0x1fbf0000 0x0 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1843200>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-lts.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-lts.dts
index 596a259..709fe65 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-lts.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-lts.dts
@@ -5,7 +5,7 @@
#include "sun50i-a64-sopine-baseboard.dts"
/ {
- model = "Pine64 LTS";
+ model = "Pine64 PINE A64 LTS";
compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
"allwinner,sun50i-a64";
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-plus.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
index b54099b..026d843 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64-plus.dts
@@ -4,7 +4,7 @@
#include "sun50i-a64-pine64.dts"
/ {
- model = "Pine64+";
+ model = "Pine64 PINE A64+";
compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
/* TODO: Camera, touchscreen, etc. */
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64.dts
index 2accb5d..09e71fd 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pine64.dts
@@ -9,7 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Pine64";
+ model = "Pine64 PINE A64";
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
index 6c65d5b..379c2c8 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
@@ -13,7 +13,7 @@
#include <dt-bindings/pwm/pwm.h>
/ {
- model = "Pinebook";
+ model = "Pine64 Pinebook";
compatible = "pine64,pinebook", "allwinner,sun50i-a64";
chassis-type = "laptop";
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts
index 6265360..86cc85e 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab-early-adopter.dts
@@ -9,7 +9,7 @@
#include "sun50i-a64-pinetab.dts"
/ {
- model = "PineTab, Early Adopter's version";
+ model = "Pine64 PineTab Early Adopter";
compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64";
};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab.dts
index c6007df..f5fb1ee 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinetab.dts
@@ -14,7 +14,7 @@
#include <dt-bindings/pwm/pwm.h>
/ {
- model = "PineTab, Development Sample";
+ model = "Pine64 PineTab Developer Sample";
compatible = "pine64,pinetab", "allwinner,sun50i-a64";
chassis-type = "tablet";
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
index 5e66ce1..be2347c 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -8,7 +8,7 @@
#include "sun50i-a64-sopine.dtsi"
/ {
- model = "SoPine with baseboard";
+ model = "Pine64 SOPINE on Baseboard carrier board";
compatible = "pine64,sopine-baseboard", "pine64,sopine",
"allwinner,sun50i-a64";
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
index ce4aa44..e868ca5 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
@@ -51,10 +51,16 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
- next-level-cache = <&L2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
@@ -62,10 +68,16 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
- next-level-cache = <&L2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
@@ -73,10 +85,16 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
- next-level-cache = <&L2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
@@ -84,16 +102,25 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
- next-level-cache = <&L2>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
- L2: l2-cache {
+ l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts b/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts
index 66fe039..066fbef 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64-model-b.dts
@@ -8,7 +8,7 @@
/delete-node/ ®_gmac_3v3;
/ {
- model = "Pine H64 model B";
+ model = "Pine64 PINE H64 Model B";
compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6";
wifi_pwrseq: pwrseq {
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64.dts b/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64.dts
index 3910393..c8b2755 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h6-pine-h64.dts
@@ -9,7 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Pine H64 model A";
+ model = "Pine64 PINE H64 Model A";
compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
aliases {
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h6.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h6.dtsi
index 8a8591c..2301c59 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h6.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h6.dtsi
@@ -29,6 +29,13 @@
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
@@ -39,6 +46,13 @@
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
@@ -49,6 +63,13 @@
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
@@ -59,6 +80,22 @@
clocks = <&ccu CLK_CPUX>;
clock-latency-ns = <244144>; /* 8 32k periods */
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616-cpu-opp.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616-cpu-opp.dtsi
index aca22a7..dd10aaf 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h616-cpu-opp.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h616-cpu-opp.dtsi
@@ -11,7 +11,7 @@
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
+ opp-supported-hw = <0x3f>;
};
opp-600000000 {
@@ -25,7 +25,7 @@
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
+ opp-supported-hw = <0x2d>;
};
opp-792000000 {
@@ -50,17 +50,26 @@
opp-microvolt-speed2 = <950000>;
opp-microvolt-speed3 = <950000>;
opp-microvolt-speed4 = <1020000>;
+ opp-microvolt-speed5 = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
+ opp-supported-hw = <0x3f>;
};
+ opp-1032000000 {
+ opp-hz = /bits/ 64 <1032000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-supported-hw = <0x20>;
+ };
+
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt-speed0 = <1000000>;
opp-microvolt-speed2 = <1000000>;
opp-microvolt-speed3 = <1000000>;
+ opp-microvolt-speed5 = <950000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
+ opp-supported-hw = <0x2d>;
};
opp-1200000000 {
@@ -70,8 +79,9 @@
opp-microvolt-speed2 = <1050000>;
opp-microvolt-speed3 = <1050000>;
opp-microvolt-speed4 = <1100000>;
+ opp-microvolt-speed5 = <1020000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x1f>;
+ opp-supported-hw = <0x3f>;
};
opp-1320000000 {
@@ -85,15 +95,16 @@
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0d>;
+ opp-supported-hw = <0x2d>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt-speed1 = <1100000>;
opp-microvolt-speed3 = <1100000>;
+ opp-microvolt-speed5 = <1160000>;
clock-latency-ns = <244144>; /* 8 32k periods */
- opp-supported-hw = <0x0a>;
+ opp-supported-hw = <0x2a>;
};
};
};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
index 921d5f6..b29ce73 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
@@ -27,6 +27,13 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
@@ -36,6 +43,13 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
@@ -45,6 +59,13 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
@@ -54,6 +75,22 @@
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
@@ -113,6 +150,16 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ crypto: crypto@1904000 {
+ compatible = "allwinner,sun50i-h616-crypto";
+ reg = <0x01904000 0x800>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>,
+ <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>;
+ clock-names = "bus", "mod", "ram", "trng";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h616-system-control";
reg = <0x03000000 0x1000>;
@@ -306,6 +353,15 @@
#interrupt-cells = <3>;
};
+ iommu: iommu@30f0000 {
+ compatible = "allwinner,sun50i-h616-iommu";
+ reg = <0x030f0000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_IOMMU>;
+ resets = <&ccu RST_BUS_IOMMU>;
+ #iommu-cells = <1>;
+ };
+
mmc0: mmc@4020000 {
compatible = "allwinner,sun50i-h616-mmc",
"allwinner,sun50i-a100-mmc";
@@ -589,6 +645,17 @@
status = "disabled";
};
+ gpadc: adc@5070000 {
+ compatible = "allwinner,sun50i-h616-gpadc",
+ "allwinner,sun20i-d1-gpadc";
+ reg = <0x05070000 0x400>;
+ clocks = <&ccu CLK_BUS_GPADC>;
+ resets = <&ccu RST_BUS_GPADC>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #io-channel-cells = <1>;
+ };
+
ths: thermal-sensor@5070400 {
compatible = "allwinner,sun50i-h616-ths";
reg = <0x05070400 0x400>;
@@ -602,6 +669,16 @@
#thermal-sensor-cells = <1>;
};
+ lradc: lradc@5070800 {
+ compatible = "allwinner,sun50i-h616-lradc",
+ "allwinner,sun50i-r329-lradc";
+ reg = <0x05070800 0x400>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_KEYADC>;
+ resets = <&ccu RST_BUS_KEYADC>;
+ status = "disabled";
+ };
+
usbotg: usb@5100000 {
compatible = "allwinner,sun50i-h616-musb",
"allwinner,sun8i-h3-musb";
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
index ee30584..afb49e6 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "sun50i-h616.dtsi"
-
+#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -221,7 +221,7 @@
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1160000>;
regulator-name = "vdd-cpu";
};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts
index 6303625..ff45333 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts
@@ -9,8 +9,80 @@
/ {
model = "Anbernic RG35XX H";
compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";
+
+ adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&adc_mux 0>,
+ <&adc_mux 1>,
+ <&adc_mux 2>,
+ <&adc_mux 3>;
+ pinctrl-0 = <&joy_mux_pin>;
+ pinctrl-names = "default";
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <4096 0>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <0 4096>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <0 4096>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <4096 0>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ adc_mux: adc-mux {
+ compatible = "io-channel-mux";
+ channels = "left_x", "left_y", "right_x", "right_y";
+ #io-channel-cells = <1>;
+ io-channels = <&gpadc 0>;
+ io-channel-names = "parent";
+ mux-controls = <&gpio_mux>;
+ settle-time-us = <100>;
+ };
+
+ gpio_mux: mux-controller {
+ compatible = "gpio-mux";
+ mux-gpios = <&pio 8 1 GPIO_ACTIVE_LOW>,
+ <&pio 8 2 GPIO_ACTIVE_LOW>;
+ #mux-control-cells = <0>;
+ };
};
+&gpadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ channel@0 {
+ reg = <0>;
+ };
+};
+
&gpio_keys_gamepad {
button-thumbl {
label = "GPIO Thumb Left";
@@ -34,3 +106,10 @@
&ohci1 {
status = "okay";
};
+
+&pio {
+ joy_mux_pin: joy-mux-pin {
+ pins = "PI0";
+ function = "gpio_out";
+ };
+};
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
index cbbc53c..0def0b0 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
@@ -34,6 +34,7 @@
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x0>;
};
@@ -41,6 +42,7 @@
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x1>;
};
@@ -48,6 +50,7 @@
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x2>;
};
@@ -55,8 +58,15 @@
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x3>;
};
+
+ l2_shared: cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
};
firmware {
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
index 26173f0..4eee777 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
@@ -180,8 +180,6 @@
&qspi {
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
index 81d0e91..7c53cb9 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
@@ -169,8 +169,6 @@
&qspi {
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/dts/upstream/src/arm64/amlogic/amlogic-a4.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-a4.dtsi
index 73ca1d7..de10e7a 100644
--- a/dts/upstream/src/arm64/amlogic/amlogic-a4.dtsi
+++ b/dts/upstream/src/arm64/amlogic/amlogic-a4.dtsi
@@ -4,6 +4,7 @@
*/
#include "amlogic-a4-common.dtsi"
+#include <dt-bindings/power/amlogic,a4-pwrc.h>
/ {
cpus {
#address-cells = <2>;
@@ -37,4 +38,13 @@
enable-method = "psci";
};
};
+
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gxbb-sm";
+
+ pwrc: power-controller {
+ compatible = "amlogic,a4-pwrc";
+ #power-domain-cells = <1>;
+ };
+ };
};
diff --git a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
index 32a754f..f8fb060 100644
--- a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
+++ b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
@@ -111,8 +111,7 @@
};
gpio_intc: interrupt-controller@4080 {
- compatible = "amlogic,meson-gpio-intc",
- "amlogic,c3-gpio-intc";
+ compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";
reg = <0x0 0x4080 0x0 0x0020>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/dts/upstream/src/arm64/amlogic/meson-a1-ad402.dts b/dts/upstream/src/arm64/amlogic/meson-a1-ad402.dts
index 4bc30af..0d92f52 100644
--- a/dts/upstream/src/arm64/amlogic/meson-a1-ad402.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-a1-ad402.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "meson-a1.dtsi"
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "amlogic,ad402", "amlogic,a1";
@@ -83,6 +84,50 @@
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
+
+ thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ sustainable-power = <130>;
+
+ thermal-sensors = <&cpu_temp>;
+
+ trips {
+ soc_passive: soc-passive {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_hot: soc-hot {
+ temperature = <85000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ soc_critical: soc-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ soc_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&soc_passive>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&soc_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
/* Bluetooth HCI H4 */
diff --git a/dts/upstream/src/arm64/amlogic/meson-a1.dtsi b/dts/upstream/src/arm64/amlogic/meson-a1.dtsi
index c03e207..e5366d4 100644
--- a/dts/upstream/src/arm64/amlogic/meson-a1.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-a1.dtsi
@@ -28,6 +28,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -36,6 +37,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
l2: l2-cache0 {
@@ -398,6 +400,17 @@
power-domains = <&pwrc PWRC_USB_ID>;
};
+ cpu_temp: temperature-sensor@4c00 {
+ compatible = "amlogic,a1-cpu-thermal";
+ reg = <0x0 0x4c00 0x0 0x50>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc_periphs CLKID_TS>;
+ assigned-clocks = <&clkc_periphs CLKID_TS>;
+ assigned-clock-rates = <500000>;
+ #thermal-sensor-cells = <0>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
+
hwrng: rng@5118 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x5118 0x0 0x4>;
@@ -419,7 +432,7 @@
clock-names = "fixpll_in", "hifipll_in";
};
- sd_emmc: sd@10000 {
+ sd_emmc: mmc@10000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x10000 0x0 0x800>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -453,7 +466,6 @@
assigned-clocks = <&clkc_periphs CLKID_USB_BUS>;
assigned-clock-rates = <64000000>;
resets = <&reset RESET_USBCTRL>;
- reset-name = "usb_ctrl";
dr_mode = "otg";
diff --git a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
index 6d12b76..e9b2286 100644
--- a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
@@ -25,10 +25,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_A";
- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
- <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
@@ -36,10 +36,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_B";
- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
- <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
@@ -47,10 +47,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_C";
- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
- <&clkc_audio AUD_CLKID_MST_C_SCLK>,
- <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi
index b058ed7..d08c977 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12-common.dtsi
@@ -215,6 +215,11 @@
#sound-dai-cells = <0>;
status = "disabled";
+ assigned-clocks = <&clkc CLKID_HDMI_SEL>,
+ <&clkc CLKID_HDMI>;
+ assigned-clock-parents = <&xtal>, <0>;
+ assigned-clock-rates = <0>, <24000000>;
+
/* VPU VENC Input */
hdmi_tx_venc_port: port@0 {
reg = <0>;
@@ -987,7 +992,7 @@
mux {
groups = "spdif_out_h";
function = "spdif_out";
- drive-strength-microamp = <500>;
+ drive-strength-microamp = <3000>;
bias-disable;
};
};
@@ -996,7 +1001,7 @@
mux {
groups = "spdif_out_a11";
function = "spdif_out";
- drive-strength-microamp = <500>;
+ drive-strength-microamp = <3000>;
bias-disable;
};
};
@@ -1005,7 +1010,7 @@
mux {
groups = "spdif_out_a13";
function = "spdif_out";
- drive-strength-microamp = <500>;
+ drive-strength-microamp = <3000>;
bias-disable;
};
};
@@ -1741,9 +1746,6 @@
compatible = "amlogic,meson-gx-ao-sysctrl",
"simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
compatible = "amlogic,meson-g12a-aoclkc";
@@ -1752,278 +1754,278 @@
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
+ };
- ao_pinctrl: pinctrl {
- compatible = "amlogic,meson-g12a-aobus-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ ao_pinctrl: pinctrl@14 {
+ compatible = "amlogic,meson-g12a-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
- gpio_ao: bank@14 {
- reg = <0x0 0x14 0x0 0x8>,
- <0x0 0x1c 0x0 0x8>,
- <0x0 0x24 0x0 0x14>;
- reg-names = "mux",
- "ds",
- "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&ao_pinctrl 0 0 15>;
- };
+ gpio_ao: bank@14 {
+ reg = <0x0 0x14 0x0 0x8>,
+ <0x0 0x1c 0x0 0x8>,
+ <0x0 0x24 0x0 0x14>;
+ reg-names = "mux",
+ "ds",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ao_pinctrl 0 0 15>;
+ };
- i2c_ao_sck_pins: i2c_ao_sck_pins {
- mux {
- groups = "i2c_ao_sck";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ i2c_ao_sck_pins: i2c_ao_sck_pins {
+ mux {
+ groups = "i2c_ao_sck";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- i2c_ao_sda_pins: i2c_ao_sda {
- mux {
- groups = "i2c_ao_sda";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ i2c_ao_sda_pins: i2c_ao_sda {
+ mux {
+ groups = "i2c_ao_sda";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- i2c_ao_sck_e_pins: i2c_ao_sck_e {
- mux {
- groups = "i2c_ao_sck_e";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ i2c_ao_sck_e_pins: i2c_ao_sck_e {
+ mux {
+ groups = "i2c_ao_sck_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- i2c_ao_sda_e_pins: i2c_ao_sda_e {
- mux {
- groups = "i2c_ao_sda_e";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ i2c_ao_sda_e_pins: i2c_ao_sda_e {
+ mux {
+ groups = "i2c_ao_sda_e";
+ function = "i2c_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- mclk0_ao_pins: mclk0-ao {
- mux {
- groups = "mclk0_ao";
- function = "mclk0_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ mclk0_ao_pins: mclk0-ao {
+ mux {
+ groups = "mclk0_ao";
+ function = "mclk0_ao";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_din0_pins: tdm-ao-b-din0 {
- mux {
- groups = "tdm_ao_b_din0";
- function = "tdm_ao_b";
- bias-disable;
- };
+ tdm_ao_b_din0_pins: tdm-ao-b-din0 {
+ mux {
+ groups = "tdm_ao_b_din0";
+ function = "tdm_ao_b";
+ bias-disable;
};
+ };
- spdif_ao_out_pins: spdif-ao-out {
- mux {
- groups = "spdif_ao_out";
- function = "spdif_ao_out";
- drive-strength-microamp = <500>;
- bias-disable;
- };
+ spdif_ao_out_pins: spdif-ao-out {
+ mux {
+ groups = "spdif_ao_out";
+ function = "spdif_ao_out";
+ drive-strength-microamp = <3000>;
+ bias-disable;
};
+ };
- tdm_ao_b_din1_pins: tdm-ao-b-din1 {
- mux {
- groups = "tdm_ao_b_din1";
- function = "tdm_ao_b";
- bias-disable;
- };
+ tdm_ao_b_din1_pins: tdm-ao-b-din1 {
+ mux {
+ groups = "tdm_ao_b_din1";
+ function = "tdm_ao_b";
+ bias-disable;
};
+ };
- tdm_ao_b_din2_pins: tdm-ao-b-din2 {
- mux {
- groups = "tdm_ao_b_din2";
- function = "tdm_ao_b";
- bias-disable;
- };
+ tdm_ao_b_din2_pins: tdm-ao-b-din2 {
+ mux {
+ groups = "tdm_ao_b_din2";
+ function = "tdm_ao_b";
+ bias-disable;
};
+ };
- tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
- mux {
- groups = "tdm_ao_b_dout0";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
+ mux {
+ groups = "tdm_ao_b_dout0";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
- mux {
- groups = "tdm_ao_b_dout1";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
+ mux {
+ groups = "tdm_ao_b_dout1";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
- mux {
- groups = "tdm_ao_b_dout2";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
+ mux {
+ groups = "tdm_ao_b_dout2";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_fs_pins: tdm-ao-b-fs {
- mux {
- groups = "tdm_ao_b_fs";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ tdm_ao_b_fs_pins: tdm-ao-b-fs {
+ mux {
+ groups = "tdm_ao_b_fs";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
- mux {
- groups = "tdm_ao_b_sclk";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
+ tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
+ mux {
+ groups = "tdm_ao_b_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
+ drive-strength-microamp = <3000>;
};
+ };
- tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
- mux {
- groups = "tdm_ao_b_slv_fs";
- function = "tdm_ao_b";
- bias-disable;
- };
+ tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
+ mux {
+ groups = "tdm_ao_b_slv_fs";
+ function = "tdm_ao_b";
+ bias-disable;
};
+ };
- tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
- mux {
- groups = "tdm_ao_b_slv_sclk";
- function = "tdm_ao_b";
- bias-disable;
- };
+ tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
+ mux {
+ groups = "tdm_ao_b_slv_sclk";
+ function = "tdm_ao_b";
+ bias-disable;
};
+ };
- uart_ao_a_pins: uart-a-ao {
- mux {
- groups = "uart_ao_a_tx",
- "uart_ao_a_rx";
- function = "uart_ao_a";
- bias-disable;
- };
+ uart_ao_a_pins: uart-a-ao {
+ mux {
+ groups = "uart_ao_a_tx",
+ "uart_ao_a_rx";
+ function = "uart_ao_a";
+ bias-disable;
};
+ };
- uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
- mux {
- groups = "uart_ao_a_cts",
- "uart_ao_a_rts";
- function = "uart_ao_a";
- bias-disable;
- };
+ uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
+ mux {
+ groups = "uart_ao_a_cts",
+ "uart_ao_a_rts";
+ function = "uart_ao_a";
+ bias-disable;
};
+ };
- uart_ao_b_2_3_pins: uart-ao-b-2-3 {
- mux {
- groups = "uart_ao_b_tx_2",
- "uart_ao_b_rx_3";
- function = "uart_ao_b";
- bias-disable;
- };
+ uart_ao_b_2_3_pins: uart-ao-b-2-3 {
+ mux {
+ groups = "uart_ao_b_tx_2",
+ "uart_ao_b_rx_3";
+ function = "uart_ao_b";
+ bias-disable;
};
+ };
- uart_ao_b_8_9_pins: uart-ao-b-8-9 {
- mux {
- groups = "uart_ao_b_tx_8",
- "uart_ao_b_rx_9";
- function = "uart_ao_b";
- bias-disable;
- };
+ uart_ao_b_8_9_pins: uart-ao-b-8-9 {
+ mux {
+ groups = "uart_ao_b_tx_8",
+ "uart_ao_b_rx_9";
+ function = "uart_ao_b";
+ bias-disable;
};
+ };
- uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
- mux {
- groups = "uart_ao_b_cts",
- "uart_ao_b_rts";
- function = "uart_ao_b";
- bias-disable;
- };
+ uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
+ mux {
+ groups = "uart_ao_b_cts",
+ "uart_ao_b_rts";
+ function = "uart_ao_b";
+ bias-disable;
};
+ };
- pwm_a_e_pins: pwm-a-e {
- mux {
- groups = "pwm_a_e";
- function = "pwm_a_e";
- bias-disable;
- };
+ pwm_a_e_pins: pwm-a-e {
+ mux {
+ groups = "pwm_a_e";
+ function = "pwm_a_e";
+ bias-disable;
};
+ };
- pwm_ao_a_pins: pwm-ao-a {
- mux {
- groups = "pwm_ao_a";
- function = "pwm_ao_a";
- bias-disable;
- };
+ pwm_ao_a_pins: pwm-ao-a {
+ mux {
+ groups = "pwm_ao_a";
+ function = "pwm_ao_a";
+ bias-disable;
};
+ };
- pwm_ao_b_pins: pwm-ao-b {
- mux {
- groups = "pwm_ao_b";
- function = "pwm_ao_b";
- bias-disable;
- };
+ pwm_ao_b_pins: pwm-ao-b {
+ mux {
+ groups = "pwm_ao_b";
+ function = "pwm_ao_b";
+ bias-disable;
};
+ };
- pwm_ao_c_4_pins: pwm-ao-c-4 {
- mux {
- groups = "pwm_ao_c_4";
- function = "pwm_ao_c";
- bias-disable;
- };
+ pwm_ao_c_4_pins: pwm-ao-c-4 {
+ mux {
+ groups = "pwm_ao_c_4";
+ function = "pwm_ao_c";
+ bias-disable;
};
+ };
- pwm_ao_c_6_pins: pwm-ao-c-6 {
- mux {
- groups = "pwm_ao_c_6";
- function = "pwm_ao_c";
- bias-disable;
- };
+ pwm_ao_c_6_pins: pwm-ao-c-6 {
+ mux {
+ groups = "pwm_ao_c_6";
+ function = "pwm_ao_c";
+ bias-disable;
};
+ };
- pwm_ao_d_5_pins: pwm-ao-d-5 {
- mux {
- groups = "pwm_ao_d_5";
- function = "pwm_ao_d";
- bias-disable;
- };
+ pwm_ao_d_5_pins: pwm-ao-d-5 {
+ mux {
+ groups = "pwm_ao_d_5";
+ function = "pwm_ao_d";
+ bias-disable;
};
+ };
- pwm_ao_d_10_pins: pwm-ao-d-10 {
- mux {
- groups = "pwm_ao_d_10";
- function = "pwm_ao_d";
- bias-disable;
- };
+ pwm_ao_d_10_pins: pwm-ao-d-10 {
+ mux {
+ groups = "pwm_ao_d_10";
+ function = "pwm_ao_d";
+ bias-disable;
};
+ };
- pwm_ao_d_e_pins: pwm-ao-d-e {
- mux {
- groups = "pwm_ao_d_e";
- function = "pwm_ao_d";
- };
+ pwm_ao_d_e_pins: pwm-ao-d-e {
+ mux {
+ groups = "pwm_ao_d_e";
+ function = "pwm_ao_d";
};
+ };
- remote_input_ao_pins: remote-input-ao {
- mux {
- groups = "remote_ao_input";
- function = "remote_ao_input";
- bias-disable;
- };
+ remote_input_ao_pins: remote-input-ao {
+ mux {
+ groups = "remote_ao_input";
+ function = "remote_ao_input";
+ bias-disable;
};
};
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12.dtsi
index e732df3..664912d 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12.dtsi
@@ -363,6 +363,10 @@
power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};
+&hdmi_tx {
+ power-domains = <&pwrc PWRC_G12A_VPU_ID>;
+};
+
&vpu {
power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12a-u200.dts b/dts/upstream/src/arm64/amlogic/meson-g12a-u200.dts
index 3da7922..0e23993 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12a-u200.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12a-u200.dts
@@ -24,7 +24,6 @@
compatible = "simple-audio-amplifier";
enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
VCC-supply = <&vcc_5v>;
- #sound-dai-cells = <0>;
sound-name-prefix = "10U2";
};
@@ -374,6 +373,7 @@
};
&acodec {
+ AVDD-supply = <&vddao_1v8>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
index 4b8db87..6a346cb 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
@@ -44,13 +44,6 @@
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
- fan0: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- cooling-levels = <0 120 170 220>;
- pwms = <&pwm_cd 1 40000 0>;
- };
-
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
@@ -374,13 +367,6 @@
clock-names = "clkin0";
};
-&pwm_cd {
- status = "okay";
- pinctrl-0 = <&pwm_d_x6_pins>;
- pinctrl-names = "default";
- pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>;
-};
-
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-one.dts b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-one.dts
new file mode 100644
index 0000000..ecfa1c6
--- /dev/null
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-one.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-dreambox.dtsi"
+
+/ {
+ compatible = "dream,dreambox-one", "amlogic,s922x", "amlogic,g12b";
+ model = "Dreambox One";
+};
+
+&sd_emmc_a {
+ sd-uhs-sdr12;
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-two.dts b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-two.dts
new file mode 100644
index 0000000..df0d719
--- /dev/null
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox-two.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-dreambox.dtsi"
+
+/ {
+ compatible = "dream,dreambox-two", "amlogic,s922x", "amlogic,g12b";
+ model = "Dreambox Two";
+};
+
+&sd_emmc_a {
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox.dtsi
new file mode 100644
index 0000000..3a24c24
--- /dev/null
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-dreambox.dtsi
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ cvbs-connector {
+ status = "disabled";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOA_11 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ spdif_dit: audio-codec-1 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "DREAMBOX";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "SPDIFOUT_A IN 0", "FRDDR_A OUT 3",
+ "SPDIFOUT_A IN 1", "FRDDR_B OUT 3",
+ "SPDIFOUT_A IN 2", "FRDDR_C OUT 3";
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* spdif hdmi or toslink interface */
+ dai-link-4 {
+ sound-dai = <&spdifout_a>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+
+ codec-1 {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
+ };
+ };
+
+ /* spdif hdmi interface */
+ dai-link-5 {
+ sound-dai = <&spdifout_b>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-6 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-dreambox";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+&spdifout_a {
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spdifout_b {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi
index d80dd9a..86eb811 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-odroid-n2.dtsi
@@ -31,6 +31,30 @@
enable-active-high;
};
+ /* USB hub supports both USB 2.0 and USB 3.0 root hub */
+ usb-hub {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ vdd-supply = <&usb_pwr_en>;
+ };
+
+ /* 3.0 hub on port 4 */
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+ };
+
sound {
compatible = "amlogic,axg-sound-card";
model = "ODROID-N2";
@@ -234,18 +258,6 @@
"PIN_3", /* GPIOX_17 */
"PIN_5", /* GPIOX_18 */
"PIN_36"; /* GPIOX_19 */
- /*
- * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub-hog {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
};
&i2c3 {
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-radxa-zero2.dts b/dts/upstream/src/arm64/amlogic/meson-g12b-radxa-zero2.dts
index 890f5bf..8445701 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-radxa-zero2.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-radxa-zero2.dts
@@ -33,6 +33,13 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 64 128 192 255>;
+ pwms = <&pwm_AO_ab 0 40000 0>;
+ };
+
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <100>;
@@ -286,6 +293,23 @@
clock-latency = <50000>;
};
+&cpu_thermal {
+ trips {
+ cpu_active: cpu-active {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_active>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&frddr_a {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/dts/upstream/src/arm64/amlogic/meson-gxbb-odroidc2.dts
index c431986..c37cc6b 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-odroidc2.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-odroidc2.dts
@@ -408,6 +408,6 @@
compatible = "usb5e3,610";
reg = <1>;
vdd-supply = <&p5v0>;
- reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxbb.dtsi
index 12ef6e8..ed00e67 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb.dtsi
@@ -311,10 +311,16 @@
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
+ clocks = <&clkc CLKID_HDMI>,
+ <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
+
+ assigned-clocks = <&clkc CLKID_HDMI_SEL>,
+ <&clkc CLKID_HDMI>;
+ assigned-clock-parents = <&xtal>, <0>;
+ assigned-clock-rates = <0>, <24000000>;
};
&sysctrl {
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-vero4k.dts b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-vero4k.dts
new file mode 100644
index 0000000..de996e9
--- /dev/null
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-vero4k.dts
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "osmc,vero4k", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "OSMC Vero 4K";
+
+ reserved-memory {
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-standby {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ dio2133: analog-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "AU2";
+ VCC-supply = <&hdmi_5v>;
+ enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ };
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ sound-name-prefix = "DIT";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "VERO4K";
+ audio-aux-devs = <&dio2133>;
+ audio-widgets = "Line", "Lineout";
+ audio-routing = "AU2 INL", "ACODEC LOLP",
+ "AU2 INR", "ACODEC LORP",
+ "AU2 INL", "ACODEC LOLN",
+ "AU2 INR", "ACODEC LORN",
+ "Lineout", "AU2 OUTL",
+ "Lineout", "AU2 OUTR";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+
+ codec-1 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ dai-link-5 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddio_ao18>;
+ status = "okay";
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&internal_phy {
+ pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxl.dtsi
index 17bcfa4..f58d179 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl.dtsi
@@ -323,10 +323,16 @@
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_HDMI_TX>;
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
+ clocks = <&clkc CLKID_HDMI>,
+ <&clkc CLKID_HDMI_PCLK>,
<&clkc CLKID_GCLK_VENCI_INT0>;
clock-names = "isfr", "iahb", "venci";
+ power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
+
+ assigned-clocks = <&clkc CLKID_HDMI_SEL>,
+ <&clkc CLKID_HDMI>;
+ assigned-clock-parents = <&xtal>, <0>;
+ assigned-clock-rates = <0>, <24000000>;
};
&sysctrl {
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxlx-s905l-p271.dts b/dts/upstream/src/arm64/amlogic/meson-gxlx-s905l-p271.dts
new file mode 100644
index 0000000..1221f45
--- /dev/null
+++ b/dts/upstream/src/arm64/amlogic/meson-gxlx-s905l-p271.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+
+/ {
+ compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxlx";
+ model = "Amlogic Meson GXLX (S905L) P271 Development Board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ sound {
+ model = "P271";
+ };
+};
+
+&apb {
+ mali: gpu@c0000 {
+ /* Mali 450-MP2 */
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1";
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc";
+};
+
+&usb {
+ dr_mode = "host";
+};
+
+&vdec {
+ compatible = "amlogic,gxlx-vdec", "amlogic,gx-vdec";
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-s4.dtsi b/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
index 10896f9..b686eac 100644
--- a/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
@@ -312,6 +312,160 @@
};
};
+ pwm_a_pins1: pwm-a-pins1 {
+ mux {
+ groups = "pwm_a_d";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins2: pwm-a-pins2 {
+ mux {
+ groups = "pwm_a_x";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm-b-pins1 {
+ mux {
+ groups = "pwm_b_d";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins2: pwm-b-pins2 {
+ mux {
+ groups = "pwm_b_x";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm-c-pins1 {
+ mux {
+ groups = "pwm_c_d";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins2: pwm-c-pins2 {
+ mux {
+ groups = "pwm_c_x";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm-d-pins1 {
+ mux {
+ groups = "pwm_d_d";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins2: pwm-d-pins2 {
+ mux {
+ groups = "pwm_d_h";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins1: pwm-e-pins1 {
+ mux {
+ groups = "pwm_e_x";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins2: pwm-e-pins2 {
+ mux {
+ groups = "pwm_e_z";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm-f-pins1 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm-f-pins2 {
+ mux {
+ groups = "pwm_f_z";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_g_pins1: pwm-g-pins1 {
+ mux {
+ groups = "pwm_g_d";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins2: pwm-g-pins2 {
+ mux {
+ groups = "pwm_g_z";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_h_pins: pwm-h-pins {
+ mux {
+ groups = "pwm_h";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_i_pins1: pwm-i-pins1 {
+ mux {
+ groups = "pwm_i_d";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins2: pwm-i-pins2 {
+ mux {
+ groups = "pwm_i_h";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_j_pins: pwm-j-pins {
+ mux {
+ groups = "pwm_j";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_a_hiz_pins: pwm-a-hiz-pins {
+ mux {
+ groups = "pwm_a_hiz";
+ function = "pwm_a_hiz";
+ };
+ };
+
+ pwm_b_hiz_pins: pwm-b-hiz-pins {
+ mux {
+ groups = "pwm_b_hiz";
+ function = "pwm_b_hiz";
+ };
+ };
+
+ pwm_c_hiz_pins: pwm-c-hiz-pins {
+ mux {
+ groups = "pwm_c_hiz";
+ function = "pwm_c_hiz";
+ };
+ };
+
+ pwm_g_hiz_pins: pwm-g-hiz-pins {
+ mux {
+ groups = "pwm_g_hiz";
+ function = "pwm_g_hiz";
+ };
+ };
+
spicc0_pins_x: spicc0-pins_x {
mux {
groups = "spi_a_mosi_x",
@@ -399,6 +553,51 @@
status = "disabled";
};
+ pwm_ab: pwm@58000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x0 0x58000 0x0 0x24>;
+ clocks = <&clkc_periphs CLKID_PWM_A>,
+ <&clkc_periphs CLKID_PWM_B>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@5a000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x0 0x5a000 0x0 0x24>;
+ clocks = <&clkc_periphs CLKID_PWM_C>,
+ <&clkc_periphs CLKID_PWM_D>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@5c000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x0 0x5c000 0x0 0x24>;
+ clocks = <&clkc_periphs CLKID_PWM_E>,
+ <&clkc_periphs CLKID_PWM_F>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_gh: pwm@5e000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x0 0x5e000 0x0 0x24>;
+ clocks = <&clkc_periphs CLKID_PWM_G>,
+ <&clkc_periphs CLKID_PWM_H>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ij: pwm@60000 {
+ compatible = "amlogic,meson-s4-pwm";
+ reg = <0x0 0x60000 0x0 0x24>;
+ clocks = <&clkc_periphs CLKID_PWM_I>,
+ <&clkc_periphs CLKID_PWM_J>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
i2c0: i2c@66000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x66000 0x0 0x20>;
diff --git a/dts/upstream/src/arm64/amlogic/meson-sm1.dtsi b/dts/upstream/src/arm64/amlogic/meson-sm1.dtsi
index 643f94d..97e4b52 100644
--- a/dts/upstream/src/arm64/amlogic/meson-sm1.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-sm1.dtsi
@@ -17,10 +17,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_A";
- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
- <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_A_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
@@ -28,10 +28,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_B";
- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
- <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_B_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
@@ -39,10 +39,10 @@
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_C";
- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
- <&clkc_audio AUD_CLKID_MST_C_SCLK>,
- <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
+ clocks = <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_LRCLK>,
+ <&clkc_audio AUD_CLKID_MST_C_MCLK>;
+ clock-names = "sclk", "lrclk", "mclk";
status = "disabled";
};
@@ -275,8 +275,7 @@
};
tdmin_a: audio-controller@300 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
+ compatible = "amlogic,sm1-tdmin";
reg = <0x0 0x300 0x0 0x40>;
sound-name-prefix = "TDMIN_A";
resets = <&clkc_audio AUD_RESET_TDMIN_A>;
@@ -291,8 +290,7 @@
};
tdmin_b: audio-controller@340 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
+ compatible = "amlogic,sm1-tdmin";
reg = <0x0 0x340 0x0 0x40>;
sound-name-prefix = "TDMIN_B";
resets = <&clkc_audio AUD_RESET_TDMIN_B>;
@@ -307,8 +305,7 @@
};
tdmin_c: audio-controller@380 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
+ compatible = "amlogic,sm1-tdmin";
reg = <0x0 0x380 0x0 0x40>;
sound-name-prefix = "TDMIN_C";
resets = <&clkc_audio AUD_RESET_TDMIN_C>;
@@ -323,8 +320,7 @@
};
tdmin_lb: audio-controller@3c0 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
+ compatible = "amlogic,sm1-tdmin";
reg = <0x0 0x3c0 0x0 0x40>;
sound-name-prefix = "TDMIN_LB";
resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
@@ -339,7 +335,7 @@
};
spdifin: audio-controller@400 {
- compatible = "amlogic,g12a-spdifin",
+ compatible = "amlogic,sm1-spdifin",
"amlogic,axg-spdifin";
reg = <0x0 0x400 0x0 0x30>;
#sound-dai-cells = <0>;
@@ -353,7 +349,7 @@
};
spdifout_a: audio-controller@480 {
- compatible = "amlogic,g12a-spdifout",
+ compatible = "amlogic,sm1-spdifout",
"amlogic,axg-spdifout";
reg = <0x0 0x480 0x0 0x50>;
#sound-dai-cells = <0>;
@@ -518,6 +514,10 @@
"amlogic,meson-gpio-intc";
};
+&hdmi_tx {
+ power-domains = <&pwrc PWRC_SM1_VPU_ID>;
+};
+
&pcie {
power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
};
diff --git a/dts/upstream/src/arm64/apm/apm-merlin.dts b/dts/upstream/src/arm64/apm/apm-merlin.dts
index 6e05cf1a..b116078 100644
--- a/dts/upstream/src/arm64/apm/apm-merlin.dts
+++ b/dts/upstream/src/arm64/apm/apm-merlin.dts
@@ -32,7 +32,7 @@
};
poweroff_mbox: poweroff_mbox@10548000 {
- compatible = "syscon";
+ compatible = "apm,merlin-poweroff-mailbox", "syscon";
reg = <0x0 0x10548000 0x0 0x30>;
};
diff --git a/dts/upstream/src/arm64/apm/apm-mustang.dts b/dts/upstream/src/arm64/apm/apm-mustang.dts
index e7644cd..2ef6587 100644
--- a/dts/upstream/src/arm64/apm/apm-mustang.dts
+++ b/dts/upstream/src/arm64/apm/apm-mustang.dts
@@ -32,7 +32,7 @@
};
poweroff_mbox: poweroff_mbox@10548000 {
- compatible = "syscon";
+ compatible = "apm,mustang-poweroff-mailbox", "syscon";
reg = <0x0 0x10548000 0x0 0x30>;
};
diff --git a/dts/upstream/src/arm64/arm/corstone1000-fvp.dts b/dts/upstream/src/arm64/arm/corstone1000-fvp.dts
index 901a7fc..abd0135 100644
--- a/dts/upstream/src/arm64/arm/corstone1000-fvp.dts
+++ b/dts/upstream/src/arm64/arm/corstone1000-fvp.dts
@@ -21,7 +21,7 @@
reg-io-width = <2>;
};
- vmmc_v3_3d: fixed_v3_3d {
+ vmmc_v3_3d: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc_supply";
regulator-min-microvolt = <3300000>;
diff --git a/dts/upstream/src/arm64/arm/corstone1000.dtsi b/dts/upstream/src/arm64/arm/corstone1000.dtsi
index 6ad7829..bb9b96f 100644
--- a/dts/upstream/src/arm64/arm/corstone1000.dtsi
+++ b/dts/upstream/src/arm64/arm/corstone1000.dtsi
@@ -60,14 +60,14 @@
cache-sets = <1024>;
};
- refclk100mhz: refclk100mhz {
+ refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
- smbclk: refclk24mhzx2 {
+ smbclk: clock-48000000 {
/* Reference 24MHz clock x 2 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -83,7 +83,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
- uartclk: uartclk {
+ uartclk: clock-50000000 {
/* UART clock - 50MHz */
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/dts/upstream/src/arm64/arm/foundation-v8.dtsi b/dts/upstream/src/arm64/arm/foundation-v8.dtsi
index 7b41537..93f1e7c 100644
--- a/dts/upstream/src/arm64/arm/foundation-v8.dtsi
+++ b/dts/upstream/src/arm64/arm/foundation-v8.dtsi
@@ -99,21 +99,21 @@
timeout-sec = <30>;
};
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
diff --git a/dts/upstream/src/arm64/arm/fvp-base-revc.dts b/dts/upstream/src/arm64/arm/fvp-base-revc.dts
index 60472d6..85f1c15 100644
--- a/dts/upstream/src/arm64/arm/fvp-base-revc.dts
+++ b/dts/upstream/src/arm64/arm/fvp-base-revc.dts
@@ -243,6 +243,7 @@
iommu-map = <0x0 &smmu 0x0 0x10000>;
dma-coherent;
+ ats-supported;
};
smmu: iommu@2b400000 {
diff --git a/dts/upstream/src/arm64/arm/juno-base.dtsi b/dts/upstream/src/arm64/arm/juno-base.dtsi
index 98ed2b3..055764d 100644
--- a/dts/upstream/src/arm64/arm/juno-base.dtsi
+++ b/dts/upstream/src/arm64/arm/juno-base.dtsi
@@ -663,7 +663,6 @@
dma-coherent;
/* The SMMU is only really of interest to bare-metal hypervisors */
/* iommus = <&smmu_gpu 0>; */
- status = "disabled";
};
sram: sram@2e000000 {
diff --git a/dts/upstream/src/arm64/arm/juno-clocks.dtsi b/dts/upstream/src/arm64/arm/juno-clocks.dtsi
index 2870b5e..6d7d88e 100644
--- a/dts/upstream/src/arm64/arm/juno-clocks.dtsi
+++ b/dts/upstream/src/arm64/arm/juno-clocks.dtsi
@@ -8,35 +8,35 @@
*/
/ {
/* SoC fixed clocks */
- soc_uartclk: refclk7372800hz {
+ soc_uartclk: clock-7372800 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7372800>;
clock-output-names = "juno:uartclk";
};
- soc_usb48mhz: clk48mhz {
+ soc_usb48mhz: clock-48000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "clk48mhz";
};
- soc_smc50mhz: clk50mhz {
+ soc_smc50mhz: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "smc_clk";
};
- soc_refclk100mhz: refclk100mhz {
+ soc_refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
- soc_faxiclk: refclk400mhz {
+ soc_faxiclk: clock-400000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
diff --git a/dts/upstream/src/arm64/arm/juno-motherboard.dtsi b/dts/upstream/src/arm64/arm/juno-motherboard.dtsi
index be42932..ffa4ba4 100644
--- a/dts/upstream/src/arm64/arm/juno-motherboard.dtsi
+++ b/dts/upstream/src/arm64/arm/juno-motherboard.dtsi
@@ -8,35 +8,35 @@
*/
/ {
- mb_clk24mhz: clk24mhz {
+ mb_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "juno_mb:clk24mhz";
};
- mb_clk25mhz: clk25mhz {
+ mb_clk25mhz: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "juno_mb:clk25mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "juno_mb:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "juno_mb:refclk32khz";
};
- mb_fixed_3v3: mcc-sb-3v3 {
+ mb_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "MCC_SB_3V3";
regulator-min-microvolt = <3300000>;
@@ -158,7 +158,8 @@
};
apbregs@10000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "arm,juno-fpga-apb-regs",
+ "syscon", "simple-mfd";
reg = <0x010000 0x1000>;
ranges = <0x0 0x10000 0x1000>;
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/arm/rtsm_ve-motherboard.dtsi b/dts/upstream/src/arm64/arm/rtsm_ve-motherboard.dtsi
index ba8beef..66b1b74 100644
--- a/dts/upstream/src/arm64/arm/rtsm_ve-motherboard.dtsi
+++ b/dts/upstream/src/arm64/arm/rtsm_ve-motherboard.dtsi
@@ -8,28 +8,28 @@
* VEMotherBoard.lisa
*/
/ {
- v2m_clk24mhz: clk24mhz {
+ v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
- v2m_refclk1mhz: refclk1mhz {
+ v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
- v2m_refclk32khz: refclk32khz {
+ v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
- v2m_fixed_3v3: v2m-3v3 {
+ v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@@ -41,7 +41,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- v2m_oscclk1: oscclk1 {
+ v2m_oscclk1: clock-controller {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
diff --git a/dts/upstream/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts b/dts/upstream/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
index 9115c99..a0e1fa8 100644
--- a/dts/upstream/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/dts/upstream/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -111,7 +111,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
- smbclk: smclk {
+ smbclk: clock-controller {
/* SMC clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@@ -120,7 +120,7 @@
clock-output-names = "smclk";
};
- volt-vio {
+ regulator-vio {
/* VIO to expansion board above */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@@ -130,7 +130,7 @@
regulator-always-on;
};
- volt-12v {
+ regulator-12v {
/* 12V from power connector J6 */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
diff --git a/dts/upstream/src/arm64/exynos/exynos850.dtsi b/dts/upstream/src/arm64/exynos/exynos850.dtsi
index 0706c85..f1c8b46 100644
--- a/dts/upstream/src/arm64/exynos/exynos850.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos850.dtsi
@@ -416,6 +416,14 @@
interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
};
+ trng: rng@12081400 {
+ compatible = "samsung,exynos850-trng";
+ reg = <0x12081400 0x100>;
+ clocks = <&cmu_core CLK_GOUT_SSS_ACLK>,
+ <&cmu_core CLK_GOUT_SSS_PCLK>;
+ clock-names = "secss", "pclk";
+ };
+
pinctrl_hsi: pinctrl@13430000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x13430000 0x1000>;
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
index 5e8ffe0..387fb77 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
+++ b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
@@ -131,9 +131,9 @@
};
&usbdrd31 {
- status = "okay";
vdd10-supply = <®_placeholder>;
vdd33-supply = <®_placeholder>;
+ status = "okay";
};
&usbdrd31_dwc3 {
@@ -145,6 +145,13 @@
};
&usbdrd31_phy {
+ /* TODO: Update these once PMIC is implemented */
+ pll-supply = <®_placeholder>;
+ dvdd-usb20-supply = <®_placeholder>;
+ vddh-usb20-supply = <®_placeholder>;
+ vdd33-usb20-supply = <®_placeholder>;
+ vdda-usbdp-supply = <®_placeholder>;
+ vddh-usbdp-supply = <®_placeholder>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/exynos/google/gs101.dtsi b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
index a66e996..eadb882 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101.dtsi
+++ b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
@@ -213,9 +213,9 @@
pmu-3 {
compatible = "arm,dsu-pmu";
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
};
psci {
@@ -288,6 +288,8 @@
compatible = "google,gs101-mct",
"samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
+ clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -300,17 +302,15 @@
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
- clock-names = "fin_pll", "mct";
};
watchdog_cl0: watchdog@10060000 {
compatible = "google,gs101-wdt";
reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>,
<&ext_24_5m>;
clock-names = "watchdog", "watchdog_src";
+ interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <0>;
status = "disabled";
@@ -319,10 +319,10 @@
watchdog_cl1: watchdog@10070000 {
compatible = "google,gs101-wdt";
reg = <0x10070000 0x100>;
- interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>,
<&ext_24_5m>;
clock-names = "watchdog", "watchdog_src";
+ interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,cluster-index = <1>;
status = "disabled";
@@ -776,12 +776,12 @@
compatible = "google,gs101-hsi2c",
"samsung,exynosautov9-hsi2c";
reg = <0x10970000 0xc0>;
- interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>,
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>;
clock-names = "hsi2c", "hsi2c_pclk";
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-0 = <&hsi2c8_bus>;
pinctrl-names = "default";
status = "disabled";
@@ -831,10 +831,10 @@
serial_0: serial@10a00000 {
compatible = "google,gs101-uart";
reg = <0x10a00000 0xc0>;
- interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>,
<&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
clock-names = "uart", "clk_uart_baud0";
+ interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-0 = <&uart0_bus>;
pinctrl-names = "default";
samsung,uart-fifosize = <256>;
@@ -1157,12 +1157,12 @@
compatible = "google,gs101-hsi2c",
"samsung,exynosautov9-hsi2c";
reg = <0x10d50000 0xc0>;
- interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>,
<&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>;
clock-names = "hsi2c", "hsi2c_pclk";
+ interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-0 = <&hsi2c12_bus>;
pinctrl-names = "default";
status = "disabled";
@@ -1277,13 +1277,14 @@
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>,
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>;
clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk";
- samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
status = "disabled";
};
usbdrd31: usb@11110000 {
compatible = "google,gs101-dwusb3";
+ ranges = <0x0 0x11110000 0x10000>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>,
<&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>,
<&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>,
@@ -1291,14 +1292,13 @@
clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x11110000 0x10000>;
status = "disabled";
usbdrd31_dwc3: usb@0 {
compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>;
clock-names = "ref";
- reg = <0x0 0x10000>;
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
index a0f7bbd..e61ea7e 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -74,15 +74,15 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
- <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
- <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
- <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@1400000 {
@@ -93,7 +93,7 @@
<0x0 0x1402000 0 0x2000>, /* GICC */
<0x0 0x1404000 0 0x2000>, /* GICH */
<0x0 0x1406000 0 0x2000>; /* GICV */
- interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
reboot {
@@ -156,10 +156,10 @@
status = "disabled";
};
- esdhc0: esdhc@1560000 {
+ esdhc0: mmc@1560000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
- interrupts = <0 62 0x4>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
@@ -175,10 +175,10 @@
big-endian;
};
- esdhc1: esdhc@1580000 {
+ esdhc1: mmc@1580000 {
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
reg = <0x0 0x1580000 0x0 0x10000>;
- interrupts = <0 65 0x4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
voltage-ranges = <1800 1800 3300 3300>;
@@ -305,7 +305,7 @@
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
- interrupts = <0 33 0x4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
fsl,tmu-calibration =
<0x00000000 0x00000025>,
@@ -355,7 +355,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
- interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 2 0>;
@@ -367,7 +367,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
- interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
scl-gpios = <&gpio0 13 0>;
@@ -379,7 +379,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
@@ -391,7 +391,7 @@
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
@@ -400,16 +400,16 @@
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
- interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
status = "disabled";
};
gpio0: gpio@2300000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -417,9 +417,9 @@
};
gpio1: gpio@2310000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -430,7 +430,7 @@
compatible = "fsl,ls1012a-wdt",
"fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
- interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
big-endian;
};
@@ -439,7 +439,7 @@
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b50000 0x0 0x10000>;
- interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -449,9 +449,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 47>,
- <&edma0 1 46>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 46>,
+ <&edma0 1 47>;
status = "disabled";
};
@@ -459,7 +459,7 @@
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
reg = <0x0 0x2b60000 0x0 0x10000>;
- interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -469,9 +469,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 45>,
- <&edma0 1 44>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 44>,
+ <&edma0 1 45>;
status = "disabled";
};
@@ -481,8 +481,8 @@
reg = <0x0 0x2c00000 0x0 0x10000>,
<0x0 0x2c10000 0x0 0x10000>,
<0x0 0x2c20000 0x0 0x10000>;
- interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
- <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
big-endian;
@@ -496,12 +496,11 @@
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <0 60 0x4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- snps,host-vbus-glitches;
};
sata: sata@3200000 {
@@ -509,7 +508,7 @@
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
dma-coherent;
@@ -519,7 +518,7 @@
usb1: usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
- interrupts = <0 139 0x4>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
phy_type = "ulpi";
};
@@ -528,7 +527,7 @@
compatible = "fsl,ls1012a-msi";
reg = <0x0 0x1572000 0x0 0x8>;
msi-controller;
- interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
};
pcie1: pcie@3400000 {
@@ -536,9 +535,9 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 118 0x4>, /* controller interrupt */
- <0 117 0x4>; /* PME interrupt */
- interrupt-names = "aer", "pme";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -563,7 +562,7 @@
#fsl,rcpm-wakeup-cells = <1>;
};
- ftm_alarm0: timer@29d0000 {
+ ftm_alarm0: rtc@29d0000 {
compatible = "fsl,ls1012a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1028a-rdb.dts b/dts/upstream/src/arm64/freescale/fsl-ls1028a-rdb.dts
index ecd2c1e..757a34b 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1028a-rdb.dts
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1028a-rdb.dts
@@ -201,6 +201,37 @@
#address-cells = <1>;
#size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ /* Atmel AT24C512C-XHDB: 64 KB EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ /* AT24C04C 512-byte DDR4 SPD EEPROM */
+ /* Documentation says 0x51, but must be even and i2cdetect says 0x52 */
+ eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ /* Atmel AT24C02C-XHMB: 256-byte EEPROM */
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
index 70b8731..acf2933 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
@@ -155,7 +155,7 @@
};
thermal-zones {
- ddr-controller {
+ ddr-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
@@ -175,7 +175,7 @@
};
};
- core-cluster {
+ cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -674,7 +674,7 @@
};
pcie_ep1: pcie-ep@3400000 {
- compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ compatible = "fsl,ls1028a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -713,7 +713,7 @@
};
pcie_ep2: pcie-ep@3500000 {
- compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ compatible = "fsl,ls1028a-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x88 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
@@ -828,6 +828,7 @@
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error", "qdma-queue0",
"qdma-queue1", "qdma-queue2", "qdma-queue3";
+ #dma-cells = <1>;
dma-channels = <8>;
block-number = <1>;
block-offset = <0x10000>;
@@ -859,8 +860,8 @@
malidp0: display@f080000 {
compatible = "arm,mali-dp500";
reg = <0x0 0xf080000 0x0 0x10000>;
- interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
- <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
@@ -902,9 +903,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 4>,
- <&edma0 1 3>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 3>,
+ <&edma0 1 4>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -923,9 +924,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 6>,
- <&edma0 1 5>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 5>,
+ <&edma0 1 6>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -944,9 +945,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 8>,
- <&edma0 1 7>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 7>,
+ <&edma0 1 8>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -965,9 +966,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 10>,
- <&edma0 1 9>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 9>,
+ <&edma0 1 10>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -986,9 +987,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 12>,
- <&edma0 1 11>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 11>,
+ <&edma0 1 12>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -1007,9 +1008,9 @@
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dma-names = "tx", "rx";
- dmas = <&edma0 1 14>,
- <&edma0 1 13>;
+ dma-names = "rx", "tx";
+ dmas = <&edma0 1 13>,
+ <&edma0 1 14>;
fsl,sai-asynchronous;
status = "disabled";
};
@@ -1024,7 +1025,7 @@
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
- interrupts = <0 23 0x4>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
fsl,tmu-calibration =
<0x00000000 0x00000024>,
@@ -1325,7 +1326,7 @@
little-endian;
};
- ftm_alarm0: timer@2800000 {
+ ftm_alarm0: rtc@2800000 {
compatible = "fsl,ls1028a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
@@ -1333,7 +1334,7 @@
status = "disabled";
};
- ftm_alarm1: timer@2810000 {
+ ftm_alarm1: rtc@2810000 {
compatible = "fsl,ls1028a-ftm-alarm";
reg = <0x0 0x2810000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1043a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-ls1043a-qds.dts
index dda27ed..11b1356 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1043a-qds.dts
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1043a-qds.dts
@@ -64,7 +64,7 @@
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
- nor@0,0 {
+ flash@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1043a-rdb.dts b/dts/upstream/src/arm64/freescale/fsl-ls1043a-rdb.dts
index 26f8540..c4532c8 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1043a-rdb.dts
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1043a-rdb.dts
@@ -71,7 +71,7 @@
0x1 0x0 0x0 0x7e800000 0x00010000
0x2 0x0 0x0 0x7fb00000 0x00000100>;
- nor@0,0 {
+ flash@0,0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
@@ -104,6 +104,12 @@
compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
+ /*
+ * Standard CS timing properties replace the deprecated vendor
+ * variants below.
+ */
+ spi-cs-setup-delay-ns = <100>;
+ spi-cs-hold-delay-ns = <100>;
fsl,spi-cs-sck-delay = <100>;
fsl,spi-sck-cs-delay = <100>;
};
@@ -112,6 +118,12 @@
compatible = "maxim,ds26522";
reg = <2>;
spi-max-frequency = <2000000>;
+ /*
+ * Standard CS timing properties replace the deprecated vendor
+ * variants below.
+ */
+ spi-cs-setup-delay-ns = <100>;
+ spi-cs-hold-delay-ns = <50>;
fsl,spi-cs-sck-delay = <100>;
fsl,spi-sck-cs-delay = <50>;
};
@@ -120,6 +132,12 @@
compatible = "maxim,ds26522";
reg = <3>;
spi-max-frequency = <2000000>;
+ /*
+ * Standard CS timing properties replace the deprecated vendor
+ * variants below.
+ */
+ spi-cs-setup-delay-ns = <100>;
+ spi-cs-hold-delay-ns = <50>;
fsl,spi-cs-sck-delay = <100>;
fsl,spi-sck-cs-delay = <50>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
index 8ee6d8c..ab4c919 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -154,7 +154,7 @@
};
thermal-zones {
- ddr-controller {
+ ddr-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
@@ -174,7 +174,7 @@
};
};
- serdes {
+ serdes-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -194,7 +194,7 @@
};
};
- fman {
+ fman-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
@@ -214,7 +214,7 @@
};
};
- core-cluster {
+ cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
@@ -245,7 +245,7 @@
};
};
- sec {
+ sec-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
@@ -268,19 +268,19 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xf08>, /* Physical Secure PPI */
- <1 14 0xf08>, /* Physical Non-Secure PPI */
- <1 11 0xf08>, /* Virtual PPI */
- <1 10 0xf08>; /* Hypervisor PPI */
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
fsl,erratum-a008585;
};
pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <0 106 0x4>,
- <0 107 0x4>,
- <0 95 0x4>,
- <0 97 0x4>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
@@ -295,7 +295,7 @@
<0x0 0x1402000 0 0x2000>, /* GICC */
<0x0 0x1404000 0 0x2000>, /* GICH */
<0x0 0x1406000 0 0x2000>; /* GICV */
- interrupts = <1 9 0xf08>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc: soc {
@@ -352,7 +352,7 @@
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
- interrupts = <0 75 0x4>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
@@ -360,7 +360,7 @@
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
- interrupts = <0 71 0x4>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
@@ -368,7 +368,7 @@
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
- interrupts = <0 72 0x4>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
@@ -376,7 +376,7 @@
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
- interrupts = <0 73 0x4>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
@@ -384,7 +384,7 @@
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
- interrupts = <0 74 0x4>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -405,7 +405,7 @@
ifc: memory-controller@1530000 {
compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
- interrupts = <0 43 0x4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
qspi: spi@1550000 {
@@ -415,7 +415,7 @@
reg = <0x0 0x1550000 0x0 0x10000>,
<0x0 0x40000000 0x0 0x4000000>;
reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <0 99 0x4>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>,
@@ -424,10 +424,10 @@
status = "disabled";
};
- esdhc: esdhc@1560000 {
+ esdhc: mmc@1560000 {
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
- interrupts = <0 62 0x4>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
@@ -438,14 +438,14 @@
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
- interrupts = <0 144 0x4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
};
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
- interrupts = <0 33 0x4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
<0x00000000 0x00000023>,
@@ -505,11 +505,11 @@
memory-region = <&bman_fbpr>;
};
- bportals: bman-portals@508000000 {
+ bportals: bman-portals-bus@508000000 {
ranges = <0x0 0x5 0x08000000 0x8000000>;
};
- qportals: qman-portals@500000000 {
+ qportals: qman-portals-bus@500000000 {
ranges = <0x0 0x5 0x00000000 0x8000000>;
};
@@ -518,7 +518,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <0 64 0x4>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
@@ -532,8 +532,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
- interrupts = <0 56 0x4>;
- clock-names = "i2c";
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
dmas = <&edma0 1 38>,
@@ -547,8 +547,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
- interrupts = <0 57 0x4>;
- clock-names = "i2c";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -560,8 +560,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
- interrupts = <0 58 0x4>;
- clock-names = "i2c";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -573,8 +573,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
- interrupts = <0 59 0x4>;
- clock-names = "i2c";
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -584,7 +584,7 @@
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
- interrupts = <0 54 0x4>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
};
@@ -592,7 +592,7 @@
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
- interrupts = <0 54 0x4>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
};
@@ -600,7 +600,7 @@
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
- interrupts = <0 55 0x4>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
};
@@ -608,7 +608,7 @@
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
- interrupts = <0 55 0x4>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
};
@@ -616,7 +616,7 @@
gpio1: gpio@2300000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <0 66 0x4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -626,7 +626,7 @@
gpio2: gpio@2310000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <0 67 0x4>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -636,7 +636,7 @@
gpio3: gpio@2320000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
- interrupts = <0 68 0x4>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -646,7 +646,7 @@
gpio4: gpio@2330000 {
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
- interrupts = <0 134 0x4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -721,7 +721,7 @@
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
- interrupts = <0 48 0x4>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg";
status = "disabled";
@@ -730,7 +730,7 @@
lpuart1: serial@2960000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2960000 0x0 0x1000>;
- interrupts = <0 49 0x4>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
clock-names = "ipg";
@@ -740,7 +740,7 @@
lpuart2: serial@2970000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2970000 0x0 0x1000>;
- interrupts = <0 50 0x4>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
clock-names = "ipg";
@@ -750,7 +750,7 @@
lpuart3: serial@2980000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2980000 0x0 0x1000>;
- interrupts = <0 51 0x4>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
clock-names = "ipg";
@@ -760,7 +760,7 @@
lpuart4: serial@2990000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2990000 0x0 0x1000>;
- interrupts = <0 52 0x4>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
clock-names = "ipg";
@@ -770,7 +770,7 @@
lpuart5: serial@29a0000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x29a0000 0x0 0x1000>;
- interrupts = <0 53 0x4>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
clock-names = "ipg";
@@ -780,10 +780,9 @@
wdog0: watchdog@2ad0000 {
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
reg = <0x0 0x2ad0000 0x0 0x10000>;
- interrupts = <0 83 0x4>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
- clock-names = "wdog";
big-endian;
};
@@ -793,8 +792,8 @@
reg = <0x0 0x2c00000 0x0 0x10000>,
<0x0 0x2c10000 0x0 0x10000>,
<0x0 0x2c20000 0x0 0x10000>;
- interrupts = <0 103 0x4>,
- <0 103 0x4>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
big-endian;
@@ -805,7 +804,7 @@
QORIQ_CLK_PLL_DIV(1)>;
};
- aux_bus: aux_bus {
+ aux_bus: aux-bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
@@ -815,7 +814,7 @@
usb0: usb@2f00000 {
compatible = "snps,dwc3";
reg = <0x0 0x2f00000 0x0 0x10000>;
- interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -827,7 +826,7 @@
usb1: usb@3000000 {
compatible = "snps,dwc3";
reg = <0x0 0x3000000 0x0 0x10000>;
- interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -839,7 +838,7 @@
usb2: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -853,7 +852,7 @@
reg = <0x0 0x3200000 0x0 0x10000>,
<0x0 0x20140520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(1)>;
dma-coherent;
@@ -864,21 +863,21 @@
compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>;
msi-controller;
- interrupts = <0 116 0x4>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
};
msi2: msi-controller2@1572000 {
compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1572000 0x0 0x8>;
msi-controller;
- interrupts = <0 126 0x4>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
};
msi3: msi-controller3@1573000 {
compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1573000 0x0 0x8>;
msi-controller;
- interrupts = <0 160 0x4>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
};
pcie1: pcie@3400000 {
@@ -886,8 +885,8 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
- <0 118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -913,8 +912,8 @@
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
- <0 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -940,8 +939,8 @@
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
- <0 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -974,6 +973,7 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error", "qdma-queue0",
"qdma-queue1", "qdma-queue2", "qdma-queue3";
+ #dma-cells = <1>;
dma-channels = <8>;
block-number = <1>;
block-offset = <0x10000>;
@@ -989,7 +989,7 @@
#fsl,rcpm-wakeup-cells = <1>;
};
- ftm_alarm0: timer@29d0000 {
+ ftm_alarm0: rtc@29d0000 {
compatible = "fsl,ls1043a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts
index 3b0ed93..e5296e5 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts
@@ -151,7 +151,7 @@
0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
- nor@0,0 {
+ flash@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
index 754a64b..5501986 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -122,7 +122,7 @@
};
thermal-zones {
- ddr-controller {
+ ddr-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
@@ -142,7 +142,7 @@
};
};
- serdes {
+ serdes-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -162,7 +162,7 @@
};
};
- fman {
+ fman-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
@@ -182,7 +182,7 @@
};
};
- core-cluster {
+ cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
@@ -213,7 +213,7 @@
};
};
- sec {
+ sec-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
@@ -308,7 +308,7 @@
status = "disabled";
};
- esdhc: esdhc@1560000 {
+ esdhc: mmc@1560000 {
compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -409,11 +409,11 @@
};
- qportals: qman-portals@500000000 {
+ qportals: qman-portals-bus@500000000 {
ranges = <0x0 0x5 0x00000000 0x8000000>;
};
- bportals: bman-portals@508000000 {
+ bportals: bman-portals-bus@508000000 {
ranges = <0x0 0x5 0x08000000 0x8000000>;
};
@@ -441,7 +441,7 @@
tmu: tmu@1f00000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f00000 0x0 0x10000>;
- interrupts = <0 33 0x4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
@@ -589,7 +589,7 @@
};
gpio0: gpio@2300000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -599,7 +599,7 @@
};
gpio1: gpio@2310000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -609,7 +609,7 @@
};
gpio2: gpio@2320000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -619,7 +619,7 @@
};
gpio3: gpio@2330000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -715,7 +715,7 @@
QORIQ_CLK_PLL_DIV(2)>;
};
- aux_bus: aux_bus {
+ aux_bus: aux-bus {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
@@ -801,9 +801,9 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
- interrupt-names = "aer", "pme";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -840,9 +840,9 @@
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
- interrupt-names = "aer", "pme";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -879,9 +879,9 @@
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
- interrupt-names = "aer", "pme";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -925,6 +925,7 @@
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qdma-error", "qdma-queue0",
"qdma-queue1", "qdma-queue2", "qdma-queue3";
+ #dma-cells = <1>;
dma-channels = <8>;
block-number = <1>;
block-offset = <0x10000>;
@@ -940,7 +941,7 @@
#fsl,rcpm-wakeup-cells = <1>;
};
- ftm_alarm0: timer@29d0000 {
+ ftm_alarm0: rtc@29d0000 {
compatible = "fsl,ls1046a-ftm-alarm";
reg = <0x0 0x29d0000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x20000>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1088a-qds.dts b/dts/upstream/src/arm64/freescale/fsl-ls1088a-qds.dts
index aa52ff7..d238a84 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1088a-qds.dts
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1088a-qds.dts
@@ -113,7 +113,7 @@
3 0 0x5 0x20000000 0x00010000>;
status = "okay";
- nor@0,0 {
+ flash@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
index 604bf88..e3a7db2 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -118,7 +118,7 @@
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
- interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -131,7 +131,7 @@
};
thermal-zones {
- core-cluster {
+ cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
@@ -166,7 +166,7 @@
};
};
- soc {
+ soc-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -183,10 +183,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
- <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
- <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
- <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
};
pmu {
@@ -280,7 +280,7 @@
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
- interrupts = <0 23 0x4>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
@@ -347,7 +347,7 @@
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -356,14 +356,14 @@
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gpio0: gpio@2300000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
@@ -374,7 +374,7 @@
gpio1: gpio@2310000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
@@ -385,7 +385,7 @@
gpio2: gpio@2320000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
@@ -396,7 +396,7 @@
gpio3: gpio@2330000 {
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
- interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
gpio-controller;
#gpio-cells = <2>;
@@ -407,7 +407,7 @@
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
- interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
#address-cells = <2>;
#size-cells = <1>;
@@ -419,7 +419,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
@@ -430,7 +430,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
@@ -441,7 +441,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
@@ -452,7 +452,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(8)>;
status = "disabled";
@@ -474,10 +474,10 @@
status = "disabled";
};
- esdhc: esdhc@2140000 {
+ esdhc: mmc@2140000 {
compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
- interrupts = <0 28 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <0>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
@@ -490,7 +490,7 @@
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -501,7 +501,7 @@
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
- interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -514,7 +514,7 @@
reg = <0x0 0x3200000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
- interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
dma-coherent;
@@ -565,7 +565,7 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -604,7 +604,7 @@
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -642,7 +642,7 @@
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
<0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
@@ -880,7 +880,7 @@
};
};
- cluster1_core0_watchdog: wdt@c000000 {
+ cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -890,7 +890,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt@c010000 {
+ cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -900,7 +900,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core2_watchdog: wdt@c020000 {
+ cluster1_core2_watchdog: watchdog@c020000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc020000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -910,7 +910,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core3_watchdog: wdt@c030000 {
+ cluster1_core3_watchdog: watchdog@c030000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc030000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -920,7 +920,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt@c100000 {
+ cluster2_core0_watchdog: watchdog@c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -930,7 +930,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt@c110000 {
+ cluster2_core1_watchdog: watchdog@c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -940,7 +940,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core2_watchdog: wdt@c120000 {
+ cluster2_core2_watchdog: watchdog@c120000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc120000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -950,7 +950,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core3_watchdog: wdt@c130000 {
+ cluster2_core3_watchdog: watchdog@c130000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc130000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -1040,7 +1040,7 @@
little-endian;
};
- ftm_alarm0: timer@2800000 {
+ ftm_alarm0: rtc@2800000 {
compatible = "fsl,ls1088a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls2080a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls2080a.dtsi
index 8352197..e9bc1f4 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls2080a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls2080a.dtsi
@@ -15,7 +15,7 @@
/ {
pmu {
compatible = "arm,cortex-a57-pmu";
- interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls2088a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls2088a.dtsi
index 245bbd6..60c4225 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls2088a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls2088a.dtsi
@@ -15,7 +15,7 @@
/ {
pmu {
compatible = "arm,cortex-a72-pmu";
- interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls208xa-qds.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls208xa-qds.dtsi
index e2c94da..9178cd6 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls208xa-qds.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls208xa-qds.dtsi
@@ -43,7 +43,7 @@
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
- nor@0,0 {
+ flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls208xa-rdb.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
index 537cecb..69cd05a 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls208xa-rdb.dtsi
@@ -21,7 +21,7 @@
0x2 0x0 0x5 0x30000000 0x00010000
0x3 0x0 0x5 0x20000000 0x00010000>;
- nor@0,0 {
+ flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
index ccba0a1..1b306d6 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -58,7 +58,7 @@
#size-cells = <2>;
ranges;
interrupt-controller;
- interrupts = <1 9 0x4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
@@ -80,7 +80,7 @@
};
thermal-zones {
- ddr-controller1 {
+ ddr-ctrl1-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -94,7 +94,7 @@
};
};
- ddr-controller2 {
+ ddr-ctrl2-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
@@ -108,7 +108,7 @@
};
};
- ddr-controller3 {
+ ddr-ctrl3-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
@@ -122,7 +122,7 @@
};
};
- core-cluster1 {
+ cluster1-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
@@ -151,7 +151,7 @@
};
};
- core-cluster2 {
+ cluster2-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 5>;
@@ -180,7 +180,7 @@
};
};
- core-cluster3 {
+ cluster3-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 6>;
@@ -209,7 +209,7 @@
};
};
- core-cluster4 {
+ cluster4-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 7>;
@@ -241,10 +241,10 @@
timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
- <1 14 4>, /* Physical Non-Secure PPI, active-low */
- <1 11 4>, /* Virtual PPI, active-low */
- <1 10 4>; /* Hypervisor PPI, active-low */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hypervisor PPI */
};
psci {
@@ -314,7 +314,7 @@
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
- interrupts = <0 23 0x4>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
fsl,tmu-calibration =
<0x00000000 0x00000026>,
@@ -362,7 +362,7 @@
reg = <0x0 0x21c0500 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 32 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
serial1: serial@21c0600 {
@@ -370,7 +370,7 @@
reg = <0x0 0x21c0600 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 32 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
serial2: serial@21d0500 {
@@ -378,7 +378,7 @@
reg = <0x0 0x21d0500 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 33 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
};
serial3: serial@21d0600 {
@@ -386,10 +386,10 @@
reg = <0x0 0x21d0600 0x0 0x100>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
- interrupts = <0 33 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
};
- cluster1_core0_watchdog: wdt@c000000 {
+ cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -399,7 +399,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt@c010000 {
+ cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -409,7 +409,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt@c100000 {
+ cluster2_core0_watchdog: watchdog@c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -419,7 +419,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt@c110000 {
+ cluster2_core1_watchdog: watchdog@c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -429,7 +429,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core0_watchdog: wdt@c200000 {
+ cluster3_core0_watchdog: watchdog@c200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -439,7 +439,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core1_watchdog: wdt@c210000 {
+ cluster3_core1_watchdog: watchdog@c210000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -449,7 +449,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core0_watchdog: wdt@c300000 {
+ cluster4_core0_watchdog: watchdog@c300000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -459,7 +459,7 @@
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core1_watchdog: wdt@c310000 {
+ cluster4_core1_watchdog: watchdog@c310000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -883,48 +883,48 @@
#iommu-cells = <1>;
stream-match-mask = <0x7C00>;
dma-coherent;
- interrupts = <0 13 4>, /* global secure fault */
- <0 14 4>, /* combined secure interrupt */
- <0 15 4>, /* global non-secure fault */
- <0 16 4>, /* combined non-secure interrupt */
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, /* global non-secure fault */
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, /* combined non-secure interrupt */
/* performance counter interrupts 0-7 */
- <0 211 4>, <0 212 4>,
- <0 213 4>, <0 214 4>,
- <0 215 4>, <0 216 4>,
- <0 217 4>, <0 218 4>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
/* per context interrupt, 64 interrupts */
- <0 146 4>, <0 147 4>,
- <0 148 4>, <0 149 4>,
- <0 150 4>, <0 151 4>,
- <0 152 4>, <0 153 4>,
- <0 154 4>, <0 155 4>,
- <0 156 4>, <0 157 4>,
- <0 158 4>, <0 159 4>,
- <0 160 4>, <0 161 4>,
- <0 162 4>, <0 163 4>,
- <0 164 4>, <0 165 4>,
- <0 166 4>, <0 167 4>,
- <0 168 4>, <0 169 4>,
- <0 170 4>, <0 171 4>,
- <0 172 4>, <0 173 4>,
- <0 174 4>, <0 175 4>,
- <0 176 4>, <0 177 4>,
- <0 178 4>, <0 179 4>,
- <0 180 4>, <0 181 4>,
- <0 182 4>, <0 183 4>,
- <0 184 4>, <0 185 4>,
- <0 186 4>, <0 187 4>,
- <0 188 4>, <0 189 4>,
- <0 190 4>, <0 191 4>,
- <0 192 4>, <0 193 4>,
- <0 194 4>, <0 195 4>,
- <0 196 4>, <0 197 4>,
- <0 198 4>, <0 199 4>,
- <0 200 4>, <0 201 4>,
- <0 202 4>, <0 203 4>,
- <0 204 4>, <0 205 4>,
- <0 206 4>, <0 207 4>,
- <0 208 4>, <0 209 4>;
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
};
dspi: spi@2100000 {
@@ -933,18 +933,18 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <0 26 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "dspi";
spi-num-chipselects = <5>;
};
- esdhc: esdhc@2140000 {
+ esdhc: mmc@2140000 {
status = "disabled";
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
- interrupts = <0 28 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
voltage-ranges = <1800 1800 3300 3300>;
@@ -956,7 +956,7 @@
gpio0: gpio@2300000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <0 36 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
@@ -967,7 +967,7 @@
gpio1: gpio@2310000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <0 36 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
@@ -978,7 +978,7 @@
gpio2: gpio@2320000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
- interrupts = <0 37 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
@@ -989,7 +989,7 @@
gpio3: gpio@2330000 {
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
- interrupts = <0 37 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
@@ -1003,8 +1003,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <0 34 0x4>; /* Level high type */
- clock-names = "i2c";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
};
@@ -1015,8 +1015,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <0 34 0x4>; /* Level high type */
- clock-names = "i2c";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
};
@@ -1027,8 +1027,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <0 35 0x4>; /* Level high type */
- clock-names = "i2c";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
};
@@ -1039,8 +1039,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <0 35 0x4>; /* Level high type */
- clock-names = "i2c";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
};
@@ -1048,7 +1048,7 @@
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
- interrupts = <0 21 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
#address-cells = <2>;
#size-cells = <1>;
@@ -1077,7 +1077,7 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 108 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
@@ -1099,7 +1099,7 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 113 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
@@ -1121,7 +1121,7 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 118 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
@@ -1143,7 +1143,7 @@
pcie4: pcie@3700000 {
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
reg-names = "regs", "config";
- interrupts = <0 123 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
#address-cells = <3>;
#size-cells = <2>;
@@ -1166,7 +1166,7 @@
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
- interrupts = <0 133 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
dma-coherent;
@@ -1176,7 +1176,7 @@
status = "disabled";
compatible = "fsl,ls2080a-ahci";
reg = <0x0 0x3210000 0x0 0x10000>;
- interrupts = <0 136 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
dma-coherent;
@@ -1192,7 +1192,7 @@
usb0: usb@3100000 {
compatible = "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <0 80 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -1203,7 +1203,7 @@
usb1: usb@3110000 {
compatible = "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
- interrupts = <0 81 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
@@ -1215,7 +1215,7 @@
ccn@4000000 {
compatible = "arm,ccn-504";
reg = <0x0 0x04000000 0x0 0x01000000>;
- interrupts = <0 12 4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
rcpm: power-controller@1e34040 {
@@ -1225,7 +1225,7 @@
little-endian;
};
- ftm_alarm0: timer@2800000 {
+ ftm_alarm0: rtc@2800000 {
compatible = "fsl,ls208xa-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
@@ -1236,14 +1236,14 @@
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
- interrupts = <0 17 0x4>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
- interrupts = <0 18 0x4>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
index 9605559..bd75a65 100644
--- a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -449,7 +449,7 @@
};
thermal-zones {
- cluster6-7 {
+ cluster6-7-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
@@ -492,7 +492,7 @@
};
};
- ddr-cluster5 {
+ ddr-ctrl5-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
@@ -512,7 +512,7 @@
};
};
- wriop {
+ wriop-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 2>;
@@ -532,7 +532,7 @@
};
};
- dce-qbman-hsio2 {
+ dce-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 3>;
@@ -552,7 +552,7 @@
};
};
- ccn-dpaa-tbu {
+ ccn-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
@@ -572,7 +572,7 @@
};
};
- cluster4-hsio3 {
+ cluster4-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 5>;
@@ -592,7 +592,7 @@
};
};
- cluster2-3 {
+ cluster2-3-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 6>;
@@ -745,7 +745,7 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -761,7 +761,7 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -777,7 +777,7 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -793,7 +793,7 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -809,7 +809,7 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -825,7 +825,7 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -841,7 +841,7 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -857,7 +857,7 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
+ clock-names = "ipg";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
@@ -925,10 +925,10 @@
status = "disabled";
};
- esdhc0: esdhc@2140000 {
- compatible = "fsl,esdhc";
+ esdhc0: mmc@2140000 {
+ compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
- interrupts = <0 28 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dma-coherent;
@@ -939,10 +939,10 @@
status = "disabled";
};
- esdhc1: esdhc@2150000 {
- compatible = "fsl,esdhc";
+ esdhc1: mmc@2150000 {
+ compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
- interrupts = <0 63 0x4>; /* Level high type */
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dma-coherent;
@@ -1027,7 +1027,7 @@
};
gpio0: gpio@2300000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -1038,7 +1038,7 @@
};
gpio1: gpio@2310000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -1049,7 +1049,7 @@
};
gpio2: gpio@2320000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -1060,7 +1060,7 @@
};
gpio3: gpio@2330000 {
- compatible = "fsl,qoriq-gpio";
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
reg = <0x0 0x2330000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
@@ -1085,7 +1085,7 @@
little-endian;
};
- ftm_alarm0: timer@2800000 {
+ ftm_alarm0: rtc@2800000 {
compatible = "fsl,lx2160a-ftm-alarm";
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
@@ -1702,8 +1702,8 @@
pinmux_i2crv: pinmux@70010012c {
compatible = "pinctrl-single";
reg = <0x00000007 0x0010012c 0x0 0xc>;
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
index 897cbb7..ff5df0f 100644
--- a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
@@ -447,7 +447,6 @@
<&lsio_mu13 2 1>,
<&lsio_mu13 3 0>,
<&lsio_mu13 3 1>;
- memory-region = <&dsp_reserved>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-cm41.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-cm41.dtsi
new file mode 100644
index 0000000..d715f2a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8-ss-cm41.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
+
+cm41_ipg_clk: clock-cm41-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm41_ipg_clk";
+};
+
+cm41_subsys: bus@38000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x38000000 0x0 0x38000000 0x4000000>;
+ interrupt-parent = <&cm41_intmux>;
+
+ cm41_i2c: i2c@3b230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x3b230000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>,
+ <&cm41_i2c_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+ status = "disabled";
+ };
+
+ cm41_intmux: intmux@3b400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x3b400000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&cm41_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;
+ status = "disabled";
+ };
+
+ cm41_i2c_lpcg: clock-controller@3b630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x3b630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,
+ <&cm41_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "cm41_lpcg_i2c_clk",
+ "cm41_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_1_I2C>;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi
index 4aaf5a0..a4a10ce 100644
--- a/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8-ss-conn.dtsi
@@ -28,6 +28,13 @@
clock-output-names = "conn_ipg_clk";
};
+conn_bch_clk: clock-conn-bch {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "conn_bch_clk";
+};
+
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -302,4 +309,66 @@
"usb3_aclk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
};
+
+ rawnand_0_lpcg: clock-controller@5b290000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "gpmi_bch",
+ "gpmi_io",
+ "gpmi_apb",
+ "gpmi_bch_apb";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ rawnand_4_lpcg: clock-controller@5b290004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290004 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "apbhdma_hclk";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ dma_apbh: dma-controller@5b810000 {
+ compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x5b810000 0x2000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>;
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ gpmi: nand-controller@5b812000{
+ compatible = "fsl,imx8qxp-gpmi-nand";
+ reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_4>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_0>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "gpmi_io", "gpmi_apb",
+ "gpmi_bch", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ };
};
diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts b/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts
index 2412ab1..1a74ac3 100644
--- a/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx8dxl-evk.dts
@@ -24,6 +24,19 @@
stdout-path = &lpuart0;
};
+ imx8dxl-cm4 {
+ compatible = "fsl,imx8qxp-cm4";
+ clocks = <&clk_dummy>;
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ fsl,entry-address = <0x34fe0000>;
+ };
+
+
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
@@ -51,6 +64,37 @@
alloc-ranges = <0 0x98000000 0 0x14000000>;
linux,cma-default;
};
+
+ vdev0vring0: memory0@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: memory-rsc-table@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory-vdevbuffer@90400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
};
m2_uart1_sel: regulator-m2uart1sel {
@@ -137,6 +181,76 @@
enable-active-high;
regulator-always-on;
};
+
+ bt_sco_codec: audio-codec-bt {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai0>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&bt_sco_codec 1>;
+ };
+ };
+
+ sound-wm8960-1 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai1>;
+ audio-codec = <&wm8960_1>;
+ audio-asrc = <&asrc0>;
+ audio-routing = "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "Mic Jack", "MICB";
+ };
+
+ sound-wm8960-2 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio-2";
+ audio-cpu = <&sai2>;
+ audio-codec = <&wm8960_2>;
+ audio-routing = "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "Mic Jack", "MICB";
+ };
+
+ sound-wm8960-3 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio-3";
+ audio-cpu = <&sai3>;
+ audio-codec = <&wm8960_3>;
+ audio-routing = "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "Mic Jack", "MICB";
+ };
};
&adc0 {
@@ -144,6 +258,11 @@
status = "okay";
};
+&asrc0 {
+ fsl,asrc-rate = <48000>;
+ status = "okay";
+};
+
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
@@ -271,6 +390,78 @@
};
};
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ wm8960_1: audio-codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "mclk";
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>,
+ <49152000>,
+ <12288000>,
+ <12288000>;
+ wlf,shared-lrclk;
+ wlf,hp-cfg = <2 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ wm8960_2: audio-codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "mclk";
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>,
+ <49152000>,
+ <12288000>,
+ <12288000>;
+ wlf,shared-lrclk;
+ wlf,hp-cfg = <2 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ wm8960_3: audio-codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "mclk";
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&mclkout1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>,
+ <49152000>,
+ <12288000>,
+ <12288000>;
+ wlf,shared-lrclk;
+ wlf,hp-cfg = <2 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ };
+ };
+
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
@@ -358,6 +549,10 @@
status = "okay";
};
+&lsio_mu5 {
+ status = "okay";
+};
+
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -390,6 +585,53 @@
status = "okay";
};
+&sai0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai0>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai0_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ status = "okay";
+};
+
+&sai1 {
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ status = "okay";
+};
+
+&sai2 {
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai2_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&sai3 {
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai3_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
@@ -632,6 +874,41 @@
>;
};
+ pinctrl_sai0: sai0grp {
+ fsl,pins = <
+ IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060
+ IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040
+ IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060
+ IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060
+ IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040
+ IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040
+ IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060
+ IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040
+ IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040
+ IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040
+ IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040
+ IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi
index 5d012c9..7243452 100644
--- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-adma.dtsi
@@ -3,6 +3,63 @@
* Copyright 2019~2020, 2022 NXP
*/
+/delete-node/ &asrc1;
+/delete-node/ &asrc1_lpcg;
+/delete-node/ &adc1;
+/delete-node/ &adc1_lpcg;
+/delete-node/ &amix;
+/delete-node/ &amix_lpcg;
+/delete-node/ &edma1;
+/delete-node/ &esai0;
+/delete-node/ &esai0_lpcg;
+/delete-node/ &sai4;
+/delete-node/ &sai4_lpcg;
+/delete-node/ &sai5;
+/delete-node/ &sai5_lpcg;
+
+&acm {
+ compatible = "fsl,imx8dxl-acm";
+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+ <&pd IMX_SC_R_AUDIO_CLK_1>,
+ <&pd IMX_SC_R_MCLK_OUT_0>,
+ <&pd IMX_SC_R_MCLK_OUT_1>,
+ <&pd IMX_SC_R_AUDIO_PLL_0>,
+ <&pd IMX_SC_R_AUDIO_PLL_1>,
+ <&pd IMX_SC_R_ASRC_0>,
+ <&pd IMX_SC_R_SAI_0>,
+ <&pd IMX_SC_R_SAI_1>,
+ <&pd IMX_SC_R_SAI_2>,
+ <&pd IMX_SC_R_SAI_3>,
+ <&pd IMX_SC_R_SPDIF_0>,
+ <&pd IMX_SC_R_MQS_0>;
+ clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_rec1_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&clk_ext_aud_mclk0>,
+ <&clk_ext_aud_mclk1>,
+ <&clk_spdif0_rx>,
+ <&clk_sai0_rx_bclk>,
+ <&clk_sai0_tx_bclk>,
+ <&clk_sai1_rx_bclk>,
+ <&clk_sai1_tx_bclk>,
+ <&clk_sai2_rx_bclk>,
+ <&clk_sai3_rx_bclk>;
+ clock-names = "aud_rec_clk0_lpcg_clk",
+ "aud_rec_clk1_lpcg_clk",
+ "aud_pll_div_clk0_lpcg_clk",
+ "aud_pll_div_clk1_lpcg_clk",
+ "ext_aud_mclk0",
+ "ext_aud_mclk1",
+ "spdif0_rx",
+ "sai0_rx_bclk",
+ "sai0_tx_bclk",
+ "sai1_rx_bclk",
+ "sai1_tx_bclk",
+ "sai2_rx_bclk",
+ "sai3_rx_bclk";
+};
+
&audio_ipg_clk {
clock-frequency = <160000000>;
};
@@ -177,3 +234,24 @@
&lpspi3 {
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&sai0 {
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai1 {
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai2 {
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sai3 {
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spdif0 {
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
index 6d13e4f..1e02b04 100644
--- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
@@ -108,6 +108,13 @@
};
+&dma_apbh {
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&enet0_lpcg {
clocks = <&conn_enet0_root_clk>,
<&conn_enet0_root_clk>,
@@ -127,6 +134,10 @@
assigned-clock-rates = <125000000>;
};
+&gpmi {
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&usdhc1 {
compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
index 90d1901..930e14f 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
@@ -400,7 +400,7 @@
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
- interrupts = <11 8>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
typec1_con: connector {
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-iot-gateway.dts b/dts/upstream/src/arm64/freescale/imx8mm-iot-gateway.dts
new file mode 100644
index 0000000..370558a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-iot-gateway.dts
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2020 CompuLab
+
+#include "imx8mm-ucm-som.dtsi"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+/ {
+ model = "CompuLab i.MX8MM IoT Gateway";
+ compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm";
+
+ regulator-usbhub-ena {
+ compatible = "regulator-fixed";
+ regulator-name = "usbhub_ena";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-usbhub-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "usbhub_rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-uart1-mode {
+ compatible = "regulator-fixed";
+ regulator-name = "uart1_mode";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-uart1-duplex {
+ compatible = "regulator-fixed";
+ regulator-name = "uart1_duplex";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-uart1-shdn {
+ compatible = "regulator-fixed";
+ regulator-name = "uart1_shdn";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-uart1-trmen {
+ compatible = "regulator-fixed";
+ regulator-name = "uart1_trmen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ regulator-usdhc2-v {
+ compatible = "regulator-fixed";
+ regulator-name = "usdhc2_v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-mpcie2-rst {
+ compatible = "regulator-fixed";
+ regulator-name = "mpcie2_rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-mpcie2lora-dis {
+ compatible = "regulator-fixed";
+ regulator-name = "mpcie2lora_dis";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ pcie0_refclk: clock-pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbotg2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dr_mode = "host";
+ usb-role-switch;
+ status = "okay";
+
+ usbhub@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb9514>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet: ethernet@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ mmc-ddr-1_8v;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* mPCIe2 */
+ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x140
+ MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1csgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140
+ >;
+ };
+
+ pinctrl_usb9514: usb9514grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x140 /* USB_PS_EN */
+ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 /* HUB_RSTn */
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso
new file mode 100644
index 0000000..353ace3
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Jens Lang <j.lang@phytec.de>
+ *
+ * Tauri-L 2 x RS232:
+ * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "phytec,imx8mm-phygate-tauri-l";
+
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+ uart4_rs485_en {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "uart4_rs485_en";
+ };
+};
+
+/* UART2 - RS232 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+/* UART4 - RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpio3_hog: gpio3hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso
new file mode 100644
index 0000000..8a75d67
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Jens Lang <j.lang@phytec.de>
+ *
+ * Tauri-L RS232 + RS485:
+ * - GPIO3_20 uart4_rs485_en needs to be driven high (active)
+ * - GPIO3_25 RS485_DE Driver enable
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "phytec,imx8mm-phygate-tauri-l";
+
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+ uart4_rs485_en {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "uart4_rs485_en";
+ };
+};
+
+/* UART2 - RS232 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+/* UART4 - RS485 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpio3_hog: gpio3hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso
new file mode 100644
index 0000000..107f743
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Author: Jens Lang <j.lang@phytec.de>
+ *
+ * Tauri-L RS232 with RTS/CTS hardware flow control:
+ * - UART4_TX becomes RTS
+ * - UART4_RX becomes CTS
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include "imx8mm-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+
+&{/} {
+ compatible = "phytec,imx8mm-phygate-tauri-l";
+
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
+ MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00
+ MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
index 27a9025..ba6ce3c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-phycore-som.dtsi"
/ {
@@ -185,6 +186,15 @@
status = "okay";
};
+&pcie_phy {
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ fsl,clkreq-unsupported;
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ status = "okay";
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml.dtsi
index 8c0c6e7..ca0205b 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml.dtsi
@@ -62,11 +62,15 @@
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-ucm-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-ucm-som.dtsi
new file mode 100644
index 0000000..d3b2120
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-ucm-som.dtsi
@@ -0,0 +1,679 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2018 CompuLab
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ mmc0 = &usdhc3;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 3000000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <222>;
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ heartbeat-led {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ pmic_osc: clock-pmic {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic_osc";
+ };
+
+ wlreg_on: regulator-wlreg-on {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "wlreg_on";
+ gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ regulator-usdhc3rst {
+ compatible = "regulator-fixed";
+ regulator-name = "usdhc3_rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ enable-active-high;
+ };
+
+ regulator-fec1rst {
+ compatible = "regulator-fixed";
+ regulator-name = "fec1_rst";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ enable-active-high;
+ startup-delay-us = <500>;
+ regulator-boot-on;
+ };
+};
+
+&A53_0 {
+ arm-supply = <&buck2>;
+};
+
+&cpu_alert0 {
+ temperature = <105000>;
+};
+
+&cpu_crit0 {
+ temperature = <115000>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ reg = <0x4b>;
+ compatible = "rohm,bd71837";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ #clock-cells = <0>;
+ clocks = <&pmic_osc>;
+ clock-names = "osc";
+ clock-output-names = "pmic_clk";
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7: BUCK7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck8: BUCK8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7: LDO7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ rtc_i2c: rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "disabled";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm_backlight>;
+ status = "okay";
+};
+
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <49152000>;
+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
+ <&clk IMX8MM_AUDIO_PLL2_OUT>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&snvs {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ status = "disabled";
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 { /* bluetooth */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "disabled";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt>;
+ max-speed = <3000000>;
+ device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ hnp-disable;
+ srp-disable;
+ disable-over-current;
+ status = "disabled";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+ bus-width = <4>;
+ non-removable;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ no-1-8-v;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x190
+ >;
+ };
+
+ pinctrl_bt: bt0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 /* BT_REG_ON */
+ MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 /* BT_DEV_WU */
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 /* BT_HST_WU */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_pwm_backlight: pwmbacklightgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x03
+ >;
+ };
+
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
+ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x00
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi
index de7f67a..36803b0 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw700x.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -113,6 +114,25 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7901.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7901.dts
index 35ae0fa..136cb30 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7901.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7901.dts
@@ -364,8 +364,6 @@
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
index c11260c..1d56f2a 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
@@ -314,8 +314,6 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7903.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7903.dts
index db1737b..4547016 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7903.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7903.dts
@@ -280,8 +280,6 @@
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7904.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7904.dts
index 05489a3..ef951bc 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7904.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7904.dts
@@ -330,8 +330,6 @@
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-verdin.dtsi
index 9854474..5fa3959 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-verdin.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin.dtsi
@@ -228,15 +228,16 @@
pinctrl-0 = <&pinctrl_ecspi2>;
};
-/* Verdin CAN_1 (On-module) */
+/* On-module SPI */
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
+ pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>;
status = "okay";
+ /* Verdin CAN_1 */
can1: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&clk40m>;
@@ -246,6 +247,12 @@
reg = <0>;
spi-max-frequency = <8500000>;
};
+
+ verdin_som_tpm: tpm@1 {
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
/* Verdin ETH_1 (On-module PHY) */
@@ -548,7 +555,7 @@
/* Verdin I2C_2_DSI */
&i2c2 {
- clock-frequency = <10000>;
+ clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@@ -808,8 +815,7 @@
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
- <&pinctrl_pmic_tpm_ena>;
+ <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
pinctrl_can1_int: can1intgrp {
fsl,pins =
@@ -1111,7 +1117,7 @@
};
/* control signal for optional ATTPM20P or SE050 */
- pinctrl_pmic_tpm_ena: pmictpmenagrp {
+ pinctrl_tpm_spi_cs: tpmspicsgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi
index fb24b9a..e68a3fd 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi
@@ -60,11 +60,15 @@
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts b/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts
index 0b1fa04..72004ab 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mn-venice-gw7902.dts
@@ -312,8 +312,6 @@
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts b/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
index e5d3901..cc9b81d 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
@@ -211,13 +211,12 @@
simple-audio-card,cpu {
sound-dai = <&sai3>;
+ frame-master;
+ bitclock-master;
};
simple-audio-card,codec {
sound-dai = <&wm8962>;
- clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- frame-master;
- bitclock-master;
};
};
};
@@ -302,10 +301,18 @@
adv_bridge: hdmi@3d {
compatible = "adi,adv7535";
- reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
- reg-names = "main", "cec", "edid", "packet";
+ reg = <0x3d>;
+ reg-names = "main";
+ interrupt-parent = <&gpio4>;
+ interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
#sound-dai-cells = <0>;
+ avdd-supply = <&buck5>;
+ dvdd-supply = <&buck5>;
+ pvdd-supply = <&buck5>;
+ a2vdd-supply = <&buck5>;
+ v1p2-supply = <&buck5>;
+ v3p3-supply = <&buck4>;
ports {
#address-cells = <1>;
@@ -499,10 +506,9 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
- <&clk IMX8MP_AUDIO_PLL2> ;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <12288000>, <361267200>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-beacon-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-beacon-som.dtsi
index 8be251b..15f7ab5 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-beacon-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-beacon-som.dtsi
@@ -71,7 +71,6 @@
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
- snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -106,7 +105,6 @@
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
index 9b8f97a..af02af9 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
@@ -20,6 +20,18 @@
stdout-path = &uart2;
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -94,6 +106,28 @@
};
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -239,6 +273,10 @@
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -356,6 +394,15 @@
>;
};
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts
index 3b1c940..ebdf13e 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk2.dts
@@ -69,6 +69,18 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X38";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
led {
compatible = "gpio-leds";
@@ -184,6 +196,33 @@
status = "okay";
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
&pcie_phy {
clock-names = "ref";
clocks = <&hsio_blk_ctrl>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk3.dts b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk3.dts
index ac7ec75..ef012e8 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk3.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-pdk3.dts
@@ -75,6 +75,18 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X28";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
led {
compatible = "gpio-leds";
@@ -248,6 +260,33 @@
status = "okay";
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ ddc-i2c-bus = <&i2cmuxed1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
&pcie_phy {
clocks = <&pcieclk 1>;
clock-names = "ref";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
index f5115f9..a90e28c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
@@ -78,6 +78,11 @@
cpu-supply = <&buck2>;
};
+&audio_blk_ctrl {
+ assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>;
+ assigned-clock-rates = <393216000>;
+};
+
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
@@ -105,14 +110,14 @@
#size-cells = <0>;
/* Up to one of these two PHYs may be populated. */
- ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
+ ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
- reg = <0>;
+ reg = <1>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>;
@@ -151,14 +156,14 @@
#size-cells = <0>;
/* Up to one PHY may be populated. */
- ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
+ ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
- reg = <1>;
+ reg = <2>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso
new file mode 100644
index 0000000..1b71890
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ panel-lvds {
+ compatible = "koe,tx26d202vm0bwa";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_vext_3v3>;
+
+ panel-timing {
+ clock-frequency = <148500000>;
+ hactive = <1920>;
+ vactive = <1200>;
+ hfront-porch = <130>;
+ hback-porch = <70>;
+ hsync-len = <30>;
+ vfront-porch = <5>;
+ vback-porch = <5>;
+ vsync-len = <5>;
+ de-active = <1>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+
+ panel_in_odd: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+
+ panel_in_even: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+ };
+};
+
+&backlight_lvds {
+ status = "okay";
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ status = "okay";
+
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&panel_in_odd>;
+ };
+ };
+
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&panel_in_even>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
index 8be5b2a..9383477 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
@@ -16,6 +16,16 @@
stdout-path = &uart2;
};
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 100000 0>;
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <100>;
+ power-supply = <®_per_12v>;
+ status = "disabled";
+ };
+
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
@@ -96,6 +106,15 @@
enable-active-high;
};
+ reg_per_12v: regulator-per-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "PER_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -114,6 +133,11 @@
regulator-max-microvolt = <3300000>;
};
+ audio_codec_bt_sco: audio-codec-bt-sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "wm8960-audio";
@@ -143,6 +167,25 @@
sound-dai = <&wm8960>;
};
+ };
+
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&audio_codec_bt_sco 1>;
+ };
};
sound-hdmi {
@@ -166,6 +209,19 @@
};
};
+ sound-xcvr {
+ compatible = "fsl,imx-audio-card";
+ model = "imx-audio-xcvr";
+
+ pri-dai-link {
+ link-name = "XCVR PCM";
+
+ cpu {
+ sound-dai = <&xcvr>;
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -251,7 +307,6 @@
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -608,6 +663,17 @@
status = "okay";
};
+&sai2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@@ -694,7 +760,15 @@
status = "okay";
};
+&xcvr {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
pinctrl_audio_pwr_reg: audiopwrreggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
@@ -784,6 +858,12 @@
>;
};
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
@@ -880,6 +960,15 @@
>;
};
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
+ MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
+ >;
+ };
+
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts b/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
index da4b180..83194ea 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
@@ -46,6 +46,24 @@
};
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
&i2c1 {
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
@@ -92,6 +110,15 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_smarc_gpio>;
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
+ MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
+ >;
+ };
+
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
new file mode 100644
index 0000000..d7fd9d3
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
@@ -0,0 +1,906 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Martin Schmiedel
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx8mp-tqma8mpql.dtsi"
+
+/ {
+ model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
+ compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
+ chassis-type = "embedded";
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc1;
+ rtc0 = &pcf85063;
+ rtc1 = &snvs_rtc;
+ };
+
+ /* X8 */
+ backlight_lvds: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm2 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_vcc_12v0>;
+ enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ /* X7 + X8 */
+ display: display {
+ /*
+ * Display is not fixed, so compatible has to be added from
+ * DT overlay
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvdsdisplay>;
+ power-supply = <®_vcc_3v3>;
+ enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight_lvds>;
+ status = "disabled";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpioled>;
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <0>;
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X9";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+
+ reg_vcc_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vcc_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_12v0: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x38000000>;
+ alloc-ranges = <0 0x40000000 0 0xB0000000>;
+ linux,cma-default;
+ };
+ };
+
+ rfkill {
+ compatible = "rfkill-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rfkill>;
+ label = "rfkill-pcie-wlan";
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-tlv320aic32x4";
+ model = "tq-mba8mp-ras314";
+ audio-cpu = <&sai5>;
+ audio-codec = <&tlv320aic3x04>;
+ audio-routing =
+ "IN3_L", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR";
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy3>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos_phy>;
+ reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy>;
+ reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ enet-phy-lane-no-swap;
+ interrupt-parent = <&gpio4>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+ };
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>;
+
+ gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "",
+ "", "", "GPIO8", "",
+ "", "", "", "",
+ "", "", "GPIO12", "GPIO13",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+
+ wifi-pmic-en-hog {
+ gpio-hog;
+ gpios = <0 0>;
+ output-high;
+ line-name = "WIFI_PMIC_EN";
+ };
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio2>;
+
+ gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25",
+ "GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2",
+ "", "", "GPIO1", "GPIO0",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3>;
+
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "TEMP_EVENT#", "", "", "",
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "HDMI_OC#", "GPIO14", "GPIO15", "GPIO16",
+ "GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20",
+ "PCIE_PERST#", "", "", "";
+
+ pewake-hog {
+ gpio-hog;
+ gpios = <25 0>;
+ input;
+ line-name = "PCIE_WAKE#";
+ };
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>,
+ <&pinctrl_gpt2_gpio>, <&pinctrl_gpt3_gpio>;
+
+ gpio-line-names = "", "GPIO18", "", "GPIO3",
+ "GPIO2", "GPIO21", "", "",
+ "", "", "", "",
+ "", "", "", "",
+ "", "", "GPIO5", "GPIO6",
+ "", "", "GPIO11", "GPIO10",
+ "GPIO9", "GPIO7", "", "GPIO4",
+ "", "", "", "";
+};
+
+&gpt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpt1>;
+ status = "disabled";
+};
+
+&gpt2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpt2>;
+ status = "disabled";
+};
+
+&gpt3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpt3>;
+ status = "disabled";
+};
+
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
+/* X5 + X6 Camera & Display interface */
+&i2c2 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+/* X1 ID_I2C */
+&i2c3 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ tlv320aic3x04: audio-codec@18 {
+ compatible = "ti,tlv320aic32x4";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tlv320aic3x04>;
+ reg = <0x18>;
+ clock-names = "mclk";
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>;
+ reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ iov-supply = <®_vcc_3v3>;
+ ldoin-supply = <®_vcc_3v3>;
+ };
+};
+
+/* X1 I2C */
+&i2c5 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c5>;
+ pinctrl-1 = <&pinctrl_i2c5_gpio>;
+ scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+/* X1 I2C on GPIO24/GPIO25 */
+&i2c6 {
+ clock-frequency = <384000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c6>;
+ pinctrl-1 = <&pinctrl_i2c6_gpio>;
+ scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "disabled";
+};
+
+&lcdif3 {
+ status = "okay";
+};
+
+&pcf85063 {
+ /* RTC_EVENT# is connected on MBa8MP-RAS314 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcf85063>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&pcie_phy {
+ clocks = <&hsio_blk_ctrl>;
+ clock-names = "ref";
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&sai5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai5>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* X1 UART1 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ assigned-clocks = <&clk IMX8MP_CLK_UART2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ status = "okay";
+};
+
+&uart4 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usb3_0 {
+ fsl,disable-port-power-control;
+ status = "okay";
+};
+
+&usb3_1 {
+ fsl,disable-port-power-control;
+ fsl,permanently-attached;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_vcc_5v0>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_vcc_5v0>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_vcc_3v3>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_vcc_3v3>;
+ };
+};
+
+/* X1 SD card on GPIO22-GPIO27 */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ disable-wp;
+ bus-width = <4>;
+ status = "disabled";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ no-mmc;
+ no-sdio;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x14>;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x140>,
+ <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x140>,
+ <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
+ <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x140>,
+ <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140>;
+ };
+
+ pinctrl_ecspi3_gpio: ecspi3gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x80>,
+ <MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x80>,
+ <MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x80>,
+ <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x80>,
+ <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x80>;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
+ <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
+ <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
+ <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
+ <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
+ <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
+ <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
+ <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
+ <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
+ <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
+ <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
+ <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
+ <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
+ <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
+ };
+
+ pinctrl_eqos_phy: eqosphygrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
+ <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
+ <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
+ <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
+ <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
+ <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
+ <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
+ };
+
+ pinctrl_fec_phy: fecphygrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
+ <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
+ };
+
+ pinctrl_gpioled: gpioledgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>,
+ <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>;
+ };
+
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x14>,
+ <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x14>;
+ };
+
+ pinctrl_gpio2: gpio2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x94>,
+ <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x94>,
+ <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x94>;
+ };
+
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>;
+ };
+
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x80>,
+ /* PCIE_WAKE# */
+ <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>,
+ <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x94>,
+ <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x94>;
+ };
+
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x80>,
+ <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x80>;
+ };
+
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
+ <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
+ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
+ <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>;
+ };
+
+ pinctrl_gpt1: gpt1grp {
+ fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>;
+ };
+
+ pinctrl_gpt1_gpio: gpt1gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x80>;
+ };
+
+ pinctrl_gpt2: gpt2grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>;
+ };
+
+ pinctrl_gpt2_gpio: gpt2gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>;
+ };
+
+ pinctrl_gpt3: gpt3grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>;
+ };
+
+ pinctrl_gpt3_gpio: gpt3gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x80>;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
+ <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>,
+ <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>;
+ };
+
+ pinctrl_i2c5: i2c5grp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c5_gpio: i2c5-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>,
+ <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>;
+ };
+
+ pinctrl_i2c6: i2c6grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
+ };
+
+ pinctrl_i2c6_gpio: i2c6-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
+ <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
+ };
+
+ pinctrl_pcf85063: pcf85063grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
+ <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x94>;
+ };
+
+ pinctrl_lvdsdisplay: lvdsdisplaygrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10>;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x14>;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>;
+ };
+
+ pinctrl_pwm3_gpio: pwm3grpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>;
+ };
+
+ pinctrl_pwm4_gpio: pwm4grpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
+ };
+
+ pinctrl_rfkill: rfkillgrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x14>;
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>,
+ <MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>,
+ <MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>,
+ <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>,
+ <MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>;
+ };
+
+ pinctrl_tlv320aic3x04: tlv320aic3x04grp {
+ fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
+ <MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
+ <MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
+ <MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x80>,
+ <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x80>,
+ <MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x80>,
+ <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x80>;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>,
+ <MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>,
+ <MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x14>,
+ <MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x14>;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
+ <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>,
+ <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>;
+ };
+
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>,
+ <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>,
+ <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>,
+ <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>,
+ <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>,
+ <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
+ <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
+ <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
+ <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index c51ed7d..ae64731 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -222,11 +222,6 @@
#size-cells = <2>;
ranges;
- ocram: ocram@900000 {
- no-map;
- reg = <0 0x900000 0 0x70000>;
- };
-
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
index ebc29a9..336785a 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
@@ -45,12 +45,16 @@
flash0: flash@0 {
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi
index 560c68e..6c75a5e 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw702x.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -102,6 +103,25 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
index a77e9a4..d765b79 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "imx8mp.dtsi"
@@ -225,6 +226,29 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
index 6e6b9c2..fbcd93e 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
@@ -4,6 +4,18 @@
*/
/ {
+ native-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X21";
+ type = "a";
+
+ port {
+ native_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
@@ -94,6 +106,27 @@
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
+/* Verdin HDMI_1 */
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&native_hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
/* Current measurement into module VCC */
&hwmon {
status = "okay";
@@ -139,6 +172,10 @@
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
/* Verdin PCIE_1 */
&pcie {
vpcie-supply = <®_pcie>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dev.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dev.dtsi
index 42ed44a..09733fe 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dev.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dev.dtsi
@@ -4,6 +4,18 @@
*/
/ {
+ native-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X37";
+ type = "a";
+
+ port {
+ native_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
reg_eth2phy: regulator-eth2phy {
compatible = "regulator-fixed";
enable-active-high;
@@ -103,6 +115,27 @@
vcc-supply = <®_1p8v>;
};
+/* Verdin HDMI_1 */
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&native_hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
/* Current measurement into module VCC */
&hwmon {
status = "okay";
@@ -141,6 +174,10 @@
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
/* Verdin PCIE_1 */
&pcie {
status = "okay";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi
index 1d15f74..3a40338 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi
@@ -11,6 +11,18 @@
#include <dt-bindings/leds/common.h>
/ {
+ native-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X14";
+ type = "a";
+
+ port {
+ native_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -91,6 +103,27 @@
status = "okay";
};
+/* Verdin HDMI_1 */
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&native_hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
/* Temperature sensor on Mallow */
&hwmon_temp {
compatible = "ti,tmp1075";
@@ -117,6 +150,10 @@
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
/* Verdin PCIE_1 */
&pcie {
status = "okay";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi.dtsi
index 91d5973..2ee91f3 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi.dtsi
@@ -41,8 +41,7 @@
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
- <&pinctrl_hdmi_hog>;
+ <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
};
/*
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi.dtsi
index ef94f9a..efcab00 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi.dtsi
@@ -55,8 +55,7 @@
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>,
- <&pinctrl_hdmi_hog>;
+ <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>;
};
/* On-module Bluetooth */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-yavia.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-yavia.dtsi
index a7b261f..533b7fe 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-yavia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-yavia.dtsi
@@ -6,6 +6,18 @@
#include <dt-bindings/leds/common.h>
/ {
+ native-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "J15";
+ type = "a";
+
+ port {
+ native_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
/* Carrier Board Supply +V1.8 */
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
@@ -105,6 +117,27 @@
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
+/* Verdin HDMI_1 */
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&native_hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
&hwmon_temp {
status = "okay";
};
@@ -127,6 +160,10 @@
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
/* Verdin PCIE_1 */
&pcie {
status = "okay";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
index aef4bef..d23a394 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
@@ -241,7 +241,6 @@
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
- snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -276,7 +275,6 @@
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -457,6 +455,13 @@
"SODIMM_44";
};
+/* Verdin HDMI_1 */
+&hdmi_tx {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+};
+
/* On-module I2C */
&i2c1 {
clock-frequency = <400000>;
@@ -650,8 +655,7 @@
/* Verdin I2C_2_DSI */
&i2c2 {
- /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
- clock-frequency = <10000>;
+ clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@@ -1117,10 +1121,10 @@
<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
};
- pinctrl_hdmi_hog: hdmihoggrp {
+ pinctrl_hdmi: hdmigrp {
fsl,pins =
- <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
- <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
+ <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x140>, /* SODIMM 63 */
+ <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SODIMM 61 */
};
/* On-module I2C */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp.dtsi b/dts/upstream/src/arm64/freescale/imx8mp.dtsi
index b92abb5..603dfe8 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp.dtsi
@@ -789,6 +789,23 @@
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_mlmix: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
+ <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>,
+ <800000000>,
+ <300000000>;
+ };
+
pgc_audio: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
@@ -821,6 +838,12 @@
assigned-clock-rates = <800000000>, <400000000>;
};
+ pgc_vpumix: power-domain@8 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
+ clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
+ };
+
pgc_gpu3d: power-domain@9 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
@@ -836,6 +859,28 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
+ pgc_vpu_g1: power-domain@11 {
+ #power-domain-cells = <0>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
+ clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+ };
+
+ pgc_vpu_g2: power-domain@12 {
+ #power-domain-cells = <0>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
+ clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+
+ };
+
+ pgc_vpu_vc8000e: power-domain@13 {
+ #power-domain-cells = <0>;
+ power-domains = <&pgc_vpumix>;
+ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
+ clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+ };
+
pgc_hdmimix: power-domain@14 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
@@ -873,50 +918,6 @@
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
};
-
- pgc_vpumix: power-domain@19 {
- #power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
- clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
- };
-
- pgc_vpu_g1: power-domain@20 {
- #power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
- clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
- };
-
- pgc_vpu_g2: power-domain@21 {
- #power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
- clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
- };
-
- pgc_vpu_vc8000e: power-domain@22 {
- #power-domain-cells = <0>;
- power-domains = <&pgc_vpumix>;
- reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
- clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
- };
-
- pgc_mlmix: power-domain@24 {
- #power-domain-cells = <0>;
- reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
- clocks = <&clk IMX8MP_CLK_ML_AXI>,
- <&clk IMX8MP_CLK_ML_AHB>,
- <&clk IMX8MP_CLK_NPU_ROOT>;
- assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
- <&clk IMX8MP_CLK_ML_AXI>,
- <&clk IMX8MP_CLK_ML_AHB>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
- assigned-clock-rates = <800000000>,
- <800000000>,
- <300000000>;
- };
};
};
};
@@ -1540,6 +1541,31 @@
dma-names = "tx";
status = "disabled";
};
+
+ xcvr: xcvr@30cc0000 {
+ compatible = "fsl,imx8mp-xcvr";
+ reg = <0x30cc0000 0x800>,
+ <0x30cc0800 0x400>,
+ <0x30cc0c00 0x080>,
+ <0x30cc0e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo",
+ "txfifo";
+ interrupts = /* XCVR IRQ 0 */
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ /* XCVR IRQ 1 */
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ /* XCVR PHY - SPDIF wakeup IRQ */
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+ dma-names = "rx", "tx";
+ resets = <&audio_blk_ctrl 0>;
+ status = "disabled";
+ };
};
sdma3: dma-controller@30e00000 {
@@ -1568,6 +1594,7 @@
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
@@ -1579,6 +1606,9 @@
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
power-domains = <&pgc_audio>;
+ assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
+ <&clk IMX8MP_AUDIO_PLL2>;
+ assigned-clock-rates = <393216000>, <361267200>;
};
};
@@ -1946,7 +1976,7 @@
};
irqsteer_hdmi: interrupt-controller@32fc2000 {
- compatible = "fsl,imx-irqsteer";
+ compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
reg = <0x32fc2000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
index ffb5fe6..1b39514 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
@@ -45,7 +45,6 @@
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <50>;
- wakeup-source;
};
key-vol-up {
@@ -53,7 +52,6 @@
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <50>;
- wakeup-source;
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq.dtsi
index 5ca6b22..01e5092 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq.dtsi
@@ -251,11 +251,15 @@
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8qm-mek.dts b/dts/upstream/src/arm64/freescale/imx8qm-mek.dts
index 6e05361..778741d 100644
--- a/dts/upstream/src/arm64/freescale/imx8qm-mek.dts
+++ b/dts/upstream/src/arm64/freescale/imx8qm-mek.dts
@@ -40,12 +40,99 @@
enable-active-high;
};
+ reg_fec2_supply: regulator-fec2-nvcc {
+ compatible = "regulator-fixed";
+ regulator-name = "fec2_nvcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can01_en: regulator-can01-gen {
+ compatible = "regulator-fixed";
+ regulator-name = "can01-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can2_en: regulator-can2-gen {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can01_stby: regulator-can01-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can01-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can01_en>;
+ };
+
+ reg_can2_stby: regulator-can2-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_can2_en>;
+ };
+
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ bt_sco_codec: audio-codec-bt {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <1>;
+ };
+
+ sound-bt-sco {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "bt-sco-audio";
+ simple-audio-card,format = "dsp_a";
+ simple-audio-card,bitclock-inversion;
+ simple-audio-card,frame-master = <&btcpu>;
+ simple-audio-card,bitclock-master = <&btcpu>;
+
+ btcpu: simple-audio-card,cpu {
+ sound-dai = <&sai0>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&bt_sco_codec 1>;
+ };
+ };
+
+ sound-wm8960 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai1>;
+ audio-codec = <&wm8960>;
+ hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
+ audio-routing = "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Mic Jack",
+ "Mic Jack", "MICB";
+ };
};
&adc0 {
@@ -55,6 +142,78 @@
status = "okay";
};
+&amix {
+ status = "okay";
+};
+
+&asrc0 {
+ fsl,asrc-rate = <48000>;
+ status = "okay";
+};
+
+&cm41_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cm41_i2c>;
+ status = "okay";
+
+ pca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&cm41_intmux {
+ status = "okay";
+};
+
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ accelerometer@19 {
+ compatible = "st,lsm303agr-accel";
+ reg = <0x19>;
+ };
+
+ gyrometer@20 {
+ compatible = "nxp,fxas21002c";
+ reg = <0x20>;
+ };
+
+ light-sensor@44 {
+ compatible = "isil,isl29023";
+ reg = <0x44>;
+ interrupt-parent = <&lsio_gpio4>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gyrometer@69 {
+ compatible = "st,l3g4200d-gyro";
+ reg = <0x69>;
+ };
+};
+
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
@@ -65,8 +224,44 @@
scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ wm8960: audio-codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "mclk";
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&mclkout0_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
+ wlf,shared-lrclk;
+ wlf,hp-cfg = <2 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_can01_stby>;
+ status = "okay";
};
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can01_stby>;
+ status = "okay";
+};
+
+&flexcan3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan3>;
+ xceiver-supply = <®_can2_stby>;
+ status = "okay";
+};
+
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@@ -100,6 +295,14 @@
};
};
+&lsio_mu5 {
+ status = "okay";
+};
+
+&lsio_mu6 {
+ status = "okay";
+};
+
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
@@ -140,6 +343,19 @@
};
};
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <ðphy1>;
+ phy-supply = <®_fec2_supply>;
+ nvmem-cells = <&fec_mac1>;
+ nvmem-cell-names = "mac-address";
+ rx-internal-delay-ps = <2000>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -160,7 +376,71 @@
status = "okay";
};
+&sai0 {
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai0_lpcg IMX_LPCG_CLK_4>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai0>;
+ status = "okay";
+};
+
+&sai1 {
+ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai1_lpcg IMX_LPCG_CLK_4>;
+ assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ status = "okay";
+};
+
+&sai6 {
+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai6_lpcg IMX_LPCG_CLK_4>;
+ assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
+&sai7 {
+ assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
+ <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
+ <&sai7_lpcg IMX_LPCG_CLK_4>;
+ assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
+ fsl,sai-asynchronous;
+ status = "okay";
+};
+
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
+ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
+ >;
+ };
+
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
+ IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
@@ -181,6 +461,13 @@
>;
};
+ pinctrl_cm41_i2c: cm41i2cgrp {
+ fsl,pins = <
+ IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c
+ IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
@@ -235,6 +522,45 @@
>;
};
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
+ IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
+ IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
+ IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
+ IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
+ IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
+ IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
+ IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
+ IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
+ IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
+ IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
+ IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan0grp {
+ fsl,pins = <
+ IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21
+ IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan1grp {
+ fsl,pins = <
+ IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21
+ IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21
+ >;
+ };
+
+ pinctrl_flexcan3: flexcan3grp {
+ fsl,pins = <
+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21
+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21
+ >;
+ };
+
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
@@ -256,6 +582,24 @@
>;
};
+ pinctrl_sai0: sai0grp {
+ fsl,pins = <
+ IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c
+ IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c
+ IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c
+ IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040
+ IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040
+ IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060
+ IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
diff --git a/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi
new file mode 100644
index 0000000..3036af4
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-audio.dtsi
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/delete-node/ &acm;
+/delete-node/ &sai4;
+/delete-node/ &sai5;
+/delete-node/ &sai4_lpcg;
+/delete-node/ &sai5_lpcg;
+
+&amix {
+ dais = <&sai6>, <&sai7>;
+};
+
+&asrc0 {
+ clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
+ <&asrc0_lpcg IMX_LPCG_CLK_2>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_ASRC_0>;
+};
+
+&asrc0_lpcg {
+ clocks = <&audio_ipg_clk>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
+ clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk";
+};
+
+&asrc1 {
+ clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>,
+ <&asrc1_lpcg IMX_LPCG_CLK_2>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
+ <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_ASRC_1>;
+};
+
+&asrc1_lpcg {
+ clocks = <&audio_ipg_clk>, <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
+ clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk";
+};
+
+&audio_subsys {
+
+ sai4: sai@59080000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59080000 0x10000>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai4_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai4_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx";
+ dmas = <&edma0 18 0 1>;
+ fsl,dataline = <0 0xf 0x0>;
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5: sai@59090000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59090000 0x10000>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai5_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai5_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma0 19 0 0>;
+ fsl,dataline = <0 0x0 0xf>;
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ sai4_lpcg: clock-controller@59480000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59480000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_4>;
+ status = "disabled";
+ };
+
+ sai5_lpcg: clock-controller@59490000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59490000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_5>;
+ status = "disabled";
+ };
+
+ esai1: esai@59810000 {
+ compatible = "fsl,imx8qm-esai";
+ reg = <0x59810000 0x10000>;
+ interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&esai1_lpcg IMX_LPCG_CLK_0>,
+ <&esai1_lpcg IMX_LPCG_CLK_4>,
+ <&esai1_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>;
+ clock-names = "core", "extal", "fsys", "spba";
+ dmas = <&edma1 6 0 1>, <&edma1 7 0 0>;
+ dma-names = "rx", "tx";
+ power-domains = <&pd IMX_SC_R_ESAI_1>;
+ status = "disabled";
+ };
+
+ sai6: sai@59820000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59820000 0x10000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai6_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai6_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_6>;
+ status = "disabled";
+ };
+
+ sai7: sai@59830000 {
+ compatible = "fsl,imx8qm-sai";
+ reg = <0x59830000 0x10000>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sai7_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai7_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx";
+ dmas = <&edma1 10 0 0>;
+ power-domains = <&pd IMX_SC_R_SAI_7>;
+ status = "disabled";
+ };
+
+ esai1_lpcg: clock-controller@59c10000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c10000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ESAI_1>;
+ };
+
+ sai6_lpcg: clock-controller@59c20000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_6>;
+ };
+
+ sai7_lpcg: clock-controller@59c30000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x59c30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>,
+ <&audio_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SAI_7>;
+ };
+
+ acm: acm@59e00000 {
+ compatible = "fsl,imx8qm-acm";
+ reg = <0x59e00000 0x1d0000>;
+ #clock-cells = <1>;
+ power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
+ <&pd IMX_SC_R_AUDIO_CLK_1>,
+ <&pd IMX_SC_R_MCLK_OUT_0>,
+ <&pd IMX_SC_R_MCLK_OUT_1>,
+ <&pd IMX_SC_R_AUDIO_PLL_0>,
+ <&pd IMX_SC_R_AUDIO_PLL_1>,
+ <&pd IMX_SC_R_ASRC_0>,
+ <&pd IMX_SC_R_ASRC_1>,
+ <&pd IMX_SC_R_ESAI_0>,
+ <&pd IMX_SC_R_ESAI_1>,
+ <&pd IMX_SC_R_SAI_0>,
+ <&pd IMX_SC_R_SAI_1>,
+ <&pd IMX_SC_R_SAI_2>,
+ <&pd IMX_SC_R_SAI_3>,
+ <&pd IMX_SC_R_SAI_4>,
+ <&pd IMX_SC_R_SAI_5>,
+ <&pd IMX_SC_R_SAI_6>,
+ <&pd IMX_SC_R_SAI_7>,
+ <&pd IMX_SC_R_SPDIF_0>,
+ <&pd IMX_SC_R_SPDIF_1>,
+ <&pd IMX_SC_R_MQS_0>;
+ clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_rec1_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
+ <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
+ <&clk_mlb_clk>,
+ <&clk_hdmi_rx_mclk>,
+ <&clk_ext_aud_mclk0>,
+ <&clk_ext_aud_mclk1>,
+ <&clk_esai0_rx_clk>,
+ <&clk_esai0_rx_hf_clk>,
+ <&clk_esai0_tx_clk>,
+ <&clk_esai0_tx_hf_clk>,
+ <&clk_esai1_rx_clk>,
+ <&clk_esai1_rx_hf_clk>,
+ <&clk_esai1_tx_clk>,
+ <&clk_esai1_tx_hf_clk>,
+ <&clk_spdif0_rx>,
+ <&clk_spdif0_rx>,
+ <&clk_sai0_rx_bclk>,
+ <&clk_sai0_tx_bclk>,
+ <&clk_sai1_rx_bclk>,
+ <&clk_sai1_tx_bclk>,
+ <&clk_sai2_rx_bclk>,
+ <&clk_sai3_rx_bclk>,
+ <&clk_sai4_rx_bclk>,
+ <&clk_sai5_rx_bclk>,
+ <&clk_sai6_rx_bclk>;
+ clock-names = "aud_rec_clk0_lpcg_clk",
+ "aud_rec_clk1_lpcg_clk",
+ "aud_pll_div_clk0_lpcg_clk",
+ "aud_pll_div_clk1_lpcg_clk",
+ "mlb_clk",
+ "hdmi_rx_mclk",
+ "ext_aud_mclk0",
+ "ext_aud_mclk1",
+ "esai0_rx_clk",
+ "esai0_rx_hf_clk",
+ "esai0_tx_clk",
+ "esai0_tx_hf_clk",
+ "esai1_rx_clk",
+ "esai1_rx_hf_clk",
+ "esai1_tx_clk",
+ "esai1_tx_hf_clk",
+ "spdif0_rx",
+ "spdif1_rx",
+ "sai0_rx_bclk",
+ "sai0_tx_bclk",
+ "sai1_rx_bclk",
+ "sai1_tx_bclk",
+ "sai2_rx_bclk",
+ "sai3_rx_bclk",
+ "sai4_rx_bclk",
+ "sai5_tx_bclk",
+ "sai6_rx_bclk";
+ };
+};
+
+&dsp_lpcg {
+ status = "disabled";
+};
+
+&dsp_ram_lpcg {
+ status = "disabled";
+};
+
+/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */
+&edma0{
+ reg = <0x591f0000 0x150000>;
+ dma-channels = <20>;
+ dma-channel-mask = <0>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
+ <&pd IMX_SC_R_DMA_2_CH1>,
+ <&pd IMX_SC_R_DMA_2_CH2>,
+ <&pd IMX_SC_R_DMA_2_CH3>,
+ <&pd IMX_SC_R_DMA_2_CH4>,
+ <&pd IMX_SC_R_DMA_2_CH5>,
+ <&pd IMX_SC_R_DMA_2_CH6>,
+ <&pd IMX_SC_R_DMA_2_CH7>,
+ <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>,
+ <&pd IMX_SC_R_DMA_2_CH16>,
+ <&pd IMX_SC_R_DMA_2_CH17>,
+ <&pd IMX_SC_R_DMA_2_CH18>,
+ <&pd IMX_SC_R_DMA_2_CH19>;
+};
+
+/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */
+&edma1{
+ reg = <0x599f0000 0xc0000>;
+ dma-channels = <11>;
+ dma-channel-mask = <0xc0>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
+ <&pd IMX_SC_R_DMA_3_CH1>,
+ <&pd IMX_SC_R_DMA_3_CH2>,
+ <&pd IMX_SC_R_DMA_3_CH3>,
+ <&pd IMX_SC_R_DMA_3_CH4>,
+ <&pd IMX_SC_R_DMA_3_CH5>,
+ <&pd IMX_SC_R_DMA_3_CH6>,
+ <&pd IMX_SC_R_DMA_3_CH7>,
+ <&pd IMX_SC_R_DMA_3_CH8>,
+ <&pd IMX_SC_R_DMA_3_CH9>,
+ <&pd IMX_SC_R_DMA_3_CH10>;
+};
+
+&esai0 {
+ clocks = <&esai0_lpcg IMX_LPCG_CLK_0>,
+ <&esai0_lpcg IMX_LPCG_CLK_4>,
+ <&esai0_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_ESAI_0>;
+};
+
+&esai0_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk";
+};
+
+&mqs0_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk";
+};
+
+&sai0 {
+ clocks = <&sai0_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai0_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_SAI_0>;
+};
+
+&sai0_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk";
+};
+
+&sai1 {
+ clocks = <&sai1_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai1_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_SAI_1>;
+};
+
+&sai1_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk";
+};
+
+&sai2 {
+ clocks = <&sai2_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai2_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_SAI_2>;
+};
+
+&sai2_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk";
+};
+
+&sai3 {
+ clocks = <&sai3_lpcg IMX_LPCG_CLK_0>,
+ <&clk_dummy>,
+ <&sai3_lpcg IMX_LPCG_CLK_4>,
+ <&clk_dummy>,
+ <&clk_dummy>;
+ power-domains = <&pd IMX_SC_R_SAI_3>;
+};
+
+&sai3_lpcg {
+ clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
+ clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk";
+};
+
+&spdif0 {
+ clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */
+ <&clk_dummy>, /* rxtx0 */
+ <&spdif0_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */
+ <&clk_dummy>, /* rxtx2 */
+ <&clk_dummy>, /* rxtx3 */
+ <&clk_dummy>, /* rxtx4 */
+ <&audio_ipg_clk>, /* rxtx5 */
+ <&clk_dummy>, /* rxtx6 */
+ <&clk_dummy>, /* rxtx7 */
+ <&clk_dummy>; /* spba */
+ power-domains = <&pd IMX_SC_R_SPDIF_0>;
+};
+
+&spdif0_lpcg {
+ clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8qm.dtsi b/dts/upstream/src/arm64/freescale/imx8qm.dtsi
index b3d0167..61986e0 100644
--- a/dts/upstream/src/arm64/freescale/imx8qm.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8qm.dtsi
@@ -333,6 +333,21 @@
compatible = "fsl,imx8qxp-sc-rtc";
};
+ ocotp: ocotp {
+ compatible = "fsl,imx8qm-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+
+ fec_mac0: mac@1c4 {
+ reg = <0x1c4 6>;
+ };
+
+ fec_mac1: mac@1c6 {
+ reg = <0x1c6 6>;
+ };
+ };
+
tsens: thermal-sensor {
compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
#thermal-sensor-cells = <1>;
@@ -461,8 +476,95 @@
};
};
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
+
+ clk_esai1_rx_clk: clock-esai1-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai1_rx_clk";
+ };
+
+ clk_esai1_rx_hf_clk: clock-esai1-rx-hf {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai1_rx_hf_clk";
+ };
+
+ clk_esai1_tx_clk: clock-esai1-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai1_tx_clk";
+ };
+
+ clk_esai1_tx_hf_clk: clock-esai1-tx-hf {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "esai1_tx_hf_clk";
+ };
+
+ clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "hdmi-rx-mclk";
+ };
+
+ clk_mlb_clk: clock-mlb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "mlb_clk";
+ };
+
+ clk_sai5_rx_bclk: clock-sai5-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai5_rx_bclk";
+ };
+
+ clk_sai5_tx_bclk: clock-sai5-tx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai5_tx_bclk";
+ };
+
+ clk_sai6_rx_bclk: clock-sai6-rx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai6_rx_bclk";
+ };
+
+ clk_sai6_tx_bclk: clock-sai6-tx-bclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "sai6_tx_bclk";
+ };
+
+ clk_spdif1_rx: clock-spdif1-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "spdif1_rx";
+ };
+
/* sorted in register address */
+ #include "imx8-ss-cm41.dtsi"
+ #include "imx8-ss-audio.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
@@ -473,3 +575,4 @@
#include "imx8qm-ss-dma.dtsi"
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"
+#include "imx8qm-ss-audio.dtsi"
diff --git a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
index cee13e5..936ba5e 100644
--- a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
+++ b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
@@ -63,6 +63,7 @@
};
&dsp {
+ memory-region = <&dsp_reserved>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
index bd98eff..a15987f 100644
--- a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
@@ -97,89 +97,6 @@
status = "okay";
};
-&mu1 {
- status = "okay";
-};
-
-&mu2 {
- status = "okay";
-};
-
-&lpi2c3 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpi2c3>;
- status = "okay";
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x50>;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- data-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- op-sink-microwatt = <15000000>;
- self-powered;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
- };
- };
-
- ptn5110_2: tcpc@51 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x51>;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
- typec2_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- data-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- op-sink-microwatt = <15000000>;
- self-powered;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec2_dr_sw: endpoint {
- remote-endpoint = <&usb2_drd_sw>;
- };
- };
- };
- };
- };
-};
-
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
@@ -228,81 +145,6 @@
};
};
-&lpuart1 { /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&lpuart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart5>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- usb-role-switch;
- disable-over-current;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- status = "okay";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usbotg2 {
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- usb-role-switch;
- disable-over-current;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- status = "okay";
-
- port {
- usb2_drd_sw: endpoint {
- remote-endpoint = <&typec2_dr_sw>;
- };
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
- no-mmc;
-};
-
-&wdog3 {
- status = "okay";
-};
-
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -402,11 +244,79 @@
};
&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ ptn5110_2: tcpc@51 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x51>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec2_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec2_dr_sw: endpoint {
+ remote-endpoint = <&usb2_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
@@ -415,6 +325,89 @@
};
};
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb2_drd_sw: endpoint {
+ remote-endpoint = <&typec2_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+ no-mmc;
+};
+
+&wdog3 {
+ status = "okay";
+};
+
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
diff --git a/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
new file mode 100644
index 0000000..950dece
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx93.dtsi"
+
+/ {
+ model = "NXP i.MX93 9x9 Quick Start Board";
+ compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4010000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@2021e000 {
+ reg = <0 0x2021e000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "VREF_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_rpi_3v3: regulator-rpi {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_RPI_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2237500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ no-mmc;
+ status = "okay";
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
index af795ec..852dd3d 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
@@ -303,6 +303,32 @@
reg = <0x1c>;
};
+ ptn5110: usb-typec@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "X17";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ typec-power-opmode = "default";
+ pd-disable;
+ self-powered;
+
+ port {
+ typec_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+ };
+
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
@@ -371,18 +397,6 @@
"WLAN_PERST#", "12V_EN";
/*
- * Controls the on board USB Hub reset which is low
- * active as reset signal. The output-low states, the
- * signal is inactive, e.g. no reset
- */
- usb-reset-hog {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "USB_RESET#";
- };
-
- /*
* Controls the WiFi card PD pin which is low active
* as power down signal. The output-high states, the signal
* is active, e.g. card is powered down
@@ -492,6 +506,41 @@
status = "okay";
};
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ typec_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb424,2517";
+ reg = <1>;
+ reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3v3>;
+ };
+};
+
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
index eb3f4cf..e2ee9f5 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
@@ -252,6 +252,32 @@
reg = <0x1c>;
};
+ ptn5110: usb-typec@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "X17";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ typec-power-opmode = "default";
+ pd-disable;
+ self-powered;
+
+ port {
+ typec_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+ };
+
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
@@ -433,12 +459,47 @@
pinctrl-0 = <&pinctrl_tpm5>;
};
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ typec_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb424,2517";
+ reg = <1>;
+ reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
+ vdd-supply = <®_3v3>;
+ };
+};
+
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi b/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi
index 9d2328c..72a9a5d 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352.dtsi
@@ -19,7 +19,7 @@
linux,cma {
compatible = "shared-dma-pool";
reusable;
- alloc-ranges = <0 0x60000000 0 0x40000000>;
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
@@ -75,6 +75,12 @@
spi-max-frequency = <62000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
@@ -150,6 +156,7 @@
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/freescale/imx93.dtsi b/dts/upstream/src/arm64/freescale/imx93.dtsi
index 4a3f423..a099302 100644
--- a/dts/upstream/src/arm64/freescale/imx93.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx93.dtsi
@@ -1105,7 +1105,7 @@
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
- snps,clk-csr = <0>;
+ snps,clk-csr = <6>;
nvmem-cells = <ð_mac2>;
nvmem-cell-names = "mac-address";
status = "disabled";
diff --git a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
new file mode 100644
index 0000000..d14a54a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include "imx95.dtsi"
+
+/ {
+ model = "NXP i.MX95 19X19 board";
+ compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
+
+ aliases {
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ reg_m2_pwr: regulator-m2-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "M.2-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_pcie0: regulator-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_WLAN_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_m2_pwr>;
+ gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_slot_pwr: regulator-slot-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIe slot-power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VDD_SD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&lpi2c7 {
+ clock-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c7>;
+ status = "okay";
+
+ i2c7_pcal6524: i2c7-gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&mu7 {
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-0 = <&pinctrl_pcie0>;
+ pinctrl-names = "default";
+ reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-0 = <&pinctrl_pcie1>;
+ pinctrl-names = "default";
+ reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_slot_pwr>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c7: lpi2c7grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx95-clock.h b/dts/upstream/src/arm64/freescale/imx95-clock.h
new file mode 100644
index 0000000..e1f9120
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx95-clock.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __CLOCK_IMX95_H
+#define __CLOCK_IMX95_H
+
+/* The index should match i.MX95 SCMI Firmware */
+#define IMX95_CLK_32K 1
+#define IMX95_CLK_24M 2
+#define IMX95_CLK_FRO 3
+#define IMX95_CLK_SYSPLL1_VCO 4
+#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5
+#define IMX95_CLK_SYSPLL1_PFD0 6
+#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7
+#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8
+#define IMX95_CLK_SYSPLL1_PFD1 9
+#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10
+#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11
+#define IMX95_CLK_SYSPLL1_PFD2 12
+#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13
+#define IMX95_CLK_AUDIOPLL1_VCO 14
+#define IMX95_CLK_AUDIOPLL1 15
+#define IMX95_CLK_AUDIOPLL2_VCO 16
+#define IMX95_CLK_AUDIOPLL2 17
+#define IMX95_CLK_VIDEOPLL1_VCO 18
+#define IMX95_CLK_VIDEOPLL1 19
+#define IMX95_CLK_RESERVED20 20
+#define IMX95_CLK_RESERVED21 21
+#define IMX95_CLK_RESERVED22 22
+#define IMX95_CLK_RESERVED23 23
+#define IMX95_CLK_ARMPLL_VCO 24
+#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25
+#define IMX95_CLK_ARMPLL_PFD0 26
+#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27
+#define IMX95_CLK_ARMPLL_PFD1 28
+#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29
+#define IMX95_CLK_ARMPLL_PFD2 30
+#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31
+#define IMX95_CLK_ARMPLL_PFD3 32
+#define IMX95_CLK_DRAMPLL_VCO 33
+#define IMX95_CLK_DRAMPLL 34
+#define IMX95_CLK_HSIOPLL_VCO 35
+#define IMX95_CLK_HSIOPLL 36
+#define IMX95_CLK_LDBPLL_VCO 37
+#define IMX95_CLK_LDBPLL 38
+#define IMX95_CLK_EXT1 39
+#define IMX95_CLK_EXT2 40
+
+#define IMX95_CCM_NUM_CLK_SRC 41
+
+#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0)
+#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1)
+#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2)
+#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3)
+#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4)
+#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5)
+#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6)
+#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7)
+#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8)
+#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9)
+#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10)
+#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11)
+#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12)
+#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13)
+#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14)
+#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15)
+#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16)
+#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17)
+#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18)
+#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19)
+#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20)
+#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21)
+#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22)
+#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23)
+#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24)
+#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25)
+#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26)
+#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27)
+#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28)
+#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29)
+#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30)
+#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31)
+#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32)
+#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33)
+#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34)
+#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35)
+#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36)
+#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37)
+#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38)
+#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39)
+#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40)
+#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41)
+#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42)
+#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43)
+#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44)
+#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45)
+#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46)
+#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47)
+#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48)
+#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49)
+#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50)
+#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51)
+#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52)
+#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53)
+#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54)
+#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55)
+#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56)
+#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57)
+#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58)
+#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59)
+#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60)
+#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61)
+#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62)
+#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63)
+#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64)
+#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65)
+#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66)
+#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67)
+#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68)
+#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69)
+#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70)
+#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71)
+#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72)
+#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73)
+#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74)
+#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75)
+#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76)
+#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77)
+#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78)
+#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79)
+#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80)
+#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81)
+#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82)
+#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83)
+#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84)
+#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85)
+#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86)
+#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87)
+#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88)
+#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89)
+#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90)
+#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91)
+#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92)
+#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93)
+#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94)
+#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95)
+#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96)
+#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97)
+#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98)
+#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99)
+#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100)
+#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101)
+#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102)
+#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103)
+#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104)
+#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105)
+#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106)
+#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107)
+#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108)
+#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109)
+#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110)
+#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111)
+#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112)
+#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113)
+#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114)
+#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115)
+#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116)
+#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117)
+#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118)
+#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119)
+#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120)
+#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121)
+#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122)
+#define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + 0)
+#define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + 1)
+#define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + 2)
+#define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + 3)
+#define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + 4)
+#define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + 5)
+#define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + 6)
+#define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7)
+#define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8)
+#define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9)
+
+#endif /* __CLOCK_IMX95_H */
diff --git a/dts/upstream/src/arm64/freescale/imx95-pinfunc.h b/dts/upstream/src/arm64/freescale/imx95-pinfunc.h
new file mode 100644
index 0000000..9f614ee
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx95-pinfunc.h
@@ -0,0 +1,865 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DTS_IMX95_PINFUNC_H
+#define __DTS_IMX95_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00
+#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00
+#define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00
+#define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00
+#define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00
+#define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00
+#define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00
+
+#define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00
+#define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00
+#define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00
+#define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x0004 0x0208 0x0000 0x05 0x00
+#define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0208 0x0000 0x06 0x00
+
+#define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x020C 0x060C 0x00 0x00
+#define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x0008 0x020C 0x044C 0x02 0x00
+#define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x0008 0x020C 0x0460 0x04 0x00
+#define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x0008 0x020C 0x0000 0x05 0x00
+#define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x020C 0x056C 0x06 0x00
+
+#define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x0210 0x0000 0x00 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x0210 0x0000 0x01 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x000C 0x0210 0x0000 0x02 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x0210 0x0444 0x03 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x000C 0x0210 0x0464 0x04 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x000C 0x0210 0x0000 0x05 0x00
+#define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x0210 0x0574 0x06 0x00
+
+#define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x0010 0x0214 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x0214 0x0504 0x11 0x00
+#define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0214 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0214 0x0574 0x05 0x01
+#define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0214 0x0514 0x16 0x00
+#define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x0010 0x0214 0x0468 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x0014 0x0218 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x0218 0x0500 0x11 0x00
+#define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0218 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0218 0x0570 0x05 0x01
+#define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0218 0x0510 0x16 0x00
+#define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x0014 0x0218 0x046C 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x0018 0x021C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x021C 0x050C 0x11 0x00
+#define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x021C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x021C 0x056C 0x05 0x01
+#define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x021C 0x051C 0x16 0x00
+#define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x0018 0x021C 0x0470 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x001C 0x0220 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x0220 0x0508 0x11 0x00
+#define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x0220 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x0220 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x0220 0x0518 0x16 0x00
+#define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x001C 0x0220 0x0474 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x0020 0x0224 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0224 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0224 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO04__CAN4_TX 0x0020 0x0224 0x0000 0x03 0x00
+#define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0224 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0224 0x0580 0x05 0x01
+#define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0224 0x051C 0x16 0x01
+#define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x0020 0x0224 0x0478 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x0024 0x0228 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0228 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0024 0x0228 0x040C 0x02 0x01
+#define IMX95_PAD_GPIO_IO05__CAN4_RX 0x0024 0x0228 0x044C 0x03 0x01
+#define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0228 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0228 0x057C 0x05 0x01
+#define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0228 0x0518 0x16 0x01
+#define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x0024 0x0228 0x047C 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x0028 0x022C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x022C 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0028 0x022C 0x0410 0x02 0x01
+#define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x022C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x022C 0x0578 0x05 0x01
+#define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x022C 0x0524 0x16 0x00
+#define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x0028 0x022C 0x0480 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x002C 0x0230 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x0230 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x0230 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x0230 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x0230 0x0520 0x16 0x00
+#define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x002C 0x0230 0x0484 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x0030 0x0234 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0234 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0234 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0234 0x0588 0x05 0x01
+#define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0234 0x0524 0x16 0x01
+#define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x0030 0x0234 0x0488 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x0034 0x0238 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0238 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0238 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0238 0x0584 0x05 0x01
+#define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0238 0x0520 0x16 0x01
+#define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x0034 0x0238 0x048C 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x0038 0x023C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x023C 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x023C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x023C 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x023C 0x052C 0x16 0x00
+#define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x0038 0x023C 0x0490 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x003C 0x0240 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x0240 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x0240 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x0240 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x0240 0x0528 0x16 0x00
+#define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x003C 0x0240 0x0494 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x0040 0x0244 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0244 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0040 0x0244 0x0414 0x02 0x00
+#define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x0040 0x0244 0x0498 0x03 0x00
+#define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0244 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0244 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0244 0x052C 0x16 0x01
+#define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x0244 0x0590 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x0044 0x0248 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0248 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x0044 0x0248 0x0418 0x02 0x00
+#define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0248 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0248 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0248 0x0528 0x16 0x01
+#define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x0044 0x0248 0x049C 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x0048 0x024C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x024C 0x055C 0x01 0x01
+#define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x024C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x024C 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x024C 0x0568 0x06 0x01
+#define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x0048 0x024C 0x04A0 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x004C 0x0250 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x0250 0x0558 0x01 0x01
+#define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x0250 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x0250 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x0250 0x0564 0x06 0x01
+#define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x004C 0x0250 0x04A4 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x0050 0x0254 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0254 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0050 0x0254 0x0414 0x02 0x01
+#define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0254 0x0554 0x04 0x01
+#define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0254 0x0538 0x05 0x01
+#define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0254 0x0560 0x06 0x01
+#define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x0050 0x0254 0x04A8 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x0054 0x0258 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0258 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0258 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0258 0x0534 0x05 0x01
+#define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0258 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x0054 0x0258 0x04AC 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x0058 0x025C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x025C 0x058C 0x01 0x00
+#define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x025C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x025C 0x0530 0x05 0x01
+#define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x025C 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x0058 0x025C 0x04B0 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x005C 0x0260 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x0260 0x0590 0x01 0x01
+#define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x005C 0x0260 0x0418 0x02 0x01
+#define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x005C 0x0260 0x04B4 0x03 0x00
+#define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x0260 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x0260 0x0540 0x05 0x01
+#define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x0260 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x005C 0x0260 0x0000 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x0060 0x0264 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x0060 0x0264 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0060 0x0264 0x040C 0x02 0x02
+#define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0264 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0264 0x0544 0x05 0x01
+#define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0264 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x0060 0x0264 0x04B8 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x0064 0x0268 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x0064 0x0268 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0268 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x0064 0x0268 0x04BC 0x03 0x00
+#define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0268 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0268 0x053C 0x05 0x01
+#define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0268 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0268 0x058C 0x07 0x01
+
+#define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x0068 0x026C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x026C 0x05C8 0x01 0x00
+#define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x026C 0x0454 0x02 0x02
+#define IMX95_PAD_GPIO_IO22__CAN5_TX 0x0068 0x026C 0x0000 0x03 0x00
+#define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x026C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x026C 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x026C 0x0514 0x16 0x01
+#define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x0068 0x026C 0x04C0 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x006C 0x0270 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x0270 0x05CC 0x01 0x00
+#define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x0270 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO23__CAN5_RX 0x006C 0x0270 0x0450 0x03 0x00
+#define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x0270 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x0270 0x0510 0x16 0x01
+#define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x006C 0x0270 0x04C4 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x0070 0x0274 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0274 0x05D0 0x01 0x00
+#define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0274 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0274 0x0000 0x05 0x00
+#define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0274 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x0070 0x0274 0x04C8 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x0074 0x0278 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0278 0x05D4 0x01 0x00
+#define IMX95_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0278 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0278 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0278 0x060C 0x05 0x01
+#define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0278 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x0074 0x0278 0x04CC 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x0078 0x027C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x027C 0x05D8 0x01 0x00
+#define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0078 0x027C 0x0410 0x02 0x02
+#define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x0078 0x027C 0x0458 0x03 0x01
+#define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x027C 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x027C 0x0610 0x05 0x01
+#define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x027C 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x027C 0x0000 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x007C 0x0280 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x0280 0x05DC 0x01 0x00
+#define IMX95_PAD_GPIO_IO27__CAN2_RX 0x007C 0x0280 0x0444 0x02 0x02
+#define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x0280 0x0000 0x04 0x00
+#define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x0280 0x0614 0x05 0x01
+#define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x0280 0x0000 0x06 0x00
+#define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x007C 0x0280 0x045C 0x07 0x01
+
+#define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x0080 0x0284 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0284 0x0504 0x11 0x01
+#define IMX95_PAD_GPIO_IO28__CAN3_TX 0x0080 0x0284 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x0080 0x0284 0x0000 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x0084 0x0288 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0288 0x0500 0x11 0x01
+#define IMX95_PAD_GPIO_IO29__CAN3_RX 0x0084 0x0288 0x0448 0x02 0x01
+#define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x0084 0x0288 0x0000 0x07 0x00
+
+#define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x0088 0x028C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x0088 0x028C 0x050C 0x11 0x01
+#define IMX95_PAD_GPIO_IO30__CAN5_TX 0x0088 0x028C 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x0088 0x028C 0x0460 0x07 0x01
+
+#define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x008C 0x0290 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x008C 0x0290 0x0508 0x11 0x01
+#define IMX95_PAD_GPIO_IO31__CAN5_RX 0x008C 0x0290 0x0450 0x02 0x01
+#define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x008C 0x0290 0x0464 0x07 0x01
+
+#define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x0090 0x0294 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x0294 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x0090 0x0294 0x0580 0x02 0x00
+#define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x0090 0x0294 0x0538 0x04 0x00
+
+#define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x0094 0x0298 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x0094 0x0298 0x057C 0x02 0x00
+#define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x0094 0x0298 0x0534 0x04 0x00
+
+#define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x0098 0x029C 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x0098 0x029C 0x0578 0x02 0x00
+#define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x0098 0x029C 0x0530 0x04 0x00
+
+#define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x009C 0x02A0 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x009C 0x02A0 0x0000 0x01 0x00
+#define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x009C 0x02A0 0x0000 0x02 0x00
+#define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x009C 0x02A0 0x0540 0x04 0x00
+
+#define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00A0 0x02A4 0x0544 0x04 0x00
+#define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00A0 0x02A4 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00A0 0x02A4 0x0588 0x02 0x00
+
+#define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00A4 0x02A8 0x0000 0x00 0x00
+#define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00A4 0x02A8 0x0584 0x02 0x00
+#define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00A4 0x02A8 0x053C 0x04 0x00
+
+#define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00A8 0x02AC 0x0000 0x00 0x00
+#define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00A8 0x02AC 0x0434 0x01 0x00
+#define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00A8 0x02AC 0x0458 0x04 0x00
+#define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00A8 0x02AC 0x0000 0x05 0x00
+
+#define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00AC 0x02B0 0x0000 0x05 0x00
+#define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00AC 0x02B0 0x0000 0x00 0x00
+#define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00AC 0x02B0 0x0000 0x01 0x00
+#define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00AC 0x02B0 0x045C 0x04 0x00
+
+#define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00B0 0x02B4 0x0000 0x00 0x00
+#define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00B0 0x02B4 0x0438 0x01 0x00
+#define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00B0 0x02B4 0x0000 0x02 0x00
+#define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00B0 0x02B4 0x0000 0x04 0x00
+#define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00B0 0x02B4 0x0000 0x05 0x00
+
+#define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00B4 0x02B8 0x0000 0x00 0x00
+#define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00B4 0x02B8 0x0000 0x01 0x00
+#define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00B4 0x02B8 0x0448 0x02 0x00
+#define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00B4 0x02B8 0x0000 0x04 0x00
+#define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00B4 0x02B8 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00B8 0x02BC 0x0424 0x00 0x00
+#define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00B8 0x02BC 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00B8 0x02BC 0x04F8 0x02 0x00
+#define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00B8 0x02BC 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00B8 0x02BC 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00B8 0x02BC 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00BC 0x02C0 0x0428 0x00 0x00
+#define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00BC 0x02C0 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00BC 0x02C0 0x04FC 0x02 0x00
+#define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00BC 0x02C0 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00BC 0x02C0 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00BC 0x02C0 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00C0 0x02C4 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00C0 0x02C4 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00C0 0x02C4 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00C0 0x02C4 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00C0 0x02C4 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00C4 0x02C8 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00C4 0x02C8 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00C4 0x02C8 0x0444 0x02 0x01
+#define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00C4 0x02C8 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00C4 0x02C8 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00C4 0x02C8 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00C8 0x02CC 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00C8 0x02CC 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00C8 0x02CC 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00C8 0x02CC 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00C8 0x02CC 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00C8 0x02CC 0x0000 0x05 0x00
+#define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00C8 0x02CC 0x0000 0x06 0x00
+#define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00C8 0x02CC 0x0000 0x07 0x00
+
+#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00CC 0x02D0 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00CC 0x02D0 0x055C 0x01 0x00
+#define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00CC 0x02D0 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00CC 0x02D0 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00CC 0x02D0 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00D0 0x02D4 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00D0 0x02D4 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00D0 0x02D4 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00D0 0x02D4 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00D0 0x02D4 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00D4 0x02D8 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00D4 0x02D8 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00D4 0x02D8 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00D4 0x02D8 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00D8 0x02DC 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00D8 0x02DC 0x0000 0x01 0x00
+#define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00D8 0x02DC 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00D8 0x02DC 0x0000 0x03 0x00
+#define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00D8 0x02DC 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00D8 0x02DC 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00DC 0x02E0 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00DC 0x02E0 0x042C 0x01 0x00
+#define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00DC 0x02E0 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00DC 0x02E0 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00E0 0x02E4 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00E0 0x02E4 0x0558 0x01 0x00
+#define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00E0 0x02E4 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00E0 0x02E4 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00E0 0x02E4 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00E4 0x02E8 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00E4 0x02E8 0x0554 0x01 0x00
+#define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00E4 0x02E8 0x0000 0x02 0x00
+#define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00E4 0x02E8 0x0548 0x03 0x00
+#define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00E4 0x02E8 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00E4 0x02E8 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00E8 0x02EC 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00E8 0x02EC 0x042C 0x02 0x01
+#define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00E8 0x02EC 0x054C 0x03 0x00
+#define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00E8 0x02EC 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00E8 0x02EC 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00EC 0x02F0 0x0000 0x00 0x00
+#define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00EC 0x02F0 0x0550 0x03 0x00
+#define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00EC 0x02F0 0x0000 0x04 0x00
+#define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00EC 0x02F0 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00F0 0x02F4 0x0424 0x00 0x01
+#define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00F0 0x02F4 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00F0 0x02F4 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00F0 0x02F4 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00F0 0x02F4 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00F4 0x02F8 0x0428 0x00 0x01
+#define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00F4 0x02F8 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00F4 0x02F8 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00F4 0x02F8 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00F4 0x02F8 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00F8 0x02FC 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00F8 0x02FC 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00F8 0x02FC 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00F8 0x02FC 0x0000 0x00 0x00
+
+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00FC 0x0300 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00FC 0x0300 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00FC 0x0300 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00FC 0x0300 0x05A4 0x03 0x00
+#define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00FC 0x0300 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00FC 0x0300 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x0100 0x0304 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x0100 0x0304 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x0100 0x0304 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x0100 0x0304 0x05A0 0x03 0x00
+#define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x0100 0x0304 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x0100 0x0304 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x0100 0x0304 0x0000 0x06 0x00
+
+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0104 0x0308 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x0104 0x0308 0x0568 0x01 0x00
+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x0104 0x0308 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x0104 0x0308 0x0000 0x03 0x00
+#define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x0104 0x0308 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x0104 0x0308 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0104 0x0308 0x0000 0x06 0x00
+
+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0108 0x030C 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x0108 0x030C 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0108 0x030C 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0108 0x030C 0x0000 0x03 0x00
+#define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x0108 0x030C 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x0108 0x030C 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x010C 0x0310 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x010C 0x0310 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x010C 0x0310 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x010C 0x0310 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x010C 0x0310 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x0110 0x0314 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x0110 0x0314 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x0110 0x0314 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x0110 0x0314 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x0110 0x0314 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x0110 0x0314 0x0000 0x06 0x00
+
+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0114 0x0318 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0114 0x0318 0x0430 0x01 0x00
+#define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x0114 0x0318 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x0114 0x0318 0x059C 0x03 0x00
+#define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x0114 0x0318 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x0114 0x0318 0x0000 0x05 0x00
+
+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0118 0x031C 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x0118 0x031C 0x0564 0x01 0x00
+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x0118 0x031C 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x0118 0x031C 0x0594 0x03 0x00
+#define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x0118 0x031C 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x0118 0x031C 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0118 0x031C 0x0000 0x06 0x00
+
+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x011C 0x0320 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x011C 0x0320 0x0454 0x01 0x00
+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x011C 0x0320 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x011C 0x0320 0x0598 0x03 0x00
+#define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x011C 0x0320 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x011C 0x0320 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x011C 0x0320 0x0000 0x06 0x00
+
+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x0120 0x0324 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x0120 0x0324 0x0560 0x01 0x00
+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x0120 0x0324 0x0000 0x02 0x00
+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x0120 0x0324 0x0000 0x03 0x00
+#define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x0120 0x0324 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x0120 0x0324 0x0000 0x05 0x00
+#define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0120 0x0324 0x0430 0x06 0x01
+
+#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0124 0x0328 0x0000 0x00 0x00
+#define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x0124 0x0328 0x0000 0x01 0x00
+#define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x0124 0x0328 0x0454 0x02 0x01
+#define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0124 0x0328 0x0000 0x03 0x00
+#define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x0124 0x0328 0x0000 0x04 0x00
+#define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x0124 0x0328 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x0128 0x032C 0x0488 0x04 0x01
+#define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x0128 0x032C 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x0128 0x032C 0x0000 0x00 0x00
+
+#define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x012C 0x0330 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x012C 0x0330 0x048C 0x04 0x01
+#define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x012C 0x0330 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x0130 0x0334 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x0130 0x0334 0x0490 0x04 0x01
+#define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x0130 0x0334 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x0134 0x0338 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x0134 0x0338 0x0494 0x04 0x01
+#define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x0134 0x0338 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x0138 0x033C 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x0138 0x033C 0x0498 0x04 0x01
+#define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x0138 0x033C 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0138 0x033C 0x0000 0x06 0x00
+
+#define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x013C 0x0340 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x013C 0x0340 0x0000 0x01 0x00
+#define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x013C 0x0340 0x049C 0x04 0x01
+#define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x013C 0x0340 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x0140 0x0344 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0140 0x0344 0x04E4 0x01 0x00
+#define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x0140 0x0344 0x04A0 0x04 0x01
+#define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x0140 0x0344 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x0140 0x0344 0x05FC 0x06 0x00
+
+#define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x0144 0x0348 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0144 0x0348 0x04E8 0x01 0x00
+#define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x0144 0x0348 0x0000 0x02 0x00
+#define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x0144 0x0348 0x04A4 0x04 0x01
+#define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x0144 0x0348 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x0144 0x0348 0x0600 0x06 0x00
+
+#define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x0148 0x034C 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0148 0x034C 0x04EC 0x01 0x00
+#define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x0148 0x034C 0x0000 0x02 0x00
+#define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x0148 0x034C 0x04A8 0x04 0x01
+#define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x0148 0x034C 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x0148 0x034C 0x0604 0x06 0x00
+
+#define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x014C 0x0350 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x014C 0x0350 0x04F0 0x01 0x00
+#define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x014C 0x0350 0x0000 0x02 0x00
+#define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x014C 0x0350 0x04AC 0x04 0x01
+#define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x014C 0x0350 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x014C 0x0350 0x0608 0x06 0x00
+
+#define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x0150 0x0354 0x0000 0x00 0x00
+#define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0150 0x0354 0x04D0 0x01 0x00
+#define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x0150 0x0354 0x04B0 0x04 0x01
+#define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x0150 0x0354 0x0000 0x05 0x00
+#define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x0150 0x0354 0x05E4 0x06 0x00
+
+#define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0154 0x0358 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x0154 0x0358 0x0000 0x01 0x00
+#define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0154 0x0358 0x0550 0x02 0x01
+#define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x0154 0x0358 0x04B4 0x04 0x01
+#define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x0154 0x0358 0x0000 0x05 0x00
+#define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0154 0x0358 0x0420 0x06 0x01
+
+#define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x0158 0x035C 0x05C8 0x00 0x01
+#define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0158 0x035C 0x04F4 0x01 0x00
+#define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x0158 0x035C 0x0000 0x02 0x00
+#define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x0158 0x035C 0x05AC 0x03 0x00
+#define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x0158 0x035C 0x04B8 0x04 0x01
+#define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x0158 0x035C 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_CLK__XSPI_CLK 0x0158 0x035C 0x05E8 0x06 0x00
+
+#define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x015C 0x0360 0x05CC 0x00 0x01
+#define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x015C 0x0360 0x0000 0x01 0x00
+#define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x015C 0x0360 0x0000 0x02 0x00
+#define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x015C 0x0360 0x05BC 0x03 0x00
+#define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x015C 0x0360 0x04BC 0x04 0x01
+#define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x015C 0x0360 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_CMD__XSPI_CS 0x015C 0x0360 0x05E0 0x06 0x00
+
+#define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x0160 0x0364 0x05D0 0x00 0x01
+#define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x0160 0x0364 0x04D4 0x01 0x00
+#define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x0160 0x0364 0x0000 0x02 0x00
+#define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x0160 0x0364 0x05A8 0x03 0x00
+#define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x0160 0x0364 0x04C0 0x04 0x01
+#define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x0160 0x0364 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x0160 0x0364 0x05EC 0x06 0x00
+
+#define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x0164 0x0368 0x05D4 0x00 0x01
+#define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x0164 0x0368 0x04D8 0x01 0x00
+#define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x0164 0x0368 0x05B0 0x02 0x00
+#define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x0164 0x0368 0x0000 0x03 0x00
+#define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x0164 0x0368 0x04C4 0x04 0x01
+#define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x0164 0x0368 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x0164 0x0368 0x05F0 0x06 0x00
+
+#define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x0168 0x036C 0x05D8 0x00 0x01
+#define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x0168 0x036C 0x04DC 0x01 0x00
+#define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x0168 0x036C 0x05B4 0x02 0x00
+#define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x0168 0x036C 0x05C4 0x03 0x00
+#define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x0168 0x036C 0x04C8 0x04 0x01
+#define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x0168 0x036C 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x0168 0x036C 0x05F4 0x06 0x00
+
+#define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x016C 0x0370 0x05DC 0x00 0x01
+#define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x016C 0x0370 0x04E0 0x01 0x00
+#define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x016C 0x0370 0x05B8 0x02 0x00
+#define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x016C 0x0370 0x05C0 0x03 0x00
+#define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x016C 0x0370 0x04CC 0x04 0x01
+#define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x016C 0x0370 0x0000 0x05 0x00
+#define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x016C 0x0370 0x05F8 0x06 0x00
+
+#define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x0170 0x0374 0x04D4 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x0170 0x0374 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x0170 0x0374 0x05A0 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x0170 0x0374 0x0000 0x03 0x00
+#define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x0170 0x0374 0x05EC 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x0170 0x0374 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x0174 0x0378 0x04D8 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x0174 0x0378 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x0174 0x0378 0x05A4 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x0174 0x0378 0x0000 0x03 0x00
+#define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x0174 0x0378 0x05F0 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x0174 0x0378 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x0178 0x037C 0x04DC 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x0178 0x037C 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x0178 0x037C 0x0000 0x02 0x00
+#define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x0178 0x037C 0x05F4 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x0178 0x037C 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x017C 0x0380 0x04E0 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x017C 0x0380 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x017C 0x0380 0x0598 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x017C 0x0380 0x05F8 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x017C 0x0380 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0180 0x0384 0x04E4 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x0180 0x0384 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x0180 0x0384 0x05B0 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x0180 0x0384 0x05FC 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x0180 0x0384 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0184 0x0388 0x04E8 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x0184 0x0388 0x05C4 0x01 0x01
+#define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x0184 0x0388 0x05B4 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0184 0x0388 0x043C 0x03 0x00
+#define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x0184 0x0388 0x0600 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x0184 0x0388 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0188 0x038C 0x04EC 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x0188 0x038C 0x05C0 0x01 0x01
+#define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x0188 0x038C 0x05B8 0x02 0x01
+#define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x0188 0x038C 0x0440 0x03 0x00
+#define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x0188 0x038C 0x0604 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x0188 0x038C 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x018C 0x0390 0x04F0 0x00 0x01
+#define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x018C 0x0390 0x05AC 0x01 0x01
+#define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x018C 0x0390 0x0000 0x02 0x00
+#define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x018C 0x0390 0x0608 0x04 0x01
+#define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x018C 0x0390 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x0190 0x0394 0x04D0 0x00 0x01
+#define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x0190 0x0394 0x05BC 0x01 0x01
+#define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x0190 0x0394 0x0000 0x02 0x00
+#define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0190 0x0394 0x043C 0x03 0x01
+#define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x0190 0x0394 0x05E4 0x04 0x01
+#define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x0190 0x0394 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x0194 0x0398 0x04F4 0x00 0x01
+#define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x0194 0x0398 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x0194 0x0398 0x059C 0x02 0x01
+#define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x0194 0x0398 0x0000 0x03 0x00
+#define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x0194 0x0398 0x05E8 0x04 0x01
+#define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x0194 0x0398 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x0198 0x039C 0x0000 0x00 0x00
+#define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x0198 0x039C 0x0000 0x01 0x00
+#define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0198 0x039C 0x0594 0x02 0x01
+#define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x0198 0x039C 0x0000 0x03 0x00
+#define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x0198 0x039C 0x05E0 0x04 0x01
+#define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x0198 0x039C 0x0000 0x05 0x00
+
+#define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x019C 0x03A0 0x0000 0x00 0x00
+#define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x019C 0x03A0 0x05A8 0x01 0x01
+#define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x019C 0x03A0 0x0000 0x02 0x00
+#define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x019C 0x03A0 0x0440 0x03 0x01
+#define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x019C 0x03A0 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01A0 0x03A4 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01A0 0x03A4 0x0434 0x01 0x01
+#define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01A0 0x03A4 0x04F8 0x02 0x01
+#define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01A0 0x03A4 0x0468 0x04 0x01
+#define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01A0 0x03A4 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01A4 0x03A8 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01A4 0x03A8 0x0000 0x01 0x00
+#define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01A4 0x03A8 0x04FC 0x02 0x01
+#define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01A4 0x03A8 0x046C 0x04 0x01
+#define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01A4 0x03A8 0x0000 0x05 0x00
+#define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01A4 0x03A8 0x0000 0x06 0x00
+
+#define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01A8 0x03AC 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01A8 0x03AC 0x0438 0x01 0x01
+#define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01A8 0x03AC 0x0000 0x02 0x00
+#define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01A8 0x03AC 0x0000 0x03 0x00
+#define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01A8 0x03AC 0x0470 0x04 0x01
+#define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01A8 0x03AC 0x0000 0x05 0x00
+#define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01A8 0x03AC 0x0000 0x06 0x00
+
+#define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01AC 0x03B0 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01AC 0x03B0 0x0000 0x01 0x00
+#define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01AC 0x03B0 0x0000 0x02 0x00
+#define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01AC 0x03B0 0x0474 0x04 0x01
+#define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01AC 0x03B0 0x0000 0x05 0x00
+#define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01AC 0x03B0 0x0000 0x06 0x00
+
+#define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01B0 0x03B4 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01B0 0x03B4 0x0000 0x01 0x00
+#define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01B0 0x03B4 0x0444 0x02 0x03
+#define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01B0 0x03B4 0x0478 0x04 0x01
+#define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01B0 0x03B4 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01B4 0x03B8 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01B4 0x03B8 0x0000 0x01 0x00
+#define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01B4 0x03B8 0x0000 0x02 0x00
+#define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01B4 0x03B8 0x047C 0x04 0x01
+#define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01B4 0x03B8 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01B8 0x03BC 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01B8 0x03BC 0x0548 0x01 0x01
+#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01B8 0x03BC 0x0000 0x02 0x00
+#define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01B8 0x03BC 0x0000 0x03 0x00
+#define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01B8 0x03BC 0x0480 0x04 0x01
+#define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01B8 0x03BC 0x0000 0x05 0x00
+
+#define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01BC 0x03C0 0x0000 0x00 0x00
+#define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01BC 0x03C0 0x054C 0x01 0x01
+#define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01BC 0x03C0 0x0000 0x03 0x00
+#define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01BC 0x03C0 0x0484 0x04 0x01
+#define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01BC 0x03C0 0x0000 0x05 0x00
+
+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01C0 0x03C4 0x0000 0x00 0x00
+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01C0 0x03C4 0x0000 0x01 0x00
+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01C0 0x03C4 0x0000 0x02 0x00
+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01C0 0x03C4 0x0000 0x03 0x00
+#define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01C0 0x03C4 0x0000 0x04 0x00
+#define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01C0 0x03C4 0x0000 0x05 0x00
+
+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01C4 0x03C8 0x0000 0x00 0x00
+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01C4 0x03C8 0x0000 0x01 0x00
+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01C4 0x03C8 0x0000 0x02 0x00
+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01C4 0x03C8 0x0000 0x03 0x00
+#define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01C4 0x03C8 0x0000 0x04 0x00
+#define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01C4 0x03C8 0x0000 0x05 0x00
+
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01C8 0x03CC 0x0000 0x00 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01C8 0x03CC 0x0000 0x01 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01C8 0x03CC 0x0000 0x02 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01C8 0x03CC 0x0000 0x03 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01C8 0x03CC 0x0000 0x04 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01C8 0x03CC 0x0000 0x05 0x00
+#define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01C8 0x03CC 0x0000 0x06 0x00
+
+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01CC 0x03D0 0x0000 0x00 0x00
+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01CC 0x03D0 0x0000 0x02 0x00
+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01CC 0x03D0 0x0000 0x03 0x00
+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01CC 0x03D0 0x0000 0x04 0x00
+#define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01CC 0x03D0 0x0000 0x05 0x00
+
+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01D0 0x03D4 0x0000 0x00 0x00
+#define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01D0 0x03D4 0x0000 0x01 0x00
+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01D0 0x03D4 0x0000 0x02 0x00
+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01D0 0x03D4 0x0000 0x03 0x00
+#define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01D0 0x03D4 0x0000 0x05 0x00
+
+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01D4 0x03D8 0x0000 0x00 0x00
+#define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01D4 0x03D8 0x0000 0x01 0x00
+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01D4 0x03D8 0x0000 0x02 0x00
+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01D4 0x03D8 0x0000 0x03 0x00
+#define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01D4 0x03D8 0x0000 0x05 0x00
+
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01D8 0x03DC 0x0000 0x00 0x00
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01D8 0x03DC 0x0000 0x01 0x00
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01D8 0x03DC 0x0000 0x02 0x00
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01D8 0x03DC 0x0000 0x03 0x00
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01D8 0x03DC 0x041C 0x04 0x00
+#define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01D8 0x03DC 0x0000 0x05 0x00
+
+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01DC 0x03E0 0x0000 0x00 0x00
+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01DC 0x03E0 0x0000 0x01 0x00
+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01DC 0x03E0 0x0000 0x02 0x00
+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01DC 0x03E0 0x0000 0x03 0x00
+#define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01DC 0x03E0 0x0000 0x05 0x00
+
+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01E0 0x03E4 0x0000 0x00 0x00
+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01E0 0x03E4 0x0000 0x01 0x00
+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01E0 0x03E4 0x0000 0x04 0x00
+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01E0 0x03E4 0x0000 0x05 0x00
+#define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01E0 0x03E4 0x0000 0x06 0x00
+
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01E4 0x03E8 0x040C 0x00 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01E4 0x03E8 0x0000 0x01 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01E4 0x03E8 0x0000 0x02 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01E4 0x03E8 0x0000 0x03 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01E4 0x03E8 0x0000 0x04 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01E4 0x03E8 0x0000 0x05 0x00
+#define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01E4 0x03E8 0x0408 0x06 0x00
+
+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01E8 0x03EC 0x0410 0x00 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01E8 0x03EC 0x0000 0x01 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01E8 0x03EC 0x0000 0x02 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01E8 0x03EC 0x0000 0x03 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01E8 0x03EC 0x0000 0x04 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01E8 0x03EC 0x0000 0x05 0x00
+#define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01E8 0x03EC 0x0420 0x06 0x00
+
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01EC 0x03F0 0x0000 0x00 0x00
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01EC 0x03F0 0x0000 0x01 0x00
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01EC 0x03F0 0x0000 0x02 0x00
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01EC 0x03F0 0x0000 0x03 0x00
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01EC 0x03F0 0x0000 0x04 0x00
+#define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01EC 0x03F0 0x0000 0x05 0x00
+
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01F0 0x03F4 0x0000 0x00 0x00
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01F0 0x03F4 0x0000 0x01 0x00
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01F0 0x03F4 0x0000 0x02 0x00
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01F0 0x03F4 0x0000 0x03 0x00
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01F0 0x03F4 0x0408 0x04 0x01
+#define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01F0 0x03F4 0x0000 0x05 0x00
+
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01F4 0x03F8 0x0000 0x00 0x00
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01F4 0x03F8 0x0000 0x01 0x00
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01F4 0x03F8 0x0000 0x02 0x00
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01F4 0x03F8 0x0000 0x03 0x00
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01F4 0x03F8 0x0000 0x04 0x00
+#define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01F4 0x03F8 0x0000 0x05 0x00
+
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01F8 0x03FC 0x0000 0x00 0x00
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01F8 0x03FC 0x041C 0x01 0x01
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01F8 0x03FC 0x0000 0x02 0x00
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01F8 0x03FC 0x0000 0x03 0x00
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01F8 0x03FC 0x0000 0x04 0x00
+#define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01F8 0x03FC 0x0000 0x05 0x00
+
+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01FC 0x0400 0x0000 0x00 0x00
+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01FC 0x0400 0x0000 0x01 0x00
+#define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01FC 0x0400 0x0000 0x05 0x00
+#endif /* __DTS_IMX95_PINFUNC_H */
diff --git a/dts/upstream/src/arm64/freescale/imx95-power.h b/dts/upstream/src/arm64/freescale/imx95-power.h
new file mode 100644
index 0000000..0b7f0bc
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx95-power.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __IMX95_POWER_H__
+#define __IMX95_POWER_H__
+
+#define IMX95_PD_ANA 0
+#define IMX95_PD_AON 1
+#define IMX95_PD_BBSM 2
+#define IMX95_PD_CAMERA 3
+#define IMX95_PD_CCMSRCGPC 4
+#define IMX95_PD_A55C0 5
+#define IMX95_PD_A55C1 6
+#define IMX95_PD_A55C2 7
+#define IMX95_PD_A55C3 8
+#define IMX95_PD_A55C4 9
+#define IMX95_PD_A55C5 10
+#define IMX95_PD_A55P 11
+#define IMX95_PD_DDR 12
+#define IMX95_PD_DISPLAY 13
+#define IMX95_PD_GPU 14
+#define IMX95_PD_HSIO_TOP 15
+#define IMX95_PD_HSIO_WAON 16
+#define IMX95_PD_M7 17
+#define IMX95_PD_NETC 18
+#define IMX95_PD_NOC 19
+#define IMX95_PD_NPU 20
+#define IMX95_PD_VPU 21
+#define IMX95_PD_WAKEUP 22
+
+#define IMX95_PERF_ELE 0
+#define IMX95_PERF_M33 1
+#define IMX95_PERF_WAKEUP 2
+#define IMX95_PERF_M7 3
+#define IMX95_PERF_DRAM 4
+#define IMX95_PERF_HSIO 5
+#define IMX95_PERF_NPU 6
+#define IMX95_PERF_NOC 7
+#define IMX95_PERF_A55 8
+#define IMX95_PERF_GPU 9
+#define IMX95_PERF_VPU 10
+#define IMX95_PERF_CAM 11
+#define IMX95_PERF_DISP 12
+
+#endif
diff --git a/dts/upstream/src/arm64/freescale/imx95.dtsi b/dts/upstream/src/arm64/freescale/imx95.dtsi
new file mode 100644
index 0000000..425272a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx95.dtsi
@@ -0,0 +1,1192 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "imx95-clock.h"
+#include "imx95-pinfunc.h"
+#include "imx95-power.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ A55_2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l2>;
+ };
+
+ A55_3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l3>;
+ };
+
+ A55_4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l4>;
+ };
+
+ A55_5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ power-domains = <&scmi_perf IMX95_PERF_A55>;
+ power-domain-names = "perf";
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_cache_l5>;
+ };
+
+ l2_cache_l0: l2-cache-l0 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l1: l2-cache-l1 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l2: l2-cache-l2 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l3: l2-cache-l3 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l4: l2-cache-l4 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l2_cache_l5: l2-cache-l5 {
+ compatible = "cache";
+ cache-size = <65536>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_cache>;
+ };
+
+ l3_cache: l3-cache {
+ compatible = "cache";
+ cache-size = <524288>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&A55_0>;
+ };
+
+ core1 {
+ cpu = <&A55_1>;
+ };
+
+ core2 {
+ cpu = <&A55_2>;
+ };
+
+ core3 {
+ cpu = <&A55_3>;
+ };
+
+ core4 {
+ cpu = <&A55_4>;
+ };
+
+ core5 {
+ cpu = <&A55_5>;
+ };
+ };
+ };
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ sai1_mclk: clock-sai-mclk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <0>;
+ clock-output-names = "sai1_mclk";
+ };
+
+ sai2_mclk: clock-sai-mclk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <0>;
+ clock-output-names = "sai2_mclk";
+ };
+
+ sai3_mclk: clock-sai-mclk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <0>;
+ clock-output-names = "sai3_mclk";
+ };
+
+ sai4_mclk: clock-sai-mclk4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <0>;
+ clock-output-names = "sai4_mclk";
+ };
+
+ sai5_mclk: clock-sai-mclk5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency= <0>;
+ clock-output-names = "sai5_mclk";
+ };
+
+ osc_24m: clock-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ sram1: sram@204c0000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x204c0000 0x0 0x18000>;
+ ranges = <0x0 0x0 0x204c0000 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>;
+ shmem = <&scmi_buf0>, <&scmi_buf1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_perf: protocol@13 {
+ reg = <0x13>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ scmi_iomuxc: protocol@19 {
+ reg = <0x19>;
+ };
+
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ thermal-zones {
+ a55-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 1>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@48000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x48000000 0 0x10000>,
+ <0 0x48060000 0 0xc0000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ dma-noncoherent;
+ ranges;
+
+ its: msi-controller@48040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0 0x48040000 0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ dma-noncoherent;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aips2: bus@42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x42000000 0x0 0x800000>;
+ ranges = <0x42000000 0x0 0x42000000 0x8000000>,
+ <0x28000000 0x0 0x28000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mu7: mailbox@42430000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42430000 0x10000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@42490000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x42490000 0x10000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+
+ tpm3: pwm@424e0000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x424e0000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm4: pwm@424f0000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x424f0000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_TPM4>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm5: pwm@42500000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42500000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_TPM5>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm6: pwm@42510000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x42510000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_TPM6>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@42530000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42530000 0x10000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C3>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@42540000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42540000 0x10000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C4>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@42550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42550000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI3>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42560000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42560000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI4>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@42570000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42570000 0x1000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART3>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@42580000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42580000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART4>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@42590000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42590000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART5>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart6: serial@425a0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x425a0000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART6>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart7: serial@42690000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42690000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART7>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart8: serial@426a0000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x426a0000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART8>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@426b0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426b0000 0x10000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C5>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@426c0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426c0000 0x10000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C6>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpi2c7: i2c@426d0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426d0000 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C7>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpi2c8: i2c@426e0000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426e0000 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C8>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpspi5: spi@426f0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x426f0000 0x10000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI5>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi6: spi@42700000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42700000 0x10000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI6>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi7: spi@42710000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42710000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI7>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi8: spi@42720000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x42720000 0x10000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI8>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ mu8: mailbox@42730000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x42730000 0x10000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@42800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0 0x42800000 0 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x42800000 0x0 0x42800000 0x800000>;
+
+ usdhc1: mmc@42850000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42850000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX95_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@42860000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42860000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX95_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@428b0000 {
+ compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x428b0000 0x10000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_WAKEUPAXI>,
+ <&scmi_clk IMX95_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>;
+ assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <1>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43810000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 4 32>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43820000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>,
+ <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>;
+ };
+
+ gpio4: gpio@43840000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43840000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>;
+ };
+
+ gpio5: gpio@43850000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x43850000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>;
+ };
+
+ aips1: bus@44000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x44000000 0x0 0x800000>;
+ ranges = <0x44000000 0x0 0x44000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mu1: mailbox@44220000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44220000 0x10000>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ tpm1: pwm@44310000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x44310000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ tpm2: pwm@44320000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x44320000 0x1000>;
+ clocks = <&scmi_clk IMX95_CLK_TPM2>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ lpi2c1: i2c@44340000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44340000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C1>,
+ <&scmi_clk IMX95_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@44350000 {
+ compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44350000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPI2C2>,
+ <&scmi_clk IMX95_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@44360000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44360000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI1>,
+ <&scmi_clk IMX95_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi2: spi@44370000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi";
+ reg = <0x44370000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPSPI2>,
+ <&scmi_clk IMX95_CLK_BUSAON>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@44380000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44380000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44390000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_LPUART2>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ adc1: adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_ADC>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ mu2: mailbox@445b0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445b0000 0x1000>;
+ ranges;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #mbox-cells = <2>;
+
+ sram0: sram@445b1000 {
+ compatible = "mmio-sram";
+ reg = <0x445b1000 0x400>;
+ ranges = <0x0 0x445b1000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ scmi_buf1: scmi-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+
+ };
+
+ mu3: mailbox@445d0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445d0000 0x10000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu4: mailbox@445f0000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x445f0000 0x10000>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu6: mailbox@44630000 {
+ compatible = "fsl,imx95-mu";
+ reg = <0x44630000 0x10000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ mailbox@47320000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47350000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47350000 0x0 0x10000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ /* GPIO1 is under exclusive control of System Manager */
+ gpio1: gpio@47400000 {
+ compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio";
+ reg = <0x0 0x47400000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&scmi_clk IMX95_CLK_M33>,
+ <&scmi_clk IMX95_CLK_M33>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&scmi_iomuxc 0 112 16>;
+ status = "disabled";
+ };
+
+ elemu0: mailbox@47520000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47520000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu1: mailbox@47530000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47530000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu2: mailbox@47540000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47540000 0x0 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu3: mailbox@47550000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ elemu4: mailbox@47560000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47560000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ elemu5: mailbox@47570000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47570000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ aips4: bus@49000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x0 0x49000000 0x0 0x800000>;
+ ranges = <0x49000000 0x0 0x49000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ smmu: iommu@490d0000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x490d0000 0x100000>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+ };
+
+ pcie0: pcie@4c300000 {
+ compatible = "fsl,imx95-pcie";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x60100000 0 0xfe00000>,
+ <0 0x4c360000 0 0x10000>,
+ <0 0x4c340000 0 0x2000>;
+ reg-names = "dbi", "config", "atu", "app";
+ ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
+ <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+ fsl,max-link-speed = <3>;
+ status = "disabled";
+ };
+
+ pcie0_ep: pcie-ep@4c300000 {
+ compatible = "fsl,imx95-pcie-ep";
+ reg = <0 0x4c300000 0 0x10000>,
+ <0 0x4c360000 0 0x1000>,
+ <0 0x4c320000 0 0x1000>,
+ <0 0x4c340000 0 0x2000>,
+ <0 0x4c370000 0 0x10000>,
+ <0x9 0 1 0>;
+ reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@4c380000 {
+ compatible = "fsl,imx95-pcie";
+ reg = <0 0x4c380000 0 0x10000>,
+ <8 0x80100000 0 0xfe00000>,
+ <0 0x4c3e0000 0 0x10000>,
+ <0 0x4c3c0000 0 0x2000>;
+ reg-names = "dbi", "config", "atu", "app";
+ ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
+ <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ num-viewport = <8>;
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+ fsl,max-link-speed = <3>;
+ status = "disabled";
+ };
+
+ pcie1_ep: pcie-ep@4c380000 {
+ compatible = "fsl,imx95-pcie-ep";
+ reg = <0 0x4c380000 0 0x10000>,
+ <0 0x4c3e0000 0 0x1000>,
+ <0 0x4c3a0000 0 0x1000>,
+ <0 0x4c3c0000 0 0x2000>,
+ <0 0x4c3f0000 0 0x10000>,
+ <0xa 0 1 0>;
+ reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ clocks = <&scmi_clk IMX95_CLK_HSIO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+ <&scmi_clk IMX95_CLK_HSIOPLL>,
+ <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+ assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
+ assigned-clock-parents = <0>, <0>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi
index dbd2fc3..65f7b5a 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-0.dtsi
@@ -32,7 +32,7 @@
mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xf1000 0x1000>;
pcsphy6: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi
index 6fc5d25..3f70482 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-10g-1.dtsi
@@ -32,7 +32,7 @@
mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xf3000 0x1000>;
pcsphy7: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi
index 4e02276..78841c1 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-0.dtsi
@@ -31,7 +31,7 @@
mdio@e1000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi
index 0312fa4..1f43fa6 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-1.dtsi
@@ -31,7 +31,7 @@
mdio@e3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi
index af2df07..de0aa01 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-2.dtsi
@@ -31,7 +31,7 @@
mdio@e5000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xe5000 0x1000>;
pcsphy2: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi
index 4ac98dc..6904aa5 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-3.dtsi
@@ -31,7 +31,7 @@
mdio@e7000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xe7000 0x1000>;
pcsphy3: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi
index bd932d8..a3d29d4 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-4.dtsi
@@ -31,7 +31,7 @@
mdio@e9000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xe9000 0x1000>;
pcsphy4: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi
index 7de1c52..01b78c0 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0-1g-5.dtsi
@@ -31,7 +31,7 @@
mdio@eb000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xeb000 0x1000>;
pcsphy5: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/freescale/qoriq-fman3-0.dtsi b/dts/upstream/src/arm64/freescale/qoriq-fman3-0.dtsi
index ae1c2ab..b0390b7 100644
--- a/dts/upstream/src/arm64/freescale/qoriq-fman3-0.dtsi
+++ b/dts/upstream/src/arm64/freescale/qoriq-fman3-0.dtsi
@@ -67,14 +67,14 @@
mdio0: mdio@fc000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xfc000 0x1000>;
};
xmdio0: mdio@fd000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+ compatible = "fsl,fman-memac-mdio";
reg = <0xfd000 0x1000>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/tqma8xx.dtsi b/dts/upstream/src/arm64/freescale/tqma8xx.dtsi
index d98469a..366912b 100644
--- a/dts/upstream/src/arm64/freescale/tqma8xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/tqma8xx.dtsi
@@ -61,12 +61,16 @@
flash0: flash@0 {
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/hisilicon/hi3660.dtsi b/dts/upstream/src/arm64/hisilicon/hi3660.dtsi
index 7e137a8..957a1b4 100644
--- a/dts/upstream/src/arm64/hisilicon/hi3660.dtsi
+++ b/dts/upstream/src/arm64/hisilicon/hi3660.dtsi
@@ -1161,7 +1161,7 @@
};
usb3_otg_bc: usb3_otg_bc@ff200000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd";
reg = <0x0 0xff200000 0x0 0x1000>;
usb_phy: usb-phy {
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
index ad99aef..b31cfa6 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
@@ -106,8 +106,6 @@
&qspi {
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
index 2d70a92..7952c7f 100644
--- a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
+++ b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
@@ -83,8 +83,6 @@
&qspi {
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts b/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
index 63fbc83..56930f2 100644
--- a/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
+++ b/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
@@ -41,7 +41,7 @@
keys {
compatible = "gpio-keys";
- reset {
+ button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
@@ -57,17 +57,17 @@
leds {
compatible = "gpio-leds";
- vpn {
+ led-vpn {
label = "green:vpn";
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-wan {
label = "green:wan";
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
};
- led_power: power {
+ led_power: led-power {
label = "green:power";
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
default-state = "on";
diff --git a/dts/upstream/src/arm64/marvell/cn9130-cf-base.dts b/dts/upstream/src/arm64/marvell/cn9130-cf-base.dts
new file mode 100644
index 0000000..788a5c3
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9130-cf-base.dts
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for SolidRun CN9130 Clearfog Base.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "cn9130.dtsi"
+#include "cn9130-sr-som.dtsi"
+#include "cn9130-cf.dtsi"
+
+/ {
+ model = "SolidRun CN9130 Clearfog Base";
+ compatible = "solidrun,cn9130-clearfog-base",
+ "solidrun,cn9130-sr-som", "marvell,cn9130";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button-0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&cp0_gpio1 31 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ rfkill-m2-gnss {
+ compatible = "rfkill-gpio";
+ label = "m.2 GNSS";
+ radio-type = "gps";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* M.2 is B-keyed, so w-disable is for WWAN */
+ rfkill-m2-wwan {
+ compatible = "rfkill-gpio";
+ label = "m.2 WWAN";
+ radio-type = "wwan";
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* SRDS #3 - SGMII 1GE */
+&cp0_eth1 {
+ phy = <&phy1>;
+ phys = <&cp0_comphy3 1>;
+ phy-mode = "sgmii";
+ status = "okay";
+};
+
+&cp0_eth2_phy {
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link/activity: On/blink (green)
+ * - LED[1]: link is 100/1000Mbps: On (yellow)
+ * - LED[2]: high impedance (floating)
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a61>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
+};
+
+&cp0_gpio1 {
+ sim-select-hog {
+ gpio-hog;
+ gpios = <27 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "sim-select";
+ };
+};
+
+&cp0_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link/activity: On/blink (green)
+ * - LED[1]: link is 100/1000Mbps: On (yellow)
+ * - LED[2]: high impedance (floating)
+ *
+ * Configure LEDs electrical polarity
+ * - on-state: low
+ * - off-state: high (not hi-z, to avoid residual glow)
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a61>,
+ <3 17 0x003f 0x000a>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+&cp0_pinctrl {
+ pinctrl-0 = <&sim_select_pins>;
+ pintrl-names = "default";
+
+ rear_button_pins: cp0-rear-button-pins {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ sim_select_pins: cp0-sim-select-pins {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+};
+
+/*
+ * SRDS #4 - USB 3.0 host on M.2 connector
+ * USB-2.0 Host on Type-A connector
+ */
+&cp0_usb3_1 {
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "comphy", "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&expander0 {
+ m2-full-card-power-off-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-full-card-power-off";
+ };
+
+ m2-reset-hog {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-reset";
+ };
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9130-cf-pro.dts b/dts/upstream/src/arm64/marvell/cn9130-cf-pro.dts
new file mode 100644
index 0000000..a27fe00
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9130-cf-pro.dts
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for SolidRun CN9130 Clearfog Pro.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "cn9130.dtsi"
+#include "cn9130-sr-som.dtsi"
+#include "cn9130-cf.dtsi"
+
+/ {
+ model = "SolidRun CN9130 Clearfog Pro";
+ compatible = "solidrun,cn9130-clearfog-pro",
+ "solidrun,cn9130-sr-som", "marvell,cn9130";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&rear_button_pins>;
+ pinctrl-names = "default";
+
+ button-0 {
+ /* The rear SW3 button */
+ label = "Rear Button";
+ gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+ };
+};
+
+/* SRDS #3 - SGMII 1GE to L2 switch */
+&cp0_eth1 {
+ phys = <&cp0_comphy3 1>;
+ phy-mode = "sgmii";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&cp0_eth2_phy {
+ /*
+ * Configure LEDs default behaviour similar to switch ports:
+ * - LED[0]: link/activity: On/blink (green)
+ * - LED[1]: link is 100/1000Mbps: On (red)
+ * - LED[2]: high impedance (floating)
+ *
+ * Switch port defaults:
+ * - LED0: link/activity: On/blink (green)
+ * - LED1: link is 1000Mbps: On (red)
+ *
+ * Identical configuration is impossible with hardware offload.
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a61>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ label = "LED2";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WAN;
+ label = "LED1";
+ default-state = "keep";
+ };
+ };
+};
+
+&cp0_mdio {
+ ethernet-switch@4 {
+ compatible = "marvell,mv88e6085";
+ reg = <4>;
+ pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ label = "lan5";
+ phy = <&switch0phy0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ label = "LED12";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_LAN;
+ label = "LED11";
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan4";
+ phy = <&switch0phy1>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ label = "LED10";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_LAN;
+ label = "LED9";
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy = <&switch0phy2>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ label = "LED8";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_LAN;
+ label = "LED7";
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan2";
+ phy = <&switch0phy3>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ label = "LED6";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_LAN;
+ label = "LED5";
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@4 {
+ reg = <4>;
+ label = "lan1";
+ phy = <&switch0phy4>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ label = "LED4";
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_LAN;
+ label = "LED3";
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&cp0_eth1>;
+ phy-mode = "sgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet-port@6 {
+ reg = <6>;
+ label = "lan6";
+ phy-mode = "rgmii";
+
+ /*
+ * Because of mdio address conflict the
+ * external phy is not readable.
+ * Force a fixed link instead.
+ */
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ switch0phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ /*
+ * Indirectly configure default behaviour
+ * for port lan6 leds behind external phy.
+ * Internal PHYs are not using page 3,
+ * therefore writing to it is safe.
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a61>;
+ };
+
+ switch0phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+
+ /*
+ * There is an external phy on the switch mdio bus.
+ * Because its mdio address collides with internal phys,
+ * it is not readable.
+ *
+ * mdio-external {
+ * compatible = "marvell,mv88e6xxx-mdio-external";
+ * #address-cells = <1>;
+ * #size-cells = <0>;
+ *
+ * ethernet-phy@1 {
+ * reg = <0x1>;
+ * };
+ * };
+ */
+ };
+};
+
+/* SRDS #4 - miniPCIe (CON2) */
+&cp0_pcie1 {
+ num-lanes = <1>;
+ phys = <&cp0_comphy4 1>;
+ /* dw-pcie inverts internally */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cp0_pinctrl {
+ dsa_clk_pins: cp0-dsa-clk-pins {
+ marvell,pins = "mpp40";
+ marvell,function = "synce1";
+ };
+
+ dsa_pins: cp0-dsa-pins {
+ marvell,pins = "mpp27", "mpp29";
+ marvell,function = "gpio";
+ };
+
+ rear_button_pins: cp0-rear-button-pins {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+
+ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+};
+
+&cp0_spi1 {
+ /* add pin for chip-select 1 on mikrobus */
+ pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
+};
+
+/* USB-2.0 Host on Type-A connector */
+&cp0_usb3_1 {
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&expander0 {
+ /* CON2 */
+ pcie1-0-clkreq-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+
+ /* CON2 */
+ pcie1-0-w-disable-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9130-cf.dtsi b/dts/upstream/src/arm64/marvell/cn9130-cf.dtsi
new file mode 100644
index 0000000..ad0ab34
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9130-cf.dtsi
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for common base of SolidRun CN9130 Clearfog Base and Pro.
+ *
+ */
+
+/ {
+ aliases {
+ /* label nics same order as armada 388 clearfog */
+ ethernet0 = &cp0_eth2;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth0;
+ i2c1 = &cp0_i2c1;
+ mmc1 = &cp0_sdhci0;
+ };
+
+ reg_usb3_vbus0: regulator-usb3-vbus0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+/* SRDS #2 - SFP+ 10GE */
+&cp0_eth0 {
+ managed = "in-band-status";
+ phys = <&cp0_comphy2 0>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp>;
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ expander0: gpio-expander@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-0 = <&expander0_pins>;
+ pinctrl-names = "default";
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+ /* CON3 */
+ pcie2-0-clkreq-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+
+ /* CON3 */
+ pcie2-0-w-disable-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+
+ usb3-ilimit-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+
+ m2-devslp-hog {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ };
+
+ /* The MCP3021 supports standard and fast modes */
+ adc@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ carrier_eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <8>;
+ };
+};
+
+&cp0_i2c1 {
+ /*
+ * Routed to SFP, M.2, mikrobus, and miniPCIe
+ * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
+ * address pins tied low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C bus being present.
+ * PCIe uses ARP to assign addresses, or 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* SRDS #5 - miniPCIe (CON3) */
+&cp0_pcie2 {
+ num-lanes = <1>;
+ phys = <&cp0_comphy5 2>;
+ /* dw-pcie inverts internally */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&cp0_pinctrl {
+ cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ cp0_mmc0_pins: cp0-mmc0-pins {
+ marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+
+ mikro_spi_pins: cp0-spi1-cs1-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+
+ mikro_uart_pins: cp0-uart-pins {
+ marvell,pins = "mpp2", "mpp3";
+ marvell,function = "uart1";
+ };
+
+ expander0_pins: cp0-expander0-pins {
+ marvell,pins = "mpp4";
+ marvell,function = "gpio";
+ };
+};
+
+/* SRDS #0 - SATA on M.2 connector */
+&cp0_sata0 {
+ phys = <&cp0_comphy0 1>;
+ status = "okay";
+
+ /* only port 1 is available */
+ /delete-node/ sata-port@0;
+};
+
+/* microSD */
+&cp0_sdhci0 {
+ pinctrl-0 = <&cp0_mmc0_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ /* CS1 for mikrobus */
+ pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
+};
+
+/*
+ * SRDS #1 - USB-3.0 Host on Type-A connector
+ * USB-2.0 Host on mPCI-e connector (CON3)
+ */
+&cp0_usb3_0 {
+ phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
+ phy-names = "comphy", "utmi";
+ vbus-supply = <®_usb3_vbus0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp0_utmi {
+ status = "okay";
+};
+
+/* mikrobus uart */
+&cp0_uart0 {
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9130-sr-som.dtsi b/dts/upstream/src/arm64/marvell/cn9130-sr-som.dtsi
new file mode 100644
index 0000000..4676e34
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9130-sr-som.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "SolidRun CN9130 SoM";
+ compatible = "solidrun,cn9130-sr-som", "marvell,cn9130";
+
+ aliases {
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ i2c0 = &cp0_i2c0;
+ mmc0 = &ap_sdhci0;
+ rtc0 = &cp0_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ /* requires assembly of R9307 */
+ vhv: regulator-vhv-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vhv-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-0 = <&cp0_reg_vhv_pins>;
+ pinctrl-names = "default";
+ gpios = <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&ap_pinctrl {
+ ap_mmc0_pins: ap-mmc0-pins {
+ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
+ marvell,function = "sdio";
+ /*
+ * mpp12 is emmc reset, function should be sdio (hw_rst),
+ * but pinctrl-mvebu does not support this.
+ *
+ * From pinctrl-mvebu.h:
+ * "The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes."
+ */
+ };
+};
+
+&ap_sdhci0 {
+ bus-width = <8>;
+ pinctrl-0 = <&ap_mmc0_pins>;
+ pinctrl-names = "default";
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* for assembly with phy */
+&cp0_eth2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_eth2_pins>;
+ phy-mode = "rgmii-id";
+ phy = <&cp0_eth2_phy>;
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ som_eeprom: eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <8>;
+ };
+};
+
+&cp0_mdio {
+ pinctrl-0 = <&cp0_mdio_pins>;
+ status = "okay";
+
+ /* assembly option */
+ cp0_eth2_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins>;
+ /* max speed limited by a mux */
+ spi-max-frequency = <1800000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ /* read command supports max. 50MHz */
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_eth2_pins: cp0-ge2-rgmii-pins {
+ marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47",
+ "mpp48", "mpp49", "mpp50", "mpp51",
+ "mpp52", "mpp53", "mpp54", "mpp55";
+ /* docs call it "ge2", but cp110-pinctrl "ge1" */
+ marvell,function = "ge1";
+ };
+
+ cp0_i2c0_pins: cp0-i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+
+ cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+
+ cp0_spi1_pins: cp0-spi1-pins {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+
+ cp0_reg_vhv_pins: cp0-reg-vhv-pins {
+ marvell,pins = "mpp41";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* AP default console */
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
new file mode 100644
index 0000000..b1ea7dc
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for SolidRun CN9130 Clearfog Base.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "cn9130.dtsi"
+#include "cn9130-sr-som.dtsi"
+
+/*
+ * Instantiate the external CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+/ {
+ model = "SolidRun CN9131 SolidWAN";
+ compatible = "solidrun,cn9131-solidwan",
+ "solidrun,cn9130-sr-som", "marvell,cn9130";
+
+ aliases {
+ ethernet0 = &cp1_eth1;
+ ethernet1 = &cp1_eth2;
+ ethernet2 = &cp0_eth1;
+ ethernet3 = &cp0_eth2;
+ ethernet4 = &cp0_eth0;
+ ethernet5 = &cp1_eth0;
+ gpio0 = &ap_gpio;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ gpio5 = &expander0;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ i2c2 = &cp1_i2c1;
+ mmc0 = &ap_sdhci0;
+ mmc1 = &cp0_sdhci0;
+ rtc0 = &cp0_rtc;
+ rtc1 = &carrier_rtc;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
+
+ /* for sfp-1 (J42) */
+ led-sfp1-activity {
+ label = "sfp1:green";
+ gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* for sfp-1 (J42) */
+ led-sfp1-link {
+ label = "sfp1:yellow";
+ gpios = <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* (J28) */
+ led-sfp0-activity {
+ label = "sfp0:green";
+ gpios = <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* (J28) */
+ led-sfp0-link {
+ label = "sfp0:yellow";
+ gpios = <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ /* Type-A port on J53 */
+ reg_usb_a_vbus0: regulator-usb-a-vbus0 {
+ compatible = "regulator-fixed";
+ pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
+ pinctrl-names = "default";
+ regulator-name = "vbus0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usb_a_vbus1: regulator-usb-a-vbus1 {
+ compatible = "regulator-fixed";
+ pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
+ pinctrl-names = "default";
+ regulator-name = "vbus1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sfp0: sfp-0 {
+ compatible = "sff,sfp";
+ pinctrl-0 = <&cp0_sfp0_pins>;
+ pinctrl-names = "default";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ pinctrl-0 = <&cp1_sfp1_pins>;
+ pinctrl-names = "default";
+ i2c-bus = <&cp1_i2c1>;
+ los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SRDS #2 - SFP+ 10GE */
+&cp0_eth0 {
+ managed = "in-band-status";
+ phy-mode = "10gbase-r";
+ phys = <&cp0_comphy2 0>;
+ sfp = <&sfp0>;
+ status = "okay";
+};
+
+/* SRDS #3 - SGMII 1GE */
+&cp0_eth1 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ /* Without mdio phy access rely on sgmii auto-negotiation. */
+ phys = <&cp0_comphy3 1>;
+ status = "okay";
+};
+
+/* SRDS #1 - SGMII */
+&cp0_eth2 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phy = <&cp0_phy1>;
+ phys = <&cp0_comphy1 2>;
+};
+
+&cp0_gpio1 {
+ pcie0-0-w-disable-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie0.0-w-disable";
+ };
+
+ /* J34 */
+ m2-full-card-power-off-hog {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-full-card-power-off";
+ };
+};
+
+&cp0_i2c0 {
+ /* assembly option */
+ fan-controller@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ };
+
+ expander0: gpio@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+
+ usb-a-vbus0-ilimit-hog {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "vbus0-ilimit";
+ };
+
+ /* duplicate connection, controlled by soc gpio */
+ usb-vbus0-enable-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "vbus0-enable";
+ };
+
+ usb-a-vbus1-ilimit-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "vbus1-ilimit";
+ };
+
+ /* duplicate connection, controlled by soc gpio */
+ usb-vbus1-enable-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "vbus1-enable";
+ };
+ };
+
+ carrier_eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <8>;
+ };
+
+ /* usb-hub@60 */
+
+ /* assembly option */
+ carrier_rtc: rtc@68 {
+ compatible = "st,m41t83";
+ reg = <0x68>;
+ pinctrl-0 = <&cp1_rtc_pins>;
+ pinctrl-names = "default";
+ interrupt-parent = <&cp1_gpio1>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cp0_i2c1 {
+ /*
+ * Routed to SFP.
+ * Limit to 100kHz for compatibility with SFP modules,
+ * featuring AT24C01A/02/04 at addresses 0x50/0x51.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cp0_mdio {
+ /*
+ * SoM + Carrier each have a PHY at address 0.
+ * Remove the SoM phy node, and skip adding the carrier node.
+ * SGMII Auto-Negotation is enabled by bootloader for
+ * autonomous operation without mdio control.
+ */
+ /delete-node/ ethernet-phy@0;
+
+ /* U17016 */
+ cp0_phy1: ethernet-phy@1 {
+ reg = <1>;
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link is 1000Mbps: On (yellow)
+ * - LED[1]: link/activity: On/blink (green)
+ * - LED[2]: high impedance (floating)
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a17>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+/* SRDS #0 - miniPCIe */
+&cp0_pcie0 {
+ num-lanes = <1>;
+ phys = <&cp0_comphy0 0>;
+ status = "okay";
+};
+
+/* SRDS #5 - M.2 B-Key (J34) */
+&cp0_pcie2 {
+ num-lanes = <1>;
+ phys = <&cp0_comphy5 2>;
+ status = "okay";
+};
+
+&cp0_pinctrl {
+ pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>;
+ pinctrl-names = "default";
+
+ cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ cp0_led_pins: cp0-led-pins {
+ marvell,pins = "mpp4", "mpp7";
+ marvell,function = "gpio";
+ };
+
+ cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+
+ cp0_mmc0_pins: cp0-mmc0-pins {
+ marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+
+ cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {
+ marvell,pins = "mpp6";
+ marvell,function = "gpio";
+ };
+
+ cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+
+ cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {
+ marvell,pins = "mpp28";
+ marvell,function = "gpio";
+ };
+
+ cp0_sfp0_pins: cp0-sfp0-pins {
+ marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34";
+ marvell,function = "gpio";
+ };
+
+ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+};
+
+/* microSD */
+&cp0_sdhci0 {
+ pinctrl-0 = <&cp0_mmc0_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ /* add pin for chip-select 1 */
+ pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
+
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ /* read command supports max. 50MHz */
+ spi-max-frequency = <50000000>;
+ };
+};
+
+/* USB-2.0 Host to USB-Hub */
+&cp0_usb3_0 {
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SRDS #4 - USB-3.0 Host to USB-Hub */
+&cp0_usb3_1 {
+ phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
+ phy-names = "comphy", "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp0_utmi {
+ status = "okay";
+};
+
+&cp0_utmi1 {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* SRDS #4 - SFP+ 10GE */
+&cp1_eth0 {
+ managed = "in-band-status";
+ phy-mode = "10gbase-r";
+ phys = <&cp1_comphy4 0>;
+ sfp = <&sfp1>;
+ status = "okay";
+};
+
+/* SRDS #3 - SGMII 1GE */
+&cp1_eth1 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phy = <&cp1_phy0>;
+ phys = <&cp0_comphy3 1>;
+ status = "okay";
+};
+
+/* SRDS #5 - SGMII 1GE */
+&cp1_eth2 {
+ managed = "in-band-status";
+ phy-mode = "sgmii";
+ phy = <&cp1_phy1>;
+ phys = <&cp0_comphy5 2>;
+ status = "okay";
+};
+
+&cp1_gpio1 {
+ status = "okay";
+
+ /* J30 */
+ m2-full-card-power-off-hog-0 {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-full-card-power-off";
+ };
+
+ /* J44 */
+ m2-full-card-power-off-hog-1 {
+ gpio-hog;
+ gpios = <30 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m2-full-card-power-off";
+ };
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c1 {
+ /*
+ * Routed to SFP.
+ * Limit to 100kHz for compatibility with SFP modules,
+ * featuring AT24C01A/02/04 at addresses 0x50/0x51.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&cp1_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&cp1_mdio {
+ pinctrl-0 = <&cp1_mdio_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ cp1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link is 1000Mbps: On (yellow)
+ * - LED[1]: link/activity: On/blink (green)
+ * - LED[2]: high impedance (floating)
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a17>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ cp1_phy1: ethernet-phy@1 {
+ reg = <1>;
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link is 1000Mbps: On (yellow)
+ * - LED[1]: link/activity: On/blink (green)
+ * - LED[2]: high impedance (floating)
+ */
+ marvell,reg-init = <3 16 0xf000 0x0a17>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+/* SRDS #0 - M.2 (J30) */
+&cp1_pcie0 {
+ num-lanes = <1>;
+ phys = <&cp1_comphy0 0>;
+ status = "okay";
+};
+
+&cp1_rtc {
+ status = "disabled";
+};
+
+/* SRDS #1 - SATA on M.2 (J44) */
+&cp1_sata0 {
+ phys = <&cp1_comphy1 0>;
+ status = "okay";
+
+ /* only port 0 is available */
+ /delete-node/ sata-port@1;
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+ pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>;
+ pinctrl-names = "default";
+
+ cp1_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ cp1_led_pins: cp1-led-pins {
+ marvell,pins = "mpp54", "mpp55";
+ marvell,function = "gpio";
+ };
+
+ cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {
+ marvell,pins = "mpp30";
+ marvell,function = "gpio";
+ };
+
+ cp1_mdio_pins: cp1-mdio-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "ge";
+ };
+
+ cp1_rtc_pins: cp1-rtc-pins {
+ marvell,pins = "mpp12", "mpp13";
+ marvell,function = "gpio";
+ };
+
+ cp1_sfp1_pins: cp1-sfp1-pins {
+ marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/*
+ * SRDS #2 - USB-3.0 Host to M.2 (J44)
+ * USB-2.0 Host to M.2 (J30)
+ */
+&cp1_usb3_0 {
+ phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
+ phy-names = "comphy", "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* USB-2.0 Host to M.2 (J44) */
+&cp1_usb3_1 {
+ phys = <&cp1_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp1_utmi {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts b/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts
new file mode 100644
index 0000000..0f53745
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9132-clearfog.dts
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ * DTS for SolidRun CN9132 Clearfog.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "cn9130.dtsi"
+#include "cn9132-sr-cex7.dtsi"
+
+/ {
+ model = "SolidRun CN9132 Clearfog";
+ compatible = "solidrun,cn9132-clearfog",
+ "solidrun,cn9132-sr-cex7", "marvell,cn9130";
+
+ aliases {
+ ethernet1 = &cp0_eth2;
+ ethernet2 = &cp0_eth0;
+ ethernet3 = &cp2_eth0;
+ ethernet4 = &cp1_eth0;
+ i2c7 = &carrier_mpcie_i2c;
+ i2c8 = &carrier_ptp_i2c;
+ mmc1 = &cp0_sdhci0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_wake0_pins>;
+
+ button-0 {
+ label = "SW2";
+ gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_2>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
+
+ /* LED11 */
+ led-io-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ function-enumerator = <0>;
+ default-state = "off";
+ gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED12 */
+ led-io-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DISK;
+ function-enumerator = <1>;
+ default-state = "off";
+ gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ /* CON4 W_DISABLE1/W_DISABLE2 */
+ rfkill-m2-wlan {
+ compatible = "rfkill-gpio";
+ label = "m.2 wlan (CON4)";
+ radio-type = "wlan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* CON5 W_DISABLE1/W_DISABLE2 */
+ rfkill-m2-wlan {
+ compatible = "rfkill-gpio";
+ label = "m.2 wlan (CON5)";
+ radio-type = "wlan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* J21 W_DISABLE1 */
+ rfkill-m2-wwan {
+ compatible = "rfkill-gpio";
+ label = "m.2 wwan (J21)";
+ radio-type = "wwan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_rsvd3_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* J21 W_DISABLE1 */
+ rfkill-m2-gnss {
+ compatible = "rfkill-gpio";
+ label = "m.2 gnss (J21)";
+ radio-type = "gps";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_rsvd8_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* J14 W_DISABLE */
+ rfkill-mpcie-wlan {
+ compatible = "rfkill-gpio";
+ label = "mpcie wlan (J14)";
+ radio-type = "wlan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_rsvd2_pins>;
+ /* rfkill-gpio inverts internally */
+ shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&com_10g_sfp_i2c0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&com_10g_int0_pins>;
+ mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <2000>;
+ };
+};
+
+&com_smbus {
+ /* This bus is also routed to STM32 BMC Microcontroller (U2) */
+
+ power-sensor@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ #io-channel-cells = <1>;
+ label = "vdd_12v0";
+ shunt-resistor = <2000>;
+ };
+
+ adc@48 {
+ compatible = "ti,tla2021";
+ reg = <0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* supplied by chaoskey hardware noise generator circuit */
+ channel@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&cp0_eth_phy0 {
+ /*
+ * Configure LEDs default behaviour:
+ * - LED[0]: link is 1000Mbps: On (yellow): 0111
+ * - LED[1]: link/activity: On/Blink (green): 0001
+ * - LED[2]: Off (green): 1000
+ */
+ marvell,reg-init = <3 16 0xf000 0x0817>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ /* link */
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ /* act */
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ /* 1000 */
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+};
+
+/* SRDS #4 - 10GE */
+&cp0_eth0 {
+ phys = <&cp0_comphy4 0>;
+ phy-mode = "10gbase-r";
+ managed = "in-band-status";
+ sfp = <&sfp>;
+ status = "okay";
+};
+
+&cp0_eth2 {
+ phy-mode = "2500base-x";
+ phys = <&cp0_comphy5 2>;
+ status = "okay";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+};
+
+&cp0_i2c1 {
+ /*
+ * Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
+ * Describe them as a single device merging each child bus.
+ */
+
+ i2c-mux@77 {
+ i2c@0 {
+ /* Routed to Full PCIe (J4) */
+ };
+
+ i2c@1 {
+ /* Routed to USB Hub (U29) */
+ };
+
+ i2c@2 {
+ /* Routed to M.2 (CON4) */
+ };
+
+ i2c@3 {
+ /* Routed to M.2 (CON5) */
+ };
+
+ i2c@4 {
+ /* Routed to M.2 (J21) */
+ };
+
+ carrier_mpcie_i2c: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+
+ /* Routed to mini-PCIe (J14) */
+ };
+
+ carrier_ptp_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ /* Routed to various optional PTP related components */
+ };
+ };
+};
+
+&cp0_mdio {
+ ethernet-switch@4 {
+ compatible = "marvell,mv88e6085";
+ reg = <4>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x11>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x12>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x13>;
+ };
+
+ sw_phy4: ethernet-phy@4 {
+ reg = <0x14>;
+ };
+ };
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&sw_phy3>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@4 {
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&sw_phy4>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+
+ ethernet-port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&cp0_eth2>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+};
+
+/* SRDS #0,#1,#2,#3 - PCIe */
+&cp0_pcie0 {
+ num-lanes = <4>;
+ phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
+ status = "okay";
+};
+
+&cp0_pinctrl {
+ /*
+ * configure unused gpios exposed via pin headers:
+ * - J7-10: PWRBTN
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_pwrbtn_pins>;
+};
+
+/* microSD */
+&cp0_sdhci0 {
+ pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ /* add CS1 */
+ pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
+
+ flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ /* read command supports max. 50MHz */
+ spi-max-frequency = <50000000>;
+ };
+};
+
+/* J38 */
+&cp0_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart2_pins>;
+ status = "okay";
+};
+
+&cp0_utmi {
+ /* M.2 "CON5" swaps D+/D- */
+ swap-dx-lanes = <1>;
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* SRDS #2 - 5GE */
+&cp1_eth0 {
+ phys = <&cp1_comphy2 0>;
+ phy-mode = "5gbase-r";
+ phy = <&cp1_eth_phy0>;
+ managed = "in-band-status";
+ status = "okay";
+};
+
+/* SRDS #0,#1 - PCIe */
+&cp1_pcie0 {
+ num-lanes = <2>;
+ phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
+ status = "okay";
+};
+
+/* SRDS #4 - PCIe */
+&cp1_pcie1 {
+ num-lanes = <1>;
+ phys = <&cp1_comphy4 1>;
+ status = "okay";
+};
+
+/* SRDS #5 - PCIe */
+&cp1_pcie2 {
+ num-lanes = <1>;
+ phys = <&cp1_comphy5 2>;
+ status = "okay";
+};
+
+&cp1_pinctrl {
+ /*
+ * configure unused gpios exposed via pin headers:
+ * - J7-8: RSVD16
+ * - J7-10: THRM
+ * - J10-1: WAKE1
+ * - J10-2: SATA_ACT
+ * - J10-8: THERMTRIP
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
+ <&cp1_thrm_trip_pins &cp1_wake1_pins>;
+};
+
+/* SRDS #3 - SATA */
+&cp1_sata0 {
+ status = "okay";
+
+ /* only port 1 is available */
+ /delete-node/ sata-port@0;
+
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ };
+};
+
+&cp1_utmi {
+ /* M.2 "CON4" swaps D+/D- */
+ swap-dx-lanes = <0>;
+};
+
+&cp1_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xmdio_pins>;
+ status = "okay";
+
+ cp1_eth_phy0: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&com_10g_int1_pins>;
+ interrupt-parent = <&cp1_gpio2>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SRDS #2 - 5GE */
+&cp2_eth0 {
+ phys = <&cp2_comphy2 0>;
+ phy-mode = "5gbase-r";
+ phy = <&cp2_eth_phy0>;
+ managed = "in-band-status";
+ status = "okay";
+};
+
+&cp2_gpio1 {
+ pinctrl-names= "default";
+ pinctrl-0 = <&cp2_rsvd9_pins>;
+
+ /* J21 */
+ m2-wwan-reset-hog {
+ gpio-hog;
+ gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ output-low;
+ line-name = "m2-wwan-reset";
+ };
+};
+
+/* SRDS #0 - PCIe */
+&cp2_pcie0 {
+ num-lanes = <1>;
+ phys = <&cp2_comphy0 0>;
+ status = "okay";
+};
+
+/* SRDS #4 - PCIe */
+&cp2_pcie1 {
+ num-lanes = <1>;
+ phys = <&cp2_comphy4 1>;
+ status = "okay";
+};
+
+/* SRDS #5 - PCIe */
+&cp2_pcie2 {
+ num-lanes = <1>;
+ phys = <&cp2_comphy5 2>;
+ status = "okay";
+};
+
+&cp2_pinctrl {
+ /*
+ * configure unused gpios exposed via pin headers:
+ * - J7-1: RSVD10
+ * - J7-3: RSVD11
+ * - J7-5: RSVD56
+ * - J7-6: RSVD7
+ * - J7-7: RSVD27
+ * - J10-3: RSVD31
+ * - J10-5: RSVD5
+ * - J10-6: RSVD32
+ * - J10-7: RSVD0
+ * - J10-9: RSVD1
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
+ <&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
+ <&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
+ <&cp2_rsvd56_pins>;
+};
+
+/* SRDS #3 - SATA */
+&cp2_sata0 {
+ status = "okay";
+
+ /* only port 1 is available */
+ /delete-node/ sata-port@0;
+
+ sata-port@1 {
+ phys = <&cp2_comphy3 1>;
+ };
+};
+
+&cp2_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_xmdio_pins>;
+ status = "okay";
+
+ cp2_eth_phy0: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&com_10g_int2_pins>;
+ interrupt-parent = <&cp2_gpio2>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9132-sr-cex7.dtsi b/dts/upstream/src/arm64/marvell/cn9132-sr-cex7.dtsi
new file mode 100644
index 0000000..afc041c
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9132-sr-cex7.dtsi
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/*
+ * Instantiate the first external CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+/*
+ * Instantiate the second external CP115
+ */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+/ {
+ model = "SolidRun CN9132 COM Express Type 7 Module";
+ compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130";
+
+ aliases {
+ ethernet0 = &cp0_eth1;
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ i2c2 = &com_clkgen_i2c;
+ i2c3 = &com_10g_led_i2c;
+ i2c4 = &com_10g_sfp_i2c0;
+ i2c5 = &com_smbus;
+ i2c6 = &com_fanctrl_i2c;
+ mmc0 = &ap_sdhci0;
+ rtc0 = &cp0_rtc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 51 102 153 204 255>;
+ #cooling-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>;
+ pwms = <&cp0_gpio2 7 40000>;
+ interrupt-parent = <&cp0_gpio1>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ap_vhv: regulator-ap-vhv-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ap-vhv-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-0 = <&cp0_reg_ap_vhv_pins>;
+ pinctrl-names = "default";
+ gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ cp_vhv: regulator-cp-vhv-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp-vhv-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-0 = <&cp0_reg_cp_vhv_pins>;
+ pinctrl-names = "default";
+ gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&ap_pinctrl {
+ ap_mmc0_pins: ap-mmc0-pins {
+ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
+ marvell,function = "sdio";
+ /*
+ * mpp12 is emmc reset, function should be sdio (hw_rst),
+ * but pinctrl-mvebu does not support this.
+ *
+ * From pinctrl-mvebu.h:
+ * "The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes."
+ */
+ };
+};
+
+&ap_sdhci0 {
+ bus-width = <8>;
+ pinctrl-0 = <&ap_mmc0_pins>;
+ pinctrl-names = "default";
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
+
+&ap_thermal_ic {
+ polling-delay = <1000>;
+
+ trips {
+ ap_active: trip-active {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&ap_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 4>;
+ };
+
+ map1 {
+ trip = <&ap_crit>;
+ cooling-device = <&fan 4 5>;
+ };
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_eth1_pins>;
+ phy-mode = "rgmii-id";
+ phy = <&cp0_eth_phy0>;
+ status = "okay";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+
+ /*
+ * Tacho signal used as interrupt source by pwm-fan driver.
+ * Hog IO as input to ensure mvebu-gpio irq driver`s
+ * irq_set_type can succeed.
+ */
+ pwm-tacho-irq-hog {
+ gpio-hog;
+ gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ input;
+ line-name = "fan-tacho";
+ };
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ com_eeprom: eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+};
+
+&cp0_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ com_clkgen_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ /* clock-controller@6b */
+ };
+
+ com_10g_led_i2c: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ /* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */
+ };
+
+ com_10g_sfp_i2c0: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ /* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */
+ };
+
+ com_smbus: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ /* Routed to B2B Connector as SBM_CLK/DAT */
+ };
+
+ com_fanctrl_i2c: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ /* fan-controller@2f (assembly option) */
+ };
+ };
+};
+
+&cp0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_mdio_pins>;
+ status = "okay";
+
+ cp0_eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ /* read command supports max. 50MHz */
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ com_10g_int0_pins: cp0-10g-int-pins {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ cp0_eth1_pins: cp0-eth1-pins {
+ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+ "mpp4", "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10", "mpp11";
+ /* docs call it "ge1", but cp110-pinctrl "ge0" */
+ marvell,function = "ge0";
+ };
+
+ cp0_fan_pwm_pins: cp0-fan-pwm-pins {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+
+ cp0_fan_tacho_pins: cp0-fan-tacho-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ cp0_i2c0_pins: cp0-i2c0-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+
+ cp0_i2c1_pins: cp0-i2c1-pins {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+
+ cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+
+ cp0_mmc0_pins: cp0-mmc0-pins {
+ marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59",
+ "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+
+ cp0_mmc0_cd_pins: cp0-mmc0-cd-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "sdio_cd";
+ };
+
+ cp0_pwrbtn_pins: cp0-pwrbtn-pins {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins {
+ marvell,pins = "mpp53";
+ marvell,function = "gpio";
+ };
+
+ cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins {
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+
+ cp0_spi1_pins: cp0-spi1-pins {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+
+ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
+ marvell,pins = "mpp12";
+ marvell,function = "spi1";
+ };
+
+ cp0_uart2_pins: cp0-uart2-pins {
+ marvell,pins = "mpp50", "mpp51";
+ marvell,function = "uart2";
+ };
+ };
+};
+
+&cp0_thermal_ic {
+ polling-delay = <1000>;
+
+ trips {
+ cp0_active: trip-active {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cp0_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 4>;
+ };
+
+ map1 {
+ trip = <&cp0_crit>;
+ cooling-device = <&fan 4 5>;
+ };
+ };
+};
+
+/* USB-2.0 Host */
+&cp0_usb3_0 {
+ phys = <&cp0_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* USB-2.0 Host */
+&cp0_usb3_1 {
+ phys = <&cp0_utmi1>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp0_utmi {
+ status = "okay";
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_rtc {
+ status = "disabled";
+};
+
+&cp1_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi1_pins>;
+ status = "okay";
+
+ tpm@0 {
+ reg = <0>;
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <10000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_tpm_irq_pins>;
+ interrupt-parent = <&cp1_gpio1>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ com_10g_int1_pins: cp1-10g-int-pins {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+
+ cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+
+ cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins {
+ marvell,pins = "mpp42";
+ marvell,function = "gpio";
+ };
+
+ cp1_batlow_pins: cp1-batlow-pins {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+
+ cp1_rsvd16_pins: cp1-rsvd16-pins {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ cp1_sata_act_pins: cp1-sata-act-pins {
+ marvell,pins = "mpp39";
+ marvell,function = "gpio";
+ };
+
+ cp1_spi1_pins: cp1-spi1-pins {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+
+ cp1_thrm_irq_pins: cp1-thrm-irq-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+
+ cp1_thrm_trip_pins: cp1-thrm-trip-pins {
+ marvell,pins = "mpp33";
+ marvell,function = "gpio";
+ };
+
+ cp1_tpm_irq_pins: cp1-tpm-irq-pins {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ cp1_wake0_pins: cp1-wake0-pins {
+ marvell,pins = "mpp40";
+ marvell,function = "gpio";
+ };
+
+ cp1_wake1_pins: cp1-wake1-pins {
+ marvell,pins = "mpp51";
+ marvell,function = "gpio";
+ };
+
+ cp1_xmdio_pins: cp1-xmdio-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "xg";
+ };
+ };
+};
+
+&cp1_thermal_ic {
+ polling-delay = <1000>;
+
+ trips {
+ cp1_active: trip-active {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cp1_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 4>;
+ };
+
+ map1 {
+ trip = <&cp1_crit>;
+ cooling-device = <&fan 4 5>;
+ };
+ };
+};
+
+/* USB-2.0 Host */
+&cp1_usb3_0 {
+ phys = <&cp1_utmi0>;
+ phy-names = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp1_utmi {
+ status = "okay";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_rtc {
+ status = "disabled";
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ com_10g_int2_pins: cp2-10g-int-pins {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd0_pins: cp2-rsvd0-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd1_pins: cp2-rsvd1-pins {
+ marvell,pins = "mpp1";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd2_pins: cp2-rsvd2-pins {
+ marvell,pins = "mpp2";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd3_pins: cp2-rsvd3-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd4_pins: cp2-rsvd4-pins {
+ marvell,pins = "mpp4";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd5_pins: cp2-rsvd5-pins {
+ marvell,pins = "mpp54";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd7_pins: cp2-rsvd7-pins {
+ marvell,pins = "mpp7";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd8_pins: cp2-rsvd8-pins {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd9_pins: cp2-rsvd9-pins {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd10_pins: cp2-rsvd10-pins {
+ marvell,pins = "mpp10";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd11_pins: cp2-rsvd11-pins {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd27_pins: cp2-rsvd27-pins {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd31_pins: cp2-rsvd31-pins {
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd32_pins: cp2-rsvd32-pins {
+ marvell,pins = "mpp32";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd55_pins: cp2-rsvd55-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "gpio";
+ };
+
+ cp2_rsvd56_pins: cp2-rsvd56-pins {
+ marvell,pins = "mpp56";
+ marvell,function = "gpio";
+ };
+
+ cp2_xmdio_pins: cp2-xmdio-pins {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "xg";
+ };
+ };
+};
+
+&cp2_thermal_ic {
+ polling-delay = <1000>;
+
+ trips {
+ cp2_active: trip-active {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cp2_active>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 4>;
+ };
+
+ map1 {
+ trip = <&cp2_crit>;
+ cooling-device = <&fan 4 5>;
+ };
+ };
+};
+
+/* USB-2.0/3.0 Host */
+&cp2_usb3_0 {
+ phys = <&cp2_utmi0>, <&cp2_comphy1 0>;
+ phy-names = "utmi", "comphy";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&cp2_utmi {
+ status = "okay";
+};
+
+/* AP default console */
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
index 234e3b2..c84c47c 100644
--- a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
@@ -137,7 +137,7 @@
<MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
<MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
<MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
rx_pins {
pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
@@ -151,7 +151,7 @@
mdio_pins {
pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
<MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
input-enable;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt6795-sony-xperia-m5.dts b/dts/upstream/src/arm64/mediatek/mt6795-sony-xperia-m5.dts
index 7364c72..91de920 100644
--- a/dts/upstream/src/arm64/mediatek/mt6795-sony-xperia-m5.dts
+++ b/dts/upstream/src/arm64/mediatek/mt6795-sony-xperia-m5.dts
@@ -288,25 +288,25 @@
<PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO162__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-clk {
pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins-ds {
pinmux = <PINMUX_GPIO164__FUNC_MSDC0_DSL>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
index 224bb28..d12eac9 100644
--- a/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -149,9 +149,9 @@
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <0x1f>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -329,8 +329,8 @@
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
+ function = "emmc";
+ groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
diff --git a/dts/upstream/src/arm64/mediatek/mt7622-rfb1.dts b/dts/upstream/src/arm64/mediatek/mt7622-rfb1.dts
index 4162976..8c3e2e2 100644
--- a/dts/upstream/src/arm64/mediatek/mt7622-rfb1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7622-rfb1.dts
@@ -268,8 +268,8 @@
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
+ function = "emmc";
+ groups = "emmc", "emmc_rst";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
diff --git a/dts/upstream/src/arm64/mediatek/mt7981b-cudy-wr3000-v1.dts b/dts/upstream/src/arm64/mediatek/mt7981b-cudy-wr3000-v1.dts
new file mode 100644
index 0000000..54101cc
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7981b-cudy-wr3000-v1.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "mt7981b.dtsi"
+
+/ {
+ compatible = "cudy,wr3000-v1", "mediatek,mt7981b";
+ model = "Cudy WR3000 V1";
+
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x10000000>;
+ device_type = "memory";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ key-wps {
+ label = "WPS";
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ key-reset {
+ label = "RESET";
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_LAN;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led-5 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts b/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts
new file mode 100644
index 0000000..4f6cbb4
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7981b-openwrt-one.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+
+/dts-v1/;
+
+#include "mt7981b.dtsi"
+
+/ {
+ compatible = "openwrt,one", "mediatek,mt7981b";
+ model = "OpenWrt One";
+
+ memory@40000000 {
+ reg = <0 0x40000000 0 0x40000000>;
+ device_type = "memory";
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7981b.dtsi b/dts/upstream/src/arm64/mediatek/mt7981b.dtsi
index 4feff3d..64aeeb2 100644
--- a/dts/upstream/src/arm64/mediatek/mt7981b.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt7981b.dtsi
@@ -2,6 +2,7 @@
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/mt7986-resets.h>
/ {
compatible = "mediatek,mt7981b";
@@ -62,12 +63,19 @@
#clock-cells = <1>;
};
- clock-controller@1001b000 {
+ topckgen: clock-controller@1001b000 {
compatible = "mediatek,mt7981-topckgen", "syscon";
reg = <0 0x1001b000 0 0x1000>;
#clock-cells = <1>;
};
+ watchdog: watchdog@1001c000 {
+ compatible = "mediatek,mt7986-wdt";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
clock-controller@1001e000 {
compatible = "mediatek,mt7981-apmixedsys";
reg = <0 0x1001e000 0 0x1000>;
@@ -78,20 +86,80 @@
compatible = "mediatek,mt7981-pwm";
reg = <0 0x10048000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_PWM_STA>,
- <&infracfg CLK_INFRA_PWM_HCK>,
- <&infracfg CLK_INFRA_PWM1_CK>,
- <&infracfg CLK_INFRA_PWM2_CK>,
- <&infracfg CLK_INFRA_PWM3_CK>;
+ <&infracfg CLK_INFRA_PWM_HCK>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
#pwm-cells = <2>;
};
+ i2c@11007000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0 0x11007000 0 0x1000>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>,
+ <&infracfg CLK_INFRA_I2C_MCK_CK>,
+ <&infracfg CLK_INFRA_I2C_PCK_CK>;
+ clock-names = "main", "dma", "arb", "pmic";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pio: pinctrl@11d00000 {
+ compatible = "mediatek,mt7981-pinctrl";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x11c00000 0 0x1000>,
+ <0 0x11c10000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11e00000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x11f10000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
+ "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ gpio-ranges = <&pio 0 0 56>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ efuse@11f20000 {
+ compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
+ reg = <0 0x11f20000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
clock-controller@15000000 {
compatible = "mediatek,mt7981-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ wifi@18000000 {
+ compatible = "mediatek,mt7981-wmac";
+ reg = <0 0x18000000 0 0x1000000>,
+ <0 0x10003000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
+ <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
+ clock-names = "mcu", "ap2conn";
+ resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
+ reset-names = "consys";
+ };
};
timer {
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
index 779dc67..047a838 100644
--- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
@@ -9,21 +9,17 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- bus-width = <8>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- hs400-ds-delay = <0x14014>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
- };
- };
};
+&{/soc/mmc@11230000} {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x14014>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-mini.dts b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
new file mode 100644
index 0000000..e2a2fea
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-mini.dts
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Authors: Frank Wunderlich <frank-w@public-files.de>
+ * Eric Woudstra <ericwouds@gmail.com>
+ * Tianling Shen <cnsztl@immortalwrt.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+ model = "Bananapi BPI-R3 Mini";
+ chassis-type = "embedded";
+ compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcin: regulator-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "12vd";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ /*
+ * The signal is inverted on this board and the PWM driver
+ * does not support polarity inversion.
+ */
+ /* cooling level (0, 1, 2) */
+ cooling-levels = <255 96 0>;
+ pwms = <&pwm 0 10000>;
+ };
+
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1.8vd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&dcin>;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3vd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&dcin>;
+ };
+
+ usb_vbus: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&pio 20 GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ };
+
+ en8811_a: regulator-phy1 {
+ compatible = "regulator-fixed";
+ regulator-name = "phy1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 16 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ en8811_b: regulator-phy2 {
+ compatible = "regulator-fixed";
+ regulator-name = "phy2";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 17 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset-key {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ map1 {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ map2 {
+ /* active: set fan to cooling level 0 */
+ cooling-device = <&fan 0 0>;
+ trip = <&cpu_trip_active_low>;
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ phy-handle = <&phy0>;
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "2500base-x";
+ phy-handle = <&phy1>;
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+};
+
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+
+ /* MAC Address EEPROM */
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+
+ address-width = <8>;
+ pagesize = <8>;
+ size = <256>;
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy@14 {
+ reg = <14>;
+ interrupts-extended = <&pio 48 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ phy-mode = "2500base-x";
+ full-duplex;
+ pause;
+ airoha,pnswap-rx;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 { /* en8811_a_gpio5 */
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+ led@1 { /* en8811_a_gpio4 */
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+
+ phy1: ethernet-phy@15 {
+ reg = <15>;
+ interrupts-extended = <&pio 46 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+ phy-mode = "2500base-x";
+ full-duplex;
+ pause;
+ airoha,pnswap-rx;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 { /* en8811_b_gpio5 */
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_WAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+ led@1 { /* en8811_b_gpio4 */
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pio {
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c";
+ };
+ };
+
+ mmc0_pins_default: mmc0-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ mux {
+ function = "emmc";
+ groups = "emmc_51";
+ };
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-ds {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
+ };
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0";
+ };
+ };
+
+ spi_flash_pins: spi-flash-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+
+ usb_ngff_pins: usb-ngff-pins {
+ ngff-gnss-off-conf {
+ pins = "GPIO_6";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ ngff-pe-rst-conf {
+ pins = "GPIO_7";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ ngff-wwan-off-conf {
+ pins = "GPIO_8";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ ngff-pwr-off-conf {
+ pins = "GPIO_9";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ ngff-rst-conf {
+ pins = "GPIO_10";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ ngff-coex-conf {
+ pins = "SPI1_CS";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ };
+
+ wf_2g_5g_pins: wf-2g-5g-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_2g", "wf_5g";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_dbdc_pins: wf-dbdc-pins {
+ mux {
+ function = "wifi";
+ groups = "wf_dbdc";
+ };
+ conf {
+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+ "WF1_TOP_CLK", "WF1_TOP_DATA";
+ drive-strength = <4>;
+ };
+ };
+
+ wf_led_pins: wf-led-pins {
+ mux {
+ function = "led";
+ groups = "wifi_led";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "spi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&ssusb {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_ngff_pins>;
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <&usb_vbus>;
+ status = "okay";
+};
+
+&trng {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+ pinctrl-names = "default", "dbdc";
+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
+
+ led {
+ led-active-low;
+ };
+};
+
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
index 7b97c5c..24398f8 100644
--- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
@@ -9,46 +9,44 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+};
- fragment@0 {
- target-path = "/soc/spi@1100a000";
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- spi_nand: flash@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <10000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
+&{/soc/spi@1100a000} {
+ #address-cells = <1>;
+ #size-cells = <0>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
+ spi_nand: flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "bl2";
- reg = <0x0 0x100000>;
- read-only;
- };
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
- partition@100000 {
- label = "reserved";
- reg = <0x100000 0x280000>;
- };
+ partition@100000 {
+ label = "reserved";
+ reg = <0x100000 0x280000>;
+ };
- partition@380000 {
- label = "fip";
- reg = <0x380000 0x200000>;
- read-only;
- };
+ partition@380000 {
+ label = "fip";
+ reg = <0x380000 0x200000>;
+ read-only;
+ };
- partition@580000 {
- label = "ubi";
- reg = <0x580000 0x7a80000>;
- };
- };
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x7a80000>;
};
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
index e48881b..6a0d529 100644
--- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
@@ -9,54 +9,52 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+};
- fragment@0 {
- target-path = "/soc/spi@1100a000";
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
+&{/soc/spi@1100a000} {
+ #address-cells = <1>;
+ #size-cells = <0>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
- partition@0 {
- label = "bl2";
- reg = <0x0 0x40000>;
- read-only;
- };
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x40000>;
- };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x40000>;
+ };
- partition@80000 {
- label = "reserved2";
- reg = <0x80000 0x80000>;
- };
+ partition@80000 {
+ label = "reserved2";
+ reg = <0x80000 0x80000>;
+ };
- partition@100000 {
- label = "fip";
- reg = <0x100000 0x80000>;
- read-only;
- };
+ partition@100000 {
+ label = "fip";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
- partition@180000 {
- label = "recovery";
- reg = <0x180000 0xa80000>;
- };
+ partition@180000 {
+ label = "recovery";
+ reg = <0x180000 0xa80000>;
+ };
- partition@c00000 {
- label = "fit";
- reg = <0xc00000 0x1400000>;
- };
- };
+ partition@c00000 {
+ label = "fit";
+ reg = <0xc00000 0x1400000>;
};
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
index f623bce..d9e0196 100644
--- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
@@ -9,15 +9,11 @@
/ {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- fragment@0 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- bus-width = <4>;
- max-frequency = <52000000>;
- cap-sd-highspeed;
- status = "okay";
- };
- };
};
+&{/soc/mmc@11230000} {
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
index bba97de..aa72833 100644
--- a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
/ {
compatible = "mediatek,mt7988a";
@@ -78,7 +80,7 @@
#interrupt-cells = <3>;
};
- clock-controller@10001000 {
+ infracfg: clock-controller@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
@@ -103,6 +105,92 @@
#clock-cells = <1>;
};
+ pwm@10048000 {
+ compatible = "mediatek,mt7988-pwm";
+ reg = <0 0x10048000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+ "pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ i2c@11003000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0 0x11003000 0 0x1000>,
+ <0 0x10217080 0 0x80>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c@11004000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0 0x11004000 0 0x1000>,
+ <0 0x10217100 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c@11005000 {
+ compatible = "mediatek,mt7981-i2c";
+ reg = <0 0x11005000 0 0x1000>,
+ <0 0x10217180 0 0x80>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb@11190000 {
+ compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11190000 0 0x2e00>,
+ <0 0x11193e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_USB_SYS>,
+ <&infracfg CLK_INFRA_USB_REF>,
+ <&infracfg CLK_INFRA_66M_USB_HCK>,
+ <&infracfg CLK_INFRA_133M_USB_HCK>,
+ <&infracfg CLK_INFRA_USB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ };
+
+ usb@11200000 {
+ compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
+ <&infracfg CLK_INFRA_USB_CK_P1>,
+ <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
+ <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
+ <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+ };
+
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
index 90cbbc1..8d1cbc9 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
@@ -27,6 +27,15 @@
hid-descr-addr = <0x0020>;
interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
+
+ /* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */
+ touchscreen@40 {
+ compatible = "hid-over-i2c";
+ reg = <0x40>;
+ hid-descr-addr = <0x0001>;
+ interrupt-parent = <&pio>;
+ interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
+ };
};
&i2c4 {
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
index 6d962d4..b4d8514 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
@@ -1134,12 +1134,6 @@
rtc: mt6397rtc {
compatible = "mediatek,mt6397-rtc";
};
-
- syscfg_pctl_pmic: syscon@c000 {
- compatible = "mediatek,mt6397-pctl-pmic-syscfg",
- "syscon";
- reg = <0 0x0000c000 0 0x0108>;
- };
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
index 3fab21f..bb4671c 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
@@ -213,14 +213,14 @@
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
bias-pull-down;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
};
pins_insert {
@@ -241,13 +241,13 @@
<MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
<MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <2>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <2>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
@@ -265,13 +265,13 @@
<MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_4mA>;
+ drive-strength = <4>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-evb.dts b/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
index 681dedd..f04baea 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
@@ -160,7 +160,6 @@
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -169,7 +168,6 @@
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -178,7 +176,6 @@
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -187,7 +184,6 @@
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -196,7 +192,6 @@
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -205,7 +200,6 @@
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
index 8b57706..586eee7 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
@@ -27,7 +27,7 @@
dlg,btn-cfg = <50>;
dlg,mic-det-thr = <500>;
dlg,jack-ins-deb = <20>;
- dlg,jack-det-rate = "32ms_64ms";
+ dlg,jack-det-rate = "32_64";
dlg,jack-rem-deb = <1>;
dlg,a-d-btn-thr = <0xa>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
index 072133f..f34964a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-cozmo.dts
@@ -9,6 +9,7 @@
/ {
model = "Google cozmo board";
+ chassis-type = "laptop";
compatible = "google,cozmo", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
index b595622..72852b7 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku1 board";
+ chassis-type = "convertible";
compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
pwmleds {
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
index 5a1c393..757d0af 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku6 board";
+ chassis-type = "convertible";
compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
index 3ea4fdb..6641b08 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
@@ -9,6 +9,7 @@
/ {
model = "Google fennel sku7 board";
+ chassis-type = "convertible";
compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
index 3fc5a61..877256e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts
@@ -9,6 +9,7 @@
/ {
model = "Google fennel14 sku2 board";
+ chassis-type = "laptop";
compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
index 23ad0b9..b981dd3 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
@@ -9,6 +9,7 @@
/ {
model = "Google fennel14 sku0 board";
+ chassis-type = "laptop";
compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
index e5bd919..f3ac9c0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
@@ -9,6 +9,7 @@
/ {
model = "Google kappa board";
+ chassis-type = "laptop";
compatible = "google,kappa", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
index 8fa89db..e824158 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -9,5 +9,6 @@
/ {
model = "Google kenzo sku17 board";
+ chassis-type = "laptop";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
index 4eb2a0d..ddb9935 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
@@ -19,6 +19,6 @@
&mmc1_pins_uhs {
pins-clk {
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
index 6a73336..10c4f92 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
@@ -19,6 +19,6 @@
&mmc1_pins_uhs {
pins-clk {
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts
index 6a7ae61..cce326a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts
@@ -17,7 +17,7 @@
pinctrl-names = "default";
pinctrl-0 = <&bt_pins_wakeup>;
- wobt {
+ event-wobt {
label = "Wake on BT";
gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
@@ -47,10 +47,8 @@
};
};
-&wifi_wakeup {
- wowlan {
- gpios = <&pio 113 GPIO_ACTIVE_LOW>;
- };
+&wifi_wakeup_event {
+ gpios = <&pio 113 GPIO_ACTIVE_LOW>;
};
&wifi_pwrseq {
@@ -68,16 +66,16 @@
&mmc1_pins_default {
pins-cmd-dat {
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
pins-clk {
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
&mmc1_pins_uhs {
pins-clk {
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
index 89208b8..928b205 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
@@ -9,6 +9,7 @@
/ {
model = "Google willow board sku0";
+ chassis-type = "laptop";
compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
index c7b2044..71307a8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
@@ -9,5 +9,6 @@
/ {
model = "Google willow board sku1";
+ chassis-type = "laptop";
compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 7592e3b..fa4ab4d 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -155,21 +155,24 @@
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&vddio_mipibrdg>;
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- anx7625_in: endpoint {
- remote-endpoint = <&dsi_out>;
+ port@0 {
+ reg = <0>;
+
+ anx7625_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
};
- };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- anx7625_out: endpoint {
- remote-endpoint = <&panel_in>;
+ anx7625_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama-sku32.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama-sku32.dts
index 7739358..5a41614 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama-sku32.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama-sku32.dts
@@ -12,6 +12,7 @@
/ {
model = "MediaTek kodama sku32 board";
+ chassis-type = "tablet";
compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
index 100191c..6345e96 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -152,7 +152,7 @@
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_wakeup>;
- button-wowlan {
+ wifi_wakeup_event: event-wowlan {
label = "Wake on WiFi";
gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_WAKEUP>;
@@ -488,7 +488,7 @@
<PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
<PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
<PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
@@ -502,7 +502,7 @@
<PINMUX_GPIO10__FUNC_GPIO10>;
input-enable;
bias-pull-down;
- drive-strength = <MTK_DRIVE_2mA>;
+ drive-strength = <2>;
};
};
@@ -533,7 +533,6 @@
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -542,7 +541,6 @@
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -551,7 +549,6 @@
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -560,7 +557,6 @@
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -569,7 +565,6 @@
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -578,7 +573,6 @@
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -679,14 +673,14 @@
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
};
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
mediatek,pull-down-adv = <10>;
input-enable;
};
@@ -803,7 +797,6 @@
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
- output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
@@ -822,7 +815,6 @@
};
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
- output-enable;
};
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
index 333c516..1aa668c 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -197,7 +197,6 @@
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -206,7 +205,6 @@
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -215,7 +213,6 @@
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -224,7 +221,6 @@
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -233,7 +229,6 @@
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -242,7 +237,6 @@
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
- mediatek,drive-strength-adv = <00>;
};
};
@@ -356,14 +350,14 @@
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
<PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
input-enable;
mediatek,pull-up-adv = <10>;
};
pins_clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
mediatek,pull-down-adv = <10>;
input-enable;
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183.dtsi b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
index 774ae5d..fbf1456 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
@@ -1183,7 +1183,7 @@
status = "disabled";
};
- thermal: thermal@1100b000 {
+ thermal: thermal-sensor@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8183-thermal";
reg = <0 0x1100b000 0 0xc00>;
@@ -2090,61 +2090,129 @@
};
};
- /* The tzts1 ~ tzts6 don't need to polling */
- /* The tzts1 ~ tzts6 don't need to thermal throttle */
-
- tzts1: tzts1 {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tzts1: soc-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+ trips {
+ soc_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- tzts2: tzts2 {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tzts2: gpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+
+ trips {
+ gpu_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- tzts3: tzts3 {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tzts3: md1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+
+ trips {
+ md1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- tzts4: tzts4 {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tzts4: cpu-little-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+
+ trips {
+ cpul_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpul_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- tzts5: tzts5 {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tzts5: cpu-big-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+
+ trips {
+ cpub_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpub_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
- tztsABB: tztsABB {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ tztsABB: tsabb-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
- trips {};
- cooling-maps {};
+
+ trips {
+ tsabb_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ tsabb_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589824.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589824.dts
new file mode 100644
index 0000000..d16834e
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589824.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-voltorb.dtsi"
+
+/ {
+ model = "Google Voltorb sku589824 board";
+ compatible = "google,voltorb-sku589824", "google,voltorb",
+ "mediatek,mt8186";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589825.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589825.dts
new file mode 100644
index 0000000..45e57f7
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb-sku589825.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-voltorb.dtsi"
+
+/ {
+ model = "Google Voltorb sku589825 board";
+ compatible = "google,voltorb-sku589825", "google,voltorb",
+ "mediatek,mt8186";
+};
+
+&i2c1 {
+ touchscreen@10 {
+ compatible = "elan,ekth6915";
+ reg = <0x10>;
+ interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+ vcc33-supply = <&pp3300_s3>;
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb.dtsi
new file mode 100644
index 0000000..52ec581
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-voltorb.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 Google LLC
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/spmi/spmi.h>
+
+#include "mt8186-corsola-steelix.dtsi"
+
+/ {
+ chassis-type = "laptop";
+
+ max98360a: max98360a {
+ compatible = "maxim,max98360a";
+ sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&cpu6 {
+ proc-supply = <&mt6319_buck1>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6319_buck1>;
+};
+
+&gpio_keys {
+ status = "disabled";
+};
+
+&keyboard_controller {
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
+&mt6366_vproc11_reg {
+ status = "disabled";
+};
+
+&cluster1_opp_14 {
+ opp-hz = /bits/ 64 <2050000000>;
+ opp-microvolt = <1118750>;
+};
+
+&cluster1_opp_15 {
+ opp-hz = /bits/ 64 <2200000000>;
+};
+
+&rt1019p{
+ status = "disabled";
+};
+
+&sound {
+ compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound";
+ status = "okay";
+
+ spk-hdmi-playback-dai-link {
+ codec {
+ sound-dai = <&it6505dptx>, <&max98360a>;
+ };
+ };
+};
+
+&spmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spmi_pins>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pmic@6 {
+ compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator";
+ reg = <0x6 SPMI_USID>;
+
+ regulators {
+ mt6319_buck1: vbuck1 {
+ regulator-name = "ppvar_dvdd_proc_bc_mt6319";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&touchscreen {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
index 1807e9d..afdab57 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
@@ -42,7 +42,7 @@
default-brightness-level = <576>;
};
- bt-sco-codec {
+ bt-sco {
compatible = "linux,bt-sco";
#sound-dai-cells = <0>;
};
@@ -223,12 +223,44 @@
mediatek,adsp = <&adsp>;
mediatek,platform = <&afe>;
- playback-codecs {
- sound-dai = <&it6505dptx>, <&rt1019p>;
+ audio-routing =
+ "Headphone", "HPOL",
+ "Headphone", "HPOR",
+ "IN1P", "Headset Mic",
+ "Speakers", "Speaker",
+ "HDMI1", "TX";
+
+ hs-playback-dai-link {
+ link-name = "I2S0";
+ dai-format = "i2s";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&rt5682s 0>;
+ };
+ };
+
+ hs-capture-dai-link {
+ link-name = "I2S1";
+ dai-format = "i2s";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&rt5682s 0>;
+ };
+ };
+
+ spk-share-dai-link {
+ link-name = "I2S2";
+ mediatek,clk-provider = "cpu";
};
- headset-codec {
- sound-dai = <&rt5682s 0>;
+ spk-hdmi-playback-dai-link {
+ link-name = "I2S3";
+ dai-format = "i2s";
+ mediatek,clk-provider = "cpu";
+ /* RT1019P and IT6505 connected to the same I2S line */
+ codec {
+ sound-dai = <&it6505dptx>, <&rt1019p>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188.dtsi b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
index b4315c9..29d012d 100644
--- a/dts/upstream/src/arm64/mediatek/mt8188.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
@@ -293,6 +294,112 @@
clock-output-names = "clk32k";
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-390000000 {
+ opp-hz = /bits/ 64 <390000000>;
+ opp-microvolt = <575000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-431000000 {
+ opp-hz = /bits/ 64 <431000000>;
+ opp-microvolt = <587500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-473000000 {
+ opp-hz = /bits/ 64 <473000000>;
+ opp-microvolt = <600000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-515000000 {
+ opp-hz = /bits/ 64 <515000000>;
+ opp-microvolt = <612500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-556000000 {
+ opp-hz = /bits/ 64 <556000000>;
+ opp-microvolt = <625000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <637500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-microvolt = <650000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-microvolt = <662500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <675000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-730000000 {
+ opp-hz = /bits/ 64 <730000000>;
+ opp-microvolt = <687500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-760000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-microvolt = <700000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-790000000 {
+ opp-hz = /bits/ 64 <790000000>;
+ opp-microvolt = <712500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-835000000 {
+ opp-hz = /bits/ 64 <835000000>;
+ opp-microvolt = <731250>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-880000000 {
+ opp-hz = /bits/ 64 <880000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-915000000 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <775000>;
+ opp-supported-hw = <0x8f>;
+ };
+ opp-915000000-5 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <762500>;
+ opp-supported-hw = <0x30>;
+ };
+ opp-915000000-6 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0x70>;
+ };
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <800000>;
+ opp-supported-hw = <0x8f>;
+ };
+ opp-950000000-5 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <775000>;
+ opp-supported-hw = <0x30>;
+ };
+ opp-950000000-6 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0x70>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
@@ -383,6 +490,329 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8188-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
+ reg = <MT8188_POWER_DOMAIN_MFG0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_MFG1 {
+ reg = <MT8188_POWER_DOMAIN_MFG1>;
+ clocks = <&topckgen CLK_APMIXED_MFGPLL>,
+ <&topckgen CLK_TOP_MFG_CORE_TMP>;
+ clock-names = "mfg", "alt";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_MFG2 {
+ reg = <MT8188_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_MFG3 {
+ reg = <MT8188_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_MFG4 {
+ reg = <MT8188_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
+ reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
+ clocks = <&topckgen CLK_TOP_VPP>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_IMG>,
+ <&topckgen CLK_TOP_VENC>,
+ <&topckgen CLK_TOP_VDEC>,
+ <&topckgen CLK_TOP_WPE_VPP>,
+ <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>,
+ <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>,
+ <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "top", "cam", "ccu", "img", "venc",
+ "vdec", "wpe", "cfgck", "cfgxo",
+ "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
+ "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
+ "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
+ "ss-sram-rdr", "ss-iommu", "ss-imgcam",
+ "ss-emi", "ss-subcmn-rdr", "ss-rsi",
+ "ss-cmn-l4", "ss-vdec1", "ss-wpe",
+ "ss-cvdo-ve1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
+ reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>,
+ <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>,
+ <&vdosys0 CLK_VDO0_APB_BUS>;
+ clock-names = "cfgck", "cfgxo", "ss-gals",
+ "ss-cmn", "ss-emi", "ss-iommu",
+ "ss-larb", "ss-rsi", "ss-bus";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
+ reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
+ <&vppsys1 CLK_VPP1_GALS5>,
+ <&vppsys1 CLK_VPP1_GALS6>,
+ <&vppsys1 CLK_VPP1_LARB5>,
+ <&vppsys1 CLK_VPP1_LARB6>;
+ clock-names = "cfgck", "cfgxo",
+ "ss-vpp1-g5", "ss-vpp1-g6",
+ "ss-vpp1-l5", "ss-vpp1-l6";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VDEC1 {
+ reg = <MT8188_POWER_DOMAIN_VDEC1>;
+ clocks = <&vdecsys CLK_VDEC2_LARB1>;
+ clock-names = "ss-vdec";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VDEC0 {
+ reg = <MT8188_POWER_DOMAIN_VDEC0>;
+ clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
+ clock-names = "ss-vdec";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
+ reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
+ clocks = <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_CCU_AHB>,
+ <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
+ clock-names = "cam", "ccu", "bus", "cfgck";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
+ reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
+ clocks = <&camsys CLK_CAM_MAIN_LARB13>,
+ <&camsys CLK_CAM_MAIN_LARB14>,
+ <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>;
+ clock-names= "ss-cam-l13", "ss-cam-l14",
+ "ss-cam-mm0", "ss-cam-mm1",
+ "ss-camsys";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
+ reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
+ clock-names = "ss-camb-sub",
+ "ss-camb-raw",
+ "ss-camb-yuv";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
+ reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_yuva CLK_CAM_YUVA_LARBX>;
+ clock-names = "ss-cama-sub",
+ "ss-cama-raw",
+ "ss-cama-yuv";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
+ reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "cfgck", "cfgxo", "ss-larb2",
+ "ss-larb3", "ss-gals";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
+ reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_HDCP_24M>;
+ clock-names = "bus", "hdcp";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_DP_TX {
+ reg = <MT8188_POWER_DOMAIN_DP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_EDP_TX {
+ reg = <MT8188_POWER_DOMAIN_EDP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VENC {
+ reg = <MT8188_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC1_LARB>,
+ <&vencsys CLK_VENC1_VENC>,
+ <&vencsys CLK_VENC1_GALS>,
+ <&vencsys CLK_VENC1_GALS_SRAM>;
+ clock-names = "ss-ve1-larb", "ss-ve1-core",
+ "ss-ve1-gals", "ss-ve1-sram";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_WPE {
+ reg = <MT8188_POWER_DOMAIN_WPE>;
+ clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
+ <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>;
+ clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
+ reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
+ clock-names = "ss-pextp-fmem";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
+ reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>;
+ clock-names = "seninf0", "seninf1";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
+ reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
+ reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
+ clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_ADSP>;
+ clock-names = "bus", "main";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
+ reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
+ reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
+ clocks = <&topckgen CLK_TOP_ASM_H>;
+ clock-names = "asm";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_AUDIO {
+ reg = <MT8188_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>;
+ clock-names = "a1sys", "intbus", "adspck";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP {
+ reg = <MT8188_POWER_DOMAIN_ADSP>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ETHER {
+ reg = <MT8188_POWER_DOMAIN_ETHER>;
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "ethermac";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8188-wdt";
reg = <0 0x10007000 0 0x100>;
@@ -413,6 +843,22 @@
clock-names = "spi", "wrap";
};
+ gce0: mailbox@10320000 {
+ compatible = "mediatek,mt8188-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@10330000 {
+ compatible = "mediatek,mt8188-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8188-scp";
reg = <0 0x10500000 0 0x100000>,
@@ -827,6 +1273,23 @@
#clock-cells = <1>;
};
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
+ reg = <0 0x13000000 0 0x4000>;
+
+ clocks = <&mfgcfg CLK_MFGCFG_BG3D>;
+ interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
+ <&spm MT8188_POWER_DOMAIN_MFG3>,
+ <&spm MT8188_POWER_DOMAIN_MFG4>;
+ power-domain-names = "core0", "core1", "core2";
+ status = "disabled";
+ };
+
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8188-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
@@ -951,6 +1414,23 @@
compatible = "mediatek,mt8188-vencsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ };
+
+ vdosys0: syscon@1c01d000 {
+ compatible = "mediatek,mt8188-vdosys0", "syscon";
+ reg = <0 0x1c01d000 0 0x1000>;
+ #clock-cells = <1>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
+ };
+
+ vdosys1: syscon@1c100000 {
+ compatible = "mediatek,mt8188-vdosys1", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
};
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r1.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r1.dts
index fd2cb87..ac2673e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r1.dts
@@ -7,6 +7,7 @@
/ {
model = "Google Hayato rev1";
+ chassis-type = "convertible";
compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
index 3127ee5..cd86ad9 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
@@ -7,6 +7,7 @@
/ {
model = "Google Hayato rev5";
+ chassis-type = "convertible";
compatible = "google,hayato-rev5-sku2", "google,hayato-sku2",
"google,hayato", "mediatek,mt8192";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r0.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r0.dts
index bc88866..29aa87e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r0.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r0.dts
@@ -8,6 +8,7 @@
/ {
model = "Google Spherion (rev0 - 3)";
+ chassis-type = "laptop";
compatible = "google,spherion-rev3", "google,spherion-rev2",
"google,spherion-rev1", "google,spherion-rev0",
"google,spherion", "mediatek,mt8192";
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
index 0039158..5e9e598 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
@@ -8,6 +8,7 @@
/ {
model = "Google Spherion (rev4)";
+ chassis-type = "laptop";
compatible = "google,spherion-rev4", "google,spherion",
"mediatek,mt8192";
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
index 7a70424..08d71dd 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
@@ -147,6 +147,7 @@
regulator-boot-on;
gpio = <&pio 127 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_g>;
+ off-on-delay-us = <500000>;
};
/* separately switched 3.3V power rail */
diff --git a/dts/upstream/src/arm64/mediatek/mt8192.dtsi b/dts/upstream/src/arm64/mediatek/mt8192.dtsi
index 84cbdf6..47dea10 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192.dtsi
@@ -2234,7 +2234,7 @@
};
};
- gpu0-thermal {
+ gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-cherry-dojo-r1.dts b/dts/upstream/src/arm64/mediatek/mt8195-cherry-dojo-r1.dts
new file mode 100644
index 0000000..8812384
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8195-cherry-dojo-r1.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8195-cherry.dtsi"
+
+/ {
+ model = "HP Dojo (sku 1, 3, 5, 7) board";
+ chassis-type = "convertible";
+ compatible = "google,dojo-sku7", "google,dojo-sku5",
+ "google,dojo-sku3", "google,dojo-sku1",
+ "google,dojo", "mediatek,mt8195";
+};
+
+&audio_codec {
+ compatible = "realtek,rt5682s";
+ realtek,amic-delay-ms = <250>;
+};
+
+&i2c2 {
+ spk_r_amp: amplifier@38 {
+ compatible = "maxim,max98390";
+ reg = <0x38>;
+ reset-gpios = <&pio 100 GPIO_ACTIVE_LOW>;
+ sound-name-prefix = "Right";
+ #sound-dai-cells = <0>;
+ };
+
+ spk_l_amp: amplifier@39 {
+ compatible = "maxim,max98390";
+ reg = <0x39>;
+ sound-name-prefix = "Left";
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2c4 {
+ touchscreen@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+ hid-descr-addr = <0x0001>;
+ interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ post-power-on-delay-ms = <10>;
+ vdd-supply = <&pp3300_s3>;
+ };
+};
+
+&keyboard_controller {
+ linux,keymap = <
+ CROS_STD_MAIN_KEYMAP
+
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE)
+ MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE)
+ MATRIX_KEY(0x00, 0x04, KEY_MICMUTE)
+ MATRIX_KEY(0x00, 0x01, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP)
+ >;
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins_default>;
+ status = "okay";
+};
+
+&pciephy {
+ status = "okay";
+};
+
+&pio_default {
+ pins-low-power-hdmi-disable {
+ pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
+ <PINMUX_GPIO32__FUNC_GPIO32>,
+ <PINMUX_GPIO33__FUNC_GPIO33>,
+ <PINMUX_GPIO34__FUNC_GPIO34>,
+ <PINMUX_GPIO35__FUNC_GPIO35>;
+ input-enable;
+ bias-pull-down;
+ };
+};
+
+&sound {
+ compatible = "mediatek,mt8195_mt6359_max98390_rt5682";
+ model = "m8195_m98390_5682s";
+
+ audio-routing =
+ "Headphone", "HPOL",
+ "Headphone", "HPOR",
+ "IN1P", "Headset Mic",
+ "Right Spk", "Right BE_OUT",
+ "Left Spk", "Left BE_OUT";
+
+ spk-playback-dai-link {
+ codec {
+ sound-dai = <&spk_r_amp>, <&spk_l_amp>;
+ };
+ };
+};
+
+&spk_amplifier {
+ /* Disable RT1019P, not present on Dojo */
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
index 4a11918..fe5400e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
@@ -240,6 +240,7 @@
spk_amplifier: rt1019p {
compatible = "realtek,rt1019p";
label = "rt1019p";
+ #sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&rt1019p_pins_default>;
sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
@@ -366,6 +367,7 @@
&dp_tx {
status = "okay";
+ #sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&dptx_pin>;
@@ -436,6 +438,7 @@
/* Realtek RT5682i or RT5682s, sharing the same configuration */
reg = <0x1a>;
interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
+ #sound-dai-cells = <0>;
realtek,jd-src = <1>;
AVDD-supply = <&mt6359_vio18_ldo_reg>;
@@ -1162,6 +1165,48 @@
"AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
+
+ audio-routing =
+ "Headphone", "HPOL",
+ "Headphone", "HPOR",
+ "IN1P", "Headset Mic",
+ "Ext Spk", "Speaker";
+
+ mm-dai-link {
+ link-name = "ETDM1_IN_BE";
+ mediatek,clk-provider = "cpu";
+ };
+
+ hs-playback-dai-link {
+ link-name = "ETDM1_OUT_BE";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&audio_codec>;
+ };
+ };
+
+ hs-capture-dai-link {
+ link-name = "ETDM2_IN_BE";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&audio_codec>;
+ };
+ };
+
+ spk-playback-dai-link {
+ link-name = "ETDM2_OUT_BE";
+ mediatek,clk-provider = "cpu";
+ codec {
+ sound-dai = <&spk_amplifier>;
+ };
+ };
+
+ displayport-dai-link {
+ link-name = "DPTX_BE";
+ codec {
+ sound-dai = <&dp_tx>;
+ };
+ };
};
&spi0 {
@@ -1389,6 +1434,11 @@
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+
+ /* T11 to T13 are present only on Dojo */
+ MATRIX_KEY(0x00, 0x01, 0) /* T11 */
+ MATRIX_KEY(0x01, 0x05, 0) /* T12 */
+ MATRIX_KEY(0x03, 0x05, 0) /* T13 */
>;
linux,keymap = <
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
index b82f717..31d424b 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
@@ -305,14 +305,14 @@
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO86__FUNC_GBE_RXC>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
pins-rxd {
pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
@@ -377,7 +377,7 @@
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -392,13 +392,13 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -406,7 +406,7 @@
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -421,19 +421,19 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -441,7 +441,7 @@
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -452,7 +452,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
@@ -465,7 +465,7 @@
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -476,7 +476,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-evb.dts b/dts/upstream/src/arm64/mediatek/mt8195-evb.dts
index 341b6e0..83456d6 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8195-evb.dts
@@ -74,7 +74,6 @@
pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
<PINMUX_GPIO9__FUNC_SCL0>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
- mediatek,drive-strength-adv = <0>;
drive-strength = <6>;
};
};
@@ -84,7 +83,6 @@
pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
<PINMUX_GPIO11__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
- mediatek,drive-strength-adv = <0>;
drive-strength = <6>;
};
};
@@ -94,7 +92,7 @@
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
- mediatek,drive-strength-adv = <7>;
+ drive-strength-microamp = <1000>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8195.dtsi b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
index 5d8b68f..2ee4575 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
@@ -3880,7 +3880,7 @@
};
};
- gpu0-thermal {
+ gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
index 50cbaef..4211a99 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
@@ -308,7 +308,7 @@
mmc1_uhs_pins: mmc1-uhs-pins {
clk-pins {
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -319,7 +319,7 @@
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8365.dtsi b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
index 24581f7..eb449bf 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
@@ -300,9 +300,8 @@
};
scpsys: syscon@10006000 {
- compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
+ compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
diff --git a/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
new file mode 100644
index 0000000..1474bef
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Chris Chen <chris-qj.chen@mediatek.com>
+ * Pablo Sun <pablo.sun@mediatek.com>
+ * Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+/dts-v1/;
+
+#include "mt8188.dtsi"
+#include "mt6359.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
+#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/usb/pd.h>
+
+/ {
+ model = "MediaTek Genio-700 EVK";
+ compatible = "mediatek,mt8390-evk", "mediatek,mt8390",
+ "mediatek,mt8188";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0x2 0x00000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: memory@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ apu_mem: memory@55000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
+ };
+
+ vpu_mem: memory@57000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
+ };
+ };
+
+ common_fixed_5v: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_en";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ edp_panel_fixed_3v3: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "edp_panel_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_panel_3v3_en_pins>;
+ };
+
+ gpio_fixed_3v3: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "gpio_3v3_en";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sdio_fixed_1v8: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "sdio_io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sdio_fixed_3v3: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "sdio_card";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 74 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ touch0_fixed_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 119 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_hub_fixed_3v3: regulator-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */
+ startup-delay-us = <10000>;
+ enable-active-high;
+ };
+
+ usb_hub_reset_1v8: regulator-7 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_hub_reset";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */
+ vin-supply = <&usb_hub_fixed_3v3>;
+ };
+
+ usb_p0_vbus: regulator-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_p0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 84 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_p1_vbus: regulator-9 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_p1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 87 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb_p2_vbus: regulator-10 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_p2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt9271";
+ reg = <0x5d>;
+ interrupt-parent = <&pio>;
+ interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>;
+ irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+ AVDD28-supply = <&touch0_fixed_3v3>;
+ VDDIO-supply = <&mt6359_vio18_ldo_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_pins>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&rt1715_int_pins>;
+ clock-frequency = <1000000>;
+ status = "okay";
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x1481b>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ non-removable;
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ no-mmc;
+ no-sdio;
+ cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&mt6359_vpa_buck_reg>;
+ vqmmc-supply = <&mt6359_vsim1_ldo_reg>;
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcn18_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcn33_2_bt_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpa_buck_reg {
+ regulator-max-microvolt = <3100000>;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsim1_ldo_reg {
+ regulator-enable-ramp-delay = <480>;
+};
+
+&mt6359_vufs_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359codec {
+ mediatek,mic-type-0 = <1>; /* ACC */
+ mediatek,mic-type-1 = <3>; /* DCC */
+};
+
+&pio {
+ audio_default_pins: audio-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>,
+ <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>,
+ <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>,
+ <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>,
+ <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>,
+ <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>,
+ <PINMUX_GPIO107__FUNC_B0_I2SIN_MCK>,
+ <PINMUX_GPIO108__FUNC_B0_I2SIN_BCK>,
+ <PINMUX_GPIO109__FUNC_B0_I2SIN_WS>,
+ <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>,
+ <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>,
+ <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>,
+ <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>,
+ <PINMUX_GPIO117__FUNC_O_I2SO2_D0>,
+ <PINMUX_GPIO118__FUNC_O_I2SO2_D1>,
+ <PINMUX_GPIO121__FUNC_B0_PCM_CLK>,
+ <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>,
+ <PINMUX_GPIO124__FUNC_I0_PCM_DI>,
+ <PINMUX_GPIO125__FUNC_O_DMIC1_CLK>,
+ <PINMUX_GPIO126__FUNC_I0_DMIC1_DAT>,
+ <PINMUX_GPIO128__FUNC_O_DMIC2_CLK>,
+ <PINMUX_GPIO129__FUNC_I0_DMIC2_DAT>;
+ };
+ };
+
+ dptx_pins: dptx-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
+ bias-pull-up;
+ };
+ };
+
+ edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {
+ pins1 {
+ pinmux = <PINMUX_GPIO15__FUNC_B_GPIO15>;
+ output-high;
+ };
+ };
+
+ eth_default_pins: eth-default-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
+ <PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
+ <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
+ <PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
+ drive-strength = <8>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
+ <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
+ drive-strength = <8>;
+ input-enable;
+ };
+
+ pins-power {
+ pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
+ <PINMUX_GPIO146__FUNC_B_GPIO146>;
+ output-high;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
+ <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
+ <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
+ <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
+ drive-strength = <8>;
+ };
+
+ pins-txd {
+ pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
+ <PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
+ <PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
+ <PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
+ drive-strength = <8>;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-cc {
+ pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
+ <PINMUX_GPIO140__FUNC_B_GPIO140>,
+ <PINMUX_GPIO141__FUNC_B_GPIO141>,
+ <PINMUX_GPIO142__FUNC_B_GPIO142>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
+ <PINMUX_GPIO144__FUNC_B_GPIO144>;
+ input-disable;
+ bias-disable;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
+ <PINMUX_GPIO136__FUNC_B_GPIO136>,
+ <PINMUX_GPIO137__FUNC_B_GPIO137>,
+ <PINMUX_GPIO138__FUNC_B_GPIO138>;
+ };
+
+ pins-txd {
+ pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
+ <PINMUX_GPIO132__FUNC_B_GPIO132>,
+ <PINMUX_GPIO133__FUNC_B_GPIO133>,
+ <PINMUX_GPIO134__FUNC_B_GPIO134>;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
+ <PINMUX_GPIO55__FUNC_B1_SCL0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
+ <PINMUX_GPIO57__FUNC_B1_SCL1>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins {
+ pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
+ <PINMUX_GPIO59__FUNC_B1_SCL2>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins {
+ pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
+ <PINMUX_GPIO61__FUNC_B1_SCL3>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
+ <PINMUX_GPIO63__FUNC_B1_SCL4>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c5_pins: i2c5-pins {
+ pins {
+ pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
+ <PINMUX_GPIO65__FUNC_B1_SCL5>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
+ <PINMUX_GPIO67__FUNC_B1_SCL6>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ gpio_key_pins: gpio-key-pins {
+ pins {
+ pinmux = <PINMUX_GPIO42__FUNC_B1_KPCOL0>,
+ <PINMUX_GPIO43__FUNC_B1_KPCOL1>,
+ <PINMUX_GPIO44__FUNC_B1_KPROW0>;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>,
+ <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>,
+ <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>,
+ <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>,
+ <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-insert {
+ pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>,
+ <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>,
+ <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>,
+ <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>,
+ <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc2_default_pins: mmc2-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>;
+ drive-strength = <4>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>,
+ <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>,
+ <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>,
+ <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>,
+ <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-pcm {
+ pinmux = <PINMUX_GPIO123__FUNC_O_PCM_DO>;
+ };
+ };
+
+ mmc2_uhs_pins: mmc2-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>;
+ drive-strength = <4>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>,
+ <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>,
+ <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>,
+ <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>,
+ <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc2_eint_pins: mmc2-eint-pins {
+ pins-dat1 {
+ pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc2_dat1_pins: mmc2-dat1-pins {
+ pins-dat1 {
+ pinmux = <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ panel_default_pins: panel-default-pins {
+ pins-dcdc {
+ pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>;
+ output-low;
+ };
+
+ pins-en {
+ pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
+ output-low;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>;
+ output-high;
+ };
+ };
+
+ rt1715_int_pins: rt1715-int-pins {
+ pins_cmd0_dat {
+ pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
+ <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
+ <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
+ <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
+ bias-disable;
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
+ <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
+ <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
+ <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
+ bias-disable;
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
+ <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
+ <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
+ <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
+ bias-disable;
+ };
+ };
+
+ touch_pins: touch-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>;
+ input-enable;
+ bias-disable;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>;
+ output-high;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
+ <PINMUX_GPIO32__FUNC_I1_URXD0>;
+ bias-pull-up;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>,
+ <PINMUX_GPIO34__FUNC_I1_URXD1>;
+ bias-pull-up;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
+ <PINMUX_GPIO36__FUNC_I1_URXD2>;
+ bias-pull-up;
+ };
+ };
+
+ usb_default_pins: usb-default-pins {
+ pins-iddig {
+ pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-valid {
+ pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
+ input-enable;
+ };
+
+ pins-vbus {
+ pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>;
+ output-high;
+ };
+
+ };
+
+ usb1_default_pins: usb1-default-pins {
+ pins-valid {
+ pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>;
+ input-enable;
+ };
+
+ pins-usb-hub-3v3-en {
+ pinmux = <PINMUX_GPIO112__FUNC_B_GPIO112>;
+ output-high;
+ };
+ };
+
+ wifi_pwrseq_pins: wifi-pwrseq-pins {
+ pins-wifi-enable {
+ pinmux = <PINMUX_GPIO127__FUNC_B_GPIO127>;
+ output-low;
+ };
+ };
+};
+
+&pmic {
+ interrupt-parent = <&pio>;
+ interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&scp {
+ memory-region = <&scp_mem>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-0 = <&spi2_pins>;
+ pinctrl-names = "default";
+ mediatek,pad-select = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+};
+
+&u3phy0 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+};
+
+&xhci1 {
+ status = "okay";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ vbus-supply = <&usb_hub_reset_1v8>;
+};
+
+&xhci2 {
+ status = "okay";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
index 1558649..a06610f 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
@@ -475,7 +475,7 @@
<PINMUX_GPIO86__FUNC_GBE_RXC>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
pins-mdio {
@@ -502,7 +502,7 @@
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
};
@@ -567,7 +567,7 @@
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
@@ -582,7 +582,7 @@
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -597,13 +597,13 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -611,7 +611,7 @@
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -626,19 +626,19 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -646,7 +646,7 @@
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -657,7 +657,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -665,7 +665,7 @@
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -676,7 +676,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -854,6 +854,10 @@
&u3phy1 {
status = "okay";
+
+ u3port1: usb-phy@700 {
+ mediatek,force-mode;
+ };
};
&u3phy2 {
@@ -900,6 +904,8 @@
};
&xhci1 {
+ phys = <&u2port1 PHY_TYPE_USB2>,
+ <&u3port1 PHY_TYPE_USB3>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
new file mode 100644
index 0000000..e4b2af9
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
@@ -0,0 +1,1127 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Kontron Europe GmbH
+ *
+ * Author: Michael Walle <mwalle@kernel.org>
+ */
+/dts-v1/;
+
+#include "mt8195.dtsi"
+#include "mt6359.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ model = "Kontron 3.5\"-SBC-i1200";
+ compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195";
+
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+
+ key-0 {
+ gpios = <&pio 106 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-0 {
+ gpios = <&pio 107 GPIO_ACTIVE_HIGH>;
+ default-state = "keep";
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0x0 0x80000000>;
+ };
+
+ vsys: regulator-vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+
+ vpu_mem: memory@53000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_mem: memory@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ snd_dma_mem: memory@60000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60000000 0 0x1100000>;
+ no-map;
+ };
+
+ apu_mem: memory@62000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
+ };
+ };
+
+ thermal_sensor0: thermal-sensor-0 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 0>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = <(-25000) 1474
+ (-20000) 1374
+ (-15000) 1260
+ (-10000) 1134
+ (-5000) 1004
+ 0 874
+ 5000 750
+ 10000 635
+ 15000 532
+ 20000 443
+ 25000 367
+ 30000 303
+ 35000 250
+ 40000 206
+ 45000 170
+ 50000 141
+ 55000 117
+ 60000 97
+ 65000 81
+ 70000 68
+ 75000 57
+ 80000 48
+ 85000 41
+ 90000 35
+ 95000 30
+ 100000 25
+ 105000 22
+ 110000 19
+ 115000 16
+ 120000 14
+ 125000 12
+ 130000 10
+ 135000 9
+ 140000 8
+ 145000 7
+ 150000 6>;
+ };
+
+ thermal_sensor1: thermal-sensor-1 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 1>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = <(-25000) 1474
+ (-20000) 1374
+ (-15000) 1260
+ (-10000) 1134
+ (-5000) 1004
+ 0 874
+ 5000 750
+ 10000 635
+ 15000 532
+ 20000 443
+ 25000 367
+ 30000 303
+ 35000 250
+ 40000 206
+ 45000 170
+ 50000 141
+ 55000 117
+ 60000 97
+ 65000 81
+ 70000 68
+ 75000 57
+ 80000 48
+ 85000 41
+ 90000 35
+ 95000 30
+ 100000 25
+ 105000 22
+ 110000 19
+ 115000 16
+ 120000 14
+ 125000 12
+ 130000 10
+ 135000 9
+ 140000 8
+ 145000 7
+ 150000 6>;
+ };
+
+ thermal_sensor2: thermal-sensor-2 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 2>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = <(-25000) 1474
+ (-20000) 1374
+ (-15000) 1260
+ (-10000) 1134
+ (-5000) 1004
+ 0 874
+ 5000 750
+ 10000 635
+ 15000 532
+ 20000 443
+ 25000 367
+ 30000 303
+ 35000 250
+ 40000 206
+ 45000 170
+ 50000 141
+ 55000 117
+ 60000 97
+ 65000 81
+ 70000 68
+ 75000 57
+ 80000 48
+ 85000 41
+ 90000 35
+ 95000 30
+ 100000 25
+ 105000 22
+ 110000 19
+ 115000 16
+ 120000 14
+ 125000 12
+ 130000 10
+ 135000 9
+ 140000 8
+ 145000 7
+ 150000 6>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+ð {
+ phy-mode ="rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð_default_pins>;
+ pinctrl-1 = <ð_sleep_pins>;
+ status = "okay";
+
+ mdio {
+ ethernet_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&mt6315_7_vbuck1>;
+};
+
+/* CSI1/CSI2 connector */
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+/* CSI3 connector */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* LVDS bridge @f */
+};
+
+/* Touch panel connector */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+/* B2B connector */
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mt6360: pmic@34 {
+ compatible = "mediatek,mt6360";
+ reg = <0x34>;
+ interrupt-controller;
+ interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "IRQB";
+ #interrupt-cells = <1>;
+
+ regulator {
+ compatible = "mediatek,mt6360-regulator";
+ LDO_VIN1-supply = <&vsys>;
+ LDO_VIN2-supply = <&vsys>;
+ LDO_VIN3-supply = <&vsys>;
+
+ mt6360_buck1: BUCK1 {
+ regulator-name = "emi_vdd2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_buck2: BUCK2 {
+ regulator-name = "emi_vddq";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_ldo1: LDO1 {
+ regulator-name = "mt6360_ldo1"; /* Test point */
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo2: LDO2 {
+ regulator-name = "panel1_p1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo3: LDO3 {
+ regulator-name = "vmc_pmu";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo5: LDO5 {
+ regulator-name = "vmch_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo6: LDO6 {
+ regulator-name = "mt6360_ldo6"; /* Test point */
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo7: LDO7 {
+ regulator-name = "emi_vmddr_en";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ hs400-ds-delay = <0x14c11>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ no-sdio;
+ no-sd;
+ non-removable;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>;
+ pinctrl-1 = <&mmc1_default_pins>;
+ cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ no-mmc;
+ vmmc-supply = <&mt6360_ldo5>;
+ vqmmc-supply = <&mt6360_ldo3>;
+ status = "okay";
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc1_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc2_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_others_ldo_reg {
+ regulator-always-on;
+};
+
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins_default>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins_default>;
+ status = "okay";
+};
+
+&pciephy {
+ status = "okay";
+};
+
+&pio {
+ eth_default_pins: eth-default-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <8>;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>;
+ drive-strength = <8>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+
+ pins-power {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+
+ pins-reset {
+ pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+ output-high;
+ };
+
+ pins-interrupt {
+ pinmux = <PINMUX_GPIO94__FUNC_GPIO94>;
+ input-enable;
+ };
+ };
+
+ eth_sleep_pins: eth-sleep-pins {
+ pins-txd {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+
+ pins-cc {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+
+ pins-rxd {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+
+ pins-mdio {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ gpio_keys_pins: gpio-keys-pins {
+ pins {
+ pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
+ input-enable;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c2_pins: i2c2-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
+ <PINMUX_GPIO13__FUNC_SCL2>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins {
+ pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
+ <PINMUX_GPIO15__FUNC_SCL3>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up;
+ drive-strength-microamp = <1000>;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_detect_pins: mmc1-detect-pins {
+ pins-insert {
+ pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
+ bias-pull-up;
+ };
+ };
+
+ nor_pins_default: nor-default-pins {
+ pins-ck-io {
+ pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO141__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ pins-cs {
+ pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_pins_default: pcie0-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
+ <PINMUX_GPIO20__FUNC_PERSTN>,
+ <PINMUX_GPIO21__FUNC_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_pins_default: pcie1-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>,
+ <PINMUX_GPIO1__FUNC_CLKREQN_1>,
+ <PINMUX_GPIO2__FUNC_WAKEN_1>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ led_pins: led-pins {
+ pins-power-en {
+ pinmux = <PINMUX_GPIO107__FUNC_GPIO107>;
+ output-high;
+ };
+ };
+
+ spi0_pins: spi0-default-pins {
+ pins-cs-mosi-clk {
+ pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
+ <PINMUX_GPIO134__FUNC_SPIM0_MO>,
+ <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
+ bias-disable;
+ };
+
+ pins-miso {
+ pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
+ bias-pull-down;
+ };
+ };
+
+ spi1_pins: spi1-default-pins {
+ pins-cs-mosi-clk {
+ pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
+ <PINMUX_GPIO138__FUNC_SPIM1_MO>,
+ <PINMUX_GPIO137__FUNC_SPIM1_CLK>;
+ bias-disable;
+ };
+
+ pins-miso {
+ pinmux = <PINMUX_GPIO139__FUNC_SPIM1_MI>;
+ bias-pull-down;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO99__FUNC_URXD0>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-tx {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO103__FUNC_URXD1>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-tx {
+ pinmux = <PINMUX_GPIO102__FUNC_UTXD1>;
+ };
+
+ pins-rts {
+ pinmux = <PINMUX_GPIO100__FUNC_URTS1>;
+ };
+
+ pins-cts {
+ pinmux = <PINMUX_GPIO101__FUNC_UCTS1>;
+ input-enable;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO68__FUNC_URXD2>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-tx {
+ pinmux = <PINMUX_GPIO67__FUNC_UTXD2>;
+ };
+
+ pins-rts {
+ pinmux = <PINMUX_GPIO66__FUNC_URTS2>;
+ };
+
+ pins-cts {
+ pinmux = <PINMUX_GPIO65__FUNC_UCTS2>;
+ input-enable;
+ };
+ };
+
+ uart3_pins: uart3-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO5__FUNC_URXD3>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-tx {
+ pinmux = <PINMUX_GPIO4__FUNC_UTXD3>;
+ };
+ };
+
+ uart4_pins: uart4-pins {
+ pins-rx {
+ pinmux = <PINMUX_GPIO7__FUNC_URXD4>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-tx {
+ pinmux = <PINMUX_GPIO6__FUNC_UTXD4>;
+ };
+ };
+};
+
+&pmic {
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&scp {
+ memory-region = <&scp_mem>;
+ firmware-name = "mediatek/mt8195/scp.img";
+ status = "okay";
+};
+
+&spmi {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ mt6315@6 {
+ compatible = "mediatek,mt6315-regulator";
+ reg = <0x6 SPMI_USID>;
+
+ regulators {
+ mt6315_6_vbuck1: vbuck1 {
+ regulator-name = "Vbcpu";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-ramp-delay = <6250>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ mt6315@7 {
+ compatible = "mediatek,mt6315-regulator";
+ reg = <0x7 SPMI_USID>;
+
+ regulators {
+ mt6315_7_vbuck1: vbuck1 {
+ regulator-name = "Vgpu";
+ regulator-min-microvolt = <625000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-ramp-delay = <6250>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+/* USB3.2 front port */
+&ssusb0 {
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+/* USB2.0 M.2 Key-E */
+&ssusb2 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+/* USB2.0 to on-board usb hub */
+&ssusb3 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+ tpm: tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* B2B connector */
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&thermal_zones {
+ cpu-thermal {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&thermal_sensor0>;
+
+ trips {
+ trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pcb-top-thermal {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&thermal_sensor1>;
+
+ trips {
+ trip-alert {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-crit {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pcb-bottom-thermal {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&thermal_sensor2>;
+
+ trips {
+ trip-alert {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-crit {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "okay";
+};
+
+/* USB3 */
+&u3phy0 {
+ status = "okay";
+};
+
+/* PCIe1/USB2 */
+&u3phy1 {
+ status = "okay";
+};
+
+/* USB2 */
+&u3phy2 {
+ status = "okay";
+};
+
+/* USB2 */
+&u3phy3 {
+ status = "okay";
+};
+
+/* USB3.2 front port */
+&xhci0 {
+ status = "okay";
+};
+
+/* USB2.0 M.2 Key-B */
+&xhci1 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};
+
+/* USB2.0 M.2 Key-E */
+&xhci2 {
+ status = "okay";
+};
+
+/* USB2.0 to on-board usb hub */
+&xhci3 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
index e5d9b67..4b5f6cf1 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
@@ -140,6 +140,38 @@
};
};
+&cpu0 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu1 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu2 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu3 {
+ cpu-supply = <&mt6359_vcore_buck_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu5 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu6 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
+&cpu7 {
+ cpu-supply = <&mt6315_6_vbuck1>;
+};
+
ð {
phy-mode = "rgmii-rxid";
phy-handle = <&rgmii_phy>;
@@ -343,6 +375,14 @@
};
};
+&mfg0 {
+ domain-supply = <&mt6315_7_vbuck1>;
+};
+
+&mfg1 {
+ domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */
&mmc0 {
pinctrl-names = "default", "state_uhs";
@@ -434,6 +474,8 @@
};
&pio {
+ mediatek,rsel-resistance-in-si-unit;
+
eth_default_pins: eth-default-pins {
pins-cc {
pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
@@ -509,7 +551,7 @@
pins-bus {
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
- bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ bias-pull-up = <1000>;
drive-strength = <6>;
drive-strength-microamp = <1000>;
};
@@ -519,7 +561,7 @@
pins-bus {
pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
<PINMUX_GPIO17__FUNC_SCL4>;
- bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ bias-pull-up = <1000>;
drive-strength-microamp = <1000>;
};
};
@@ -528,7 +570,7 @@
pins {
pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
<PINMUX_GPIO26__FUNC_SCL6>;
- bias-pull-up = <MTK_PULL_SET_RSEL_111>;
+ bias-disable;
};
};
@@ -683,6 +725,26 @@
};
};
+ usb3_port0_pins: usb3p0-default-pins {
+ pins-vbus {
+ pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
+ input-enable;
+ };
+ };
+
+ usb2_port0_pins: usb2p0-default-pins {
+ pins-iddig {
+ pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-vbus {
+ pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>;
+ output-low;
+ };
+ };
+
wifi_vreg_pins: wifi-vreg-pins {
pins-wifi-pmu-en {
pinmux = <PINMUX_GPIO65__FUNC_GPIO65>;
@@ -707,6 +769,10 @@
status = "okay";
};
+&pciephy {
+ status = "okay";
+};
+
&pmic {
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -774,6 +840,18 @@
};
};
+&u3phy0 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
&uart0 {
/* Exposed at 40 pin connector */
pinctrl-0 = <&uart0_pins>;
@@ -789,6 +867,8 @@
};
&ssusb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_port0_pins>;
role-switch-default-mode = "host";
usb-role-switch;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
@@ -802,6 +882,8 @@
};
&ssusb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_port0_pins>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/microchip/sparx5_pcb134_board.dtsi b/dts/upstream/src/arm64/microchip/sparx5_pcb134_board.dtsi
index 2c55747..e60acc7 100644
--- a/dts/upstream/src/arm64/microchip/sparx5_pcb134_board.dtsi
+++ b/dts/upstream/src/arm64/microchip/sparx5_pcb134_board.dtsi
@@ -13,6 +13,20 @@
priority = <200>;
};
+ i2c0_imux: i2c-mux-0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+
+ i2c0_emux: i2c-mux-1 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+
leds {
compatible = "gpio-leds";
led-0 {
@@ -248,6 +262,186 @@
default-state = "off";
};
};
+
+ sfp_eth12: sfp-eth12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth13: sfp-eth13 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth14: sfp-eth14 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth15: sfp-eth15 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth48: sfp-eth48 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp5>;
+ tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth49: sfp-eth49 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp6>;
+ tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth50: sfp-eth50 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp7>;
+ tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth51: sfp-eth51 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp8>;
+ tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth52: sfp-eth52 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp9>;
+ tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth53: sfp-eth53 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp10>;
+ tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth54: sfp-eth54 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp11>;
+ tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth55: sfp-eth55 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp12>;
+ tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth56: sfp-eth56 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp13>;
+ tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth57: sfp-eth57 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp14>;
+ tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth58: sfp-eth58 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp15>;
+ tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth59: sfp-eth59 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp16>;
+ tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp17>;
+ tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp18>;
+ tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp19>;
+ tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp20>;
+ tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ };
};
&sgpio0 {
@@ -385,21 +579,6 @@
};
};
-&axi {
- i2c0_imux: i2c-mux-0 {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-parent = <&i2c0>;
- };
- i2c0_emux: i2c-mux-1 {
- compatible = "i2c-mux-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-parent = <&i2c0>;
- };
-};
-
&i2c0_imux {
pinctrl-names =
"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
@@ -535,169 +714,6 @@
};
};
-&axi {
- sfp_eth12: sfp-eth12 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth13: sfp-eth13 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp2>;
- tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth14: sfp-eth14 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp3>;
- tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth15: sfp-eth15 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp4>;
- tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth48: sfp-eth48 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp5>;
- tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth49: sfp-eth49 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp6>;
- tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth50: sfp-eth50 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp7>;
- tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth51: sfp-eth51 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp8>;
- tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth52: sfp-eth52 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp9>;
- tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth53: sfp-eth53 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp10>;
- tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth54: sfp-eth54 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp11>;
- tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth55: sfp-eth55 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp12>;
- tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth56: sfp-eth56 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp13>;
- tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth57: sfp-eth57 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp14>;
- tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth58: sfp-eth58 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp15>;
- tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth59: sfp-eth59 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp16>;
- tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth60: sfp-eth60 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp17>;
- tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth61: sfp-eth61 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp18>;
- tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth62: sfp-eth62 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp19>;
- tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth63: sfp-eth63 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp20>;
- tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
- los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
- };
-};
-
&switch {
ethernet-ports {
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/microchip/sparx5_pcb135_board.dtsi b/dts/upstream/src/arm64/microchip/sparx5_pcb135_board.dtsi
index af2f183..1968688 100644
--- a/dts/upstream/src/arm64/microchip/sparx5_pcb135_board.dtsi
+++ b/dts/upstream/src/arm64/microchip/sparx5_pcb135_board.dtsi
@@ -13,6 +13,13 @@
priority = <200>;
};
+ i2c0_imux: i2c-mux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+
leds {
compatible = "gpio-leds";
led-0 {
@@ -56,6 +63,46 @@
default-state = "off";
};
};
+
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
+ };
};
&gpio {
@@ -119,15 +166,6 @@
microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
};
-&axi {
- i2c0_imux: i2c-mux {
- compatible = "i2c-mux-pinctrl";
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-parent = <&i2c0>;
- };
-};
-
&i2c0_imux {
pinctrl-names =
"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
@@ -159,45 +197,6 @@
};
};
-&axi {
- sfp_eth60: sfp-eth60 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
- rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth61: sfp-eth61 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp2>;
- tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
- rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth62: sfp-eth62 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp3>;
- tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
- rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
- };
- sfp_eth63: sfp-eth63 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp4>;
- tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
- rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
- };
-};
-
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts
index 1607ee1..82a59e3 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts
+++ b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0000.dts
@@ -1,11 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
+#include "tegra234-p3768-0000+p3767.dtsi"
/ {
compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234";
@@ -29,83 +25,12 @@
status = "okay";
};
- pwm@32a0000 {
- assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
- status = "okay";
- };
-
hda@3510000 {
nvidia,model = "NVIDIA Jetson Orin NX HDA";
};
-
- padctl@3520000 {
- status = "okay";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-force-recovery {
- label = "Force Recovery";
- gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_1>;
- };
-
- key-power {
- label = "Power";
- gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_POWER>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- key-suspend {
- label = "Suspend";
- gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_SLEEP>;
- };
};
- pwm-fan {
- cooling-levels = <0 88 187 255>;
- };
-
- vdd_3v3_pcie: regulator-vdd-3v3-pcie {
- compatible = "regulator-fixed";
- regulator-name = "VDD_3V3_PCIE";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
label = "NVIDIA Jetson Orin NX APE";
};
-
- thermal-zones {
- tj-thermal {
- cooling-maps {
- map-active-0 {
- cooling-device = <&fan 0 1>;
- trip = <&tj_trip_active0>;
- };
-
- map-active-1 {
- cooling-device = <&fan 1 2>;
- trip = <&tj_trip_active1>;
- };
-
- map-active-2 {
- cooling-device = <&fan 2 3>;
- trip = <&tj_trip_active2>;
- };
- };
- };
- };
};
diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts
index dc2d4be..9f5e070 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts
+++ b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767-0005.dts
@@ -1,11 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
+#include "tegra234-p3768-0000+p3767.dtsi"
/ {
compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";
@@ -17,32 +13,7 @@
};
};
- pwm-fan {
- cooling-levels = <0 88 187 255>;
- };
-
sound {
label = "NVIDIA Jetson Orin Nano APE";
};
-
- thermal-zones {
- tj-thermal {
- cooling-maps {
- map-active-0 {
- cooling-device = <&fan 0 1>;
- trip = <&tj_trip_active0>;
- };
-
- map-active-1 {
- cooling-device = <&fan 1 2>;
- trip = <&tj_trip_active1>;
- };
-
- map-active-2 {
- cooling-device = <&fan 2 3>;
- trip = <&tj_trip_active2>;
- };
- };
- };
- };
};
diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi
new file mode 100644
index 0000000..6d64a24
--- /dev/null
+++ b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+#include "tegra234-p3767.dtsi"
+
+/ {
+
+ aliases {
+ serial0 = &tcu;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ bus@0 {
+ i2c@3160000 {
+ status = "okay";
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+
+ label = "system";
+ vcc-supply = <&vdd_1v8_sys>;
+ address-width = <8>;
+ pagesize = <8>;
+ size = <256>;
+ read-only;
+ };
+ };
+
+ serial@31d0000 {
+ current-speed = <115200>;
+ status = "okay";
+ };
+
+ pwm@32a0000 {
+ assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
+ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+ status = "okay";
+ };
+
+ padctl@3520000 {
+ status = "okay";
+
+ pads {
+ usb2 {
+ lanes {
+ usb2-0 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-1 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb2-2 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+ };
+ };
+
+ usb3 {
+ lanes {
+ usb3-0 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+
+ usb3-1 {
+ nvidia,function = "xusb";
+ status = "okay";
+ };
+ };
+ };
+ };
+
+ ports {
+ /* recovery port */
+ usb2-0 {
+ mode = "otg";
+ vbus-supply = <&vdd_5v0_sys>;
+ status = "okay";
+ usb-role-switch;
+ };
+
+ /* hub */
+ usb2-1 {
+ mode = "host";
+ vbus-supply = <&vdd_1v1_hub>;
+ status = "okay";
+ };
+
+ /* M.2 Key-E */
+ usb2-2 {
+ mode = "host";
+ vbus-supply = <&vdd_5v0_sys>;
+ status = "okay";
+ };
+
+ /* hub */
+ usb3-0 {
+ nvidia,usb2-companion = <1>;
+ status = "okay";
+ };
+
+ /* J5 */
+ usb3-1 {
+ nvidia,usb2-companion = <0>;
+ status = "okay";
+ };
+ };
+ };
+
+ usb@3550000 {
+ status = "okay";
+
+ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
+ phy-names = "usb2-0", "usb3-0";
+ };
+
+ usb@3610000 {
+ status = "okay";
+
+ phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+ <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+ <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+ <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
+ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0",
+ "usb3-1";
+ };
+
+ /* C8 - Ethernet */
+ pcie@140a0000 {
+ status = "okay";
+
+ num-lanes = <2>;
+
+ phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
+ phy-names = "p2u-0", "p2u-1";
+
+ vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+ vpcie3v3-supply = <&vdd_3v3_pcie>;
+ };
+
+ /* C1 - M.2 Key-E */
+ pcie@14100000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+ phys = <&p2u_hsio_3>;
+ phy-names = "p2u-0";
+ };
+
+ /* C4 - M.2 Key-M */
+ pcie@14160000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+ phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+ <&p2u_hsio_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+
+ /* C7 - M.2 Key-M */
+ pcie@141e0000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+ phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
+ phy-names = "p2u-0", "p2u-1";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-force-recovery {
+ label = "Force Recovery";
+ gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <BTN_1>;
+ };
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_POWER>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ key-suspend {
+ label = "Suspend";
+ gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_KEY>;
+ linux,code = <KEY_SLEEP>;
+ };
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm3 0 45334>;
+ #cooling-cells = <2>;
+ cooling-levels = <0 88 187 255>;
+ };
+
+ vdd_1v8_sys: regulator-vdd-1v8-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8_SYS";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd_1v1_hub: regulator-vdd-1v1-hub {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_AV10_HUB";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vdd_5v0_sys>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_pcie: regulator-vdd-3v3-pcie {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_PCIE";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ serial {
+ status = "okay";
+ };
+
+ thermal-zones {
+ tj-thermal {
+ cooling-maps {
+ map-active-0 {
+ cooling-device = <&fan 0 1>;
+ trip = <&tj_trip_active0>;
+ };
+
+ map-active-1 {
+ cooling-device = <&fan 1 2>;
+ trip = <&tj_trip_active1>;
+ };
+
+ map-active-2 {
+ cooling-device = <&fan 2 3>;
+ trip = <&tj_trip_active2>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000.dtsi b/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000.dtsi
deleted file mode 100644
index 5d0298b..0000000
--- a/dts/upstream/src/arm64/nvidia/tegra234-p3768-0000.dtsi
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-/ {
- compatible = "nvidia,p3768-0000";
-
- aliases {
- serial0 = &tcu;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- bus@0 {
- i2c@3160000 {
- status = "okay";
-
- eeprom@57 {
- compatible = "atmel,24c02";
- reg = <0x57>;
-
- label = "system";
- vcc-supply = <&vdd_1v8_sys>;
- address-width = <8>;
- pagesize = <8>;
- size = <256>;
- read-only;
- };
- };
-
- serial@31d0000 {
- current-speed = <115200>;
- status = "okay";
- };
-
- pwm@32a0000 {
- assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
- assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
- status = "okay";
- };
-
- padctl@3520000 {
- status = "okay";
-
- pads {
- usb2 {
- lanes {
- usb2-0 {
- nvidia,function = "xusb";
- status = "okay";
- };
-
- usb2-1 {
- nvidia,function = "xusb";
- status = "okay";
- };
-
- usb2-2 {
- nvidia,function = "xusb";
- status = "okay";
- };
- };
- };
-
- usb3 {
- lanes {
- usb3-0 {
- nvidia,function = "xusb";
- status = "okay";
- };
-
- usb3-1 {
- nvidia,function = "xusb";
- status = "okay";
- };
- };
- };
- };
-
- ports {
- /* recovery port */
- usb2-0 {
- mode = "otg";
- vbus-supply = <&vdd_5v0_sys>;
- status = "okay";
- usb-role-switch;
- };
-
- /* hub */
- usb2-1 {
- mode = "host";
- vbus-supply = <&vdd_1v1_hub>;
- status = "okay";
- };
-
- /* M.2 Key-E */
- usb2-2 {
- mode = "host";
- vbus-supply = <&vdd_5v0_sys>;
- status = "okay";
- };
-
- /* hub */
- usb3-0 {
- nvidia,usb2-companion = <1>;
- status = "okay";
- };
-
- /* J5 */
- usb3-1 {
- nvidia,usb2-companion = <0>;
- status = "okay";
- };
- };
- };
-
- usb@3550000 {
- status = "okay";
-
- phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
- phy-names = "usb2-0", "usb3-0";
- };
-
- usb@3610000 {
- status = "okay";
-
- phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
- <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
- <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
- <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
- phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0",
- "usb3-1";
- };
-
- /* C8 - Ethernet */
- pcie@140a0000 {
- status = "okay";
-
- num-lanes = <2>;
-
- phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
- phy-names = "p2u-0", "p2u-1";
-
- vddio-pex-ctl-supply = <&vdd_1v8_ao>;
- vpcie3v3-supply = <&vdd_3v3_pcie>;
- };
-
- /* C1 - M.2 Key-E */
- pcie@14100000 {
- status = "okay";
-
- vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
- phys = <&p2u_hsio_3>;
- phy-names = "p2u-0";
- };
-
- /* C4 - M.2 Key-M */
- pcie@14160000 {
- status = "okay";
-
- vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
- phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
- <&p2u_hsio_7>;
- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
- };
-
- /* C7 - M.2 Key-M */
- pcie@141e0000 {
- status = "okay";
-
- vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
- phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
- phy-names = "p2u-0", "p2u-1";
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-force-recovery {
- label = "Force Recovery";
- gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <BTN_1>;
- };
-
- key-power {
- label = "Power";
- gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_POWER>;
- wakeup-event-action = <EV_ACT_ASSERTED>;
- wakeup-source;
- };
-
- key-suspend {
- label = "Suspend";
- gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_KEY>;
- linux,code = <KEY_SLEEP>;
- };
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- pwms = <&pwm3 0 45334>;
- #cooling-cells = <2>;
- };
-
- vdd_1v8_sys: regulator-vdd-1v8-sys {
- compatible = "regulator-fixed";
- regulator-name = "VDD_1V8_SYS";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- vdd_1v1_hub: regulator-vdd-1v1-hub {
- compatible = "regulator-fixed";
- regulator-name = "VDD_AV10_HUB";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- vin-supply = <&vdd_5v0_sys>;
- regulator-always-on;
- };
-
- vdd_3v3_pcie: regulator-vdd-3v3-pcie {
- compatible = "regulator-fixed";
- regulator-name = "VDD_3V3_PCIE";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- serial {
- status = "okay";
- };
-};
diff --git a/dts/upstream/src/arm64/qcom/apq8016-schneider-hmibsc.dts b/dts/upstream/src/arm64/qcom/apq8016-schneider-hmibsc.dts
new file mode 100644
index 0000000..75c6137
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/apq8016-schneider-hmibsc.dts
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
+
+/ {
+ model = "Schneider Electric HMIBSC Board";
+ compatible = "schneider,apq8016-hmibsc", "qcom,apq8016";
+
+ aliases {
+ i2c1 = &blsp_i2c6;
+ i2c3 = &blsp_i2c4;
+ i2c4 = &blsp_i2c3;
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart1;
+ serial1 = &blsp_uart2;
+ spi0 = &blsp_spi5;
+ usid0 = &pm8916_0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7533_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <&msm_key_volp_n_default>;
+ pinctrl-names = "default";
+
+ button {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pm8916_mpps_leds>;
+ pinctrl-names = "default";
+
+ led-1 {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ reserved-memory {
+ ramoops@bff00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xbff00000 0x0 0x100000>;
+ record-size = <0x20000>;
+ console-size = <0x20000>;
+ ftrace-size = <0x20000>;
+ ecc-size = <16>;
+ };
+ };
+
+ usb-hub {
+ compatible = "smsc,usb3503";
+ reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb_id_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c3 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ adv_bridge: bridge@39 {
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+
+ adi,dsi-lanes = <4>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+ clock-names = "cec";
+ pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+
+ avdd-supply = <&pm8916_l6>;
+ a2vdd-supply = <&pm8916_l6>;
+ dvdd-supply = <&pm8916_l6>;
+ pvdd-supply = <&pm8916_l6>;
+ v1p2-supply = <&pm8916_l6>;
+ v3p3-supply = <&pm8916_l17>;
+
+ pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
+ pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
+ pinctrl-names = "default","sleep";
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7533_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7533_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ rtc@30 {
+ compatible = "sii,s35390a";
+ reg = <0x30>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+&blsp_spi5 {
+ cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+};
+
+&blsp_uart1 {
+ label = "UART0";
+ status = "okay";
+};
+
+&blsp_uart2 {
+ label = "UART1";
+ status = "okay";
+};
+
+&lpass {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&adv7533_in>;
+};
+
+&pm8916_codec {
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+ status = "okay";
+};
+
+&pm8916_gpios {
+ gpio-line-names =
+ "USB_HUB_RESET_N_PM",
+ "USB_SW_SEL_PM",
+ "NC",
+ "NC";
+
+ usb_hub_reset_pm: usb-hub-reset-pm-state {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-disable;
+ output-high;
+ };
+
+ usb_hub_reset_pm_device: usb-hub-reset-pm-device-state {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-disable;
+ output-low;
+ };
+
+ usb_sw_sel_pm: usb-sw-sel-pm-state {
+ pins = "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <PM8916_GPIO_VPH>;
+ input-disable;
+ output-high;
+ };
+
+ usb_sw_sel_pm_device: usb-sw-sel-pm-device-state {
+ pins = "gpio2";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <PM8916_GPIO_VPH>;
+ input-disable;
+ output-low;
+ };
+};
+
+&pm8916_mpps {
+ gpio-line-names =
+ "NC",
+ "WLAN_LED_CTRL",
+ "BT_LED_CTRL",
+ "NC";
+
+ pm8916_mpps_leds: pm8916-mpps-state {
+ pins = "mpp2", "mpp3";
+ function = "digital";
+ output-low;
+ };
+};
+
+&pm8916_resin {
+ linux,code = <KEY_POWER>;
+ status = "okay";
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&sound {
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
+ pinctrl-names = "default", "sleep";
+ model = "HMIBSC";
+ audio-routing =
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+ status = "okay";
+
+ quaternary-dai-link {
+ link-name = "ADV7533";
+ cpu {
+ sound-dai = <&lpass MI2S_QUATERNARY>;
+ };
+ codec {
+ sound-dai = <&adv_bridge 0>;
+ };
+ };
+
+ primary-dai-link {
+ link-name = "WCD";
+ cpu {
+ sound-dai = <&lpass MI2S_PRIMARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
+ };
+ };
+
+ tertiary-dai-link {
+ link-name = "WCD-Capture";
+ cpu {
+ sound-dai = <&lpass MI2S_TERTIARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
+ };
+ };
+};
+
+&tlmm {
+ pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>;
+ pinctrl-names = "default";
+
+ adv7533_int_active: adv533-int-active-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ adv7533_int_suspend: adv7533-int-suspend-state {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ adv7533_switch_active: adv7533-switch-active-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ adv7533_switch_suspend: adv7533-switch-suspend-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ msm_key_volp_n_default: msm-key-volp-n-default-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /*
+ * UART1 being the debug console supports various modes of
+ * operation (RS-232/485/422) controlled via GPIOs configured
+ * mux as follows:
+ *
+ * gpio100 gpio99 UART mode
+ * 0 0 loopback
+ * 0 1 RS-232
+ * 1 0 RS-485
+ * 1 1 RS-422
+ *
+ * The default mode configured here is RS-232 mode.
+ */
+ uart1_mux0_rs232_high: uart1-mux0-rs232-state {
+ bootph-all;
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+
+ uart1_mux1_rs232_low: uart1-mux1-rs232-state {
+ bootph-all;
+ pins = "gpio100";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ usb_id_default: usb-id-default-state {
+ pins = "gpio110";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
+
+&usb {
+ extcon = <&usb_id>, <&usb_id>;
+ pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
+ pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
+ pinctrl-names = "default", "device";
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&wcnss {
+ firmware-name = "qcom/apq8016/wcnss.mbn";
+ status = "okay";
+};
+
+&wcnss_ctrl {
+ firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in msm8916.dtsi */
+
+/*
+ * 2mA drive strength is not enough when connecting multiple
+ * I2C devices with different pull up resistors.
+ */
+&blsp_i2c4_default {
+ drive-strength = <16>;
+};
+
+&blsp_i2c6_default {
+ drive-strength = <16>;
+};
+
+&blsp_uart1_default {
+ bootph-all;
+};
+
+/* Enable CoreSight */
+&cti0 { status = "okay"; };
+&cti1 { status = "okay"; };
+&cti12 { status = "okay"; };
+&cti13 { status = "okay"; };
+&cti14 { status = "okay"; };
+&cti15 { status = "okay"; };
+&debug0 { status = "okay"; };
+&debug1 { status = "okay"; };
+&debug2 { status = "okay"; };
+&debug3 { status = "okay"; };
+&etf { status = "okay"; };
+&etm0 { status = "okay"; };
+&etm1 { status = "okay"; };
+&etm2 { status = "okay"; };
+&etm3 { status = "okay"; };
+&etr { status = "okay"; };
+&funnel0 { status = "okay"; };
+&funnel1 { status = "okay"; };
+&replicator { status = "okay"; };
+&stm { status = "okay"; };
+&tpiu { status = "okay"; };
diff --git a/dts/upstream/src/arm64/qcom/ipq5018-tplink-archer-ax55-v1.dts b/dts/upstream/src/arm64/qcom/ipq5018-tplink-archer-ax55-v1.dts
new file mode 100644
index 0000000..5bb021c
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq5018-tplink-archer-ax55-v1.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "ipq5018.dtsi"
+
+/ {
+ model = "TP-Link Archer AX55 v1";
+ compatible = "tplink,archer-ax55-v1", "qcom,ipq5018";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&led_pins>;
+ pinctrl-names = "default";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-4 {
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-5 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_USB;
+ gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ button-reset {
+ debounce-interval = <60>;
+ gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+
+ button-wps {
+ debounce-interval = <60>;
+ gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ button_pins: button-pins-state {
+ pins = "gpio25", "gpio31";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ led_pins: led-pins-state {
+ pins = "gpio10", "gpio11", "gpio13", "gpio18", "gpio22",
+ "gpio38", "gpio39";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ uart_pins: uart-pins-state {
+ pins = "gpio20", "gpio21";
+ function = "blsp0_uart0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
+
+&xo_board_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/ipq5018.dtsi b/dts/upstream/src/arm64/qcom/ipq5018.dtsi
index 32b178b..7e6e2c1 100644
--- a/dts/upstream/src/arm64/qcom/ipq5018.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5018.dtsi
@@ -179,7 +179,6 @@
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
diff --git a/dts/upstream/src/arm64/qcom/ipq5332.dtsi b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
index 770d9c2..0a74ed4 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
@@ -208,7 +208,6 @@
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
@@ -321,8 +320,8 @@
reg = <0x08af8800 0x400>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
diff --git a/dts/upstream/src/arm64/qcom/ipq6018.dtsi b/dts/upstream/src/arm64/qcom/ipq6018.dtsi
index 17ab6c4..e1e45da 100644
--- a/dts/upstream/src/arm64/qcom/ipq6018.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq6018.dtsi
@@ -396,7 +396,7 @@
};
};
- gcc: gcc@1800000 {
+ gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq6018";
reg = <0x0 0x01800000 0x0 0x80000>;
clocks = <&xo>, <&sleep_clk>;
@@ -457,6 +457,25 @@
};
};
+ sdhc: mmc@7804000 {
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>;
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
+ max-frequency = <192000000>;
+ status = "disabled";
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;
@@ -685,6 +704,7 @@
clocks = <&xo>;
clock-names = "ref";
tx-fifo-resize;
+ snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@@ -923,7 +943,6 @@
thermal-zones {
nss-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
trips {
@@ -937,7 +956,6 @@
nss-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
trips {
@@ -951,7 +969,6 @@
wcss-phya0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
trips {
@@ -979,7 +996,6 @@
cpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
trips {
@@ -1009,7 +1025,6 @@
lpass-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
trips {
@@ -1023,7 +1038,6 @@
ddrss-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/ipq8074.dtsi b/dts/upstream/src/arm64/qcom/ipq8074.dtsi
index 5d42de8..284a455 100644
--- a/dts/upstream/src/arm64/qcom/ipq8074.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq8074.dtsi
@@ -363,7 +363,7 @@
};
};
- gcc: gcc@1800000 {
+ gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
clocks = <&xo>,
@@ -666,6 +666,7 @@
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@@ -715,6 +716,7 @@
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
phys = <&qusb_phy_1>, <&ssphy_1>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@@ -982,7 +984,6 @@
thermal-zones {
nss-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -997,7 +998,6 @@
nss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -1012,7 +1012,6 @@
nss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -1027,7 +1026,6 @@
wcss-phya0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -1042,7 +1040,6 @@
wcss-phya1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -1057,7 +1054,6 @@
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
@@ -1072,7 +1068,6 @@
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 10>;
@@ -1087,7 +1082,6 @@
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 11>;
@@ -1102,7 +1096,6 @@
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 12>;
@@ -1117,7 +1110,6 @@
cluster_thermal: cluster-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
@@ -1132,7 +1124,6 @@
wcss-phyb0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
@@ -1147,7 +1138,6 @@
wcss-phyb1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
diff --git a/dts/upstream/src/arm64/qcom/ipq9574.dtsi b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
index 7f2e5cb..48dfafe 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -232,6 +233,16 @@
clock-names = "core";
};
+ mdio: mdio@90000 {
+ compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
+ reg = <0x00090000 0x64>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+ status = "disabled";
+ };
+
qfprom: efuse@a4000 {
compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x5a1>;
@@ -305,7 +316,7 @@
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
- #power-domain-cells = <1>;
+ #interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
@@ -749,8 +760,6 @@
thermal-zones {
nss-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 3>;
trips {
@@ -763,8 +772,6 @@
};
ubi-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 4>;
trips {
@@ -777,8 +784,6 @@
};
ubi-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 5>;
trips {
@@ -791,8 +796,6 @@
};
ubi-2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 6>;
trips {
@@ -805,8 +808,6 @@
};
ubi-3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 7>;
trips {
@@ -819,8 +820,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 8>;
trips {
@@ -833,8 +832,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 9>;
trips {
@@ -847,8 +844,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 10>;
trips {
@@ -877,8 +872,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 11>;
trips {
@@ -907,8 +900,6 @@
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 12>;
trips {
@@ -937,8 +928,6 @@
};
cpu3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 13>;
trips {
@@ -967,8 +956,6 @@
};
wcss-phyb-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 14>;
trips {
@@ -981,8 +968,6 @@
};
top-glue-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens 15>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/msm8216-samsung-fortuna3g.dts b/dts/upstream/src/arm64/qcom/msm8216-samsung-fortuna3g.dts
index 366914b..fba68bf 100644
--- a/dts/upstream/src/arm64/qcom/msm8216-samsung-fortuna3g.dts
+++ b/dts/upstream/src/arm64/qcom/msm8216-samsung-fortuna3g.dts
@@ -9,3 +9,17 @@
compatible = "samsung,fortuna3g", "qcom,msm8916";
chassis-type = "handset";
};
+
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1000000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
+&st_accel {
+ status = "okay";
+};
+
+&st_magn {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts b/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
index b32c7a9..b4ce14a 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -135,6 +136,17 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x4500000>;
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <150 237 450 500 590>;
+ qcom,mbhc-vthreshold-high = <150 237 450 500 590>;
+ qcom,hphl-jack-type-normally-open;
+};
+
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -170,6 +182,20 @@
status = "okay";
};
+&sound {
+ model = "acer-a1-724";
+ audio-routing =
+ "DMIC1", "MIC BIAS External1",
+ "DMIC1", "Digital Mic1",
+ "AMIC2", "MIC BIAS Internal2",
+ "DMIC2", "MIC BIAS External1",
+ "DMIC2", "Digital Mic2";
+
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default &pri_mi2s_mclk_default &cdc_dmic_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep &pri_mi2s_mclk_sleep &cdc_dmic_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
&usb {
extcon = <&usb_id>, <&usb_id>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-gplus-fl8005a.dts b/dts/upstream/src/arm64/qcom/msm8916-gplus-fl8005a.dts
index b748d14..f7be7e3 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-gplus-fl8005a.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-gplus-fl8005a.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -23,6 +24,28 @@
stdout-path = "serial0";
};
+ battery: battery {
+ compatible = "simple-battery";
+ device-chemistry = "lithium-ion-polymer";
+ voltage-min-design-microvolt = <3700000>;
+ voltage-max-design-microvolt = <4200000>;
+ energy-full-design-microwatt-hours = <13690000>;
+ charge-full-design-microamp-hours = <3700000>;
+
+ ocv-capacity-celsius = <25>;
+ ocv-capacity-table-0 =
+ <4186000 100>, <4126000 95>, <4078000 90>,
+ <4036000 85>, <3997000 80>, <3962000 75>,
+ <3932000 70>, <3904000 65>, <3874000 60>,
+ <3839000 55>, <3809000 50>, <3792000 45>,
+ <3780000 40>, <3772000 35>, <3764000 30>,
+ <3752000 25>, <3731000 20>, <3704000 16>,
+ <3677000 13>, <3670000 11>, <3668000 10>,
+ <3666000 9>, <3662000 8>, <3658000 7>, <3648000 6>,
+ <3624000 5>, <3580000 4>, <3518000 3>, <3434000 2>,
+ <3310000 1>, <3000000 0>;
+ };
+
flash-led-controller {
/* Actually qcom,leds-gpio-flash */
compatible = "sgmicro,sgm3140";
@@ -111,6 +134,22 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5000000>;
+};
+
+&pm8916_bms {
+ monitored-battery = <&battery>;
+ status = "okay";
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <150 180 237 450 500>;
+ qcom,mbhc-vthreshold-high = <150 180 237 450 500>;
+ qcom,hphl-jack-type-normally-open;
+};
+
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -141,6 +180,14 @@
status = "okay";
};
+&sound {
+ model = "msm8916-1mic";
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
&usb {
extcon = <&usb_id>, <&usb_id>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-lg-c50.dts b/dts/upstream/src/arm64/qcom/msm8916-lg-c50.dts
new file mode 100644
index 0000000..a823a1c
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-lg-c50.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "LG Leon LTE";
+ compatible = "lg,c50", "qcom,msm8916";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ volume-up-button {
+ label = "Volume Up";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down-button {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ reg_sd_vmmc: regulator-sdcard-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "sdcard-vmmc";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ startup-delay-us = <5000>;
+
+ pinctrl-0 = <&sd_vmmc_en_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_uart2 {
+ status = "okay";
+};
+
+&pm8916_usbin {
+ status = "okay";
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <®_sd_vmmc>;
+
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+};
+
+&usb {
+ dr_mode = "peripheral";
+ extcon = <&pm8916_usbin>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&pm8916_usbin>;
+};
+
+&venus {
+ status = "okay";
+};
+
+&venus_mem {
+ status = "okay";
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+&tlmm {
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio107", "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sd_vmmc_en_default: sd-vmmc-en-default-state {
+ pins = "gpio60";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-lg-m216.dts b/dts/upstream/src/arm64/qcom/msm8916-lg-m216.dts
new file mode 100644
index 0000000..07345e6
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-lg-m216.dts
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "LG K10 (K420n)";
+ compatible = "lg,m216", "qcom,msm8916";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3300000>;
+ voltage-max-design-microvolt = <4350000>;
+ energy-full-design-microwatt-hours = <8800000>;
+ charge-full-design-microamp-hours = <2300000>;
+
+ ocv-capacity-celsius = <25>;
+ ocv-capacity-table-0 = <4342000 100>, <4266000 95>, <4206000 90>,
+ <4148000 85>, <4094000 80>, <4046000 75>, <3994000 70>,
+ <3956000 65>, <3916000 60>, <3866000 55>, <3831000 50>,
+ <3808000 45>, <3789000 40>, <3776000 35>, <3769000 30>,
+ <3760000 25>, <3740000 20>, <3712000 16>, <3684000 13>,
+ <3676000 11>, <3674000 10>, <3672000 9>, <3669000 8>,
+ <3665000 7>, <3660000 6>, <3643000 5>, <3602000 4>,
+ <3542000 3>, <3458000 2>, <3326000 1>, <3000000 0>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ volume-up-button {
+ label = "Volume Up";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down-button {
+ label = "Volume Down";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ accelerometer@11 {
+ compatible = "bosch,bmc150_accel";
+ reg = <0x11>;
+
+ interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+ };
+
+ magnetometer@13 {
+ compatible = "bosch,bmc150_magn";
+ reg = <0x13>;
+
+ interrupts-extended = <&tlmm 69 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-0 = <&magn_int_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ touchscreen@34 {
+ compatible = "melfas,mip4_ts";
+ reg = <0x34>;
+
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
+ ce-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_uart2 {
+ status = "okay";
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x4a00000>;
+};
+
+&pm8916_bms {
+ monitored-battery = <&battery>;
+ power-supplies = <&pm8916_charger>;
+
+ status = "okay";
+};
+
+&pm8916_charger {
+ qcom,fast-charge-safe-current = <700000>;
+ qcom,fast-charge-safe-voltage = <4300000>;
+
+ monitored-battery = <&battery>;
+ status = "okay";
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
+ qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
+ qcom,hphl-jack-type-normally-open;
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&usb {
+ dr_mode = "peripheral";
+ extcon = <&pm8916_charger>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&pm8916_charger>;
+};
+
+&venus {
+ status = "okay";
+};
+
+&venus_mem {
+ status = "okay";
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio107", "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ magn_int_default: magn-int-default-state {
+ pins = "gpio69";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touchscreen_default: touchscreen-default-state {
+ touchscreen-pins {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ ce-pins {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-motorola-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-motorola-common.dtsi
new file mode 100644
index 0000000..6a27d0e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-motorola-common.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* SD card */
+ serial0 = &blsp_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ volume-up-button {
+ label = "Volume Up";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb_id_default>;
+ pinctrl-1 = <&usb_id_sleep>;
+ pinctrl-names = "default", "sleep";
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ touchscreen: touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vio-supply = <&pm8916_l6>;
+
+ syna,startup-delay-ms = <100>;
+
+ rmi4-f01@1 {
+ reg = <1>;
+ syna,nosleep-mode = <1>; /* Allow sleeping */
+ };
+
+ rmi4-f11@11 {
+ reg = <11>;
+ syna,sensor-type = <1>; /* Touchscreen */
+ };
+ };
+};
+
+&blsp_uart1 {
+ status = "okay";
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5500000>;
+};
+
+&pm8916_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l16: l16 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ status = "okay";
+};
+
+&usb {
+ extcon = <&usb_id>, <&usb_id>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&venus {
+ status = "okay";
+};
+
+&venus_mem {
+ status = "okay";
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+/* CTS/RTX are not used */
+&blsp_uart1_default {
+ pins = "gpio0", "gpio1";
+};
+&blsp_uart1_sleep {
+ pins = "gpio0", "gpio1";
+};
+
+&tlmm {
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ usb_id_default: usb-id-default-state {
+ pins = "gpio91";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ usb_id_sleep: usb-id-sleep-state {
+ pins = "gpio91";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-motorola-harpia.dts b/dts/upstream/src/arm64/qcom/msm8916-motorola-harpia.dts
new file mode 100644
index 0000000..8380451
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-motorola-harpia.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-motorola-common.dtsi"
+
+/ {
+ model = "Motorola Moto G4 Play";
+ compatible = "motorola,harpia", "qcom,msm8916";
+ chassis-type = "handset";
+};
+
+&blsp_i2c1 {
+ status = "okay";
+
+ battery@36 {
+ compatible = "maxim,max17050";
+ reg = <0x36>;
+
+ interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&battery_alert_default>;
+ pinctrl-names = "default";
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,cold-temp = <(-200)>;
+ maxim,dead-volt = <3200>;
+ maxim,over-volt = <4500>;
+ };
+
+ /* charger@6b */
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ accelerometer@19 {
+ compatible = "bosch,bma253";
+ reg = <0x19>;
+
+ interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>,
+ <&tlmm 119 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "1";
+
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+ };
+
+ /* proximity@49 */
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+ qcom,micbias1-ext-cap;
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
+ pinctrl-0 = <&cdc_pdm_default &headset_switch_supply_en
+ &headset_switch_in>;
+ pinctrl-1 = <&cdc_pdm_sleep &headset_switch_supply_en
+ &headset_switch_in>;
+ pinctrl-names = "default", "sleep";
+};
+
+&touchscreen {
+ interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l16>;
+
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-names = "default";
+};
+
+&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio115", "gpio119";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ battery_alert_default: battery-alert-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ headset_switch_in: headset-switch-in-state {
+ pins = "gpio112";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ headset_switch_supply_en: headset-switch-supply-en-state {
+ pins = "gpio111";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio118";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-motorola-osprey.dts b/dts/upstream/src/arm64/qcom/msm8916-motorola-osprey.dts
new file mode 100644
index 0000000..ec5589f
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-motorola-osprey.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-motorola-common.dtsi"
+
+/ {
+ model = "Motorola Moto G 2015";
+ compatible = "motorola,osprey", "qcom,msm8916";
+ chassis-type = "handset";
+
+ reg_touch_vdda: regulator-touch-vdda {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_vdda";
+ gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&touch_vdda_default>;
+ pinctrl-names = "default";
+ startup-delay-us = <300>;
+ vin-supply = <&pm8916_l16>;
+ };
+};
+
+&blsp_i2c1 {
+ status = "okay";
+
+ battery@36 {
+ compatible = "maxim,max17050";
+ reg = <0x36>;
+
+ interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&battery_alert_default>;
+ pinctrl-names = "default";
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,cold-temp = <(-200)>;
+ maxim,dead-volt = <3200>;
+ maxim,over-volt = <4500>;
+
+ };
+};
+
+&blsp_i2c6 {
+ /* magnetometer@c */
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias2-ext-cap;
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&touchscreen {
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <®_touch_vdda>;
+
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-names = "default";
+};
+
+&tlmm {
+ battery_alert_default: battery-alert-default-state {
+ pins = "gpio49";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touch_vdda_default: touch-vdda-default-state {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-motorola-surnia.dts b/dts/upstream/src/arm64/qcom/msm8916-motorola-surnia.dts
new file mode 100644
index 0000000..eecf78b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-motorola-surnia.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8916-motorola-common.dtsi"
+
+/ {
+ model = "Motorola Moto E 2015 LTE";
+ compatible = "motorola,surnia", "qcom,msm8916";
+ chassis-type = "handset";
+};
+
+&blsp_i2c4 {
+ status = "okay";
+
+ battery@36 {
+ compatible = "maxim,max17050";
+ reg = <0x36>;
+
+ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&battery_alert_default>;
+ pinctrl-names = "default";
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,cold-temp = <(-200)>;
+ maxim,dead-volt = <3200>;
+ maxim,over-volt = <4500>;
+
+ };
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias2-ext-cap;
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+};
+
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC3", "MIC BIAS External1";
+};
+
+&touchscreen {
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l16>;
+
+ pinctrl-0 = <&ts_int_default>;
+ pinctrl-names = "default";
+};
+
+&tlmm {
+ battery_alert_default: battery-alert-default-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
index 4bbbee8..e6355e5 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
@@ -28,6 +28,12 @@
};
};
+ battery: battery {
+ compatible = "simple-battery";
+ precharge-current-microamp = <450000>;
+ precharge-upper-limit-microvolt = <3500000>;
+ };
+
clk_pwm: pwm {
compatible = "clk-pwm";
#pwm-cells = <2>;
@@ -245,7 +251,7 @@
&blsp_i2c4 {
status = "okay";
- battery@35 {
+ fuel-gauge@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
interrupt-parent = <&tlmm>;
@@ -253,9 +259,47 @@
pinctrl-names = "default";
pinctrl-0 = <&fg_alert_default>;
+
+ power-supplies = <&charger>;
};
};
+&blsp_i2c6 {
+ status = "okay";
+
+ pmic@34 {
+ compatible = "richtek,rt5033";
+ reg = <0x34>;
+
+ interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&pmic_int_default>;
+ pinctrl-names = "default";
+
+ regulators {
+ rt5033_reg_safe_ldo: SAFE_LDO {
+ regulator-min-microvolt = <4900000>;
+ regulator-max-microvolt = <4900000>;
+ regulator-always-on;
+ };
+
+ /*
+ * Needed for camera, but not used yet.
+ * Define empty nodes to allow disabling the unused
+ * regulators.
+ */
+ LDO {};
+ BUCK {};
+ };
+
+ charger: charger {
+ compatible = "richtek,rt5033-charger";
+ monitored-battery = <&battery>;
+ richtek,usb-connector = <&usb_con>;
+ };
+ };
+};
+
&blsp_uart2 {
status = "okay";
};
@@ -476,6 +520,13 @@
bias-disable;
};
+ pmic_int_default: pmic-int-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
index 3b934f5..906d31f 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
@@ -55,6 +55,12 @@
"0", "0", "1";
};
+&battery {
+ charge-term-current-microamp = <150000>;
+ constant-charge-current-max-microamp = <1000000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
&blsp_i2c5 {
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
index 391befa..fe39be7 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
@@ -29,6 +29,12 @@
"0", "0", "1";
};
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1500000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
&blsp_i2c5 {
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-e5.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-e5.dts
index fad2535..800cb10 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-e5.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-e5.dts
@@ -23,6 +23,12 @@
chassis-type = "handset";
};
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1500000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
&blsp_i2c5 {
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-e7.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-e7.dts
index b412b61..ec1debd 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-e7.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-e7.dts
@@ -23,6 +23,13 @@
chassis-type = "handset";
};
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1500000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
+
&pm8916_l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi
index 5e933fb..81b3e07 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-fortuna-common.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
@@ -26,6 +27,12 @@
};
};
+ battery: battery {
+ compatible = "simple-battery";
+ precharge-current-microamp = <450000>;
+ precharge-upper-limit-microvolt = <3500000>;
+ };
+
clk_pwm_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&clk_pwm 0 100000>;
@@ -78,6 +85,35 @@
max-microvolt = <3300000>;
};
+ i2c_nfc: i2c-nfc {
+ compatible = "i2c-gpio";
+ sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-0 = <&nfc_i2c_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ s3fwrn5_nfc: nfc@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+ reg = <0x27>;
+
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>;
+
+ en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+ pinctrl-0 = <&nfc_default>, <&nfc_clk_req>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
reg_motor_vdd: regulator-motor-vdd {
compatible = "regulator-fixed";
regulator-name = "motor_vdd";
@@ -114,9 +150,85 @@
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
+
+ usb_con: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
};
};
+&blsp_i2c2 {
+ /* Available sensors vary depending on model variant */
+ status = "okay";
+
+ bosch_accel: accelerometer@10 {
+ compatible = "bosch,bmc150_accel";
+ reg = <0x10>;
+ interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l5>;
+ vddio-supply = <&pm8916_l5>;
+
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ status = "disabled";
+ };
+
+ bosch_magn: magnetometer@12 {
+ compatible = "bosch,bmc150_magn";
+ reg = <0x12>;
+
+ vdd-supply = <&pm8916_l5>;
+ vddio-supply = <&pm8916_l5>;
+
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ status = "disabled";
+ };
+
+ st_accel: accelerometer@1d {
+ compatible = "st,lsm303c-accel";
+ reg = <0x1d>;
+ interrupts-extended = <&tlmm 115 IRQ_TYPE_LEVEL_HIGH>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+
+ st,drdy-int-pin = <1>;
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+
+ status = "disabled";
+ };
+
+ st_magn: magnetometer@1e {
+ compatible = "st,lsm303c-magn";
+ reg = <0x1e>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+
+ status = "disabled";
+ };
+};
+
&blsp_i2c4 {
status = "okay";
@@ -128,6 +240,8 @@
pinctrl-0 = <&fg_alert_default>;
pinctrl-names = "default";
+
+ power-supplies = <&charger>;
};
};
@@ -148,6 +262,42 @@
pinctrl-0 = <&tsp_int_default>;
pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ pmic@34 {
+ compatible = "richtek,rt5033";
+ reg = <0x34>;
+
+ interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&pmic_int_default>;
+ pinctrl-names = "default";
+
+ regulators {
+ rt5033_reg_safe_ldo: SAFE_LDO {
+ regulator-min-microvolt = <4900000>;
+ regulator-max-microvolt = <4900000>;
+ regulator-always-on;
+ };
+
+ /*
+ * Needed for camera, but not used yet.
+ * Define empty nodes to allow disabling the unused
+ * regulators.
+ */
+ LDO {};
+ BUCK {};
+ };
+
+ charger: charger {
+ compatible = "richtek,rt5033-charger";
+ monitored-battery = <&battery>;
+ richtek,usb-connector = <&usb_con>;
+ };
};
};
@@ -223,6 +373,13 @@
};
&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
backlight_en_default: backlight-en-default-state {
pins = "gpio98";
function = "gpio";
@@ -263,6 +420,36 @@
bias-disable;
};
+ nfc_default: nfc-default-state {
+ irq-pins {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ nfc-pins {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ nfc_i2c_default: nfc-i2c-default-state {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pmic_int_default: pmic-int-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc2_cd_default: sdc2-cd-default-state {
pins = "gpio38";
function = "gpio";
@@ -282,5 +469,15 @@
function = "gpio";
drive-strength = <2>;
bias-disable;
+ };
+};
+
+&pm8916_gpios {
+ nfc_clk_req: nfc-clk-req-state {
+ pins = "gpio2";
+ function = "func1";
+ power-source = <PM8916_GPIO_L2>;
+ bias-disable;
+ input-enable;
};
};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts
index 9d65fa5..677e4e2 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-gprimeltecan.dts
@@ -21,6 +21,76 @@
};
};
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1000000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
+&bosch_accel {
+ status = "okay";
+};
+
+&bosch_magn {
+ status = "okay";
+};
+
+&blsp_i2c6 {
+ /* pmic@34 is on i2c_nfc instead */
+ /delete-node/ pmic@34;
+
+ nfc@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+ reg = <0x27>;
+
+ interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>;
+
+ en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+ pinctrl-0 = <&nfc_default>, <&nfc_clk_req>;
+ pinctrl-names = "default";
+ };
+};
+
+&i2c_nfc {
+ /* nfc@27 is on &blsp_i2c6 */
+
+ pmic@34 {
+ compatible = "richtek,rt5033";
+ reg = <0x34>;
+
+ interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&pmic_int_default>;
+ pinctrl-names = "default";
+
+ regulators {
+ rt5033_reg_safe_ldo: SAFE_LDO {
+ regulator-min-microvolt = <4900000>;
+ regulator-max-microvolt = <4900000>;
+ regulator-always-on;
+ };
+
+ /*
+ * Needed for camera, but not used yet.
+ * Define empty nodes to allow disabling the unused
+ * regulators.
+ */
+ LDO {};
+ BUCK {};
+ };
+
+ charger: charger {
+ compatible = "richtek,rt5033-charger";
+ monitored-battery = <&battery>;
+ richtek,usb-connector = <&usb_con>;
+ };
+ };
+};
+
&mpss_mem {
/* Firmware for gprimeltecan needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
index 5882b3a..135df17 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
@@ -41,6 +41,12 @@
};
};
+&battery {
+ charge-term-current-microamp = <150000>;
+ constant-charge-current-max-microamp = <1000000>;
+ constant-charge-voltage-max-microvolt = <4400000>;
+};
+
®_motor_vdd {
gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandprimelte.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandprimelte.dts
index a66ce4b..582bfcb 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandprimelte.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandprimelte.dts
@@ -10,6 +10,20 @@
chassis-type = "handset";
};
+&battery {
+ charge-term-current-microamp = <200000>;
+ constant-charge-current-max-microamp = <1000000>;
+ constant-charge-voltage-max-microvolt = <4350000>;
+};
+
+&bosch_accel {
+ status = "okay";
+};
+
+&bosch_magn {
+ status = "okay";
+};
+
&mpss_mem {
/* Firmware for grandprimelte needs more space */
reg = <0x0 0x86800000 0x0 0x5400000>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi
index b438fa8..e7f265e 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa-common.dtsi
@@ -15,6 +15,12 @@
interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-0 = <&muic_int_default>;
pinctrl-names = "default";
+
+ usb_con: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
};
};
@@ -26,3 +32,15 @@
&clk_pwm_backlight {
status = "disabled";
};
+
+&s3fwrn5_nfc {
+ status = "okay";
+};
+
+&st_accel {
+ compatible = "st,lis2hh12";
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "1";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts
index ebaa13c..1981bb7 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-rossa.dts
@@ -10,6 +10,12 @@
chassis-type = "handset";
};
+&battery {
+ charge-term-current-microamp = <150000>;
+ constant-charge-current-max-microamp = <700000>;
+ constant-charge-voltage-max-microvolt = <4400000>;
+};
+
&mpss_mem {
/* Firmware for rossa needs more space */
reg = <0x0 0x86800000 0x0 0x5800000>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916.dtsi b/dts/upstream/src/arm64/qcom/msm8916.dtsi
index cedff41..7383bcc 100644
--- a/dts/upstream/src/arm64/qcom/msm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916.dtsi
@@ -308,7 +308,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
@@ -360,7 +360,7 @@
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -385,7 +385,7 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -410,8 +410,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -1978,7 +1977,7 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
- qcom,ipc = <&apcs 8 12>;
+ mboxes = <&apcs 12>;
qcom,remote-pid = <1>;
label = "hexagon";
@@ -2459,7 +2458,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 17>;
+ mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -2626,7 +2625,6 @@
thermal-zones {
cpu0-1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -2656,7 +2654,6 @@
cpu2-3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -2686,7 +2683,6 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
@@ -2713,7 +2709,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
@@ -2728,7 +2723,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
diff --git a/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts b/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
index 0c599e7..91acdb1 100644
--- a/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
+++ b/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
@@ -33,6 +33,15 @@
};
};
+ battery: battery {
+ compatible = "simple-battery";
+ charge-term-current-microamp = <150000>;
+ constant-charge-current-max-microamp = <1500000>;
+ constant-charge-voltage-max-microvolt = <4300000>;
+ precharge-current-microamp = <450000>;
+ precharge-upper-limit-microvolt = <3500000>;
+ };
+
gpio-hall-sensor {
compatible = "gpio-keys";
@@ -82,7 +91,7 @@
#address-cells = <1>;
#size-cells = <0>;
- battery@35 {
+ fuel-gauge@35 {
compatible = "richtek,rt5033-battery";
reg = <0x35>;
@@ -91,6 +100,8 @@
pinctrl-0 = <&fg_alert_default>;
pinctrl-names = "default";
+
+ power-supplies = <&charger>;
};
};
@@ -322,6 +333,42 @@
pinctrl-0 = <&tsp_int_default>;
pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ pmic@34 {
+ compatible = "richtek,rt5033";
+ reg = <0x34>;
+
+ interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&pmic_int_default>;
+ pinctrl-names = "default";
+
+ regulators {
+ rt5033_reg_safe_ldo: SAFE_LDO {
+ regulator-min-microvolt = <4900000>;
+ regulator-max-microvolt = <4900000>;
+ regulator-always-on;
+ };
+
+ /*
+ * Needed for camera, but not used yet.
+ * Define empty nodes to allow disabling the unused
+ * regulators.
+ */
+ LDO {};
+ BUCK {};
+ };
+
+ charger: charger {
+ compatible = "richtek,rt5033-charger";
+ monitored-battery = <&battery>;
+ richtek,usb-connector = <&usb_con>;
+ };
};
};
@@ -510,6 +557,13 @@
bias-disable;
};
+ pmic_int_default: pmic-int-default-state {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
reg_tsp_en_default: reg-tsp-en-default-state {
pins = "gpio73";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8939.dtsi b/dts/upstream/src/arm64/qcom/msm8939.dtsi
index dd45975..46d9480 100644
--- a/dts/upstream/src/arm64/qcom/msm8939.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8939.dtsi
@@ -248,7 +248,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs1_mbox 8 0>;
+ mboxes = <&apcs1_mbox 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
@@ -443,8 +443,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs1_mbox 8 13>;
- qcom,ipc-3 = <&apcs1_mbox 8 19>;
+ mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -2067,7 +2066,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs1_mbox 8 17>;
+ mboxes = <&apcs1_mbox 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -2299,7 +2298,6 @@
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -2330,7 +2328,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -2361,7 +2358,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -2392,7 +2388,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -2423,7 +2418,6 @@
cpu4567-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
@@ -2454,7 +2448,6 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
@@ -2482,7 +2475,6 @@
modem1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -2497,7 +2489,6 @@
modem2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
@@ -2512,7 +2503,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
diff --git a/dts/upstream/src/arm64/qcom/msm8953-motorola-potter.dts b/dts/upstream/src/arm64/qcom/msm8953-motorola-potter.dts
index 711d84d..2edf804 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-motorola-potter.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-motorola-potter.dts
@@ -301,5 +301,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-daisy.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-daisy.dts
index a5957e7..336b916 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-daisy.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-daisy.dts
@@ -321,5 +321,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
index 6b9245c..bdf1bfc 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
@@ -326,5 +326,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
index 9ac4f50..fccb9c4 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
@@ -322,5 +322,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
index b0588f3..d46325e 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
@@ -357,5 +357,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8953.dtsi b/dts/upstream/src/arm64/qcom/msm8953.dtsi
index 5d818fe..a4bfb62 100644
--- a/dts/upstream/src/arm64/qcom/msm8953.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8953.dtsi
@@ -195,7 +195,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
@@ -361,7 +361,7 @@
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -386,7 +386,7 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -411,8 +411,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -1267,7 +1266,7 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
- qcom,ipc = <&apcs 8 12>;
+ mboxes = <&apcs 12>;
qcom,remote-pid = <1>;
label = "modem";
@@ -1748,7 +1747,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 17>;
+ mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -1968,8 +1967,9 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 9>;
+
trips {
cpu0_alert: trip-point0 {
temperature = <80000>;
@@ -1991,8 +1991,9 @@
};
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 10>;
+
trips {
cpu1_alert: trip-point0 {
temperature = <80000>;
@@ -2014,8 +2015,9 @@
};
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 11>;
+
trips {
cpu2_alert: trip-point0 {
temperature = <80000>;
@@ -2037,8 +2039,9 @@
};
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 12>;
+
trips {
cpu3_alert: trip-point0 {
temperature = <80000>;
@@ -2060,7 +2063,6 @@
};
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
trips {
cpu4_alert: trip-point0 {
@@ -2083,7 +2085,6 @@
};
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
cpu5_alert: trip-point0 {
@@ -2106,7 +2107,6 @@
};
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
cpu6_alert: trip-point0 {
@@ -2129,7 +2129,6 @@
};
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cpu7_alert: trip-point0 {
@@ -2153,7 +2152,6 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/msm8956.dtsi b/dts/upstream/src/arm64/qcom/msm8956.dtsi
index 668e051..fa36b62 100644
--- a/dts/upstream/src/arm64/qcom/msm8956.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8956.dtsi
@@ -8,8 +8,8 @@
#include "msm8976.dtsi"
-&pmu {
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+&pmu_a72 {
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
};
&tsens {
diff --git a/dts/upstream/src/arm64/qcom/msm8976.dtsi b/dts/upstream/src/arm64/qcom/msm8976.dtsi
index d2bb1ad..d62dcb7 100644
--- a/dts/upstream/src/arm64/qcom/msm8976.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8976.dtsi
@@ -222,11 +222,17 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
- pmu: pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ pmu_a72: pmu-a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -237,7 +243,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
@@ -361,7 +367,7 @@
smp2p-hexagon {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 10>;
+ mboxes = <&apcs 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
@@ -384,7 +390,7 @@
smp2p-modem {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -407,7 +413,7 @@
smp2p-wcnss {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -433,9 +439,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-2 = <&apcs 8 9>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -771,6 +775,36 @@
drive-strength = <2>;
bias-disable;
};
+
+ wcss_wlan_default: wcss-wlan-default-state {
+ wcss-wlan2-pins {
+ pins = "gpio40";
+ function = "wcss_wlan2";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan1-pins {
+ pins = "gpio41";
+ function = "wcss_wlan1";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan0-pins {
+ pins = "gpio42";
+ function = "wcss_wlan0";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ wcss-wlan-pins {
+ pins = "gpio43", "gpio44";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
};
gcc: clock-controller@1800000 {
@@ -785,10 +819,10 @@
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
- <0>,
- <0>,
- <0>,
- <0>;
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&mdss_dsi1_phy 0>;
clock-names = "xo",
"xo_a",
"dsi0pll",
@@ -808,6 +842,430 @@
reg = <0x01937000 0x30000>;
};
+ mdss: display-subsystem@1a00000 {
+ compatible = "qcom,mdss";
+
+ reg = <0x01a00000 0x1000>,
+ <0x01ab0000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ power-domains = <&gcc MDSS_GDSC>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync",
+ "core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@1a01000 {
+ compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
+ reg = <0x01a01000 0x89000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDP_TBU_CLK>,
+ <&gcc GCC_MDP_RT_TBU_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync",
+ "tbu",
+ "tbu_rt";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&gcc MDSS_GDSC>;
+
+ iommus = <&apps_iommu 22>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_mdp5_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_mdp5_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-177780000 {
+ opp-hz = /bits/ 64 <177780000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@1a94000 {
+ compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x01a94000 0x300>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE0_CLK>,
+ <&gcc GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
+ <&gcc GCC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&gcc MDSS_GDSC>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-161250000 {
+ opp-hz = /bits/ 64 <161250000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi1: dsi@1a96000 {
+ compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x01a96000 0x300>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE1_CLK>,
+ <&gcc GCC_MDSS_PCLK1_CLK>,
+ <&gcc GCC_MDSS_ESC1_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+
+ assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
+ <&gcc GCC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ operating-points-v2 = <&dsi0_opp_table>;
+ power-domains = <&gcc MDSS_GDSC>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&mdss_mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@1a94a00 {
+ compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
+ reg = <0x01a94a00 0xd4>,
+ <0x01a94400 0x280>,
+ <0x01a94b80 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1_phy: phy@1a96a00 {
+ compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
+ reg = <0x01a96a00 0xd4>,
+ <0x01a96400 0x280>,
+ <0x01a96b80 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ adreno_gpu: gpu@1c00000 {
+ compatible = "qcom,adreno-510.0", "qcom,adreno";
+
+ reg = <0x01c00000 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
+ <&gcc GCC_GFX3D_OXILI_AHB_CLK>,
+ <&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
+ <&gcc GCC_GFX3D_BIMC_CLK>,
+ <&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
+ <&gcc GCC_GFX3D_OXILI_AON_CLK>;
+ clock-names = "core",
+ "iface",
+ "mem",
+ "mem_iface",
+ "rbbmtimer",
+ "alwayson";
+
+ power-domains = <&gcc OXILI_GX_GDSC>;
+
+ iommus = <&gpu_iommu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmpd_opp_nom_plus>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ opp-supported-hw = <0xff>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ opp-supported-hw = <0xff>;
+ };
+ };
+ };
+
+ apps_iommu: iommu@1ee0000 {
+ compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
+ reg = <0x01ee0000 0x3000>;
+ ranges = <0 0x01e20000 0x20000>;
+
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+
+ qcom,iommu-secure-id = <17>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+
+ /* VFE */
+ iommu-ctx@15000 {
+ compatible = "qcom,msm-iommu-v2-ns";
+ reg = <0x15000 0x1000>;
+ qcom,ctx-asid = <20>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* VENUS NS */
+ iommu-ctx@16000 {
+ compatible = "qcom,msm-iommu-v2-ns";
+ reg = <0x16000 0x1000>;
+ qcom,ctx-asid = <21>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* MDP0 */
+ iommu-ctx@17000 {
+ compatible = "qcom,msm-iommu-v2-ns";
+ reg = <0x17000 0x1000>;
+ qcom,ctx-asid = <22>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
+ ranges = <0 0x01f08000 0x8000>;
+
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX3D_TCU_CLK>;
+ clock-names = "iface", "bus";
+
+ power-domains = <&gcc OXILI_CX_GDSC>;
+
+ qcom,iommu-secure-id = <18>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+
+ /* gfx3d user */
+ iommu-ctx@0 {
+ compatible = "qcom,msm-iommu-v2-ns";
+ reg = <0x0 0x1000>;
+ qcom,ctx-asid = <0>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* gfx3d secure */
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v2-sec";
+ reg = <0x1000 0x1000>;
+ qcom,ctx-asid = <2>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* gfx3d priv */
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v2-sec";
+ reg = <0x2000 0x1000>;
+ qcom,ctx-asid = <1>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x1000>,
@@ -1032,6 +1490,81 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ };
+
+ wcnss: remoteproc@a204000 {
+ compatible = "qcom,pronto-v3-pil", "qcom,pronto";
+ reg = <0x0a204000 0x2000>,
+ <0x0a202000 0x1000>,
+ <0x0a21b000 0x3000>;
+ reg-names = "ccu",
+ "dxe",
+ "pmu";
+
+ memory-region = <&wcnss_fw_mem>;
+
+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ power-domains = <&rpmpd MSM8976_VDDCX>,
+ <&rpmpd MSM8976_VDDMX>;
+ power-domain-names = "cx", "mx";
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ pinctrl-0 = <&wcss_wlan_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+
+ wcnss_iris: iris {
+ /* Separate chip, compatible is board-specific */
+ clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+ clock-names = "xo";
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss_ctrl: wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&wcnss>;
+
+ wcnss_bt: bluetooth {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wcnss_wifi: wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>,
+ <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable",
+ "tx-rings-empty";
+ };
+ };
+ };
};
intc: interrupt-controller@b000000 {
@@ -1124,7 +1657,6 @@
thermal-zones {
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -1139,7 +1671,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
trips {
@@ -1153,7 +1684,6 @@
qdsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
trips {
@@ -1167,7 +1697,6 @@
cam-isp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
trips {
@@ -1181,7 +1710,7 @@
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 4>;
trips {
@@ -1205,7 +1734,7 @@
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 5>;
trips {
@@ -1229,7 +1758,7 @@
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 6>;
trips {
@@ -1253,7 +1782,7 @@
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 7>;
trips {
@@ -1277,7 +1806,7 @@
big-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 8>;
trips {
@@ -1301,7 +1830,7 @@
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 9>;
trips {
@@ -1325,7 +1854,7 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens 10>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/msm8994.dtsi b/dts/upstream/src/arm64/qcom/msm8994.dtsi
index 695e541..917fa24 100644
--- a/dts/upstream/src/arm64/qcom/msm8994.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8994.dtsi
@@ -183,7 +183,7 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
qcom,remote-pid = <6>;
@@ -300,7 +300,7 @@
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 10>;
+ mboxes = <&apcs 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
@@ -325,7 +325,7 @@
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -1093,10 +1093,10 @@
timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 0xff08>,
- <GIC_PPI 3 0xff08>,
- <GIC_PPI 4 0xff08>,
- <GIC_PPI 1 0xff08>;
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
vph_pwr: vph-pwr-regulator {
diff --git a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-common.dtsi b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-common.dtsi
index 5ab583b..0386636 100644
--- a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-common.dtsi
@@ -405,7 +405,6 @@
&hsusb_phy1 {
status = "okay";
- extcon = <&typec>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
diff --git a/dts/upstream/src/arm64/qcom/msm8996.dtsi b/dts/upstream/src/arm64/qcom/msm8996.dtsi
index 8d2cb6f..0fd2b1b 100644
--- a/dts/upstream/src/arm64/qcom/msm8996.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8996.dtsi
@@ -982,6 +982,8 @@
<&mmcc MDSS_MDP_CLK>;
clock-names = "iface", "core";
+ resets = <&mmcc MDSS_BCR>;
+
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -2077,24 +2079,20 @@
power-domains = <&gcc UFS_GDSC>;
clock-names =
- "core_clk_src",
"core_clk",
"bus_clk",
"bus_aggr_clk",
"iface_clk",
- "core_clk_unipro_src",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
- <&gcc UFS_AXI_CLK_SRC>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
- <&gcc UFS_ICE_CORE_CLK_SRC>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_ICE_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
@@ -2105,10 +2103,8 @@
<0 0>,
<0 0>,
<0 0>,
- <0 0>,
- <150000000 300000000>,
<75000000 150000000>,
- <0 0>,
+ <150000000 300000000>,
<0 0>,
<0 0>,
<0 0>;
@@ -2483,6 +2479,13 @@
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ label = "dsps";
+ qcom,remote-pid = <3>;
+ mboxes = <&apcs_glb 27>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
@@ -2552,6 +2555,13 @@
memory-region = <&mdata_mem>;
};
+ glink-edge {
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 15>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
@@ -3091,6 +3101,7 @@
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,is-utmi-l1-suspend;
+ snps,parkmode-disable-ss-quirk;
tx-fifo-resize;
};
};
@@ -3497,6 +3508,14 @@
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ mboxes = <&apcs_glb 9>;
+ };
+
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
@@ -3553,6 +3572,63 @@
};
};
};
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,smd-channels = "fastrpcsmd-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&lpass_q6_smmu 5>;
+ };
+
+ cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&lpass_q6_smmu 6>;
+ };
+
+ cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&lpass_q6_smmu 7>;
+ };
+
+ cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&lpass_q6_smmu 8>;
+ };
+
+ cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&lpass_q6_smmu 9>;
+ };
+
+ cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&lpass_q6_smmu 10>;
+ };
+
+ cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&lpass_q6_smmu 11>;
+ };
+
+ cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&lpass_q6_smmu 12>;
+ };
+ };
};
};
@@ -3654,7 +3730,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -3675,7 +3750,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -3696,7 +3770,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -3717,7 +3790,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -3738,7 +3810,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -3760,7 +3831,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -3782,7 +3852,6 @@
m4m-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -3797,7 +3866,6 @@
l3-or-venus-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -3812,7 +3880,6 @@
cluster0-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -3827,7 +3894,6 @@
cluster1-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -3842,7 +3908,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -3857,7 +3922,6 @@
q6-dsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -3872,7 +3936,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -3887,7 +3950,6 @@
modemtx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
diff --git a/dts/upstream/src/arm64/qcom/msm8998.dtsi b/dts/upstream/src/arm64/qcom/msm8998.dtsi
index d795b2b..7f44807 100644
--- a/dts/upstream/src/arm64/qcom/msm8998.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8998.dtsi
@@ -488,7 +488,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -509,7 +508,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -530,7 +528,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -551,7 +548,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -572,7 +568,6 @@
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -593,7 +588,6 @@
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -614,7 +608,6 @@
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -635,7 +628,6 @@
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -656,7 +648,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -671,7 +662,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
@@ -686,7 +676,6 @@
clust0-mhm-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -701,7 +690,6 @@
clust1-mhm-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -716,7 +704,6 @@
cluster1-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -731,7 +718,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -746,7 +732,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -761,7 +746,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -776,7 +760,6 @@
q6-dsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -791,7 +774,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -806,7 +788,6 @@
multimedia-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -1590,7 +1571,6 @@
* SoC VDDMX RPM Power Domain in the Adreno driver.
*/
power-domains = <&gpucc GPU_GX_GDSC>;
- status = "disabled";
};
gpucc: clock-controller@5065000 {
@@ -2164,6 +2144,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&qusb2phy>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,has-lpm-erratum;
@@ -3020,6 +3001,54 @@
};
};
+ venus: video-codec@cc00000 {
+ compatible = "qcom,msm8998-venus";
+ reg = <0x0cc00000 0xff000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc VIDEO_TOP_GDSC>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc VIDEO_MAXI_CLK>;
+ clock-names = "core", "iface", "bus", "mbus";
+ iommus = <&mmss_smmu 0x400>,
+ <&mmss_smmu 0x401>,
+ <&mmss_smmu 0x40a>,
+ <&mmss_smmu 0x407>,
+ <&mmss_smmu 0x40e>,
+ <&mmss_smmu 0x40f>,
+ <&mmss_smmu 0x408>,
+ <&mmss_smmu 0x409>,
+ <&mmss_smmu 0x40b>,
+ <&mmss_smmu 0x40c>,
+ <&mmss_smmu 0x40d>,
+ <&mmss_smmu 0x410>,
+ <&mmss_smmu 0x421>,
+ <&mmss_smmu 0x428>,
+ <&mmss_smmu 0x429>,
+ <&mmss_smmu 0x42b>,
+ <&mmss_smmu 0x42c>,
+ <&mmss_smmu 0x42d>,
+ <&mmss_smmu 0x411>,
+ <&mmss_smmu 0x431>;
+ memory-region = <&venus_mem>;
+ status = "disabled";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
+ };
+ };
+
mmss_smmu: iommu@cd00000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x0cd00000 0x40000>;
@@ -3195,6 +3224,7 @@
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
qcom,snoc-host-cap-8bit-quirk;
+ qcom,no-msa-ready-indicator;
};
};
};
diff --git a/dts/upstream/src/arm64/qcom/pm6125.dtsi b/dts/upstream/src/arm64/qcom/pm6125.dtsi
index 99369a0..d0db283 100644
--- a/dts/upstream/src/arm64/qcom/pm6125.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm6125.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm6125-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm6150.dtsi b/dts/upstream/src/arm64/qcom/pm6150.dtsi
index 6de6ed5..5952460 100644
--- a/dts/upstream/src/arm64/qcom/pm6150.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm6150.dtsi
@@ -13,7 +13,7 @@
thermal-zones {
pm6150_thermal: pm6150-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm6150_temp>;
trips {
@@ -166,5 +166,11 @@
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ pm6150_vib: vibrator@5300 {
+ compatible = "qcom,pm6150-vib", "qcom,pmi632-vib";
+ reg = <0x5300>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/upstream/src/arm64/qcom/pm6150l.dtsi b/dts/upstream/src/arm64/qcom/pm6150l.dtsi
index 0fce452..334f976 100644
--- a/dts/upstream/src/arm64/qcom/pm6150l.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm6150l.dtsi
@@ -10,9 +10,6 @@
/ {
thermal-zones {
pm6150l-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm6150l_temp>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm6350.dtsi b/dts/upstream/src/arm64/qcom/pm6350.dtsi
index 3a2a841..a20ee24 100644
--- a/dts/upstream/src/arm64/qcom/pm6350.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm6350.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm6350-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm6350_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm660.dtsi b/dts/upstream/src/arm64/qcom/pm660.dtsi
index 98dc049..156b2dd 100644
--- a/dts/upstream/src/arm64/qcom/pm660.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm660.dtsi
@@ -13,7 +13,6 @@
thermal-zones {
pm660-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&pm660_temp>;
@@ -74,6 +73,23 @@
};
};
+ pm660_charger: charger@1000 {
+ compatible = "qcom,pm660-charger";
+ reg = <0x1000>;
+
+ interrupts = <0x0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "usb-plugin", "bat-ov", "wdog-bark", "usbin-icl-change";
+
+ io-channels = <&pm660_rradc 3>,
+ <&pm660_rradc 4>;
+ io-channel-names = "usbin_i", "usbin_v";
+
+ status = "disabled";
+ };
+
pm660_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
@@ -181,6 +197,14 @@
};
};
+ pm660_rradc: adc@4500 {
+ compatible = "qcom,pm660-rradc";
+ reg = <0x4500>;
+ #io-channel-cells = <1>;
+
+ status = "disabled";
+ };
+
pm660_gpios: gpio@c000 {
compatible = "qcom,pm660-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
diff --git a/dts/upstream/src/arm64/qcom/pm660l.dtsi b/dts/upstream/src/arm64/qcom/pm660l.dtsi
index 6fdbf50..0094e0e 100644
--- a/dts/upstream/src/arm64/qcom/pm660l.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm660l.dtsi
@@ -13,7 +13,6 @@
thermal-zones {
pm660l-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&pm660l_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm7250b.dtsi b/dts/upstream/src/arm64/qcom/pm7250b.dtsi
index 3bf7cf5..0761e6b 100644
--- a/dts/upstream/src/arm64/qcom/pm7250b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm7250b.dtsi
@@ -11,7 +11,6 @@
thermal-zones {
pm7250b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm7250b_temp>;
@@ -45,6 +44,52 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm7250b_vbus: usb-vbus-regulator@1100 {
+ compatible = "qcom,pm7250b-vbus-reg", "qcom,pm8150b-vbus-reg";
+ reg = <0x1100>;
+ status = "disabled";
+ };
+
+ pm7250b_typec: typec@1500 {
+ compatible = "qcom,pm7250b-typec", "qcom,pm8150b-typec";
+ reg = <0x1500>,
+ <0x1700>;
+ interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x03 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x04 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x05 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x15 0x06 IRQ_TYPE_EDGE_BOTH>,
+ <PM7250B_SID 0x15 0x07 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x00 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x01 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x02 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x03 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x04 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x05 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x06 IRQ_TYPE_EDGE_RISING>,
+ <PM7250B_SID 0x17 0x07 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "or-rid-detect-change",
+ "vpd-detect",
+ "cc-state-change",
+ "vconn-oc",
+ "vbus-change",
+ "attach-detach",
+ "legacy-cable-detect",
+ "try-snk-src-detect",
+ "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded",
+ "fr-swap";
+ vdd-vbus-supply = <&pm7250b_vbus>;
+ status = "disabled";
+ };
+
pm7250b_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
diff --git a/dts/upstream/src/arm64/qcom/pm7325.dtsi b/dts/upstream/src/arm64/qcom/pm7325.dtsi
index d1c5476..6e29468 100644
--- a/dts/upstream/src/arm64/qcom/pm7325.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm7325.dtsi
@@ -35,7 +35,7 @@
&thermal_zones {
pm7325_thermal: pm7325-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm7325_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm7550ba.dtsi b/dts/upstream/src/arm64/qcom/pm7550ba.dtsi
index 8b00ece..853a1d8 100644
--- a/dts/upstream/src/arm64/qcom/pm7550ba.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm7550ba.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm7550ba-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm7550ba_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8010.dtsi b/dts/upstream/src/arm64/qcom/pm8010.dtsi
index 0ea641e..ef33019 100644
--- a/dts/upstream/src/arm64/qcom/pm8010.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8010.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8010-m-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8010_m_temp_alarm>;
@@ -31,7 +30,6 @@
pm8010-n-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8010_n_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8150.dtsi b/dts/upstream/src/arm64/qcom/pm8150.dtsi
index 3ba3ba5..a74a7ff 100644
--- a/dts/upstream/src/arm64/qcom/pm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8150.dtsi
@@ -13,7 +13,6 @@
thermal-zones {
pm8150-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm8150b.dtsi b/dts/upstream/src/arm64/qcom/pm8150b.dtsi
index 1aee327..3f7b0b6 100644
--- a/dts/upstream/src/arm64/qcom/pm8150b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8150b.dtsi
@@ -12,7 +12,6 @@
thermal-zones {
pm8150b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8150b_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm8150l.dtsi b/dts/upstream/src/arm64/qcom/pm8150l.dtsi
index ac08a09..3911d6d 100644
--- a/dts/upstream/src/arm64/qcom/pm8150l.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8150l.dtsi
@@ -12,7 +12,6 @@
thermal-zones {
pm8150l-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm8350.dtsi b/dts/upstream/src/arm64/qcom/pm8350.dtsi
index 9ed9ba2..cb55b23 100644
--- a/dts/upstream/src/arm64/qcom/pm8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8350.dtsi
@@ -10,7 +10,7 @@
thermal-zones {
pm8350_thermal: pm8350-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm8350_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm8350b.dtsi b/dts/upstream/src/arm64/qcom/pm8350b.dtsi
index 05c1058..cf82f8a 100644
--- a/dts/upstream/src/arm64/qcom/pm8350b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8350b.dtsi
@@ -10,7 +10,7 @@
thermal-zones {
pm8350b_thermal: pm8350b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm8350b_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm8350c.dtsi b/dts/upstream/src/arm64/qcom/pm8350c.dtsi
index aa74e21..1a24e64 100644
--- a/dts/upstream/src/arm64/qcom/pm8350c.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8350c.dtsi
@@ -48,7 +48,7 @@
thermal-zones {
pm8350c_thermal: pm8350c-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm8350c_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm8450.dtsi b/dts/upstream/src/arm64/qcom/pm8450.dtsi
index ae5bce3..decb880 100644
--- a/dts/upstream/src/arm64/qcom/pm8450.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8450.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8450-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8450_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8550.dtsi b/dts/upstream/src/arm64/qcom/pm8550.dtsi
index 797a18c..896bcac 100644
--- a/dts/upstream/src/arm64/qcom/pm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8550-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8550b.dtsi b/dts/upstream/src/arm64/qcom/pm8550b.dtsi
index 72609f3..74d23b8 100644
--- a/dts/upstream/src/arm64/qcom/pm8550b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550b.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8550b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550b_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8550ve.dtsi b/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
index 4dc1f03..9d4734e 100644
--- a/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8550ve-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550ve_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8550vs.dtsi b/dts/upstream/src/arm64/qcom/pm8550vs.dtsi
index 97b1c18..6426b43 100644
--- a/dts/upstream/src/arm64/qcom/pm8550vs.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550vs.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pm8550vs-c-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_c_temp_alarm>;
@@ -31,7 +30,6 @@
pm8550vs-d-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_d_temp_alarm>;
@@ -52,7 +50,6 @@
pm8550vs-e-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_e_temp_alarm>;
@@ -73,7 +70,6 @@
pm8550vs-g-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pm8550vs_g_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pm8916.dtsi b/dts/upstream/src/arm64/qcom/pm8916.dtsi
index 4b2e8fb..f8e4829 100644
--- a/dts/upstream/src/arm64/qcom/pm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8916.dtsi
@@ -4,8 +4,37 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-&spmi_bus {
+/ {
+ thermal-zones {
+ pm8916-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8916_temp>;
+
+ trips {
+ trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
pm8916_0: pmic@0 {
compatible = "qcom,pm8916", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
diff --git a/dts/upstream/src/arm64/qcom/pm8953.dtsi b/dts/upstream/src/arm64/qcom/pm8953.dtsi
index 1067e14..6425850 100644
--- a/dts/upstream/src/arm64/qcom/pm8953.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8953.dtsi
@@ -9,9 +9,6 @@
/ {
thermal-zones {
pm8953-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm8953_temp>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pm8994.dtsi b/dts/upstream/src/arm64/qcom/pm8994.dtsi
index d44a95c..353e4a6 100644
--- a/dts/upstream/src/arm64/qcom/pm8994.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8994.dtsi
@@ -8,7 +8,6 @@
thermal-zones {
pm8994-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&pm8994_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pm8998.dtsi b/dts/upstream/src/arm64/qcom/pm8998.dtsi
index 3f82715..3ecb330 100644
--- a/dts/upstream/src/arm64/qcom/pm8998.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8998.dtsi
@@ -11,7 +11,6 @@
thermal-zones {
pm8998-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&pm8998_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pmi632.dtsi b/dts/upstream/src/arm64/qcom/pmi632.dtsi
index 94d53b1..8c899d1 100644
--- a/dts/upstream/src/arm64/qcom/pmi632.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmi632.dtsi
@@ -11,7 +11,6 @@
thermal-zones {
pmi632-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmi632_temp>;
@@ -200,5 +199,11 @@
status = "disabled";
};
+
+ pmi632_vib: vibrator@5700 {
+ compatible = "qcom,pmi632-vib";
+ reg = <0x5700>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/upstream/src/arm64/qcom/pmi8950.dtsi b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
index 1029f3b..b4822cb 100644
--- a/dts/upstream/src/arm64/qcom/pmi8950.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
@@ -84,6 +84,14 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmi8950_pwm: pwm@b000 {
+ compatible = "qcom,pmi8950-pwm";
+ reg = <0xb000 0x100>;
+ #pwm-cells = <2>;
+
+ status = "disabled";
+ };
+
pmi8950_wled: leds@d800 {
compatible = "qcom,pmi8950-wled";
reg = <0xd800>, <0xd900>;
diff --git a/dts/upstream/src/arm64/qcom/pmm8155au_1.dtsi b/dts/upstream/src/arm64/qcom/pmm8155au_1.dtsi
index dbd4b91..5084de6 100644
--- a/dts/upstream/src/arm64/qcom/pmm8155au_1.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmm8155au_1.dtsi
@@ -12,7 +12,6 @@
thermal-zones {
pmm8155au-1-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmm8155au_1_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pmm8155au_2.dtsi b/dts/upstream/src/arm64/qcom/pmm8155au_2.dtsi
index 1cee20a..555e4a4 100644
--- a/dts/upstream/src/arm64/qcom/pmm8155au_2.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmm8155au_2.dtsi
@@ -11,7 +11,6 @@
thermal-zones {
pmm8155au-2-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmm8155au_2_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pmr735a.dtsi b/dts/upstream/src/arm64/qcom/pmr735a.dtsi
index febda50..f8efd8e 100644
--- a/dts/upstream/src/arm64/qcom/pmr735a.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmr735a.dtsi
@@ -36,7 +36,7 @@
thermal-zones {
pmr735a_thermal: pmr735a-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmr735a_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pmr735b.dtsi b/dts/upstream/src/arm64/qcom/pmr735b.dtsi
index f7473e2..09affc0 100644
--- a/dts/upstream/src/arm64/qcom/pmr735b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmr735b.dtsi
@@ -10,7 +10,7 @@
thermal-zones {
pmr735b_thermal: pmr735b-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmr735b_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/pmr735d_a.dtsi b/dts/upstream/src/arm64/qcom/pmr735d_a.dtsi
index 37daaef..f9f1793 100644
--- a/dts/upstream/src/arm64/qcom/pmr735d_a.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmr735d_a.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pmr735d-k-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmr735d_k_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pmr735d_b.dtsi b/dts/upstream/src/arm64/qcom/pmr735d_b.dtsi
index 3b470f6..d91fbd3 100644
--- a/dts/upstream/src/arm64/qcom/pmr735d_b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmr735d_b.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pmr735d-l-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmr735d_l_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/pms405.dtsi b/dts/upstream/src/arm64/qcom/pms405.dtsi
index 461ad97..3f9100c 100644
--- a/dts/upstream/src/arm64/qcom/pms405.dtsi
+++ b/dts/upstream/src/arm64/qcom/pms405.dtsi
@@ -12,7 +12,6 @@
thermal-zones {
pms405-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&pms405_temp>;
diff --git a/dts/upstream/src/arm64/qcom/pmx75.dtsi b/dts/upstream/src/arm64/qcom/pmx75.dtsi
index 373e45f..2e61b78 100644
--- a/dts/upstream/src/arm64/qcom/pmx75.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmx75.dtsi
@@ -10,7 +10,6 @@
thermal-zones {
pmx75-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmx75_temp_alarm>;
diff --git a/dts/upstream/src/arm64/qcom/qcm2290.dtsi b/dts/upstream/src/arm64/qcom/qcm2290.dtsi
index 106110a..8f3be4c 100644
--- a/dts/upstream/src/arm64/qcom/qcm2290.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcm2290.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -758,6 +759,11 @@
reg = <0x25b 0x1>;
bits = <1 4>;
};
+
+ gpu_speed_bin: gpu-speed-bin@2006 {
+ reg = <0x2006 0x2>;
+ bits = <5 8>;
+ };
};
pmu@1b8e300 {
@@ -1425,6 +1431,154 @@
};
};
+ gpu: gpu@5900000 {
+ compatible = "qcom,adreno-07000200", "qcom,adreno";
+ reg = <0x0 0x05900000 0x0 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>;
+ clock-names = "core",
+ "iface",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo";
+
+ interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0 1>,
+ <&adreno_smmu 2 0>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+ qcom,gmu = <&gmu_wrapper>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */
+ opp-1123200000 {
+ opp-hz = /bits/ 64 <1123200000>;
+ required-opps = <&rpmpd_opp_turbo_plus>;
+ opp-peak-kBps = <6881000>;
+ opp-supported-hw = <0x3>;
+ turbo-mode;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ opp-peak-kBps = <6881000>;
+ opp-supported-hw = <0x3>;
+ turbo-mode;
+ };
+
+ opp-921600000 {
+ opp-hz = /bits/ 64 <921600000>;
+ required-opps = <&rpmpd_opp_nom_plus>;
+ opp-peak-kBps = <6881000>;
+ opp-supported-hw = <0x3>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <6881000>;
+ opp-supported-hw = <0x7>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <3879000>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ required-opps = <&rpmpd_opp_svs>;
+ opp-peak-kBps = <2929000>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-355200000 {
+ opp-hz = /bits/ 64 <355200000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <1720000>;
+ opp-supported-hw = <0xf>;
+ };
+ };
+ };
+
+ gmu_wrapper: gmu@596a000 {
+ compatible = "qcom,adreno-gmu-wrapper";
+ reg = <0x0 0x0596a000 0x0 0x30000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ };
+
+ gpucc: clock-controller@5990000 {
+ compatible = "qcom,qcm2290-gpucc";
+ reg = <0x0 0x05990000 0x0 0x9000>;
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@59a0000 {
+ compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x059a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ clock-names = "mem",
+ "hlos",
+ "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ };
+
mdss: display-subsystem@5e00000 {
compatible = "qcom,qcm2290-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
@@ -1924,9 +2078,6 @@
thermal-zones {
mapss-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 0>;
trips {
@@ -1951,9 +2102,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 1>;
trips {
@@ -1978,9 +2126,6 @@
};
wlan-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 2>;
trips {
@@ -2005,9 +2150,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 3>;
trips {
@@ -2032,9 +2174,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 4>;
trips {
@@ -2059,9 +2198,6 @@
};
mdm0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 5>;
trips {
@@ -2086,9 +2222,6 @@
};
mdm1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 6>;
trips {
@@ -2113,9 +2246,6 @@
};
gpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 7>;
trips {
@@ -2140,9 +2270,6 @@
};
hm-center-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 8>;
trips {
@@ -2167,9 +2294,6 @@
};
camera-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 9>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
index f343270..8ab30c0 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
@@ -167,7 +167,7 @@
thermal-zones {
camera-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 2>;
trips {
@@ -181,7 +181,7 @@
chg-skin-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pm7250b_adc_tm 0>;
trips {
@@ -195,7 +195,7 @@
conn-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pm7250b_adc_tm 1>;
trips {
@@ -207,9 +207,28 @@
};
};
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
quiet-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 1>;
trips {
@@ -223,7 +242,7 @@
rear-cam-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 4>;
trips {
@@ -237,7 +256,7 @@
sdm-skin-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 3>;
trips {
@@ -251,7 +270,7 @@
xo-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 0>;
trips {
@@ -271,46 +290,54 @@
qcom,pmic-id = "b";
vreg_s1b: smps1 {
+ regulator-name = "vreg_s1b";
regulator-min-microvolt = <1840000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7b: smps7 {
+ regulator-name = "vreg_s7b";
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
};
vreg_s8b: smps8 {
+ regulator-name = "vreg_s8b";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
};
vreg_l1b: ldo1 {
+ regulator-name = "vreg_l1b";
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b: ldo2 {
+ regulator-name = "vreg_l2b";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b: ldo3 {
+ regulator-name = "vreg_l3b";
regulator-min-microvolt = <312000>;
regulator-max-microvolt = <910000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b: ldo6 {
+ regulator-name = "vreg_l6b";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b: ldo7 {
+ regulator-name = "vreg_l7b";
/* Constrained for UFS VCC, at least until UFS driver scales voltage */
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <2952000>;
@@ -318,66 +345,77 @@
};
vreg_l8b: ldo8 {
+ regulator-name = "vreg_l8b";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b: ldo9 {
+ regulator-name = "vreg_l9b";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11b: ldo11 {
+ regulator-name = "vreg_l11b";
regulator-min-microvolt = <1504000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12b: ldo12 {
+ regulator-name = "vreg_l12b";
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13b: ldo13 {
+ regulator-name = "vreg_l13b";
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <824000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14b: ldo14 {
+ regulator-name = "vreg_l14b";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15b: ldo15 {
+ regulator-name = "vreg_l15b";
regulator-min-microvolt = <765000>;
regulator-max-microvolt = <1020000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16b: ldo16 {
+ regulator-name = "vreg_l16b";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17b: ldo17 {
+ regulator-name = "vreg_l17b";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18b: ldo18 {
+ regulator-name = "vreg_l18b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19b: ldo19 {
+ regulator-name = "vreg_l19b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -389,60 +427,70 @@
qcom,pmic-id = "c";
vreg_s1c: smps1 {
+ regulator-name = "vreg_s1c";
regulator-min-microvolt = <2190000>;
regulator-max-microvolt = <2210000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9c: smps9 {
+ regulator-name = "vreg_s9c";
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 {
+ regulator-name = "vreg_l1c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c: ldo3 {
+ regulator-name = "vreg_l3c";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3400000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
+ regulator-name = "vreg_l4c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c: ldo5 {
+ regulator-name = "vreg_l5c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
+ regulator-name = "vreg_l6c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
+ regulator-name = "vreg_l7c";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
+ regulator-name = "vreg_l8c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -451,36 +499,42 @@
};
vreg_l9c: ldo9 {
+ regulator-name = "vreg_l9c";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c: ldo10 {
+ regulator-name = "vreg_l10c";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c: ldo11 {
+ regulator-name = "vreg_l11c";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c: ldo12 {
+ regulator-name = "vreg_l12c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c: ldo13 {
+ regulator-name = "vreg_l13c";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob: bob {
+ regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
@@ -522,7 +576,76 @@
&i2c1 {
status = "okay";
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pm8350c_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s8b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_s1b>;
+ vdd-l7-supply = <&vreg_bob>;
+
- /* PM8008 PMIC @ 8 and 9 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1152000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1904000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+
/* Pixelworks @ 26 */
/* FSA4480 USB audio switch @ 42 */
/* AW86927FCR haptics @ 5a */
@@ -551,7 +674,7 @@
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
- firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mdt";
+ firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn";
status = "okay";
};
@@ -653,6 +776,14 @@
};
};
+&pm8350c_gpios {
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+};
+
&pmk8350_rtc {
status = "okay";
};
@@ -810,6 +941,13 @@
bias-pull-up;
};
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
pins = "gpio28";
function = "gpio";
@@ -864,7 +1002,6 @@
};
&uart5 {
- compatible = "qcom,geni-debug-uart";
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
index 47ca2d0..a0668f7 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
@@ -658,7 +658,6 @@
};
&uart5 {
- compatible = "qcom,geni-debug-uart";
status = "okay";
};
@@ -667,6 +666,7 @@
};
&usb_1_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
new file mode 100644
index 0000000..4667e47
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
@@ -0,0 +1,961 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Luca Weiss <luca.weiss@fairphone.com>
+ * Copyright (c) 2024, Caleb Connolly <caleb@postmarketos.org>
+ */
+
+/dts-v1/;
+
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sc7280.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/delete-node/ &rmtfs_mem;
+
+/ {
+ model = "SHIFT SHIFTphone 8";
+ compatible = "shift,otter", "qcom,qcm6490";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ serial1 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ framebuffer0: framebuffer@a000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>;
+ width = <1080>;
+ height = <2400>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_down_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ cont_splash_mem: cont-splash@e1000000 {
+ reg = <0x0 0xe1000000 0x0 0x2300000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@88f00000 {
+ reg = <0x0 0x88f00000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@f8500000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xf8500000 0x0 0x600000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>, <QCOM_SCM_VMID_NAV>;
+ };
+ };
+
+ thermal-zones {
+ camera-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 2>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ chg-skin-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7250b_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7250b_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-cam-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 4>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vreg_s1b: smps1 {
+ regulator-name = "vreg_s1b";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7b: smps7 {
+ regulator-name = "vreg_s7b";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b: smps8 {
+ regulator-name = "vreg_s8b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b: ldo1 {
+ regulator-name = "vreg_l1b";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b: ldo2 {
+ regulator-name = "vreg_l2b";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b: ldo3 {
+ regulator-name = "vreg_l3b";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b: ldo6 {
+ regulator-name = "vreg_l6b";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b: ldo7 {
+ regulator-name = "vreg_l7b";
+ /* Constrained for UFS VCC, at least until UFS driver scales voltage */
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b: ldo8 {
+ regulator-name = "vreg_l8b";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b: ldo9 {
+ regulator-name = "vreg_l9b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b: ldo11 {
+ regulator-name = "vreg_l11b";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b: ldo12 {
+ regulator-name = "vreg_l12b";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b: ldo13 {
+ regulator-name = "vreg_l13b";
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b: ldo14 {
+ regulator-name = "vreg_l14b";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b: ldo15 {
+ regulator-name = "vreg_l15b";
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b: ldo16 {
+ regulator-name = "vreg_l16b";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b: ldo17 {
+ regulator-name = "vreg_l17b";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b: ldo18 {
+ regulator-name = "vreg_l18b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b: ldo19 {
+ regulator-name = "vreg_l19b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_s1c: smps1 {
+ regulator-name = "vreg_s1c";
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9c: smps9 {
+ regulator-name = "vreg_s9c";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c: ldo1 {
+ regulator-name = "vreg_l1c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c: ldo3 {
+ regulator-name = "vreg_l3c";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c: ldo4 {
+ regulator-name = "vreg_l4c";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c: ldo5 {
+ regulator-name = "vreg_l5c";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c: ldo6 {
+ regulator-name = "vreg_l6c";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c: ldo7 {
+ regulator-name = "vreg_l7c";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c: ldo8 {
+ regulator-name = "vreg_l8c";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c: ldo9 {
+ regulator-name = "vreg_l9c";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c: ldo10 {
+ regulator-name = "vreg_l10c";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c: ldo11 {
+ regulator-name = "vreg_l11c";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c: ldo12 {
+ regulator-name = "vreg_l12c";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c: ldo13 {
+ regulator-name = "vreg_l13c";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_EDP_CLKREF_EN>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcm6490/SHIFT/otter/a660_zap.mbn";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* PM8008 PMIC @ 8 and 9 */
+ /* rtc6226 FM receiver @ 64 */
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* tas2563 audio codec @ 4d */
+};
+
+&i2c9 {
+ status = "okay";
+
+ /* TMS(?) NFC @ 28 */
+ /* Ti drv2624 haptics @ 5a */
+};
+
+&i2c13 {
+ status = "okay";
+
+ /* focaltech FT3658U @ 38 */
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn";
+ status = "okay";
+};
+
+&pm7250b_adc {
+ channel@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "charger_skin_therm";
+ };
+
+ channel@4f {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "conn_therm";
+ };
+};
+
+&pm7250b_adc_tm {
+ status = "okay";
+
+ charger-skin-therm@0 {
+ reg = <0>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ conn-therm@1 {
+ reg = <1>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm7325_gpios {
+ volume_down_default: volume-down-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ wide-rfc-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pmk8350_vadc {
+ status = "okay";
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_xo_therm";
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@145 {
+ reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_cam_flash_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+
+ channel@147 {
+ reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_wide_rfc_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qup_spi13_cs {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_spi13_data_clk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcm6490/SHIFT/otter/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcm6490/SHIFT/otter/cdsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/qcm6490/SHIFT/otter/modem.mbn";
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/qcm6490/SHIFT/otter/wpss.mbn";
+ status = "okay";
+};
+
+&sdc2_clk {
+ drive-strength = <16>;
+ bias-disable;
+};
+
+&sdc2_cmd {
+ drive-strength = <10>;
+ bias-pull-up;
+};
+
+&sdc2_data {
+ drive-strength = <10>;
+ bias-pull-up;
+};
+
+&sdhc_2 {
+ vmmc-supply = <&vreg_l9c>;
+ vqmmc-supply = <&vreg_l6c>;
+
+ pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
+ pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
+
+ status = "okay";
+};
+
+&tlmm {
+ /*
+ * 48-52: protected by XPU, not sure why.
+ */
+ gpio-reserved-ranges = <48 4>;
+
+ bluetooth_enable_default: bluetooth-enable-default-state {
+ pins = "gpio85";
+ function = "gpio";
+ output-low;
+ bias-disable;
+ };
+
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio86";
+ function = "gpio";
+ bias-pull-down;
+ };
+};
+
+&uart5 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
+&uart7 {
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ bluetooth: bluetooth {
+ compatible = "qcom,wcn6750-bt";
+
+ pinctrl-0 = <&bluetooth_enable_default>, <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&vreg_l19b>;
+ vddaon-supply = <&vreg_s7b>;
+ vddbtcxmx-supply = <&vreg_s7b>;
+ vddrfacmn-supply = <&vreg_s7b>;
+ vddrfa0p8-supply = <&vreg_s7b>;
+ vddrfa1p7-supply = <&vreg_s1b>;
+ vddrfa1p2-supply = <&vreg_s8b>;
+ vddrfa2p2-supply = <&vreg_s1c>;
+ vddasd-supply = <&vreg_l11c>;
+
+ max-speed = <3200000>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b>;
+ vcc-max-microamp = <800000>;
+ /*
+ * Technically l9b enables an eLDO (supplied by s1b) which then powers
+ * VCCQ2 of the UFS.
+ */
+ vccq-supply = <&vreg_l9b>;
+ vccq-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c>;
+ vdda-pll-supply = <&vreg_l6b>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c>;
+ vdda18-supply = <&vreg_l1c>;
+ vdda33-supply = <&vreg_l2b>;
+
+ qcom,hs-crossover-voltage-microvolt = <28000>;
+ qcom,hs-output-impedance-micro-ohms = <2600000>;
+ qcom,hs-rise-fall-time-bp = <5430>;
+ qcom,hs-disconnect-bp = <1743>;
+ qcom,hs-amplitude-bp = <2430>;
+
+ qcom,pre-emphasis-amplitude-bp = <20000>;
+ qcom,pre-emphasis-duration-bp = <20000>;
+
+ qcom,squelch-detector-bp = <(-2090)>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b>;
+ vdda-pll-supply = <&vreg_l1b>;
+
+ status = "okay";
+};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "SHIFTphone_8";
+
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs404.dtsi b/dts/upstream/src/arm64/qcom/qcs404.dtsi
index ac451f3..c291bbe 100644
--- a/dts/upstream/src/arm64/qcom/qcs404.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs404.dtsi
@@ -1324,7 +1324,7 @@
};
apcs_hfpll: clock-controller@b016000 {
- compatible = "qcom,hfpll";
+ compatible = "qcom,qcs404-hfpll";
reg = <0x0b016000 0x30>;
#clock-cells = <0>;
clock-output-names = "apcs_hfpll";
@@ -1531,10 +1531,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 0xff08>,
- <GIC_PPI 3 0xff08>,
- <GIC_PPI 4 0xff08>,
- <GIC_PPI 1 0xff08>;
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
smp2p-adsp {
@@ -1600,7 +1600,6 @@
thermal-zones {
aoss-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -1615,7 +1614,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
@@ -1630,7 +1628,6 @@
lpass-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
@@ -1645,7 +1642,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
@@ -1660,7 +1656,6 @@
cluster-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -1694,7 +1689,6 @@
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -1728,7 +1722,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -1762,7 +1755,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -1796,7 +1788,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -1830,7 +1821,6 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
index a085ff5..0d45662 100644
--- a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
+++ b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
@@ -52,6 +52,25 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ lt9611_1v2: lt9611-vdd12-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
reserved-memory {
xbl_mem: xbl@80700000 {
reg = <0x0 0x80700000 0x0 0x100000>;
@@ -530,6 +549,54 @@
<GCC_WPSS_RSCP_CLK>;
};
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <&vreg_l11c_2p8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
&i2c1 {
status = "okay";
@@ -587,6 +654,21 @@
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
+&mdss_dsi {
+ vdda-supply = <&vreg_l6b_1p2>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi_phy {
+ vdds-supply = <&vreg_l10c_0p88>;
+ status = "okay";
+};
+
&mdss_edp {
status = "okay";
};
@@ -602,10 +684,18 @@
status = "okay";
};
+&pmk8350_rtc {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&remoteproc_adsp {
firmware-name = "qcom/qcs6490/adsp.mbn";
status = "okay";
@@ -632,7 +722,6 @@
};
&uart5 {
- compatible = "qcom,geni-debug-uart";
status = "okay";
};
@@ -711,3 +800,23 @@
function = "gpio";
bias-disable;
};
+
+&pm7250b_gpios {
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio2";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ power-source = <0>;
+ };
+};
+
+&tlmm {
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8550-aim300-aiot.dts b/dts/upstream/src/arm64/qcom/qcs8550-aim300-aiot.dts
new file mode 100644
index 0000000..2e2e46f
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8550-aim300-aiot.dts
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "qcs8550-aim300.dtsi"
+#include "pm8010.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT";
+ compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550",
+ "qcom,sm8550";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ debounce-interval = <15>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ };
+
+ regulators-3 {
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ };
+
+ regulators-4 {
+ vdd-s4-supply = <&vph_pwr>;
+ };
+
+ regulators-5 {
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ };
+};
+
+&i2c_hub_2 {
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob1>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+
+ typec-retimer@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ orientation-switch;
+ retimer-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_ss_out: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_ss_in: endpoint {
+ data-lanes = <3 2 1 0>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&mdss_dsi0 {
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ pinctrl-0 = <&dsi_active>, <&te_default>;
+ pinctrl-1 = <&dsi_suspend>, <&te_default>;
+ pinctrl-names = "default", "sleep";
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+ vddio-supply = <&vreg_l12b_1p8>;
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mbn",
+ "qcom/qcs8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mbn",
+ "qcom/qcs8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&swr1 {
+ status = "okay";
+};
+
+&swr2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ dsi_active: dsi-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ dsi_suspend: dsi-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ te_default: te-default-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_ss_in>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
new file mode 100644
index 0000000..f6960e2
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+
+ vreg_s1g_1p25: smps1 {
+ regulator-name = "vreg_s1g_1p25";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p85: smps2 {
+ regulator-name = "vreg_s2g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p8: smps3 {
+ regulator-name = "vreg_s3g_0p8";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1272000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_hsphy {
+ phys = <&pm8550b_eusb2_repeater>;
+
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8550.dtsi b/dts/upstream/src/arm64/qcom/qcs8550.dtsi
new file mode 100644
index 0000000..07b3148
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8550.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "sm8550.dtsi"
+
+/delete-node/ &reserved_memory;
+
+/ {
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
+ /* These are 3 types of reserved memory regions here:
+ * 1. Firmware related regions which aren't shared with kernel.
+ * The device tree source in kernel doesn't need to have node to
+ * indicate the firmware related reserved information. Bootloader
+ * conveys the information by updating devicetree at runtime.
+ * This will be described as: UEFI saves the physical address of
+ * the UEFI System Table to dts file's chosen node. Kernel read this
+ * table and add reserved memory regions to efi config table. Current
+ * reserved memory region may have reserved region which was not yet
+ * used, release note of the firmware have such kind of information.
+ * 2. Firmware related memory regions which are shared with Kernel
+ * The device tree source in the kernel needs to include nodes
+ * that indicate fimware-related shared information. A label name
+ * is suggested because this type of shared information needs to
+ * be referenced by specific drivers for handling purposes.
+ * Unlike previous platforms, QCS8550 boots using EFI and describes
+ * most reserved regions in the ESRT memory map. As a result, reserved
+ * memory regions which aren't relevant to the kernel(like the hypervisor
+ ( region) don't need to be described in DT.
+ * 3. Remoteproc regions.
+ * Remoteproc regions will be reserved and then assigned to
+ * subsystem firmware later.
+ * Here is a reserved memory map for this platform:
+ * 0x80000000 +-------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x8a800000 +-------------------+
+ * | |
+ * | Remoteproc Region |
+ * | |
+ * 0xa7000000 +-------------------+
+ * | |
+ * | Kernel Available |
+ * | |
+ * 0xd4d00000 +-------------------+
+ * | |
+ * | Firmware Related |
+ * | |
+ * 0x100000000 +-------------------+
+ */
+
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ no-map;
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ mpss_mem: mpss-region@8a800000 {
+ reg = <0x0 0x8a800000 0x0 0x10800000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@9b100000 {
+ reg = <0x0 0x9b100000 0x0 0x180000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x80000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp-region@9c200000 {
+ reg = <0x0 0x9c200000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0x0 0x9c900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
+ reg = <0x0 0x9e900000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
+ reg = <0x0 0x9e980000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x4080000>;
+ no-map;
+ };
+
+ mpss_dsm_mem: mpss_dsm_region@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
index 5a25cde..e65305f 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
@@ -500,3 +500,26 @@
&uart7 {
status = "okay";
};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l8a_0p91>;
+ vdda18-supply = <&vreg_l14a_1p8>;
+ vdda33-supply = <&vreg_l2a_2p3>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l8a_0p91>;
+ vdda-pll-supply = <&vreg_l3a_1p2>;
+
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/qdu1000.dtsi b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
index f90f03f..642ca8f 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000.dtsi
+++ b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -913,6 +915,126 @@
};
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,qdu1000-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0x0 0x088e3000 0x0 0x120>;
+ #phy-cells = <0>;
+
+ clocks =<&gcc GCC_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_qmpphy: phy@88e5000 {
+ compatible = "qcom,qdu1000-qmp-usb3-uni-phy";
+ reg = <0x0 0x088e5000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB2_CLKREF_EN>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,qdu1000-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0xc0 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_1_hsphy>,
+ <&usb_1_qmpphy>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
@@ -1478,6 +1600,21 @@
"llcc7_base",
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvmem-cells = <&multi_chan_ddr>;
+ nvmem-cell-names = "multi-chan-ddr";
+ };
+
+ sec_qfprom: efuse@221c8000 {
+ compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom";
+ reg = <0 0x221c8000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ multi_chan_ddr: multi-chan-ddr@12b {
+ reg = <0x12b 0x1>;
+ bits = <0 2>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
index bb519142..e197904 100644
--- a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
+++ b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
@@ -59,6 +59,17 @@
};
};
+ i2c2_gpio: i2c {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
leds {
compatible = "gpio-leds";
@@ -199,7 +210,15 @@
status = "okay";
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/qcm2290/a702_zap.mbn";
+ };
+};
+
-&i2c2 {
+&i2c2_gpio {
clock-frequency = <400000>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
index 2c39bb1..1888d99 100644
--- a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
+++ b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
@@ -60,6 +60,17 @@
};
};
+ i2c2_gpio: i2c {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
leds {
compatible = "gpio-leds";
@@ -190,7 +201,7 @@
};
};
-&i2c2 {
+&i2c2_gpio {
clock-frequency = <400000>;
status = "okay";
@@ -294,7 +305,7 @@
&pmi632_vbus {
regulator-min-microamp = <500000>;
- regulator-max-microamp = <3000000>;
+ regulator-max-microamp = <1000000>;
status = "okay";
};
@@ -403,6 +414,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
+ regulator-always-on;
+ regulator-boot-on;
};
vreg_l10a_1p8: l10 {
diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
index cd0db4f..ccff6cd 100644
--- a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
+++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
@@ -108,10 +108,69 @@
regulator-always-on;
};
+ qca6390-pmu {
+ compatible = "qcom,qca6390-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
+
+ vddaon-supply = <&vreg_s6a_0p95>;
+ vddpmu-supply = <&vreg_s2f_0p95>;
+ vddrfa0p95-supply = <&vreg_s2f_0p95>;
+ vddrfa1p3-supply = <&vreg_s8c_1p3>;
+ vddrfa1p9-supply = <&vreg_s5a_1p9>;
+ vddpcie1p3-supply = <&vreg_s8c_1p3>;
+ vddpcie1p9-supply = <&vreg_s5a_1p9>;
+ vddio-supply = <&vreg_s4a_1p8>;
+
+ wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p7: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p7";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+
thermal-zones {
conn-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150b_adc_tm 0>;
trips {
@@ -124,8 +183,6 @@
};
pm8150l-pcb-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>;
trips {
@@ -138,8 +195,6 @@
};
skin-msm-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 0>;
trips {
@@ -152,8 +207,6 @@
};
wifi-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
@@ -166,8 +219,6 @@
};
xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
@@ -734,6 +785,23 @@
vdda-pll-supply = <&vreg_l9a_1p2>;
};
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1101";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
&pcie1 {
status = "okay";
};
@@ -1303,6 +1371,14 @@
function = "gpio";
bias-pull-up;
};
+
+ wlan_en_state: wlan-default-state {
+ pins = "gpio20";
+ function = "gpio";
+ drive-strength = <16>;
+ output-low;
+ bias-pull-up;
+ };
};
&uart6 {
@@ -1311,17 +1387,12 @@
bluetooth {
compatible = "qcom,qca6390-bt";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_en_state>;
-
- enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
-
- vddio-supply = <&vreg_s4a_1p8>;
- vddpmu-supply = <&vreg_s2f_0p95>;
- vddaon-supply = <&vreg_s6a_0p95>;
- vddrfa0p9-supply = <&vreg_s2f_0p95>;
- vddrfa1p3-supply = <&vreg_s8c_1p3>;
- vddrfa1p9-supply = <&vreg_s5a_1p9>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
};
};
@@ -1356,8 +1427,8 @@
usb-role-switch;
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_1_hsphy {
@@ -1373,7 +1444,6 @@
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p92>;
- orientation-switch;
};
&usb_1_qmpphy_out {
@@ -1465,8 +1535,8 @@
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
diff --git a/dts/upstream/src/arm64/qcom/qru1000-idp.dts b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
index 2a862c8..1c781d9 100644
--- a/dts/upstream/src/arm64/qcom/qru1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
@@ -467,3 +467,26 @@
&uart7 {
status = "okay";
};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l8a_0p91>;
+ vdda18-supply = <&vreg_l14a_1p8>;
+ vdda33-supply = <&vreg_l2a_2p3>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l8a_0p91>;
+ vdda-pll-supply = <&vreg_l3a_1p2>;
+
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sa8155p.dtsi b/dts/upstream/src/arm64/qcom/sa8155p.dtsi
index ffb7ab6..9e70eff 100644
--- a/dts/upstream/src/arm64/qcom/sa8155p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8155p.dtsi
@@ -38,3 +38,7 @@
*/
compatible = "qcom,sa8155p-rpmhpd";
};
+
+&videocc {
+ power-domains = <&rpmhpd SA8155P_CX>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-pmics.dtsi b/dts/upstream/src/arm64/qcom/sa8775p-pmics.dtsi
index eaa43f0..1369c3d 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p-pmics.dtsi
@@ -10,7 +10,7 @@
thermal-zones {
pmm8654au_0_thermal: pm8775-0-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmm8654au_0_temp_alarm>;
trips {
@@ -30,7 +30,7 @@
pmm8654au_1_thermal: pm8775-1-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmm8654au_1_temp_alarm>;
trips {
@@ -50,7 +50,7 @@
pmm8654au_2_thermal: pm8775-2-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmm8654au_2_temp_alarm>;
trips {
@@ -70,7 +70,7 @@
pmm8654au_3_thermal: pm8775-3-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pmm8654au_3_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts b/dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts
new file mode 100644
index 0000000..ae065ae
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include "sa8775p-ride.dtsi"
+
+/ {
+ model = "Qualcomm SA8775P Ride Rev3";
+ compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p";
+};
+
+ðernet0 {
+ phy-mode = "2500base-x";
+};
+
+ðernet1 {
+ phy-mode = "2500base-x";
+};
+
+&mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy0: phy@8 {
+ compatible = "ethernet-phy-id31c3.1c33";
+ reg = <0x8>;
+ device_type = "ethernet-phy";
+ interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+ };
+
+ sgmii_phy1: phy@0 {
+ compatible = "ethernet-phy-id31c3.1c33";
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride.dts b/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
index 26ad05b..2e87fd7 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
@@ -5,835 +5,43 @@
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-
-#include "sa8775p.dtsi"
-#include "sa8775p-pmics.dtsi"
+#include "sa8775p-ride.dtsi"
/ {
model = "Qualcomm SA8775P Ride";
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
-
- aliases {
- ethernet0 = ðernet0;
- ethernet1 = ðernet1;
- i2c11 = &i2c11;
- i2c18 = &i2c18;
- serial0 = &uart10;
- serial1 = &uart12;
- serial2 = &uart17;
- spi16 = &spi16;
- ufshc1 = &ufs_mem_hc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&apps_rsc {
- regulators-0 {
- compatible = "qcom,pmm8654au-rpmh-regulators";
- qcom,pmic-id = "a";
-
- vreg_s4a: smps4 {
- regulator-name = "vreg_s4a";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1816000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s5a: smps5 {
- regulator-name = "vreg_s5a";
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1996000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s9a: smps9 {
- regulator-name = "vreg_s9a";
- regulator-min-microvolt = <535000>;
- regulator-max-microvolt = <1120000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4a: ldo4 {
- regulator-name = "vreg_l4a";
- regulator-min-microvolt = <788000>;
- regulator-max-microvolt = <1050000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l5a: ldo5 {
- regulator-name = "vreg_l5a";
- regulator-min-microvolt = <870000>;
- regulator-max-microvolt = <950000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6a: ldo6 {
- regulator-name = "vreg_l6a";
- regulator-min-microvolt = <870000>;
- regulator-max-microvolt = <970000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l7a: ldo7 {
- regulator-name = "vreg_l7a";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <950000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l8a: ldo8 {
- regulator-name = "vreg_l8a";
- regulator-min-microvolt = <2504000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9a: ldo9 {
- regulator-name = "vreg_l9a";
- regulator-min-microvolt = <2970000>;
- regulator-max-microvolt = <3544000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-1 {
- compatible = "qcom,pmm8654au-rpmh-regulators";
- qcom,pmic-id = "c";
-
- vreg_l1c: ldo1 {
- regulator-name = "vreg_l1c";
- regulator-min-microvolt = <1140000>;
- regulator-max-microvolt = <1260000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l2c: ldo2 {
- regulator-name = "vreg_l2c";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l3c: ldo3 {
- regulator-name = "vreg_l3c";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1300000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l4c: ldo4 {
- regulator-name = "vreg_l4c";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- /*
- * FIXME: This should have regulator-allow-set-load but
- * we're getting an over-current fault from the PMIC
- * when switching to LPM.
- */
- };
-
- vreg_l5c: ldo5 {
- regulator-name = "vreg_l5c";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1300000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6c: ldo6 {
- regulator-name = "vreg_l6c";
- regulator-min-microvolt = <1620000>;
- regulator-max-microvolt = <1980000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l7c: ldo7 {
- regulator-name = "vreg_l7c";
- regulator-min-microvolt = <1620000>;
- regulator-max-microvolt = <2000000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l8c: ldo8 {
- regulator-name = "vreg_l8c";
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <3300000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l9c: ldo9 {
- regulator-name = "vreg_l9c";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <2700000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
- };
-
- regulators-2 {
- compatible = "qcom,pmm8654au-rpmh-regulators";
- qcom,pmic-id = "e";
-
- vreg_s4e: smps4 {
- regulator-name = "vreg_s4e";
- regulator-min-microvolt = <970000>;
- regulator-max-microvolt = <1520000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s7e: smps7 {
- regulator-name = "vreg_s7e";
- regulator-min-microvolt = <1010000>;
- regulator-max-microvolt = <1170000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_s9e: smps9 {
- regulator-name = "vreg_s9e";
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <570000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l6e: ldo6 {
- regulator-name = "vreg_l6e";
- regulator-min-microvolt = <1280000>;
- regulator-max-microvolt = <1450000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
-
- vreg_l8e: ldo8 {
- regulator-name = "vreg_l8e";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1950000>;
- regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
- regulator-allow-set-load;
- regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_HPM>;
- };
- };
};
ðernet0 {
phy-mode = "sgmii";
- phy-handle = <&sgmii_phy0>;
-
- pinctrl-0 = <ðernet0_default>;
- pinctrl-names = "default";
-
- snps,mtl-rx-config = <&mtl_rx_setup>;
- snps,mtl-tx-config = <&mtl_tx_setup>;
- snps,ps-speed = <1000>;
-
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sgmii_phy0: phy@8 {
- compatible = "ethernet-phy-id0141.0dd4";
- reg = <0x8>;
- device_type = "ethernet-phy";
- interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
- reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
- reset-assert-us = <11000>;
- reset-deassert-us = <70000>;
- };
-
- sgmii_phy1: phy@a {
- compatible = "ethernet-phy-id0141.0dd4";
- reg = <0xa>;
- device_type = "ethernet-phy";
- interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
- reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
- reset-assert-us = <11000>;
- reset-deassert-us = <70000>;
- };
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <4>;
- snps,rx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,map-to-dma-channel = <0x0>;
- snps,route-up;
- snps,priority = <0x1>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,map-to-dma-channel = <0x1>;
- snps,route-ptp;
- };
-
- queue2 {
- snps,avb-algorithm;
- snps,map-to-dma-channel = <0x2>;
- snps,route-avcp;
- };
-
- queue3 {
- snps,avb-algorithm;
- snps,map-to-dma-channel = <0x3>;
- snps,priority = <0xc>;
- };
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- };
-
- queue1 {
- snps,dcb-algorithm;
- };
-
- queue2 {
- snps,avb-algorithm;
- snps,send_slope = <0x1000>;
- snps,idle_slope = <0x1000>;
- snps,high_credit = <0x3e800>;
- snps,low_credit = <0xffc18000>;
- };
-
- queue3 {
- snps,avb-algorithm;
- snps,send_slope = <0x1000>;
- snps,idle_slope = <0x1000>;
- snps,high_credit = <0x3e800>;
- snps,low_credit = <0xffc18000>;
- };
- };
};
ðernet1 {
phy-mode = "sgmii";
- phy-handle = <&sgmii_phy1>;
-
- snps,mtl-rx-config = <&mtl_rx_setup1>;
- snps,mtl-tx-config = <&mtl_tx_setup1>;
- snps,ps-speed = <1000>;
-
- status = "okay";
-
- mtl_rx_setup1: rx-queues-config {
- snps,rx-queues-to-use = <4>;
- snps,rx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,map-to-dma-channel = <0x0>;
- snps,route-up;
- snps,priority = <0x1>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,map-to-dma-channel = <0x1>;
- snps,route-ptp;
- };
-
- queue2 {
- snps,avb-algorithm;
- snps,map-to-dma-channel = <0x2>;
- snps,route-avcp;
- };
-
- queue3 {
- snps,avb-algorithm;
- snps,map-to-dma-channel = <0x3>;
- snps,priority = <0xc>;
- };
- };
-
- mtl_tx_setup1: tx-queues-config {
- snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- };
-
- queue1 {
- snps,dcb-algorithm;
- };
-
- queue2 {
- snps,avb-algorithm;
- snps,send_slope = <0x1000>;
- snps,idle_slope = <0x1000>;
- snps,high_credit = <0x3e800>;
- snps,low_credit = <0xffc18000>;
- };
-
- queue3 {
- snps,avb-algorithm;
- snps,send_slope = <0x1000>;
- snps,idle_slope = <0x1000>;
- snps,high_credit = <0x3e800>;
- snps,low_credit = <0xffc18000>;
- };
- };
-};
-
-&i2c11 {
- clock-frequency = <400000>;
- pinctrl-0 = <&qup_i2c11_default>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&i2c18 {
- clock-frequency = <400000>;
- pinctrl-0 = <&qup_i2c18_default>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pmm8654au_0_gpios {
- gpio-line-names = "DS_EN",
- "POFF_COMPLETE",
- "UFS0_VER_ID",
- "FAST_POFF",
- "DBU1_PON_DONE",
- "AOSS_SLEEP",
- "CAM_DES0_EN",
- "CAM_DES1_EN",
- "CAM_DES2_EN",
- "CAM_DES3_EN",
- "UEFI",
- "ANALOG_PON_OPT";
-};
-
-&pmm8654au_0_pon_resin {
- linux,code = <KEY_VOLUMEDOWN>;
- status = "okay";
-};
-
-&pmm8654au_1_gpios {
- gpio-line-names = "PMIC_C_ID0",
- "PMIC_C_ID1",
- "UFS1_VER_ID",
- "IPA_PWR",
- "",
- "WLAN_DBU4_EN",
- "WLAN_EN",
- "BT_EN",
- "USB2_PWR_EN",
- "USB2_FAULT";
-
- usb2_en_state: usb2-en-state {
- pins = "gpio9";
- function = "normal";
- output-high;
- power-source = <0>;
- };
-};
-
-&pmm8654au_2_gpios {
- gpio-line-names = "PMIC_E_ID0",
- "PMIC_E_ID1",
- "USB0_PWR_EN",
- "USB0_FAULT",
- "SENSOR_IRQ_1",
- "SENSOR_IRQ_2",
- "SENSOR_RST",
- "SGMIIO0_RST",
- "SGMIIO1_RST",
- "USB1_PWR_ENABLE",
- "USB1_FAULT",
- "VMON_SPX8";
-
- usb0_en_state: usb0-en-state {
- pins = "gpio3";
- function = "normal";
- output-high;
- power-source = <0>;
- };
-
- usb1_en_state: usb1-en-state {
- pins = "gpio10";
- function = "normal";
- output-high;
- power-source = <0>;
- };
-};
-
-&pmm8654au_3_gpios {
- gpio-line-names = "PMIC_G_ID0",
- "PMIC_G_ID1",
- "GNSS_RST",
- "GNSS_EN",
- "GNSS_BOOT_MODE";
-};
-
-&qupv3_id_1 {
- status = "okay";
-};
-
-&qupv3_id_2 {
- status = "okay";
-};
-
-&serdes0 {
- phy-supply = <&vreg_l5a>;
- status = "okay";
-};
-
-&serdes1 {
- phy-supply = <&vreg_l5a>;
- status = "okay";
-};
-
-&sleep_clk {
- clock-frequency = <32764>;
-};
-
-&spi16 {
- pinctrl-0 = <&qup_spi16_default>;
- pinctrl-names = "default";
- status = "okay";
};
-&tlmm {
- ethernet0_default: ethernet0-default-state {
- ethernet0_mdc: ethernet0-mdc-pins {
- pins = "gpio8";
- function = "emac0_mdc";
- drive-strength = <16>;
- bias-pull-up;
- };
-
- ethernet0_mdio: ethernet0-mdio-pins {
- pins = "gpio9";
- function = "emac0_mdio";
- drive-strength = <16>;
- bias-pull-up;
- };
- };
-
- qup_uart10_default: qup-uart10-state {
- pins = "gpio46", "gpio47";
- function = "qup1_se3";
- };
-
- qup_spi16_default: qup-spi16-state {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- function = "qup2_se2";
- drive-strength = <6>;
- bias-disable;
- };
-
- qup_i2c11_default: qup-i2c11-state {
- pins = "gpio48", "gpio49";
- function = "qup1_se4";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_i2c18_default: qup-i2c18-state {
- pins = "gpio95", "gpio96";
- function = "qup2_se4";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- qup_uart12_default: qup-uart12-state {
- qup_uart12_cts: qup-uart12-cts-pins {
- pins = "gpio52";
- function = "qup1_se5";
- bias-disable;
- };
-
- qup_uart12_rts: qup-uart12-rts-pins {
- pins = "gpio53";
- function = "qup1_se5";
- bias-pull-down;
- };
-
- qup_uart12_tx: qup-uart12-tx-pins {
- pins = "gpio54";
- function = "qup1_se5";
- bias-pull-up;
- };
-
- qup_uart12_rx: qup-uart12-rx-pins {
- pins = "gpio55";
- function = "qup1_se5";
- bias-pull-down;
- };
- };
-
- qup_uart17_default: qup-uart17-state {
- qup_uart17_cts: qup-uart17-cts-pins {
- pins = "gpio91";
- function = "qup2_se3";
- bias-disable;
- };
-
- qup_uart17_rts: qup0-uart17-rts-pins {
- pins = "gpio92";
- function = "qup2_se3";
- bias-pull-down;
- };
-
- qup_uart17_tx: qup0-uart17-tx-pins {
- pins = "gpio93";
- function = "qup2_se3";
- bias-pull-up;
- };
-
- qup_uart17_rx: qup0-uart17-rx-pins {
- pins = "gpio94";
- function = "qup2_se3";
- bias-pull-down;
- };
- };
+&mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
- pcie0_default_state: pcie0-default-state {
- perst-pins {
- pins = "gpio2";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- clkreq-pins {
- pins = "gpio1";
- function = "pcie0_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- wake-pins {
- pins = "gpio0";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
+ sgmii_phy0: phy@8 {
+ compatible = "ethernet-phy-id0141.0dd4";
+ reg = <0x8>;
+ device_type = "ethernet-phy";
+ interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
};
- pcie1_default_state: pcie1-default-state {
- perst-pins {
- pins = "gpio4";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- clkreq-pins {
- pins = "gpio3";
- function = "pcie1_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- wake-pins {
- pins = "gpio5";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
+ sgmii_phy1: phy@a {
+ compatible = "ethernet-phy-id0141.0dd4";
+ reg = <0xa>;
+ device_type = "ethernet-phy";
+ interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
};
};
-
-&pcie0 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_default_state>;
-
- status = "okay";
-};
-
-&pcie1 {
- perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_default_state>;
-
- status = "okay";
-};
-
-&pcie0_phy {
- vdda-phy-supply = <&vreg_l5a>;
- vdda-pll-supply = <&vreg_l1c>;
-
- status = "okay";
-};
-
-&pcie1_phy {
- vdda-phy-supply = <&vreg_l5a>;
- vdda-pll-supply = <&vreg_l1c>;
-
- status = "okay";
-};
-
-&uart10 {
- compatible = "qcom,geni-debug-uart";
- pinctrl-0 = <&qup_uart10_default>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&uart12 {
- pinctrl-0 = <&qup_uart12_default>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&uart17 {
- pinctrl-0 = <&qup_uart17_default>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&ufs_mem_hc {
- reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- vcc-supply = <&vreg_l8a>;
- vcc-max-microamp = <1100000>;
- vccq-supply = <&vreg_l4c>;
- vccq-max-microamp = <1200000>;
-
- status = "okay";
-};
-
-&ufs_mem_phy {
- vdda-phy-supply = <&vreg_l4a>;
- vdda-pll-supply = <&vreg_l1c>;
-
- status = "okay";
-};
-
-&usb_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_en_state>;
-
- status = "okay";
-};
-
-&usb_0_dwc3 {
- dr_mode = "peripheral";
-};
-
-&usb_0_hsphy {
- vdda-pll-supply = <&vreg_l7a>;
- vdda18-supply = <&vreg_l6c>;
- vdda33-supply = <&vreg_l9a>;
-
- status = "okay";
-};
-
-&usb_0_qmpphy {
- vdda-phy-supply = <&vreg_l1c>;
- vdda-pll-supply = <&vreg_l7a>;
-
- status = "okay";
-};
-
-&usb_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_en_state>;
-
- status = "okay";
-};
-
-&usb_1_dwc3 {
- dr_mode = "host";
-};
-
-&usb_1_hsphy {
- vdda-pll-supply = <&vreg_l7a>;
- vdda18-supply = <&vreg_l6c>;
- vdda33-supply = <&vreg_l9a>;
-
- status = "okay";
-};
-
-&usb_1_qmpphy {
- vdda-phy-supply = <&vreg_l1c>;
- vdda-pll-supply = <&vreg_l7a>;
-
- status = "okay";
-};
-
-&usb_2 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_en_state>;
-
- status = "okay";
-};
-
-&usb_2_dwc3 {
- dr_mode = "host";
-};
-
-&usb_2_hsphy {
- vdda-pll-supply = <&vreg_l7a>;
- vdda18-supply = <&vreg_l6c>;
- vdda33-supply = <&vreg_l9a>;
-
- status = "okay";
-};
-
-&xo_board_clk {
- clock-frequency = <38400000>;
-};
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
new file mode 100644
index 0000000..2a61706
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sa8775p.dtsi"
+#include "sa8775p-pmics.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = ðernet0;
+ ethernet1 = ðernet1;
+ i2c11 = &i2c11;
+ i2c18 = &i2c18;
+ serial0 = &uart10;
+ serial1 = &uart12;
+ serial2 = &uart17;
+ spi16 = &spi16;
+ ufshc1 = &ufs_mem_hc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pmm8654au-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vreg_s4a: smps4 {
+ regulator-name = "vreg_s4a";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1816000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a: smps5 {
+ regulator-name = "vreg_s5a";
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1996000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9a: smps9 {
+ regulator-name = "vreg_s9a";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4a: ldo4 {
+ regulator-name = "vreg_l4a";
+ regulator-min-microvolt = <788000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a: ldo5 {
+ regulator-name = "vreg_l5a";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a: ldo6 {
+ regulator-name = "vreg_l6a";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a: ldo7 {
+ regulator-name = "vreg_l7a";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8a: ldo8 {
+ regulator-name = "vreg_l8a";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a: ldo9 {
+ regulator-name = "vreg_l9a";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmm8654au-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_l1c: ldo1 {
+ regulator-name = "vreg_l1c";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c: ldo3 {
+ regulator-name = "vreg_l3c";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c: ldo4 {
+ regulator-name = "vreg_l4c";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ /*
+ * FIXME: This should have regulator-allow-set-load but
+ * we're getting an over-current fault from the PMIC
+ * when switching to LPM.
+ */
+ };
+
+ vreg_l5c: ldo5 {
+ regulator-name = "vreg_l5c";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c: ldo6 {
+ regulator-name = "vreg_l6c";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c: ldo7 {
+ regulator-name = "vreg_l7c";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c: ldo8 {
+ regulator-name = "vreg_l8c";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c: ldo9 {
+ regulator-name = "vreg_l9c";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmm8654au-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vreg_s4e: smps4 {
+ regulator-name = "vreg_s4e";
+ regulator-min-microvolt = <970000>;
+ regulator-max-microvolt = <1520000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7e: smps7 {
+ regulator-name = "vreg_s7e";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9e: smps9 {
+ regulator-name = "vreg_s9e";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <570000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6e: ldo6 {
+ regulator-name = "vreg_l6e";
+ regulator-min-microvolt = <1280000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8e: ldo8 {
+ regulator-name = "vreg_l8e";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+ðernet0 {
+ phy-handle = <&sgmii_phy0>;
+
+ pinctrl-0 = <ðernet0_default>;
+ pinctrl-names = "default";
+
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,ps-speed = <1000>;
+
+ status = "okay";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
+ðernet1 {
+ phy-handle = <&sgmii_phy1>;
+
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,ps-speed = <1000>;
+
+ status = "okay";
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
+&i2c11 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&qup_i2c11_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c18 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&qup_i2c18_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pmm8654au_0_gpios {
+ gpio-line-names = "DS_EN",
+ "POFF_COMPLETE",
+ "UFS0_VER_ID",
+ "FAST_POFF",
+ "DBU1_PON_DONE",
+ "AOSS_SLEEP",
+ "CAM_DES0_EN",
+ "CAM_DES1_EN",
+ "CAM_DES2_EN",
+ "CAM_DES3_EN",
+ "UEFI",
+ "ANALOG_PON_OPT";
+};
+
+&pmm8654au_0_pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pmm8654au_1_gpios {
+ gpio-line-names = "PMIC_C_ID0",
+ "PMIC_C_ID1",
+ "UFS1_VER_ID",
+ "IPA_PWR",
+ "",
+ "WLAN_DBU4_EN",
+ "WLAN_EN",
+ "BT_EN",
+ "USB2_PWR_EN",
+ "USB2_FAULT";
+
+ usb2_en_state: usb2-en-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8654au_2_gpios {
+ gpio-line-names = "PMIC_E_ID0",
+ "PMIC_E_ID1",
+ "USB0_PWR_EN",
+ "USB0_FAULT",
+ "SENSOR_IRQ_1",
+ "SENSOR_IRQ_2",
+ "SENSOR_RST",
+ "SGMIIO0_RST",
+ "SGMIIO1_RST",
+ "USB1_PWR_ENABLE",
+ "USB1_FAULT",
+ "VMON_SPX8";
+
+ usb0_en_state: usb0-en-state {
+ pins = "gpio3";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+
+ usb1_en_state: usb1-en-state {
+ pins = "gpio10";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8654au_3_gpios {
+ gpio-line-names = "PMIC_G_ID0",
+ "PMIC_G_ID1",
+ "GNSS_RST",
+ "GNSS_EN",
+ "GNSS_BOOT_MODE";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&serdes0 {
+ phy-supply = <&vreg_l5a>;
+ status = "okay";
+};
+
+&serdes1 {
+ phy-supply = <&vreg_l5a>;
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&spi16 {
+ pinctrl-0 = <&qup_spi16_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tlmm {
+ ethernet0_default: ethernet0-default-state {
+ ethernet0_mdc: ethernet0-mdc-pins {
+ pins = "gpio8";
+ function = "emac0_mdc";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ ethernet0_mdio: ethernet0-mdio-pins {
+ pins = "gpio9";
+ function = "emac0_mdio";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qup_uart10_default: qup-uart10-state {
+ pins = "gpio46", "gpio47";
+ function = "qup1_se3";
+ };
+
+ qup_spi16_default: qup-spi16-state {
+ pins = "gpio86", "gpio87", "gpio88", "gpio89";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_i2c11_default: qup-i2c11-state {
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c18_default: qup-i2c18-state {
+ pins = "gpio95", "gpio96";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart12_default: qup-uart12-state {
+ qup_uart12_cts: qup-uart12-cts-pins {
+ pins = "gpio52";
+ function = "qup1_se5";
+ bias-disable;
+ };
+
+ qup_uart12_rts: qup-uart12-rts-pins {
+ pins = "gpio53";
+ function = "qup1_se5";
+ bias-pull-down;
+ };
+
+ qup_uart12_tx: qup-uart12-tx-pins {
+ pins = "gpio54";
+ function = "qup1_se5";
+ bias-pull-up;
+ };
+
+ qup_uart12_rx: qup-uart12-rx-pins {
+ pins = "gpio55";
+ function = "qup1_se5";
+ bias-pull-down;
+ };
+ };
+
+ qup_uart17_default: qup-uart17-state {
+ qup_uart17_cts: qup-uart17-cts-pins {
+ pins = "gpio91";
+ function = "qup2_se3";
+ bias-disable;
+ };
+
+ qup_uart17_rts: qup0-uart17-rts-pins {
+ pins = "gpio92";
+ function = "qup2_se3";
+ bias-pull-down;
+ };
+
+ qup_uart17_tx: qup0-uart17-tx-pins {
+ pins = "gpio93";
+ function = "qup2_se3";
+ bias-pull-up;
+ };
+
+ qup_uart17_rx: qup0-uart17-rx-pins {
+ pins = "gpio94";
+ function = "qup2_se3";
+ bias-pull-down;
+ };
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio1";
+ function = "pcie0_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio0";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio3";
+ function = "pcie1_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pcie0 {
+ perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l1c>;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l5a>;
+ vdda-pll-supply = <&vreg_l1c>;
+
+ status = "okay";
+};
+
+&uart10 {
+ compatible = "qcom,geni-debug-uart";
+ pinctrl-0 = <&qup_uart10_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart12 {
+ pinctrl-0 = <&qup_uart12_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart17 {
+ pinctrl-0 = <&qup_uart17_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l8a>;
+ vcc-max-microamp = <1100000>;
+ vccq-supply = <&vreg_l4c>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4a>;
+ vdda-pll-supply = <&vreg_l1c>;
+
+ status = "okay";
+};
+
+&usb_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_en_state>;
+
+ status = "okay";
+};
+
+&usb_0_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_0_hsphy {
+ vdda-pll-supply = <&vreg_l7a>;
+ vdda18-supply = <&vreg_l6c>;
+ vdda33-supply = <&vreg_l9a>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy {
+ vdda-phy-supply = <&vreg_l1c>;
+ vdda-pll-supply = <&vreg_l7a>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_en_state>;
+
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l7a>;
+ vdda18-supply = <&vreg_l6c>;
+ vdda33-supply = <&vreg_l9a>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l1c>;
+ vdda-pll-supply = <&vreg_l7a>;
+
+ status = "okay";
+};
+
+&usb_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_en_state>;
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_2_hsphy {
+ vdda-pll-supply = <&vreg_l7a>;
+ vdda18-supply = <&vreg_l6c>;
+ vdda33-supply = <&vreg_l9a>;
+
+ status = "okay";
+};
+
+&xo_board_clk {
+ clock-frequency = <38400000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sa8775p.dtsi b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
index 1b3dc0e..23f1b2e 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
@@ -205,9 +205,23 @@
};
};
+ dummy-sink {
+ compatible = "arm,coresight-dummy-sink";
+
+ in-ports {
+ port {
+ eud_in: endpoint {
+ remote-endpoint =
+ <&swao_rep_out1>;
+ };
+ };
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
+ memory-region = <&tz_ffi_mem>;
};
};
@@ -418,6 +432,12 @@
no-map;
};
+ tz_ffi_mem: tz-ffi@91c00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x91c00000 0x0 0x1400000>;
+ no-map;
+ };
+
lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
@@ -1644,6 +1664,919 @@
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
+ stm: stm@4002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x4002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@4003000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4003000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qdss_tpdm0_out: endpoint {
+ remote-endpoint =
+ <&qdss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@4004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x4004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ qdss_tpda_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in6>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ qdss_tpda_in0: endpoint {
+ remote-endpoint =
+ <&qdss_tpdm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ qdss_tpda_in1: endpoint {
+ remote-endpoint =
+ <&qdss_tpdm1_out>;
+ };
+ };
+ };
+ };
+
+ tpdm@400f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x400f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qdss_tpdm1_out: endpoint {
+ remote-endpoint =
+ <&qdss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@4041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&qdss_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ funnel0_in6: endpoint {
+ remote-endpoint =
+ <&qdss_tpda_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint =
+ <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@4042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4042000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&qdss_funnel_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ funnel1_in4: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_out>;
+ };
+ };
+ };
+ };
+
+ funnel@4045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4045000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ qdss_funnel_out: endpoint {
+ remote-endpoint =
+ <&aoss_funnel_in7>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ qdss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ qdss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+ };
+ };
+
+ funnel@4b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x4b04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ aoss_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf0_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ aoss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ aoss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&qdss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ tmc_etf: tmc@4b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x4b05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf0_out: endpoint {
+ remote-endpoint =
+ <&swao_rep_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf0_in: endpoint {
+ remote-endpoint =
+ <&aoss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ replicator@4b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x4b06000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ swao_rep_out1: endpoint {
+ remote-endpoint =
+ <&eud_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ swao_rep_in: endpoint {
+ remote-endpoint =
+ <&etf0_out>;
+ };
+ };
+ };
+ };
+
+ tpda@4b08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x4b08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ aoss_tpda_out: endpoint {
+ remote-endpoint =
+ <&aoss_funnel_in6>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ aoss_tpda_in0: endpoint {
+ remote-endpoint =
+ <&aoss_tpdm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ aoss_tpda_in1: endpoint {
+ remote-endpoint =
+ <&aoss_tpdm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ aoss_tpda_in2: endpoint {
+ remote-endpoint =
+ <&aoss_tpdm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ aoss_tpda_in3: endpoint {
+ remote-endpoint =
+ <&aoss_tpdm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ aoss_tpda_in4: endpoint {
+ remote-endpoint =
+ <&aoss_tpdm4_out>;
+ };
+ };
+ };
+ };
+
+ tpdm@4b09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4b09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm0_out: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@4b0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4b0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm1_out: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@4b0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4b0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm2_out: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@4b0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4b0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm3_out: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@4b0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x4b0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ aoss_tpdm4_out: endpoint {
+ remote-endpoint =
+ <&aoss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ aoss_cti: cti@4b13000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x4b13000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ etm@6040000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6040000 0x0 0x1000>;
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in0>;
+ };
+ };
+ };
+ };
+
+ etm@6140000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6140000 0x0 0x1000>;
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in1>;
+ };
+ };
+ };
+ };
+
+ etm@6240000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6240000 0x0 0x1000>;
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in2>;
+ };
+ };
+ };
+ };
+
+ etm@6340000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6340000 0x0 0x1000>;
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in3>;
+ };
+ };
+ };
+ };
+
+ etm@6440000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6440000 0x0 0x1000>;
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in4>;
+ };
+ };
+ };
+ };
+
+ etm@6540000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6540000 0x0 0x1000>;
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in5>;
+ };
+ };
+ };
+ };
+
+ etm@6640000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6640000 0x0 0x1000>;
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in6>;
+ };
+ };
+ };
+ };
+
+ etm@6740000 {
+ compatible = "arm,primecell";
+ reg = <0x0 0x6740000 0x0 0x1000>;
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6800000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x6800000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel0_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel0_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel0_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel0_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel0_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel0_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel0_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel0_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x6810000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel1_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in4>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel1_in0: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel1_in3: endpoint {
+ remote-endpoint =
+ <&apss_tpda_out>;
+ };
+ };
+ };
+ };
+
+ tpdm@6860000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x6860000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ apss_tpdm3_out: endpoint {
+ remote-endpoint =
+ <&apss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@6861000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x6861000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ apss_tpdm4_out: endpoint {
+ remote-endpoint =
+ <&apss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ tpda@6863000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x6863000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_tpda_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in3>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_tpda_in0: endpoint {
+ remote-endpoint =
+ <&apss_tpdm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_tpda_in1: endpoint {
+ remote-endpoint =
+ <&apss_tpdm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_tpda_in2: endpoint {
+ remote-endpoint =
+ <&apss_tpdm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_tpda_in3: endpoint {
+ remote-endpoint =
+ <&apss_tpdm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_tpda_in4: endpoint {
+ remote-endpoint =
+ <&apss_tpdm4_out>;
+ };
+ };
+ };
+ };
+
+ tpdm@68a0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x68a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ apss_tpdm0_out: endpoint {
+ remote-endpoint =
+ <&apss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@68b0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x68b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ apss_tpdm1_out: endpoint {
+ remote-endpoint =
+ <&apss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@68c0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x68c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ apss_tpdm2_out: endpoint {
+ remote-endpoint =
+ <&apss_tpda_in2>;
+ };
+ };
+ };
+ };
+
usb_0_hsphy: phy@88e4000 {
compatible = "qcom,sa8775p-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
@@ -1959,6 +2892,25 @@
status = "disabled";
};
+ llcc: system-cache-controller@9200000 {
+ compatible = "qcom,sa8775p-llcc";
+ reg = <0x0 0x09200000 0x0 0x80000>,
+ <0x0 0x09300000 0x0 0x80000>,
+ <0x0 0x09400000 0x0 0x80000>,
+ <0x0 0x09500000 0x0 0x80000>,
+ <0x0 0x09600000 0x0 0x80000>,
+ <0x0 0x09700000 0x0 0x80000>,
+ <0x0 0x09a00000 0x0 0x80000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc4_base",
+ "llcc5_base",
+ "llcc_broadcast_base";
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -2099,6 +3051,20 @@
wakeup-parent = <&pdc>;
};
+ sram: sram@146d8000 {
+ compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd";
+ reg = <0x0 0x146d8000 0x0 0x1000>;
+ ranges = <0x0 0x0 0x146d8000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
@@ -2504,6 +3470,7 @@
phy-names = "serdes";
iommus = <&apps_smmu 0x140 0xf>;
+ dma-coherent;
snps,tso;
snps,pbl = <32>;
@@ -2538,6 +3505,7 @@
phy-names = "serdes";
iommus = <&apps_smmu 0x120 0xf>;
+ dma-coherent;
snps,tso;
snps,pbl = <32>;
@@ -2550,9 +3518,6 @@
thermal-zones {
aoss-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 0>;
trips {
@@ -2572,7 +3537,6 @@
cpu-0-0-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
@@ -2593,7 +3557,6 @@
cpu-0-1-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
@@ -2614,7 +3577,6 @@
cpu-0-2-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
@@ -2635,7 +3597,6 @@
cpu-0-3-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
@@ -2656,7 +3617,6 @@
gpuss-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
@@ -2677,7 +3637,6 @@
gpuss-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
@@ -2698,7 +3657,6 @@
gpuss-2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
@@ -2718,9 +3676,6 @@
};
audio-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 8>;
trips {
@@ -2739,9 +3694,6 @@
};
camss-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 9>;
trips {
@@ -2760,9 +3712,6 @@
};
pcie-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 10>;
trips {
@@ -2781,9 +3730,6 @@
};
cpuss-0-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 11>;
trips {
@@ -2802,9 +3748,6 @@
};
aoss-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 0>;
trips {
@@ -2824,7 +3767,6 @@
cpu-0-0-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
@@ -2845,7 +3787,6 @@
cpu-0-1-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
@@ -2866,7 +3807,6 @@
cpu-0-2-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
@@ -2887,7 +3827,6 @@
cpu-0-3-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
@@ -2908,7 +3847,6 @@
gpuss-3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
@@ -2929,7 +3867,6 @@
gpuss-4-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 6>;
@@ -2950,7 +3887,6 @@
gpuss-5-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 7>;
@@ -2970,9 +3906,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 8>;
trips {
@@ -2991,9 +3924,6 @@
};
camss-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 9>;
trips {
@@ -3012,9 +3942,6 @@
};
pcie-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 10>;
trips {
@@ -3033,9 +3960,6 @@
};
cpuss-0-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 11>;
trips {
@@ -3054,9 +3978,6 @@
};
aoss-2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens2 0>;
trips {
@@ -3076,7 +3997,6 @@
cpu-1-0-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 1>;
@@ -3097,7 +4017,6 @@
cpu-1-1-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 2>;
@@ -3118,7 +4037,6 @@
cpu-1-2-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 3>;
@@ -3139,7 +4057,6 @@
cpu-1-3-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 4>;
@@ -3160,7 +4077,6 @@
nsp-0-0-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 5>;
@@ -3181,7 +4097,6 @@
nsp-0-1-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 6>;
@@ -3202,7 +4117,6 @@
nsp-0-2-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 7>;
@@ -3223,7 +4137,6 @@
nsp-1-0-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 8>;
@@ -3244,7 +4157,6 @@
nsp-1-1-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 9>;
@@ -3265,7 +4177,6 @@
nsp-1-2-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 10>;
@@ -3285,9 +4196,6 @@
};
ddrss-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens2 11>;
trips {
@@ -3306,9 +4214,6 @@
};
cpuss-1-0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens2 12>;
trips {
@@ -3327,9 +4232,6 @@
};
aoss-3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens3 0>;
trips {
@@ -3349,7 +4251,6 @@
cpu-1-0-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 1>;
@@ -3370,7 +4271,6 @@
cpu-1-1-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 2>;
@@ -3391,7 +4291,6 @@
cpu-1-2-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 3>;
@@ -3412,7 +4311,6 @@
cpu-1-3-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 4>;
@@ -3433,7 +4331,6 @@
nsp-0-0-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 5>;
@@ -3454,7 +4351,6 @@
nsp-0-1-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 6>;
@@ -3475,7 +4371,6 @@
nsp-0-2-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 7>;
@@ -3496,7 +4391,6 @@
nsp-1-0-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 8>;
@@ -3517,7 +4411,6 @@
nsp-1-1-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 9>;
@@ -3538,7 +4431,6 @@
nsp-1-2-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
thermal-sensors = <&tsens3 10>;
@@ -3558,9 +4450,6 @@
};
ddrss-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens3 11>;
trips {
@@ -3579,9 +4468,6 @@
};
cpuss-1-1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens3 12>;
trips {
@@ -3689,6 +4575,53 @@
};
};
+ pcie0_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sa8775p-pcie-ep";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40200000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>,
+ <0x0 0x40005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio", "dma";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "global", "doorbell", "dma";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ dma-coherent;
+ iommus = <&pcie_smmu 0x0000 0x7f>;
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_0_GDSC>;
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+ max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
@@ -3799,6 +4732,53 @@
};
};
+ pcie1_ep: pcie-ep@1c10000 {
+ compatible = "qcom,sa8775p-pcie-ep";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf20>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x4000>,
+ <0x0 0x60200000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>,
+ <0x0 0x60005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio", "dma";
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "global", "doorbell", "dma";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ dma-coherent;
+ iommus = <&pcie_smmu 0x80 0x7f>;
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_1_GDSC>;
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+ max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+ num-lanes = <4>;
+
+ status = "disabled";
+ };
+
pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-clamshell.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-clamshell.dtsi
new file mode 100644
index 0000000..d91533b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-clamshell.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Trogdor dts fragment for clamshells
+ *
+ * Copyright 2024 Google LLC.
+ */
+
+/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */
+#include <arm/cros-ec-keyboard.dtsi>
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-coachz.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
index 7765c8f..3c124bb 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
@@ -7,6 +7,7 @@
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
+#include "sc7180-trogdor-detachable.dtsi"
/* Deleted nodes from sc7180-trogdor.dtsi */
@@ -25,7 +26,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;
@@ -80,10 +80,6 @@
};
&cros_ec {
- keyboard-controller {
- compatible = "google,cros-ec-keyb-switches";
- };
-
cros_ec_proximity: proximity {
compatible = "google,cros-ec-mkbp-proximity";
label = "proximity-wifi";
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-detachable.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-detachable.dtsi
new file mode 100644
index 0000000..7c5d8a5
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-detachable.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Trogdor dts fragment for detachables
+ *
+ * Copyright 2024 Google LLC.
+ */
+
+/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */
+&cros_ec {
+ keyboard-controller {
+ compatible = "google,cros-ec-keyb-switches";
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-homestar.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-homestar.dtsi
index 2ba3bbf..b2df22f 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-homestar.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-homestar.dtsi
@@ -5,9 +5,8 @@
* Copyright 2021 Google LLC.
*/
-/* This file must be included after sc7180-trogdor.dtsi */
-
#include "sc7180-trogdor-rt5682i-sku.dtsi"
+#include "sc7180-trogdor-detachable.dtsi"
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */
@@ -45,7 +44,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;
@@ -135,12 +133,6 @@
status = "okay";
};
-&cros_ec {
- keyboard-controller {
- compatible = "google,cros-ec-keyb-switches";
- };
-};
-
&panel {
compatible = "samsung,atna33xc20";
enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-kingoftown.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-kingoftown.dts
index d6db7d8..655bea9 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-kingoftown.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-kingoftown.dts
@@ -9,7 +9,7 @@
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
-#include <arm/cros-ec-keyboard.dtsi>
+#include "sc7180-trogdor-clamshell.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
#include "sc7180-trogdor-rt5682s-sku.dtsi"
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts
index 919bfae..340cb11 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-kb.dts
@@ -12,6 +12,6 @@
compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts
index eb20157..d45e60e 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r1-lte.dts
@@ -17,6 +17,6 @@
status = "okay";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-kb.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-kb.dts
index 45d3471..e906ce8 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-kb.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-kb.dts
@@ -18,6 +18,6 @@
compatible = "google,lazor-sku2", "qcom,sc7180";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-lte.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-lte.dts
index 79028d0..4b9ee15 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-lte.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r10-lte.dts
@@ -22,6 +22,6 @@
status = "okay";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts
index 3459b81..a960553 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-kb.dts
@@ -21,6 +21,6 @@
"qcom,sc7180";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts
index ff8f47d..82bd9ed 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r3-lte.dts
@@ -25,6 +25,6 @@
status = "okay";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-kb.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-kb.dts
index faf5279..6278c17 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-kb.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-kb.dts
@@ -18,6 +18,6 @@
compatible = "google,lazor-rev9-sku2", "qcom,sc7180";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-lte.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-lte.dts
index d737fd0..0ec1697 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-lte.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor-r9-lte.dts
@@ -22,6 +22,6 @@
status = "okay";
};
-&keyboard_backlight {
+&pwmleds {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
index e9f213d..c3fd676 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
@@ -5,8 +5,7 @@
* Copyright 2020 Google LLC.
*/
-/* This file must be included after sc7180-trogdor.dtsi */
-#include <arm/cros-ec-keyboard.dtsi>
+#include "sc7180-trogdor-clamshell.dtsi"
&ap_sar_sensor {
semtech,cs0-ground;
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pazquel.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pazquel.dtsi
index 8823edb..cc2c561 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pazquel.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pazquel.dtsi
@@ -5,8 +5,7 @@
* Copyright 2021 Google LLC.
*/
-/* This file must be included after sc7180-trogdor.dtsi */
-#include <arm/cros-ec-keyboard.dtsi>
+#include "sc7180-trogdor-clamshell.dtsi"
&ap_sar_sensor {
compatible = "semtech,sx9324";
@@ -83,6 +82,8 @@
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
+/* PINCTRL - modifications to sc7180-trogdor.dtsi */
+
&en_pp3300_dx_edp {
pins = "gpio67";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index 067813f..ac8d458 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -6,17 +6,13 @@
*/
#include "sc7180-trogdor.dtsi"
-/* Must come after sc7180-trogdor.dtsi to modify cros_ec */
-#include <arm/cros-ec-keyboard.dtsi>
+#include "sc7180-trogdor-clamshell.dtsi"
#include "sc7180-trogdor-rt5682i-sku.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/ {
thermal-zones {
5v-choke-thermal {
- polling-delay-passive = <0>;
- polling-delay = <250>;
-
thermal-sensors = <&pm6150_adc_tm 1>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
index 5f06842..00229b1 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
@@ -9,9 +9,7 @@
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-rt5682i-sku.dtsi"
-
-/* This board only has 1 USB Type-C port. */
-/delete-node/ &usb_c1;
+#include "sc7180-trogdor-detachable.dtsi"
/ {
ppvar_lcd: ppvar-lcd-regulator {
@@ -47,12 +45,6 @@
status = "okay";
};
-&cros_ec {
- keyboard-controller {
- compatible = "google,cros-ec-keyb-switches";
- };
-};
-
&gpio_keys {
status = "okay";
};
@@ -136,6 +128,11 @@
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
+/* This board only has 1 USB Type-C port. */
+&usb_c1 {
+ status = "disabled";
+};
+
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
/*
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-r1.dts b/dts/upstream/src/arm64/qcom/sc7180-trogdor-r1.dts
index c966775..d393a27 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-r1.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-r1.dts
@@ -8,8 +8,7 @@
/dts-v1/;
#include "sc7180-trogdor.dtsi"
-/* Must come after sc7180-trogdor.dtsi to modify cros_ec */
-#include <arm/cros-ec-keyboard.dtsi>
+#include "sc7180-trogdor-clamshell.dtsi"
#include "sc7180-trogdor-rt5682i-sku.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-wormdingler.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-wormdingler.dtsi
index 305ad12..af89d80 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-wormdingler.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-wormdingler.dtsi
@@ -8,6 +8,7 @@
/dts-v1/;
#include "sc7180-trogdor.dtsi"
+#include "sc7180-trogdor-detachable.dtsi"
/ {
avdd_lcd: avdd-lcd-regulator {
@@ -50,7 +51,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <574>;
@@ -104,10 +104,6 @@
base_detection: cbas {
compatible = "google,cros-cbas";
};
-
- keyboard-controller {
- compatible = "google,cros-ec-keyb-switches";
- };
};
&i2c4 {
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi
index 8513be2..74ab321 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor.dtsi
@@ -21,9 +21,6 @@
/ {
thermal-zones {
charger_thermal: charger-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm6150_adc_tm 0>;
trips {
@@ -359,10 +356,11 @@
#sound-dai-cells = <0>;
};
- pwmleds {
+ pwmleds: pwmleds {
compatible = "pwm-leds";
+ status = "disabled";
+
keyboard_backlight: led-0 {
- status = "disabled";
label = "cros_ec::kbd_backlight";
function = LED_FUNCTION_KBD_BACKLIGHT;
pwms = <&cros_ec_pwm 0>;
diff --git a/dts/upstream/src/arm64/qcom/sc7180.dtsi b/dts/upstream/src/arm64/qcom/sc7180.dtsi
index 4774a85..b5ebf89 100644
--- a/dts/upstream/src/arm64/qcom/sc7180.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180.dtsi
@@ -1582,8 +1582,7 @@
};
ufs_mem_phy: phy@1d87000 {
- compatible = "qcom,sc7180-qmp-ufs-phy",
- "qcom,sm7150-qmp-ufs-phy";
+ compatible = "qcom,sc7180-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
@@ -3067,6 +3066,7 @@
iommus = <&apps_smmu 0x540 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
@@ -4036,7 +4036,6 @@
thermal-zones {
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
sustainable-power = <1052>;
@@ -4085,7 +4084,6 @@
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
sustainable-power = <1052>;
@@ -4134,7 +4132,6 @@
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
sustainable-power = <1052>;
@@ -4183,7 +4180,6 @@
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
sustainable-power = <1052>;
@@ -4232,7 +4228,6 @@
cpu4_thermal: cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
sustainable-power = <1052>;
@@ -4281,7 +4276,6 @@
cpu5_thermal: cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
sustainable-power = <1052>;
@@ -4330,7 +4324,6 @@
cpu6_thermal: cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
sustainable-power = <1425>;
@@ -4371,7 +4364,6 @@
cpu7_thermal: cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
sustainable-power = <1425>;
@@ -4412,7 +4404,6 @@
cpu8_thermal: cpu8-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
sustainable-power = <1425>;
@@ -4453,7 +4444,6 @@
cpu9_thermal: cpu9-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
sustainable-power = <1425>;
@@ -4494,7 +4484,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
@@ -4515,7 +4504,6 @@
cpuss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
@@ -4535,7 +4523,6 @@
cpuss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
@@ -4555,7 +4542,6 @@
gpuss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
@@ -4583,7 +4569,6 @@
gpuss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
@@ -4611,7 +4596,6 @@
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
@@ -4632,7 +4616,6 @@
cwlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
@@ -4653,7 +4636,6 @@
audio-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
@@ -4674,7 +4656,6 @@
ddr-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
@@ -4695,7 +4676,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
@@ -4716,7 +4696,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
@@ -4737,7 +4716,6 @@
mdm-core-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 6>;
@@ -4758,7 +4736,6 @@
mdm-dsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 7>;
@@ -4779,7 +4756,6 @@
npu-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
@@ -4800,7 +4776,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 9>;
diff --git a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
index a005952..7370aa0 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
@@ -495,7 +495,6 @@
};
&uart5 {
- compatible = "qcom,geni-debug-uart";
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi b/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi
index f9b96bd..7d1d5bb 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-qcard.dtsi
@@ -427,7 +427,6 @@
};
uart_dbg: &uart5 {
- compatible = "qcom,geni-debug-uart";
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7280.dtsi b/dts/upstream/src/arm64/qcom/sc7280.dtsi
index fc9ec36..3d84106 100644
--- a/dts/upstream/src/arm64/qcom/sc7280.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280.dtsi
@@ -24,6 +24,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/thermal/thermal.h>
@@ -710,6 +711,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sc7280", "qcom,scm";
+ qcom,dload-mode = <&tcsr_2 0x13000>;
};
};
@@ -1440,12 +1442,12 @@
};
uart5: serial@994000 {
- compatible = "qcom,geni-uart";
+ compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
+ pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
@@ -2129,6 +2131,8 @@
reg = <0 0x016e0000 0 0x1c080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
@@ -2136,6 +2140,7 @@
compatible = "qcom,sc7280-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1740000 {
@@ -2989,6 +2994,18 @@
dma-coherent;
};
+ gfx_0_tbu: tbu@3dd9000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x3dd9000 0x0 0x1000>;
+ qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
+ };
+
+ gfx_1_tbu: tbu@3ddd000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x3ddd000 0x0 0x1000>;
+ qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
+ };
+
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
reg = <0 0x04080000 0 0x10000>;
@@ -3762,6 +3779,75 @@
label = "lpass";
qcom,remote-pid = <2>;
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ service@3 {
+ reg = <APR_SVC_ADSP_CORE>;
+ compatible = "qcom,q6core";
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+
+ q6afecc: clock-controller {
+ compatible = "qcom,q6afe-clocks";
+ #clock-cells = <2>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ iommus = <&apps_smmu 0x1801 0x0>;
+
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
@@ -4150,6 +4236,7 @@
iommus = <&apps_smmu 0xe0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
@@ -5407,16 +5494,6 @@
function = "qup04";
};
- qup_uart5_cts: qup-uart5-cts-state {
- pins = "gpio20";
- function = "qup05";
- };
-
- qup_uart5_rts: qup-uart5-rts-state {
- pins = "gpio21";
- function = "qup05";
- };
-
qup_uart5_tx: qup-uart5-tx-state {
pins = "gpio22";
function = "qup05";
@@ -5802,6 +5879,83 @@
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
};
+ anoc_1_tbu: tbu@151dd000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151dd000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
+ };
+
+ anoc_2_tbu: tbu@151e1000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151e1000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
+ };
+
+ mnoc_hf_0_tbu: tbu@151e5000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151e5000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
+ };
+
+ mnoc_hf_1_tbu: tbu@151e9000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151e9000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
+ };
+
+ compute_dsp_1_tbu: tbu@151ed000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151ed000 0x0 0x1000>;
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
+ };
+
+ compute_dsp_0_tbu: tbu@151f1000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151f1000 0x0 0x1000>;
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
+ };
+
+ adsp_tbu: tbu@151f5000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151f5000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
+ };
+
+ anoc_1_pcie_tbu: tbu@151f9000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151f9000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
+ };
+
+ mnoc_sf_0_tbu: tbu@151fd000 {
+ compatible = "qcom,sc7280-tbu";
+ reg = <0x0 0x151fd000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0 0x17a00000 0 0x10000>, /* GICD */
@@ -5991,10 +6145,12 @@
};
};
+ sound: sound {
+ };
+
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
@@ -6038,7 +6194,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
@@ -6082,7 +6237,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
@@ -6126,7 +6280,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
@@ -6170,7 +6323,6 @@
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
@@ -6214,7 +6366,6 @@
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
@@ -6258,7 +6409,6 @@
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
@@ -6302,7 +6452,6 @@
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
@@ -6346,7 +6495,6 @@
cpu8-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
@@ -6390,7 +6538,6 @@
cpu9-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
@@ -6434,7 +6581,6 @@
cpu10-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
@@ -6478,7 +6624,6 @@
cpu11-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
@@ -6522,7 +6667,6 @@
aoss0-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
@@ -6543,7 +6687,6 @@
aoss1-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
@@ -6564,7 +6707,6 @@
cpuss0-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
@@ -6584,7 +6726,6 @@
cpuss1-thermal {
polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
@@ -6604,7 +6745,6 @@
gpuss0-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
@@ -6632,7 +6772,6 @@
gpuss1-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
@@ -6659,9 +6798,6 @@
};
nspss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 3>;
trips {
@@ -6680,9 +6816,6 @@
};
nspss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 4>;
trips {
@@ -6701,9 +6834,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 5>;
trips {
@@ -6722,9 +6852,6 @@
};
ddr-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 6>;
trips {
@@ -6743,9 +6870,6 @@
};
mdmss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 7>;
trips {
@@ -6764,9 +6888,6 @@
};
mdmss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 8>;
trips {
@@ -6785,9 +6906,6 @@
};
mdmss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 9>;
trips {
@@ -6806,9 +6924,6 @@
};
mdmss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 10>;
trips {
@@ -6827,9 +6942,6 @@
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 11>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
index 6af9911..5b22657 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
@@ -68,7 +68,7 @@
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -103,7 +103,7 @@
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -582,6 +582,10 @@
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -590,8 +594,8 @@
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_sec_hsphy {
@@ -619,10 +623,6 @@
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-pmics.dtsi b/dts/upstream/src/arm64/qcom/sc8180x-pmics.dtsi
index ddc8428..1c6f12f 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8180x-pmics.dtsi
@@ -13,7 +13,6 @@
thermal-zones {
pmc8180-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmc8180_temp>;
@@ -40,7 +39,6 @@
pmc8180c-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
thermal-sensors = <&pmc8180c_temp>;
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
index bfee60c..65d9234 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
@@ -71,7 +71,7 @@
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -106,7 +106,7 @@
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -648,6 +648,10 @@
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -656,10 +660,6 @@
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_sec_hsphy {
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
@@ -685,10 +685,6 @@
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
@@ -697,6 +693,10 @@
dr_mode = "host";
};
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&wifi {
memory-region = <&wlan_mem>;
diff --git a/dts/upstream/src/arm64/qcom/sc8180x.dtsi b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
index 581a70c..6e707d9 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -1890,7 +1891,7 @@
power-domains = <&gcc PCIE_3_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
- <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie3_phy>;
@@ -2012,7 +2013,7 @@
power-domains = <&gcc PCIE_1_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
- <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie1_phy>;
@@ -2134,7 +2135,7 @@
power-domains = <&gcc PCIE_2_GDSC>;
interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
- <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie2_phy>;
@@ -2245,18 +2246,13 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
#phy-cells = <0>;
status = "disabled";
};
- ipa_virt: interconnect@1e00000 {
- compatible = "qcom,sc8180x-ipa-virt";
- reg = <0 0x01e00000 0 0x1000>;
- #interconnect-cells = <2>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- };
-
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -2511,28 +2507,25 @@
status = "disabled";
};
- usb_prim_qmpphy: phy@88e9000 {
+ usb_prim_qmpphy: phy@88e8000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088e8000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
+
resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2546,59 +2539,40 @@
usb_prim_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_prim_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_prim_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
usb_prim_qmpphy_dp_in: endpoint {};
};
};
-
- usb_prim_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_prim_phy_pipe_clk_src";
- };
-
- usb_prim_dpphy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
};
usb_sec_qmpphy: phy@88ee000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088ee000 0 0x18c>,
- <0 0x088ed000 0 0x10>,
- <0 0x088ef000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088ed000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2612,37 +2586,20 @@
usb_sec_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_sec_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_sec_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
usb_sec_qmpphy_dp_in: endpoint {};
};
};
-
- usb_sec_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088ee200 0 0x200>,
- <0 0x088ee400 0 0x200>,
- <0 0x088eec00 0 0x218>,
- <0 0x088ee600 0 0x200>,
- <0 0x088ee800 0 0x200>,
- <0 0x088eea00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_sec_phy_pipe_clk_src";
- };
-
- usb_sec_dpphy: dp-phy@88ef200 {
- reg = <0 0x088ef200 0 0x200>,
- <0 0x088ef400 0 0x200>,
- <0 0x088efa00 0 0x200>,
- <0 0x088ef600 0 0x200>,
- <0 0x088ef800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- clock-output-names = "qmp_dptx1_phy_pll_link_clk",
- "qmp_dptx1_phy_pll_vco_div_clk";
- };
};
system-cache-controller@9200000 {
@@ -2714,11 +2671,26 @@
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
+ phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_prim_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_prim_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_prim_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -2771,11 +2743,26 @@
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
+ phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_sec_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_sec_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_sec_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3089,9 +3076,10 @@
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
+ assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_prim_dpphy>;
+ phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3166,9 +3154,10 @@
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
- assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
+ assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_sec_dpphy>;
+ phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3311,21 +3300,27 @@
compatible = "qcom,sc8180x-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&sleep_clk>,
- <&usb_prim_dpphy 0>,
- <&usb_prim_dpphy 1>,
- <&usb_sec_dpphy 0>,
- <&usb_sec_dpphy 1>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&edp_phy 0>,
- <&edp_phy 1>;
+ <&edp_phy 1>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
- "sleep_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk";
+ "edp_phy_pll_vco_div_clk",
+ "dptx1_phy_pll_link_clk",
+ "dptx1_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
@@ -3371,7 +3366,6 @@
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
- #power-domain-cells = <1>;
};
sram@c3f0000 {
@@ -3774,7 +3768,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -3789,7 +3782,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -3804,7 +3796,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -3819,7 +3810,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -3834,7 +3824,6 @@
cpu4-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -3849,7 +3838,6 @@
cpu5-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -3864,7 +3852,6 @@
cpu6-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -3879,7 +3866,6 @@
cpu7-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -3894,7 +3880,6 @@
cpu4-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -3909,7 +3894,6 @@
cpu5-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -3924,7 +3908,6 @@
cpu6-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
@@ -3939,7 +3922,6 @@
cpu7-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
@@ -3954,7 +3936,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
@@ -3969,7 +3950,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -3984,7 +3964,6 @@
cluster1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -3999,7 +3978,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
@@ -4012,16 +3990,27 @@
trips {
gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
@@ -4036,7 +4025,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -4051,7 +4039,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -4066,7 +4053,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -4081,7 +4067,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -4096,7 +4081,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -4111,7 +4095,6 @@
compute-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -4126,7 +4109,6 @@
mdm-dsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -4141,7 +4123,6 @@
npu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
@@ -4156,7 +4137,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 11>;
@@ -4169,10 +4149,22 @@
trips {
gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
index 372b35f..b98b2f7 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
@@ -56,7 +56,7 @@
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -91,7 +91,7 @@
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -675,6 +675,10 @@
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -700,10 +704,6 @@
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -712,6 +712,10 @@
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -737,10 +741,6 @@
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&xo_board_clk {
clock-frequency = <38400000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 4bf99b6..b27143f 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -117,7 +117,7 @@
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -152,7 +152,7 @@
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -297,9 +297,30 @@
};
thermal-zones {
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
skin-temp-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8280_adc_tm 5>;
trips {
@@ -671,6 +692,85 @@
};
};
+&i2c11 {
+ clock-frequency = <400000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c11_default>;
+
+ status = "okay";
+
+ pm8008: pmic@c {
+ compatible = "qcom,pm8008";
+ reg = <0xc>;
+
+ interrupts-extended = <&tlmm 41 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s11b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_default>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1q: ldo1 {
+ regulator-name = "vreg_l1q";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2q: ldo2 {
+ regulator-name = "vreg_l2q";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3q: ldo3 {
+ regulator-name = "vreg_l3q";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vreg_l4q: ldo4 {
+ regulator-name = "vreg_l4q";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vreg_l5q: ldo5 {
+ regulator-name = "vreg_l5q";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l6q: ldo6 {
+ regulator-name = "vreg_l6q";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l7q: ldo7 {
+ regulator-name = "vreg_l7q";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ };
+ };
+};
+
&i2c21 {
clock-frequency = <400000>;
@@ -1132,6 +1232,10 @@
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -1157,10 +1261,6 @@
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -1169,6 +1269,10 @@
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -1194,10 +1298,6 @@
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_2 {
status = "okay";
};
@@ -1356,6 +1456,13 @@
bias-disable;
};
+ i2c11_default: i2c11-default-state {
+ pins = "gpio18", "gpio19";
+ function = "qup11";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
i2c21_default: i2c21-default-state {
pins = "gpio81", "gpio82";
function = "qup21";
@@ -1459,6 +1566,22 @@
};
};
+ pm8008_default: pm8008-default-state {
+ int-pins {
+ pins = "gpio41";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ reset-n-pins {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
spkr_1_sd_n_default: spkr-1-sd-n-default-state {
perst-n-pins {
pins = "gpio178";
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-pmics.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp-pmics.dtsi
index 945de77..1e3babf 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-pmics.dtsi
@@ -14,7 +14,7 @@
thermal-zones {
pm8280_1_thermal: pm8280-1-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm8280_1_temp_alarm>;
trips {
@@ -34,7 +34,7 @@
pm8280_2_thermal: pm8280-2-thermal {
polling-delay-passive = <100>;
- polling-delay = <0>;
+
thermal-sensors = <&pm8280_2_temp_alarm>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
index 59f0a85..80a57aa 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
@@ -3222,6 +3222,14 @@
usb_0_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3275,6 +3283,14 @@
usb_1_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3560,8 +3576,23 @@
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_0_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3622,8 +3653,23 @@
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
- port {
- usb_1_role_switch: endpoint {
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -5833,7 +5879,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -5848,7 +5893,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -5863,7 +5907,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -5878,7 +5921,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -5893,7 +5935,6 @@
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -5908,7 +5949,6 @@
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -5923,7 +5963,6 @@
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -5938,7 +5977,6 @@
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -5953,7 +5991,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -5967,13 +6004,25 @@
};
gpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <250>;
thermal-sensors = <&tsens2 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- gpu-crit {
+ gpu_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
@@ -5983,7 +6032,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 15>;
diff --git a/dts/upstream/src/arm64/qcom/sda660-inforce-ifc6560.dts b/dts/upstream/src/arm64/qcom/sda660-inforce-ifc6560.dts
index 702ab49..6041228 100644
--- a/dts/upstream/src/arm64/qcom/sda660-inforce-ifc6560.dts
+++ b/dts/upstream/src/arm64/qcom/sda660-inforce-ifc6560.dts
@@ -96,6 +96,18 @@
vin-supply = <&vph_pwr>;
};
+
+ /*
+ * this is also used for APC1 CPU power, touching it resets the board
+ */
+ vreg_l10a_1p8: vreg-l10a-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_l10a_1p8";
+ regulator-min-microvolt = <1804000>;
+ regulator-max-microvolt = <1896000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&adsp_pil {
@@ -220,6 +232,7 @@
status = "okay";
vdd-supply = <&vreg_l1b_0p925>;
+ vdda-pll-supply = <&vreg_l10a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
};
@@ -227,6 +240,7 @@
status = "okay";
vdd-supply = <&vreg_l1b_0p925>;
+ vdda-pll-supply = <&vreg_l10a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
};
@@ -464,5 +478,6 @@
&usb3_qmpphy {
vdda-phy-supply = <&vreg_l1b_0p925>;
+ vdda-pll-supply = <&vreg_l10a_1p8>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
new file mode 100644
index 0000000..175befc
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Neil Armstrong <neil.armstrong@linaro.org>
+ */
+/dts-v1/;
+
+#include "sdm450.dtsi"
+#include "pm8953.dtsi"
+#include "pmi8950.dtsi"
+
+/ {
+ model = "Lenovo Smart Tab M10";
+ compatible = "lenovo,tbx605f", "qcom,sdm450";
+ chassis-type = "tablet";
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@90001000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x90001000 0 (1200 * 1920 * 3)>;
+
+ width = <1200>;
+ height = <1920>;
+ stride = <(1200 * 3)>;
+ format = "r8g8b8";
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_BYTE0_CLK>,
+ <&gcc GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>;
+ };
+ };
+
+ reserved-memory {
+ other_ext_region@0 {
+ no-map;
+ reg = <0x00 0x84500000 0x00 0x2300000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ key-volume-up {
+ label = "volume_up";
+ gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&hsusb_phy {
+ vdd-supply = <&pm8953_l3>;
+ vdda-pll-supply = <&pm8953_l7>;
+ vdda-phy-dpdm-supply = <&pm8953_l13>;
+
+ status = "okay";
+};
+
+&i2c_3 {
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5506";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <65 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply = <&pm8953_l10>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1200>;
+ touchscreen-size-y = <1920>;
+ };
+};
+
+&pm8953_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8953-regulators";
+
+ vdd_s1-supply = <&vph_pwr>;
+ vdd_s2-supply = <&vph_pwr>;
+ vdd_s3-supply = <&vph_pwr>;
+ vdd_s4-supply = <&vph_pwr>;
+ vdd_s5-supply = <&vph_pwr>;
+ vdd_s6-supply = <&vph_pwr>;
+ vdd_s7-supply = <&vph_pwr>;
+ vdd_l1-supply = <&pm8953_s3>;
+ vdd_l2_l3-supply = <&pm8953_s3>;
+ vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>;
+ vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>;
+ vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>;
+
+ pm8953_s1: s1 {
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <1156000>;
+ };
+
+ pm8953_s3: s3 {
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1224000>;
+ };
+
+ pm8953_s4: s4 {
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8953_l1: l1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ pm8953_l2: l2 {
+ regulator-min-microvolt = <975000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8953_l3: l3 {
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ };
+
+ pm8953_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8953_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8953_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ pm8953_l8: l8 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ pm8953_l9: l9 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8953_l10: l10 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8953_l11: l11 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8953_l12: l12 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8953_l13: l13 {
+ regulator-min-microvolt = <3125000>;
+ regulator-max-microvolt = <3125000>;
+ };
+
+ pm8953_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8953_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8953_l19: l19 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8953_l22: l22 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8953_l23: l23 {
+ regulator-min-microvolt = <975000>;
+ regulator-max-microvolt = <1225000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8953_l8>;
+ vqmmc-supply = <&pm8953_l5>;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8953_l11>;
+ vqmmc-supply = <&pm8953_l12>;
+
+ cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <135 4>;
+
+ ts_int_active: ts-int-active-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ ts_reset_active: ts-reset-active-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <0x08>;
+ bias-pull-up;
+ };
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&wcnss {
+ vddpx-supply = <&pm8953_l5>;
+
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3660b";
+
+ vddxo-supply = <&pm8953_l7>;
+ vddrfa-supply = <&pm8953_l19>;
+ vddpa-supply = <&pm8953_l9>;
+ vdddig-supply = <&pm8953_l5>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sdm450-motorola-ali.dts b/dts/upstream/src/arm64/qcom/sdm450-motorola-ali.dts
index e27f3c5..a288d52 100644
--- a/dts/upstream/src/arm64/qcom/sdm450-motorola-ali.dts
+++ b/dts/upstream/src/arm64/qcom/sdm450-motorola-ali.dts
@@ -248,5 +248,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/sdm630.dtsi b/dts/upstream/src/arm64/qcom/sdm630.dtsi
index f5921b8..c7e3764 100644
--- a/dts/upstream/src/arm64/qcom/sdm630.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm630.dtsi
@@ -1302,6 +1302,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&qusb2phy0>, <&usb3_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
@@ -2422,7 +2423,6 @@
thermal-zones {
aoss-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -2437,7 +2437,6 @@
cpuss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
@@ -2452,7 +2451,6 @@
cpuss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
@@ -2467,7 +2465,6 @@
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
@@ -2488,7 +2485,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -2509,7 +2505,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -2530,7 +2525,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -2557,7 +2551,6 @@
pwr-cluster-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -2578,7 +2571,6 @@
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -2591,20 +2583,32 @@
trips {
gpu_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 0xf08>,
- <GIC_PPI 2 0xf08>,
- <GIC_PPI 3 0xf08>,
- <GIC_PPI 0 0xf08>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts b/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
index e2708c7..2c1172a 100644
--- a/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
+++ b/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
@@ -143,6 +143,10 @@
status = "okay";
};
+&pmi632_vib {
+ status = "okay";
+};
+
&sdhc_1 {
status = "okay";
vmmc-supply = <&pm8953_l8>;
diff --git a/dts/upstream/src/arm64/qcom/sdm632-motorola-ocean.dts b/dts/upstream/src/arm64/qcom/sdm632-motorola-ocean.dts
index c82d6e6..2f55db0 100644
--- a/dts/upstream/src/arm64/qcom/sdm632-motorola-ocean.dts
+++ b/dts/upstream/src/arm64/qcom/sdm632-motorola-ocean.dts
@@ -287,5 +287,6 @@
};
&usb3_dwc3 {
+ /delete-property/ usb-role-switch;
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/sdm670.dtsi b/dts/upstream/src/arm64/qcom/sdm670.dtsi
index 80e81c4..187c669 100644
--- a/dts/upstream/src/arm64/qcom/sdm670.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm670.dtsi
@@ -509,6 +509,18 @@
no-map;
};
+ smem@86000000 {
+ compatible = "qcom,smem";
+ reg = <0 0x86000000 0 0x200000>;
+ no-map;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ tz_mem: tz@86200000 {
+ reg = <0 0x86200000 0 0x2d00000>;
+ no-map;
+ };
+
camera_mem: camera-mem@8ab00000 {
reg = <0 0x8ab00000 0 0x500000>;
no-map;
@@ -1139,6 +1151,12 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0 0x01f40000 0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
tlmm: pinctrl@3400000 {
compatible = "qcom,sdm670-tlmm";
reg = <0 0x03400000 0 0xc00000>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-mtp.dts b/dts/upstream/src/arm64/qcom/sdm845-mtp.dts
index 76bfa78..2391f84 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sdm845-mtp.dts
@@ -51,9 +51,6 @@
thermal-zones {
xo_thermal: xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm8998_adc_tm 1>;
trips {
@@ -66,9 +63,6 @@
};
msm_thermal: msm-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm8998_adc_tm 2>;
trips {
@@ -81,9 +75,6 @@
};
pa_thermal: pa-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm8998_adc_tm 3>;
trips {
@@ -96,9 +87,6 @@
};
quiet_thermal: quiet-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&pm8998_adc_tm 4>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sdm845.dtsi b/dts/upstream/src/arm64/qcom/sdm845.dtsi
index 10de2bd..5407754 100644
--- a/dts/upstream/src/arm64/qcom/sdm845.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -2666,6 +2667,8 @@
"ref_aux",
"qref";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -4028,6 +4031,35 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&dp_out>;
+ };
+ };
+ };
};
usb_2_qmpphy: phy@88eb000 {
@@ -4106,8 +4138,29 @@
iommus = <&apps_smmu 0x740 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
};
};
@@ -4161,6 +4214,7 @@
iommus = <&apps_smmu 0x760 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-ss-quirk;
phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -4598,7 +4652,9 @@
port@1 {
reg = <1>;
- dp_out: endpoint { };
+ dp_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_dp_in>;
+ };
};
};
@@ -5105,6 +5161,78 @@
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
};
+ anoc_1_tbu: tbu@150c5000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150c5000 0x0 0x1000>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
+ };
+
+ anoc_2_tbu: tbu@150c9000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150c9000 0x0 0x1000>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
+ };
+
+ mnoc_hf_0_tbu: tbu@150cd000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150cd000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
+ };
+
+ mnoc_hf_1_tbu: tbu@150d1000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150d1000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
+ };
+
+ mnoc_sf_0_tbu: tbu@150d5000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150d5000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
+ };
+
+ compute_dsp_tbu: tbu@150d9000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150d9000 0x0 0x1000>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
+ };
+
+ adsp_tbu: tbu@150dd000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150dd000 0x0 0x1000>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
+ };
+
+ anoc_1_pcie_tbu: tbu@150e1000 {
+ compatible = "qcom,sdm845-tbu";
+ reg = <0x0 0x150e1000 0x0 0x1000>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
+ qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
+ };
+
lpasscc: clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
@@ -5358,7 +5486,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -5385,7 +5512,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -5412,7 +5538,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -5439,7 +5564,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -5466,7 +5590,6 @@
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -5493,7 +5616,6 @@
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -5520,7 +5642,6 @@
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -5547,7 +5668,6 @@
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -5574,7 +5694,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
@@ -5589,7 +5708,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -5609,7 +5727,6 @@
cluster1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -5629,7 +5746,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -5642,16 +5758,27 @@
trips {
gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -5664,16 +5791,27 @@
trips {
gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
@@ -5688,7 +5826,6 @@
q6-modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -5703,7 +5840,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -5718,7 +5854,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -5733,7 +5868,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -5748,7 +5882,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -5763,7 +5896,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -5778,7 +5910,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
diff --git a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
index 47dc42f..f180508 100644
--- a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
@@ -370,6 +370,66 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+
+ embedded-controller@70 {
+ compatible = "lenovo,yoga-c630-ec";
+ reg = <0x70>;
+
+ interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ec_int_state>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "host";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ucsi0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ucsi0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ucsi0_sbu: endpoint {
+ };
+ };
+ };
+ };
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "host";
+
+ /*
+ * connected to the onboard USB hub, orientation is
+ * handled by the controller
+ */
+ };
+ };
};
&i2c3 {
@@ -494,6 +554,7 @@
&ipa {
qcom,gsi-loader = "self";
memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sdm850/LENOVO/81JL/ipa_fws.elf";
status = "okay";
};
@@ -694,6 +755,13 @@
bias-disable;
};
+
+ ec_int_state: ec-int-state {
+ pins = "gpio20";
+ function = "gpio";
+
+ bias-disable;
+ };
};
&uart6 {
@@ -741,6 +809,10 @@
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&ucsi0_hs_in>;
+};
+
&usb_1_hsphy {
status = "okay";
@@ -761,6 +833,10 @@
vdda-pll-supply = <&vdda_usb1_ss_core>;
};
+&usb_1_qmpphy_out {
+ remote-endpoint = <&ucsi0_ss_in>;
+};
+
&usb_2 {
status = "okay";
};
@@ -834,6 +910,7 @@
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
+ qcom,ath10k-calibration-variant = "Lenovo_C630";
};
&crypto {
diff --git a/dts/upstream/src/arm64/qcom/sdx75-idp.dts b/dts/upstream/src/arm64/qcom/sdx75-idp.dts
index f76e72f..fde1630 100644
--- a/dts/upstream/src/arm64/qcom/sdx75-idp.dts
+++ b/dts/upstream/src/arm64/qcom/sdx75-idp.dts
@@ -41,6 +41,29 @@
vin-supply = <&vph_ext>;
};
+
+ reg_2v952_vcc: regulator-2v952-vcc {
+ compatible = "regulator-gpio";
+ regulator-name = "2v952_vcc";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3600000>;
+ enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+ states = <1650000 0>, <3600000 1>;
+ startup-delay-us = <5000>;
+ enable-active-high;
+ regulator-boot-on;
+
+ vin-supply = <&vph_ext>;
+ };
+
+ reg_2v95_vdd: regulator-2v95-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "2v95_vdd";
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ vin-supply = <®_2v952_vcc>;
+ };
};
&apps_rsc {
@@ -259,8 +282,30 @@
status = "okay";
};
+&sdhc {
+ cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_2v95_vdd>;
+ vqmmc-supply = <®_2v952_vcc>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc1_default &sd_cd>;
+ pinctrl-1 = <&sdc1_sleep &sd_cd>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <110 6>;
+
+ sd_cd: sd-cd-state {
+ pins = "gpio103";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
&uart1 {
diff --git a/dts/upstream/src/arm64/qcom/sdx75.dtsi b/dts/upstream/src/arm64/qcom/sdx75.dtsi
index da17040..9b93f65 100644
--- a/dts/upstream/src/arm64/qcom/sdx75.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdx75.dtsi
@@ -8,9 +8,12 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sdx75.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -405,7 +408,42 @@
};
};
- smem: qcom,smem {
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smem: smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
@@ -441,6 +479,37 @@
#power-domain-cells = <1>;
};
+ ipcc: mailbox@408000 {
+ compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ gpi_dma: dma-controller@900000 {
+ compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00900000 0x0 0x60000>;
+ #dma-cells = <3>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x7f>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x2000>;
@@ -457,6 +526,52 @@
ranges;
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00980000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00980000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
uart1: serial@984000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00984000 0x0 0x4000>;
@@ -475,6 +590,229 @@
"sleep";
status = "disabled";
};
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00988000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00988000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00990000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00994000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00998000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00998000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0099c000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0099c000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ pinctrl-names = "default";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
usb_hsphy: phy@ff4000 {
@@ -538,6 +876,59 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sdx75-tcsr", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0x30000>;
+ };
+
+ sdhc: mmc@8804000 {
+ compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+ iommus = <&apps_smmu 0x00a0 0x0>;
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+ bus-width = <4>;
+ dma-coherent;
+
+ /* Forbid SDR104/SDR50 - broken hw! */
+ sdhci-caps-mask = <0x3 0>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
usb: usb@a6f8800 {
compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
reg = <0x0 0x0a6f8800 0x0 0x400>;
@@ -627,6 +1018,17 @@
interrupt-controller;
};
+ aoss_qmp: power-controller@c310000 {
+ compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c310000 0 0x1000>;
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c400000 0x0 0x3000>,
@@ -661,6 +1063,145 @@
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio110", "gpio111";
+ function = "qup_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio112", "gpio113";
+ function = "qup_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio116", "gpio117";
+ function = "qup_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio11";
+ function = "qup_se0";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup_se0";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio17";
+ function = "qup_se2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup_se2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio55";
+ function = "qup_se3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup_se3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio115";
+ function = "qup_se6";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio112", "gpio113", "gpio114";
+ function = "qup_se6";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi7_cs: qup-spi7-cs-state {
+ pins = "gpio119";
+ function = "qup_se7";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio116", "gpio117", "gpio118";
+ function = "qup_se7";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ qup_uart4_cts_rts: qup-uart4-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio52", "gpio53";
+ function = "qup_se3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ /* TX, RX */
+ pins = "gpio54", "gpio55";
+ function = "qup_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
tx-pins {
pins = "gpio12";
@@ -683,6 +1224,46 @@
drive-strength = <2>;
bias-pull-down;
};
+
+ sdc1_default: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc1_sleep: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
apps_smmu: iommu@15000000 {
diff --git a/dts/upstream/src/arm64/qcom/sm4250-oneplus-billie2.dts b/dts/upstream/src/arm64/qcom/sm4250-oneplus-billie2.dts
index 2c7a129..9153a5a 100644
--- a/dts/upstream/src/arm64/qcom/sm4250-oneplus-billie2.dts
+++ b/dts/upstream/src/arm64/qcom/sm4250-oneplus-billie2.dts
@@ -240,6 +240,7 @@
};
&usb_dwc3 {
+ /delete-property/ usb-role-switch;
maximum-speed = "high-speed";
dr_mode = "peripheral";
diff --git a/dts/upstream/src/arm64/qcom/sm4450.dtsi b/dts/upstream/src/arm64/qcom/sm4450.dtsi
index 603c962..9c9919e 100644
--- a/dts/upstream/src/arm64/qcom/sm4450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4450.dtsi
@@ -29,6 +29,14 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
};
cpus {
@@ -39,10 +47,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -63,10 +73,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
@@ -81,10 +93,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
@@ -99,10 +113,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
@@ -117,10 +133,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
@@ -135,10 +153,12 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
@@ -153,10 +173,12 @@
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
@@ -171,10 +193,12 @@
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x700>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
@@ -268,9 +292,14 @@
reg = <0x0 0xa0000000 0x0 0x0>;
};
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
- pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@@ -526,6 +555,19 @@
};
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x17d91000 0 0x1000>,
+ <0 0x17d92000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
diff --git a/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts b/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts
index 98eb072..4a30024 100644
--- a/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts
+++ b/dts/upstream/src/arm64/qcom/sm6115-fxtec-pro1x.dts
@@ -234,6 +234,7 @@
};
&usb_dwc3 {
+ /delete-property/ usb-role-switch;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/sm6115.dtsi b/dts/upstream/src/arm64/qcom/sm6115.dtsi
index 9ed0621..e374733 100644
--- a/dts/upstream/src/arm64/qcom/sm6115.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6115.dtsi
@@ -1088,6 +1088,8 @@
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface", "core", "xo", "ice";
+ resets = <&gcc GCC_SDCC1_BCR>;
+
power-domains = <&rpmpd SM6115_VDDCX>;
operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0x00c0 0x0>;
@@ -1231,6 +1233,8 @@
"ref_aux",
"qref";
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -1656,6 +1660,7 @@
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
+ snps,parkmode-disable-ss-quirk;
usb-role-switch;
@@ -3012,8 +3017,6 @@
thermal-zones {
mapss-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -3032,8 +3035,6 @@
};
cdsp-hvx-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -3052,8 +3053,6 @@
};
wlan-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -3072,8 +3071,6 @@
};
camera-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -3092,8 +3089,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -3112,8 +3107,6 @@
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -3132,8 +3125,6 @@
};
cpu4-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -3158,8 +3149,6 @@
};
cpu5-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -3184,8 +3173,6 @@
};
cpu6-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -3210,8 +3197,6 @@
};
cpu7-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -3236,8 +3221,6 @@
};
cpu45-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -3262,8 +3245,6 @@
};
cpu67-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -3288,8 +3269,6 @@
};
cpu0123-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -3314,8 +3293,6 @@
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -3334,8 +3311,6 @@
};
display-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
@@ -3354,8 +3329,8 @@
};
gpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <250>;
+
thermal-sensors = <&tsens0 15>;
cooling-maps {
@@ -3367,13 +3342,13 @@
trips {
gpu_alert0: trip-point0 {
- temperature = <115000>;
- hysteresis = <5000>;
+ temperature = <85000>;
+ hysteresis = <1000>;
type = "passive";
};
trip-point1 {
- temperature = <125000>;
+ temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
diff --git a/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts b/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts
index 54da053..9d78bb3 100644
--- a/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts
+++ b/dts/upstream/src/arm64/qcom/sm6115p-lenovo-j606f.dts
@@ -359,6 +359,7 @@
};
&usb_dwc3 {
+ /delete-property/ usb-role-switch;
maximum-speed = "high-speed";
dr_mode = "peripheral";
diff --git a/dts/upstream/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts b/dts/upstream/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts
index 08046f8..dcd05f3 100644
--- a/dts/upstream/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts
+++ b/dts/upstream/src/arm64/qcom/sm6125-sony-xperia-seine-pdx201.dts
@@ -90,8 +90,6 @@
thermal-zones {
rf-pa0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 0>;
trips {
@@ -104,8 +102,6 @@
};
quiet-thermal {
- polling-delay-passive = <0>;
- polling-delay = <5000>;
thermal-sensors = <&pm6125_adc_tm 1>;
trips {
@@ -118,8 +114,6 @@
};
xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 2>;
trips {
@@ -132,8 +126,6 @@
};
rf-pa1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 3>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm6125-xiaomi-laurel-sprout.dts b/dts/upstream/src/arm64/qcom/sm6125-xiaomi-laurel-sprout.dts
index a49d3eb..994fb04 100644
--- a/dts/upstream/src/arm64/qcom/sm6125-xiaomi-laurel-sprout.dts
+++ b/dts/upstream/src/arm64/qcom/sm6125-xiaomi-laurel-sprout.dts
@@ -84,8 +84,6 @@
thermal-zones {
rf-pa0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 0>;
trips {
@@ -98,8 +96,6 @@
};
quiet-thermal {
- polling-delay-passive = <0>;
- polling-delay = <5000>;
thermal-sensors = <&pm6125_adc_tm 1>;
trips {
@@ -112,8 +108,6 @@
};
xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm6125_adc_tm 2>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm6125.dtsi b/dts/upstream/src/arm64/qcom/sm6125.dtsi
index 98ab083..777c380 100644
--- a/dts/upstream/src/arm64/qcom/sm6125.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6125.dtsi
@@ -1588,10 +1588,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 0xf08
- GIC_PPI 2 0xf08
- GIC_PPI 3 0xf08
- GIC_PPI 0 0xf08>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};
diff --git a/dts/upstream/src/arm64/qcom/sm6350-sony-xperia-lena-pdx213.dts b/dts/upstream/src/arm64/qcom/sm6350-sony-xperia-lena-pdx213.dts
index dddd6e4..bf23033 100644
--- a/dts/upstream/src/arm64/qcom/sm6350-sony-xperia-lena-pdx213.dts
+++ b/dts/upstream/src/arm64/qcom/sm6350-sony-xperia-lena-pdx213.dts
@@ -293,7 +293,7 @@
compatible = "samsung,s6sy761";
reg = <0x48>;
interrupt-parent = <&tlmm>;
- interrupts = <22 0x2008>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&pm6350_l11>;
avdd-supply = <&touch_en_vreg>;
@@ -375,6 +375,7 @@
};
&usb_1_dwc3 {
+ /delete-property/ usb-role-switch;
maximum-speed = "super-speed";
dr_mode = "peripheral";
};
diff --git a/dts/upstream/src/arm64/qcom/sm6350.dtsi b/dts/upstream/src/arm64/qcom/sm6350.dtsi
index 84ff20a..7986ddb 100644
--- a/dts/upstream/src/arm64/qcom/sm6350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6350.dtsi
@@ -1197,6 +1197,8 @@
"ref_aux",
"qref";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -1321,6 +1323,7 @@
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
+ qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@@ -1580,6 +1583,7 @@
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
+ qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
@@ -1713,10 +1717,39 @@
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
+ orientation-switch;
+
#clock-cells = <1>;
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
dc_noc: interconnect@9160000 {
@@ -1890,8 +1923,30 @@
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,parkmode-disable-ss-quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
+ usb-role-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
};
};
@@ -2831,9 +2886,6 @@
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 0>;
trips {
@@ -2846,9 +2898,6 @@
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 0>;
trips {
@@ -2861,9 +2910,6 @@
};
audio-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 2>;
trips {
@@ -2876,9 +2922,6 @@
};
camera-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 5>;
trips {
@@ -2891,9 +2934,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 1>;
trips {
@@ -2919,9 +2959,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 2>;
trips {
@@ -2947,9 +2984,6 @@
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 3>;
trips {
@@ -2975,9 +3009,6 @@
};
cpu3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 4>;
trips {
@@ -3003,9 +3034,6 @@
};
cpu4-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 5>;
trips {
@@ -3031,9 +3059,6 @@
};
cpu5-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 6>;
trips {
@@ -3059,9 +3084,6 @@
};
cpu6-left-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 9>;
trips {
@@ -3087,9 +3109,6 @@
};
cpu6-right-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 10>;
trips {
@@ -3115,9 +3134,6 @@
};
cpu7-left-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 11>;
trips {
@@ -3143,9 +3159,6 @@
};
cpu7-right-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 12>;
trips {
@@ -3171,9 +3184,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 7>;
trips {
@@ -3186,9 +3196,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 8>;
trips {
@@ -3201,9 +3208,6 @@
};
cwlan-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 1>;
trips {
@@ -3216,9 +3220,6 @@
};
ddr-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 3>;
trips {
@@ -3231,21 +3232,20 @@
};
gpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <250>;
thermal-sensors = <&tsens0 13>;
trips {
gpuss0_alert0: trip-point0 {
- temperature = <95000>;
+ temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpuss0-crit {
- temperature = <115000>;
- hysteresis = <0>;
+ temperature = <110000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -3259,21 +3259,20 @@
};
gpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <250>;
thermal-sensors = <&tsens0 14>;
trips {
gpuss1_alert0: trip-point0 {
- temperature = <95000>;
+ temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpuss1-crit {
- temperature = <115000>;
- hysteresis = <0>;
+ temperature = <110000>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -3287,9 +3286,6 @@
};
modem-core0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 6>;
trips {
@@ -3302,9 +3298,6 @@
};
modem-core1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 7>;
trips {
@@ -3317,9 +3310,6 @@
};
modem-scl-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 9>;
trips {
@@ -3332,9 +3322,6 @@
};
modem-vec-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 8>;
trips {
@@ -3347,9 +3334,6 @@
};
npu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 10>;
trips {
@@ -3362,9 +3346,6 @@
};
q6-hvx-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 4>;
trips {
@@ -3377,9 +3358,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 11>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts b/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
index cca2c2e..e04a3b8 100644
--- a/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
+++ b/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
@@ -142,7 +142,7 @@
compatible = "samsung,s6sy761";
reg = <0x48>;
interrupt-parent = <&tlmm>;
- interrupts = <22 0x2008>;
+ interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&pm6125_l13>;
avdd-supply = <&touch_avdd>;
diff --git a/dts/upstream/src/arm64/qcom/sm6375.dtsi b/dts/upstream/src/arm64/qcom/sm6375.dtsi
index f40509d..ddea681 100644
--- a/dts/upstream/src/arm64/qcom/sm6375.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6375.dtsi
@@ -1837,9 +1837,6 @@
thermal-zones {
mapss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 0>;
trips {
@@ -1864,9 +1861,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 1>;
trips {
@@ -1891,9 +1885,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 2>;
trips {
@@ -1918,9 +1909,6 @@
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 3>;
trips {
@@ -1945,9 +1933,6 @@
};
cpu3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 4>;
trips {
@@ -1972,9 +1957,6 @@
};
cpu4-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 5>;
trips {
@@ -1999,9 +1981,6 @@
};
cpu5-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 6>;
trips {
@@ -2026,9 +2005,6 @@
};
cluster0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 7>;
trips {
@@ -2053,9 +2029,6 @@
};
cluster1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 8>;
trips {
@@ -2080,9 +2053,6 @@
};
cpu6-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 9>;
trips {
@@ -2107,9 +2077,6 @@
};
cpu7-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 10>;
trips {
@@ -2134,9 +2101,6 @@
};
cpu-unk0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 11>;
trips {
@@ -2161,9 +2125,6 @@
};
cpu-unk1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 12>;
trips {
@@ -2188,9 +2149,6 @@
};
gpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 13>;
trips {
@@ -2215,9 +2173,6 @@
};
gpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens0 14>;
trips {
@@ -2242,9 +2197,6 @@
};
mapss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 0>;
trips {
@@ -2269,9 +2221,6 @@
};
cwlan-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 1>;
trips {
@@ -2296,9 +2245,6 @@
};
audio-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 2>;
trips {
@@ -2323,9 +2269,6 @@
};
ddr-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 3>;
trips {
@@ -2350,9 +2293,6 @@
};
q6hvx-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 4>;
trips {
@@ -2377,9 +2317,6 @@
};
camera-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 5>;
trips {
@@ -2404,9 +2341,6 @@
};
mdm-core0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 6>;
trips {
@@ -2431,9 +2365,6 @@
};
mdm-core1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 7>;
trips {
@@ -2458,9 +2389,6 @@
};
mdm-vec-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 8>;
trips {
@@ -2485,9 +2413,6 @@
};
msm-scl-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 9>;
trips {
@@ -2512,9 +2437,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
thermal-sensors = <&tsens1 10>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
index bc67e8c..2ee2561 100644
--- a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
+++ b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
@@ -19,6 +19,7 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/usb/pd.h>
#include "sm7225.dtsi"
#include "pm6150l.dtsi"
#include "pm6350.dtsi"
@@ -92,10 +93,22 @@
};
};
+ msm_therm_sensor: thermal-sensor-msm {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&pm6150l_adc ADC5_AMUX_THM2_100K_PU>;
+ io-channel-names = "sensor-channel";
+ };
+
+ rear_cam_sensor: thermal-sensor-rear-cam {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&pm6150l_adc ADC5_GPIO2_100K_PU>;
+ io-channel-names = "sensor-channel";
+ };
+
thermal-zones {
chg-skin-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 0>;
trips {
@@ -108,8 +121,6 @@
};
conn-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm7250b_adc_tm 1>;
trips {
@@ -120,6 +131,119 @@
};
};
};
+
+ pa0-thermal {
+ thermal-sensors = <&pm6150l_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa1-thermal {
+ thermal-sensors = <&pm6150l_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ quiet-thermal {
+ thermal-sensors = <&pm6150l_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-cam-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&rear_cam_sensor>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rfc-flash-thermal {
+ thermal-sensors = <&pm6150l_adc_tm 2>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&msm_therm_sensor>;
+
+ trips {
+ trip0 {
+ temperature = <45000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <55000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ xo-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
};
};
@@ -134,124 +258,145 @@
qcom,pmic-id = "a";
vreg_s1a: smps1 {
+ regulator-name = "vreg_s1a";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
};
vreg_s2a: smps2 {
+ regulator-name = "vreg_s2a";
regulator-min-microvolt = <1503000>;
regulator-max-microvolt = <2048000>;
};
vreg_l2a: ldo2 {
+ regulator-name = "vreg_l2a";
regulator-min-microvolt = <1503000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a: ldo3 {
+ regulator-name = "vreg_l3a";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
+ regulator-name = "vreg_l4a";
regulator-min-microvolt = <352000>;
regulator-max-microvolt = <801000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
+ regulator-name = "vreg_l5a";
regulator-min-microvolt = <1503000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
+ regulator-name = "vreg_l6a";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
+ regulator-name = "vreg_l7a";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
+ regulator-name = "vreg_l8a";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
+ regulator-name = "vreg_l9a";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3401000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a: ldo11 {
+ regulator-name = "vreg_l11a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12a: ldo12 {
+ regulator-name = "vreg_l12a";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a: ldo13 {
+ regulator-name = "vreg_l13a";
regulator-min-microvolt = <570000>;
regulator-max-microvolt = <650000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a: ldo14 {
+ regulator-name = "vreg_l14a";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a: ldo15 {
+ regulator-name = "vreg_l15a";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1305000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a: ldo16 {
+ regulator-name = "vreg_l16a";
regulator-min-microvolt = <830000>;
regulator-max-microvolt = <921000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a: ldo18 {
+ regulator-name = "vreg_l18a";
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1049000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19a: ldo19 {
+ regulator-name = "vreg_l19a";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1305000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a: ldo20 {
+ regulator-name = "vreg_l20a";
regulator-min-microvolt = <530000>;
regulator-max-microvolt = <801000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21a: ldo21 {
+ regulator-name = "vreg_l21a";
regulator-min-microvolt = <751000>;
regulator-max-microvolt = <825000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22a: ldo22 {
+ regulator-name = "vreg_l22a";
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1305000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -263,41 +408,48 @@
qcom,pmic-id = "e";
vreg_s8e: smps8 {
+ regulator-name = "vreg_s8e";
regulator-min-microvolt = <313000>;
regulator-max-microvolt = <1395000>;
};
vreg_l1e: ldo1 {
+ regulator-name = "vreg_l1e";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2e: ldo2 {
+ regulator-name = "vreg_l2e";
regulator-min-microvolt = <1170000>;
regulator-max-microvolt = <1305000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3e: ldo3 {
+ regulator-name = "vreg_l3e";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1299000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4e: ldo4 {
+ regulator-name = "vreg_l4e";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5e: ldo5 {
+ regulator-name = "vreg_l5e";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6e: ldo6 {
+ regulator-name = "vreg_l6e";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -307,18 +459,21 @@
};
vreg_l7e: ldo7 {
+ regulator-name = "vreg_l7e";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8e: ldo8 {
+ regulator-name = "vreg_l8e";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9e: ldo9 {
+ regulator-name = "vreg_l9e";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@@ -328,18 +483,21 @@
};
vreg_l10e: ldo10 {
+ regulator-name = "vreg_l10e";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3401000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11e: ldo11 {
+ regulator-name = "vreg_l11e";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3401000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob: bob {
+ regulator-name = "vreg_bob";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <5492000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
@@ -407,7 +565,79 @@
};
&i2c10 {
- /* PM8008 PMIC @ 8 and 9 */
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 59 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s8e>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_s2a>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_default>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2904000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3140000>;
+ };
+ };
+ };
+
/* PX8618 @ 26 */
/* SMB1395 PMIC @ 34 */
/* awinic,aw8695 @ 5a */
@@ -460,6 +690,91 @@
&mpss {
firmware-name = "qcom/sm7225/fairphone4/modem.mbn";
status = "okay";
+};
+
+&pm6150l_adc {
+ pinctrl-0 = <&pm6150l_adc_default>;
+ pinctrl-names = "default";
+
+ channel@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ label = "pa_therm1";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ label = "msm_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@4f {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ label = "pa_therm0";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@53 {
+ reg = <ADC5_GPIO2_100K_PU>;
+ label = "rear_cam_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@54 {
+ reg = <ADC5_GPIO3_100K_PU>;
+ label = "rear_cam_flash_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+
+ channel@55 {
+ reg = <ADC5_GPIO4_100K_PU>;
+ label = "quiet_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ };
+};
+
+&pm6150l_adc_tm {
+ status = "okay";
+
+ pa-therm1@0 {
+ reg = <0>;
+ io-channels = <&pm6150l_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,ratiometric;
+ };
+
+ pa-therm0@1 {
+ reg = <1>;
+ io-channels = <&pm6150l_adc ADC5_AMUX_THM3_100K_PU>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,ratiometric;
+ };
+
+ rear-cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pm6150l_adc ADC5_GPIO3_100K_PU>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,ratiometric;
+ };
+
+ quiet-therm@3 {
+ reg = <3>;
+ io-channels = <&pm6150l_adc ADC5_GPIO4_100K_PU>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,ratiometric;
+ };
};
&pm6150l_flash {
@@ -484,6 +799,14 @@
};
};
+&pm6150l_gpios {
+ pm6150l_adc_default: adc-default-state {
+ pins = "gpio6", "gpio7", "gpio10";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-high-impedance;
+ };
+};
+
&pm6150l_wled {
qcom,switching-freq = <800>;
qcom,current-limit-microamp = <20000>;
@@ -540,6 +863,64 @@
io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm7250b_typec {
+ vdd-pdphy-supply = <&vreg_l3a>;
+
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ power-role = "dual";
+ data-role = "dual";
+ self-powered;
+
+ /*
+ * Disable USB Power Delivery for now, seems to need extra work
+ * to support role switching while also letting the battery
+ * charge still - without charger driver
+ */
+ typec-power-opmode = "default";
+ pd-disable;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pm7250b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pm7250b_ss_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out>;
+ };
+ };
+ };
+ };
+};
+
+&pm7250b_vbus {
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <1500000>;
+ status = "okay";
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,hw-settle-time-us = <200>;
+ qcom,ratiometric;
};
};
@@ -673,6 +1054,22 @@
*/
bias-pull-up;
};
+
+ pm8008_default: pm8008-default-state {
+ int-pins {
+ pins = "gpio59";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ reset-n-pins {
+ pins = "gpio58";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
&uart1 {
@@ -726,7 +1123,11 @@
&usb_1_dwc3 {
maximum-speed = "super-speed";
- dr_mode = "peripheral";
+ dr_mode = "otg";
+};
+
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm7250b_hs_in>;
};
&usb_1_hsphy {
@@ -744,6 +1145,10 @@
status = "okay";
};
+&usb_1_qmpphy_out {
+ remote-endpoint = <&pm7250b_ss_in>;
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&vreg_l4a>;
vdd-1.8-xo-supply = <&vreg_l7a>;
diff --git a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
index 6cb6f50..bac08f0 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
@@ -470,7 +470,6 @@
&mdss_dp_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
&mdss_dsi0 {
@@ -556,7 +555,7 @@
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
+ pm8150b_hs_in: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -676,18 +675,10 @@
orientation-switch;
};
-&usb_1_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp_out>;
-};
-
&usb_1_qmpphy_out {
remote-endpoint = <&pm8150b_typec_mux_in>;
};
-&usb_1_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
@@ -708,11 +699,7 @@
};
&usb_1_dwc3_hs {
- remote-endpoint = <&pm8150b_role_switch_in>;
-};
-
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_2_dwc3 {
diff --git a/dts/upstream/src/arm64/qcom/sm8150.dtsi b/dts/upstream/src/arm64/qcom/sm8150.dtsi
index ff22e43..3e236ad 100644
--- a/dts/upstream/src/arm64/qcom/sm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
+#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/thermal/thermal.h>
@@ -3507,6 +3508,7 @@
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3514,6 +3516,7 @@
reg = <2>;
usb_1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp_out>;
};
};
};
@@ -3672,6 +3675,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
@@ -3735,6 +3739,19 @@
};
};
+ videocc: clock-controller@ab00000 {
+ compatible = "qcom,sm8150-videocc";
+ reg = <0 0x0ab00000 0 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bi_tcxo";
+ power-domains = <&rpmhpd SM8150_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
camnoc_virt: interconnect@ac00000 {
compatible = "qcom,sm8150-camnoc-virt";
reg = <0 0x0ac00000 0 0x1000>;
@@ -3894,6 +3911,7 @@
reg = <1>;
mdss_dp_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
};
};
@@ -4577,7 +4595,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -4621,7 +4638,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -4665,7 +4681,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -4709,7 +4724,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -4753,7 +4767,6 @@
cpu4-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -4797,7 +4810,6 @@
cpu5-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -4841,7 +4853,6 @@
cpu6-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -4885,7 +4896,6 @@
cpu7-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -4929,7 +4939,6 @@
cpu4-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -4973,7 +4982,6 @@
cpu5-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -5017,7 +5025,6 @@
cpu6-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
@@ -5061,7 +5068,6 @@
cpu7-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
@@ -5105,7 +5111,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
@@ -5120,7 +5125,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -5140,7 +5144,6 @@
cluster1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -5160,7 +5163,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
@@ -5173,16 +5175,27 @@
trips {
gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
@@ -5197,7 +5210,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -5212,7 +5224,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -5227,7 +5238,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -5242,7 +5252,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -5257,7 +5266,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -5272,7 +5280,6 @@
compute-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -5287,7 +5294,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -5302,7 +5308,6 @@
npu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
@@ -5317,7 +5322,6 @@
modem-vec-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 9>;
@@ -5332,7 +5336,6 @@
modem-scl-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 10>;
@@ -5347,7 +5350,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 11>;
@@ -5360,10 +5362,22 @@
trips {
gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
index 7ef9903..21b2ca1 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
@@ -53,8 +53,6 @@
thermal-zones {
camera-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 0>;
trips {
@@ -67,8 +65,6 @@
};
conn-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150b_adc_tm 0>;
trips {
@@ -81,8 +77,6 @@
};
mmw-pa1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 2>;
trips {
@@ -95,8 +89,6 @@
};
mmw-pa2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 2>;
trips {
@@ -109,8 +101,6 @@
};
skin-msm-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>;
trips {
@@ -123,8 +113,6 @@
};
skin-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
@@ -137,8 +125,6 @@
};
xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
index e07d031..f6870d3 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
@@ -520,7 +520,7 @@
compatible = "samsung,s6sy761";
reg = <0x48>;
interrupt-parent = <&tlmm>;
- interrupts = <39 0x2008>;
+ interrupts = <39 IRQ_TYPE_LEVEL_LOW>;
/* It's "vddio" downstream but it works anyway! */
vdd-supply = <&vreg_l1c_1p8>;
avdd-supply = <&vreg_l10c_3p3>;
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
index 41f1174..3596dd3 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -659,8 +659,8 @@
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
};
@@ -725,8 +725,8 @@
status = "okay";
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&ufs_mem_hc {
diff --git a/dts/upstream/src/arm64/qcom/sm8250.dtsi b/dts/upstream/src/arm64/qcom/sm8250.dtsi
index 8ccade6..9d6c97d 100644
--- a/dts/upstream/src/arm64/qcom/sm8250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250.dtsi
@@ -2204,7 +2204,7 @@
status = "disabled";
- pcie@0 {
+ pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2580,6 +2580,8 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
#phy-cells = <0>;
status = "disabled";
@@ -3936,6 +3938,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -3947,6 +3951,10 @@
port@1 {
reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss_out>;
+ };
};
port@2 {
@@ -4225,8 +4233,24 @@
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_1_role_switch_out: endpoint {};
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
};
};
};
@@ -6275,7 +6299,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -6319,7 +6342,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -6363,7 +6385,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -6407,7 +6428,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -6451,7 +6471,6 @@
cpu4-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -6495,7 +6514,6 @@
cpu5-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -6539,7 +6557,6 @@
cpu6-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -6583,7 +6600,6 @@
cpu7-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -6627,7 +6643,6 @@
cpu4-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -6671,7 +6686,6 @@
cpu5-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -6715,7 +6729,6 @@
cpu6-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
@@ -6759,7 +6772,6 @@
cpu7-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
@@ -6803,7 +6815,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
@@ -6818,7 +6829,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -6838,7 +6848,6 @@
cluster1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -6858,7 +6867,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
@@ -6871,16 +6879,27 @@
trips {
gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
@@ -6895,7 +6914,6 @@
wlan-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -6910,7 +6928,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -6925,7 +6942,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -6940,7 +6956,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -6955,7 +6970,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -6970,7 +6984,6 @@
compute-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -6985,7 +6998,6 @@
npu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -7000,7 +7012,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
@@ -7013,10 +7024,22 @@
trips {
gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
index 4c25ab2..895adce 100644
--- a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
@@ -486,17 +486,10 @@
&mdss_dp {
status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
+};
- mdss_dp0_out: endpoint {
- data-lanes = <0 1>;
- remote-endpoint = <&usb_1_qmpphy_dp_in>;
- };
- };
- };
+&mdss_dp_out {
+ data-lanes = <0 1>;
};
&mpss {
@@ -864,10 +857,6 @@
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
status = "okay";
@@ -881,22 +870,12 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p88>;
-
- orientation-switch;
-};
-
-&usb_1_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
};
&usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_1_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&usb_2 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sm8350.dtsi b/dts/upstream/src/arm64/qcom/sm8350.dtsi
index f7c4700..38ee085 100644
--- a/dts/upstream/src/arm64/qcom/sm8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8350.dtsi
@@ -301,11 +301,21 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-x1 {
+ compatible = "arm,cortex-x1-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1779,6 +1789,8 @@
"ref_aux",
"qref";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -2256,6 +2268,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
@@ -2273,6 +2287,7 @@
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -2280,6 +2295,7 @@
reg = <2>;
usb_1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp_out>;
};
};
};
@@ -2405,6 +2421,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
@@ -2626,6 +2643,14 @@
remote-endpoint = <&dpu_intf0_out>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_dp_in>;
+ };
+ };
};
dp_opp_table: opp-table {
@@ -3665,7 +3690,6 @@
thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -3709,7 +3733,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -3753,7 +3776,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -3797,7 +3819,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
@@ -3841,7 +3862,6 @@
cpu4-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -3885,7 +3905,6 @@
cpu5-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -3929,7 +3948,6 @@
cpu6-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
@@ -3973,7 +3991,6 @@
cpu7-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -4017,7 +4034,6 @@
cpu4-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
@@ -4061,7 +4077,6 @@
cpu5-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -4105,7 +4120,6 @@
cpu6-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
@@ -4149,7 +4163,6 @@
cpu7-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
@@ -4193,7 +4206,6 @@
aoss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
@@ -4208,7 +4220,6 @@
cluster0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -4228,7 +4239,6 @@
cluster1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
@@ -4248,7 +4258,6 @@
aoss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
@@ -4263,7 +4272,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -4276,16 +4284,27 @@
trips {
gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -4298,16 +4317,27 @@
trips {
gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
hysteresis = <1000>;
type = "hot";
};
+
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
};
};
nspss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -4322,7 +4352,6 @@
nspss2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
@@ -4337,7 +4366,6 @@
nspss3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
@@ -4352,7 +4380,6 @@
video-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -4367,7 +4394,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -4382,7 +4408,6 @@
modem1-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
@@ -4397,7 +4422,6 @@
modem2-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 9>;
@@ -4412,7 +4436,6 @@
modem3-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 10>;
@@ -4427,7 +4450,6 @@
modem4-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 11>;
@@ -4442,7 +4464,6 @@
camera-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 12>;
@@ -4457,7 +4478,6 @@
cam-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 13>;
diff --git a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
index 3be46b5..a754b8f 100644
--- a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
@@ -138,7 +138,7 @@
thermal-zones {
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 2>;
trips {
@@ -152,7 +152,7 @@
rear-tof-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 5>;
trips {
@@ -166,7 +166,7 @@
skin-msm-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 1>;
trips {
@@ -180,7 +180,7 @@
therm1-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 3>;
trips {
@@ -194,7 +194,7 @@
therm2-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 6>;
trips {
@@ -208,7 +208,7 @@
usb-conn-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 7>;
trips {
@@ -222,7 +222,7 @@
wide-rfc-thermal {
polling-delay-passive = <250>;
- polling-delay = <0>;
+
thermal-sensors = <&pmk8350_adc_tm 4>;
trips {
@@ -235,8 +235,6 @@
};
xo-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm 0>;
trips {
@@ -674,17 +672,10 @@
&mdss_dp0 {
status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
+};
- mdss_dp0_out: endpoint {
- data-lanes = <0 1>;
- remote-endpoint = <&usb_1_qmpphy_dp_in>;
- };
- };
- };
+&mdss_dp0_out {
+ data-lanes = <0 1>;
};
&pcie0 {
@@ -1114,10 +1105,6 @@
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
status = "okay";
@@ -1131,22 +1118,12 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p91>;
-
- orientation-switch;
};
-&usb_1_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_1_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/qcom/sm8450-sony-xperia-nagara.dtsi b/dts/upstream/src/arm64/qcom/sm8450-sony-xperia-nagara.dtsi
index 8b29fcf..17dbb67 100644
--- a/dts/upstream/src/arm64/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -488,7 +488,7 @@
compatible = "samsung,s6sy761";
reg = <0x48>;
interrupt-parent = <&tlmm>;
- interrupts = <21 0x2008>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&pm8350c_l2>;
avdd-supply = <&pm8350c_l3>;
diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi
index 616461f..9bafb3b 100644
--- a/dts/upstream/src/arm64/qcom/sm8450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi
@@ -754,8 +754,8 @@
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1803,6 +1803,12 @@
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie0_phy>,
@@ -1845,8 +1851,35 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
+ operating-points-v2 = <&pcie0_opp_table>;
+
status = "disabled";
+ pcie0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+ };
+
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -1932,6 +1965,12 @@
<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&pcie1_phy>,
@@ -1972,8 +2011,56 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
+ operating-points-v2 = <&pcie1_opp_table>;
+
status = "disabled";
+ pcie1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <250000 1>;
+ };
+
+ /* GEN 1 x2 and GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <500000 1>;
+ };
+
+ /* GEN 2 x2 */
+ opp-10000000 {
+ opp-hz = /bits/ 64 <10000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ opp-peak-kBps = <1000000 1>;
+ };
+
+ /* GEN 3 x1 */
+ opp-8000000 {
+ opp-hz = /bits/ 64 <8000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <984500 1>;
+ };
+
+ /* GEN 3 x2 and GEN 4 x1 */
+ opp-16000000 {
+ opp-hz = /bits/ 64 <16000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <1969000 1>;
+ };
+
+ /* GEN 4 x2 */
+ opp-32000000 {
+ opp-hz = /bits/ 64 <32000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <3938000 1>;
+ };
+ };
+
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -2001,7 +2088,7 @@
"pipe";
clock-output-names = "pcie_1_pipe_clk";
- #clock-cells = <0>;
+ #clock-cells = <1>;
#phy-cells = <0>;
@@ -2304,6 +2391,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
@@ -2321,6 +2410,7 @@
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -2328,6 +2418,7 @@
reg = <2>;
usb_1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -3119,6 +3210,14 @@
remote-endpoint = <&dpu_intf0_out>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_dp_in>;
+ };
+ };
};
dp_opp_table: opp-table {
@@ -4362,9 +4461,10 @@
compatible = "qcom,sm8450-llcc";
reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
<0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
- <0 0x19a00000 0 0x80000>;
+ <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
- "llcc3_base", "llcc_broadcast_base";
+ "llcc3_base", "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -4429,6 +4529,8 @@
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_0_CLKREF_EN>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
@@ -4584,6 +4686,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
@@ -4610,8 +4713,6 @@
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -4630,8 +4731,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -4650,8 +4749,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -4670,8 +4767,6 @@
};
cpuss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -4690,8 +4785,6 @@
};
cpuss4-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -4710,8 +4803,6 @@
};
cpu4-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -4736,8 +4827,6 @@
};
cpu4-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -4762,8 +4851,6 @@
};
cpu5-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -4788,8 +4875,6 @@
};
cpu5-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -4814,8 +4899,6 @@
};
cpu6-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -4840,8 +4923,6 @@
};
cpu6-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -4866,8 +4947,6 @@
};
cpu7-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -4892,8 +4971,6 @@
};
cpu7-middle-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -4918,8 +4995,6 @@
};
cpu7-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -4945,7 +5020,7 @@
gpu-top-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens0 14>;
cooling-maps {
@@ -4956,35 +5031,29 @@
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu_top_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-cfg {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu_top_alert0: trip-point0 {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpu-bottom-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens0 15>;
cooling-maps {
@@ -4995,35 +5064,27 @@
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu_bottom_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-cfg {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu_bottom_alert0: trip-point0 {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
@@ -5042,8 +5103,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
@@ -5068,8 +5127,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
@@ -5094,8 +5151,6 @@
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
@@ -5120,8 +5175,6 @@
};
cpu3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
trips {
@@ -5147,7 +5200,7 @@
cdsp0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 5>;
trips {
@@ -5179,7 +5232,7 @@
cdsp1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 6>;
trips {
@@ -5211,7 +5264,7 @@
cdsp2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 7>;
trips {
@@ -5242,8 +5295,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
trips {
@@ -5263,7 +5314,7 @@
mem-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 9>;
trips {
@@ -5288,8 +5339,6 @@
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 10>;
trips {
@@ -5320,8 +5369,6 @@
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 11>;
trips {
@@ -5352,8 +5399,6 @@
};
modem2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 12>;
trips {
@@ -5384,8 +5429,6 @@
};
modem3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 13>;
trips {
@@ -5416,8 +5459,6 @@
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 14>;
trips {
@@ -5436,8 +5477,6 @@
};
camera1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 15>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
index 12d60a0..2e12219 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
@@ -940,7 +940,6 @@
};
&mdss_dp0_out {
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
data-lanes = <0 1>;
};
@@ -979,10 +978,6 @@
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
@@ -1111,6 +1106,7 @@
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
+ qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker South */
@@ -1128,6 +1124,7 @@
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
+ qcom,port-mapping = <4 5 6 7 11 13>;
};
};
@@ -1258,19 +1255,10 @@
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1284,23 +1272,13 @@
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
index 3d4ad5a..ab447fc 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
@@ -736,13 +736,8 @@
&mdss_dp0_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -847,6 +842,7 @@
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3g_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845 */
@@ -860,6 +856,7 @@
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3g_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
};
};
@@ -951,19 +948,10 @@
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -977,23 +965,13 @@
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p91>;
- orientation-switch;
-
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
index 92f0150..774bdfc 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
@@ -214,6 +214,68 @@
regulator-always-on;
regulator-boot-on;
};
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>, <&pmk8550_sleep_clk>;
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ /*
+ * TODO Add bt-enable-gpios once the Bluetooth driver is
+ * converted to using the power sequencer.
+ */
+
+ vdd-supply = <&vreg_s5g_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p85>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
};
&apps_rsc {
@@ -720,17 +782,6 @@
status = "okay";
};
-&gcc {
- clocks = <&bi_tcxo_div2>, <&sleep_clk>,
- <&pcie0_phy>,
- <&pcie1_phy>,
- <0>,
- <&ufs_mem_phy 0>,
- <&ufs_mem_phy 1>,
- <&ufs_mem_phy 2>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-};
-
&gpi_dma1 {
status = "okay";
};
@@ -807,11 +858,6 @@
&mdss_dp0_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
-};
-
-&pcie_1_phy_aux_clk {
- status = "disabled";
};
&pcie0 {
@@ -824,6 +870,23 @@
status = "okay";
};
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -907,8 +970,15 @@
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
};
&qupv3_id_0 {
@@ -955,6 +1025,7 @@
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3g_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker South */
@@ -968,6 +1039,7 @@
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3g_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
};
};
@@ -1084,6 +1156,13 @@
bias-disable;
output-low;
};
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
};
&uart7 {
@@ -1135,19 +1214,10 @@
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1e_0p88>;
vdda12-supply = <&vreg_l3e_1p2>;
@@ -1161,23 +1231,13 @@
vdda-phy-supply = <&vreg_l3e_1p2>;
vdda-pll-supply = <&vreg_l3f_0p88>;
- orientation-switch;
-
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&redriver_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
new file mode 100644
index 0000000..3d351e9
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/delete-node/ &adspslpi_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &mpss_dsm_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &rmtfs_mem;
+
+/ {
+ model = "Samsung Galaxy Z Fold5";
+ compatible = "samsung,q5q", "qcom,sm8550";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@b8000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ width = <2176>;
+ height = <1812>;
+ stride = <(2176 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ adspslpi_mem: adspslpi@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x59b4000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9c900000 {
+ reg = <0 0x9c900000 0 0x2000000>;
+ no-map;
+ };
+
+ mpss_dsm_mem: mpss-dsm@d4d00000 {
+ reg = <0x0 0xd4d00000 0x0 0x3300000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8b400000 {
+ reg = <0x0 0x8b400000 0x0 0xfc00000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs-region@d4a80000 {
+ reg = <0x0 0xd4a80000 0x0 0x280000>;
+ no-map;
+ };
+
+ /*
+ * The bootloader will only keep display hardware enabled
+ * if this memory region is named exactly 'splash_region'
+ */
+ splash_region@b8000000 {
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ no-map;
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_l3c_0p91: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vreg_s4e_0p9: smps4 {
+ regulator-name = "vreg_s4e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p1: smps5 {
+ regulator-name = "vreg_s5e_1p1";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p91: ldo3 {
+ regulator-name = "vreg_l3f_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vreg_s1g_1p2: smps1 {
+ regulator-name = "vreg_s1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p8: smps2 {
+ regulator-name = "vreg_s2g_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p7: smps3 {
+ regulator-name = "vreg_s3g_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p3: smps4 {
+ regulator-name = "vreg_s4g_1p3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p8: smps5 {
+ regulator-name = "vreg_s5g_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p8: smps6 {
+ regulator-name = "vreg_s6g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ status = "disabled";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/adsp.mdt",
+ "qcom/sm8550/adsp_dtb.mdt";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/cdsp.mdt",
+ "qcom/sm8550/cdsp_dtb.mdt";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8550/modem.mdt",
+ "qcom/sm8550/modem_dtb.mdt";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, <50 2>;
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 85e0d3d..85d487e 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -737,19 +737,10 @@
status = "okay";
};
-&usb_1_dwc3 {
- dr_mode = "otg";
- usb-role-switch;
-};
-
&usb_1_dwc3_hs {
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&pm8550vs_2_l1>;
vdda12-supply = <&pm8550vs_2_l3>;
@@ -761,7 +752,6 @@
&usb_dp_qmpphy {
vdda-phy-supply = <&pm8550vs_2_l3>;
vdda-pll-supply = <&pm8550ve_l3>;
- orientation-switch;
status = "okay";
};
@@ -770,10 +760,6 @@
remote-endpoint = <&pmic_glink_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8550.dtsi b/dts/upstream/src/arm64/qcom/sm8550.dtsi
index bc5aeb0..4c9820a 100644
--- a/dts/upstream/src/arm64/qcom/sm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8550.dtsi
@@ -58,11 +58,6 @@
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -357,8 +352,23 @@
reg = <0 0xa0000000 0 0>;
};
+ pmu-a510 {
+ compatible = "arm,cortex-a510-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-a710 {
+ compatible = "arm,cortex-a710-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-a715 {
+ compatible = "arm,cortex-a715-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-x3 {
+ compatible = "arm,cortex-x3-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
@@ -776,8 +786,8 @@
#power-domain-cells = <1>;
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -1774,7 +1784,7 @@
status = "disabled";
- pcie@0 {
+ pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1928,7 +1938,7 @@
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
+ #clock-cells = <1>;
clock-output-names = "pcie1_pipe_clk";
#phy-cells = <0>;
@@ -2910,6 +2920,7 @@
port@1 {
reg = <1>;
mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
};
};
@@ -3169,6 +3180,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
@@ -3186,6 +3199,7 @@
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3193,6 +3207,7 @@
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -3264,6 +3279,7 @@
snps,has-lpm-erratum;
tx-fifo-resize;
dma-coherent;
+ usb-role-switch;
ports {
#address-cells = <1>;
@@ -3280,6 +3296,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
@@ -4295,12 +4312,14 @@
<0 0x25200000 0 0x200000>,
<0 0x25400000 0 0x200000>,
<0 0x25600000 0 0x200000>,
- <0 0x25800000 0 0x200000>;
+ <0 0x25800000 0 0x200000>,
+ <0 0x25a00000 0 0x200000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
- "llcc_broadcast_base";
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -4571,8 +4590,6 @@
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -4591,8 +4608,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -4611,8 +4626,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -4631,8 +4644,6 @@
};
cpuss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -4651,8 +4662,6 @@
};
cpuss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -4671,8 +4680,6 @@
};
cpu3-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -4697,8 +4704,6 @@
};
cpu3-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -4723,8 +4728,6 @@
};
cpu4-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -4749,8 +4752,6 @@
};
cpu4-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -4775,8 +4776,6 @@
};
cpu5-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -4801,8 +4800,6 @@
};
cpu5-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -4827,8 +4824,6 @@
};
cpu6-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -4853,8 +4848,6 @@
};
cpu6-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -4879,8 +4872,6 @@
};
cpu7-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -4905,8 +4896,6 @@
};
cpu7-middle-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
@@ -4931,8 +4920,6 @@
};
cpu7-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 15>;
trips {
@@ -4957,8 +4944,6 @@
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
@@ -4977,8 +4962,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
@@ -5003,8 +4986,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
@@ -5029,8 +5010,6 @@
};
cpu2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
@@ -5056,7 +5035,7 @@
cdsp0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
trips {
@@ -5088,7 +5067,7 @@
cdsp1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
trips {
@@ -5120,7 +5099,7 @@
cdsp2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
trips {
@@ -5152,7 +5131,7 @@
cdsp3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
trips {
@@ -5183,8 +5162,6 @@
};
video-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
trips {
@@ -5204,7 +5181,7 @@
mem-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 9>;
trips {
@@ -5229,8 +5206,6 @@
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 10>;
trips {
@@ -5261,8 +5236,6 @@
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 11>;
trips {
@@ -5293,8 +5266,6 @@
};
modem2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 12>;
trips {
@@ -5325,8 +5296,6 @@
};
modem3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 13>;
trips {
@@ -5357,8 +5326,6 @@
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 14>;
trips {
@@ -5377,8 +5344,6 @@
};
camera1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 15>;
trips {
@@ -5397,8 +5362,6 @@
};
aoss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 0>;
trips {
@@ -5418,312 +5381,264 @@
gpuss-0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 1>;
cooling-maps {
map0 {
- trip = <&gpu0_junction_config>;
+ trip = <&gpu0_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu0_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 2>;
cooling-maps {
map0 {
- trip = <&gpu1_junction_config>;
+ trip = <&gpu1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu1_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 3>;
cooling-maps {
map0 {
- trip = <&gpu2_junction_config>;
+ trip = <&gpu2_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu2_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu2_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
cooling-maps {
map0 {
- trip = <&gpu3_junction_config>;
+ trip = <&gpu3_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu3_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu3_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-4-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
cooling-maps {
map0 {
- trip = <&gpu4_junction_config>;
+ trip = <&gpu4_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu4_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu4_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-5-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
cooling-maps {
map0 {
- trip = <&gpu5_junction_config>;
+ trip = <&gpu5_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu5_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
- };
-
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
+ type = "hot";
};
- gpu5_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-6-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
cooling-maps {
map0 {
- trip = <&gpu6_junction_config>;
+ trip = <&gpu6_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu6_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu6_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
gpuss-7-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
cooling-maps {
map0 {
- trip = <&gpu7_junction_config>;
+ trip = <&gpu7_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
- thermal-engine-config {
- temperature = <125000>;
+ gpu7_alert0: trip-point0 {
+ temperature = <85000>;
hysteresis = <1000>;
type = "passive";
};
- thermal-hal-config {
- temperature = <125000>;
+ trip-point1 {
+ temperature = <90000>;
hysteresis = <1000>;
- type = "passive";
+ type = "hot";
};
- reset-mon-config {
- temperature = <115000>;
- hysteresis = <5000>;
- type = "passive";
- };
-
- gpu7_junction_config: junction-config {
- temperature = <95000>;
- hysteresis = <5000>;
- type = "passive";
+ trip-point2 {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
diff --git a/dts/upstream/src/arm64/qcom/sm8650-hdk-display-card.dtso b/dts/upstream/src/arm64/qcom/sm8650-hdk-display-card.dtso
new file mode 100644
index 0000000..cb10253
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8650-hdk-display-card.dtso
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/*
+ * Display Card kit overlay
+ * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */
+
+&i2c6 {
+ status = "disabled";
+};
+
+<9611_1v2 {
+ status = "disabled";
+};
+
+<9611_3v3 {
+ status = "disabled";
+};
+
+&vreg_bob_3v3 {
+ status = "disabled";
+};
+
+<9611_codec {
+ status = "disabled";
+};
+
+&mdss_dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&vreg_l12b_1p8>;
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+
+ pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>;
+ pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ remote-endpoint = <&panel0_in>;
+ };
+ };
+ };
+};
+
+&spi4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <162 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l14b_3p2>;
+
+ spi-max-frequency = <1000000>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+
+ pinctrl-0 = <&ts_irq>, <&ts_reset>;
+ pinctrl-names = "default";
+ };
+};
+
+&tlmm {
+ disp0_reset_n_active: disp0-reset-n-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ disp0_reset_n_suspend: disp0-reset-n-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync: mdp-vsync-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ ts_irq: ts-irq-state {
+ pins = "gpio161";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-disable;
+ };
+
+ ts_reset: ts-reset-state {
+ pins = "gpio162";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
new file mode 100644
index 0000000..591e6ab
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
@@ -0,0 +1,1355 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8650.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8650 HDK";
+ compatible = "qcom,sm8650-hdk", "qcom,sm8650";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart15;
+ serial1 = &uart14;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ panic-indicator;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&pm8550b_gpios 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8650-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&wcd_usbss_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ lt9611_1v2: regulator-lt9611-1v2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vph_pwr>;
+ gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ lt9611_3v3: regulator-lt9611-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "LT9611_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_bob_3v3>;
+ gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>;
+
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard";
+ model = "SM8650-HDK";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC5", "MIC BIAS4",
+ "TX SWR_INPUT0", "ADC1_OUTPUT",
+ "TX SWR_INPUT1", "ADC2_OUTPUT",
+ "TX SWR_INPUT3", "ADC4_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_bob_3v3: regulator-vreg-bob-3v3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_BOB_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ wcd939x: audio-codec {
+ compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>;
+
+ wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+ /*
+ * TODO Add bt-enable-gpios once the Bluetooth driver is
+ * converted to using the power sequencer.
+ */
+
+ vdd-supply = <&vreg_s4i_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddio1p2-supply = <&vreg_l3c_1p2>;
+ vddaon-supply = <&vreg_s2c_0p8>;
+ vdddig-supply = <&vreg_s3c_0p9>;
+ vddrfa1p2-supply = <&vreg_s1c_1p2>;
+ vddrfa1p8-supply = <&vreg_s6c_1p8>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s1c_1p2>;
+ vdd-l12-supply = <&vreg_s6c_1p8>;
+ vdd-l15-supply = <&vreg_s6c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1c_1p2>;
+ vdd-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "c";
+
+ vreg_s1c_1p2: smps1 {
+ regulator-name = "vreg_s1c_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1348000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2c_0p8: smps2 {
+ regulator-name = "vreg_s2c_0p8";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3c_0p9: smps3 {
+ regulator-name = "vreg_s3c_0p9";
+ regulator-min-microvolt = <976000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4c_1p2: smps4 {
+ regulator-name = "vreg_s4c_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1280000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5c_0p7: smps5 {
+ regulator-name = "vreg_s5c_0p7";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6c_1p8: smps6 {
+ regulator-name = "vreg_s6c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-name = "vreg_l3c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "e";
+
+ vreg_l3e_0p9: ldo3 {
+ regulator-name = "vreg_l3e_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "g";
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_0p91: ldo3 {
+ regulator-name = "vreg_l3g_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l2-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s4i_0p85: smps4 {
+ regulator-name = "vreg_s4i_0p85";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_0p88: ldo1 {
+ regulator-name = "vreg_l1i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_0p88: ldo2 {
+ regulator-name = "vreg_l2i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_1p2: ldo3 {
+ regulator-name = "vreg_l3i_0p91";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6c_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-l4-supply = <&vreg_s6c_1p8>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p056: ldo2 {
+ regulator-name = "vreg_l2n_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ wcd_usbss: typec-mux@e {
+ compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss";
+ reg = <0xe>;
+
+ vdd-supply = <&vreg_l15b_1p8>;
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>;
+
+ mode-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ wcd_usbss_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_connector_out>;
+ };
+ };
+ };
+ };
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sm8650/ipa_fws.mbn";
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8650/gen70900_zap.mbn";
+ };
+};
+
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&mdss_dp0_out {
+ data-lanes = <0 1>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1i_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3e_0p9>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+ vdda-qref-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ output-disable;
+ power-source = <1>; /* 1.8 V */
+ };
+
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+/* The RGB signals are routed to 3 separate LEDs on the HDK8650 */
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_rtc {
+ status = "okay";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qup_i2c3_data_clk {
+ /* Use internal I2C pull-up */
+ bias-pull-up = <2200>;
+};
+
+&qupv3_id_0 {
+ iommus = <&apps_smmu 0xa3 0x3>;
+
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8650/adsp.mbn",
+ "qcom/sm8650/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8650/cdsp.mbn",
+ "qcom/sm8650/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8650/modem.mbn",
+ "qcom/sm8650/modem_dtb.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker North */
+ north_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Speaker South */
+ south_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9395 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010e00";
+ reg = <0 4>;
+
+ /*
+ * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R)
+ * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH)
+ * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R)
+ * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
+ * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R)
+ * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5 9>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9395 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010e00";
+ reg = <0 3>;
+
+ /*
+ * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3)
+ * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7)
+ * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11)
+ */
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ /* Reserved I/Os for NFC */
+ gpio-reserved-ranges = <32 8>, <74 1>;
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio18";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio85";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio28";
+ function = "gpio";
+ output-high;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio77";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddio-supply = <&vreg_l3c_1p2>;
+ vddaon-supply = <&vreg_l15b_1p8>;
+ vdddig-supply = <&vreg_s3c_0p9>;
+ vddrfa0p8-supply = <&vreg_s3c_0p9>;
+ vddrfa1p2-supply = <&vreg_s1c_1p2>;
+ vddrfa1p9-supply = <&vreg_s6c_1p8>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1c_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+/*
+ * DPAUX -> WCD9395 -> USB_SBU -> USB-C
+ * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C
+ * USB SS -> USB-C
+ */
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1i_0p88>;
+ vdda12-supply = <&vreg_l3i_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3i_1p2>;
+ vdda-pll-supply = <&vreg_l3g_0p91>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
index d04ceaa..c63822f 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
@@ -59,7 +59,7 @@
reg = <1>;
pmic_glink_ss_in: endpoint {
- remote-endpoint = <&usb_1_dwc3_ss>;
+ remote-endpoint = <&usb_dp_qmpphy_out>;
};
};
};
@@ -641,10 +641,6 @@
status = "okay";
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -755,6 +751,16 @@
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker Right */
@@ -768,6 +774,16 @@
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <4 5 6 7 11 13>;
};
};
@@ -853,10 +869,6 @@
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&pmic_glink_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1i_0p88>;
vdda12-supply = <&vreg_l3i_1p2>;
@@ -873,6 +885,10 @@
status = "okay";
};
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
index 4e94f7f..b0d7927 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
@@ -203,6 +203,71 @@
};
};
};
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>;
+
+ wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+ /*
+ * TODO Add bt-enable-gpios once the Bluetooth driver is
+ * converted to using the power sequencer.
+ */
+
+ vdd-supply = <&vreg_s4i_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddio1p2-supply = <&vreg_l3c_1p2>;
+ vddaon-supply = <&vreg_s2c_0p8>;
+ vdddig-supply = <&vreg_s3c_0p9>;
+ vddrfa1p2-supply = <&vreg_s1c_1p2>;
+ vddrfa1p8-supply = <&vreg_s6c_1p8>;
+
+ clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
};
&apps_rsc {
@@ -832,13 +897,8 @@
&mdss_dp0_out {
data-lanes = <0 1>;
- remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
-&pcie_1_phy_aux_clk {
- clock-frequency = <1000>;
-};
-
&pcie0 {
wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
@@ -849,6 +909,23 @@
status = "okay";
};
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1i_0p88>;
vdda-pll-supply = <&vreg_l3i_1p2>;
@@ -1012,6 +1089,16 @@
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Speaker Right */
@@ -1025,6 +1112,16 @@
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b_1p8>;
vdd-io-supply = <&vreg_l3c_1p2>;
+
+ /*
+ * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R)
+ * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP)
+ * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST)
+ * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR)
+ * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI)
+ * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS)
+ */
+ qcom,port-mapping = <4 5 6 7 11 13>;
};
};
@@ -1143,6 +1240,13 @@
bias-disable;
output-low;
};
+
+ wlan_en: wlan-en-state {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
};
&uart14 {
@@ -1211,10 +1315,6 @@
remote-endpoint = <&pmic_glink_hs_in>;
};
-&usb_1_dwc3_ss {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
-};
-
&usb_1_hsphy {
vdd-supply = <&vreg_l1i_0p88>;
vdda12-supply = <&vreg_l3i_1p2>;
@@ -1228,23 +1328,13 @@
vdda-phy-supply = <&vreg_l3i_1p2>;
vdda-pll-supply = <&vreg_l3g_0p91>;
- orientation-switch;
-
status = "okay";
};
-&usb_dp_qmpphy_dp_in {
- remote-endpoint = <&mdss_dp0_out>;
-};
-
&usb_dp_qmpphy_out {
remote-endpoint = <&redriver_ss_in>;
};
-&usb_dp_qmpphy_usb_ss_in {
- remote-endpoint = <&usb_1_dwc3_ss>;
-};
-
&xo_board {
clock-frequency = <76800000>;
};
diff --git a/dts/upstream/src/arm64/qcom/sm8650.dtsi b/dts/upstream/src/arm64/qcom/sm8650.dtsi
index 62a6e77..9d9bbb9 100644
--- a/dts/upstream/src/arm64/qcom/sm8650.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8650.dtsi
@@ -4,10 +4,12 @@
*/
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-camcc.h>
#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
@@ -60,11 +62,6 @@
clock-mult = <1>;
clock-div = <2>;
};
-
- pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- };
};
cpus {
@@ -371,6 +368,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8650", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
@@ -394,8 +392,18 @@
reg = <0 0xa0000000 0 0>;
};
+ pmu-a520 {
+ compatible = "arm,cortex-a520-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu-a720 {
+ compatible = "arm,cortex-a720-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-x4 {
+ compatible = "arm,cortex-x4-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
@@ -758,8 +766,8 @@
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&pcie0_phy>,
- <&pcie1_phy>,
- <&pcie_1_phy_aux_clk>,
+ <&pcie1_phy QMP_PCIE_PIPE_CLK>,
+ <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
@@ -2208,7 +2216,7 @@
reg = <0 0x010c3000 0 0x1000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -2294,7 +2302,7 @@
status = "disabled";
- pcie@0 {
+ pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2336,7 +2344,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c08000 0 0x3000>,
@@ -2467,7 +2475,7 @@
power-domains = <&gcc PCIE_1_PHY_GDSC>;
- #clock-cells = <0>;
+ #clock-cells = <1>;
clock-output-names = "pcie1_pipe_clk";
#phy-cells = <0>;
@@ -2626,6 +2634,7 @@
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
status = "disabled";
@@ -3309,6 +3318,30 @@
};
};
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8650-videocc";
+ reg = <0 0x0aaf0000 0 0x10000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,sm8650-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8650-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@@ -3675,6 +3708,7 @@
reg = <1>;
mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
};
};
};
@@ -3750,6 +3784,8 @@
#clock-cells = <1>;
#phy-cells = <1>;
+ orientation-switch;
+
status = "disabled";
ports {
@@ -3767,6 +3803,7 @@
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
};
};
@@ -3774,6 +3811,7 @@
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -3864,6 +3902,7 @@
reg = <1>;
usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
@@ -4982,12 +5021,14 @@
<0 0x25400000 0 0x200000>,
<0 0x25200000 0 0x200000>,
<0 0x25600000 0 0x200000>,
- <0 0x25800000 0 0x200000>;
+ <0 0x25800000 0 0x200000>,
+ <0 0x25a00000 0 0x200000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
- "llcc_broadcast_base";
+ "llcc_broadcast_base",
+ "llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -5328,8 +5369,6 @@
thermal-zones {
aoss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
trips {
@@ -5348,8 +5387,6 @@
};
cpuss0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
trips {
@@ -5368,8 +5405,6 @@
};
cpuss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
trips {
@@ -5388,8 +5423,6 @@
};
cpuss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
trips {
@@ -5408,8 +5441,6 @@
};
cpuss3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
trips {
@@ -5428,8 +5459,6 @@
};
cpu2-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
trips {
@@ -5454,8 +5483,6 @@
};
cpu2-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
trips {
@@ -5480,8 +5507,6 @@
};
cpu3-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
trips {
@@ -5506,8 +5531,6 @@
};
cpu3-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
trips {
@@ -5532,8 +5555,6 @@
};
cpu4-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
trips {
@@ -5558,8 +5579,6 @@
};
cpu4-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
trips {
@@ -5584,8 +5603,6 @@
};
cpu5-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
trips {
@@ -5610,8 +5627,6 @@
};
cpu5-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
trips {
@@ -5636,8 +5651,6 @@
};
cpu6-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
trips {
@@ -5662,8 +5675,6 @@
};
cpu6-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
trips {
@@ -5688,8 +5699,6 @@
};
aoss1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
trips {
@@ -5708,8 +5717,6 @@
};
cpu7-top-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
@@ -5734,8 +5741,6 @@
};
cpu7-middle-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
@@ -5760,8 +5765,6 @@
};
cpu7-bottom-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
trips {
@@ -5786,8 +5789,6 @@
};
cpu0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
trips {
@@ -5812,8 +5813,6 @@
};
cpu1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
trips {
@@ -5839,7 +5838,7 @@
nsphvx0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
trips {
@@ -5859,7 +5858,7 @@
nsphvx1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
trips {
@@ -5879,7 +5878,7 @@
nsphmx0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
trips {
@@ -5899,7 +5898,7 @@
nsphmx1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 9>;
trips {
@@ -5919,7 +5918,7 @@
nsphmx2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 10>;
trips {
@@ -5939,7 +5938,7 @@
nsphmx3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 11>;
trips {
@@ -5959,7 +5958,7 @@
video-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 12>;
trips {
@@ -5979,7 +5978,7 @@
ddr-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens1 13>;
trips {
@@ -5998,8 +5997,6 @@
};
camera0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 14>;
trips {
@@ -6018,8 +6015,6 @@
};
camera1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens1 15>;
trips {
@@ -6038,8 +6033,6 @@
};
aoss2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 0>;
trips {
@@ -6059,19 +6052,32 @@
gpuss0-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 1>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss0-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6079,19 +6085,32 @@
gpuss1-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss1-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6099,19 +6118,32 @@
gpuss2-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu2_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu2_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss2-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6119,19 +6151,32 @@
gpuss3-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 4>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu3_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu3_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss3-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6139,19 +6184,32 @@
gpuss4-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu4_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu4_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss4-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6159,19 +6217,32 @@
gpuss5-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu5_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu5_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss5-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6179,19 +6250,32 @@
gpuss6-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu6_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu6_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss6-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
@@ -6199,27 +6283,38 @@
gpuss7-thermal {
polling-delay-passive = <10>;
- polling-delay = <0>;
+
thermal-sensors = <&tsens2 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu7_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
+ gpu7_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
temperature = <90000>;
- hysteresis = <2000>;
+ hysteresis = <1000>;
type = "hot";
};
- gpuss7-critical {
+ trip-point2 {
temperature = <110000>;
- hysteresis = <0>;
+ hysteresis = <1000>;
type = "critical";
};
};
};
modem0-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 9>;
trips {
@@ -6238,8 +6333,6 @@
};
modem1-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 10>;
trips {
@@ -6258,8 +6351,6 @@
};
modem2-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 11>;
trips {
@@ -6278,8 +6369,6 @@
};
modem3-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
thermal-sensors = <&tsens2 12>;
trips {
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
new file mode 100644
index 0000000..9caa14d
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
@@ -0,0 +1,652 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+ model = "ASUS Vivobook S 15";
+ compatible = "asus,vivobook-s15", "qcom,x1e80100";
+ chassis-type = "laptop";
+
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Left-side port, closer to the screen */
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ /* Left-side port, farther from the screen */
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss1_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x8000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&nvme_reg_en>;
+ pinctrl-names = "default";
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p8: ldo1 {
+ regulator-name = "vreg_l1j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* PS8830 USB4 Retimer? @ 0x8 */
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* PS8830 USB4 Retimer? @ 0x8 */
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&kybd_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ /* EC? @ 0x5b, 0x76 */
+};
+
+&i2c7 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ /* PS8830 USB4 Retimer? @ 0x8 */
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mdss_dp3_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie4_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a {
+ perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-0 = <&pcie6a_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l1d_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcadsp8380.mbn",
+ "qcom/x1e80100/ASUSTeK/vivobook-s15/adsp_dtbs.elf";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qccdsp8380.mbn",
+ "qcom/x1e80100/ASUSTeK/vivobook-s15/cdsp_dtbs.elf";
+
+ status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2 {
+ status = "disabled";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <34 2>, /* Unused */
+ <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ kybd_default: kybd-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ bias-disable;
+ };
+
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ tpad_default: tpad-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ bias-disable;
+ };
+};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_0_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p8>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_1_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
index be6b1e7..e17ab82 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
@@ -49,6 +49,104 @@
stdout-path = "serial0:115200n8";
};
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>,
+ <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+ /* Left-side rear port */
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ /* Left-side front port */
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss1_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ /* Right-side port */
+ connector@2 {
+ compatible = "usb-c-connector";
+ reg = <2>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss2_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss2_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
@@ -170,9 +268,22 @@
pinctrl-0 = <&edp_reg_en>;
pinctrl-names = "default";
- regulator-always-on;
regulator-boot-on;
};
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+ };
};
&apps_rsc {
@@ -525,6 +636,14 @@
};
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
+ };
+};
+
&i2c0 {
clock-frequency = <400000>;
@@ -612,9 +731,13 @@
aux-bus {
panel {
- compatible = "edp-panel";
+ compatible = "samsung,atna45af01", "samsung,atna33xc20";
+ enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
power-supply = <&vreg_edp_3p3>;
+ pinctrl-0 = <&edp_bl_en>;
+ pinctrl-names = "default";
+
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_dp3_out>;
@@ -644,27 +767,51 @@
};
&pcie4 {
+ perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie4_default>;
+ pinctrl-names = "default";
+
status = "okay";
};
&pcie4_phy {
- vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
+ perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie6a_default>;
+
status = "okay";
};
&pcie6a_phy {
- vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
};
+&pmc8380_3_gpios {
+ edp_bl_en: edp-bl-en-state {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <1>; /* 1.8V */
+ input-disable;
+ output-enable;
+ };
+};
+
&qupv3_0 {
status = "okay";
};
@@ -804,6 +951,59 @@
bias-disable;
};
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
tpad_default: tpad-default-state {
pins = "gpio3";
function = "gpio";
@@ -840,8 +1040,8 @@
};
&usb_1_ss0_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_0_eusb2_repeater>;
@@ -849,6 +1049,9 @@
};
&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p8>;
+
status = "okay";
};
@@ -858,12 +1061,19 @@
&usb_1_ss0_dwc3 {
dr_mode = "host";
- usb-role-switch;
+};
+
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
&usb_1_ss1_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_1_eusb2_repeater>;
@@ -871,6 +1081,9 @@
};
&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
status = "okay";
};
@@ -880,12 +1093,19 @@
&usb_1_ss1_dwc3 {
dr_mode = "host";
- usb-role-switch;
+};
+
+&usb_1_ss1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
};
&usb_1_ss2_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_2_eusb2_repeater>;
@@ -893,6 +1113,9 @@
};
&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
status = "okay";
};
@@ -902,5 +1125,12 @@
&usb_1_ss2_dwc3 {
dr_mode = "host";
- usb-role-switch;
+};
+
+&usb_1_ss2_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss2_ss_in>;
};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
new file mode 100644
index 0000000..1943bdb
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
@@ -0,0 +1,967 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+ model = "Lenovo Yoga Slim 7x";
+ compatible = "lenovo,yoga-slim7x", "qcom,x1e80100";
+
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>,
+ <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+ /* Left-side rear port */
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ /* Left-side front port */
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss1_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ /* Right-side port */
+ connector@2 {
+ compatible = "usb-c-connector";
+ reg = <2>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss2_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss2_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x8000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ sound {
+ compatible = "qcom,x1e80100-sndcard";
+ model = "X1E80100-LENOVO-Yoga-Slim7x";
+ audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT",
+ "TweeterLeft IN", "WSA WSA_SPK2 OUT",
+ "WooferRight IN", "WSA2 WSA_SPK2 OUT",
+ "TweeterRight IN", "WSA2 WSA_SPK2 OUT";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_woofer>, <&left_tweeter>,
+ <&swr0 0>, <&lpass_wsamacro 0>,
+ <&right_woofer>, <&right_tweeter>,
+ <&swr3 0>, <&lpass_wsa2macro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&nvme_reg_en>;
+ pinctrl-names = "default";
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_3p0: ldo8 {
+ regulator-name = "vreg_l8b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p2: ldo12 {
+ regulator-name = "vreg_l12b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_0p8: ldo2 {
+ regulator-name = "vreg_l2c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p8: ldo3 {
+ regulator-name = "vreg_l3c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p0: ldo1 {
+ regulator-name = "vreg_l1f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_1p0: ldo2 {
+ regulator-name = "vreg_l2f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_1p0: ldo3 {
+ regulator-name = "vreg_l3f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_s1i_0p9: smps1 {
+ regulator-name = "vreg_s1i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2i_1p0: smps2 {
+ regulator-name = "vreg_s2i_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p8: ldo1 {
+ regulator-name = "vreg_l1i_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p8: ldo1 {
+ regulator-name = "vreg_l1j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/x1e80100/LENOVO/83ED/qcdxkmsuc8380.mbn";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+
+ hid-descr-addr = <0x20>;
+ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&kybd_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchscreen@14 {
+ compatible = "hid-over-i2c";
+ reg = <0x14>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ts0_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&lpass_tlmm {
+ spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ spkr_23_sd_n_active: spkr-23-sd-n-active-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+ pinctrl-names = "default";
+
+ vdd-micb-supply = <&vreg_l1b_1p8>;
+ qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mdss_dp3_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie4_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie4_port0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ qcom,ath12k-calibration-variant = "LES790";
+ };
+};
+
+&pcie6a {
+ perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-0 = <&pcie6a_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l1d_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/LENOVO/83ED/qcadsp8380.mbn",
+ "qcom/x1e80100/LENOVO/83ED/adsp_dtbs.elf";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/LENOVO/83ED/qccdsp8380.mbn",
+ "qcom/x1e80100/LENOVO/83ED/cdsp_dtbs.elf";
+
+ status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2_eusb2_repeater {
+ vdd18-supply = <&vreg_l3d_1p8>;
+ vdd3-supply = <&vreg_l8b_3p0>;
+};
+
+&swr0 {
+ status = "okay";
+
+ pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+ pinctrl-names = "default";
+
+ /* WSA8845, Left Woofer */
+ left_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Left Tweeter */
+ left_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TweeterLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+
+&swr3 {
+ status = "okay";
+
+ pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>;
+ pinctrl-names = "default";
+
+ /* WSA8845, Right Woofer */
+ right_woofer: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "WooferRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ /* WSA8845, Right Tweeter */
+ right_tweeter: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TweeterRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <34 2>, /* Unused */
+ <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ kybd_default: kybd-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ bias-disable;
+ };
+
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ tpad_default: tpad-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ bias-disable;
+ };
+
+ ts0_default: ts0-default-state {
+ int-n-pins {
+ pins = "gpio51";
+ function = "gpio";
+ bias-disable;
+ };
+
+ reset-n-pins {
+ pins = "gpio48";
+ function = "gpio";
+ output-high;
+ drive-strength = <16>;
+ };
+ };
+
+};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_0_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p8>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_1_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ orientation-switch;
+
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
+
+ phys = <&smb2360_2_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
+ status = "okay";
+};
+
+&usb_1_ss2 {
+ status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_1_ss2_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss2_ss_in>;
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
index 04301f7..e34e709 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
@@ -3,12 +3,479 @@
* Copyright (c) 2024, Linaro Limited
*/
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
+ thermal-zones {
+ pm8550-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-2-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_2_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmc8380-3-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmc8380_3_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmc8380-4-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmc8380_4_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmc8380-5-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmc8380_5_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pmc8380-6-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pmc8380_6_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-8-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_8_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-9-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_9_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8010-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8010_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
};
+&spmi_bus0 {
+ /* PMK8380 */
+ pmk8550: pmic@0 {
+ compatible = "qcom,pm8550", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmk8550_pon: pon@1300 {
+ compatible = "qcom,pmk8350-pon";
+ reg = <0x1300>, <0x800>;
+ reg-names = "hlos", "pbs";
+
+ pon_pwrkey: pwrkey {
+ compatible = "qcom,pmk8350-pwrkey";
+ interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ };
+
+ pon_resin: resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ status = "disabled";
+ };
+ };
+
+ pmk8550_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ /* Not yet sure what blocks access */
+ status = "reserved";
+ };
+
+ pmk8550_sdam_2: nvram@7100 {
+ compatible = "qcom,spmi-sdam";
+ reg = <0x7100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7100 0x100>;
+
+ reboot_reason: reboot-reason@48 {
+ reg = <0x48 0x1>;
+ bits = <1 7>;
+ };
+ };
+
+ pmk8550_gpios: gpio@8800 {
+ compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio";
+ reg = <0xb800>;
+ gpio-controller;
+ gpio-ranges = <&pmk8550_gpios 0 0 6>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ /* PMC8380C */
+ pm8550: pmic@1 {
+ compatible = "qcom,pm8550", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550_gpios: gpio@8800 {
+ compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm8550_flash: led-controller@ee00 {
+ compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led";
+ reg = <0xee00>;
+ status = "disabled";
+ };
+
+ pm8550_pwm: pwm {
+ compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";
+ #pwm-cells = <2>;
+
+ status = "disabled";
+ };
+ };
+
+ /* PMC8380VE */
+ pm8550ve_2: pmic@2 {
+ compatible = "qcom,pm8550", "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_2_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_2_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_2_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ /* PMC8380 is actually not a PM8550 series rebrand */
+ pmc8380_3: pmic@3 {
+ compatible = "qcom,pmc8380", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmc8380_3_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmc8380_3_gpios: gpio@8800 {
+ compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmc8380_3_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmc8380_4: pmic@4 {
+ compatible = "qcom,pmc8380", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmc8380_4_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmc8380_4_gpios: gpio@8800 {
+ compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmc8380_4_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmc8380_5: pmic@5 {
+ compatible = "qcom,pmc8380", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmc8380_5_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmc8380_5_gpios: gpio@8800 {
+ compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmc8380_5_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmc8380_6: pmic@6 {
+ compatible = "qcom,pmc8380", "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmc8380_6_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmc8380_6_gpios: gpio@8800 {
+ compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmc8380_6_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ /* PMC8380VE */
+ pm8550ve_8: pmic@8 {
+ compatible = "qcom,pm8550", "qcom,spmi-pmic";
+ reg = <0x8 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_8_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_8_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_8_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ /* PMC8380VE */
+ pm8550ve_9: pmic@9 {
+ compatible = "qcom,pm8550", "qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_9_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_9_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_9_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8010: pmic@c {
+ compatible = "qcom,pm8010", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8010_temp_alarm: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
+
&spmi_bus1 {
smb2360_0: pmic@7 {
compatible = "qcom,smb2360", "qcom,spmi-pmic";
@@ -48,4 +515,19 @@
#phy-cells = <0>;
};
};
+
+ smb2360_3: pmic@c {
+ compatible = "qcom,smb2360", "qcom,spmi-pmic";
+ reg = <0xc SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ smb2360_3_eusb2_repeater: phy@fd00 {
+ compatible = "qcom,smb2360-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
index 8f67c39..8098e67 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
@@ -19,10 +19,131 @@
serial0 = &uart21;
};
+ wcd938x: audio-codec {
+ compatible = "qcom,wcd9385-codec";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_default>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+ vdd-buck-supply = <&vreg_l15b_1p8>;
+ vdd-rxtx-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob1>;
+
+ #sound-dai-cells = <1>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
+ pmic-glink {
+ compatible = "qcom,x1e80100-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>,
+ <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss0_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss0_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss1_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss1_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+ };
+ };
+ };
+ };
+
+ connector@2 {
+ compatible = "usb-c-connector";
+ reg = <2>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_ss2_hs_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss2_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
linux,cma {
compatible = "shared-dma-pool";
@@ -32,6 +153,66 @@
};
};
+ sound {
+ compatible = "qcom,x1e80100-sndcard";
+ model = "X1E80100-QCP";
+ audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_INPUT1", "ADC2_OUTPUT";
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
@@ -59,6 +240,20 @@
regulator-always-on;
regulator-boot-on;
};
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_NVME_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+ };
};
&apps_rsc {
@@ -411,6 +606,24 @@
};
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
+ };
+};
+
+&lpass_tlmm {
+ spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
&mdss {
status = "okay";
};
@@ -455,22 +668,36 @@
};
&pcie4 {
+ perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie4_default>;
+ pinctrl-names = "default";
+
status = "okay";
};
&pcie4_phy {
- vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
status = "okay";
};
&pcie6a {
+ perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie6a_default>;
+
status = "okay";
};
&pcie6a_phy {
- vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
status = "okay";
@@ -502,6 +729,10 @@
status = "okay";
};
+&smb2360_3 {
+ status = "okay";
+};
+
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
@@ -517,6 +748,57 @@
vdd3-supply = <&vreg_l8b_3p0>;
};
+&swr0 {
+ pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ /* WSA8845, Left Speaker */
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+
+ /* WSA8845, Right Speaker */
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ #sound-dai-cells = <0>;
+ reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l12b_1p2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ /* WCD9385 RX */
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr2 {
+ status = "okay";
+
+ /* WCD9385 TX */
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <33 3>, /* Unused */
<44 4>, /* SPI (TPM) */
@@ -528,6 +810,67 @@
drive-strength = <16>;
bias-disable;
};
+
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio147";
+ function = "pcie4_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio146";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie6a_default: pcie6a-default-state {
+ clkreq-n-pins {
+ pins = "gpio153";
+ function = "pcie6a_clk";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio152";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake-n-pins {
+ pins = "gpio154";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio191";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
};
&uart21 {
@@ -536,8 +879,8 @@
};
&usb_1_ss0_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_0_eusb2_repeater>;
@@ -545,6 +888,9 @@
};
&usb_1_ss0_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l1j_0p8>;
+
status = "okay";
};
@@ -554,12 +900,19 @@
&usb_1_ss0_dwc3 {
dr_mode = "host";
- usb-role-switch;
};
+&usb_1_ss0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss0_ss_in>;
+};
+
&usb_1_ss1_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_1_eusb2_repeater>;
@@ -567,6 +920,9 @@
};
&usb_1_ss1_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
status = "okay";
};
@@ -576,12 +932,19 @@
&usb_1_ss1_dwc3 {
dr_mode = "host";
- usb-role-switch;
};
+&usb_1_ss1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss1_ss_in>;
+};
+
&usb_1_ss2_hsphy {
- vdd-supply = <&vreg_l2e_0p8>;
- vdda12-supply = <&vreg_l3e_1p2>;
+ vdd-supply = <&vreg_l3j_0p8>;
+ vdda12-supply = <&vreg_l2j_1p2>;
phys = <&smb2360_2_eusb2_repeater>;
@@ -589,6 +952,9 @@
};
&usb_1_ss2_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l2d_0p9>;
+
status = "okay";
};
@@ -598,5 +964,12 @@
&usb_1_ss2_dwc3 {
dr_mode = "host";
- usb-role-switch;
+};
+
+&usb_1_ss2_dwc3_hs {
+ remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+ remote-endpoint = <&pmic_glink_ss2_ss_in>;
};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100.dtsi b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
index 05e4d49..cd732ef 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -2505,6 +2506,66 @@
};
};
+ tsens0: thermal-sensor@c271000 {
+ compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c271000 0 0x1000>,
+ <0 0x0c222000 0 0x1000>;
+
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <16>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c272000 {
+ compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c272000 0 0x1000>,
+ <0 0x0c223000 0 0x1000>;
+
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <16>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c273000 {
+ compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c273000 0 0x1000>,
+ <0 0x0c224000 0 0x1000>;
+
+ interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <16>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c274000 {
+ compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c274000 0 0x1000>,
+ <0 0x0c225000 0 0x1000>;
+
+ interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <16>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
usb_1_ss0_hsphy: phy@fd3000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
@@ -2543,6 +2604,34 @@
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss0_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
+ };
+ };
+ };
};
usb_1_ss1_hsphy: phy@fd9000 {
@@ -2583,6 +2672,34 @@
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp1_out>;
+ };
+ };
+ };
};
usb_1_ss2_hsphy: phy@fde000 {
@@ -2623,6 +2740,34 @@
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss2_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp2_out>;
+ };
+ };
+ };
};
cnoc_main: interconnect@1500000 {
@@ -2756,7 +2901,7 @@
dma-coherent;
- linux,pci-domain = <7>;
+ linux,pci-domain = <6>;
num-lanes = <2>;
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
@@ -2814,6 +2959,7 @@
"link_down";
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie6a_phy>;
phy-names = "pciephy";
@@ -2877,7 +3023,7 @@
dma-coherent;
- linux,pci-domain = <5>;
+ linux,pci-domain = <4>;
num-lanes = <2>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
@@ -2935,11 +3081,22 @@
"link_down";
power-domains = <&gcc GCC_PCIE_4_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>;
phy-names = "pciephy";
status = "disabled";
+
+ pcie4_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie4_phy: phy@1c0e000 {
@@ -2985,6 +3142,201 @@
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
+ };
+
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-43050c01", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x0>,
+ <&adreno_smmu 1 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&gpu_microcode_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <16500000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <14398438>;
+ };
+
+ opp-925000000 {
+ opp-hz = /bits/ 64 <925000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <14398438>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <12449219>;
+ };
+
+ opp-744000000 {
+ opp-hz = /bits/ 64 <744000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <10687500>;
+ };
+
+ opp-687000000 {
+ opp-hz = /bits/ 64 <687000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <6074219>;
+ };
+
+ opp-390000000 {
+ opp-hz = /bits/ 64 <390000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136719>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x35000>,
+ <0x0 0x03d50000 0x0 0x10000>,
+ <0x0 0x0b280000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,x1e80100-gpucc";
+ reg = <0 0x03d90000 0 0xa000>;
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ dma-coherent;
};
gem_noc: interconnect@26400000 {
@@ -3447,8 +3799,23 @@
dma-coherent;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
- port {
- usb_1_ss2_role_switch: endpoint {
+ usb_1_ss2_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3516,8 +3883,15 @@
phy-names = "usb2-phy";
maximum-speed = "high-speed";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
- port {
- usb_2_role_switch: endpoint {
+ usb_2_dwc3_hs: endpoint {
+ };
};
};
};
@@ -3592,8 +3966,23 @@
dma-coherent;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
- port {
- usb_1_ss0_role_switch: endpoint {
+ usb_1_ss0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3675,8 +4064,23 @@
dma-coherent;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
- port {
- usb_1_ss1_role_switch: endpoint {
+ usb_1_ss1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3862,6 +4266,7 @@
reg = <1>;
mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
};
};
};
@@ -3944,6 +4349,7 @@
reg = <1>;
mdss_dp1_out: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
};
};
};
@@ -4023,6 +4429,10 @@
port@1 {
reg = <1>;
+
+ mdss_dp2_out: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
+ };
};
};
@@ -5157,6 +5567,129 @@
};
};
+ pmu@24091000 {
+ compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x24091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <800000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <6220800>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6835200>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <8371200>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <10944000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <12748800>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <14745600>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <16896000>;
+ };
+ };
+ };
+
+ /* cluster0 */
+ pmu@240b3400 {
+ compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x240b3400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <4800000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <7464000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <9600000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <12896000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <14928000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <17064000>;
+ };
+ };
+ };
+
+ /* cluster2 */
+ pmu@240b5400 {
+ compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x240b5400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ };
+
+ /* cluster1 */
+ pmu@240b6400 {
+ compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x240b6400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ };
+
system-cache-controller@25000000 {
compatible = "qcom,x1e80100-llcc";
reg = <0 0x25000000 0 0x200000>,
@@ -5226,24 +5759,73 @@
label = "lpass";
qcom,remote-pid = <2>;
- gpr {
- compatible = "qcom,gpr";
- qcom,glink-channels = "adsp_apps";
- qcom,domain = <GPR_DOMAIN_ID_ADSP>;
- qcom,intents = <512 20>;
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
- q6apm: service@1 {
- compatible = "qcom,q6apm";
- reg = <GPR_APM_MODULE_IID>;
- #sound-dai-cells = <0>;
- qcom,protection-domain = "avs/audio",
- "msm/adsp/audio_pd";
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1063 0x0>;
+ dma-coherent;
+ };
- q6apmbedai: bedais {
- compatible = "qcom,q6apm-lpass-dais";
- #sound-dai-cells = <1>;
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1064 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1065 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1066 0x0>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x1007 0x80>,
+ <&apps_smmu 0x1067 0x0>;
+ dma-coherent;
+ };
+ };
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
};
q6apmdai: dais {
@@ -5315,6 +5897,101 @@
label = "cdsp";
qcom,remote-pid = <5>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0c01 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0c02 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0c03 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x0c04 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x0c05 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x0c06 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x0c07 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu 0x0c08 0x20>;
+ dma-coherent;
+ };
+
+ /* note: compute-cb@9 is secure */
+
+ compute-cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&apps_smmu 0x0c0c 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu 0x0c0d 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu 0x0c0e 0x20>;
+ dma-coherent;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu 0x0c0f 0x20>;
+ dma-coherent;
+ };
+ };
};
};
};
@@ -5327,4 +6004,1158 @@
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-0-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-0-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-1-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-1-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-2-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-2-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-3-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-3-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-top-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-btm-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mem-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mem-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-0-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-0-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-1-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-1-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-2-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-2-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-3-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-3-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-top-thermal {
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-btm-thermal {
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss2-thermal {
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-0-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-0-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-1-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-1-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-2-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-2-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-3-top-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-3-btm-thermal {
+ polling-delay-passive = <250>;
+
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss2-top-thermal {
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss2-btm-thermal {
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss3-thermal {
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp0-thermal {
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsp0-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp1-thermal {
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsp1-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp2-thermal {
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsp2-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp3-thermal {
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsp3-critical {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-2-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-3-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-4-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-5-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-6-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-7-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens3 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ trip-point2 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ thermal-sensors = <&tsens3 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera1-thermal {
+ thermal-sensors = <&tsens3 14>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/dts/upstream/src/arm64/renesas/condor-common.dtsi b/dts/upstream/src/arm64/renesas/condor-common.dtsi
index 7c34d14..8b7c0c3 100644
--- a/dts/upstream/src/arm64/renesas/condor-common.dtsi
+++ b/dts/upstream/src/arm64/renesas/condor-common.dtsi
@@ -227,6 +227,12 @@
};
};
};
+
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
};
&i2c1 {
diff --git a/dts/upstream/src/arm64/renesas/r8a774a1.dtsi b/dts/upstream/src/arm64/renesas/r8a774a1.dtsi
index a8a44fe..1dbf9d5 100644
--- a/dts/upstream/src/arm64/renesas/r8a774a1.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a774a1.dtsi
@@ -2853,6 +2853,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a774b1.dtsi b/dts/upstream/src/arm64/renesas/r8a774b1.dtsi
index 4fff511..10f22c5 100644
--- a/dts/upstream/src/arm64/renesas/r8a774b1.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a774b1.dtsi
@@ -2704,6 +2704,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a774c0.dtsi b/dts/upstream/src/arm64/renesas/r8a774c0.dtsi
index 1ef43d7..3e2af50 100644
--- a/dts/upstream/src/arm64/renesas/r8a774c0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a774c0.dtsi
@@ -1990,6 +1990,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a774e1.dtsi b/dts/upstream/src/arm64/renesas/r8a774e1.dtsi
index be55ae8..1eeb4c7 100644
--- a/dts/upstream/src/arm64/renesas/r8a774e1.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a774e1.dtsi
@@ -2985,6 +2985,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a77951.dtsi b/dts/upstream/src/arm64/renesas/r8a77951.dtsi
index bea4edd..96f3b5f 100644
--- a/dts/upstream/src/arm64/renesas/r8a77951.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77951.dtsi
@@ -3473,6 +3473,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a77960.dtsi b/dts/upstream/src/arm64/renesas/r8a77960.dtsi
index 7846fea..1122c47 100644
--- a/dts/upstream/src/arm64/renesas/r8a77960.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77960.dtsi
@@ -3068,6 +3068,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a77961.dtsi b/dts/upstream/src/arm64/renesas/r8a77961.dtsi
index 58f9286..bf1130a 100644
--- a/dts/upstream/src/arm64/renesas/r8a77961.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77961.dtsi
@@ -2889,6 +2889,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a77965.dtsi b/dts/upstream/src/arm64/renesas/r8a77965.dtsi
index 6929406..f02d154 100644
--- a/dts/upstream/src/arm64/renesas/r8a77965.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77965.dtsi
@@ -2877,6 +2877,7 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
/* External USB clocks - can be overridden by the board */
diff --git a/dts/upstream/src/arm64/renesas/r8a77970.dtsi b/dts/upstream/src/arm64/renesas/r8a77970.dtsi
index d2d3cec..64fb95b 100644
--- a/dts/upstream/src/arm64/renesas/r8a77970.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77970.dtsi
@@ -1223,5 +1223,6 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a77980-condor.dts b/dts/upstream/src/arm64/renesas/r8a77980-condor.dts
index 68d1f1d..1d32655 100644
--- a/dts/upstream/src/arm64/renesas/r8a77980-condor.dts
+++ b/dts/upstream/src/arm64/renesas/r8a77980-condor.dts
@@ -14,11 +14,3 @@
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
};
-
-&i2c0 {
- eeprom@50 {
- compatible = "rohm,br24t01", "atmel,24c01";
- reg = <0x50>;
- pagesize = <8>;
- };
-};
diff --git a/dts/upstream/src/arm64/renesas/r8a77980.dtsi b/dts/upstream/src/arm64/renesas/r8a77980.dtsi
index c0ba110..0c2b157 100644
--- a/dts/upstream/src/arm64/renesas/r8a77980.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77980.dtsi
@@ -1630,5 +1630,6 @@
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a77990.dtsi b/dts/upstream/src/arm64/renesas/r8a77990.dtsi
index 37063e3..233af30 100644
--- a/dts/upstream/src/arm64/renesas/r8a77990.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77990.dtsi
@@ -2157,5 +2157,6 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a77995.dtsi b/dts/upstream/src/arm64/renesas/r8a77995.dtsi
index 89990dd..5f0828a 100644
--- a/dts/upstream/src/arm64/renesas/r8a77995.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a77995.dtsi
@@ -1476,5 +1476,6 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
index cfa70b4..d763470 100644
--- a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
@@ -2919,6 +2919,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi b/dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi
index 477f311..4ed8d4c 100644
--- a/dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779f0-spider-cpu.dtsi
@@ -15,6 +15,12 @@
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &scif0;
};
diff --git a/dts/upstream/src/arm64/renesas/r8a779f0.dtsi b/dts/upstream/src/arm64/renesas/r8a779f0.dtsi
index 72cf303..9629adb 100644
--- a/dts/upstream/src/arm64/renesas/r8a779f0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779f0.dtsi
@@ -1324,7 +1324,10 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
ufs30_clk: ufs30-clk {
diff --git a/dts/upstream/src/arm64/renesas/r8a779f4-s4sk.dts b/dts/upstream/src/arm64/renesas/r8a779f4-s4sk.dts
index bc65a7b..fa910b8 100644
--- a/dts/upstream/src/arm64/renesas/r8a779f4-s4sk.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779f4-s4sk.dts
@@ -14,6 +14,12 @@
compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
serial0 = &hscif0;
serial1 = &hscif1;
ethernet0 = &rswitch;
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
index e6f5337..e6cf304 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
+++ b/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
@@ -155,11 +155,7 @@
pinctrl-0 = <&sound_clk_pins>, <&sound_pins>;
pinctrl-names = "default";
- /* Single DAI */
- #sound-dai-cells = <0>;
-
/* audio_clkout */
- #clock-cells = <0>;
clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */
// clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
index 9bc542b..53d1d4d 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
@@ -815,8 +815,6 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
@@ -862,8 +860,6 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
@@ -909,8 +905,6 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
@@ -1724,18 +1718,6 @@
};
rcar_sound: sound@ec5a0000 {
- /*
- * #sound-dai-cells is required
- *
- * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
- * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
- */
- /*
- * #clock-cells is required
- *
- * clkout : #clock-cells = <0>; <&rcar_sound>;
- * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>;
- */
compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4";
reg = <0 0xec5a0000 0 0x020>,
<0 0xec540000 0 0x1000>,
@@ -1745,6 +1727,11 @@
clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
clock-names = "ssiu.0", "ssi.0", "clkin";
+ /* #clock-cells is fixed */
+ #clock-cells = <0>;
+ /* #sound-dai-cells is fixed */
+ #sound-dai-cells = <0>;
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 2926>, <&cpg 2927>;
reset-names = "ssiu.0", "ssi.0";
@@ -2359,6 +2346,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
index cfbe8c8..2b9a19b 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
@@ -17,6 +17,10 @@
compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
serial0 = &hscif0;
serial1 = &hscif2;
ethernet0 = &avb0;
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
index 6d79102..a03ab2b 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
@@ -14,9 +14,15 @@
#address-cells = <2>;
#size-cells = <2>;
+ /* External Audio clock - to be overridden by boards that provide it */
+ audio_clkin: audio_clkin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
- opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
@@ -937,8 +943,456 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ };
+
+ vin00: video@e6ef0000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 730>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 730>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin00isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin00>;
+ };
+ };
+ };
+ };
+
+ vin01: video@e6ef1000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 731>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 731>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin01isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin01>;
+ };
+ };
+ };
+ };
+
+ vin02: video@e6ef2000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 800>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 800>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin02isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin02>;
+ };
+ };
+ };
+ };
+
+ vin03: video@e6ef3000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 801>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 801>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin03isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin03>;
+ };
+ };
+ };
+ };
+
+ vin04: video@e6ef4000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 802>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 802>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin04isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin04>;
+ };
+ };
+ };
};
+ vin05: video@e6ef5000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 803>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 803>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin05isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin05>;
+ };
+ };
+ };
+ };
+
+ vin06: video@e6ef6000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 804>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin06isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin06>;
+ };
+ };
+ };
+ };
+
+ vin07: video@e6ef7000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 805>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin07isp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&isp0vin07>;
+ };
+ };
+ };
+ };
+
+ vin08: video@e6ef8000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 806>;
+ renesas,id = <8>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin08isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin08>;
+ };
+ };
+ };
+ };
+
+ vin09: video@e6ef9000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 807>;
+ renesas,id = <9>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin09isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin09>;
+ };
+ };
+ };
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 808>;
+ renesas,id = <10>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin10isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin10>;
+ };
+ };
+ };
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 809>;
+ renesas,id = <11>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin11isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin11>;
+ };
+ };
+ };
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 810>;
+ renesas,id = <12>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin12isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin12>;
+ };
+ };
+ };
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 811>;
+ renesas,id = <13>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin13isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin13>;
+ };
+ };
+ };
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 812>;
+ renesas,id = <14>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin14isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin14>;
+ };
+ };
+ };
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a779h0";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 813>;
+ renesas,id = <15>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <2>;
+
+ vin15isp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&isp1vin15>;
+ };
+ };
+ };
+ };
+
dmac1: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779h0",
"renesas,rcar-gen4-dmac";
@@ -1011,6 +1465,67 @@
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
};
+ rcar_sound: sound@ec400000 {
+ compatible = "renesas,rcar_sound-r8a779h0", "renesas,rcar_sound-gen4";
+ reg = <0 0xec400000 0 0x40000>,
+ <0 0xec540000 0 0x1000>,
+ <0 0xec541000 0 0x050>,
+ <0 0xec5a0000 0 0x020>;
+ reg-names = "sdmc", "ssiu", "ssi", "adg";
+ clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>;
+ clock-names = "ssiu.0", "ssi.0", "clkin";
+ /* #clock-cells is fixed */
+ #clock-cells = <0>;
+ /* #sound-dai-cells is fixed */
+ #sound-dai-cells = <0>;
+
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 2926>, <&cpg 2927>;
+ reset-names = "ssiu.0", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&dmac1 0x6e>, <&dmac1 0x6f>;
+ dma-names = "tx", "rx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&dmac1 0x6c>, <&dmac1 0x6d>;
+ dma-names = "tx", "rx";
+ };
+ ssiu02: ssiu-2 {
+ dmas = <&dmac1 0x6a>, <&dmac1 0x6b>;
+ dma-names = "tx", "rx";
+ };
+ ssiu03: ssiu-3 {
+ dmas = <&dmac1 0x68>, <&dmac1 0x69>;
+ dma-names = "tx", "rx";
+ };
+ ssiu04: ssiu-4 {
+ dmas = <&dmac1 0x66>, <&dmac1 0x67>;
+ dma-names = "tx", "rx";
+ };
+ ssiu05: ssiu-5 {
+ dmas = <&dmac1 0x64>, <&dmac1 0x65>;
+ dma-names = "tx", "rx";
+ };
+ ssiu06: ssiu-6 {
+ dmas = <&dmac1 0x62>, <&dmac1 0x63>;
+ dma-names = "tx", "rx";
+ };
+ ssiu07: ssiu-7 {
+ dmas = <&dmac1 0x60>, <&dmac1 0x61>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779h0",
"renesas,rcar-gen4-sdhi";
@@ -1152,6 +1667,224 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ csi40: csi2@fe500000 {
+ compatible = "renesas,r8a779h0-csi2";
+ reg = <0 0xfe500000 0 0x40000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 331>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ csi40isp0: endpoint {
+ remote-endpoint = <&isp0csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@fe540000 {
+ compatible = "renesas,r8a779h0-csi2";
+ reg = <0 0xfe540000 0 0x40000>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 400>;
+ power-domains = <&sysc R8A779H0_PD_C4>;
+ resets = <&cpg 400>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ csi41isp1: endpoint {
+ remote-endpoint = <&isp1csi41>;
+ };
+ };
+ };
+ };
+
+ isp0: isp@fed00000 {
+ compatible = "renesas,r8a779h0-isp";
+ reg = <0 0xfed00000 0 0x10000>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A779H0_PD_A3ISP0>;
+ resets = <&cpg 612>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ isp0csi40: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&csi40isp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isp0vin00: endpoint {
+ remote-endpoint = <&vin00isp0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ isp0vin01: endpoint {
+ remote-endpoint = <&vin01isp0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ isp0vin02: endpoint {
+ remote-endpoint = <&vin02isp0>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ isp0vin03: endpoint {
+ remote-endpoint = <&vin03isp0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ isp0vin04: endpoint {
+ remote-endpoint = <&vin04isp0>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ isp0vin05: endpoint {
+ remote-endpoint = <&vin05isp0>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ isp0vin06: endpoint {
+ remote-endpoint = <&vin06isp0>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ isp0vin07: endpoint {
+ remote-endpoint = <&vin07isp0>;
+ };
+ };
+ };
+ };
+
+ isp1: isp@fed20000 {
+ compatible = "renesas,r8a779h0-isp";
+ reg = <0 0xfed20000 0 0x10000>;
+ interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&cpg CPG_MOD 613>;
+ power-domains = <&sysc R8A779H0_PD_A3ISP0>;
+ resets = <&cpg 613>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ isp1csi41: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csi41isp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isp1vin08: endpoint {
+ remote-endpoint = <&vin08isp1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ isp1vin09: endpoint {
+ remote-endpoint = <&vin09isp1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ isp1vin10: endpoint {
+ remote-endpoint = <&vin10isp1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ isp1vin11: endpoint {
+ remote-endpoint = <&vin11isp1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ isp1vin12: endpoint {
+ remote-endpoint = <&vin12isp1>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ isp1vin13: endpoint {
+ remote-endpoint = <&vin13isp1>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ isp1vin14: endpoint {
+ remote-endpoint = <&vin14isp1>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ isp1vin15: endpoint {
+ remote-endpoint = <&vin15isp1>;
+ };
+ };
+ };
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
@@ -1195,5 +1928,7 @@
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r9a07g043.dtsi b/dts/upstream/src/arm64/renesas/r9a07g043.dtsi
index 6212ee5..2eccab9 100644
--- a/dts/upstream/src/arm64/renesas/r9a07g043.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a07g043.dtsi
@@ -646,7 +646,7 @@
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
@@ -662,7 +662,7 @@
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi b/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi
index 165bfcf..18ef297 100644
--- a/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a07g043u.dtsi
@@ -50,7 +50,10 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r9a07g044.dtsi b/dts/upstream/src/arm64/renesas/r9a07g044.dtsi
index 88634ae..d3838e5 100644
--- a/dts/upstream/src/arm64/renesas/r9a07g044.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a07g044.dtsi
@@ -1050,7 +1050,7 @@
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g044",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@@ -1066,7 +1066,7 @@
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g044",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -1334,6 +1334,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r9a07g054.dtsi b/dts/upstream/src/arm64/renesas/r9a07g054.dtsi
index e89bfe4..1de2e5f 100644
--- a/dts/upstream/src/arm64/renesas/r9a07g054.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a07g054.dtsi
@@ -1058,7 +1058,7 @@
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g054",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@@ -1074,7 +1074,7 @@
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g054",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -1342,6 +1342,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
index f5f3f4f..0d5c47a 100644
--- a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
@@ -182,7 +182,7 @@
};
sdhi0: mmc@11c00000 {
- compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+ compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -197,7 +197,7 @@
};
sdhi1: mmc@11c10000 {
- compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+ compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -212,7 +212,7 @@
};
sdhi2: mmc@11c20000 {
- compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
+ compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
reg = <0x0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -294,6 +294,9 @@
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
index 50ed66d..9a4cbef 100644
--- a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
@@ -71,7 +71,7 @@
sdhi0: mmc@85000000 {
compatible = "renesas,sdhi-r9a09g011",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x85000000 0 0x2000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
@@ -87,7 +87,7 @@
sdhi1: mmc@85010000 {
compatible = "renesas,sdhi-r9a09g011",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x85010000 0 0x2000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
@@ -103,7 +103,7 @@
emmc: mmc@85020000 {
compatible = "renesas,sdhi-r9a09g011",
- "renesas,rcar-gen3-sdhi";
+ "renesas,rzg2l-sdhi";
reg = <0x0 0x85020000 0 0x2000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
@@ -372,5 +372,6 @@
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
};
};
diff --git a/dts/upstream/src/arm64/renesas/rz-smarc-common.dtsi b/dts/upstream/src/arm64/renesas/rz-smarc-common.dtsi
index b7a3e6c..b3485595 100644
--- a/dts/upstream/src/arm64/renesas/rz-smarc-common.dtsi
+++ b/dts/upstream/src/arm64/renesas/rz-smarc-common.dtsi
@@ -54,14 +54,6 @@
};
};
- usb0_vbus_otg: regulator-usb0-vbus-otg {
- compatible = "regulator-fixed";
-
- regulator-name = "USB0_VBUS_OTG";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
@@ -139,6 +131,9 @@
&phyrst {
status = "okay";
+ usb0_vbus_otg: regulator-vbus {
+ regulator-name = "vbus";
+ };
};
&scif0 {
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-cpu-common.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-cpu-common.dtsi
index 8ac1737..80496fb 100644
--- a/dts/upstream/src/arm64/renesas/white-hawk-cpu-common.dtsi
+++ b/dts/upstream/src/arm64/renesas/white-hawk-cpu-common.dtsi
@@ -13,6 +13,12 @@
/ {
aliases {
ethernet0 = &avb0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
serial0 = &hscif0;
};
@@ -142,18 +148,23 @@
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
- phy-handle = <&phy0>;
+ phy-handle = <&avb0_phy>;
tx-internal-delay-ps = <2000>;
status = "okay";
- phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0022.1622",
- "ethernet-phy-ieee802.3-c22";
- rxc-skew-ps = <1500>;
- reg = <0>;
- interrupt-parent = <&gpio7>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ avb0_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+ "ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-ethernet.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-ethernet.dtsi
index a218fda..595ec4f 100644
--- a/dts/upstream/src/arm64/renesas/white-hawk-ethernet.dtsi
+++ b/dts/upstream/src/arm64/renesas/white-hawk-ethernet.dtsi
@@ -6,6 +6,57 @@
* Copyright (C) 2022 Glider bv
*/
+/ {
+ aliases {
+ ethernet1 = &avb1;
+ ethernet2 = &avb2;
+ };
+};
+
+&avb1 {
+ pinctrl-0 = <&avb1_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&avb1_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <4000>;
+
+ avb1_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&avb2 {
+ pinctrl-0 = <&avb2_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&avb2_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <4000>;
+
+ avb2_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
&i2c0 {
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
@@ -14,3 +65,55 @@
pagesize = <8>;
};
};
+
+&pfc {
+ avb1_pins: avb1 {
+ mux {
+ groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
+ "avb1_txcrefclk";
+ function = "avb1";
+ };
+
+ mdio {
+ groups = "avb1_mdio";
+ drive-strength = <24>;
+ bias-disable;
+ };
+
+ rgmii {
+ groups = "avb1_rgmii";
+ drive-strength = <24>;
+ bias-disable;
+ };
+
+ link {
+ groups = "avb1_link";
+ bias-disable;
+ };
+ };
+
+ avb2_pins: avb2 {
+ mux {
+ groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
+ "avb2_txcrefclk";
+ function = "avb2";
+ };
+
+ mdio {
+ groups = "avb2_mdio";
+ drive-strength = <24>;
+ bias-disable;
+ };
+
+ rgmii {
+ groups = "avb2_rgmii";
+ drive-strength = <24>;
+ bias-disable;
+ };
+
+ link {
+ groups = "avb2_link";
+ bias-disable;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
index a608a21..3e08e2f 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -387,7 +387,7 @@
pmic {
pmic_int_l: pmic-int-l {
- rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
index 229fe9d..90fef76 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
@@ -154,6 +154,8 @@
};
&hdmi {
+ avdd-0v9-supply = <&vdd_10>;
+ avdd-1v8-supply = <&vcc_18>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328.dtsi b/dts/upstream/src/arm64/rockchip/rk3328.dtsi
index 07dcc94..b01efd6 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328.dtsi
@@ -850,8 +850,8 @@
<0>, <24000000>,
<24000000>, <24000000>,
<15000000>, <15000000>,
- <100000000>, <100000000>,
- <100000000>, <100000000>,
+ <300000000>, <100000000>,
+ <400000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-lba3368.dts b/dts/upstream/src/arm64/rockchip/rk3368-lba3368.dts
new file mode 100644
index 0000000..e0cc4da
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3368-lba3368.dts
@@ -0,0 +1,659 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/clock/rockchip,rk808.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/rt5640.h>
+#include "rk3368.dtsi"
+
+/ {
+ model = "Neardi LBA3368";
+ compatible = "neardi,lba3368", "rockchip,rk3368";
+
+ aliases {
+ ethernet0 = &gmac;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio0;
+ rtc0 = &hym8563;
+ rtc1 = &rk808;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ adc-key {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ poll-interval = <100>;
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s_8ch_p0>;
+ hp-det-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ label = "alc5640";
+ routing = "Mic Jack", "MICBIAS1",
+ "IN1P", "Mic Jack",
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR",
+ "Speakers", "SPORP",
+ "Speakers", "SPORN",
+ "Speakers", "SPOLP",
+ "Speakers", "SPOLN";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speakers";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det>;
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ hub_avdd: hub-avdd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "hub_avdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power-led {
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_reg_on>;
+ };
+
+ vcc_host: vcc-host-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vcc_lan: vcc-lan-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ regulator-always-on;
+ };
+
+ vcc_otg: vcc-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd10_usb: vdd10-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd10_usb";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ vin-supply = <&vdd_10>;
+ regulator-always-on;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&emmc {
+ bus-width = <8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ cap-mmc-highspeed;
+ non-removable;
+ no-sd;
+ no-sdio;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&gmac {
+ clock_in_out = "input";
+ phy-handle = <&phy>;
+ phy-mode = "rmii";
+ phy-supply = <&vcc_lan>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ max-speed = <100>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <1000000>;
+ reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&phy_rst>;
+ };
+ };
+};
+
+&io_domains {
+ audio-supply = <&vcca1v8_codec>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc_18>;
+ gpio1830-supply = <&vcc_io>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vdd1v8_wl>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupts-extended = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k_wifi_bt";
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &pmic_sleep>;
+ system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-suspend-microvolt = <1000000>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-suspend-microvolt = <3300000>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcca1v8_codec: LDO_REG1 {
+ regulator-name = "vcca1v8_codec";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca3v0_codec: LDO_REG2 {
+ regulator-name = "vcca3v0_codec";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-suspend-microvolt = <1000000>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd1v8_wl: LDO_REG4 {
+ regulator-name = "vdd1v8_wl";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-name = "vdd10_lcd";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-suspend-microvolt = <1800000>;
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-name = "vcc18_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_tp: SWITCH_REG1 {
+ regulator-name = "vcc_tp";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_sd: SWITCH_REG2 {
+ regulator-name = "vcc_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ codec@1c {
+ compatible = "realtek,rt5640";
+ reg = <0x1c>;
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_IN1P>;
+ realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_IN1N>;
+ realtek,in1-differential;
+ #sound-dai-cells = <0>;
+
+ port {
+ rt5640_p0_0: endpoint {
+ remote-endpoint = <&i2s_8ch_p0_0>;
+ };
+ };
+ };
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+};
+
+&i2s_8ch {
+ status = "okay";
+
+ i2s_8ch_p0: port {
+ i2s_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&rt5640_p0_0>;
+ };
+ };
+};
+
+&pinctrl {
+ bluetooth {
+ bt_host_wake: bt-host-wake {
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_reg_on: bt-reg-on {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ bt_wake: bt-wake {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ power_led: power-led {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ phy {
+ phy_rst: phy-rst {
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pmic_sleep: pmic-sleep {
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_reg_on: wifi-reg-on {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_det: hp-det {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmu-supply = <&vcc_io>;
+ vop-supply = <&vcc_io>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vdd1v8_wl>;
+ assigned-clocks = <&cru SCLK_SDIO0>;
+ assigned-clock-parents = <&cru PLL_CPLL>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ no-sd;
+ no-mmc;
+ non-removable;
+ sd-uhs-sdr104;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupts-extended = <&gpio3 RK_PA6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_host_wake>;
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_cd>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <1>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ interrupts-extended = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wakeup";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ max-speed = <15000000>;
+ vbat-supply = <&vcc_io>;
+ vddio-supply = <&vdd1v8_wl>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake &bt_wake &bt_reg_on>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ vdd-supply = <&hub_avdd>;
+ };
+};
+
+&usb_otg {
+ vbus-supply = <&vcc_otg>;
+ vusb_a-supply = <&vcc_io>;
+ vusb_d-supply = <&vdd10_usb>;
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts b/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts
index e5709c7..ef754ea 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-pinephone-pro.dts
@@ -12,6 +12,7 @@
/dts-v1/;
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -69,6 +70,34 @@
};
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&red_led_pin &green_led_pin &blue_led_pin>;
+
+ led_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_green: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_blue: led-2 {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ multi-led {
+ compatible = "leds-group-multicolor";
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ leds = <&led_red>, <&led_green>, <&led_blue>;
+ };
+
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -152,6 +181,12 @@
gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
};
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vcc3v3_sys>;
+ };
};
&cpu_alert0 {
@@ -407,6 +442,21 @@
};
};
+&i2c4 {
+ i2c-scl-rising-time-ns = <600>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ /* Accelerometer/gyroscope */
+ mpu6500@68 {
+ compatible = "invensense,mpu6500";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
&cluster0_opp {
opp04 {
status = "disabled";
@@ -481,6 +531,20 @@
};
};
+ leds {
+ red_led_pin: red-led-pin {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ green_led_pin: green-led-pin {
+ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ blue_led_pin: blue-led-pin {
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -563,6 +627,16 @@
mmc-hs200-1_8v;
non-removable;
status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
};
&tsadc {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
index ccbe3a7..d24444c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
@@ -154,6 +154,22 @@
};
};
+&gpio3 {
+ /*
+ * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
+ * eMMC and SPI flash powered-down initially (in fact it keeps the
+ * reset signal asserted). BIOS_DISABLE_OVERRIDE pin allows to override
+ * that signal so that eMMC and SPI can be used regardless of the state
+ * of the signal.
+ */
+ bios-disable-override-hog {
+ gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
+ gpio-hog;
+ line-name = "bios_disable_override";
+ output-high;
+ };
+};
+
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
@@ -409,6 +425,7 @@
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
+ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
@@ -417,8 +434,8 @@
/*
* As Q7 does not specify neither a global nor a RX clock for I2S these
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
- * Therefore we have to redefine the i2s0_2ch_bus definition to prevent
- * conflicts.
+ * Therefore we have to redefine the i2s0_2ch_bus and i2s0_2ch_bus_bclk_off
+ * definitions to prevent conflicts.
*/
&i2s0_2ch_bus {
rockchip,pins =
@@ -428,6 +445,14 @@
<3 RK_PD7 1 &pcfg_pull_none>;
};
+&i2s0_2ch_bus_bclk_off {
+ rockchip,pins =
+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD7 1 &pcfg_pull_none>;
+};
+
&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>;
@@ -449,9 +474,14 @@
&pinctrl {
pinctrl-names = "default";
- pinctrl-0 = <&q7_thermal_pin>;
+ pinctrl-0 = <&q7_thermal_pin &bios_disable_override_hog_pin>;
gpios {
+ bios_disable_override_hog_pin: bios-disable-override-hog-pin {
+ rockchip,pins =
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
q7_thermal_pin: q7-thermal-pin {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399pro.dtsi b/dts/upstream/src/arm64/rockchip/rk3399pro.dtsi
deleted file mode 100644
index bb5ebf6..0000000
--- a/dts/upstream/src/arm64/rockchip/rk3399pro.dtsi
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
-
-#include "rk3399.dtsi"
-
-/ {
- compatible = "rockchip,rk3399pro";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie_phy {
- status = "okay";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie0 {
- ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- num-lanes = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_clkreqn_cpm>;
- status = "okay";
-};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi
index d899087..ae2536c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi
@@ -674,6 +674,7 @@
};
&uart1 {
+ dma-names = "tx", "rx";
pinctrl-0 = <&uart1m0_ctsn>, <&uart1m0_rtsn>, <&uart1m0_xfer>;
pinctrl-names = "default";
uart-has-rtscts;
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
index 0b191d8..37a1303 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
@@ -738,6 +738,7 @@
};
&uart1 {
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts
index b908ce0..13e599a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts
@@ -652,6 +652,7 @@
};
&uart1 {
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts b/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
index 63eea27..67e7801 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
@@ -269,7 +269,7 @@
vcc9-supply = <&vcc3v3_sys>;
codec {
- mic-in-differential;
+ rockchip,mic-in-differential;
};
regulators {
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
index dd4e9c1..e42c474 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
@@ -614,6 +614,7 @@
};
&uart1 {
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
uart-has-rtscts;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3568-evb1-v10.dts
index 19f8fc3..8c3ab07 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-evb1-v10.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-evb1-v10.dts
@@ -475,7 +475,7 @@
};
codec {
- mic-in-differential;
+ rockchip,mic-in-differential;
};
};
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts
index 58ab7e9..b5e6799 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts
@@ -11,6 +11,10 @@
};
};
+&pmu_io_domains {
+ vccio3-supply = <&vccio_sd>;
+};
+
&sdmmc0 {
bus-width = <4>;
cap-mmc-highspeed;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi
index 89e84e3..25c49bd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi
@@ -39,9 +39,9 @@
};
};
- dc_12v: dc-12v-regulator {
+ vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
- regulator-name = "dc_12v";
+ regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
@@ -65,7 +65,7 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
+ vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
@@ -75,18 +75,9 @@
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
+ vin-supply = <&vcc12v_dcin>;
};
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb_host";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -94,8 +85,9 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
- regulator-always-on;
- regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
};
};
@@ -123,6 +115,10 @@
cpu-supply = <&vdd_cpu>;
};
+&display_subsystem {
+ status = "disabled";
+};
+
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -405,8 +401,8 @@
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
@@ -429,28 +425,12 @@
status = "okay";
};
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
&usb_host0_xhci {
dr_mode = "host";
extcon = <&usb2phy0>;
status = "okay";
};
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
&usb_host1_xhci {
status = "okay";
};
@@ -460,7 +440,7 @@
};
&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
+ phy-supply = <&vcc5v0_sys>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts
index e1fe5e4..ce2a5e1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts
@@ -39,7 +39,7 @@
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
- snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@@ -61,7 +61,7 @@
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
- snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@@ -71,18 +71,18 @@
};
&mdio0 {
- rgmii_phy0: ethernet-phy@0 {
+ rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
+ reg = <0x1>;
pinctrl-0 = <ð_phy0_reset_pin>;
pinctrl-names = "default";
};
};
&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
+ rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
+ reg = <0x1>;
pinctrl-0 = <ð_phy1_reset_pin>;
pinctrl-names = "default";
};
@@ -102,6 +102,10 @@
};
};
+&pmu_io_domains {
+ vccio3-supply = <&vcc_3v3>;
+};
+
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts
index ebdedea..59f1403 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts
@@ -531,10 +531,6 @@
};
};
};
-
- codec {
- mic-in-differential;
- };
};
};
diff --git a/dts/upstream/src/arm64/rockchip/rk356x.dtsi b/dts/upstream/src/arm64/rockchip/rk356x.dtsi
index d8543b5..c72b3a6 100644
--- a/dts/upstream/src/arm64/rockchip/rk356x.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk356x.dtsi
@@ -195,32 +195,32 @@
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <850000 850000 1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <850000 850000 1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <850000 850000 1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <825000>;
+ opp-microvolt = <900000 900000 1000000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <950000 950000 1000000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
};
};
@@ -790,6 +790,7 @@
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3568_PD_VO>;
status = "disabled";
};
@@ -1591,10 +1592,9 @@
<&cru SRST_TSADCPHY>;
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&tsadc_pin>;
- pinctrl-1 = <&tsadc_shutorg>;
- pinctrl-2 = <&tsadc_pin>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tsadc_shutorg>;
+ pinctrl-1 = <&tsadc_pin>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
index 98c622b..c667704 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
@@ -673,6 +673,10 @@
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index 78bc9dc..ee99166 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -451,46 +451,8 @@
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
- operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3588_PD_GPU>;
status = "disabled";
-
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <675000 675000 850000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <675000 675000 850000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <675000 675000 850000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <675000 675000 850000>;
- };
- opp-700000000 {
- opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = <700000 700000 850000>;
- };
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <750000 750000 850000>;
- };
- opp-900000000 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = <800000 800000 850000>;
- };
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <850000 850000 850000>;
- };
- };
};
usb_host0_xhci: usb@fc000000 {
@@ -620,14 +582,14 @@
};
vo0_grf: syscon@fd5a6000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
+ compatible = "rockchip,rk3588-vo0-grf", "syscon";
reg = <0x0 0xfd5a6000 0x0 0x2000>;
clocks = <&cru PCLK_VO0GRF>;
};
vo1_grf: syscon@fd5a8000 {
- compatible = "rockchip,rk3588-vo-grf", "syscon";
- reg = <0x0 0xfd5a8000 0x0 0x100>;
+ compatible = "rockchip,rk3588-vo1-grf", "syscon";
+ reg = <0x0 0xfd5a8000 0x0 0x4000>;
clocks = <&cru PCLK_VO1GRF>;
};
@@ -2493,17 +2455,31 @@
};
gpu_thermal: gpu-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsadc 5>;
trips {
+ gpu_alert: gpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
gpu_crit: gpu-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert>;
+ cooling-device =
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
npu_thermal: npu-thermal {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
index 709d348..03fd193 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi
@@ -466,3 +466,7 @@
};
};
};
+
+&tsadc {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
index 7be2190..00f660d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
@@ -878,6 +878,8 @@
vdd_cpu_big1_s0: dcdc-reg1 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -890,6 +892,8 @@
vdd_cpu_big0_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -902,6 +906,8 @@
vdd_cpu_lit_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -926,6 +932,8 @@
vdd_cpu_big1_mem_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -939,6 +947,8 @@
vdd_cpu_big0_mem_s0: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -963,6 +973,8 @@
vdd_cpu_lit_mem_s0: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -1131,6 +1143,10 @@
status = "okay";
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
index 3710176..0ce0934 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
@@ -186,6 +186,41 @@
};
};
+ pcie3x4_ep: pcie-ep@fe150000 {
+ compatible = "rockchip,rk3588-pcie-ep";
+ reg = <0xa 0x40000000 0x0 0x00100000>,
+ <0xa 0x40100000 0x0 0x00100000>,
+ <0x0 0xfe150000 0x0 0x00010000>,
+ <0x9 0x00000000 0x0 0x40000000>,
+ <0xa 0x40300000 0x0 0x00100000>;
+ reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
+ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux", "pipe";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
+ "dma0", "dma1", "dma2", "dma3";
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3588_PD_PCIE>;
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pwr", "pipe";
+ status = "disabled";
+ };
+
pcie3x2: pcie@fe160000 {
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
#address-cells = <3>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts
index 009566d..c2a08bd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts
@@ -261,8 +261,7 @@
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
/* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
+ compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_0_rst>;
@@ -275,8 +274,7 @@
&mdio1 {
rgmii_phy1: ethernet-phy@2 {
/* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
+ compatible = "ethernet-phy-id001c.c916";
reg = <0x2>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_1_rst>;
@@ -376,6 +374,10 @@
status = "okay";
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-opp.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-opp.dtsi
new file mode 100644
index 0000000..0f1a776
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-opp.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <675000 675000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <712500 712500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <762500 762500 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <850000 850000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <675000 675000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <762500 762500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <850000 850000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <925000 925000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <987500 987500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-microvolt = <1000000 1000000 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <675000 675000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <800000 800000 850000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <850000 850000 850000>;
+ };
+ };
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b2 {
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_b3 {
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
index e80caa3..e4a20cd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
@@ -833,6 +833,8 @@
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -846,6 +848,8 @@
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -859,6 +863,8 @@
regulator-name = "vdd_cpu_lit_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
@@ -885,6 +891,8 @@
regulator-name = "vdd_cpu_big1_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big1_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -899,6 +907,8 @@
regulator-name = "vdd_cpu_big0_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_big0_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <12500>;
@@ -925,6 +935,8 @@
regulator-name = "vdd_cpu_lit_mem_s0";
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&vdd_cpu_lit_s0>;
+ regulator-coupled-max-spread = <10000>;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
new file mode 100644
index 0000000..672d748
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
+ * in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * NOTE: If using a setup with two ROCK 5B:s, with one board running in
+ * RC mode and the other board running in EP mode, see also the device
+ * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
+
+&pcie3x4 {
+ status = "disabled";
+};
+
+&pcie3x4_ep {
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-srns.dtso b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-srns.dtso
new file mode 100644
index 0000000..1a0f1af
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-srns.dtso
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex
+ * mode in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * This device tree overlay is only needed (on the RC side) when running
+ * a setup with two ROCK 5B:s, with one board running in RC mode and the
+ * other board running in EP mode.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
index 2e75126..966bbc5 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
@@ -52,7 +52,7 @@
fan: pwm-fan {
compatible = "pwm-fan";
- cooling-levels = <0 95 145 195 255>;
+ cooling-levels = <0 120 150 180 210 240 255>;
fan-supply = <&vcc5v0_sys>;
pwms = <&pwm1 0 50000 0>;
#cooling-cells = <2>;
@@ -65,6 +65,13 @@
shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
};
+ rfkill-bt {
+ compatible = "rfkill-gpio";
+ label = "rfkill-m2-bt";
+ radio-type = "bluetooth";
+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -279,6 +286,36 @@
};
};
+&package_thermal {
+ polling-delay = <1000>;
+
+ trips {
+ package_fan0: package-fan0 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ package_fan1: package-fan1 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&package_fan0>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map2 {
+ trip = <&package_fan1>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&pcie2x1l0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
@@ -410,6 +447,20 @@
pinctrl-names = "default";
pinctrl-0 = <&sdiom0_pins>;
status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim2_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
};
&uart6 {
@@ -743,6 +794,10 @@
};
};
+&tsadc {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts
index 9090c5c..d002152 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts
@@ -648,6 +648,10 @@
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy2 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
index 6b9206c..dbaa94c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
@@ -198,8 +198,7 @@
&mdio1 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
- compatible = "ethernet-phy-id001c.c916",
- "ethernet-phy-ieee802.3-c22";
+ compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
@@ -601,6 +600,10 @@
};
};
+&tsadc {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 0bbeee3..7462cc1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -5,3 +5,4 @@
*/
#include "rk3588-extra.dtsi"
+#include "rk3588-opp.dtsi"
diff --git a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi
index 0bbeee3..bce72ba 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi
@@ -5,3 +5,144 @@
*/
#include "rk3588-extra.dtsi"
+
+/ {
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <887500 887500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <937500 937500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <787500 787500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <875000 875000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <787500 787500 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <875000 875000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <750000 750000 850000>;
+ };
+ opp-850000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <787500 787500 850000>;
+ };
+ };
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_b2 {
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_b3 {
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 3b9a349..03ed482 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -377,6 +377,19 @@
status = "okay";
};
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim0_pins>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
&spi2 {
status = "okay";
assigned-clocks = <&cru CLK_SPI2>;
@@ -699,6 +712,10 @@
};
};
+&tsadc {
+ status = "okay";
+};
+
&u2phy0 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index a379269..c7fecf8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -5,3 +5,4 @@
*/
#include "rk3588-base.dtsi"
+#include "rk3588-opp.dtsi"
diff --git a/dts/upstream/src/arm64/sprd/ums512.dtsi b/dts/upstream/src/arm64/sprd/ums512.dtsi
index dbdb79f..4c080df 100644
--- a/dts/upstream/src/arm64/sprd/ums512.dtsi
+++ b/dts/upstream/src/arm64/sprd/ums512.dtsi
@@ -136,16 +136,22 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
+ };
+
+ pmu-a75 {
+ compatible = "arm,cortex-a75-pmu";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CPU6>, <&CPU7>;
};
soc: soc {
diff --git a/dts/upstream/src/arm64/sprd/ums9620.dtsi b/dts/upstream/src/arm64/sprd/ums9620.dtsi
index 2191f0a..2458071 100644
--- a/dts/upstream/src/arm64/sprd/ums9620.dtsi
+++ b/dts/upstream/src/arm64/sprd/ums9620.dtsi
@@ -144,16 +144,22 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
};
- pmu {
- compatible = "arm,armv8-pmuv3";
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
+ };
+
+ pmu-a76 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
soc: soc {
diff --git a/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi b/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi
index 7a82896..8fdd5f0 100644
--- a/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp25-pinctrl.dtsi
@@ -6,6 +6,65 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ eth2_rgmii_pins_a: eth2-rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins4 {
+ pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ pins5 {
+ pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
+ bias-disable;
+ };
+ };
+
+ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
+ <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
+ };
+ };
+
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */
@@ -128,6 +187,47 @@
<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
};
};
+
+ usart6_pins_a: usart6-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */
+ <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */
+ <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */
+ bias-pull-up;
+ };
+ };
+
+ usart6_idle_pins_a: usart6-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */
+ bias-pull-up;
+ };
+ };
+
+ usart6_sleep_pins_a: usart6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */
+ <STM32_PINMUX('G', 5, ANALOG)>, /* USART6_RTS */
+ <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */
+ <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */
+ };
+ };
};
&pinctrl_z {
diff --git a/dts/upstream/src/arm64/st/stm32mp251.dtsi b/dts/upstream/src/arm64/st/stm32mp251.dtsi
index dcd0656..1167cf6 100644
--- a/dts/upstream/src/arm64/st/stm32mp251.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp251.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
+#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
/ {
#address-cells = <2>;
@@ -20,6 +21,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
};
};
@@ -51,9 +54,11 @@
};
firmware {
- optee {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi {
@@ -71,6 +76,40 @@
reg = <0x16>;
#reset-cells = <1>;
};
+
+ scmi_voltd: protocol@17 {
+ reg = <0x17>;
+
+ scmi_regu: regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_vddio1: regulator@0 {
+ reg = <VOLTD_SCMI_VDDIO1>;
+ regulator-name = "vddio1";
+ };
+ scmi_vddio2: regulator@1 {
+ reg = <VOLTD_SCMI_VDDIO2>;
+ regulator-name = "vddio2";
+ };
+ scmi_vddio3: regulator@2 {
+ reg = <VOLTD_SCMI_VDDIO3>;
+ regulator-name = "vddio3";
+ };
+ scmi_vddio4: regulator@3 {
+ reg = <VOLTD_SCMI_VDDIO4>;
+ regulator-name = "vddio4";
+ };
+ scmi_vdd33ucpd: regulator@5 {
+ reg = <VOLTD_SCMI_UCPD>;
+ regulator-name = "vdd33ucpd";
+ };
+ scmi_vdda18adc: regulator@7 {
+ reg = <VOLTD_SCMI_ADC>;
+ regulator-name = "vdda18adc";
+ };
+ };
+ };
};
};
@@ -88,6 +127,20 @@
psci {
compatible = "arm,psci-1.0";
method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ power-domains = <&RET_PD>;
+ };
+
+ RET_PD: power-domain-retention {
+ #power-domain-cells = <0>;
+ };
};
timer {
@@ -107,6 +160,75 @@
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
+ hpdma: dma-controller@40400000 {
+ compatible = "st,stm32mp25-dma3";
+ reg = <0x40400000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_HPDMA1>;
+ #dma-cells = <3>;
+ };
+
+ hpdma2: dma-controller@40410000 {
+ compatible = "st,stm32mp25-dma3";
+ reg = <0x40410000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_HPDMA2>;
+ #dma-cells = <3>;
+ };
+
+ hpdma3: dma-controller@40420000 {
+ compatible = "st,stm32mp25-dma3";
+ reg = <0x40420000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CK_SCMI_HPDMA3>;
+ #dma-cells = <3>;
+ };
+
rifsc: bus@42080000 {
compatible = "st,stm32mp25-rifsc", "simple-bus";
reg = <0x42080000 0x1000>;
@@ -148,6 +270,33 @@
status = "disabled";
};
+ usart3: serial@400f0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400f0000 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_USART3>;
+ access-controllers = <&rifsc 33>;
+ status = "disabled";
+ };
+
+ uart4: serial@40100000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40100000 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_UART4>;
+ access-controllers = <&rifsc 34>;
+ status = "disabled";
+ };
+
+ uart5: serial@40110000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40110000 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_UART5>;
+ access-controllers = <&rifsc 35>;
+ status = "disabled";
+ };
+
i2c1: i2c@40120000 {
compatible = "st,stm32mp25-i2c";
reg = <0x40120000 0x400>;
@@ -239,6 +388,15 @@
status = "disabled";
};
+ usart6: serial@40220000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40220000 0x400>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_USART6>;
+ access-controllers = <&rifsc 36>;
+ status = "disabled";
+ };
+
spi1: spi@40230000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -275,6 +433,24 @@
status = "disabled";
};
+ uart9: serial@402c0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x402c0000 0x400>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_UART9>;
+ access-controllers = <&rifsc 39>;
+ status = "disabled";
+ };
+
+ usart1: serial@40330000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40330000 0x400>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_USART1>;
+ access-controllers = <&rifsc 31>;
+ status = "disabled";
+ };
+
spi6: spi@40350000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -299,6 +475,24 @@
status = "disabled";
};
+ uart7: serial@40370000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40370000 0x400>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_UART7>;
+ access-controllers = <&rifsc 37>;
+ status = "disabled";
+ };
+
+ uart8: serial@40380000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40380000 0x400>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_UART8>;
+ access-controllers = <&rifsc 38>;
+ status = "disabled";
+ };
+
spi8: spi@46020000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -338,6 +532,55 @@
access-controllers = <&rifsc 76>;
status = "disabled";
};
+
+ ethernet1: ethernet@482c0000 {
+ compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
+ reg = <0x482c0000 0x4000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ptp_ref",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc CK_ETH1_MAC>,
+ <&rcc CK_ETH1_TX>,
+ <&rcc CK_ETH1_RX>,
+ <&rcc CK_KER_ETH1PTP>,
+ <&rcc CK_ETH1_STP>,
+ <&rcc CK_KER_ETH1>;
+ snps,axi-config = <&stmmac_axi_config_1>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&mtl_rx_setup_1>;
+ snps,mtl-tx-config = <&mtl_tx_setup_1>;
+ snps,pbl = <2>;
+ snps,tso;
+ st,syscon = <&syscfg 0x3000>;
+ access-controllers = <&rifsc 60>;
+ status = "disabled";
+
+ mtl_rx_setup_1: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ mtl_tx_setup_1: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ queue0 {};
+ queue1 {};
+ queue2 {};
+ queue3 {};
+ };
+
+ stmmac_axi_config_1: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,wr_osr_lmt = <0x7>;
+ };
+ };
};
bsec: efuse@44000000 {
@@ -441,6 +684,7 @@
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
+ access-controllers = <&rifsc 156>;
};
exti1: interrupt-controller@44220000 {
diff --git a/dts/upstream/src/arm64/st/stm32mp253.dtsi b/dts/upstream/src/arm64/st/stm32mp253.dtsi
index 029f889..eeceb08 100644
--- a/dts/upstream/src/arm64/st/stm32mp253.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp253.dtsi
@@ -12,6 +12,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
};
};
@@ -21,6 +23,13 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
+ psci {
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ };
+ };
+
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -28,3 +37,58 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
+
+&optee {
+ interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
+
+&rifsc {
+ ethernet2: ethernet@482d0000 {
+ compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
+ reg = <0x482d0000 0x4000>;
+ reg-names = "stmmaceth";
+ interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
+ "ptp_ref",
+ "ethstp",
+ "eth-ck";
+ clocks = <&rcc CK_ETH2_MAC>,
+ <&rcc CK_ETH2_TX>,
+ <&rcc CK_ETH2_RX>,
+ <&rcc CK_KER_ETH2PTP>,
+ <&rcc CK_ETH2_STP>,
+ <&rcc CK_KER_ETH2>;
+ snps,axi-config = <&stmmac_axi_config_2>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&mtl_rx_setup_2>;
+ snps,mtl-tx-config = <&mtl_tx_setup_2>;
+ snps,pbl = <2>;
+ snps,tso;
+ st,syscon = <&syscfg 0x3400>;
+ access-controllers = <&rifsc 61>;
+ status = "disabled";
+
+ mtl_rx_setup_2: rx-queues-config {
+ snps,rx-queues-to-use = <2>;
+ queue0 {};
+ queue1 {};
+ };
+
+ mtl_tx_setup_2: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ queue0 {};
+ queue1 {};
+ queue2 {};
+ queue3 {};
+ };
+
+ stmmac_axi_config_2: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,wr_osr_lmt = <0x7>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
index 27b7360..214191a 100644
--- a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
+++ b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
#include "stm32mp257.dtsi"
#include "stm32mp25xf.dtsi"
#include "stm32mp25-pinctrl.dtsi"
@@ -17,7 +18,9 @@
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
aliases {
+ ethernet0 = ðernet2;
serial0 = &usart2;
+ serial1 = &usart6;
};
chosen {
@@ -40,14 +43,6 @@
no-map;
};
};
-
- vdd_sdcard: vdd-sdcard {
- compatible = "regulator-fixed";
- regulator-name = "vdd_sdcard";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
};
&arm_wdt {
@@ -55,6 +50,29 @@
status = "okay";
};
+ðernet2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ð2_rgmii_pins_a>;
+ pinctrl-1 = <ð2_rgmii_sleep_pins_a>;
+ max-speed = <1000>;
+ phy-handle = <&phy0_eth2>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0_eth2: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
@@ -75,6 +93,37 @@
status = "disabled";
};
+&scmi_regu {
+ scmi_vddio1: regulator@0 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ scmi_vddcore: regulator@11 {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK2>;
+ regulator-name = "vddcore";
+ };
+ scmi_v1v8: regulator@14 {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK5>;
+ regulator-name = "v1v8";
+ };
+ scmi_v3v3: regulator@16 {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK7>;
+ regulator-name = "v3v3";
+ };
+ scmi_vdd_emmc: regulator@18 {
+ reg = <VOLTD_SCMI_STPMIC2_LDO2>;
+ regulator-name = "vdd_emmc";
+ };
+ scmi_vdd3v3_usb: regulator@20 {
+ reg = <VOLTD_SCMI_STPMIC2_LDO4>;
+ regulator-name = "vdd3v3_usb";
+ };
+ scmi_vdd_sdcard: regulator@23 {
+ reg = <VOLTD_SCMI_STPMIC2_LDO7>;
+ regulator-name = "vdd_sdcard";
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
@@ -84,7 +133,8 @@
disable-wp;
st,neg-edge;
bus-width = <4>;
- vmmc-supply = <&vdd_sdcard>;
+ vmmc-supply = <&scmi_vdd_sdcard>;
+ vqmmc-supply = <&scmi_vddio1>;
status = "okay";
};
@@ -109,3 +159,12 @@
pinctrl-2 = <&usart2_sleep_pins_a>;
status = "okay";
};
+
+&usart6 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart6_pins_a>;
+ pinctrl-1 = <&usart6_idle_pins_a>;
+ pinctrl-2 = <&usart6_sleep_pins_a>;
+ uart-has-rtscts;
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso b/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso
new file mode 100644
index 0000000..173ac60
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62-lp-sk-nand.dtso
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "k3-pinctrl.h"
+
+&mcasp1 {
+ status = "disabled";
+};
+
+&main_pmx0 {
+ gpmc0_pins_default: gpmc0-pins-default {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
+ AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
+ AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
+ AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
+ AM62X_IOPAD(0x004c, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
+ AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
+ AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
+ AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */
+ AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
+ AM62X_IOPAD(0x00a8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
+ AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
+ AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
+ AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */
+ AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
+ AM62X_IOPAD(0x00a0, PIN_OUTPUT, 0) /* (J20) GPMC0_WPn */
+ >;
+ };
+};
+
+&elm0 {
+ status = "okay";
+};
+
+&gpmc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmc0_pins_default>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nand@0,0 {
+ compatible = "ti,am64-nand";
+ reg = <0 0 64>; /* device IO registers */
+ interrupt-parent = <&gpmc0>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-polled";
+ ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
+ ti,elm-id = <&elm0>;
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <40>;
+ gpmc,cs-wr-off-ns = <40>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <25>;
+ gpmc,adv-wr-off-ns = <25>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <20>;
+ gpmc,oe-on-ns = <3>;
+ gpmc,oe-off-ns = <30>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <40>;
+ gpmc,wr-cycle-ns = <40>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "NAND.tiboot3";
+ reg = <0x00000000 0x00200000>; /* 2M */
+ };
+ partition@200000 {
+ label = "NAND.tispl";
+ reg = <0x00200000 0x00200000>; /* 2M */
+ };
+ partition@400000 {
+ label = "NAND.tiboot3.backup"; /* 2M */
+ reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
+ };
+ partition@600000 {
+ label = "NAND.u-boot";
+ reg = <0x00600000 0x00400000>; /* 4M */
+ };
+ partition@a00000 {
+ label = "NAND.u-boot-env";
+ reg = <0x00a00000 0x00040000>; /* 256K */
+ };
+ partition@a40000 {
+ label = "NAND.u-boot-env.backup";
+ reg = <0x00a40000 0x00040000>; /* 256K */
+ };
+ partition@a80000 {
+ label = "NAND.file-system";
+ reg = <0x00a80000 0x3f580000>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts b/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts
index 9a17bd3..8e9fc00 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62-lp-sk.dts
@@ -228,3 +228,7 @@
&tlv320aic3106 {
DVDD-supply = <&buck2_reg>;
};
+
+&gpmc0 {
+ ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
index 448a59d..328929c 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
@@ -141,8 +141,8 @@
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
@@ -207,10 +207,6 @@
crypto: crypto@40900000 {
compatible = "ti,am62-sa3ul";
reg = <0x00 0x40900000 0x00 0x1200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
-
dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
<&main_pktdma 0x7507 0>;
dma-names = "tx", "rx1", "rx2";
@@ -739,7 +735,7 @@
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
};
cpsw_port2: port@2 {
@@ -1057,4 +1053,33 @@
status = "disabled";
};
+ gpmc0: memory-controller@3b000000 {
+ compatible = "ti,am64-gpmc";
+ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 80 0>;
+ clock-names = "fck";
+ reg = <0x00 0x03b000000 0x00 0x400>,
+ <0x00 0x050000000 0x00 0x8000000>;
+ reg-names = "cfg", "data";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <3>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ elm0: ecc@25010000 {
+ compatible = "ti,am64-elm";
+ reg = <0x00 0x25010000 0x00 0x2000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 54 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
index e8f4d13..9202181 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
@@ -43,15 +43,6 @@
sound-dai = <&mcasp0>;
};
};
-
- reg_usb_hub: regulator-usb-hub {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- regulator-name = "HUB_PWR_EN";
- };
};
/* Verdin ETHs */
@@ -193,11 +184,6 @@
status = "okay";
};
-/* Do not force CTRL_SLEEP_MOCI# always enabled */
-®_force_sleep_moci {
- status = "disabled";
-};
-
/* Verdin SD_1 */
&sdhci1 {
status = "okay";
@@ -218,15 +204,7 @@
};
&usb1 {
- #address-cells = <1>;
- #size-cells = <0>;
status = "okay";
-
- usb-hub@1 {
- compatible = "usb424,2744";
- reg = <1>;
- vdd-supply = <®_usb_hub>;
- };
};
/* Verdin CTRL_WAKE1_MICO# */
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
index 74eec1a..5c1284b 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
@@ -14,6 +14,7 @@
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
@@ -34,7 +35,6 @@
"Line", "Line In";
codec_dai: simple-audio-card,codec {
- clocks = <&audio_refclk1>;
sound-dai = <&nau8822_1a>;
};
@@ -107,6 +107,8 @@
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s1_mclk>;
+ clock-names = "mclk";
+ clocks = <&audio_refclk1>;
#sound-dai-cells = <0>;
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
index 2038c5e..5bef31b 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
@@ -138,12 +138,6 @@
vin-supply = <®_1v8>;
};
- /*
- * By default we enable CTRL_SLEEP_MOCI#, this is required to have
- * peripherals on the carrier board powered.
- * If more granularity or power saving is required this can be disabled
- * in the carrier board device tree files.
- */
reg_force_sleep_moci: regulator-force-sleep-moci {
compatible = "regulator-fixed";
enable-active-high;
@@ -1364,8 +1358,6 @@
0 0 0 0
>;
tdm-slots = <2>;
- rx-num-evt = <32>;
- tx-num-evt = <32>;
#sound-dai-cells = <0>;
status = "disabled";
};
@@ -1382,8 +1374,6 @@
0 0 0 0
>;
tdm-slots = <2>;
- rx-num-evt = <32>;
- tx-num-evt = <32>;
#sound-dai-cells = <0>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62-wakeup.dtsi
index 66ddf2d..e0afafd 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-wakeup.dtsi
@@ -22,6 +22,11 @@
reg = <0x14 0x4>;
};
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
usb0_phy_ctrl: syscon@4008 {
compatible = "ti,am62-usb-phy-ctrl", "syscon";
reg = <0x4008 0x4>;
diff --git a/dts/upstream/src/arm64/ti/k3-am62.dtsi b/dts/upstream/src/arm64/ti/k3-am62.dtsi
index f0781f2..bfb55ca 100644
--- a/dts/upstream/src/arm64/ti/k3-am62.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62.dtsi
@@ -68,11 +68,13 @@
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
index 18e3070..70de288 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
@@ -924,6 +924,4 @@
0 0 0 0
0 0 0 0
>;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso
new file mode 100644
index 0000000..6ec6d57
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&vdd_core {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+};
+
+&a53_opp_table {
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
index 50d2573..4fa5efd 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
@@ -7,477 +7,12 @@
* https://www.phytec.com/product/phyboard-am62x
*/
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am625.dtsi"
#include "k3-am62-phycore-som.dtsi"
+#include "k3-am62x-phyboard-lyra.dtsi"
/ {
compatible = "phytec,am625-phyboard-lyra-rdk",
"phytec,am62-phycore-som", "ti,am625";
model = "PHYTEC phyBOARD-Lyra AM625";
-
- aliases {
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- mmc1 = &sdhci1;
- usb0 = &usb0;
- usb1 = &usb1;
- ethernet1 = &cpsw_port2;
- };
-
- can_tc1: can-phy0 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <8000000>;
- standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
- };
-
- hdmi0: connector-hdmi {
- compatible = "hdmi-connector";
- label = "hdmi";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&sii9022_out>;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
- autorepeat;
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins_default>;
-
- key-home {
- label = "home";
- linux,code = <KEY_HOME>;
- gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- key-menu {
- label = "menu";
- linux,code = <KEY_MENU>;
- gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "phyBOARD-Lyra";
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Headphone", "Headphone Jack",
- "Speaker", "External Speaker";
- simple-audio-card,routing =
- "MIC3R", "Mic Jack",
- "Mic Jack", "Mic Bias",
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "External Speaker", "SPOP",
- "External Speaker", "SPOM";
- simple-audio-card,format = "dsp_b";
- simple-audio-card,bitclock-master = <&sound_master>;
- simple-audio-card,frame-master = <&sound_master>;
- simple-audio-card,bitclock-inversion;
-
- simple-audio-card,cpu {
- sound-dai = <&mcasp2>;
- };
-
- sound_master: simple-audio-card,codec {
- sound-dai = <&audio_codec>;
- clocks = <&audio_refclk1>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
-
- led-1 {
- gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- };
-
- led-2 {
- gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- };
- };
-
- vcc_1v8: regulator-vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_mmc: regulator-vcc-3v3-mmc {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3_MMC";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_sw: regulator-vcc-3v3-sw {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3_SW";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&main_pmx0 {
- audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
- >;
- };
-
- gpio_keys_pins_default: gpio-keys-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
- >;
- };
-
- gpio_exp_int_pins_default: gpio-exp-int-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
- >;
- };
-
- hdmi_int_pins_default: hdmi-int-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
- >;
- };
-
- main_dss0_pins_default: main-dss0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
- AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
- AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
- AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
- AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
- AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
- AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
- AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
- AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
- AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
- AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
- AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
- AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
- AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
- AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
- AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
- AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
- AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
- AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
- AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
- AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
- >;
- };
-
- main_mcan0_pins_default: main-mcan0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
- AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
- >;
- };
-
- main_mcasp2_pins_default: main-mcasp2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */
- AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */
- AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */
- AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */
- >;
- };
-
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
- AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
- AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
- AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
- AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
- AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
- AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
- >;
- };
-
- main_rgmii2_pins_default: main-rgmii2-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
- AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
- AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
- AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
- AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
- AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
- AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
- AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
- AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
- AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
- AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
- AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
- >;
- };
-
- main_usb1_pins_default: main-usb1-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
- >;
- };
-
- user_leds_pins_default: user-leds-default-pins {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
- >;
- };
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy3>;
-};
-
-&cpsw3g_mdio {
- cpsw3g_phy3: ethernet-phy@3 {
- compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&dss {
- pinctrl-names = "default";
- pinctrl-0 = <&main_dss0_pins_default>;
- status = "okay";
-};
-
-&dss_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* VP2: DPI/HDMI Output */
- port@1 {
- reg = <1>;
-
- dpi1_out: endpoint {
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-&main_i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <100000>;
- status = "okay";
-
- audio_codec: audio-codec@18 {
- pinctrl-names = "default";
- pinctrl-0 = <&audio_ext_refclk1_pins_default>;
-
- #sound-dai-cells = <0>;
- compatible = "ti,tlv320aic3007";
- reg = <0x18>;
- ai3x-micbias-vg = <2>;
-
- AVDD-supply = <&vcc_3v3_sw>;
- IOVDD-supply = <&vcc_3v3_sw>;
- DRVDD-supply = <&vcc_3v3_sw>;
- DVDD-supply = <&vcc_1v8>;
- };
-
- gpio_exp: gpio-expander@21 {
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_exp_int_pins_default>;
- compatible = "nxp,pcf8574";
- reg = <0x21>;
- interrupt-parent = <&main_gpio1>;
- interrupts = <49 0>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-line-names = "", "GPIO1_CAN0_nEN",
- "GPIO2_LED2", "GPIO3_LVDS_GPIO",
- "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
- "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
- };
-
- usb-pd@22 {
- compatible = "ti,tps6598x";
- reg = <0x22>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- self-powered;
- data-role = "dual";
- power-role = "sink";
- port {
- usb_con_hs: endpoint {
- remote-endpoint = <&typec_hs>;
- };
- };
- };
- };
-
- sii9022: bridge-hdmi@39 {
- compatible = "sil,sii9022";
- reg = <0x39>;
-
- interrupt-parent = <&main_gpio0>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_int_pins_default>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sii9022_in: endpoint {
- remote-endpoint = <&dpi1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- sii9022_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- pagesize = <16>;
- reg = <0x51>;
- };
-};
-
-&main_mcan0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan0_pins_default>;
- phys = <&can_tc1>;
- status = "okay";
-};
-
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- status = "okay";
-};
-
-&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
- /* Main UART1 may be used by TIFS firmware */
- status = "okay";
-};
-
-&mcasp2 {
- #sound-dai-cells = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcasp2_pins_default>;
-
- /* MCASP_IIS_MODE */
- op-mode = <0>;
- tdm-slots = <2>;
-
- /* 0: INACTIVE, 1: TX, 2: RX */
- serial-dir = <
- 0 0 1 2
- 0 0 0 0
- 0 0 0 0
- 0 0 0 0
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
- status = "okay";
-};
-
-&sdhci1 {
- vmmc-supply = <&vcc_3v3_mmc>;
- vqmmc-supply = <&vddshv5_sdio>;
- pinctrl-names = "default";
- pinctrl-0 = <&main_mmc1_pins_default>;
- disable-wp;
- no-1-8-v;
- status = "okay";
-};
-
-&usbss0 {
- ti,vbus-divider;
- status = "okay";
-};
-
-&usbss1 {
- ti,vbus-divider;
- status = "okay";
-};
-
-&usb0 {
- usb-role-switch;
-
- port {
- typec_hs: endpoint {
- remote-endpoint = <&usb_con_hs>;
- };
- };
-};
-
-&usb1 {
- dr_mode = "host";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb1_pins_default>;
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
index bf9c2d9..916fcf3 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
@@ -59,6 +59,24 @@
reg = <0x4130 0x4>;
#clock-cells = <1>;
};
+
+ audio_refclk0: clock-controller@82e0 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e0 0x4>;
+ clocks = <&k3_clks 157 0>;
+ assigned-clocks = <&k3_clks 157 0>;
+ assigned-clock-parents = <&k3_clks 157 8>;
+ #clock-cells = <0>;
+ };
+
+ audio_refclk1: clock-controller@82e4 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e4 0x4>;
+ clocks = <&k3_clks 157 10>;
+ assigned-clocks = <&k3_clks 157 10>;
+ assigned-clock-parents = <&k3_clks 157 18>;
+ #clock-cells = <0>;
+ };
};
dmss: bus@48000000 {
@@ -120,8 +138,8 @@
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
@@ -216,6 +234,14 @@
};
};
+ crypto: crypto@40900000 {
+ compatible = "ti,am62-sa3ul";
+ reg = <0x00 0x40900000 0x00 0x1200>;
+ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
+ <&main_pktdma 0x7507 0>;
+ dma-names = "tx", "rx1", "rx2";
+ };
+
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
@@ -713,7 +739,7 @@
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&wkup_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
};
cpsw_port2: port@2 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi
new file mode 100644
index 0000000..a5aceaa
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62a-phycore-som.dtsi
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 - 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62a
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "PHYTEC phyCORE-AM62Ax";
+ compatible = "phytec,am62a-phycore-som", "ti,am62a7";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ gpio0 = &main_gpio0;
+ gpio1 = &main_gpio1;
+ i2c0 = &main_i2c0;
+ mmc0 = &sdhci0;
+ rtc0 = &i2c_som_rtc;
+ spi0 = &ospi0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>;
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* global cma region */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00 0x24000000>;
+ alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
+ linux,cma-default;
+ };
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c900000 0x00 0x01e00000>;
+ no-map;
+ };
+ };
+
+ vcc_5v0_som: regulator-vcc-5v0-som {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_5V0_SOM";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&main_pmx0 {
+ leds_pins_default: leds-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x034, PIN_OUTPUT, 7) /* (K20) OSPI0_CSN2.GPIO0_13 */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
+ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+ >;
+ };
+
+ main_mmc0_pins_default: main-mmc0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y6) MMC0_CMD */
+ AM62AX_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB7) MMC0_CLK */
+ AM62AX_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA6) MMC0_DAT0 */
+ AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AB6) MMC0_DAT1 */
+ AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (Y7) MMC0_DAT2 */
+ AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (AA7) MMC0_DAT3 */
+ AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y8) MMC0_DAT4 */
+ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
+ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
+ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+ AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+ AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+ AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+ AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+ AM62AX_IOPAD(0x134, PIN_OUTPUT, 0) /* (Y17) RGMII1_TD0 */
+ AM62AX_IOPAD(0x138, PIN_OUTPUT, 0) /* (V16) RGMII1_TD1 */
+ AM62AX_IOPAD(0x13c, PIN_OUTPUT, 0) /* (Y16) RGMII1_TD2 */
+ AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */
+ AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
+ AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
+ >;
+ };
+
+ ospi0_pins_default: ospi0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */
+ AM62AX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */
+ AM62AX_IOPAD(0x038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */
+ AM62AX_IOPAD(0x00c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */
+ AM62AX_IOPAD(0x010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */
+ AM62AX_IOPAD(0x014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */
+ AM62AX_IOPAD(0x018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */
+ AM62AX_IOPAD(0x01c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */
+ AM62AX_IOPAD(0x020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */
+ AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
+ AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
+ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
+ >;
+ };
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
+ >;
+ };
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&fss {
+ status = "okay";
+};
+
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic@30 {
+ compatible = "ti,tps65219";
+ reg = <0x30>;
+ buck1-supply = <&vcc_5v0_som>;
+ buck2-supply = <&vcc_5v0_som>;
+ buck3-supply = <&vcc_5v0_som>;
+ ldo1-supply = <&vdd_3v3>;
+ ldo2-supply = <&vdd_1v8>;
+ ldo3-supply = <&vcc_5v0_som>;
+ ldo4-supply = <&vcc_5v0_som>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,power-button;
+ system-power-controller;
+
+ regulators {
+ vdd_3v3: buck1 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_1v8: buck2 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_lpddr4: buck3 {
+ regulator-name = "VDD_LPDDR4";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddshv5_sdio: ldo1 {
+ regulator-name = "VDDSHV5_SDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-allow-bypass;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vddr_core: ldo2 {
+ regulator-name = "VDDR_CORE";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdda_1v8: ldo3 {
+ regulator-name = "VDDA_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_2v5: ldo4 {
+ regulator-name = "VDD_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+
+ i2c_som_rtc: rtc@52 {
+ compatible = "microcrystal,rv3028";
+ reg = <0x52>;
+ };
+};
+
+&main_gpio0 {
+ status = "okay";
+};
+
+&main_gpio1 {
+ status = "okay";
+};
+
+&main_gpio_intr {
+ status = "okay";
+};
+
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ospi0_pins_default>;
+ status = "okay";
+
+ serial_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <0>;
+ };
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc0_pins_default>;
+ disable-wp;
+ non-removable;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
index 98043e9..f5ac101 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
@@ -6,9 +6,8 @@
*/
&cbass_wakeup {
- wkup_conf: syscon@43000000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x43000000 0x00 0x20000>;
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
@@ -18,6 +17,11 @@
reg = <0x14 0x4>;
};
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
usb0_phy_ctrl: syscon@4008 {
compatible = "ti,am62-usb-phy-ctrl", "syscon";
reg = <0x4008 0x4>;
@@ -59,7 +63,6 @@
clock-names = "vbus", "osc32k";
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
wakeup-source;
- status = "disabled";
};
wkup_rti0: watchdog@2b000000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62a7-phyboard-lyra-rdk.dts b/dts/upstream/src/arm64/ti/k3-am62a7-phyboard-lyra-rdk.dts
new file mode 100644
index 0000000..3b93409
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62a7-phyboard-lyra-rdk.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 - 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phyboard-am62a
+ */
+
+#include "k3-am62a7.dtsi"
+#include "k3-am62a-phycore-som.dtsi"
+#include "k3-am62x-phyboard-lyra.dtsi"
+
+/ {
+ compatible = "phytec,am62a7-phyboard-lyra-rdk",
+ "phytec,am62a-phycore-som", "ti,am62a7";
+ model = "PHYTEC phyBOARD-Lyra AM62A7";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
index fa43cd0..67faf46 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
@@ -40,6 +40,15 @@
#size-cells = <2>;
ranges;
+ /* global cma region */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00 0x24000000>;
+ alloc-ranges = <0x00 0xc0000000 0x00 0x24000000>;
+ linux,cma-default;
+ };
+
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@@ -701,8 +710,6 @@
0 0 0 0
0 0 0 0
>;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
};
&dss {
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
new file mode 100644
index 0000000..9701fc6
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
@@ -0,0 +1,1062 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@70000000 {
+ compatible = "mmio-sram";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0xc0000>, /* GICR */
+ <0x01 0x00000000 0x00 0x2000>, /* GICC */
+ <0x01 0x00010000 0x00 0x1000>, /* GICH */
+ <0x01 0x00020000 0x00 0x2000>; /* GICV */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ dmss: bus@48000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
+ bootph-all;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ bootph-all;
+ };
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ bootph-all;
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+ bootph-all;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
+ };
+
+ dmss_csi: bus@4e000000 {
+ compatible = "simple-bus";
+ ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ti,sci-dev-id = <198>;
+
+ inta_main_dmss_csi: interrupt-controller@4e400000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x4e400000 0x00 0x8000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <200>;
+ ti,interrupt-ranges = <0 237 8>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
+ };
+
+ main_bcdma_csi: dma-controller@4e230000 {
+ compatible = "ti,am62a-dmss-bcdma-csirx";
+ reg = <0x00 0x4e230000 0x00 0x100>,
+ <0x00 0x4e180000 0x00 0x8000>,
+ <0x00 0x4e100000 0x00 0x10000>;
+ reg-names = "gcfg", "rchanrt", "ringrt";
+ #dma-cells = <3>;
+ msi-parent = <&inta_main_dmss_csi>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <199>;
+ ti,sci-rm-range-rchan = <0x21>;
+ };
+ };
+
+ dmsc: system-controller@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes = <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+ bootph-all;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ bootph-all;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ bootph-all;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ bootph-all;
+ };
+ };
+
+ crypto: crypto@40900000 {
+ compatible = "ti,am62-sa3ul";
+ reg = <0x00 0x40900000 0x00 0x1200>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
+ <&main_pktdma 0x7507 0>;
+ dma-names = "tx", "rx1", "rx2";
+ };
+
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ bootph-all;
+ };
+
+ main_pmx0: pinctrl@f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2ac>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ bootph-all;
+ };
+
+ main_esm: esm@420000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x420000 0x00 0x1000>;
+ ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
+ bootph-pre-ram;
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ bootph-all;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ status = "disabled";
+ };
+
+ main_gpio_intr: interrupt-controller@a00000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <3>;
+ ti,interrupt-ranges = <0 32 16>;
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <190>, <191>, <192>,
+ <193>, <194>, <195>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 77 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio1: gpio@601000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00601000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <180>, <181>, <182>,
+ <183>, <184>, <185>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 78 0>;
+ clock-names = "gpio";
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am64-sdhci-8bit";
+ reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 1>, <&k3_clks 57 2>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 57 2>;
+ assigned-clock-parents = <&k3_clks 57 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,clkbuf-sel = <0x7>;
+ ti,strobe-sel = <0x77>;
+ ti,trm-icp = <0x8>;
+ ti,otap-del-sel-legacy = <0x1>;
+ ti,otap-del-sel-mmc-hs = <0x1>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
+ status = "disabled";
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ status = "disabled";
+ };
+
+ sdhci2: mmc@fa20000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ status = "disabled";
+ };
+
+ usbss0: usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>,
+ <0x00 0x0f908000 0x00 0x400>;
+ clocks = <&k3_clks 161 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,usb2-gadget-lpm-disable;
+ snps,usb2-lpm-disable;
+ };
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0x08000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
+ status = "disabled";
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 13 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster1: mailbox@29010000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29010000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ main_mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan1: can@20711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20711000 0x00 0x200>,
+ <0x00 0x20718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 99 6>, <&k3_clks 99 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&k3_clks 125 0>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 125 0>;
+ assigned-clock-parents = <&k3_clks 125 2>;
+ };
+
+ main_rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&k3_clks 126 0>;
+ power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 126 0>;
+ assigned-clock-parents = <&k3_clks 126 2>;
+ };
+
+ main_rti2: watchdog@e020000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e020000 0x00 0x100>;
+ clocks = <&k3_clks 127 0>;
+ power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 127 0>;
+ assigned-clock-parents = <&k3_clks 127 2>;
+ };
+
+ main_rti3: watchdog@e030000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e030000 0x00 0x100>;
+ clocks = <&k3_clks 128 0>;
+ power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 128 0>;
+ assigned-clock-parents = <&k3_clks 128 2>;
+ };
+
+ main_rti15: watchdog@e0f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e0f0000 0x00 0x100>;
+ clocks = <&k3_clks 130 0>;
+ power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 130 0>;
+ assigned-clock-parents = <&k3_clks 130 2>;
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ mcasp0: audio-controller@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 190 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 190 0>;
+ assigned-clock-parents = <&k3_clks 190 2>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: audio-controller@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 191 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 191 0>;
+ assigned-clock-parents = <&k3_clks 191 2>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: audio-controller@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 192 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 192 0>;
+ assigned-clock-parents = <&k3_clks 192 2>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dmas = <&main_bcdma_csi 0 0x5000 0>;
+ dma-names = "rx0";
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ vpu: video-codec@30210000 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x00 0x30210000 0x00 0x10000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 204 2>;
+ power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi
new file mode 100644
index 0000000..df79451
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the MCU domain peripherals shared by AM62P and J722S
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_pmx0: pinctrl@4084000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0x04084000 0x00 0x88>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ pinctrl-single,gpio-range =
+ <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>,
+ <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>,
+ <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>;
+ bootph-all;
+
+ mcu_pmx_range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ mcu_esm: esm@4100000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x4100000 0x00 0x1000>;
+ ti,esm-pins = <0>, <1>, <2>, <85>;
+ status = "reserved";
+ bootph-pre-ram;
+ };
+
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_uart0: serial@4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ mcu_i2c0: i2c@4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ status = "disabled";
+ };
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x4201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <24>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ gpio-ranges = <&mcu_pmx0 0 0 21>, <&mcu_pmx0 21 23 1>,
+ <&mcu_pmx0 22 32 2>;
+ };
+
+ mcu_rti0: watchdog@4880000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x04880000 0x00 0x100>;
+ clocks = <&k3_clks 131 0>;
+ power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 131 0>;
+ assigned-clock-parents = <&k3_clks 131 2>;
+ /* Tightly coupled to M4F */
+ status = "reserved";
+ };
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ status = "disabled";
+ };
+
+ mcu_r5fss0: r5fss@79000000 {
+ compatible = "ti,am62-r5fss";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x79000000 0x00 0x79000000 0x8000>,
+ <0x79020000 0x00 0x79020000 0x8000>;
+ power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ mcu_r5fss0_core0: r5f@79000000 {
+ compatible = "ti,am62-r5f";
+ reg = <0x79000000 0x00008000>,
+ <0x79020000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <9>;
+ ti,sci-proc-ids = <0x03 0xff>;
+ resets = <&k3_reset 9 1>;
+ firmware-name = "am62p-mcu-r5f0_0-fw";
+ ti,atcm-enable = <0>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <0>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-thermal.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-thermal.dtsi
similarity index 100%
rename from dts/upstream/src/arm64/ti/k3-am62p-thermal.dtsi
rename to dts/upstream/src/arm64/ti/k3-am62p-j722s-common-thermal.dtsi
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi
new file mode 100644
index 0000000..315d009
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x43000000 0x20000>;
+ bootph-all;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ bootph-all;
+ };
+
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
+ usb0_phy_ctrl: syscon@4008 {
+ compatible = "ti,am62-usb-phy-ctrl", "syscon";
+ reg = <0x4008 0x4>;
+ };
+
+ usb1_phy_ctrl: syscon@4018 {
+ compatible = "ti,am62-usb-phy-ctrl", "syscon";
+ reg = <0x4018 0x4>;
+ };
+ };
+
+ wkup_uart0: serial@2b300000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x2b300000 0x00 0x100>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
+ wkup_i2c0: i2c@2b200000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x2b200000 0x00 0x100>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 4>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ wkup_rtc0: rtc@2b1f0000 {
+ compatible = "ti,am62-rtc";
+ reg = <0x00 0x2b1f0000 0x00 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
+ clock-names = "vbus", "osc32k";
+ power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
+ wakeup-source;
+ };
+
+ wkup_rti0: watchdog@2b000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2b000000 0x00 0x100>;
+ clocks = <&k3_clks 132 0>;
+ power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 132 0>;
+ assigned-clock-parents = <&k3_clks 132 2>;
+ /* Used by DM firmware */
+ status = "reserved";
+ };
+
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ wkup_r5fss0: r5fss@78000000 {
+ compatible = "ti,am62-r5fss";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78000000 0x00 0x78000000 0x8000>,
+ <0x78100000 0x00 0x78100000 0x8000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ wkup_r5fss0_core0: r5f@78000000 {
+ compatible = "ti,am62-r5f";
+ reg = <0x78000000 0x00008000>,
+ <0x78100000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <121>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 121 1>;
+ firmware-name = "am62-wkup-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
index 900d1f9..0ce9721 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
@@ -1,666 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Device Tree file for the AM62P main domain peripherals
+ * Device Tree file for the AM62P MAIN domain peripherals
+ *
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x70000000 0x10000>;
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0xc0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- main_conf: bus@100000 {
- compatible = "simple-bus";
- reg = <0x00 0x00100000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x00100000 0x20000>;
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4130 {
- compatible = "ti,am62-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
- };
-
- dmss: bus@48000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
- bootph-all;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- bootph-all;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <5 69 35>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>,
- <0x00 0x48600000 0x00 0x8000>,
- <0x00 0x484a4000 0x00 0x2000>,
- <0x00 0x484c2000 0x00 0x2000>,
- <0x00 0x48420000 0x00 0x2000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "bchan";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- bootph-all;
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
- <0x00 0x485e0000 0x00 0x10000>,
- <0x00 0x484a0000 0x00 0x2000>,
- <0x00 0x484c0000 0x00 0x2000>,
- <0x00 0x48430000 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "ring", "tchan", "rchan", "rflow";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
- bootph-all;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>; /* SAUL_TX_1_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>; /* RING_SAUL_TX_1_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>; /* SAUL_RX_3_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
- };
- };
-
- dmss_csi: bus@4e000000 {
- compatible = "simple-bus";
- ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ti,sci-dev-id = <198>;
-
- inta_main_dmss_csi: interrupt-controller@4e400000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x4e400000 0x00 0x8000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <200>;
- ti,interrupt-ranges = <0 237 8>;
- ti,unmapped-event-sources = <&main_bcdma_csi>;
- };
-
- main_bcdma_csi: dma-controller@4e230000 {
- compatible = "ti,am62a-dmss-bcdma-csirx";
- reg = <0x00 0x4e230000 0x00 0x100>,
- <0x00 0x4e180000 0x00 0x8000>,
- <0x00 0x4e100000 0x00 0x10000>;
- reg-names = "gcfg", "rchanrt", "ringrt";
- #dma-cells = <3>;
- msi-parent = <&inta_main_dmss_csi>;
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <199>;
- ti,sci-rm-range-rchan = <0x21>;
- };
- };
-
- dmsc: system-controller@44043000 {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
- reg-names = "debug_messages";
- reg = <0x00 0x44043000 0x00 0xfe0>;
- bootph-all;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- bootph-all;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- bootph-all;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- bootph-all;
- };
- };
-
- crypto: crypto@40900000 {
- compatible = "ti,am62-sa3ul";
- reg = <0x00 0x40900000 0x00 0x1200>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
-
- dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
- <&main_pktdma 0x7507 0>;
- dma-names = "tx", "rx1", "rx2";
- };
-
- secure_proxy_sa3: mailbox@43600000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x43600000 0x00 0x10000>,
- <0x00 0x44880000 0x00 0x20000>,
- <0x00 0x44860000 0x00 0x20000>;
- /*
- * Marked Disabled:
- * Node is incomplete as it is meant for bootloaders and
- * firmware on non-MPU processors
- */
- status = "disabled";
- bootph-all;
- };
-
- main_pmx0: pinctrl@f4000 {
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2ac>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- bootph-all;
- };
-
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x420000 0x00 0x1000>;
- ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
- bootph-pre-ram;
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 2>;
- assigned-clock-parents = <&k3_clks 36 3>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- bootph-all;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 2>;
- assigned-clock-parents = <&k3_clks 37 3>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 2>;
- assigned-clock-parents = <&k3_clks 38 3>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 2>;
- assigned-clock-parents = <&k3_clks 39 3>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 2>;
- assigned-clock-parents = <&k3_clks 40 3>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 2>;
- assigned-clock-parents = <&k3_clks 41 3>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 2>;
- assigned-clock-parents = <&k3_clks 42 3>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 2>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 2>;
- assigned-clock-parents = <&k3_clks 43 3>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00600000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <92>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x00601000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <52>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am64-sdhci-8bit";
- reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 1>, <&k3_clks 57 2>;
- clock-names = "clk_ahb", "clk_xin";
- assigned-clocks = <&k3_clks 57 2>;
- assigned-clock-parents = <&k3_clks 57 4>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- ti,clkbuf-sel = <0x7>;
- ti,strobe-sel = <0x77>;
- ti,trm-icp = <0x8>;
- ti,otap-del-sel-legacy = <0x1>;
- ti,otap-del-sel-mmc-hs = <0x1>;
- ti,otap-del-sel-ddr52 = <0x6>;
- ti,otap-del-sel-hs200 = <0x8>;
- ti,otap-del-sel-hs400 = <0x5>;
- ti,itap-del-sel-legacy = <0x10>;
- ti,itap-del-sel-mmc-hs = <0xa>;
- ti,itap-del-sel-ddr52 = <0x3>;
- status = "disabled";
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- status = "disabled";
- };
-
- sdhci2: mmc@fa20000 {
- compatible = "ti,am62-sdhci";
- reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
- clock-names = "clk_ahb", "clk_xin";
- bus-width = <4>;
- ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0x0>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,itap-del-sel-legacy = <0x0>;
- ti,itap-del-sel-sd-hs = <0x0>;
- ti,itap-del-sel-sdr12 = <0x0>;
- ti,itap-del-sel-sdr25 = <0x0>;
- status = "disabled";
- };
-
- usbss0: usb@f900000 {
- compatible = "ti,am62-usb";
- reg = <0x00 0x0f900000 0x00 0x800>,
- <0x00 0x0f908000 0x00 0x400>;
- clocks = <&k3_clks 161 3>;
- clock-names = "ref";
- ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
- #address-cells = <2>;
- #size-cells = <2>;
- power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
- ranges;
- status = "disabled";
-
- usb0: usb@31000000 {
- compatible = "snps,dwc3";
- reg = <0x00 0x31000000 0x00 0x50000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
- interrupt-names = "host", "peripheral";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- snps,usb2-gadget-lpm-disable;
- snps,usb2-lpm-disable;
- };
- };
-
usbss1: usb@f910000 {
compatible = "ti,am62-usb";
reg = <0x00 0x0f910000 0x00 0x800>,
@@ -686,408 +31,39 @@
snps,usb2-lpm-disable;
};
};
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 75 7>;
- assigned-clocks = <&k3_clks 75 7>;
- assigned-clock-parents = <&k3_clks 75 8>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x00 0x08000000 0x00 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 3>;
- assigned-clock-parents = <&k3_clks 13 11>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- dmas = <&main_pktdma 0xc600 15>,
- <&main_pktdma 0xc601 15>,
- <&main_pktdma 0xc602 15>,
- <&main_pktdma 0xc603 15>,
- <&main_pktdma 0xc604 15>,
- <&main_pktdma 0xc605 15>,
- <&main_pktdma 0xc606 15>,
- <&main_pktdma 0xc607 15>,
- <&main_pktdma 0x4600 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- status = "disabled";
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- status = "disabled";
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x00 0xf00 0x00 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x00 0x3d000 0x00 0x400>;
- clocks = <&k3_clks 13 3>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
+};
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
+&oc_sram {
+ reg = <0x00 0x70000000 0x00 0x10000>;
+ ranges = <0x00 0x00 0x70000000 0x10000>;
+};
- mailbox0_cluster0: mailbox@29000000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29000000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
+&inta_main_dmss {
+ ti,interrupt-ranges = <5 69 35>;
+};
- mailbox0_cluster1: mailbox@29010000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29010000 0x00 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
+&main_pmx0 {
+ pinctrl-single,gpio-range =
+ <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
- mailbox0_cluster2: mailbox@29020000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29020000 0x00 0x200>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
+ main_pmx0_range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
};
+};
- mailbox0_cluster3: mailbox@29030000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29030000 0x00 0x200>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- };
+&main_gpio0 {
+ gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
+ <&main_pmx0 70 72 22>;
+ ti,ngpio = <92>;
+};
- ecap0: pwm@23100000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23100000 0x00 0x100>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23110000 0x00 0x100>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x00 0x23120000 0x00 0x100>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan1: can@20711000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20711000 0x00 0x200>,
- <0x00 0x20718000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 99 6>, <&k3_clks 99 1>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- main_rti2: watchdog@e020000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e020000 0x00 0x100>;
- clocks = <&k3_clks 127 0>;
- power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 127 0>;
- assigned-clock-parents = <&k3_clks 127 2>;
- };
-
- main_rti3: watchdog@e030000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e030000 0x00 0x100>;
- clocks = <&k3_clks 128 0>;
- power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 128 0>;
- assigned-clock-parents = <&k3_clks 128 2>;
- };
-
- main_rti15: watchdog@e0f0000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x0e0f0000 0x00 0x100>;
- clocks = <&k3_clks 130 0>;
- power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 130 0>;
- assigned-clock-parents = <&k3_clks 130 2>;
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23000000 0x00 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23010000 0x00 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x00 0x23020000 0x00 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- mcasp0: audio-controller@2b00000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b00000 0x00 0x2000>,
- <0x00 0x02b08000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 190 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 190 0>;
- assigned-clock-parents = <&k3_clks 190 2>;
- power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp1: audio-controller@2b10000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b10000 0x00 0x2000>,
- <0x00 0x02b18000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 191 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 191 0>;
- assigned-clock-parents = <&k3_clks 191 2>;
- power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- mcasp2: audio-controller@2b20000 {
- compatible = "ti,am33xx-mcasp-audio";
- reg = <0x00 0x02b20000 0x00 0x2000>,
- <0x00 0x02b28000 0x00 0x400>;
- reg-names = "mpu", "dat";
- interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "tx", "rx";
-
- dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
- dma-names = "tx", "rx";
-
- clocks = <&k3_clks 192 0>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 192 0>;
- assigned-clock-parents = <&k3_clks 192 2>;
- power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- ti_csi2rx0: ticsi2rx@30102000 {
- compatible = "ti,j721e-csi2rx-shim";
- reg = <0x00 0x30102000 0x00 0x1000>;
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
- dmas = <&main_bcdma_csi 0 0x5000 0>;
- dma-names = "rx0";
- power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- cdns_csi2rx0: csi-bridge@30101000 {
- compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
- reg = <0x00 0x30101000 0x00 0x1000>;
- clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
- <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
- clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
- "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
- phys = <&dphy0>;
- phy-names = "dphy";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- csi0_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- csi0_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- csi0_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- csi0_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- csi0_port4: port@4 {
- reg = <4>;
- status = "disabled";
- };
- };
- };
- };
-
- dphy0: phy@30110000 {
- compatible = "cdns,dphy-rx";
- reg = <0x00 0x30110000 0x00 0x1100>;
- #phy-cells = <0>;
- power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
-
- vpu: video-codec@30210000 {
- compatible = "ti,j721s2-wave521c", "cnm,wave521c";
- reg = <0x00 0x30210000 0x00 0x10000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 204 2>;
- power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>;
- };
+&main_gpio1 {
+ gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
+ <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
+ ti,ngpio = <52>;
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-mcu.dtsi
deleted file mode 100644
index b973b55..0000000
--- a/dts/upstream/src/arm64/ti/k3-am62p-mcu.dtsi
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree file for the AM62P MCU domain peripherals
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- mcu_pmx0: pinctrl@4084000 {
- compatible = "pinctrl-single";
- reg = <0x00 0x04084000 0x00 0x88>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- bootph-all;
- };
-
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x4100000 0x00 0x1000>;
- ti,esm-pins = <0>, <1>, <2>, <85>;
- status = "reserved";
- bootph-pre-ram;
- };
-
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 2>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x00 0x4201000 0x00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <24>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- };
-
- mcu_rti0: watchdog@4880000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x04880000 0x00 0x100>;
- clocks = <&k3_clks 131 0>;
- power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 131 0>;
- assigned-clock-parents = <&k3_clks 131 2>;
- /* Tightly coupled to M4F */
- status = "reserved";
- };
-
- mcu_mcan0: can@4e08000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e08000 0x00 0x200>,
- <0x00 0x4e00000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- status = "disabled";
- };
-
- mcu_mcan1: can@4e18000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x4e18000 0x00 0x200>,
- <0x00 0x4e10000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- status = "disabled";
- };
-
- mcu_r5fss0: r5fss@79000000 {
- compatible = "ti,am62-r5fss";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x79000000 0x00 0x79000000 0x8000>,
- <0x79020000 0x00 0x79020000 0x8000>;
- power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- mcu_r5fss0_core0: r5f@79000000 {
- compatible = "ti,am62-r5f";
- reg = <0x79000000 0x00008000>,
- <0x79020000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <9>;
- ti,sci-proc-ids = <0x03 0xff>;
- resets = <&k3_reset 9 1>;
- firmware-name = "am62p-mcu-r5f0_0-fw";
- ti,atcm-enable = <0>;
- ti,btcm-enable = <1>;
- ti,loczrama = <0>;
- };
- };
-};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-wakeup.dtsi
deleted file mode 100644
index c71d962..0000000
--- a/dts/upstream/src/arm64/ti/k3-am62p-wakeup.dtsi
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree file for the AM62P wakeup domain peripherals
- * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_wakeup {
- wkup_conf: bus@43000000 {
- compatible = "simple-bus";
- reg = <0x00 0x43000000 0x00 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00 0x00 0x43000000 0x20000>;
- bootph-all;
-
- chipid: chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x14 0x4>;
- bootph-all;
- };
-
- usb0_phy_ctrl: syscon@4008 {
- compatible = "ti,am62-usb-phy-ctrl", "syscon";
- reg = <0x4008 0x4>;
- };
-
- usb1_phy_ctrl: syscon@4018 {
- compatible = "ti,am62-usb-phy-ctrl", "syscon";
- reg = <0x4018 0x4>;
- };
- };
-
- wkup_uart0: serial@2b300000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x2b300000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- wkup_i2c0: i2c@2b200000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x2b200000 0x00 0x100>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 4>;
- clock-names = "fck";
- status = "disabled";
- };
-
- wkup_rtc0: rtc@2b1f0000 {
- compatible = "ti,am62-rtc";
- reg = <0x00 0x2b1f0000 0x00 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
- clock-names = "vbus", "osc32k";
- power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
- wakeup-source;
- };
-
- wkup_rti0: watchdog@2b000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0x2b000000 0x00 0x100>;
- clocks = <&k3_clks 132 0>;
- power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 132 0>;
- assigned-clock-parents = <&k3_clks 132 2>;
- /* Used by DM firmware */
- status = "reserved";
- };
-
- wkup_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-
- wkup_r5fss0: r5fss@78000000 {
- compatible = "ti,am62-r5fss";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x78000000 0x00 0x78000000 0x8000>,
- <0x78100000 0x00 0x78100000 0x8000>;
- power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
-
- wkup_r5fss0_core0: r5f@78000000 {
- compatible = "ti,am62-r5f";
- reg = <0x78000000 0x00008000>,
- <0x78100000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <121>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 121 1>;
- firmware-name = "am62-wkup-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-};
diff --git a/dts/upstream/src/arm64/ti/k3-am62p.dtsi b/dts/upstream/src/arm64/ti/k3-am62p.dtsi
index 94babc4..75a15c3 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62p.dtsi
@@ -116,10 +116,13 @@
};
};
- #include "k3-am62p-thermal.dtsi"
+ #include "k3-am62p-j722s-common-thermal.dtsi"
};
/* Now include peripherals for each bus segment */
+#include "k3-am62p-j722s-common-main.dtsi"
+#include "k3-am62p-j722s-common-mcu.dtsi"
+#include "k3-am62p-j722s-common-wakeup.dtsi"
+
+/* Include AM62P specific peripherals */
#include "k3-am62p-main.dtsi"
-#include "k3-am62p-mcu.dtsi"
-#include "k3-am62p-wakeup.dtsi"
diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
index 6e72346..ff65955 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
@@ -207,7 +207,7 @@
pinctrl-single,pins = <
AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */
AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */
- AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
+ AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */
AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
@@ -364,14 +364,9 @@
self-powered;
data-role = "dual";
power-role = "sink";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
};
};
};
@@ -516,11 +511,8 @@
&usb0 {
usb-role-switch;
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port {
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
@@ -549,8 +541,6 @@
0 0 0 0
0 0 0 0
>;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
};
&fss {
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
new file mode 100644
index 0000000..e4633af
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ aliases {
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ mmc1 = &sdhci1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ ethernet1 = &cpsw_port2;
+ };
+
+ can_tc1: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <8000000>;
+ standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins_default>;
+
+ key-home {
+ label = "home";
+ linux,code = <KEY_HOME>;
+ gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ key-menu {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "phyBOARD-Lyra";
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "External Speaker";
+ simple-audio-card,routing =
+ "MIC3R", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "External Speaker", "SPOP",
+ "External Speaker", "SPOM";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp2>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&audio_codec>;
+ clocks = <&audio_refclk1>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
+
+ led-1 {
+ gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ led-2 {
+ gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+ };
+
+ vcc_1v8: regulator-vcc-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_mmc: regulator-vcc-3v3-mmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3_MMC";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_3v3_sw: regulator-vcc-3v3-sw {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3_SW";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&main_pmx0 {
+ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
+ >;
+ };
+
+ gpio_keys_pins_default: gpio-keys-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
+ >;
+ };
+
+ gpio_exp_int_pins_default: gpio-exp-int-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
+ >;
+ };
+
+ hdmi_int_pins_default: hdmi-int-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
+ >;
+ };
+
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
+ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
+ >;
+ };
+
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
+ AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
+ >;
+ };
+
+ main_mcasp2_pins_default: main-mcasp2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */
+ AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */
+ AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */
+ AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
+ AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
+ AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
+ AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
+ AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
+ AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
+ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
+ >;
+ };
+
+ main_rgmii2_pins_default: main-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
+ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
+ AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
+ AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
+ AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
+ AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
+ AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
+ AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
+ AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
+ AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
+ AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
+ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
+ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
+ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
+ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
+ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
+ >;
+ };
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ user_leds_pins_default: user-leds-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+ status = "okay";
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VP2: DPI/HDMI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ audio_codec: audio-codec@18 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&audio_ext_refclk1_pins_default>;
+
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3007";
+ reg = <0x18>;
+ ai3x-micbias-vg = <2>;
+
+ AVDD-supply = <&vcc_3v3_sw>;
+ IOVDD-supply = <&vcc_3v3_sw>;
+ DRVDD-supply = <&vcc_3v3_sw>;
+ DVDD-supply = <&vcc_1v8>;
+ };
+
+ gpio_exp: gpio-expander@21 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_exp_int_pins_default>;
+ compatible = "nxp,pcf8574";
+ reg = <0x21>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <49 0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-line-names = "", "GPIO1_CAN0_nEN",
+ "GPIO2_LED2", "GPIO3_LVDS_GPIO",
+ "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
+ "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
+ };
+
+ usb-pd@22 {
+ compatible = "ti,tps6598x";
+ reg = <0x22>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ self-powered;
+ data-role = "dual";
+ power-role = "sink";
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+ };
+
+ sii9022: bridge-hdmi@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_int_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ pagesize = <16>;
+ reg = <0x51>;
+ };
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&can_tc1>;
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ /* Main UART1 may be used by TIFS firmware */
+ status = "okay";
+};
+
+&mcasp2 {
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp2_pins_default>;
+
+ /* MCASP_IIS_MODE */
+ op-mode = <0>;
+ tdm-slots = <2>;
+
+ /* 0: INACTIVE, 1: TX, 2: RX */
+ serial-dir = <
+ 0 0 1 2
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+ status = "okay";
+};
+
+&sdhci1 {
+ vmmc-supply = <&vcc_3v3_mmc>;
+ vqmmc-supply = <&vddshv5_sdio>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ disable-wp;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usbss1 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ usb-role-switch;
+
+ port {
+ typec_hs: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
index 3c45782..44ff67b 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
@@ -48,6 +48,14 @@
pmsg-size = <0x8000>;
};
+ /* global cma region */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x00 0x8000000>;
+ linux,cma-default;
+ };
+
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@@ -128,6 +136,10 @@
};
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-default-pins {
@@ -156,6 +168,7 @@
};
main_i2c1_pins_default: main-i2c1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
@@ -335,15 +348,9 @@
self-powered;
data-role = "dual";
power-role = "sink";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&usb0_hs_ep>;
- };
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
};
};
};
@@ -470,12 +477,9 @@
&usb0 {
bootph-all;
- #address-cells = <1>;
- #size-cells = <0>;
usb-role-switch;
- port@0 {
- reg = <0>;
+ port {
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
@@ -504,8 +508,6 @@
0 0 0 0
0 0 0 0
>;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
};
&dss {
diff --git a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
index 6f9aa5e..f8370dd 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
@@ -1283,6 +1283,9 @@
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-pru0_0-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <16 2 2>;
+ interrupt-names = "vring";
};
rtu0_0: rtu@4000 {
@@ -1292,6 +1295,9 @@
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-rtu0_0-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <20 4 4>;
+ interrupt-names = "vring";
};
tx_pru0_0: txpru@a000 {
@@ -1310,6 +1316,9 @@
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-pru0_1-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <18 3 3>;
+ interrupt-names = "vring";
};
rtu0_1: rtu@6000 {
@@ -1319,6 +1328,9 @@
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-rtu0_1-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <22 5 5>;
+ interrupt-names = "vring";
};
tx_pru0_1: txpru@c000 {
@@ -1436,6 +1448,9 @@
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-pru1_0-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <16 2 2>;
+ interrupt-names = "vring";
};
rtu1_0: rtu@4000 {
@@ -1445,6 +1460,9 @@
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-rtu1_0-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <20 4 4>;
+ interrupt-names = "vring";
};
tx_pru1_0: txpru@a000 {
@@ -1463,6 +1481,9 @@
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-pru1_1-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <18 3 3>;
+ interrupt-names = "vring";
};
rtu1_1: rtu@6000 {
@@ -1472,6 +1493,9 @@
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am64x-rtu1_1-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <22 5 5>;
+ interrupt-names = "vring";
};
tx_pru1_1: txpru@c000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
index 125e507..ea7c58f 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
@@ -265,6 +265,50 @@
interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
+
+ pmic@61 {
+ compatible = "ti,lp8733";
+ reg = <0x61>;
+
+ buck0-in-supply = <&vcc_5v0_som>;
+ buck1-in-supply = <&vcc_5v0_som>;
+ ldo0-in-supply = <&vdd_3v3>;
+ ldo1-in-supply = <&vdd_3v3>;
+
+ regulators {
+ vdd_core: buck0 {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3: buck1 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_ldo0: ldo0 {
+ regulator-name = "VDD_1V8_LDO0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdda_1v8: ldo1 {
+ regulator-name = "VDDA_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
};
&main_r5fss0_core0 {
@@ -296,7 +340,7 @@
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
- flash@0 {
+ serial_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
diff --git a/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso b/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso
index 79ed19c..c452502 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
+ * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
/dts-v1/;
diff --git a/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso b/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso
index 32596a8..82f8a21 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
- * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
+ * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
/dts-v1/;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-evm-icssg1-dualemac-mii.dtso b/dts/upstream/src/arm64/ti/k3-am642-evm-icssg1-dualemac-mii.dtso
new file mode 100644
index 0000000..423d602
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am642-evm-icssg1-dualemac-mii.dtso
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for enabling both ICSSG1 port on AM642 EVM in MII mode
+ *
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mdio_mux>;
+ mdio-parent-bus = <&icssg1_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icssg1_phy2: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ icssg1_mii1_pins_default: icssg1-mii1-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */
+ AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */
+ AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */
+ AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */
+ AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */
+ AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */
+ AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */
+ AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */
+ AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */
+ AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */
+ AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */
+ AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */
+ >;
+ };
+
+ icssg1_mii2_pins_default: icssg1-mii2-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */
+ AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */
+ AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */
+ >;
+ };
+};
+
+&cpsw3g {
+ pinctrl-0 = <&rgmii1_pins_default>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&mdio_mux_1 {
+ status = "disabled";
+};
+
+&icssg1_eth {
+ pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>;
+};
+
+&icssg1_emac0 {
+ phy-mode = "mii";
+};
+
+&icssg1_emac1 {
+ status = "okay";
+ phy-handle = <&icssg1_phy2>;
+ phy-mode = "mii";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am642-evm-nand.dtso b/dts/upstream/src/arm64/ti/k3-am642-evm-nand.dtso
new file mode 100644
index 0000000..f08c0e2
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am642-evm-nand.dtso
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for HSE NAND expansion card on AM642 EVM
+ *
+ * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "k3-pinctrl.h"
+
+&main_pmx0 {
+ gpmc0_pins_default: gpmc0-pins-default {
+ bootph-all;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
+ AM64X_IOPAD(0x003c, PIN_INPUT, 0) /* (T20) GPMC0_AD0 */
+ AM64X_IOPAD(0x0040, PIN_INPUT, 0) /* (U21) GPMC0_AD1 */
+ AM64X_IOPAD(0x0064, PIN_INPUT, 0) /* (R16) GPMC0_AD10 */
+ AM64X_IOPAD(0x0068, PIN_INPUT, 0) /* (W20) GPMC0_AD11 */
+ AM64X_IOPAD(0x006c, PIN_INPUT, 0) /* (W21) GPMC0_AD12 */
+ AM64X_IOPAD(0x0070, PIN_INPUT, 0) /* (V18) GPMC0_AD13 */
+ AM64X_IOPAD(0x0074, PIN_INPUT, 0) /* (Y21) GPMC0_AD14 */
+ AM64X_IOPAD(0x0078, PIN_INPUT, 0) /* (Y20) GPMC0_AD15 */
+ AM64X_IOPAD(0x0044, PIN_INPUT, 0) /* (T18) GPMC0_AD2 */
+ AM64X_IOPAD(0x0048, PIN_INPUT, 0) /* (U20) GPMC0_AD3 */
+ AM64X_IOPAD(0x004c, PIN_INPUT, 0) /* (U18) GPMC0_AD4 */
+ AM64X_IOPAD(0x0050, PIN_INPUT, 0) /* (U19) GPMC0_AD5 */
+ AM64X_IOPAD(0x0054, PIN_INPUT, 0) /* (V20) GPMC0_AD6 */
+ AM64X_IOPAD(0x0058, PIN_INPUT, 0) /* (V21) GPMC0_AD7 */
+ AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */
+ AM64X_IOPAD(0x0060, PIN_INPUT, 0) /* (T17) GPMC0_AD9 */
+ AM64X_IOPAD(0x0098, PIN_INPUT_PULLUP, 0) /* (W19) GPMC0_WAIT0 */
+ AM64X_IOPAD(0x009c, PIN_INPUT_PULLUP, 0) /* (Y18) GPMC0_WAIT1 */
+ AM64X_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (R19) GPMC0_CSn0 */
+ AM64X_IOPAD(0x00ac, PIN_OUTPUT_PULLUP, 0) /* (R20) GPMC0_CSn1 */
+ AM64X_IOPAD(0x00b0, PIN_OUTPUT_PULLUP, 0) /* (P19) GPMC0_CSn2 */
+ AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 0) /* (R21) GPMC0_CSn3 */
+ AM64X_IOPAD(0x007c, PIN_OUTPUT, 0) /* (R17) GPMC0_CLK */
+ AM64X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (P16) GPMC0_ADVn_ALE */
+ AM64X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (R18) GPMC0_OEn_REn */
+ AM64X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (T21) GPMC0_WEn */
+ AM64X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (P17) GPMC0_BE0n_CLE */
+ AM64X_IOPAD(0x00a0, PIN_OUTPUT_PULLUP, 0) /* (N16) GPMC0_WPn */
+ AM64X_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (N17) GPMC0_DIR */
+ >;
+ };
+};
+
+&main_gpio0 {
+ gpio0-36 {
+ bootph-all;
+ gpio-hog;
+ gpios = <36 0>;
+ input;
+ line-name = "GPMC0_MUX_DIR";
+ };
+};
+
+&elm0 {
+ bootph-all;
+ status = "okay";
+};
+
+&gpmc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmc0_pins_default>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nand@0,0 {
+ compatible = "ti,am64-nand";
+ reg = <0 0 64>; /* device IO registers */
+ interrupt-parent = <&gpmc0>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+ ti,nand-xfer-type = "prefetch-polled";
+ ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
+ ti,elm-id = <&elm0>;
+ nand-bus-width = <8>;
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <40>;
+ gpmc,cs-wr-off-ns = <40>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <25>;
+ gpmc,adv-wr-off-ns = <25>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <20>;
+ gpmc,oe-on-ns = <3>;
+ gpmc,oe-off-ns = <30>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <40>;
+ gpmc,wr-cycle-ns = <40>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wr-access-ns = <40>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ bootph-all;
+ label = "NAND.tiboot3";
+ reg = <0x00000000 0x00200000>; /* 2M */
+ };
+ partition@200000 {
+ bootph-all;
+ label = "NAND.tispl";
+ reg = <0x00200000 0x00200000>; /* 2M */
+ };
+ partition@400000 {
+ bootph-all;
+ label = "NAND.tiboot3.backup"; /* 2M */
+ reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
+ };
+ partition@600000 {
+ bootph-all;
+ label = "NAND.u-boot";
+ reg = <0x00600000 0x00400000>; /* 4M */
+ };
+ partition@a00000 {
+ bootph-all;
+ label = "NAND.u-boot-env";
+ reg = <0x00a00000 0x00040000>; /* 256K */
+ };
+ partition@a40000 {
+ bootph-all;
+ label = "NAND.u-boot-env.backup";
+ reg = <0x00a40000 0x00040000>; /* 256K */
+ };
+ partition@a80000 {
+ bootph-all;
+ label = "NAND.file-system";
+ reg = <0x00a80000 0x3f580000>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am642-evm.dts b/dts/upstream/src/arm64/ti/k3-am642-evm.dts
index e20e4ff..6bb1ad2 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-evm.dts
@@ -466,6 +466,12 @@
AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */
>;
};
+
+ icssg1_iep0_pins_default: icssg1-iep0-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
+ >;
+ };
};
&main_uart0 {
@@ -817,3 +823,12 @@
rx-internal-delay-ps = <2000>;
};
};
+
+&gpmc0 {
+ ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */
+};
+
+&icssg1_iep0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg1_iep0_pins_default>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t.dts b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t.dts
index 234d76e..5b5e9ee 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t.dts
@@ -282,7 +282,6 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart3_default_pins>;
uart-has-rtscts;
- rs485-rts-active-low;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-pcie-usb2.dtso b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-pcie-usb2.dtso
new file mode 100644
index 0000000..7a5ce4b
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-pcie-usb2.dtso
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * DT overlay for PCIe support (limits USB to 2.0/high-speed)
+ *
+ * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
+ * Author: Matt McKee <mmckee@phytec.com>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+#include "k3-pinctrl.h"
+#include "k3-serdes.h"
+
+&{/} {
+ pcie_refclk0: pcie-refclk0 {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_usb_sel_pins_default>;
+ clocks = <&serdes_refclk>;
+ #clock-cells = <0>;
+ enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&main_pmx0 {
+ pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
+ >;
+ };
+
+ pcie_pins_default: pcie-default-pins {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
+ >;
+ };
+};
+
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins_default>;
+ reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_usb_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "okay";
+};
+
+&serdes0_pcie_usb_link {
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+/*
+ * Assign pcie_refclk0 to serdes_wiz0 as ext_ref_clk.
+ * This makes sure that the clock generator gets enabled at the right time.
+ */
+&serdes_wiz0 {
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&pcie_refclk0>;
+};
+
+&usbss0 {
+ ti,usb2-only;
+};
+
+&usb0 {
+ maximum-speed = "high-speed";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
index 6df331c..30729b4 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
@@ -190,18 +190,6 @@
>;
};
- pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
- >;
- };
-
- pcie0_pins_default: pcie0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
- >;
- };
-
user_leds_pins_default: user-leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
diff --git a/dts/upstream/src/arm64/ti/k3-am642-sk.dts b/dts/upstream/src/arm64/ti/k3-am642-sk.dts
index 5b028b3..44ecbcf 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-sk.dts
@@ -430,6 +430,18 @@
#gpio-cells = <2>;
gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
};
+
+ /* SoC power supply temperature */
+ tmp100@48 {
+ compatible = "ti,tmp100";
+ reg = <0x48>;
+ };
+
+ /* DDR power supply temperature */
+ tmp100@49 {
+ compatible = "ti,tmp100";
+ reg = <0x49>;
+ };
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index 1f4dc5a..c40ad67 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -1,7 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
+ * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
/dts-v1/;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
index 6c785ef..828d815 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
@@ -1,7 +1,7 @@
-// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
+ * Copyright (c) 2022-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany.
*/
#include "k3-am642.dtsi"
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
index ef78977..0a29ed1 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
@@ -73,3 +73,15 @@
"rx0", "rx1",
"rxmgm0", "rxmgm1";
};
+
+&icssg0_iep0 {
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <7 7 7>;
+ interrupt-names = "iep_cap_cmp";
+};
+
+&icssg0_iep1 {
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <56 8 8>;
+ interrupt-names = "iep_cap_cmp";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am65-main.dtsi b/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
index ed71561..1af3ded 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
@@ -1185,6 +1185,9 @@
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru0_0-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <16 2 2>;
+ interrupt-names = "vring";
};
rtu0_0: rtu@4000 {
@@ -1194,6 +1197,9 @@
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu0_0-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <20 4 4>;
+ interrupt-names = "vring";
};
tx_pru0_0: txpru@a000 {
@@ -1212,6 +1218,9 @@
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru0_1-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <18 3 3>;
+ interrupt-names = "vring";
};
rtu0_1: rtu@6000 {
@@ -1221,6 +1230,9 @@
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu0_1-fw";
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <22 5 5>;
+ interrupt-names = "vring";
};
tx_pru0_1: txpru@c000 {
@@ -1339,6 +1351,9 @@
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru1_0-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <16 2 2>;
+ interrupt-names = "vring";
};
rtu1_0: rtu@4000 {
@@ -1348,6 +1363,9 @@
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu1_0-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <20 4 4>;
+ interrupt-names = "vring";
};
tx_pru1_0: txpru@a000 {
@@ -1366,6 +1384,9 @@
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru1_1-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <18 3 3>;
+ interrupt-names = "vring";
};
rtu1_1: rtu@6000 {
@@ -1375,6 +1396,9 @@
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu1_1-fw";
+ interrupt-parent = <&icssg1_intc>;
+ interrupts = <22 5 5>;
+ interrupt-names = "vring";
};
tx_pru1_1: txpru@c000 {
@@ -1493,6 +1517,9 @@
<0x22400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru2_0-fw";
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <16 2 2>;
+ interrupt-names = "vring";
};
rtu2_0: rtu@4000 {
@@ -1502,6 +1529,9 @@
<0x23400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu2_0-fw";
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <20 4 4>;
+ interrupt-names = "vring";
};
tx_pru2_0: txpru@a000 {
@@ -1520,6 +1550,9 @@
<0x24400 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-pru2_1-fw";
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <18 3 3>;
+ interrupt-names = "vring";
};
rtu2_1: rtu@6000 {
@@ -1529,6 +1562,9 @@
<0x23c00 0x100>;
reg-names = "iram", "control", "debug";
firmware-name = "am65x-rtu2_1-fw";
+ interrupt-parent = <&icssg2_intc>;
+ interrupts = <22 5 5>;
+ interrupt-names = "vring";
};
tx_pru2_1: txpru@c000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
index 8feab93..43c6118 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
@@ -6,13 +6,17 @@
*/
&cbass_mcu {
- mcu_conf: scm-conf@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
+ mcu_conf: bus@40f00000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
@@ -358,7 +362,7 @@
reg = <1>;
ti,mac-only;
label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
phys = <&phy_gmii_sel 1>;
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
index aba0c52..aa7139c 100644
--- a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
@@ -33,6 +33,7 @@
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
index d743f02..90dbe31 100644
--- a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
@@ -414,6 +414,82 @@
pinctrl-0 = <&wkup_uart0_pins_default>;
};
+&wkup_i2c0 {
+ bootph-all;
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ status = "okay";
+
+ lp8733: pmic@60 {
+ compatible = "ti,lp8733";
+ reg = <0x60>;
+ buck0-in-supply = <&vsys_3v3>;
+ buck1-in-supply = <&vsys_3v3>;
+ ldo0-in-supply = <&vsys_3v3>;
+ ldo1-in-supply = <&vsys_3v3>;
+
+ lp8733_regulators: regulators {
+ lp8733_buck0_reg: buck0 {
+ /* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */
+ regulator-name = "lp8733-buck0";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_buck1_reg: buck1 {
+ /* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */
+ regulator-name = "lp8733-buck1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lp8733_ldo0_reg: ldo0 {
+ /* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */
+ regulator-name = "lp8733-ldo0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lp8733_ldo1_reg: ldo1 {
+ /* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */
+ regulator-name = "lp8733-ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps62873a: regulator@40 {
+ compatible = "ti,tps62873";
+ reg = <0x40>;
+ bootph-pre-ram;
+ regulator-name = "VDD_CPU_AVS";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ tps62873b: regulator@43 {
+ compatible = "ti,tps62873";
+ reg = <0x43>;
+ regulator-name = "VDD_CORE_0V8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-som.dtsi b/dts/upstream/src/arm64/ti/k3-am68-sk-som.dtsi
index 0f4a5da..5c66e0e 100644
--- a/dts/upstream/src/arm64/ti/k3-am68-sk-som.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am68-sk-som.dtsi
@@ -11,9 +11,10 @@
/ {
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 16 GB RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x03 0x80000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000003 0x80000000>;
};
reserved_memory: reserved-memory {
@@ -130,6 +131,25 @@
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins {
+ bootph-all;
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ >;
+ };
+};
+
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
@@ -152,6 +172,68 @@
};
};
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+
+ partitions {
+ bootph-all;
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x40000>;
+ };
+
+ partition@740000 {
+ label = "ospi.env.backup";
+ reg = <0x740000 0x40000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fc0000 {
+ bootph-pre-ram;
+ label = "ospi.phypattern";
+ reg = <0x3fc0000 0x40000>;
+ };
+ };
+ };
+};
+
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk.dts b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
index d88651c..3f65585 100644
--- a/dts/upstream/src/arm64/ti/k3-am69-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
@@ -35,8 +35,8 @@
device_type = "memory";
bootph-all;
/* 32G RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x07 0x80000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000007 0x80000000>;
};
reserved_memory: reserved-memory {
@@ -814,6 +814,27 @@
};
};
};
+
+ tps62873a: regulator@40 {
+ compatible = "ti,tps62873";
+ reg = <0x40>;
+ bootph-pre-ram;
+ regulator-name = "VDD_CPU_AVS";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ tps62873b: regulator@43 {
+ compatible = "ti,tps62873";
+ reg = <0x43>;
+ regulator-name = "VDD_CORE_0V8";
+ regulator-min-microvolt = <760000>;
+ regulator-max-microvolt = <840000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&wkup_gpio0 {
@@ -1203,3 +1224,65 @@
};
};
};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>;
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&serdes0 {
+ status = "okay";
+
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <3>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
+ };
+};
+
+&serdes_wiz1 {
+ status = "okay";
+};
+
+&serdes1 {
+ status = "okay";
+
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>;
+ };
+};
+
+&pcie0_rc {
+ status = "okay";
+ reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+};
+
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie3_rc {
+ status = "okay";
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtso b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtso
new file mode 100644
index 0000000..356c82b
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtso
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&cpsw3g_phy1 {
+ status = "disabled";
+};
+
+&cpsw_port1 {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtso b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtso
new file mode 100644
index 0000000..8b24191
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&i2c_som_rtc {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtso b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtso
new file mode 100644
index 0000000..cc0cf26
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2023 PHYTEC America, LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Copyright (C) 2024 PHYTEC America, LLC
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&serial_flash {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtso b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtso
new file mode 100644
index 0000000..969dfeb
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtso
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Nathan Morrisson <nmorrisson@phytec.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "k3-pinctrl.h"
+
+&serial_flash {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index fccaabf..5097d19 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -164,12 +164,16 @@
ti,timer-pwm;
};
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x00 0x40f00000 0x00 0x20000>;
+ mcu_conf: bus@40f00000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x00 0x00 0x40f00000 0x20000>;
+ ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
@@ -420,7 +424,7 @@
reg = <1>;
ti,mac-only;
label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
phys = <&phy_gmii_sel 1>;
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
index 7e6a584..21fe194 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
@@ -12,9 +12,10 @@
/ {
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 4G RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x00 0x80000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board-infotainment.dtso b/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board-infotainment.dtso
new file mode 100644
index 0000000..65a7e54
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j721e-common-proc-board-infotainment.dtso
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Infotainment Expansion Board for j721e-evm
+ * User Guide: <https://www.ti.com/lit/ug/spruit0a/spruit0a.pdf>
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ ddc-i2c-bus = <&main_i2c1>;
+ digital;
+ /* P12 - HDMI_HPD */
+ hpd-gpios = <&exp6 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-bridge {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,tfp410";
+ /* P10 - HDMI_PDn */
+ powerdown-gpios = <&exp6 8 GPIO_ACTIVE_LOW>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&dpi_out0>;
+ pclk-sample = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint =
+ <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ main_i2c1_exp6_pins_default: main-i2c1-exp6-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */
+ >;
+ };
+
+ dss_vout0_pins_default: dss-vout0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
+ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
+ J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
+ J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
+ J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
+ J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
+ J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
+ J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
+ J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
+ J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
+ J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
+ J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
+ J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
+ J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
+ J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
+ J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
+ J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
+ J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
+ J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
+ J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
+ J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
+ J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
+ J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
+ J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
+ J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
+ J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
+ J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
+ J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
+ >;
+ };
+};
+
+&exp1 {
+ p14-hog {
+ /* P14 - VINOUT_MUX_SEL0 */
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "VINOUT_MUX_SEL0";
+ };
+
+ p15-hog {
+ /* P15 - VINOUT_MUX_SEL1 */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "VINOUT_MUX_SEL1";
+ };
+};
+
+&main_i2c1 {
+ /* i2c1 is used for DVI DDC, so we need to use 100kHz */
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ exp6: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_exp6_pins_default>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ p11-hog {
+ /* P11 - HDMI_DDC_OE */
+ gpio-hog;
+ gpios = <9 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "HDMI_DDC_OE";
+ };
+ };
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dss_vout0_pins_default>;
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ dpi_out0: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
index 9349ae0..6b6ef6a 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
@@ -34,13 +34,17 @@
};
};
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
+ mcu_conf: bus@40f00000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
@@ -546,7 +550,7 @@
reg = <1>;
ti,mac-only;
label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
phys = <&phy_gmii_sel 1>;
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
index 0c4575a..89fbfb2 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
@@ -31,6 +31,7 @@
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
@@ -210,6 +211,42 @@
<3300000 0x1>;
};
+ transceiver1: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy2 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 65 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 66 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver4: can-phy4 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan9_gpio_pins_default>;
+ standby-gpios = <&main_gpio0 67 GPIO_ACTIVE_HIGH>;
+ };
+
dp_pwr_3v3: fixedregulator-dp-prw {
compatible = "regulator-fixed";
regulator-name = "dp-pwr";
@@ -367,6 +404,45 @@
>;
};
+ main_mcan0_pins_default: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
+ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
+ >;
+ };
+
+ main_mcan0_gpio_pins_default: main-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
+ >;
+ };
+
+ main_mcan5_pins_default: main-mcan5-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) PRG1_PRU0_GPO18.MCAN5_RX */
+ J721E_IOPAD(0x04c, PIN_OUTPUT, 6) /* (AJ21) PRG1_PRU0_GPO17.MCAN5_TX */
+ >;
+ };
+
+ main_mcan5_gpio_pins_default: main-mcan5-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x10c, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
+ >;
+ };
+
+ main_mcan9_pins_default: main-mcan9-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x0d0, PIN_INPUT, 6) /* (AC27) PRG0_PRU0_GPO8.MCAN9_RX */
+ J721E_IOPAD(0x0cc, PIN_OUTPUT, 6) /* (AC28) PRG0_PRU0_GPO7.MCAN9_TX */
+ >;
+ };
+
+ main_mcan9_gpio_pins_default: main-mcan9-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
+ >;
+ };
+
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
@@ -555,6 +631,19 @@
>;
};
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0ac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
+ J721E_WKUP_IOPAD(0x0a8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0bc, PIN_INPUT, 7) /* (F27) WKUP_GPIO0_3 */
+ >;
+ };
+
/* Reset for M.2 M Key slot on PCIe1 */
mkey_reset_pins_default: mkey-reset-pns-default-pins {
pinctrl-single,pins = <
@@ -1108,6 +1197,34 @@
num-lanes = <2>;
};
+&mcu_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver1>;
+ status = "okay";
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan0_pins_default>;
+ phys = <&transceiver2>;
+ status = "okay";
+};
+
+&main_mcan5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan5_pins_default>;
+ phys = <&transceiver3>;
+ status = "okay";
+};
+
+&main_mcan9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan9_pins_default>;
+ phys = <&transceiver4>;
+ status = "okay";
+};
+
&ufs_wrapper {
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
index 1fae649..5ba9477 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
@@ -12,6 +12,7 @@
/ {
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
index 5ccb04c..8feb42c 100644
--- a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -139,13 +139,17 @@
ti,interrupt-ranges = <16 960 16>;
};
- mcu_conf: syscon@40f00000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x40f00000 0x0 0x20000>;
+ mcu_conf: bus@40f00000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x40f00000 0x20000>;
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
+
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4040 0x4>;
@@ -544,7 +548,7 @@
reg = <1>;
ti,mac-only;
label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
phys = <&phy_gmii_sel 1>;
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
index 623c842..82aacc0 100644
--- a/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
@@ -13,9 +13,10 @@
/ {
memory@80000000 {
device_type = "memory";
+ bootph-all;
/* 16 GB RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x03 0x80000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000003 0x80000000>;
};
/* Reserving memory regions still pending */
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
index bf3c246..dd3b5f7 100644
--- a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
/ {
compatible = "ti,j722s-evm", "ti,j722s";
@@ -105,6 +107,15 @@
<3300000 0x1>;
};
+ vsys_io_3v3: regulator-vsys-io-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_io_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vsys_io_1v8: regulator-vsys-io-1v8 {
compatible = "regulator-fixed";
regulator-name = "vsys_io_1v8";
@@ -122,6 +133,35 @@
regulator-always-on;
regulator-boot-on;
};
+
+ codec_audio: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "J722S-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&audio_refclk1>;
+ };
+ };
};
&main_pmx0 {
@@ -202,6 +242,27 @@
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */
+ J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */
+ J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ >;
+ };
+
+ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
+ >;
+ };
};
&cpsw3g {
@@ -277,6 +338,12 @@
bootph-all;
};
+&k3_clks {
+ /* Configure AUDIO_EXT_REFCLK1 pin as output */
+ pinctrl-names = "default";
+ pinctrl-0 = <&audio_ext_refclk1_pins_default>;
+};
+
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
@@ -301,6 +368,48 @@
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+ p05-hog {
+ /* P05 - USB2.0_MUX_SEL */
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+
+ p01_hog: p01-hog {
+ /* P01 - TRC_MUX_SEL */
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "TRC_MUX_SEL";
+ };
+
+ p02_hog: p02-hog {
+ /* P02 - MCASP1_FET_SEL */
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MCASP1_FET_SEL";
+ };
+
+ p13_hog: p13-hog {
+ /* P13 - GPIO_AUD_RSTn */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "GPIO_AUD_RSTn";
+ };
+ };
+
+ tlv320aic3106: audio-codec@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+ AVDD-supply = <&vsys_io_3v3>;
+ IOVDD-supply = <&vsys_io_3v3>;
+ DRVDD-supply = <&vsys_io_3v3>;
+ DVDD-supply = <&vsys_io_1v8>;
};
};
@@ -384,3 +493,76 @@
status = "okay";
bootph-all;
};
+
+&serdes_ln_ctrl {
+ idle-states = <J722S_SERDES0_LANE0_USB>,
+ <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ status = "okay";
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi b/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi
new file mode 100644
index 0000000..dde4bd5
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j722s-main.dtsi
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S MAIN domain peripherals
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clk-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+};
+
+&cbass_main {
+ serdes_wiz0: phy@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ serdes_wiz1: phy@f010000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 280 1>;
+ assigned-clock-parents = <&k3_clks 280 5>;
+
+ serdes1: serdes@f010000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f010000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 280 1>,
+ <&k3_clks 280 1>,
+ <&k3_clks 280 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ max-link-speed = <3>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ cdns,no-bar-match-nbits = <64>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ status = "disabled";
+ };
+
+ usbss1: usb@f920000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x0f920000 0x00 0x100>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31200000{
+ compatible = "cdns,usb3";
+ reg = <0x00 0x31200000 0x00 0x10000>,
+ <0x00 0x31210000 0x00 0x10000>,
+ <0x00 0x31220000 0x00 0x10000>;
+ reg-names = "otg",
+ "xhci",
+ "dev";
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+};
+
+&main_conf {
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x14>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
+ <0x10 0x3>; /* SERDES1 lane0 select */
+ };
+
+ audio_refclk1: clock@82e4 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e4 0x4>;
+ clocks = <&k3_clks 157 18>;
+ assigned-clocks = <&k3_clks 157 18>;
+ assigned-clock-parents = <&k3_clks 157 33>;
+ #clock-cells = <0>;
+ };
+};
+
+&wkup_conf {
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+};
+
+&oc_sram {
+ reg = <0x00 0x70000000 0x00 0x40000>;
+ ranges = <0x00 0x00 0x70000000 0x40000>;
+};
+
+&inta_main_dmss {
+ ti,interrupt-ranges = <7 71 21>;
+};
+
+&main_pmx0 {
+ pinctrl-single,gpio-range =
+ <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
+ <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
+
+ main_pmx0_range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+};
+
+&main_gpio0 {
+ gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
+ <&main_pmx0 70 72 17>;
+ ti,ngpio = <87>;
+};
+
+&main_gpio1 {
+ gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
+ <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
+ ti,ngpio = <73>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j722s.dtsi b/dts/upstream/src/arm64/ti/k3-j722s.dtsi
index c75744e..14c6c6a 100644
--- a/dts/upstream/src/arm64/ti/k3-j722s.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j722s.dtsi
@@ -10,11 +10,133 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
-#include "k3-am62p5.dtsi"
+#include "k3-pinctrl.h"
/ {
model = "Texas Instruments K3 J722S SoC";
compatible = "ti,j722s";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 135 0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 136 0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 137 0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 138 0>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
cbass_main: bus@f0000 {
compatible = "simple-bus";
@@ -74,16 +196,39 @@
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
- };
-};
-/* Main domain overrides */
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */
+ <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
+ <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
+ <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */
+ <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */
+ bootph-all;
+ };
-&inta_main_dmss {
- ti,interrupt-ranges = <7 71 21>;
-};
+ cbass_wakeup: bus@b00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
+ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
+ bootph-all;
+ };
+ };
-&oc_sram {
- reg = <0x00 0x70000000 0x00 0x40000>;
- ranges = <0x00 0x00 0x70000000 0x40000>;
+ #include "k3-am62p-j722s-common-thermal.dtsi"
};
+
+/* Include peripherals shared with AM62P */
+#include "k3-am62p-j722s-common-main.dtsi"
+#include "k3-am62p-j722s-common-mcu.dtsi"
+#include "k3-am62p-j722s-common-wakeup.dtsi"
+
+/* Include J722S specific peripherals */
+#include "k3-j722s-main.dtsi"
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
new file mode 100644
index 0000000..6853050
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration
+ * on J784S4 EVM.
+ *
+ * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie1_rc {
+ status = "disabled";
+};
+
+&cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+
+ pcie0_ep: pcie-ep@2900000 {
+ compatible = "ti,j784s4-pcie-ep";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 332 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes1_pcie0_link>;
+ phy-names = "pcie-phy";
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j784s4-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 333 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes0_pcie1_link>;
+ phy-names = "pcie-phy";
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/dts/upstream/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
new file mode 100644
index 0000000..dcd2c7c
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
+ * board.
+ *
+ * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
+ *
+ * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-pinctrl.h"
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
+ ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
+ ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
+ ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ status = "okay";
+};
+
+&main_cpsw0_port5 {
+ phy-handle = <&cpsw9g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port6 {
+ phy-handle = <&cpsw9g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port7 {
+ phy-handle = <&cpsw9g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port8 {
+ phy-handle = <&cpsw9g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_default_pins>;
+ bus_freq = <1000000>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ cpsw9g_phy0: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw9g_phy1: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw9g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw9g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ /* Power-up ENET1 EXPANDER PHY. */
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ /* Toggle MUX2 for MDIO lines */
+ mux-sel-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
+&main_pmx0 {
+ mdio0_default_pins: mdio0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
+ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
+ >;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
+};
+
+&serdes_wiz2 {
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ serdes2_qsgmii_link: phy@0 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz2 3>;
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/dts/upstream/src/arm64/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
new file mode 100644
index 0000000..d5f8c85
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
+ * and ENET-2 Expansion slots of J784S4 EVM.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+ ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&main_cpsw0_port1 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&main_cpsw0_port2 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&serdes_wiz2 {
+ assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ serdes2_usxgmii_link: phy@2 {
+ reg = <2>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
+ resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts b/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
index d511b25..ffa38f4 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
@@ -27,14 +27,16 @@
mmc1 = &main_sdhci1;
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
+ ethernet0 = &mcu_cpsw_port1;
+ ethernet1 = &main_cpsw1_port1;
};
memory@80000000 {
device_type = "memory";
bootph-all;
/* 32G RAM */
- reg = <0x00 0x80000000 0x00 0x80000000>,
- <0x08 0x80000000 0x07 0x80000000>;
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000007 0x80000000>;
};
reserved_memory: reserved-memory {
@@ -272,6 +274,59 @@
};
};
};
+
+ transceiver0: can-phy0 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver1: can-phy1 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
+ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ transceiver2: can-phy2 {
+ /* standby pin has been grounded by default */
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ transceiver3: can-phy3 {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
+ mux-states = <&mux1 1>;
+ };
+
+ mux1: mux-controller {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>;
+ idle-state = <1>;
+ };
+
+ codec_audio: sound {
+ compatible = "ti,j7200-cpb-audio";
+ model = "j784s4-cpb";
+
+ ti,cpb-mcasp = <&mcasp0>;
+ ti,cpb-codec = <&pcm3168a_1>;
+
+ clocks = <&k3_clks 265 0>, <&k3_clks 265 1>,
+ <&k3_clks 157 34>, <&k3_clks 157 63>;
+ clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
+ "cpb-codec-scki", "cpb-codec-scki-48000";
+ };
};
&wkup_gpio0 {
@@ -280,6 +335,30 @@
&main_pmx0 {
bootph-all;
+ main_cpsw2g_default_pins: main-cpsw2g-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+ J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+ J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+ J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+ J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+ J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+ J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+ J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+ J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+
+ main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
main_uart8_pins_default: main-uart8-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -336,6 +415,49 @@
J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
>;
};
+
+ main_mcan4_pins_default: main-mcan4-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */
+ J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */
+ >;
+ };
+
+ main_mcan16_pins_default: main-mcan16-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */
+ J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ bootph-all;
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */
+ J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */
+ >;
+ };
+
+ main_mcasp0_pins_default: main-mcasp0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */
+ J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */
+ J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */
+ J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */
+ >;
+ };
+
+ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */
+ >;
+ };
};
&wkup_pmx2 {
@@ -415,6 +537,32 @@
J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
>;
};
+
+ mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */
+ J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */
+ >;
+ };
+
+ mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */
+ J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */
+ >;
+ };
+
+ mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */
+ >;
+ };
+
+ mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
+ >;
+ };
};
&wkup_pmx1 {
@@ -579,6 +727,27 @@
};
};
};
+
+ tps62873a: regulator@40 {
+ compatible = "ti,tps62873";
+ reg = <0x40>;
+ bootph-pre-ram;
+ regulator-name = "VDD_CPU_AVS";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1330000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ tps62873b: regulator@43 {
+ compatible = "ti,tps62873";
+ reg = <0x43>;
+ regulator-name = "VDD_CORE_0V8";
+ regulator-min-microvolt = <760000>;
+ regulator-max-microvolt = <840000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&mcu_uart0 {
@@ -748,6 +917,14 @@
"PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
"PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
"AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
+
+ p12-hog {
+ /* P12 - AUDIO_MUX_SEL */
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "AUDIO_MUX_SEL";
+ };
};
exp2: gpio@22 {
@@ -763,6 +940,22 @@
"CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
"ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
"USER_INPUT1", "USER_LED1", "USER_LED2";
+
+ p13-hog {
+ /* P13 - CANUART_MUX_SEL0 */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CANUART_MUX_SEL0";
+ };
+
+ p15-hog {
+ /* P15 - CANUART_MUX1_SEL1 */
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CANUART_MUX1_SEL1";
+ };
};
};
@@ -832,6 +1025,31 @@
phy-handle = <&mcu_phy0>;
};
+&main_cpsw1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_default_pins>;
+ status = "okay";
+};
+
+&main_cpsw1_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
+ status = "okay";
+
+ main_cpsw1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw1_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw1_phy0>;
+ status = "okay";
+};
+
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
@@ -1041,6 +1259,48 @@
<&k3_clks 218 22>;
};
+&serdes0 {
+ status = "okay";
+
+ serdes0_pcie1_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_usb_link: phy@3 {
+ reg = <3>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&serdes_wiz4 {
status = "okay";
};
@@ -1105,3 +1365,113 @@
};
};
};
+
+&mcu_mcan0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan0_pins_default>;
+ phys = <&transceiver0>;
+};
+
+&mcu_mcan1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mcan1_pins_default>;
+ phys = <&transceiver1>;
+};
+
+&main_mcan16 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan16_pins_default>;
+ phys = <&transceiver2>;
+};
+
+&main_mcan4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcan4_pins_default>;
+ phys = <&transceiver3>;
+};
+
+&pcie1_rc {
+ status = "okay";
+ num-lanes = <2>;
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie1_link>;
+ phy-names = "pcie-phy";
+};
+
+&serdes1 {
+ status = "okay";
+
+ serdes1_pcie0_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&serdes_wiz1 {
+ status = "okay";
+};
+
+&pcie0_rc {
+ status = "okay";
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie0_link>;
+ phy-names = "pcie-phy";
+};
+
+&k3_clks {
+ /* Confiure AUDIO_EXT_REFCLK1 pin as output */
+ pinctrl-names = "default";
+ pinctrl-0 = <&audio_ext_refclk1_pins_default>;
+};
+
+&main_i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+
+ exp3: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pcm3168a_1: audio-codec@44 {
+ compatible = "ti,pcm3168a";
+ reg = <0x44>;
+ #sound-dai-cells = <1>;
+ reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
+ clocks = <&audio_refclk1>;
+ clock-names = "scki";
+ VDD1-supply = <&vsys_3v3>;
+ VDD2-supply = <&vsys_3v3>;
+ VCCAD1-supply = <&vsys_5v0>;
+ VCCAD2-supply = <&vsys_5v0>;
+ VCCDA1-supply = <&vsys_5v0>;
+ VCCDA2-supply = <&vsys_5v0>;
+ };
+};
+
+&mcasp0 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp0_pins_default>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ auxclk-fs-ratio = <256>;
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 0 1
+ 2 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
index 6a4554c..d4ac1c9 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,39 @@
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ cpsw1_phy_gmii_sel: phy@4034 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4034 0x4>;
+ #phy-cells = <1>;
+ };
+
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j784s4-cpsw9g-phy-gmii-sel";
+ reg = <0x4044 0x20>;
+ #phy-cells = <1>;
+ ti,qsgmii-main-ports = <7>, <7>;
+ };
+
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+
+ pcie1_ctrl: pcie1-ctrl@4074 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4074 0x4>;
+ };
+
+ pcie2_ctrl: pcie2-ctrl@4078 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4078 0x4>;
+ };
+
+ pcie3_ctrl: pcie3-ctrl@407c {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x407c 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -75,8 +108,90 @@
<J784S4_SERDES4_LANE2_EDP_LANE2>,
<J784S4_SERDES4_LANE3_EDP_LANE3>;
};
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "reg-mux";
+ reg = <0x4000 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
+ };
+
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+
+ audio_refclk1: clock@82e4 {
+ compatible = "ti,am62-audio-refclk";
+ reg = <0x82e4 0x4>;
+ clocks = <&k3_clks 157 34>;
+ assigned-clocks = <&k3_clks 157 34>;
+ assigned-clock-parents = <&k3_clks 157 63>;
+ #clock-cells = <0>;
+ };
};
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3000000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3010000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3020000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3030000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3040000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ reg = <0x00 0x3050000 0x00 0x100>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>;
+ clock-names = "tbclk", "fck";
+ power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -568,6 +683,38 @@
status = "disabled";
};
+ usbss0: usb@4104000 {
+ bootph-all;
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4104000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled"; /* Needs lane config */
+
+ usb0: usb@6000000 {
+ bootph-all;
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6000000 0x00 0x10000>,
+ <0x00 0x6010000 0x00 0x10000>,
+ <0x00 0x6020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ };
+ };
+
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
@@ -907,6 +1054,122 @@
status = "disabled";
};
+ pcie0_rc: pcie@2900000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 332 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 333 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie2_rc: pcie@2920000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02920000 0x00 0x1000>,
+ <0x00 0x02927000 0x00 0x400>,
+ <0x00 0x0e000000 0x00 0x00800000>,
+ <0x44 0x00000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 334 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x20000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie3_rc: pcie@2930000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02930000 0x00 0x1000>,
+ <0x00 0x02937000 0x00 0x400>,
+ <0x00 0x0e800000 0x00 0x00800000>,
+ <0x44 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 335 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x30000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
serdes_wiz0: wiz@5060000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
@@ -1427,6 +1690,180 @@
};
};
+ main_cpsw0: ethernet@c000000 {
+ compatible = "ti,j784s4-cpswxg-nuss";
+ reg = <0x00 0xc000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 64 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw0_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port3: port@3 {
+ reg = <3>;
+ label = "port3";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port4: port@4 {
+ reg = <4>;
+ label = "port4";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port5: port@5 {
+ reg = <5>;
+ label = "port5";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port6: port@6 {
+ reg = <6>;
+ label = "port6";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port7: port@7 {
+ reg = <7>;
+ label = "port7";
+ ti,mac-only;
+ status = "disabled";
+ };
+
+ main_cpsw0_port8: port@8 {
+ reg = <8>;
+ label = "port8";
+ ti,mac-only;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw0_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 64 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 64 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ main_cpsw1: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw1_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ phys = <&cpsw1_phy_gmii_sel 1>;
+ ti,mac-only;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw1_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
@@ -2255,4 +2692,94 @@
*/
};
};
+
+ mcasp0: mcasp@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
+ dma-names = "tx", "rx";
+ clocks = <&k3_clks 265 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 265 0>;
+ assigned-clock-parents = <&k3_clks 265 1>;
+ power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: mcasp@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
+ dma-names = "tx", "rx";
+ clocks = <&k3_clks 266 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 266 0>;
+ assigned-clock-parents = <&k3_clks 266 1>;
+ power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: mcasp@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
+ dma-names = "tx", "rx";
+ clocks = <&k3_clks 267 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 267 0>;
+ assigned-clock-parents = <&k3_clks 267 1>;
+ power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp3: mcasp@2b30000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b30000 0x00 0x2000>,
+ <0x00 0x02b38000 0x00 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>;
+ dma-names = "tx", "rx";
+ clocks = <&k3_clks 268 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 268 0>;
+ assigned-clock-parents = <&k3_clks 268 1>;
+ power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp4: mcasp@2b40000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b40000 0x00 0x2000>,
+ <0x00 0x02b48000 0x00 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>;
+ dma-names = "tx", "rx";
+ clocks = <&k3_clks 269 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 269 0>;
+ assigned-clock-parents = <&k3_clks 269 1>;
+ power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
index 2e18d91..f3a6ed1 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -145,12 +145,16 @@
status = "reserved";
};
- mcu_conf: syscon@40f00000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x00 0x40f00000 0x00 0x20000>;
+ mcu_conf: bus@40f00000 {
+ compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x00 0x00 0x40f00000 0x20000>;
+ ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+ cpsw_mac_syscon: ethernet-mac-syscon@200 {
+ compatible = "ti,am62p-cpsw-mac-efuse", "syscon";
+ reg = <0x200 0x8>;
+ };
phy_gmii_sel: phy@4040 {
compatible = "ti,am654-phy-gmii-sel";
@@ -553,7 +557,7 @@
reg = <1>;
ti,mac-only;
label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
+ ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
phys = <&phy_gmii_sel 1>;
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4.dtsi
index da7368e..73cc3c1 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4.dtsi
@@ -238,7 +238,10 @@
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
+ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
+ <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
@@ -248,7 +251,12 @@
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+ <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
+ <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
+ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
+ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
/* MCUSS_WKUP Range */
diff --git a/dts/upstream/src/arm64/ti/k3-pinctrl.h b/dts/upstream/src/arm64/ti/k3-pinctrl.h
index 4cd2df4..22b8d73 100644
--- a/dts/upstream/src/arm64/ti/k3-pinctrl.h
+++ b/dts/upstream/src/arm64/ti/k3-pinctrl.h
@@ -38,6 +38,9 @@
#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT)
#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT)
+/* Default mux configuration for gpio-ranges to use with pinctrl */
+#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)
+
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
diff --git a/dts/upstream/src/arm64/ti/k3-serdes.h b/dts/upstream/src/arm64/ti/k3-serdes.h
index a011ad8..ef36060 100644
--- a/dts/upstream/src/arm64/ti/k3-serdes.h
+++ b/dts/upstream/src/arm64/ti/k3-serdes.h
@@ -201,4 +201,12 @@
#define J784S4_SERDES4_LANE3_USB 0x2
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J722S */
+
+#define J722S_SERDES0_LANE0_USB 0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
+
#endif /* DTS_ARM64_TI_K3_SERDES_H */
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-clk-ccf.dtsi b/dts/upstream/src/arm64/xilinx/zynqmp-clk-ccf.dtsi
index dd4569e..60d1b1a 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-clk-ccf.dtsi
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-clk-ccf.dtsi
@@ -70,6 +70,22 @@
clocks = <&zynqmp_clk ACPU>;
};
+&cpu0_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu1_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu2_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu3_debug {
+ clocks = <&zynqmp_clk DBF_FPD>;
+};
+
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
index d7535a7..95d1690 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -22,6 +22,17 @@
/plugin/;
&{/} {
+ compatible = "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260-revY",
+ "xlnx,zynqmp-sk-kv260-revZ",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+ model = "ZynqMP KV260 revA";
+
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -68,7 +79,12 @@
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- /* u14 - 0x40 - ina260 */
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
@@ -321,6 +337,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
conf-cd {
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
index a7b8fff..a74d0ac 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -17,6 +17,17 @@
/plugin/;
&{/} {
+ compatible = "xlnx,zynqmp-sk-kv260-rev2",
+ "xlnx,zynqmp-sk-kv260-rev1",
+ "xlnx,zynqmp-sk-kv260-revB",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+ model = "ZynqMP KV260 revB";
+
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -52,6 +63,18 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -63,8 +86,13 @@
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- /* u14 - 0x40 - ina260 */
- /* u43 - 0x2d - usb5744 */
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ /* u43 - 0x2d - USB hub */
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
@@ -81,6 +109,14 @@
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
+
+ ports {
+ port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
+ };
};
&zynqmp_dpdma {
@@ -305,6 +341,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
conf-cd {
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts b/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
index 5162289..86e6c49 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -17,8 +18,9 @@
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
- model = "ZynqMP SM-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ model = "ZynqMP SM-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev2",
+ "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";
@@ -101,12 +103,23 @@
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
};
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ status = "okay";
+ pwms = <&ttc0 2 40000 0>;
+ };
};
&modepin_gpio {
label = "modepin";
};
+&ttc0 {
+ status = "okay";
+ #pwm-cells = <3>;
+};
+
&uart1 { /* MIO36/MIO37 */
status = "okay";
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-smk-k26-revA.dts b/dts/upstream/src/arm64/xilinx/zynqmp-smk-k26-revA.dts
index 85b0d16..b804abe 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-smk-k26-revA.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-smk-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -10,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
- model = "ZynqMP SMK-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ model = "ZynqMP SMK-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev2",
+ "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
"xlnx,zynqmp";
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zcu102-rev1.0.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zcu102-rev1.0.dts
index c8f71a1..495ca94 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zcu102-rev1.0.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zcu102-rev1.0.dts
@@ -14,6 +14,14 @@
compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};
+&rproc_split {
+ status = "okay";
+};
+
+&rproc_lockstep {
+ status = "disabled";
+};
+
&eeprom {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
index d99830c..b1b31dc 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
@@ -207,13 +207,71 @@
mbox-names = "tx", "rx";
};
- nvmem-firmware {
+ soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
- #address-cells = <1>;
- #size-cells = <1>;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
- soc_revision: soc-revision@0 {
- reg = <0x0 0x4>;
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_aeskey: efuse-aeskey@60 {
+ reg = <0x60 0x20>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
+ efuse_pufuser: efuse-pufuser@100 {
+ reg = <0x100 0x7F>;
+ };
};
};
@@ -252,7 +310,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
- fpga_full: fpga-full {
+ fpga_full: fpga-region {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <2>;
@@ -260,19 +318,76 @@
ranges;
};
- remoteproc {
+ rproc_lockstep: remoteproc@ffe00000 {
compatible = "xlnx,zynqmp-r5fss";
xlnx,cluster-mode = <1>;
+ xlnx,tcm-mode = <1>;
- r5f-0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
+
+ r5f@0 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x0 0x0 0x0 0x10000>,
+ <0x0 0x20000 0x0 0x10000>,
+ <0x0 0x10000 0x0 0x10000>,
+ <0x0 0x30000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0", "atcm1", "btcm1";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_0_fw_image>;
+ };
+
+ r5f@1 {
+ compatible = "xlnx,zynqmp-r5f";
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
+ memory-region = <&rproc_1_fw_image>;
+ };
+ };
+
+ rproc_split: remoteproc-split@ffe00000 {
+ status = "disabled";
+ compatible = "xlnx,zynqmp-r5fss";
+ xlnx,cluster-mode = <0>;
+ xlnx,tcm-mode = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
+ <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
+ <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
+ <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
+
+ r5f@0 {
compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware PD_RPU_0>;
+ reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_0>,
+ <&zynqmp_firmware PD_R5_0_ATCM>,
+ <&zynqmp_firmware PD_R5_0_BTCM>;
memory-region = <&rproc_0_fw_image>;
};
- r5f-1 {
+ r5f@1 {
compatible = "xlnx,zynqmp-r5f";
- power-domains = <&zynqmp_firmware PD_RPU_1>;
+ reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
+ reg-names = "atcm0", "btcm0";
+ power-domains = <&zynqmp_firmware PD_RPU_1>,
+ <&zynqmp_firmware PD_R5_1_ATCM>,
+ <&zynqmp_firmware PD_R5_1_BTCM>;
memory-region = <&rproc_1_fw_image>;
};
};
@@ -330,6 +445,34 @@
};
};
+ cpu0_debug: debug@fec10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfec10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ cpu1_debug: debug@fed10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfed10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ cpu2_debug: debug@fee10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfee10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ cpu3_debug: debug@fef10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x0 0xfef10000 0x0 0x1000>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
/* GDMA */
fpd_dma_chan1: dma-controller@fd500000 {
status = "disabled";
@@ -684,6 +827,13 @@
power-domains = <&zynqmp_firmware PD_I2C_1>;
};
+ ocm: memory-controller@ff960000 {
+ compatible = "xlnx,zynqmp-ocmc-1.0";
+ reg = <0x0 0xff960000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pcie: pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
@@ -941,10 +1091,11 @@
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupt-names = "host", "peripheral", "otg";
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ref";
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
@@ -972,10 +1123,11 @@
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupt-names = "host", "peripheral", "otg";
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ref";
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
@@ -1024,8 +1176,6 @@
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
};
};
diff --git a/dts/upstream/src/mips/loongson/loongson64-2k1000.dtsi b/dts/upstream/src/mips/loongson/loongson64-2k1000.dtsi
index ee3e215..cc7747c 100644
--- a/dts/upstream/src/mips/loongson/loongson64-2k1000.dtsi
+++ b/dts/upstream/src/mips/loongson/loongson64-2k1000.dtsi
@@ -23,14 +23,6 @@
};
};
- memory@200000 {
- compatible = "memory";
- device_type = "memory";
- reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
- <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
- <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
- };
-
cpu_clk: cpu_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -52,6 +44,13 @@
0 0x40000000 0 0x40000000 0 0x40000000
0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+ isa@18000000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x18000000 0x4000>;
+ };
+
pm: reset-controller@1fe07000 {
compatible = "loongson,ls2k-pm";
reg = <0 0x1fe07000 0 0x422>;
@@ -100,8 +99,8 @@
rtc0: rtc@1fe07800 {
compatible = "loongson,ls2k1000-rtc";
reg = <0 0x1fe07800 0 0x78>;
- interrupt-parent = <&liointc0>;
- interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: serial@1fe00000 {
@@ -109,7 +108,7 @@
reg = <0 0x1fe00000 0 0x8>;
clock-frequency = <125000000>;
interrupt-parent = <&liointc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
@@ -118,7 +117,6 @@
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <2>;
reg = <0 0x1a000000 0 0x02000000>,
<0xfe 0x00000000 0 0x20000000>;
@@ -133,11 +131,12 @@
"pciclass0c03";
reg = <0x1800 0x0 0x0 0x0 0x0>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
- <13 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -156,11 +155,12 @@
"loongson, pci-gmac";
reg = <0x1900 0x0 0x0 0x0 0x0>;
- interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
- <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -178,7 +178,7 @@
"pciclass0c03";
reg = <0x2100 0x0 0x0 0x0 0x0>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
};
@@ -189,7 +189,7 @@
"pciclass0c03";
reg = <0x2200 0x0 0x0 0x0 0x0>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
};
@@ -200,97 +200,121 @@
"pciclass0106";
reg = <0x4000 0x0 0x0 0x0 0x0>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc0>;
};
- pci_bridge@9,0 {
+ pcie@9,0 {
compatible = "pci0014,7a19.0",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
- pci_bridge@a,0 {
+ pcie@a,0 {
compatible = "pci0014,7a09.0",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
- pci_bridge@b,0 {
+ pcie@b,0 {
compatible = "pci0014,7a09.0",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
- pci_bridge@c,0 {
+ pcie@c,0 {
compatible = "pci0014,7a09.0",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
- pci_bridge@d,0 {
+ pcie@d,0 {
compatible = "pci0014,7a19.0",
"pci0014,7a19",
"pciclass060400",
"pciclass0604";
reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
- pci_bridge@e,0 {
+ pcie@e,0 {
compatible = "pci0014,7a09.0",
"pci0014,7a09",
"pciclass060400",
"pciclass0604";
reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
external-facing;
};
diff --git a/dts/upstream/src/mips/loongson/loongson64g_4core_ls7a.dts b/dts/upstream/src/mips/loongson/loongson64g_4core_ls7a.dts
index c945f85..fb180cb 100644
--- a/dts/upstream/src/mips/loongson/loongson64g_4core_ls7a.dts
+++ b/dts/upstream/src/mips/loongson/loongson64g_4core_ls7a.dts
@@ -33,6 +33,7 @@
compatible = "loongson,pch-msi-1.0";
reg = <0 0x2ff00000 0 0x8>;
interrupt-controller;
+ #interrupt-cells = <1>;
msi-controller;
loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <192>;
diff --git a/dts/upstream/src/mips/mobileye/eyeq5-clocks.dtsi b/dts/upstream/src/mips/mobileye/eyeq5-clocks.dtsi
new file mode 100644
index 0000000..17a342c
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq5-clocks.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+
+/ {
+ /* Fixed clock */
+ xtal: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ };
+
+/* PLL_CPU derivatives */
+ occ_cpu: occ-cpu {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_CPU>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ cpc_clk: cpc-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core0_clk: core0-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core1_clk: core1-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core2_clk: core2-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ core3_clk: core3-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ cm_clk: cm-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ mem_clk: mem-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&si_css0_ref_clk>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_isram: occ-isram {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_CPU>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ isram_clk: isram-clk { /* gate ClkRstGen_isram */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_isram>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_dbu: occ-dbu {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_CPU>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ };
+ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_dbu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+/* PLL_VDI derivatives */
+ occ_vdi: occ-vdi {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_VDI>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_vdi>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ occ_can_ser: occ-can-ser {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_VDI>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ };
+ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_can_ser>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ i2c_ser_clk: i2c-ser-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_VDI>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ };
+/* PLL_PER derivatives */
+ occ_periph: occ-periph {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ };
+ periph_clk: periph-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ can_clk: can-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ spi_clk: spi-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+ i2c_clk: i2c-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "i2c_clk";
+ };
+ timer_clk: timer-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "timer_clk";
+ };
+ gpio_clk: gpio-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "gpio_clk";
+ };
+ emmc_sys_clk: emmc-sys-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ clock-output-names = "emmc_sys_clk";
+ };
+ ccf_ctrl_clk: ccf-ctrl-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clock-output-names = "ccf_ctrl_clk";
+ };
+ occ_mjpeg_core: occ-mjpeg-core {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "occ_mjpeg_core";
+ };
+ hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "hsm_clk";
+ };
+ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_mjpeg_core>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clock-output-names = "mjpeg_core_clk";
+ };
+ fcmu_a_clk: fcmu-a-clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ clock-output-names = "fcmu_a_clk";
+ };
+ occ_pci_sys: occ-pci-sys {
+ compatible = "fixed-factor-clock";
+ clocks = <&olb EQ5C_PLL_PER>;
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clock-output-names = "occ_pci_sys";
+ };
+ pclk: pclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>; /* 250MHz */
+ };
+ tsu_clk: tsu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>; /* 125MHz */
+ };
+};
diff --git a/dts/upstream/src/mips/mobileye/eyeq5-fixed-clocks.dtsi b/dts/upstream/src/mips/mobileye/eyeq5-fixed-clocks.dtsi
deleted file mode 100644
index 78f5533..0000000
--- a/dts/upstream/src/mips/mobileye/eyeq5-fixed-clocks.dtsi
+++ /dev/null
@@ -1,292 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright 2023 Mobileye Vision Technologies Ltd.
- */
-
-/ {
- /* Fixed clock */
- pll_cpu: pll-cpu {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1500000000>;
- };
-
- pll_vdi: pll-vdi {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1280000000>;
- };
-
- pll_per: pll-per {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2000000000>;
- };
-
- pll_ddr0: pll-ddr0 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1857210000>;
- };
-
- pll_ddr1: pll-ddr1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1857210000>;
- };
-
-/* PLL_CPU derivatives */
- occ_cpu: occ-cpu {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
- compatible = "fixed-factor-clock";
- clocks = <&occ_cpu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- cpc_clk: cpc-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core0_clk: core0-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core1_clk: core1-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core2_clk: core2-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- core3_clk: core3-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- cm_clk: cm-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- mem_clk: mem-clk {
- compatible = "fixed-factor-clock";
- clocks = <&si_css0_ref_clk>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_isram: occ-isram {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- isram_clk: isram-clk { /* gate ClkRstGen_isram */
- compatible = "fixed-factor-clock";
- clocks = <&occ_isram>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_dbu: occ-dbu {
- compatible = "fixed-factor-clock";
- clocks = <&pll_cpu>;
- #clock-cells = <0>;
- clock-div = <10>;
- clock-mult = <1>;
- };
- si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
- compatible = "fixed-factor-clock";
- clocks = <&occ_dbu>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
-/* PLL_VDI derivatives */
- occ_vdi: occ-vdi {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- };
- vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
- compatible = "fixed-factor-clock";
- clocks = <&occ_vdi>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- occ_can_ser: occ-can-ser {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <16>;
- clock-mult = <1>;
- };
- can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
- compatible = "fixed-factor-clock";
- clocks = <&occ_can_ser>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- i2c_ser_clk: i2c-ser-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_vdi>;
- #clock-cells = <0>;
- clock-div = <20>;
- clock-mult = <1>;
- };
-/* PLL_PER derivatives */
- occ_periph: occ-periph {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <16>;
- clock-mult = <1>;
- };
- periph_clk: periph-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- can_clk: can-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- spi_clk: spi-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- };
- i2c_clk: i2c-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "i2c_clk";
- };
- timer_clk: timer-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "timer_clk";
- };
- gpio_clk: gpio-clk {
- compatible = "fixed-factor-clock";
- clocks = <&occ_periph>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "gpio_clk";
- };
- emmc_sys_clk: emmc-sys-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <10>;
- clock-mult = <1>;
- clock-output-names = "emmc_sys_clk";
- };
- ccf_ctrl_clk: ccf-ctrl-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "ccf_ctrl_clk";
- };
- occ_mjpeg_core: occ-mjpeg-core {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <2>;
- clock-mult = <1>;
- clock-output-names = "occ_mjpeg_core";
- };
- hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
- compatible = "fixed-factor-clock";
- clocks = <&occ_mjpeg_core>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "hsm_clk";
- };
- mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
- compatible = "fixed-factor-clock";
- clocks = <&occ_mjpeg_core>;
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "mjpeg_core_clk";
- };
- fcmu_a_clk: fcmu-a-clk {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <20>;
- clock-mult = <1>;
- clock-output-names = "fcmu_a_clk";
- };
- occ_pci_sys: occ-pci-sys {
- compatible = "fixed-factor-clock";
- clocks = <&pll_per>;
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
- clock-output-names = "occ_pci_sys";
- };
- pclk: pclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>; /* 250MHz */
- };
- tsu_clk: tsu-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>; /* 125MHz */
- };
-};
diff --git a/dts/upstream/src/mips/mobileye/eyeq5-pins.dtsi b/dts/upstream/src/mips/mobileye/eyeq5-pins.dtsi
new file mode 100644
index 0000000..0b36710
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq5-pins.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+/*
+ * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
+ * pin configuration node per function.
+ */
+
+&olb {
+ timer0_pins: timer0-pins {
+ function = "timer0";
+ pins = "PA0", "PA1";
+ };
+ timer1_pins: timer1-pins {
+ function = "timer1";
+ pins = "PA2", "PA3";
+ };
+ timer2_pins: timer2-pins {
+ function = "timer2";
+ pins = "PA4", "PA5";
+ };
+ pps0_pins: pps0-pin {
+ function = "timer2";
+ pins = "PA4";
+ };
+ pps1_pins: pps1-pin {
+ function = "timer2";
+ pins = "PA5";
+ };
+ timer5_ext_pins: timer5-ext-pins {
+ function = "timer5";
+ pins = "PA6", "PA7", "PA8", "PA9";
+ };
+ timer5_ext_input_pins: timer5-ext-input-pins {
+ function = "timer5";
+ pins = "PA6", "PA7";
+ };
+ timer5_ext_incap_a_pins: timer5-ext-incap-a-pin {
+ function = "timer5";
+ pins = "PA6";
+ };
+ timer5_ext_incap_b_pins: timer5-ext-incap-b-pin {
+ function = "timer5";
+ pins = "PA7";
+ };
+ can0_pins: can0-pins {
+ function = "can0";
+ pins = "PA14", "PA15";
+ };
+ can1_pins: can1-pins {
+ function = "can1";
+ pins = "PA16", "PA17";
+ };
+ uart0_pins: uart0-pins {
+ function = "uart0";
+ pins = "PA10", "PA11";
+ };
+ uart1_pins: uart1-pins {
+ function = "uart1";
+ pins = "PA12", "PA13";
+ };
+ spi0_pins: spi0-pins {
+ function = "spi0";
+ pins = "PA18", "PA19", "PA20", "PA21", "PA22";
+ };
+ spi1_pins: spi1-pins {
+ function = "spi1";
+ pins = "PA23", "PA24", "PA25", "PA26", "PA27";
+ };
+ spi1_slave_pins: spi1-slave-pins {
+ function = "spi1";
+ pins = "PA24", "PA25", "PA26";
+ };
+ refclk0_pins: refclk0-pin {
+ function = "refclk0";
+ pins = "PA28";
+ };
+ timer3_pins: timer3-pins {
+ function = "timer3";
+ pins = "PB0", "PB1";
+ };
+ timer4_pins: timer4-pins {
+ function = "timer4";
+ pins = "PB2", "PB3";
+ };
+ timer6_ext_pins: timer6-ext-pins {
+ function = "timer6";
+ pins = "PB4", "PB5", "PB6", "PB7";
+ };
+ timer6_ext_input_pins: timer6-ext-input-pins {
+ function = "timer6";
+ pins = "PB4", "PB5";
+ };
+ timer6_ext_incap_a_pins: timer6-ext-incap-a-pin {
+ function = "timer6";
+ pins = "PB4";
+ };
+ timer6_ext_incap_b_pins: timer6-ext-incap-b-pin {
+ function = "timer6";
+ pins = "PB5";
+ };
+ can2_pins: can2-pins {
+ function = "can2";
+ pins = "PB10", "PB11";
+ };
+ uart2_pins: uart2-pins {
+ function = "uart2";
+ pins = "PB8", "PB9";
+ };
+ spi2_pins: spi2-pins {
+ function = "spi2";
+ pins = "PB12", "PB13", "PB14", "PB15", "PB16";
+ };
+ spi3_pins: spi3-pins {
+ function = "spi3";
+ pins = "PB17", "PB18", "PB19", "PB20", "PB21";
+ };
+ spi3_slave_pins: spi3-slave-pins {
+ function = "spi3";
+ pins = "PB18", "PB19", "PB20";
+ };
+ mclk0_pins: mclk0-pin {
+ function = "mclk0";
+ pins = "PB22";
+ };
+};
diff --git a/dts/upstream/src/mips/mobileye/eyeq5.dtsi b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
index 6cc5980..0708771 100644
--- a/dts/upstream/src/mips/mobileye/eyeq5.dtsi
+++ b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
-#include "eyeq5-fixed-clocks.dtsi"
+#include "eyeq5-clocks.dtsi"
/ {
#address-cells = <2>;
@@ -78,6 +78,9 @@
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
};
uart1: serial@900000 {
@@ -88,6 +91,9 @@
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 11>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
};
uart2: serial@a00000 {
@@ -98,8 +104,20 @@
interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&occ_periph>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&olb 0 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
};
+ olb: system-controller@e00000 {
+ compatible = "mobileye,eyeq5-olb", "syscon";
+ reg = <0 0xe00000 0x0 0x400>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+
gic: interrupt-controller@140000 {
compatible = "mti,gic";
reg = <0x0 0x140000 0x0 0x20000>;
@@ -122,3 +140,5 @@
};
};
};
+
+#include "eyeq5-pins.dtsi"
diff --git a/dts/upstream/src/mips/mobileye/eyeq6h-epm6.dts b/dts/upstream/src/mips/mobileye/eyeq6h-epm6.dts
new file mode 100644
index 0000000..ebc0d36
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq6h-epm6.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2024 Mobileye Vision Technologies Ltd.
+ */
+
+/dts-v1/;
+
+#include "eyeq6h.dtsi"
+
+/ {
+ compatible = "mobileye,eyeq6-epm6", "mobileye,eyeq6";
+ model = "Mobile EyeQ6H MP6 Evaluation board";
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x1 0x00000000 0x1 0x00000000>;
+ };
+};
diff --git a/dts/upstream/src/mips/mobileye/eyeq6h-fixed-clocks.dtsi b/dts/upstream/src/mips/mobileye/eyeq6h-fixed-clocks.dtsi
new file mode 100644
index 0000000..5fa99e0
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq6h-fixed-clocks.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2023 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+
+/ {
+ xtal: clock-30000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ };
+
+ pll_west: clock-2000000000-west {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000000000>;
+ };
+
+ pll_cpu: clock-2000000000-cpu {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000000000>;
+ };
+
+ /* pll-cpu derivatives */
+ occ_cpu: clock-2000000000-occ-cpu {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_cpu>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+
+ /* pll-west derivatives */
+ occ_periph_w: clock-200000000 {
+ compatible = "fixed-factor-clock";
+ clocks = <&pll_west>;
+ #clock-cells = <0>;
+ clock-div = <10>;
+ clock-mult = <1>;
+ };
+ uart_clk: clock-200000000-uart {
+ compatible = "fixed-factor-clock";
+ clocks = <&occ_periph_w>;
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ };
+
+};
diff --git a/dts/upstream/src/mips/mobileye/eyeq6h-pins.dtsi b/dts/upstream/src/mips/mobileye/eyeq6h-pins.dtsi
new file mode 100644
index 0000000..a3d1b36
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq6h-pins.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2024 Mobileye Vision Technologies Ltd.
+ */
+
+/*
+ * MUX register structure
+ * bits | field | comment
+ * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
+ * [4] | SW_LOOPBACK|
+ * [5] | SW_OUT_HZ |
+ * [7] | DBG_IN |
+ * [11:8] | DS | drive strength
+ * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
+ * [14] | OD | Open drain
+ * [15] | ST_CFG | Hysteretic input enable (Schmitt trigger)
+ */
+
+&pinctrl_west {
+ // TODO: use pinctrl-single,bias-pullup
+ // TODO: use pinctrl-single,bias-pulldown
+ // TODO: use pinctrl-single,drive-strength
+ // TODO: use pinctrl-single,input-schmitt
+
+ i2c0_pins: i2c0-pins {
+ pinctrl-single,pins = <
+ 0x000 0x200 // I2C0_SCL pin
+ 0x004 0x200 // I2C0_SDA pin
+ >;
+ };
+ i2c1_pins: i2c1-pins {
+ pinctrl-single,pins = <
+ 0x008 0x200 // I2C1_SCL pin
+ 0x00c 0x200 // I2C1_SDA pin
+ >;
+ };
+ eth0_pins: eth0-pins {
+ pinctrl-single,pins = <
+ 0x080 1 // GPIO_C4__SMA0_MDC pin
+ 0x084 1 // GPIO_C5__SMA0_MDIO pin
+ >;
+ };
+ uart0_pins: uart0-pins {
+ pinctrl-single,pins = <0x0a8 1>; // UART0 pin group
+ };
+ uart1_pins: uart1-pins {
+ pinctrl-single,pins = <0x0a0 1>; // UART1 pin group
+ };
+ spi0_pins: spi0-pins {
+ pinctrl-single,pins = <0x0ac 1>; // SPI0 pin group
+ };
+ spi1_pins: spi1-pins {
+ pinctrl-single,pins = <0x0a4 1>; // SPI1 pin group
+ };
+};
+
+&pinctrl_east {
+ i2c2_pins: i2c2-pins {
+ pinctrl-single,pins = <
+ 0x000 0x200 // i2c2_SCL pin
+ 0x004 0x200 // i2c2_SDA pin
+ >;
+ };
+ i2c3_pins: i2c3-pins {
+ pinctrl-single,pins = <
+ 0x008 0x200 // i2c3_SCL pin
+ 0x00c 0x200 // i2c3_SDA pin
+ >;
+ };
+ eth1_pins: eth1-pins {
+ pinctrl-single,pins = <
+ 0x080 1 // GPIO_D4__SMA1_MDC pin
+ 0x084 1 // GPIO_D5__SMA1_MDIO pin
+ >;
+ };
+ uart2_sel_pins: uart2-pins {
+ pinctrl-single,pins = <0x0a4 1>; // UART2 pin group
+ };
+ uart3_pins: uart3-pins {
+ pinctrl-single,pins = <0x09c 1>; // UART3 pin group
+ };
+ spi2_pins: spi2-pins {
+ pinctrl-single,pins = <0x0a8 1>; // SPI2 pin group
+ };
+ spi3_pins: spi3-pins {
+ pinctrl-single,pins = <0x0a0 1>; // SPI3 pin group
+ };
+};
diff --git a/dts/upstream/src/mips/mobileye/eyeq6h.dtsi b/dts/upstream/src/mips/mobileye/eyeq6h.dtsi
new file mode 100644
index 0000000..1db3c3c
--- /dev/null
+++ b/dts/upstream/src/mips/mobileye/eyeq6h.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+/*
+ * Copyright 2024 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+#include "eyeq6h-fixed-clocks.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "img,i6500";
+ reg = <0>;
+ clocks = <&occ_cpu>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart0: serial@d3331000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0xd3331000 0x0 0x1000>;
+ reg-io-width = <4>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&occ_periph_w>, <&occ_periph_w>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ pinctrl_west: pinctrl@d3337000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xd3337000 0x0 0xb0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffff>;
+ };
+
+ pinctrl_east: pinctrl@d3357000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xd3357000 0x0 0xb0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffff>;
+ };
+
+ pinctrl_south: pinctrl@d8014000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xd8014000 0x0 0xf8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffff>;
+ };
+
+ gic: interrupt-controller@f0920000 {
+ compatible = "mti,gic";
+ reg = <0x0 0xf0920000 0x0 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpu_intc>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&occ_cpu>;
+ };
+ };
+ };
+};
+
+#include "eyeq6h-pins.dtsi"
diff --git a/dts/upstream/src/mips/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts b/dts/upstream/src/mips/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
new file mode 100644
index 0000000..77d2566
--- /dev/null
+++ b/dts/upstream/src/mips/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "cameo,rtl9302c-2x-rtl8224-2xge", "realtek,rtl9302-soc";
+ model = "RTL9302C Development Board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "LOADER";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "BDINFO";
+ reg = <0xe0000 0x10000>;
+ };
+ partition@f0000 {
+ label = "SYSINFO";
+ reg = <0xf0000 0x10000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "JFFS2 CFG";
+ reg = <0x100000 0x100000>;
+ };
+ partition@200000 {
+ label = "JFFS2 LOG";
+ reg = <0x200000 0x100000>;
+ };
+ partition@300000 {
+ label = "RUNTIME";
+ reg = <0x300000 0xe80000>;
+ };
+ partition@1180000 {
+ label = "RUNTIME2";
+ reg = <0x1180000 0xe80000>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/mips/realtek/rtl838x.dtsi b/dts/upstream/src/mips/realtek/rtl838x.dtsi
index 6cc4ff5..722106e 100644
--- a/dts/upstream/src/mips/realtek/rtl838x.dtsi
+++ b/dts/upstream/src/mips/realtek/rtl838x.dtsi
@@ -6,6 +6,7 @@
#size-cells = <0>;
cpu@0 {
+ device_type = "cpu";
compatible = "mips,mips4KEc";
reg = <0>;
clocks = <&baseclk 0>;
diff --git a/dts/upstream/src/mips/realtek/rtl83xx.dtsi b/dts/upstream/src/mips/realtek/rtl83xx.dtsi
index de65a11..03ddc61 100644
--- a/dts/upstream/src/mips/realtek/rtl83xx.dtsi
+++ b/dts/upstream/src/mips/realtek/rtl83xx.dtsi
@@ -22,7 +22,7 @@
#size-cells = <1>;
ranges = <0x0 0x18000000 0x10000>;
- uart0: uart@2000 {
+ uart0: serial@2000 {
compatible = "ns16550a";
reg = <0x2000 0x100>;
@@ -39,7 +39,7 @@
status = "disabled";
};
- uart1: uart@2100 {
+ uart1: serial@2100 {
compatible = "ns16550a";
reg = <0x2100 0x100>;
diff --git a/dts/upstream/src/mips/realtek/rtl930x.dtsi b/dts/upstream/src/mips/realtek/rtl930x.dtsi
new file mode 100644
index 0000000..f271940
--- /dev/null
+++ b/dts/upstream/src/mips/realtek/rtl930x.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+
+#include "rtl83xx.dtsi"
+
+/ {
+ compatible = "realtek,rtl9302-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips34Kc";
+ reg = <0>;
+ clocks = <&baseclk 0>;
+ clock-names = "cpu";
+ };
+ };
+
+ baseclk: clock-800mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ };
+
+ lx_clk: clock-175mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <175000000>;
+ };
+};
+
+&soc {
+ intc: interrupt-controller@3000 {
+ compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
+ reg = <0x3000 0x18>, <0x3018 0x18>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
+ };
+
+ spi0: spi@1200 {
+ compatible = "realtek,rtl8380-spi";
+ reg = <0x1200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer0: timer@3200 {
+ compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
+ reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
+ <0x3230 0x10>, <0x3240 0x10>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <7>, <8>, <9>, <10>, <11>;
+ clocks = <&lx_clk>;
+ };
+};
+
+&uart0 {
+ /delete-property/ clock-frequency;
+ clocks = <&lx_clk>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+};
+
+&uart1 {
+ /delete-property/ clock-frequency;
+ clocks = <&lx_clk>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+};
+
diff --git a/dts/upstream/src/powerpc/acadia.dts b/dts/upstream/src/powerpc/acadia.dts
deleted file mode 100644
index 5fedda8..0000000
--- a/dts/upstream/src/powerpc/acadia.dts
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Device Tree Source for AMCC Acadia (405EZ)
- *
- * Copyright IBM Corp. 2008
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "amcc,acadia";
- compatible = "amcc,acadia";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EZ";
- reg = <0x0>;
- clock-frequency = <0>; /* Filled in by wrapper */
- timebase-frequency = <0>; /* Filled in by wrapper */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>;
- d-cache-size = <16384>;
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x0 0x0>; /* Filled in by wrapper */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic-405ez", "ibm,uic";
- interrupt-controller;
- dcr-reg = <0x0c0 0x009>;
- cell-index = <0>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- plb {
- compatible = "ibm,plb-405ez", "ibm,plb3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by wrapper */
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-405ez", "ibm,mcmal";
- dcr-reg = <0x380 0x62>;
- num-tx-chans = <1>;
- num-rx-chans = <1>;
- interrupt-parent = <&UIC0>;
- /* 405EZ has only 3 interrupts to the UIC, as
- * SERR, TXDE, and RXDE are or'd together into
- * one UIC bit
- */
- interrupts = <
- 0x13 0x4 /* TXEOB */
- 0x15 0x4 /* RXEOB */
- 0x12 0x4 /* SERR, TXDE, RXDE */>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405ez", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- dcr-reg = <0x0a 0x05>;
- clock-frequency = <0>; /* Filled in by wrapper */
-
- UART0: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x8>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by wrapper */
- current-speed = <115200>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x5 0x4>;
- };
-
- UART1: serial@ef600400 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600400 0x8>;
- clock-frequency = <0>; /* Filled in by wrapper */
- current-speed = <115200>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x6 0x4>;
- };
-
- IIC: i2c@ef600500 {
- compatible = "ibm,iic-405ez", "ibm,iic";
- reg = <0xef600500 0x11>;
- interrupt-parent = <&UIC0>;
- interrupts = <0xa 0x4>;
- };
-
- GPIO0: gpio@ef600700 {
- compatible = "ibm,gpio-405ez";
- reg = <0xef600700 0x20>;
- };
-
- GPIO1: gpio@ef600800 {
- compatible = "ibm,gpio-405ez";
- reg = <0xef600800 0x20>;
- };
-
- EMAC0: ethernet@ef600900 {
- device_type = "network";
- compatible = "ibm,emac-405ez", "ibm,emac";
- interrupt-parent = <&UIC0>;
- interrupts = <
- 0x10 0x4 /* Ethernet */
- 0x11 0x4 /* Ethernet Wake up */>;
- local-mac-address = [000000000000]; /* Filled in by wrapper */
- reg = <0xef600900 0x70>;
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <1500>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- phy-mode = "mii";
- phy-map = <0x0>;
- };
-
- CAN0: can@ef601000 {
- compatible = "amcc,can-405ez";
- reg = <0xef601000 0x620>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x7 0x4>;
- };
-
- CAN1: can@ef601800 {
- compatible = "amcc,can-405ez";
- reg = <0xef601800 0x620>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x8 0x4>;
- };
-
- cameleon@ef602000 {
- compatible = "amcc,cameleon-405ez";
- reg = <0xef602000 0x800>;
- interrupt-parent = <&UIC0>;
- interrupts = <0xb 0x4 0xc 0x4>;
- };
-
- ieee1588@ef602800 {
- compatible = "amcc,ieee1588-405ez";
- reg = <0xef602800 0x60>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x4 0x4>;
- /* This thing is a bit weird. It has its own UIC
- * that it uses to generate snapshot triggers. We
- * don't really support this device yet, and it needs
- * work to figure this out.
- */
- dcr-reg = <0xe0 0x9>;
- };
-
- usb@ef603000 {
- compatible = "ohci-be";
- reg = <0xef603000 0x80>;
- interrupt-parent = <&UIC0>;
- interrupts = <0xd 0x4 0xe 0x4>;
- };
-
- dac@ef603300 {
- compatible = "amcc,dac-405ez";
- reg = <0xef603300 0x40>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x18 0x4>;
- };
-
- adc@ef603400 {
- compatible = "amcc,adc-405ez";
- reg = <0xef603400 0x40>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x17 0x4>;
- };
-
- spi@ef603500 {
- compatible = "amcc,spi-405ez";
- reg = <0xef603500 0x100>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x9 0x4>;
- };
- };
-
- EBC0: ebc {
- compatible = "ibm,ebc-405ez", "ibm,ebc";
- dcr-reg = <0x12 0x2>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by wrapper */
- };
- };
-
- chosen {
- stdout-path = "/plb/opb/serial@ef600300";
- };
-};
diff --git a/dts/upstream/src/powerpc/haleakala.dts b/dts/upstream/src/powerpc/haleakala.dts
deleted file mode 100644
index f81ce87..0000000
--- a/dts/upstream/src/powerpc/haleakala.dts
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * Device Tree Source for AMCC Haleakala (405EXr)
- *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "amcc,haleakala";
- compatible = "amcc,haleakala", "amcc,kilauea";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EXr";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>; /* 16 kB */
- d-cache-size = <16384>; /* 16 kB */
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic-405exr", "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-405exr","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-405exr","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- plb {
- compatible = "ibm,plb-405exr", "ibm,plb4";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-405exr", "ibm,sdram-4xx-ddr2";
- dcr-reg = <0x010 0x002>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x5 0x4 /* ECC DED Error */
- 0x6 0x4>; /* ECC SEC Error */
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <2>;
- interrupt-parent = <&MAL0>;
- interrupts = <0x0 0x1 0x2 0x3 0x4>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
- /*RXEOB*/ 0x1 &UIC0 0xb 0x4
- /*SERR*/ 0x2 &UIC1 0x0 0x4
- /*TXDE*/ 0x3 &UIC1 0x1 0x4
- /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
- interrupt-map-mask = <0xffffffff>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405exr", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x80000000 0x80000000 0x10000000
- 0xef600000 0xef600000 0x00a00000
- 0xf0000000 0xf0000000 0x10000000>;
- dcr-reg = <0x0a0 0x005>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-405exr", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x5 0x1>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x04000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x00200000>;
- };
- partition@200000 {
- label = "root";
- reg = <0x00200000 0x00200000>;
- };
- partition@400000 {
- label = "user";
- reg = <0x00400000 0x03b60000>;
- };
- partition@3f60000 {
- label = "env";
- reg = <0x03f60000 0x00040000>;
- };
- partition@3fa0000 {
- label = "u-boot";
- reg = <0x03fa0000 0x00060000>;
- };
- };
- };
-
- UART0: serial@ef600200 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600200 0x00000008>;
- virtual-reg = <0xef600200>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1a 0x4>;
- };
-
- UART1: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600400 {
- compatible = "ibm,iic-405exr", "ibm,iic";
- reg = <0xef600400 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- };
-
- IIC1: i2c@ef600500 {
- compatible = "ibm,iic-405exr", "ibm,iic";
- reg = <0xef600500 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x7 0x4>;
- };
-
-
- RGMII0: emac-rgmii@ef600b00 {
- compatible = "ibm,rgmii-405exr", "ibm,rgmii";
- reg = <0xef600b00 0x00000104>;
- has-mdio;
- };
-
- EMAC0: ethernet@ef600900 {
- linux,network-index = <0x0>;
- device_type = "network";
- compatible = "ibm,emac-405exr", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
- /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
- reg = <0xef600900 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
- };
-
- PCIE0: pcie@a0000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0xa0000000 0x20000000 /* Config space access */
- 0xef000000 0x00001000>; /* Registers */
- dcr-reg = <0x040 0x020>;
- sdr-base = <0x400>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0x00 to 0x3f */
- bus-range = <0x0 0x3f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
- };
- };
-};
diff --git a/dts/upstream/src/powerpc/hotfoot.dts b/dts/upstream/src/powerpc/hotfoot.dts
deleted file mode 100644
index b93bf2d..0000000
--- a/dts/upstream/src/powerpc/hotfoot.dts
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Device Tree Source for ESTeem 195E Hotfoot
- *
- * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "est,hotfoot";
- compatible = "est,hotfoot";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EP";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by zImage */
- timebase-frequency = <0>; /* Filled in by zImage */
- i-cache-line-size = <0x20>;
- d-cache-line-size = <0x20>;
- i-cache-size = <0x4000>;
- d-cache-size = <0x4000>;
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000>; /* Filled in by zImage */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- plb {
- compatible = "ibm,plb3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by zImage */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-405ep";
- dcr-reg = <0x010 0x002>;
- };
-
- MAL: mcmal {
- compatible = "ibm,mcmal-405ep", "ibm,mcmal";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <4>;
- num-rx-chans = <2>;
- interrupt-parent = <&UIC0>;
- interrupts = <
- 0xb 0x4 /* TXEOB */
- 0xc 0x4 /* RXEOB */
- 0xa 0x4 /* SERR */
- 0xd 0x4 /* TXDE */
- 0xe 0x4 /* RXDE */>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405ep", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0xef600000 0xef600000 0x00a00000>;
- dcr-reg = <0x0a0 0x005>;
- clock-frequency = <0>; /* Filled in by zImage */
-
- /* Hotfoot has UART0/UART1 swapped */
-
- UART0: serial@ef600400 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600400 0x00000008>;
- virtual-reg = <0xef600400>;
- clock-frequency = <0>; /* Filled in by zImage */
- current-speed = <0x9600>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- UART1: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by zImage */
- current-speed = <0x9600>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x0 0x4>;
- };
-
- IIC: i2c@ef600500 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ibm,iic-405ep", "ibm,iic";
- reg = <0xef600500 0x00000011>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
-
- rtc@68 {
- /* Actually a DS1339 */
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
-
- temp@4a {
- /* Not present on all boards */
- compatible = "national,lm75";
- reg = <0x4a>;
- };
- };
-
- GPIO: gpio@ef600700 {
- #gpio-cells = <2>;
- compatible = "ibm,ppc4xx-gpio";
- reg = <0xef600700 0x00000020>;
- gpio-controller;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- status {
- label = "Status";
- gpios = <&GPIO 1 0>;
- };
- radiorx {
- label = "Rx";
- gpios = <&GPIO 0xe 0>;
- };
- };
-
- EMAC0: ethernet@ef600800 {
- linux,network-index = <0x0>;
- device_type = "network";
- compatible = "ibm,emac-405ep", "ibm,emac";
- interrupt-parent = <&UIC0>;
- interrupts = <
- 0xf 0x4 /* Ethernet */
- 0x9 0x4 /* Ethernet Wake Up */>;
- local-mac-address = [000000000000]; /* Filled in by zImage */
- reg = <0xef600800 0x00000070>;
- mal-device = <&MAL>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <0x5dc>;
- rx-fifo-size = <0x1000>;
- tx-fifo-size = <0x800>;
- phy-mode = "mii";
- phy-map = <0x00000000>;
- };
-
- EMAC1: ethernet@ef600900 {
- linux,network-index = <0x1>;
- device_type = "network";
- compatible = "ibm,emac-405ep", "ibm,emac";
- interrupt-parent = <&UIC0>;
- interrupts = <
- 0x11 0x4 /* Ethernet */
- 0x9 0x4 /* Ethernet Wake Up */>;
- local-mac-address = [000000000000]; /* Filled in by zImage */
- reg = <0xef600900 0x00000070>;
- mal-device = <&MAL>;
- mal-tx-channel = <2>;
- mal-rx-channel = <1>;
- cell-index = <1>;
- max-frame-size = <0x5dc>;
- rx-fifo-size = <0x1000>;
- tx-fifo-size = <0x800>;
- mdio-device = <&EMAC0>;
- phy-mode = "mii";
- phy-map = <0x0000001>;
- };
- };
-
- EBC0: ebc {
- compatible = "ibm,ebc-405ep", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
-
- /* The ranges property is supplied by the bootwrapper
- * and is based on the firmware's configuration of the
- * EBC bridge
- */
- clock-frequency = <0>; /* Filled in by zImage */
-
- nor_flash@0 {
- compatible = "cfi-flash";
- bank-width = <2>;
- reg = <0x0 0xff800000 0x00800000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* This mapping is for the 8M flash
- 4M flash has all ofssets -= 4M,
- and FeatFS partition is not present */
- partition@0 {
- label = "Bootloader";
- reg = <0x7c0000 0x40000>;
- /* read-only; */
- };
- partition@1 {
- label = "Env_and_Config_Primary";
- reg = <0x400000 0x10000>;
- };
- partition@2 {
- label = "Kernel";
- reg = <0x420000 0x100000>;
- };
- partition@3 {
- label = "Filesystem";
- reg = <0x520000 0x2a0000>;
- };
- partition@4 {
- label = "Env_and_Config_Secondary";
- reg = <0x410000 0x10000>;
- };
- partition@5 {
- label = "FeatFS";
- reg = <0x000000 0x400000>;
- };
- partition@6 {
- label = "Bootloader_Env";
- reg = <0x7d0000 0x10000>;
- };
- };
- };
-
- PCI0: pci@ec000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
- primary;
- reg = <0xeec00000 0x00000008 /* Config space access */
- 0xeed80000 0x00000004 /* IACK */
- 0xeed80000 0x00000004 /* Special cycle */
- 0xef480000 0x00000040>; /* Internal registers */
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed. Chip supports a second
- * IO range but we don't use it for now
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
- 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- interrupt-parent = <&UIC0>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
- /* IDSEL 3 -- slot1 (optional) 27/29 A/B IRQ2/4 */
- 0x1800 0x0 0x0 0x1 &UIC0 0x1b 0x8
- 0x1800 0x0 0x0 0x2 &UIC0 0x1d 0x8
-
- /* IDSEL 4 -- slot0, 26/28 A/B IRQ1/3 */
- 0x2000 0x0 0x0 0x1 &UIC0 0x1a 0x8
- 0x2000 0x0 0x0 0x2 &UIC0 0x1c 0x8
- >;
- };
- };
-
- chosen {
- stdout-path = &UART0;
- };
-};
diff --git a/dts/upstream/src/powerpc/kilauea.dts b/dts/upstream/src/powerpc/kilauea.dts
deleted file mode 100644
index c07a752..0000000
--- a/dts/upstream/src/powerpc/kilauea.dts
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Device Tree Source for AMCC Kilauea (405EX)
- *
- * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "amcc,kilauea";
- compatible = "amcc,kilauea";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EX";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>; /* 16 kB */
- d-cache-size = <16384>; /* 16 kB */
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic-405ex", "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- CPM0: cpm {
- compatible = "ibm,cpm";
- dcr-access-method = "native";
- dcr-reg = <0x0b0 0x003>;
- unused-units = <0x00000000>;
- idle-doze = <0x02000000>;
- standby = <0xe3e74800>;
- };
-
- plb {
- compatible = "ibm,plb-405ex", "ibm,plb4";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
- dcr-reg = <0x010 0x002>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x5 0x4 /* ECC DED Error */
- 0x6 0x4>; /* ECC SEC Error */
- };
-
- CRYPTO: crypto@ef700000 {
- compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
- reg = <0xef700000 0x80400>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x17 0x2>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <2>;
- interrupt-parent = <&MAL0>;
- interrupts = <0x0 0x1 0x2 0x3 0x4>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
- /*RXEOB*/ 0x1 &UIC0 0xb 0x4
- /*SERR*/ 0x2 &UIC1 0x0 0x4
- /*TXDE*/ 0x3 &UIC1 0x1 0x4
- /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
- interrupt-map-mask = <0xffffffff>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405ex", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x80000000 0x80000000 0x10000000
- 0xef600000 0xef600000 0x00a00000
- 0xf0000000 0xf0000000 0x10000000>;
- dcr-reg = <0x0a0 0x005>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-405ex", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x5 0x1>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x04000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x001e0000>;
- };
- partition@1e0000 {
- label = "dtb";
- reg = <0x001e0000 0x00020000>;
- };
- partition@200000 {
- label = "root";
- reg = <0x00200000 0x00200000>;
- };
- partition@400000 {
- label = "user";
- reg = <0x00400000 0x03b60000>;
- };
- partition@3f60000 {
- label = "env";
- reg = <0x03f60000 0x00040000>;
- };
- partition@3fa0000 {
- label = "u-boot";
- reg = <0x03fa0000 0x00060000>;
- };
- };
-
- ndfc@1,0 {
- compatible = "ibm,ndfc";
- reg = <0x00000001 0x00000000 0x00002000>;
- ccr = <0x00001000>;
- bank-settings = <0x80002222>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- nand {
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x00100000>;
- };
- partition@100000 {
- label = "user";
- reg = <0x00000000 0x03f00000>;
- };
- };
- };
- };
-
- UART0: serial@ef600200 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600200 0x00000008>;
- virtual-reg = <0xef600200>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1a 0x4>;
- };
-
- UART1: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600400 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600400 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@68 {
- compatible = "dallas,ds1338";
- reg = <0x68>;
- };
-
- dtt@48 {
- compatible = "dallas,ds1775";
- reg = <0x48>;
- };
- };
-
- IIC1: i2c@ef600500 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600500 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x7 0x4>;
- };
-
- RGMII0: emac-rgmii@ef600b00 {
- compatible = "ibm,rgmii-405ex", "ibm,rgmii";
- reg = <0xef600b00 0x00000104>;
- has-mdio;
- };
-
- EMAC0: ethernet@ef600900 {
- linux,network-index = <0x0>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
- /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
- reg = <0xef600900 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600a00 {
- linux,network-index = <0x1>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
- /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
- reg = <0xef600a00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <1>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
- };
-
- PCIE0: pcie@a0000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0xa0000000 0x20000000 /* Config space access */
- 0xef000000 0x00001000>; /* Registers */
- dcr-reg = <0x040 0x020>;
- sdr-base = <0x400>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0x00 to 0x3f */
- bus-range = <0x0 0x3f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
- };
-
- PCIE1: pcie@c0000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
- primary;
- port = <0x1>; /* port number */
- reg = <0xc0000000 0x20000000 /* Config space access */
- 0xef001000 0x00001000>; /* Registers */
- dcr-reg = <0x060 0x020>;
- sdr-base = <0x440>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
- 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0x40 to 0x7f */
- bus-range = <0x40 0x7f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
- };
- };
-};
diff --git a/dts/upstream/src/powerpc/klondike.dts b/dts/upstream/src/powerpc/klondike.dts
deleted file mode 100644
index 9743217..0000000
--- a/dts/upstream/src/powerpc/klondike.dts
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Device Tree for Klondike (APM8018X) board.
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tanmay Inamdar <tinamdar@apm.com>
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "apm,klondike";
- compatible = "apm,klondike";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,apm8018x";
- reg = <0x00000000>;
- clock-frequency = <300000000>; /* Filled in by U-Boot */
- timebase-frequency = <300000000>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>; /* 16 kB */
- d-cache-size = <16384>; /* 16 kB */
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x010>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x010>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x010>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x010>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- plb {
- compatible = "ibm,plb4";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-apm8018x";
- dcr-reg = <0x010 0x002>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <16>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC1>;
- interrupts = </*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x1 0x4
- /*TXDE*/ 0x2 0x4
- /*RXDE*/ 0x3 0x4>;
- };
-
- POB0: opb {
- compatible = "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x20000000 0x20000000 0x30000000
- 0x50000000 0x50000000 0x10000000
- 0x60000000 0x60000000 0x10000000
- 0xFE000000 0xFE000000 0x00010000>;
- dcr-reg = <0x100 0x020>;
- clock-frequency = <300000000>; /* Filled in by U-Boot */
-
- RGMII0: emac-rgmii@400a2000 {
- compatible = "ibm,rgmii";
- reg = <0x400a2000 0x00000010>;
- has-mdio;
- };
-
- TAH0: emac-tah@400a3000 {
- compatible = "ibm,tah";
- reg = <0x400a3000 0x100>;
- };
-
- TAH1: emac-tah@400a4000 {
- compatible = "ibm,tah";
- reg = <0x400a4000 0x100>;
- };
-
- EMAC0: ethernet@400a0000 {
- compatible = "ibm,emac4", "ibm-emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
- reg = <0x400a0000 0x00000100>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0x0>;
- mal-rx-channel = <0x0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- phy-mode = "rgmii";
- phy-address = <0x2>;
- turbo = "no";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@400a1000 {
- compatible = "ibm,emac4", "ibm-emac4sync";
- status = "disabled";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
- reg = <0x400a1000 0x00000100>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <8>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- phy-mode = "rgmii";
- phy-address = <0x3>;
- turbo = "no";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- tah-device = <&TAH1>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- mdio-device = <&EMAC0>;
- };
- };
- };
-
- chosen {
- stdout-path = "/plb/opb/serial@50001000";
- };
-};
diff --git a/dts/upstream/src/powerpc/makalu.dts b/dts/upstream/src/powerpc/makalu.dts
deleted file mode 100644
index c473cd9..0000000
--- a/dts/upstream/src/powerpc/makalu.dts
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Device Tree Source for AMCC Makalu (405EX)
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "amcc,makalu";
- compatible = "amcc,makalu";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EX";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>; /* 16 kB */
- d-cache-size = <16384>; /* 16 kB */
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic-405ex", "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- plb {
- compatible = "ibm,plb-405ex", "ibm,plb4";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
- dcr-reg = <0x010 0x002>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x5 0x4 /* ECC DED Error */
- 0x6 0x4 /* ECC SEC Error */ >;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <2>;
- interrupt-parent = <&MAL0>;
- interrupts = <0x0 0x1 0x2 0x3 0x4>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
- /*RXEOB*/ 0x1 &UIC0 0xb 0x4
- /*SERR*/ 0x2 &UIC1 0x0 0x4
- /*TXDE*/ 0x3 &UIC1 0x1 0x4
- /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
- interrupt-map-mask = <0xffffffff>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405ex", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x80000000 0x80000000 0x10000000
- 0xef600000 0xef600000 0x00a00000
- 0xf0000000 0xf0000000 0x10000000>;
- dcr-reg = <0x0a0 0x005>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-405ex", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x5 0x1>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x04000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x00200000>;
- };
- partition@200000 {
- label = "root";
- reg = <0x00200000 0x00200000>;
- };
- partition@400000 {
- label = "user";
- reg = <0x00400000 0x03b60000>;
- };
- partition@3f60000 {
- label = "env";
- reg = <0x03f60000 0x00040000>;
- };
- partition@3fa0000 {
- label = "u-boot";
- reg = <0x03fa0000 0x00060000>;
- };
- };
- };
-
- UART0: serial@ef600200 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600200 0x00000008>;
- virtual-reg = <0xef600200>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1a 0x4>;
- };
-
- UART1: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600400 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600400 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- };
-
- IIC1: i2c@ef600500 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600500 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x7 0x4>;
- };
-
-
- RGMII0: emac-rgmii@ef600b00 {
- compatible = "ibm,rgmii-405ex", "ibm,rgmii";
- reg = <0xef600b00 0x00000104>;
- has-mdio;
- };
-
- EMAC0: ethernet@ef600900 {
- linux,network-index = <0x0>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
- /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
- reg = <0xef600900 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x0000003f>; /* Start at 6 */
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600a00 {
- linux,network-index = <0x1>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
- /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
- reg = <0xef600a00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <1>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
- };
-
- PCIE0: pcie@a0000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0xa0000000 0x20000000 /* Config space access */
- 0xef000000 0x00001000>; /* Registers */
- dcr-reg = <0x040 0x020>;
- sdr-base = <0x400>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
- 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0x00 to 0x3f */
- bus-range = <0x0 0x3f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
- };
-
- PCIE1: pcie@c0000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
- primary;
- port = <0x1>; /* port number */
- reg = <0xc0000000 0x20000000 /* Config space access */
- 0xef001000 0x00001000>; /* Registers */
- dcr-reg = <0x060 0x020>;
- sdr-base = <0x440>;
-
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
- 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
-
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
-
- /* This drives busses 0x40 to 0x7f */
- bus-range = <0x40 0x7f>;
-
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
- };
- };
-};
diff --git a/dts/upstream/src/powerpc/obs600.dts b/dts/upstream/src/powerpc/obs600.dts
deleted file mode 100644
index d10b041..0000000
--- a/dts/upstream/src/powerpc/obs600.dts
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * Device Tree Source for PlatHome OpenBlockS 600 (405EX)
- *
- * Copyright 2011 Ben Herrenschmidt, IBM Corp.
- *
- * Based on Kilauea by:
- *
- * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "PlatHome,OpenBlockS 600";
- compatible = "plathome,obs600";
- dcr-parent = <&{/cpus/cpu@0}>;
-
- aliases {
- ethernet0 = &EMAC0;
- ethernet1 = &EMAC1;
- serial0 = &UART0;
- serial1 = &UART1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,405EX";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <16384>; /* 16 kB */
- d-cache-size = <16384>; /* 16 kB */
- dcr-controller;
- dcr-access-method = "native";
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
-
- UIC0: interrupt-controller {
- compatible = "ibm,uic-405ex", "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
-
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic-405ex","ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- CPM0: cpm {
- compatible = "ibm,cpm";
- dcr-access-method = "native";
- dcr-reg = <0x0b0 0x003>;
- unused-units = <0x00000000>;
- idle-doze = <0x02000000>;
- standby = <0xe3e74800>;
- };
-
- plb {
- compatible = "ibm,plb-405ex", "ibm,plb4";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: memory-controller {
- compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
- dcr-reg = <0x010 0x002>;
- interrupt-parent = <&UIC2>;
- interrupts = <0x5 0x4 /* ECC DED Error */
- 0x6 0x4>; /* ECC SEC Error */
- };
-
- CRYPTO: crypto@ef700000 {
- compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
- reg = <0xef700000 0x80400>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x17 0x2>;
- };
-
- MAL0: mcmal {
- compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <2>;
- num-rx-chans = <2>;
- interrupt-parent = <&MAL0>;
- interrupts = <0x0 0x1 0x2 0x3 0x4>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
- /*RXEOB*/ 0x1 &UIC0 0xb 0x4
- /*SERR*/ 0x2 &UIC1 0x0 0x4
- /*TXDE*/ 0x3 &UIC1 0x1 0x4
- /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
- interrupt-map-mask = <0xffffffff>;
- };
-
- POB0: opb {
- compatible = "ibm,opb-405ex", "ibm,opb";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x80000000 0x80000000 0x10000000
- 0xef600000 0xef600000 0x00a00000
- 0xf0000000 0xf0000000 0x10000000>;
- dcr-reg = <0x0a0 0x005>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc-405ex", "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- interrupts = <0x5 0x1>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x08000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel + initrd";
- reg = <0x00000000 0x03de0000>;
- };
- partition@3de0000 {
- label = "user config area";
- reg = <0x03de0000 0x00080000>;
- };
- partition@3e60000 {
- label = "user program area";
- reg = <0x03e60000 0x04000000>;
- };
- partition@7e60000 {
- label = "flat device tree";
- reg = <0x07e60000 0x00080000>;
- };
- partition@7ee0000 {
- label = "test program";
- reg = <0x07ee0000 0x00080000>;
- };
- partition@7f60000 {
- label = "u-boot env";
- reg = <0x07f60000 0x00040000>;
- };
- partition@7fa0000 {
- label = "u-boot";
- reg = <0x07fa0000 0x00060000>;
- };
- };
- };
-
- UART0: serial@ef600200 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600200 0x00000008>;
- virtual-reg = <0xef600200>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1a 0x4>;
- };
-
- UART1: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
- };
-
- IIC0: i2c@ef600400 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600400 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@68 {
- compatible = "dallas,ds1340";
- reg = <0x68>;
- };
- };
-
- IIC1: i2c@ef600500 {
- compatible = "ibm,iic-405ex", "ibm,iic";
- reg = <0xef600500 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x7 0x4>;
- };
-
- RGMII0: emac-rgmii@ef600b00 {
- compatible = "ibm,rgmii-405ex", "ibm,rgmii";
- reg = <0xef600b00 0x00000104>;
- has-mdio;
- };
-
- EMAC0: ethernet@ef600900 {
- linux,network-index = <0x0>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
- /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
- reg = <0xef600900 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- EMAC1: ethernet@ef600a00 {
- linux,network-index = <0x1>;
- device_type = "network";
- compatible = "ibm,emac-405ex", "ibm,emac4sync";
- interrupt-parent = <&EMAC1>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
- /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
- reg = <0xef600a00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <1>;
- mal-rx-channel = <1>;
- cell-index = <1>;
- max-frame-size = <9000>;
- rx-fifo-size = <4096>;
- tx-fifo-size = <2048>;
- rx-fifo-size-gige = <16384>;
- tx-fifo-size-gige = <16384>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <1>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
- };
-
- GPIO: gpio@ef600800 {
- device_type = "gpio";
- compatible = "ibm,gpio-405ex", "ibm,ppc4xx-gpio";
- reg = <0xef600800 0x50>;
- };
- };
- };
- chosen {
- stdout-path = "/plb/opb/serial@ef600200";
- };
-};
diff --git a/dts/upstream/src/riscv/allwinner/sun20i-d1-clockworkpi-v3.14.dts b/dts/upstream/src/riscv/allwinner/sun20i-d1-clockworkpi-v3.14.dts
new file mode 100644
index 0000000..750aec6
--- /dev/null
+++ b/dts/upstream/src/riscv/allwinner/sun20i-d1-clockworkpi-v3.14.dts
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
+
+#include <dt-bindings/gpio/gpio.h>
+
+/dts-v1/;
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-common-regulators.dtsi"
+
+/ {
+ model = "ClockworkPi v3.14 (R-01)";
+ compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &ap6256;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <®_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpu>;
+};
+
+&dcxo {
+ clock-frequency = <24000000>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pb10_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ axp221: pmic@34 {
+ compatible = "x-powers,axp228", "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ ac_power_supply: ac-power {
+ compatible = "x-powers,axp221-ac-power-supply";
+ };
+
+ axp_adc: adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+
+ battery_power_supply: battery-power {
+ compatible = "x-powers,axp221-battery-power-supply";
+ };
+
+ axp_gpio: gpio {
+ compatible = "x-powers,axp221-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "sys-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "sys-1v8";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aud-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "disp-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "vdd-wifi";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ /* DLDO1 and ELDO1-3 are connected in parallel. */
+ reg_dldo1: dldo1 {
+ regulator-name = "vbat-wifi-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* DLDO2-DLDO4 are connected in parallel. */
+ reg_dldo2: dldo2 {
+ regulator-name = "vcc-3v3-ext-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "vcc-3v3-ext-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "vcc-3v3-ext-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "vbat-wifi-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "vbat-wifi-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "vbat-wifi-d";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ usb_power_supply: usb-power {
+ compatible = "x-powers,axp221-usb-power-supply";
+ status = "disabled";
+ };
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_aldo3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ap6256: wifi@1 {
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pg-supply = <®_ldoa>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ interrupt-parent = <&pio>;
+ interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
+ device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
+ shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
+ max-speed = <1500000>;
+ vbat-supply = <®_dldo1>;
+ vddio-supply = <®_aldo3>;
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus_power-supply = <&ac_power_supply>;
+ usb1_vbus-supply = <®_vcc>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/riscv/allwinner/sun20i-d1-devterm-v3.14.dts b/dts/upstream/src/riscv/allwinner/sun20i-d1-devterm-v3.14.dts
new file mode 100644
index 0000000..bc5c84f
--- /dev/null
+++ b/dts/upstream/src/riscv/allwinner/sun20i-d1-devterm-v3.14.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
+
+#include "sun20i-d1-clockworkpi-v3.14.dts"
+
+/ {
+ model = "Clockwork DevTerm (R-01)";
+ compatible = "clockwork,r-01-devterm-v3.14",
+ "clockwork,r-01-clockworkpi-v3.14",
+ "allwinner,sun20i-d1";
+
+ fan {
+ compatible = "gpio-fan";
+ gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
+ gpio-fan,speed-map = <0 0>,
+ <6000 1>;
+ #cooling-cells = <2>;
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
+ scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@54 {
+ compatible = "ti,adc101c";
+ reg = <0x54>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
+ vref-supply = <®_dldo2>;
+ #io-channel-cells = <1>;
+ };
+ };
+};
diff --git a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
index 5a9d7f5..e4175ad 100644
--- a/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
+++ b/dts/upstream/src/riscv/allwinner/sunxi-d1s-t113.dtsi
@@ -396,6 +396,17 @@
ranges;
#address-cells = <1>;
#size-cells = <1>;
+
+ regulators@3000150 {
+ compatible = "allwinner,sun20i-d1-system-ldos";
+ reg = <0x3000150 0x4>;
+
+ reg_ldoa: ldoa {
+ };
+
+ reg_ldob: ldob {
+ };
+ };
};
dma: dma-controller@3002000 {
diff --git a/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire-fabric.dtsi b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire-fabric.dtsi
new file mode 100644
index 0000000..e153eaf
--- /dev/null
+++ b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire-fabric.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ fabric-bus@40000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
+ <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
+ <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
+ <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
+ <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
+
+ cape_gpios_p8: gpio@41100000 {
+ compatible = "microchip,coregpio-rtl-v3";
+ reg = <0x0 0x41100000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <16>;
+ gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
+ "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
+ "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
+ "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
+ };
+
+ cape_gpios_p9: gpio@41200000 {
+ compatible = "microchip,coregpio-rtl-v3";
+ reg = <0x0 0x41200000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <20>;
+ gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
+ "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
+ "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
+ "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
+ "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
+ };
+
+ hsi_gpios: gpio@44000000 {
+ compatible = "microchip,coregpio-rtl-v3";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <20>;
+ gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
+ "B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
+ "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
+ "XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
+ "XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
+ "XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
+ "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
+ };
+ };
+
+ refclk_ccc: cccrefclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
+&ccc_nw {
+ clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+ <&refclk_ccc>, <&refclk_ccc>;
+ clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+ "dll0_ref", "dll1_ref";
+ status = "okay";
+};
diff --git a/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts
new file mode 100644
index 0000000..47cf693
--- /dev/null
+++ b/dts/upstream/src/riscv/microchip/mpfs-beaglev-fire.dts
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mpfs.dtsi"
+#include "mpfs-beaglev-fire-fabric.dtsi"
+
+/* Clock frequency (in Hz) of MTIMER */
+#define MTIMER_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "BeagleBoard BeagleV-Fire";
+ compatible = "beagle,beaglev-fire", "microchip,mpfs";
+
+ aliases {
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ status = "okay";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss: hss-buffer@103fc00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10 0x3fc00000 0x0 0x400000>;
+ no-map;
+ };
+ };
+
+ imx219_clk: camera-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ imx219_vana: fixedregulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vana";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ imx219_vdig: fixedregulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vdig";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ imx219_vddl: fixedregulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vddl";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ ngpios=<32>;
+ gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
+ "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
+ "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
+ "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
+ "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
+ "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
+ "P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
+ "M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
+ status = "okay";
+
+ vio-enable-hog {
+ gpio-hog;
+ gpios = <30 30>;
+ output-high;
+ line-name = "VIO_ENABLE";
+ };
+
+ sd-det-hog {
+ gpio-hog;
+ gpios = <31 31>;
+ input;
+ line-name = "SD_DET";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&imx219_clk>;
+ VANA-supply = <&imx219_vana>; /* 2.8v */
+ VDIG-supply = <&imx219_vdig>; /* 1.8v */
+ VDDL-supply = <&imx219_vddl>; /* 1.2v */
+
+ port {
+ imx219_0: endpoint {
+ data-lanes = <1 2>;
+ clock-noncontinuous;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&mac0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&mmuart0 {
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+ clock-frequency = <50000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ microchip,bitstream-flash = <&sys_ctrl_flash>;
+ status = "okay";
+};
+
+&syscontroller_qspi {
+ status = "okay";
+
+ sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+};
diff --git a/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts b/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts
index 49b4b9c..80cb017 100644
--- a/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts
+++ b/dts/upstream/src/riscv/sophgo/sg2042-milkv-pioneer.dts
@@ -14,6 +14,18 @@
};
};
+&cgi_main {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll0 {
+ clock-frequency = <25000000>;
+};
+
+&cgi_dpll1 {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/dts/upstream/src/riscv/sophgo/sg2042.dtsi b/dts/upstream/src/riscv/sophgo/sg2042.dtsi
index 81fda31..34c802b 100644
--- a/dts/upstream/src/riscv/sophgo/sg2042.dtsi
+++ b/dts/upstream/src/riscv/sophgo/sg2042.dtsi
@@ -4,8 +4,10 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
+#include <dt-bindings/clock/sophgo,sg2042-pll.h>
+#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
-
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
@@ -20,12 +22,60 @@
serial0 = &uart0;
};
+ cgi_main: oscillator0 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_main";
+ #clock-cells = <0>;
+ };
+
+ cgi_dpll0: oscillator1 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_dpll0";
+ #clock-cells = <0>;
+ };
+
+ cgi_dpll1: oscillator2 {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi_dpll1";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ pllclk: clock-controller@70300100c0 {
+ compatible = "sophgo,sg2042-pll";
+ reg = <0x70 0x300100c0 0x0 0x40>;
+ clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
+ clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
+ #clock-cells = <1>;
+ };
+
+ rpgate: clock-controller@7030010368 {
+ compatible = "sophgo,sg2042-rpgate";
+ reg = <0x70 0x30010368 0x0 0x98>;
+ clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
+ clock-names = "rpgate";
+ #clock-cells = <1>;
+ };
+
+ clkgen: clock-controller@7030012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x70 0x30012000 0x0 0x1000>;
+ clocks = <&pllclk MPLL_CLK>,
+ <&pllclk FPLL_CLK>,
+ <&pllclk DPLL0_CLK>,
+ <&pllclk DPLL1_CLK>;
+ clock-names = "mpll",
+ "fpll",
+ "dpll0",
+ "dpll1";
+ #clock-cells = <1>;
+ };
+
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
@@ -341,6 +391,9 @@
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rstgen RST_UART0>;
diff --git a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
index 68d1671..c7771b3 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110-common.dtsi
@@ -294,6 +294,20 @@
status = "okay";
};
+&pcie0 {
+ perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+ phys = <&pciephy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+};
+
+&pcie1 {
+ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ phys = <&pciephy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+};
+
&pwmdac {
pinctrl-names = "default";
pinctrl-0 = <&pwmdac_pins>;
@@ -321,16 +335,13 @@
#size-cells = <1>;
spl@0 {
- reg = <0x0 0x80000>;
+ reg = <0x0 0xf0000>;
};
uboot-env@f0000 {
reg = <0xf0000 0x10000>;
};
uboot@100000 {
- reg = <0x100000 0x400000>;
- };
- reserved-data@600000 {
- reg = <0x600000 0xa00000>;
+ reg = <0x100000 0xf00000>;
};
};
};
@@ -354,6 +365,12 @@
};
};
+&syscrg {
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+ <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+ assigned-clock-rates = <500000000>, <1500000000>;
+};
+
&sysgpio {
i2c0_pins: i2c0-0 {
i2c-pins {
@@ -476,6 +493,54 @@
};
};
+ pcie0_pins: pcie0-0 {
+ clkreq-pins {
+ pinmux = <GPIOMUX(27, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ wake-pins {
+ pinmux = <GPIOMUX(32, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_pins: pcie1-0 {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
pwmdac_pins: pwmdac-0 {
pwmdac-pins {
pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
index fa0eac7..5cb9e99 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
@@ -17,6 +17,13 @@
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
&phy0 {
motorcomm,tx-clk-adj-enabled;
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
new file mode 100644
index 0000000..b720cdd
--- /dev/null
+++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+ model = "Pine64 Star64";
+ compatible = "pine64,star64", "starfive,jh7110";
+ aliases {
+ ethernet1 = &gmac1;
+ };
+};
+
+&gmac0 {
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+&gmac1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&phy0 {
+ rx-internal-delay-ps = <1900>;
+ tx-internal-delay-ps = <1500>;
+ motorcomm,rx-clk-drv-microamp = <2910>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-10-inverted;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+};
+
+&phy1 {
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <300>;
+ motorcomm,rx-clk-drv-microamp = <2910>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-10-inverted;
+ motorcomm,tx-clk-100-inverted;
+};
diff --git a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
index 9d70f21..18f38fc 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -32,3 +32,11 @@
&mmc0 {
non-removable;
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index 1804719..0d83393 100644
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -387,12 +387,13 @@
};
uart0: serial@10000000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
<&syscrg JH7110_SYSCLK_UART0_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>,
+ <&syscrg JH7110_SYSRST_UART0_CORE>;
interrupts = <32>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -400,12 +401,13 @@
};
uart1: serial@10010000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
<&syscrg JH7110_SYSCLK_UART1_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>,
+ <&syscrg JH7110_SYSRST_UART1_CORE>;
interrupts = <33>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -413,12 +415,13 @@
};
uart2: serial@10020000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x10020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
<&syscrg JH7110_SYSCLK_UART2_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>,
+ <&syscrg JH7110_SYSRST_UART2_CORE>;
interrupts = <34>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -642,12 +645,13 @@
};
uart3: serial@12000000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
<&syscrg JH7110_SYSCLK_UART3_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>,
+ <&syscrg JH7110_SYSRST_UART3_CORE>;
interrupts = <45>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -655,12 +659,13 @@
};
uart4: serial@12010000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12010000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
<&syscrg JH7110_SYSCLK_UART4_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>,
+ <&syscrg JH7110_SYSRST_UART4_CORE>;
interrupts = <46>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -668,12 +673,13 @@
};
uart5: serial@12020000 {
- compatible = "snps,dw-apb-uart";
+ compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
reg = <0x0 0x12020000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
<&syscrg JH7110_SYSCLK_UART5_APB>;
clock-names = "baudclk", "apb_pclk";
- resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>,
+ <&syscrg JH7110_SYSRST_UART5_CORE>;
interrupts = <47>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -1214,5 +1220,91 @@
#reset-cells = <1>;
power-domains = <&pwrc JH7110_PD_VOUT>;
};
+
+ pcie0: pcie@940000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x9 0x40000000 0x0 0x1000000>,
+ <0x0 0x2b000000 0x0 0x100000>;
+ reg-names = "cfg", "apb";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
+ interrupts = <56>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+ msi-controller;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
+ <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE0_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pcie1: pcie@9c0000000 {
+ compatible = "starfive,jh7110-pcie";
+ reg = <0x9 0xc0000000 0x0 0x1000000>,
+ <0x0 0x2c000000 0x0 0x100000>;
+ reg-names = "cfg", "apb";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
+ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
+ interrupts = <57>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
+ msi-controller;
+ device_type = "pci";
+ starfive,stg-syscon = <&stg_syscon>;
+ bus-range = <0x0 0xff>;
+ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+ <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
+ <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+ clock-names = "noc", "tl", "axi_mst0", "apb";
+ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
+ <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+ <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+ <&stgcrg JH7110_STGRST_PCIE1_APB>;
+ reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+ status = "disabled";
+
+ pcie_intc1: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
};
};
diff --git a/dts/upstream/src/riscv/thead/th1520.dtsi b/dts/upstream/src/riscv/thead/th1520.dtsi
index d2fa258..3c99740 100644
--- a/dts/upstream/src/riscv/thead/th1520.dtsi
+++ b/dts/upstream/src/riscv/thead/th1520.dtsi
@@ -122,6 +122,87 @@
};
};
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmcounters =
+ <0x00003 0x00003 0x0007fff8>,
+ <0x00004 0x00004 0x0007fff8>,
+ <0x00005 0x00005 0x0007fff8>,
+ <0x00006 0x00006 0x0007fff8>,
+ <0x00007 0x00007 0x0007fff8>,
+ <0x00008 0x00008 0x0007fff8>,
+ <0x00009 0x00009 0x0007fff8>,
+ <0x0000a 0x0000a 0x0007fff8>,
+ <0x10000 0x10000 0x0007fff8>,
+ <0x10001 0x10001 0x0007fff8>,
+ <0x10002 0x10002 0x0007fff8>,
+ <0x10003 0x10003 0x0007fff8>,
+ <0x10010 0x10010 0x0007fff8>,
+ <0x10011 0x10011 0x0007fff8>,
+ <0x10012 0x10012 0x0007fff8>,
+ <0x10013 0x10013 0x0007fff8>;
+ riscv,event-to-mhpmevent =
+ <0x00003 0x00000000 0x00000001>,
+ <0x00004 0x00000000 0x00000002>,
+ <0x00006 0x00000000 0x00000006>,
+ <0x00005 0x00000000 0x00000007>,
+ <0x00007 0x00000000 0x00000008>,
+ <0x00008 0x00000000 0x00000009>,
+ <0x00009 0x00000000 0x0000000a>,
+ <0x0000a 0x00000000 0x0000000b>,
+ <0x10000 0x00000000 0x0000000c>,
+ <0x10001 0x00000000 0x0000000d>,
+ <0x10002 0x00000000 0x0000000e>,
+ <0x10003 0x00000000 0x0000000f>,
+ <0x10010 0x00000000 0x00000010>,
+ <0x10011 0x00000000 0x00000011>,
+ <0x10012 0x00000000 0x00000012>,
+ <0x10013 0x00000000 0x00000013>;
+ riscv,raw-event-to-mhpmcounters =
+ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
+ <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
+ };
+
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_24m";
diff --git a/env/common.c b/env/common.c
index 8d47d72..6cba7f1 100644
--- a/env/common.c
+++ b/env/common.c
@@ -401,7 +401,15 @@
* Special use-case: import from default environment
* (and use \0 as a separator)
*/
- flags |= H_NOCLEAR | H_DEFAULT;
+
+ /*
+ * When vars are passed remove variables that are not in
+ * the default environment.
+ */
+ if (!nvars)
+ flags |= H_NOCLEAR;
+
+ flags |= H_DEFAULT;
return himport_r(&env_htab, default_environment,
sizeof(default_environment), '\0',
flags, 0, nvars, vars);
diff --git a/env/mmc.c b/env/mmc.c
index 0338aa6..e2f8e7e 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -53,11 +53,74 @@
#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
+
+static int mmc_env_partition_by_name(struct blk_desc *desc, const char *str,
+ struct disk_partition *info)
+{
+ int i, ret;
+
+ for (i = 1;; i++) {
+ ret = part_get_info(desc, i, info);
+ if (ret < 0)
+ return ret;
+
+ if (!strncmp((const char *)info->name, str, sizeof(info->name)))
+ return 0;
+ }
+}
+
+/*
+ * Look for one or two partitions with the U-Boot environment GUID.
+ *
+ * If *copy is 0, return the first such partition.
+ *
+ * If *copy is 1 on entry and two partitions are found, return the
+ * second partition and set *copy = 0.
+ *
+ * If *copy is 1 on entry and only one partition is found, return that
+ * partition, leaving *copy unmodified.
+ */
+static int mmc_env_partition_by_guid(struct blk_desc *desc, struct disk_partition *info,
+ int *copy)
+{
+ const efi_guid_t env_guid = PARTITION_U_BOOT_ENVIRONMENT;
+ efi_guid_t type_guid;
+ int i, ret, found = 0;
+ struct disk_partition dp;
+
+ for (i = 1;; i++) {
+ ret = part_get_info(desc, i, &dp);
+ if (ret < 0)
+ break;
+
+ uuid_str_to_bin(disk_partition_type_guid(&dp), type_guid.b, UUID_STR_FORMAT_GUID);
+ if (!memcmp(&env_guid, &type_guid, sizeof(efi_guid_t))) {
+ memcpy(info, &dp, sizeof(dp));
+ /* If *copy is 0, we are only looking for the first partition. */
+ if (*copy == 0)
+ return 0;
+ /* This was the second such partition. */
+ if (found) {
+ *copy = 0;
+ return 0;
+ }
+ found = 1;
+ }
+ }
+
+ /* The loop ended after finding at most one matching partition. */
+ if (found)
+ ret = 0;
+ return ret;
+}
+
+
static inline int mmc_offset_try_partition(const char *str, int copy, s64 *val)
{
struct disk_partition info;
struct blk_desc *desc;
- int len, i, ret;
+ lbaint_t len;
+ int ret;
char dev_str[4];
snprintf(dev_str, sizeof(dev_str), "%d", mmc_get_env_dev());
@@ -65,28 +128,24 @@
if (ret < 0)
return (ret);
- for (i = 1;;i++) {
- ret = part_get_info(desc, i, &info);
- if (ret < 0)
- return ret;
-
- if (str && !strncmp((const char *)info.name, str, sizeof(info.name)))
- break;
-#ifdef CONFIG_PARTITION_TYPE_GUID
- if (!str) {
- const efi_guid_t env_guid = PARTITION_U_BOOT_ENVIRONMENT;
- efi_guid_t type_guid;
-
- uuid_str_to_bin(info.type_guid, type_guid.b, UUID_STR_FORMAT_GUID);
- if (!memcmp(&env_guid, &type_guid, sizeof(efi_guid_t)))
- break;
- }
-#endif
+ if (str) {
+ ret = mmc_env_partition_by_name(desc, str, &info);
+ } else if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) && !str) {
+ ret = mmc_env_partition_by_guid(desc, &info, ©);
}
+ if (ret < 0)
+ return ret;
/* round up to info.blksz */
len = DIV_ROUND_UP(CONFIG_ENV_SIZE, info.blksz);
+ if ((1 + copy) * len > info.size) {
+ printf("Partition '%s' [0x"LBAF"; 0x"LBAF"] too small for %senvironment, required size 0x"LBAF" blocks\n",
+ (const char*)info.name, info.start, info.size,
+ copy ? "two copies of " : "", (1 + copy)*len);
+ return -ENOSPC;
+ }
+
/* use the top of the partion for the environment */
*val = (info.start + info.size - (1 + copy) * len) * info.blksz;
diff --git a/env/sf.c b/env/sf.c
index 906b85b..21ac0c2 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -16,7 +16,7 @@
#include <spi_flash.h>
#include <search.h>
#include <errno.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <dm/device-internal.h>
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 1149a3b..350cff0 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -7,7 +7,7 @@
#include <config.h>
#include <malloc.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/time.h>
#include "btrfs.h"
#include "crypto/hash.h"
diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h
index 02173de..4596b9d 100644
--- a/fs/btrfs/compat.h
+++ b/fs/btrfs/compat.h
@@ -5,7 +5,7 @@
#include <linux/errno.h>
#include <fs_internal.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
/* Provide a compatibility layer to make code syncing easier */
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index 34d9d53..14efe72 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <fs_internal.h>
#include <log.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <memalign.h>
#include "kernel-shared/btrfs_tree.h"
#include "common/rbtree-utils.h"
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 52152a2..76f7102 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2181,13 +2181,18 @@
struct ext2fs_node *diro = node;
int status;
loff_t actread;
+ size_t alloc_size;
if (!diro->inode_read) {
status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
if (status == 0)
return NULL;
}
- symlink = zalloc(le32_to_cpu(diro->inode.size) + 1);
+
+ if (__builtin_add_overflow(le32_to_cpu(diro->inode.size), 1, &alloc_size))
+ return NULL;
+
+ symlink = zalloc(alloc_size);
if (!symlink)
return NULL;
@@ -2383,6 +2388,20 @@
fs->inodesz = 128;
fs->gdsize = 32;
} else {
+ int missing = __le32_to_cpu(data->sblock.feature_incompat) &
+ ~(EXT4_FEATURE_INCOMPAT_SUPP |
+ EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO);
+
+ if (missing) {
+ /*
+ * This code used to be relaxed about feature flags.
+ * We don't stop the mount to avoid breaking existing setups.
+ * But, incompatible features can cause serious read errors.
+ */
+ log_err("fs uses incompatible features: %08x, ignoring\n",
+ missing);
+ }
+
debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n",
__le32_to_cpu(data->sblock.feature_compatibility),
__le32_to_cpu(data->sblock.feature_incompat),
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index 84500e9..3467520 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -24,6 +24,7 @@
#include <ext4fs.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <linux/compat.h>
#include <linux/errno.h>
#if defined(CONFIG_EXT4_WRITE)
#include "ext4_journal.h"
@@ -43,9 +44,7 @@
static inline void *zalloc(size_t size)
{
- void *p = memalign(ARCH_DMA_MINALIGN, size);
- memset(p, 0, size);
- return p;
+ return kzalloc(size, 0);
}
int ext4fs_read_inode(struct ext2_data *data, int ino,
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index a2dfff8..d109ed6 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -866,6 +866,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
bool store_link_in_inode = false;
memset(filename, 0x00, 256);
+ int missing_feat;
if (type != FILETYPE_REG && type != FILETYPE_SYMLINK)
return -1;
@@ -879,8 +880,15 @@
return -1;
}
- if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_METADATA_CSUM) {
- printf("Unsupported feature metadata_csum found, not writing.\n");
+ missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP;
+ if (missing_feat) {
+ log_err("Unsupported features found %08x, not writing.\n", missing_feat);
+ return -1;
+ }
+
+ missing_feat = le32_to_cpu(fs->sb->feature_ro_compat) & ~EXT4_FEATURE_RO_COMPAT_SUPP;
+ if (missing_feat) {
+ log_err("Unsupported RO compat features found %08x, not writing.\n", missing_feat);
return -1;
}
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index da59cb0..15587e9 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -27,7 +27,7 @@
#include <div64.h>
#include <malloc.h>
#include <part.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
int ext4fs_symlinknest;
struct ext_filesystem ext_fs;
diff --git a/fs/fs.c b/fs/fs.c
index 0c47943..4bc28d1 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -526,12 +526,11 @@
return ret;
}
-#ifdef CONFIG_LMB
+#if CONFIG_IS_ENABLED(LMB)
/* Check if a file may be read to the given address */
static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset,
loff_t len, struct fstype_info *info)
{
- struct lmb lmb;
int ret;
loff_t size;
loff_t read_len;
@@ -550,10 +549,9 @@
if (len && len < read_len)
read_len = len;
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
- lmb_dump_all(&lmb);
+ lmb_dump_all();
- if (lmb_alloc_addr(&lmb, addr, read_len) == addr)
+ if (lmb_alloc_addr(addr, read_len) == addr)
return 0;
log_err("** Reading file would overwrite reserved memory **\n");
@@ -568,7 +566,7 @@
void *buf;
int ret;
-#ifdef CONFIG_LMB
+#if CONFIG_IS_ENABLED(LMB)
if (do_lmb_check) {
ret = fs_read_lmb_check(filename, addr, offset, len, info);
if (ret)
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index 773b583..76f1a71 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -28,7 +28,7 @@
if (fd < 0)
return fd;
ret = os_lseek(fd, pos, OS_SEEK_SET);
- if (ret == -1) {
+ if (ret < 0) {
os_close(fd);
return ret;
}
@@ -65,14 +65,14 @@
if (fd < 0)
return fd;
ret = os_lseek(fd, pos, OS_SEEK_SET);
- if (ret == -1) {
+ if (ret < 0) {
os_close(fd);
return ret;
}
size = os_write(fd, buffer, towrite);
os_close(fd);
- if (size == -1) {
+ if (size < 0) {
ret = -1;
} else {
ret = 0;
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index 1430e67..b931401 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -24,7 +24,12 @@
#include "sqfs_filesystem.h"
#include "sqfs_utils.h"
+#define MAX_SYMLINK_NEST 8
+
static struct squashfs_ctxt ctxt;
+static int symlinknest;
+
+static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp);
static int sqfs_disk_read(__u32 block, __u32 nr_blocks, void *buf)
{
@@ -422,8 +427,10 @@
char *resolved, *target;
u32 sz;
+ if (__builtin_add_overflow(get_unaligned_le32(&sym->symlink_size), 1, &sz))
+ return NULL;
+
- sz = get_unaligned_le32(&sym->symlink_size);
- target = malloc(sz + 1);
+ target = malloc(sz);
if (!target)
return NULL;
@@ -431,9 +438,9 @@
* There is no trailling null byte in the symlink's target path, so a
* copy is made and a '\0' is added at its end.
*/
- target[sz] = '\0';
+ target[sz - 1] = '\0';
/* Get target name (relative path) */
- strncpy(target, sym->symlink, sz);
+ strncpy(target, sym->symlink, sz - 1);
/* Relative -> absolute path conversion */
resolved = sqfs_get_abs_path(base_path, target);
@@ -472,6 +479,8 @@
/* Start by root inode */
table = sqfs_find_inode(dirs->inode_table, le32_to_cpu(sblk->inodes),
sblk->inodes, sblk->block_size);
+ if (!table)
+ return -EINVAL;
dir = (struct squashfs_dir_inode *)table;
ldir = (struct squashfs_ldir_inode *)table;
@@ -506,7 +515,7 @@
goto out;
}
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, token_list[j]);
if (!ret)
break;
@@ -527,10 +536,17 @@
/* Get reference to inode in the inode table */
table = sqfs_find_inode(dirs->inode_table, new_inode_number,
sblk->inodes, sblk->block_size);
+ if (!table)
+ return -EINVAL;
dir = (struct squashfs_dir_inode *)table;
/* Check for symbolic link and inode type sanity */
if (get_unaligned_le16(&dir->inode_type) == SQFS_SYMLINK_TYPE) {
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ ret = -ELOOP;
+ goto out;
+ }
+
sym = (struct squashfs_symlink_inode *)table;
/* Get first j + 1 tokens */
path = sqfs_concat_tokens(token_list, j + 1);
@@ -551,8 +567,11 @@
ret = -ENOMEM;
goto out;
}
- /* Concatenate remaining tokens and symlink's target */
- res = malloc(strlen(rem) + strlen(target) + 1);
+ /*
+ * Concatenate remaining tokens and symlink's target.
+ * Allocate enough space for rem, target, '/' and '\0'.
+ */
+ res = malloc(strlen(rem) + strlen(target) + 2);
if (!res) {
ret = -ENOMEM;
goto out;
@@ -878,7 +897,7 @@
return metablks_count;
}
-int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp)
{
unsigned char *inode_table = NULL, *dir_table = NULL;
int j, token_count = 0, ret = 0, metablks_count;
@@ -973,8 +992,20 @@
return ret;
}
+int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+ symlinknest = 0;
+ return sqfs_opendir_nest(filename, dirsp);
+}
+
int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
{
+ symlinknest = 0;
+ return sqfs_readdir_nest(fs_dirs, dentp);
+}
+
+static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
struct squashfs_super_block *sblk = ctxt.sblk;
struct squashfs_dir_stream *dirs;
struct squashfs_lreg_inode *lreg;
@@ -1023,6 +1054,8 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+ if (!ipos)
+ return -SQFS_STOP_READDIR;
base = (struct squashfs_base_inode *)ipos;
@@ -1317,8 +1350,8 @@
return datablk_count;
}
-int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len,
- loff_t *actread)
+static int sqfs_read_nest(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actread)
{
char *dir = NULL, *fragment_block, *datablock = NULL;
char *fragment = NULL, *file = NULL, *resolved, *data;
@@ -1348,11 +1381,11 @@
}
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
sqfs_split_path(&file, &dir, filename);
- ret = sqfs_opendir(dir, &dirsp);
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
goto out;
}
@@ -1360,7 +1393,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
/* For now, only regular files are able to be loaded */
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1379,6 +1412,10 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+ if (!ipos) {
+ ret = -EINVAL;
+ goto out;
+ }
base = (struct squashfs_base_inode *)ipos;
switch (get_unaligned_le16(&base->inode_type)) {
@@ -1409,9 +1446,14 @@
break;
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE:
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ ret = -ELOOP;
+ goto out;
+ }
+
symlink = (struct squashfs_symlink_inode *)ipos;
resolved = sqfs_resolve_symlink(symlink, filename);
- ret = sqfs_read(resolved, buf, offset, len, actread);
+ ret = sqfs_read_nest(resolved, buf, offset, len, actread);
free(resolved);
goto out;
case SQFS_BLKDEV_TYPE:
@@ -1582,7 +1624,14 @@
return ret;
}
-int sqfs_size(const char *filename, loff_t *size)
+int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
+{
+ symlinknest = 0;
+ return sqfs_read_nest(filename, buf, offset, len, actread);
+}
+
+static int sqfs_size_nest(const char *filename, loff_t *size)
{
struct squashfs_super_block *sblk = ctxt.sblk;
struct squashfs_symlink_inode *symlink;
@@ -1598,10 +1647,10 @@
sqfs_split_path(&file, &dir, filename);
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
- ret = sqfs_opendir(dir, &dirsp);
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
ret = -EINVAL;
goto free_strings;
@@ -1609,7 +1658,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1627,6 +1676,13 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+
+ if (!ipos) {
+ *size = 0;
+ ret = -EINVAL;
+ goto free_strings;
+ }
+
free(dirs->entry);
dirs->entry = NULL;
@@ -1642,6 +1698,11 @@
break;
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE:
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ *size = 0;
+ return -ELOOP;
+ }
+
symlink = (struct squashfs_symlink_inode *)ipos;
resolved = sqfs_resolve_symlink(symlink, filename);
ret = sqfs_size(resolved, size);
@@ -1681,10 +1742,11 @@
sqfs_split_path(&file, &dir, filename);
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
- ret = sqfs_opendir(dir, &dirsp);
+ symlinknest = 0;
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
ret = -EINVAL;
goto free_strings;
@@ -1692,7 +1754,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1709,6 +1771,12 @@
return ret == 0;
}
+int sqfs_size(const char *filename, loff_t *size)
+{
+ symlinknest = 0;
+ return sqfs_size_nest(filename, size);
+}
+
void sqfs_close(void)
{
sqfs_decompressor_cleanup(&ctxt);
diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c
index d25cfb5..bb3ccd3 100644
--- a/fs/squashfs/sqfs_inode.c
+++ b/fs/squashfs/sqfs_inode.c
@@ -78,11 +78,16 @@
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE: {
+ int size;
+
struct squashfs_symlink_inode *symlink =
(struct squashfs_symlink_inode *)inode;
- return sizeof(*symlink) +
- get_unaligned_le32(&symlink->symlink_size);
+ if (__builtin_add_overflow(sizeof(*symlink),
+ get_unaligned_le32(&symlink->symlink_size), &size))
+ return -EINVAL;
+
+ return size;
}
case SQFS_BLKDEV_TYPE:
diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
index e89d025..c20f2f8 100644
--- a/fs/yaffs2/yaffs_guts.c
+++ b/fs/yaffs2/yaffs_guts.c
@@ -4452,13 +4452,12 @@
int yaffs_get_obj_link_count(struct yaffs_obj *obj)
{
int count = 0;
- struct list_head *i;
if (!obj->unlinked)
count++; /* the object itself */
- list_for_each(i, &obj->hard_links)
- count++; /* add the hard links; */
+ /* add the hard links; */
+ count += list_count_nodes(&obj->hard_links);
return count;
}
diff --git a/include/alist.h b/include/alist.h
new file mode 100644
index 0000000..68d268f
--- /dev/null
+++ b/include/alist.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a contiguous list of pointers which be allocated and freed
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ALIST_H
+#define __ALIST_H
+
+#include <stdbool.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+/**
+ * struct alist - object list that can be allocated and freed
+ *
+ * Holds a list of objects, each of the same size. The object is typically a
+ * C struct. The array is alloced in memory can change in size.
+ *
+ * The list rememebers the size of the list, but has a separate count of how
+ * much space is allocated, This allows it increase in size in steps as more
+ * elements are added, which is more efficient that reallocating the list every
+ * time a single item is added
+ *
+ * Two types of access are provided:
+ *
+ * alist_get...(index)
+ * gets an existing element, if its index is less that size
+ *
+ * alist_ensure(index)
+ * address an existing element, or creates a new one if not present
+ *
+ * @data: object data of size `@obj_size * @alloc`. The list can grow as
+ * needed but never shrinks
+ * @obj_size: Size of each object in bytes
+ * @count: number of objects in array
+ * @alloc: allocated length of array, to which @count can grow
+ * @flags: flags for the alist (ALISTF_...)
+ */
+struct alist {
+ void *data;
+ u16 obj_size;
+ u16 count;
+ u16 alloc;
+ u16 flags;
+};
+
+/**
+ * enum alist_flags - Flags for the alist
+ *
+ * @ALIST_FAIL: true if any allocation has failed. Once this has happened, the
+ * alist is dead and cannot grow further
+ */
+enum alist_flags {
+ ALISTF_FAIL = BIT(0),
+};
+
+/**
+ * alist_has() - Check if an index is within the list range
+ *
+ * Checks if index is within the current alist count
+ *
+ * @lst: alist to check
+ * @index: Index to check
+ * Returns: true if value, else false
+ */
+static inline bool alist_has(struct alist *lst, uint index)
+{
+ return index < lst->count;
+}
+
+/**
+ * alist_err() - Check if the alist is still valid
+ *
+ * @lst: List to check
+ * Return: false if OK, true if any previous allocation failed
+ */
+static inline bool alist_err(struct alist *lst)
+{
+ return lst->flags & ALISTF_FAIL;
+}
+
+/**
+ * alist_full() - Check if the alist is full
+ *
+ * @lst: List to check
+ * Return: true if full, false otherwise
+ */
+static inline bool alist_full(struct alist *lst)
+{
+ return lst->count == lst->alloc;
+}
+
+/**
+ * alist_get_ptr() - Get the value of a pointer
+ *
+ * @lst: alist to check
+ * @index: Index to read from
+ * Returns: pointer, if present, else NULL
+ */
+const void *alist_get_ptr(const struct alist *lst, uint index);
+
+/**
+ * alist_getd() - Get the value of a pointer directly, with no checking
+ *
+ * This must only be called on indexes for which alist_has() returns true
+ *
+ * @lst: alist to check
+ * @index: Index to read from
+ * Returns: pointer value (may be NULL)
+ */
+static inline const void *alist_getd(struct alist *lst, uint index)
+{
+ return lst->data + index * lst->obj_size;
+}
+
+/** get an entry as a constant */
+#define alist_get(_lst, _index, _struct) \
+ ((const _struct *)alist_get_ptr(_lst, _index))
+
+/** get an entry which can be written to */
+#define alist_getw(_lst, _index, _struct) \
+ ((_struct *)alist_get_ptr(_lst, _index))
+
+/**
+ * alist_ensure_ptr() - Ensure an object exists at a given index
+ *
+ * This provides read/write access to an array element. If it does not exist,
+ * it is allocated, reading for the caller to store the object into
+ *
+ * Allocates a object at the given index if needed
+ *
+ * @lst: alist to check
+ * @index: Index to address
+ * Returns: pointer where struct can be read/written, or NULL if out of memory
+ */
+void *alist_ensure_ptr(struct alist *lst, uint index);
+
+/**
+ * alist_ensure() - Address a struct, the correct object type
+ *
+ * Use as:
+ * struct my_struct *ptr = alist_ensure(&lst, 4, struct my_struct);
+ */
+#define alist_ensure(_lst, _index, _struct) \
+ ((_struct *)alist_ensure_ptr(_lst, _index))
+
+/**
+ * alist_add_placeholder() - Add a new item to the end of the list
+ *
+ * @lst: alist to add to
+ * Return: Pointer to the newly added position. Note that this is not inited so
+ * the caller must copy the requested struct to the returned pointer
+ */
+void *alist_add_placeholder(struct alist *lst);
+
+/**
+ * alist_add_ptr() - Ad a new object to the list
+ *
+ * @lst: alist to add to
+ * @obj: Pointer to object to copy in
+ * Returns: pointer to where the object was copied, or NULL if out of memory
+ */
+void *alist_add_ptr(struct alist *lst, void *obj);
+
+/**
+ * alist_expand_by() - Expand a list by the given amount
+ *
+ * @lst: alist to expand
+ * @inc_by: Amount to expand by
+ * Return: true if OK, false if out of memory
+ */
+bool alist_expand_by(struct alist *lst, uint inc_by);
+
+/**
+ * alist_add() - Used to add an object type with the correct type
+ *
+ * Use as:
+ * struct my_struct obj;
+ * struct my_struct *ptr = alist_add(&lst, &obj);
+ */
+#define alist_add(_lst, _obj) \
+ ((typeof(_obj) *)alist_add_ptr(_lst, &(_obj)))
+
+/**
+ * alist_init() - Set up a new object list
+ *
+ * Sets up a list of objects, initially empty
+ *
+ * @lst: alist to set up
+ * @obj_size: Size of each element in bytes
+ * @alloc_size: Number of items to allowed to start, before reallocation is
+ * needed (0 to start with no space)
+ * Return: true if OK, false if out of memory
+ */
+bool alist_init(struct alist *lst, uint obj_size, uint alloc_size);
+
+#define alist_init_struct(_lst, _struct) \
+ alist_init(_lst, sizeof(_struct), 0)
+
+/**
+ * alist_uninit_move_ptr() - Return the allocated contents and uninit the alist
+ *
+ * This returns the alist data to the caller, so that the caller receives data
+ * that it can be sure will hang around. The caller is responsible for freeing
+ * the data.
+ *
+ * If the alist size is 0, this returns NULL
+ *
+ * The alist is uninited as part of this.
+ *
+ * The alist must be inited before this can be called.
+ *
+ * @alist: alist to uninit
+ * @countp: if non-NULL, returns the number of objects in the returned data
+ * (which is @alist->size)
+ * Return: data contents, allocated with malloc(), or NULL if the data could not
+ * be allocated, or the data size is 0
+ */
+void *alist_uninit_move_ptr(struct alist *alist, size_t *countp);
+
+/**
+ * alist_uninit_move() - Typed version of alist_uninit_move_ptr()
+ */
+#define alist_uninit_move(_lst, _countp, _struct) \
+ (_struct *)alist_uninit_move_ptr(_lst, _countp)
+
+/**
+ * alist_uninit() - Free any memory used by an alist
+ *
+ * The alist must be inited before this can be called.
+ *
+ * @alist: alist to uninit
+ */
+void alist_uninit(struct alist *alist);
+
+#endif /* __ALIST_H */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 27aa75e..d6c15e2 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -20,6 +20,7 @@
*/
#ifndef __ASSEMBLY__
+#include <board_f.h>
#include <cyclic.h>
#include <event_internal.h>
#include <fdtdec.h>
@@ -30,6 +31,7 @@
struct acpi_ctx;
struct driver_rt;
+struct upl;
typedef struct global_data gd_t;
@@ -42,38 +44,140 @@
*/
struct bd_info *bd;
/**
+ * @new_gd: pointer to relocated global data
+ */
+ struct global_data *new_gd;
+ /**
+ * @fdt_blob: U-Boot's own device tree, NULL if none
+ */
+ const void *fdt_blob;
+ /**
+ * @cur_serial_dev: current serial device
+ */
+ struct udevice *cur_serial_dev;
+#ifndef CONFIG_SPL_BUILD
+ /**
+ * @jt: jump table
+ *
+ * The jump table contains pointers to exported functions. A pointer to
+ * the jump table is passed to standalone applications.
+ */
+ struct jt_funcs *jt;
+ /**
+ * @boardf: information only used before relocation
+ */
+ struct board_f *boardf;
+#endif
+ /**
+ * @ram_size: RAM size in bytes
+ */
+ phys_size_t ram_size;
+ /**
+ * @ram_top: top address of RAM used by U-Boot
+ */
+ phys_addr_t ram_top;
+ /**
* @flags: global data flags
*
* See &enum gd_flags
*/
unsigned long flags;
/**
+ * @cpu_clk: CPU clock rate in Hz
+ */
+ unsigned long cpu_clk;
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+ /**
+ * @env_addr: address of environment structure
+ *
+ * @env_addr contains the address of the structure holding the
+ * environment variables.
+ */
+ unsigned long env_addr;
+#endif /* ENV_SUPPORT */
+ /**
+ * @ram_base: base address of RAM used by U-Boot
+ */
+ unsigned long ram_base;
+ /**
+ * @relocaddr: start address of U-Boot in RAM
+ *
+ * After relocation this field indicates the address to which U-Boot
+ * has been relocated. It can be displayed using the bdinfo command.
+ * Its value is needed to display the source code when debugging with
+ * GDB using the 'add-symbol-file u-boot <relocaddr>' command.
+ */
+ unsigned long relocaddr;
+ /**
+ * @irq_sp: IRQ stack pointer
+ */
+ unsigned long irq_sp;
+ /**
+ * @start_addr_sp: initial stack pointer address
+ */
+ unsigned long start_addr_sp;
+ /**
+ * @reloc_off: relocation offset
+ */
+ unsigned long reloc_off;
+ /**
+ * @bus_clk: platform clock rate in Hz
+ */
+ unsigned int bus_clk;
+ /**
+ * @mem_clk: memory clock rate in Hz
+ */
+ unsigned int mem_clk;
+ /**
+ * @mon_len: monitor length in bytes
+ */
+ unsigned int mon_len;
+ /**
* @baudrate: baud rate of the serial interface
*/
unsigned int baudrate;
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
/**
- * @cpu_clk: CPU clock rate in Hz
+ * @env_has_init: bit mask indicating environment locations
+ *
+ * &enum env_location defines which bit relates to which location
*/
- unsigned long cpu_clk;
+ unsigned short env_has_init;
/**
- * @bus_clk: platform clock rate in Hz
+ * @env_valid: environment is valid
+ *
+ * See &enum env_valid
*/
- unsigned long bus_clk;
+ unsigned char env_valid;
/**
- * @pci_clk: PCI clock rate in Hz
+ * @env_load_prio: priority of the loaded environment
*/
- /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
- unsigned long pci_clk;
+ char env_load_prio;
/**
- * @mem_clk: memory clock rate in Hz
+ * @env_buf: buffer for env_get() before reloc
*/
- unsigned long mem_clk;
-#if CONFIG_IS_ENABLED(VIDEO)
+ char env_buf[32];
+#endif /* ENV_SUPPORT */
/**
- * @fb_base: base address of frame buffer memory
+ * @fdt_src: Source of FDT
*/
- unsigned long fb_base;
-#endif
+ enum fdt_source_t fdt_src;
+ /**
+ * @arch: architecture-specific data
+ */
+ struct arch_global_data arch;
+ /**
+ * @dmtag_list: List of DM tags
+ */
+ struct list_head dmtag_list;
+ /**
+ * @timebase_h: high 32 bits of timer
+ */
+ unsigned int timebase_h;
+ /**
+ * @timebase_l: low 32 bits of timer
+ */
+ unsigned int timebase_l;
#if defined(CONFIG_POST)
/**
* @post_log_word: active POST tests
@@ -103,15 +207,6 @@
*/
unsigned long board_type;
#endif
- /**
- * @have_console: console is available
- *
- * A value of 1 indicates that serial_init() was called and a console
- * is available.
- * A value of 0 indicates that console input and output drivers shall
- * not be called.
- */
- unsigned long have_console;
#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
/**
* @precon_buf_idx: pre-console buffer index
@@ -125,71 +220,6 @@
*/
long precon_buf_idx;
#endif
- /**
- * @env_addr: address of environment structure
- *
- * @env_addr contains the address of the structure holding the
- * environment variables.
- */
- unsigned long env_addr;
- /**
- * @env_valid: environment is valid
- *
- * See &enum env_valid
- */
- unsigned long env_valid;
- /**
- * @env_has_init: bit mask indicating environment locations
- *
- * &enum env_location defines which bit relates to which location
- */
- unsigned long env_has_init;
- /**
- * @env_load_prio: priority of the loaded environment
- */
- int env_load_prio;
- /**
- * @ram_base: base address of RAM used by U-Boot
- */
- unsigned long ram_base;
- /**
- * @ram_top: top address of RAM used by U-Boot
- */
- phys_addr_t ram_top;
- /**
- * @relocaddr: start address of U-Boot in RAM
- *
- * After relocation this field indicates the address to which U-Boot
- * has been relocated. It can be displayed using the bdinfo command.
- * Its value is needed to display the source code when debugging with
- * GDB using the 'add-symbol-file u-boot <relocaddr>' command.
- */
- unsigned long relocaddr;
- /**
- * @ram_size: RAM size in bytes
- */
- phys_size_t ram_size;
- /**
- * @mon_len: monitor length in bytes
- */
- unsigned long mon_len;
- /**
- * @irq_sp: IRQ stack pointer
- */
- unsigned long irq_sp;
- /**
- * @start_addr_sp: initial stack pointer address
- */
- unsigned long start_addr_sp;
- /**
- * @reloc_off: relocation offset
- */
- unsigned long reloc_off;
- /**
- * @new_gd: pointer to relocated global data
- */
- struct global_data *new_gd;
-
#ifdef CONFIG_DM
/**
* @dm_root: root instance for Driver Model
@@ -234,46 +264,18 @@
*/
struct udevice *timer;
#endif
- /**
- * @fdt_blob: U-Boot's own device tree, NULL if none
- */
- const void *fdt_blob;
- /**
- * @new_fdt: relocated device tree
- */
- void *new_fdt;
- /**
- * @fdt_size: space reserved for relocated device space
- */
- unsigned long fdt_size;
- /**
- * @fdt_src: Source of FDT
- */
- enum fdt_source_t fdt_src;
#if CONFIG_IS_ENABLED(OF_LIVE)
/**
* @of_root: root node of the live tree
*/
struct device_node *of_root;
#endif
-
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
/**
* @multi_dtb_fit: pointer to uncompressed multi-dtb FIT image
*/
const void *multi_dtb_fit;
#endif
- /**
- * @jt: jump table
- *
- * The jump table contains pointers to exported functions. A pointer to
- * the jump table is passed to standalone applications.
- */
- struct jt_funcs *jt;
- /**
- * @env_buf: buffer for env_get() before reloc
- */
- char env_buf[32];
#ifdef CONFIG_TRACE
/**
* @trace_buff: trace buffer
@@ -289,18 +291,10 @@
*/
int cur_i2c_bus;
#endif
- /**
- * @timebase_h: high 32 bits of timer
- */
- unsigned int timebase_h;
- /**
- * @timebase_l: low 32 bits of timer
- */
- unsigned int timebase_l;
+#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
/**
* @malloc_start: start of malloc() region
*/
-#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
unsigned long malloc_start;
#endif
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
@@ -309,43 +303,14 @@
*/
unsigned long malloc_base;
/**
- * @malloc_limit: limit address of early malloc()
+ * @malloc_limit: maximum size of early malloc()
*/
- unsigned long malloc_limit;
+ unsigned int malloc_limit;
/**
- * @malloc_ptr: current address of early malloc()
+ * @malloc_ptr: currently used bytes of early malloc()
*/
- unsigned long malloc_ptr;
+ unsigned int malloc_ptr;
#endif
-#ifdef CONFIG_PCI
- /**
- * @hose: PCI hose for early use
- */
- struct pci_controller *hose;
- /**
- * @pci_ram_top: top of region accessible to PCI
- */
- phys_addr_t pci_ram_top;
-#endif
-#ifdef CONFIG_PCI_BOOTDELAY
- /**
- * @pcidelay_done: delay time before scanning of PIC hose expired
- *
- * If CONFIG_PCI_BOOTDELAY=y, pci_hose_scan() waits for the number of
- * milliseconds defined by environment variable pcidelay before
- * scanning. Once this delay has expired the flag @pcidelay_done
- * is set to 1.
- */
- int pcidelay_done;
-#endif
- /**
- * @cur_serial_dev: current serial device
- */
- struct udevice *cur_serial_dev;
- /**
- * @arch: architecture-specific data
- */
- struct arch_global_data arch;
#ifdef CONFIG_CONSOLE_RECORD
/**
* @console_out: output buffer for console recording
@@ -376,13 +341,19 @@
* @bootstage: boot stage information
*/
struct bootstage_data *bootstage;
- /**
- * @new_bootstage: relocated boot stage information
- */
- struct bootstage_data *new_bootstage;
#endif
#ifdef CONFIG_LOG
/**
+ * @log_head: list of logging devices
+ */
+ struct list_head log_head;
+ /**
+ * @log_fmt: bit mask for logging format
+ *
+ * The @log_fmt bit mask selects the fields to be shown in log messages.
+ * &enum log_fmt defines the bits of the bit mask.
+ */
+ /**
* @log_drop_count: number of dropped log messages
*
* This counter is incremented for each log message which can not
@@ -396,60 +367,39 @@
* For logging devices without filters @default_log_level defines the
* logging level, cf. &enum log_level_t.
*/
- int default_log_level;
- /**
- * @log_head: list of logging devices
- */
- struct list_head log_head;
- /**
- * @log_fmt: bit mask for logging format
- *
- * The @log_fmt bit mask selects the fields to be shown in log messages.
- * &enum log_fmt defines the bits of the bit mask.
- */
- int log_fmt;
-
- /**
- * @processing_msg: a log message is being processed
- *
- * This flag is used to suppress the creation of additional messages
- * while another message is being processed.
- */
- bool processing_msg;
+ char default_log_level;
+ char log_fmt;
/**
* @logc_prev: logging category of previous message
*
* This value is used as logging category for continuation messages.
*/
- int logc_prev;
+ unsigned char logc_prev;
/**
* @logl_prev: logging level of the previous message
*
* This value is used as logging level for continuation messages.
*/
- int logl_prev;
+ unsigned char logl_prev;
/**
* @log_cont: Previous log line did not finished wtih \n
*
* This allows for chained log messages on the same line
*/
bool log_cont;
+ /**
+ * @processing_msg: a log message is being processed
+ *
+ * This flag is used to suppress the creation of additional messages
+ * while another message is being processed.
+ */
+ bool processing_msg;
#endif
#if CONFIG_IS_ENABLED(BLOBLIST)
/**
* @bloblist: blob list information
*/
struct bloblist_hdr *bloblist;
- /**
- * @new_bloblist: relocated blob list information
- */
- struct bloblist_hdr *new_bloblist;
-#endif
-#if CONFIG_IS_ENABLED(HANDOFF)
- /**
- * @spl_handoff: SPL hand-off information
- */
- struct spl_handoff *spl_handoff;
#endif
#if defined(CONFIG_TRANSLATION_OFFSET)
/**
@@ -487,10 +437,12 @@
*/
struct hlist_head cyclic_list;
#endif
+#if CONFIG_IS_ENABLED(UPL)
/**
- * @dmtag_list: List of DM tags
+ * @upl: Universal Payload-handoff information
*/
- struct list_head dmtag_list;
+ struct upl *upl;
+#endif
};
#ifndef DO_DEPS_ONLY
static_assert(sizeof(struct global_data) == GD_SIZE);
@@ -578,18 +530,20 @@
#define gd_set_malloc_start(val)
#endif
-#if CONFIG_IS_ENABLED(PCI)
-#define gd_set_pci_ram_top(val) gd->pci_ram_top = val
-#else
-#define gd_set_pci_ram_top(val)
-#endif
-
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#define gd_malloc_ptr() gd->malloc_ptr
#else
#define gd_malloc_ptr() 0L
#endif
+#if CONFIG_IS_ENABLED(UPL)
+#define gd_upl() gd->upl
+#define gd_set_upl(_val) gd->upl = (_val)
+#else
+#define gd_upl() NULL
+#define gd_set_upl(val)
+#endif
+
/**
* enum gd_flags - global data flags
*
@@ -701,6 +655,16 @@
* @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser.
*/
GD_FLG_HUSH_MODERN_PARSER = 0x2000000,
+ /**
+ * @GD_FLG_UPL: Read/write a Universal Payload (UPL) handoff
+ */
+ GD_FLG_UPL = 0x4000000,
+ /**
+ * @GD_FLG_HAVE_CONSOLE: serial_init() was called and a console
+ * is available. When not set, indicates that console input and output
+ * drivers shall not be called.
+ */
+ GD_FLG_HAVE_CONSOLE = 0x8000000,
};
#endif /* __ASSEMBLY__ */
diff --git a/include/blk.h b/include/blk.h
index 7c7cf7f..1fc9a5b 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -650,7 +650,7 @@
struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnum);
/**
- * blk_get_devnum_by_uclass_id() - Get a block device by type name, and number
+ * blk_get_devnum_by_uclass_idname() - Get block device by type name and number
*
* This looks up the block device type based on @uclass_idname, then calls
* blk_get_devnum_by_uclass_id().
@@ -660,7 +660,7 @@
* Return: point to block device descriptor, or NULL if not found
*/
struct blk_desc *blk_get_devnum_by_uclass_idname(const char *uclass_idname,
- int devnum);
+ int devnum);
/**
* blk_dselect_hwpart() - select a hardware partition
diff --git a/include/board_f.h b/include/board_f.h
new file mode 100644
index 0000000..05aa515
--- /dev/null
+++ b/include/board_f.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 Google LLC
+ * Written by: Simon Glass <sjg@chromeium.org>
+ */
+
+#ifndef __BOARD_F
+#define __BOARD_F
+
+/**
+ * struct board_f: Information used only before relocation
+ *
+ * This struct is set up in board_init_f() and used to deal with relocation. It
+ * is not available after relocation.
+ */
+struct board_f {
+ /**
+ * @new_fdt: relocated device tree
+ */
+ void *new_fdt;
+ /**
+ * @fdt_size: space reserved for relocated device space
+ */
+ unsigned long fdt_size;
+ /**
+ * @new_bootstage: relocated boot stage information
+ */
+ struct bootstage_data *new_bootstage;
+ /**
+ * @new_bloblist: relocated blob list information
+ */
+ struct bloblist_hdr *new_bloblist;
+};
+
+#endif
diff --git a/include/bootstage.h b/include/bootstage.h
index f4e77b0..5779264 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -258,7 +258,7 @@
* relocation, since memory can be overwritten later.
* Return: Always returns 0, to indicate success
*/
-int bootstage_relocate(void);
+int bootstage_relocate(void *to);
/**
* Add a new bootstage record
@@ -395,7 +395,7 @@
* and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
*/
-static inline int bootstage_relocate(void)
+static inline int bootstage_relocate(void *to)
{
return 0;
}
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
index 6fd4351..e5df82c 100644
--- a/include/configs/apalis_imx6.h
+++ b/include/configs/apalis_imx6.h
@@ -23,11 +23,6 @@
/* Network */
-/* USB Configs */
-/* Host */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* Framebuffer and LCD */
/* Command definition */
diff --git a/include/configs/arbel.h b/include/configs/arbel.h
index 61f6a5e..b5f684e 100644
--- a/include/configs/arbel.h
+++ b/include/configs/arbel.h
@@ -16,7 +16,7 @@
{ 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
/* Default environemnt variables */
-#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
+#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80800000\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 9d4a4bb..8a66b12 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -411,10 +411,6 @@
/* DMA stuff, needed for GPMI/MXS NAND support */
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* UBI support */
#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index b9cc7ba..b75db7e 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -35,11 +35,7 @@
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
-#ifdef CONFIG_AT91SAM9XE
-# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
-#else
-# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
-#endif
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index 38c98c5..d01f0d3 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h
@@ -78,7 +78,4 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif /* __CONFIG_BRPP2_IMX6_H */
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 280ae1e..8c36313 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -95,8 +95,4 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#endif
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#endif /* __CONFIG_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index 7d0f2b6..f7fd4c5 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -134,10 +134,6 @@
/* Ethernet */
#define CFG_FEC_MXC_PHYADDR 0
-/* USB */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* Boot */
#define CFG_SYS_BOOTMAPSZ (8 << 20)
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 8860cee..26b29ba 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -117,11 +117,6 @@
#define CFG_SYS_NAND_BASE -1
#endif
-/* USB Configs */
-
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* USB Device Firmware Update support */
#define DFU_DEFAULT_POLL_TIMEOUT 300
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
index 79e5b87..664b7c8 100644
--- a/include/configs/colibri_imx6.h
+++ b/include/configs/colibri_imx6.h
@@ -21,11 +21,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_SYS_FSL_USDHC_NUM 2
-/* USB Configs */
-/* Host */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* Command definition */
#define BOOT_TARGET_DEVICES(func) \
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index 33133a0b..c340dfb 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -159,9 +159,4 @@
#define CFG_SYS_NAND_BASE 0x40000000
#endif
-/* USB Configs */
-
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#endif
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index c578167..2b329b4 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -46,10 +46,6 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define ENV_MMC \
"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 4b5ef4a..9b6f03f 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -30,10 +30,6 @@
/* UART */
#define CFG_MXC_UART_BASE UART1_BASE
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* USB Gadget (DFU, UMS) */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT 300
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 2005a25..51fa2b0 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -287,5 +287,4 @@
/* The 0x120000 value corresponds to above SPI-NOR memory MAP */
#endif
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index 31c7e10..61c0d75 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -17,10 +17,6 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
deleted file mode 100644
index 807c696..0000000
--- a/include/configs/ethernut5.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * egnite GmbH <info@egnite.de>
- *
- * Configuation settings for Ethernut 5 with AT91SAM9XE.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/hardware.h>
-
-/* The first stage boot loader expects u-boot running at this address. */
-
-/* The first stage boot loader takes care of low level initialization. */
-
-/* CPU information */
-
-/* ARM asynchronous clock */
-#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
-
-/* 32kB internal SRAM */
-#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
-#define CFG_SYS_INIT_RAM_SIZE (32 << 10)
-
-/* 128MB SDRAM in 1 bank */
-#define CFG_SYS_SDRAM_BASE 0x20000000
-#define CFG_SYS_SDRAM_SIZE (128 << 20)
-
-/* 512kB on-chip NOR flash */
-# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
-
-/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-
-/* NAND flash */
-#ifdef CONFIG_CMD_NAND
-#define CFG_SYS_NAND_BASE 0x40000000
-/* our ALE is AD21 */
-#define CFG_SYS_NAND_MASK_ALE (1 << 21)
-/* our CLE is AD22 */
-#define CFG_SYS_NAND_MASK_CLE (1 << 22)
-#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#endif
-
-/* JFFS2 */
-
-/* Ethernet */
-#define CFG_PHY_ID 0
-
-/* MMC */
-#ifdef CONFIG_CMD_MMC
-#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
-#endif
-
-/* RTC */
-#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
-#define CFG_SYS_I2C_RTC_ADDR 0x51
-#endif
-
-/* I2C */
-#define CFG_SYS_MAX_I2C_BUS 1
-
-#define I2C_SOFT_DECLARATIONS
-
-#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
-#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
-
-#define I2C_INIT { \
- at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
- at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
- at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
-}
-
-#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
-#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
-#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
-#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
-#define I2C_DELAY udelay(100)
-#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
-
-/* File systems */
-
-/* Boot command */
-
-/* Misc. u-boot settings */
-
-#endif
diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
index 49b058c..f3d85c9 100644
--- a/include/configs/ge_b1x5v2.h
+++ b/include/configs/ge_b1x5v2.h
@@ -23,10 +23,6 @@
#define CONSOLE_DEVICE "ttymxc2" /* Base board debug connector */
#endif
-/* USB */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* Memory */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index ebc5d03..acfb513 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -6,55 +6,22 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/* SPL */
-/* Location in NAND to read U-Boot from */
-
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-
#include "mx6_common.h"
/* Serial */
#define CFG_MXC_UART_BASE UART2_BASE
-/* NAND */
-
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
-/*
- * PCI express
- */
-
-/*
- * PMIC
- */
+/* PMIC */
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#define CFG_POWER_LTC3676_I2C_ADDR 0x3c
-/* Various command support */
-
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
-/* Miscellaneous configurable options */
-
-/* Memory configuration */
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/*
- * MTD Command for mtdparts
- */
-
-/* Persistent Environment Config */
-
-/* Environment */
-
#endif /* __CONFIG_H */
diff --git a/include/configs/ibex_ast2700.h b/include/configs/ibex_ast2700.h
new file mode 100644
index 0000000..0f6850f
--- /dev/null
+++ b/include/configs/ibex_ast2700.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE
+#define CFG_SYS_SDRAM_BASE 0x80000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
index 66004a6..7599746 100644
--- a/include/configs/imx6_logic.h
+++ b/include/configs/imx6_logic.h
@@ -114,12 +114,6 @@
#define CFG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
/* Falcon Mode */
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
index 6c61b3f..8abb58b 100644
--- a/include/configs/imx6dl-mamoj.h
+++ b/include/configs/imx6dl-mamoj.h
@@ -42,10 +42,6 @@
/* Ethernet */
#define CFG_FEC_MXC_PHYADDR 1
-/* USB */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
/* Falcon */
/* MMC support: args@1MB kernel@2MB */
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 2c998cd..fab5063 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -110,7 +110,5 @@
#endif
#endif
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
#endif /* __IMX6Q_ACC_H */
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
index 131f182..36c4c5b 100644
--- a/include/configs/imx7-cm.h
+++ b/include/configs/imx7-cm.h
@@ -77,7 +77,4 @@
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_FSL_USDHC_NUM 2
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
index 6442e3d..146f794 100644
--- a/include/configs/imx8mm-cl-iot-gate.h
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -137,7 +137,4 @@
#define CFG_FEC_MXC_PHYADDR -1 /* Auto search of PHY on MII */
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif /*__IMX8MM_CL_IOT_GATE_H*/
diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h
index 1c92cd7..015df01 100644
--- a/include/configs/kontron-sl-mx6ul.h
+++ b/include/configs/kontron-sl-mx6ul.h
@@ -24,11 +24,6 @@
/* Board and environment settings */
#define CFG_MXC_UART_BASE UART4_BASE
-#ifdef CONFIG_USB_EHCI_HCD
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
/* Boot order for distro boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h
index eee3d2d..3a129c5 100644
--- a/include/configs/kontron-sl-mx8mm.h
+++ b/include/configs/kontron-sl-mx8mm.h
@@ -24,11 +24,6 @@
/* Board and environment settings */
-#ifdef CONFIG_USB_EHCI_HCD
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
/* GUID for capsule updatable firmware image */
#define KONTRON_SL_MX8MM_FIT_IMAGE_GUID \
EFI_GUID(0xd488e45a, 0x4929, 0x4b55, 0x8c, 0x14, \
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
index 6e383cb..78c6c67 100644
--- a/include/configs/kp_imx53.h
+++ b/include/configs/kp_imx53.h
@@ -11,7 +11,6 @@
#include <linux/sizes.h>
/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Command definition */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index 1aa4b8a..c0cb3db 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -16,12 +16,6 @@
/* FEC ethernet */
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#define CFG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \
"fdt_addr=0x18000000\0" \
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index 5811059..fc6bc6b 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -93,12 +93,6 @@
/* FLASH and environment organization */
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#ifdef CONFIG_CMD_NET
#define CFG_FEC_ENET_DEV 0
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 769ece9..ed93b51 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -47,7 +47,6 @@
#endif
/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 1
#define I2C_MUX_CH_RTC 0xB
/* Store environment at top of flash */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index 0f591e3..d44ce45 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -10,8 +10,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* Store environment at top of flash */
/*
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 5e03a96..21804fc 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -66,7 +66,6 @@
/* RTC */
#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
-#define CFG_SYS_RTC_BUS_NUM 0
/*
* Environment
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 3a316e7..5b397e2 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -8,9 +8,6 @@
#include "lx2160a_common.h"
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* MAC/PHY configuration */
/* Initial environment variables */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6404b35..e700a7b 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -8,9 +8,6 @@
#include "lx2160a_common.h"
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 4
-
#if defined(CONFIG_FSL_MC_ENET)
#define AQR113C_PHY_ADDR1 0x0
#define AQR113C_PHY_ADDR2 0x08
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index 54d7cea..2d0db47 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h
@@ -10,9 +10,6 @@
/* USB */
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
diff --git a/include/configs/lxr2.h b/include/configs/lxr2.h
new file mode 100644
index 0000000..d8d37a4
--- /dev/null
+++ b/include/configs/lxr2.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+// Copyright (C) Stefano Babic <sbabic@denx.de>
+
+#ifndef __LXR2_CONFIG_H
+#define __LXR2_CONFIG_H
+
+#include <config_distro_bootcmd.h>
+
+#include "mx6_common.h"
+
+#define PHYS_SDRAM_SIZE SZ_1G
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CFG_SYS_FSL_ESDHC_ADDR 0
+#define CFG_MXC_UART_BASE UART4_BASE
+
+#endif
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 9cf46b2..1ea4fa5 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -57,8 +57,6 @@
#define CFG_FEC_MXC_PHYADDR 0x0
#endif
-#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
-
/*
* RTC
*/
@@ -70,8 +68,6 @@
* USB
*/
#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORT 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
#endif
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
index 6ffc128..8e24817 100644
--- a/include/configs/meerkat96.h
+++ b/include/configs/meerkat96.h
@@ -23,7 +23,4 @@
/* Environment configs */
-/* USB configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index dff54d0..6c8cb78 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -33,7 +33,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/* USB Configs */
-#define CFG_MXC_USB_PORT 1
#define CFG_MXC_USB_PORTSC PORT_PTS_ULPI
#define CFG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
index dccfdc3..70aa140 100644
--- a/include/configs/mx53cx9020.h
+++ b/include/configs/mx53cx9020.h
@@ -22,8 +22,6 @@
/* bootz: zImage/initrd.img support */
/* USB Configs */
-#define CFG_MXC_USB_PORT 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Command definition */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 7398804..14095b9 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -17,8 +17,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */
-#define CFG_MXC_USB_PORT 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* PMIC Controller */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index df65dbe..6d1f669 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -12,8 +12,6 @@
#include <asm/arch/imx-regs.h>
/* USB Configs */
-#define CFG_MXC_USB_PORT 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Command definition */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index f0d6405..068b9e4 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -14,9 +14,6 @@
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-/* USB */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
/* Command definition */
#define CFG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
index f2edd13..a966c8b 100644
--- a/include/configs/mx6memcal.h
+++ b/include/configs/mx6memcal.h
@@ -31,6 +31,5 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CFG_MXC_USB_PORTSC PORT_PTS_UTMI
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index 91544c8..e491af3 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -11,10 +11,6 @@
#define CFG_MXC_UART_BASE UART4_BASE
#define CONSOLE_DEV "ttymxc3"
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
#include "mx6sabre_common.h"
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 844f10e..e34947c 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -24,10 +24,4 @@
#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#endif /* __MX6SABRESD_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 39c8ef0..d4e66a3 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -25,9 +25,9 @@
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
- "mmcdev=1\0" \
+ "mmcdev=0\0" \
"mmcpart=1\0" \
- "finduuid=part uuid mmc 1:2 uuid\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
@@ -88,12 +88,6 @@
/* Environment organization */
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#define CFG_SYS_FSL_USDHC_NUM 3
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 290996b..0ba4054 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -92,10 +92,5 @@
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_FSL_USDHC_NUM 3
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#endif
-
#include <linux/stringify.h>
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 1c14a6b..36d82e8 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -95,11 +95,6 @@
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CFG_FEC_MXC_PHYADDR 0x0
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#define CFG_SYS_FSL_USDHC_NUM 2
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index fe0ad34..844becb 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -117,11 +117,6 @@
#define CFG_FEC_MXC_PHYADDR 0x1
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#ifdef CONFIG_CMD_PCI
#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 98b743b..3716dc7 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -114,12 +114,6 @@
/* environment organization */
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#ifdef CONFIG_CMD_NET
#define CFG_FEC_ENET_DEV 1
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 94bee75..f5ab472 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -98,7 +98,4 @@
/* DMA stuff, needed for GPMI/MXS NAND support */
#endif
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif /* __CONFIG_H */
diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h
index a310c64..f8e3950 100644
--- a/include/configs/mx7ulp_com.h
+++ b/include/configs/mx7ulp_com.h
@@ -51,5 +51,4 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE SZ_256K
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index 2571098..ddd46c8 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -29,10 +29,6 @@
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define CFG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200n8\0" \
"fdt_addr_r=0x82000000\0" \
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index c03d11d..23eefaf 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -18,10 +18,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CFG_FEC_MXC_PHYADDR 6
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#ifdef CONFIG_CMD_MMC
#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 39d3afd..059b810 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -51,12 +51,6 @@
/* UART */
#define CFG_MXC_UART_BASE UART2_BASE
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
/* Extra U-Boot environment. */
#define CFG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h
index 5f93339..1caa63f 100644
--- a/include/configs/npi_imx6ull.h
+++ b/include/configs/npi_imx6ull.h
@@ -28,10 +28,6 @@
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#ifdef CONFIG_CMD_NET
#define CFG_FEC_MXC_PHYADDR 0x1
#endif
diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h
index 9050da8..f5a4898 100644
--- a/include/configs/o4-imx6ull-nano.h
+++ b/include/configs/o4-imx6ull-nano.h
@@ -11,10 +11,6 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#if IS_ENABLED(CONFIG_CMD_USB)
-# define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#endif /* CONFIG_CMD_USB */
-
#define CFG_EXTRA_ENV_SETTINGS \
"mmcdev=0\0" \
"mmcpart=2\0" \
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
index 1edb182..fd94523 100644
--- a/include/configs/opos6uldev.h
+++ b/include/configs/opos6uldev.h
@@ -17,12 +17,6 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/* USB */
-#ifdef CONFIG_USB_EHCI_MX6
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
/* LCD */
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 38dcee0..0c96506 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -41,10 +41,6 @@
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define CFG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200n8\0" \
"fdt_addr_r=0x82000000\0" \
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index d742201..0f265ad 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -43,10 +43,6 @@
/* NAND */
#define CFG_SYS_NAND_BASE 0x40000000
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define ENV_MMC \
"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index dd7cfdb..0910ae2 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -29,6 +29,14 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \
+ "update_offset=0x42\0" \
+ "update_filename=flash.bin\0" \
+ "update_bootimg=" \
+ "mmc dev ${mmcdev} ; " \
+ "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \
+ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
+ "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
+ "fi\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index d806d7d..500dd8c 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -15,10 +15,6 @@
/* MMC Configuration */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CFG_DFU_ENV_SETTINGS \
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 8a22f01..37f4c7d 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -21,10 +21,6 @@
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CFG_DFU_ENV_SETTINGS \
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index e7a8cb2..89850d8 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -105,8 +105,4 @@
#define CFG_SYS_FSL_USDHC_NUM 2
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#endif
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 45a3102..d0ae5e1 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -35,20 +35,6 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
/*
- * I2C
- */
-
-#define CFG_I2C_MULTI_BUS
-
-/*
- * Input
- */
-
-/*
- * SPL
- */
-
-/*
* Serial
*/
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index 041a83b0..c8fdb40 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -59,12 +59,6 @@
/* environment organization */
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-#endif
-
#ifdef CONFIG_CMD_NET
#define CFG_FEC_MXC_PHYADDR 0x1
#endif
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 256331a..9ef774a 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -25,11 +25,6 @@
#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
#endif
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#endif /* CONFIG_CMD_USB */
-
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index b4a06a7..fd4d170 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -26,12 +26,14 @@
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
+#if !defined(CONFIG_DM_PMIC)
+#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
+#define TQMA6_PFUZE100_I2C_BUS 2
+#endif
+
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#if defined(CONFIG_TQMA6X_MMC_BOOT)
#define TQMA6_UBOOT_OFFSET SZ_1K
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index e06fc7f..5e21463 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -16,7 +16,6 @@
/* Watchdog */
/* Config on-board RTC */
-#define CFG_SYS_RTC_BUS_NUM 2
#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Turn off RTC square-wave output to save battery */
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
index 27e61f5..5bdd124 100644
--- a/include/configs/usbarmory.h
+++ b/include/configs/usbarmory.h
@@ -23,8 +23,6 @@
#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB */
-#define CFG_MXC_USB_PORT 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Linux boot */
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index 12d2b68..b018bbe 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -63,7 +63,4 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE (long)(SZ_1G)
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-
#endif /* __VERDIN_IMX8MM_H */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index 3065419..2cf7bc7 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -36,8 +36,6 @@
/* Network */
#define CFG_FEC_MXC_PHYADDR 0x0
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
#ifdef CONFIG_CMD_PCI
#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 7b8c5cb..b5b342b 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -16,10 +16,6 @@
#define CFG_SYS_FSL_USDHC_NUM 2
#define CFG_SYS_FSL_ESDHC_ADDR 0
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define CFG_EXTRA_ENV_SETTINGS \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 0da9250..a5278d1 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -92,7 +92,6 @@
#define CFG_SYS_FSL_USDHC_NUM 1
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/* USB Device Firmware Update support */
#define DFU_DEFAULT_POLL_TIMEOUT 300
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index a2aa310..8efebf7 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -27,10 +27,6 @@
/* Environment is in stored in the eMMC boot partition */
-/* USB Configs */
-#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CFG_MXC_USB_FLAGS 0
-
#define CFG_FEC_ENET_DEV 0
#define CFG_FEC_MXC_PHYADDR 0x0
diff --git a/include/console.h b/include/console.h
index 2617e16..57fdb08 100644
--- a/include/console.h
+++ b/include/console.h
@@ -73,7 +73,7 @@
* @str: Place to put string
* @maxlen: Maximum length of @str including nul terminator
* Return: length of string returned, or -ENOSPC if the console buffer was
- * overflowed by the output
+ * overflowed by the output, or -ENOENT if there was nothing to read
*/
int console_record_readline(char *str, int maxlen);
@@ -179,6 +179,14 @@
*/
int console_clear(void);
+/**
+ * console_remove_by_name() - Remove a console by its stdio name
+ *
+ * This must only be used in tests. It removes any use of the named stdio device
+ * from the console tables.
+ */
+int console_remove_by_name(const char *name);
+
/*
* CONSOLE multiplexing.
*/
diff --git a/include/dm/test.h b/include/dm/test.h
index 0273741..3cbf2c7 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -143,7 +143,7 @@
/* Declare a new driver model test */
#define DM_TEST(_name, _flags) \
- UNIT_TEST(_name, UT_TESTF_DM | UT_TESTF_CONSOLE_REC | (_flags), dm_test)
+ UNIT_TEST(_name, UTF_DM | UTF_CONSOLE | (_flags), dm_test)
/*
* struct sandbox_sdl_plat - Platform data for the SDL video driver
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 76fcaff..cdbcaef 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -117,46 +117,51 @@
#define CLK_TOP_I2S1_MCK_DIV_PD 104
#define CLK_TOP_I2S2_MCK_DIV_PD 105
#define CLK_TOP_I2S3_MCK_DIV_PD 106
+#define CLK_TOP_A1SYS_HP_DIV_PD 107
+#define CLK_TOP_A2SYS_HP_DIV_PD 108
/* INFRACFG */
-#define CLK_INFRA_DBGCLK_PD 0
-#define CLK_INFRA_TRNG 1
+#define CLK_INFRA_MUX1_SEL 0
+#define CLK_INFRA_DBGCLK_PD 1
#define CLK_INFRA_AUDIO_PD 2
#define CLK_INFRA_IRRX_PD 3
#define CLK_INFRA_APXGPT_PD 4
#define CLK_INFRA_PMIC_PD 5
+#define CLK_INFRA_TRNG 6
/* PERICFG */
-#define CLK_PERI_THERM_PD 0
-#define CLK_PERI_PWM1_PD 1
-#define CLK_PERI_PWM2_PD 2
-#define CLK_PERI_PWM3_PD 3
-#define CLK_PERI_PWM4_PD 4
-#define CLK_PERI_PWM5_PD 5
-#define CLK_PERI_PWM6_PD 6
-#define CLK_PERI_PWM7_PD 7
-#define CLK_PERI_PWM_PD 8
-#define CLK_PERI_AP_DMA_PD 9
-#define CLK_PERI_MSDC30_0_PD 10
-#define CLK_PERI_MSDC30_1_PD 11
-#define CLK_PERI_UART0_PD 12
-#define CLK_PERI_UART1_PD 13
-#define CLK_PERI_UART2_PD 14
-#define CLK_PERI_UART3_PD 15
-#define CLK_PERI_BTIF_PD 16
-#define CLK_PERI_I2C0_PD 17
-#define CLK_PERI_I2C1_PD 18
-#define CLK_PERI_I2C2_PD 19
-#define CLK_PERI_SPI1_PD 20
-#define CLK_PERI_AUXADC_PD 21
-#define CLK_PERI_SPI0_PD 22
-#define CLK_PERI_SNFI_PD 23
-#define CLK_PERI_NFI_PD 24
-#define CLK_PERI_NFIECC_PD 25
-#define CLK_PERI_FLASH_PD 26
-#define CLK_PERI_IRTX_PD 27
+#define CLK_PERIBUS_SEL 0
+#define CLK_PERI_THERM_PD 1
+#define CLK_PERI_PWM1_PD 2
+#define CLK_PERI_PWM2_PD 3
+#define CLK_PERI_PWM3_PD 4
+#define CLK_PERI_PWM4_PD 5
+#define CLK_PERI_PWM5_PD 6
+#define CLK_PERI_PWM6_PD 7
+#define CLK_PERI_PWM7_PD 8
+#define CLK_PERI_PWM_PD 9
+#define CLK_PERI_AP_DMA_PD 10
+#define CLK_PERI_MSDC30_0_PD 11
+#define CLK_PERI_MSDC30_1_PD 12
+#define CLK_PERI_UART0_PD 13
+#define CLK_PERI_UART1_PD 14
+#define CLK_PERI_UART2_PD 15
+#define CLK_PERI_UART3_PD 16
+#define CLK_PERI_UART4_PD 17
+#define CLK_PERI_BTIF_PD 18
+#define CLK_PERI_I2C0_PD 19
+#define CLK_PERI_I2C1_PD 20
+#define CLK_PERI_I2C2_PD 21
+#define CLK_PERI_SPI1_PD 22
+#define CLK_PERI_AUXADC_PD 23
+#define CLK_PERI_SPI0_PD 24
+#define CLK_PERI_SNFI_PD 25
+#define CLK_PERI_NFI_PD 26
+#define CLK_PERI_NFIECC_PD 27
+#define CLK_PERI_FLASH_PD 28
+#define CLK_PERI_IRTX_PD 29
/* APMIXEDSYS */
@@ -169,6 +174,7 @@
#define CLK_APMIXED_AUD2PLL 6
#define CLK_APMIXED_TRGPLL 7
#define CLK_APMIXED_SGMIPLL 8
+#define CLK_APMIXED_MAIN_CORE_EN 9
/* AUDIOSYS */
@@ -206,7 +212,7 @@
#define CLK_AUDIO_DLMCH 31
#define CLK_AUDIO_ARB1 32
#define CLK_AUDIO_AWB 33
-#define CLK_AUDIO_AWB3 34
+#define CLK_AUDIO_AWB2 34
#define CLK_AUDIO_DAI 35
#define CLK_AUDIO_MOD 36
#define CLK_AUDIO_ASRCI3 37
diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
index 71ced15..0caeb65 100644
--- a/include/dt-bindings/clock/mt7623-clk.h
+++ b/include/dt-bindings/clock/mt7623-clk.h
@@ -7,407 +7,477 @@
#define _DT_BINDINGS_CLK_MT2701_H
/* TOPCKGEN */
-#define CLK_TOP_FCLKS_OFF 0
+#define CLK_TOP_SYSPLL 1
+#define CLK_TOP_SYSPLL_D2 2
+#define CLK_TOP_SYSPLL_D3 3
+#define CLK_TOP_SYSPLL_D5 4
+#define CLK_TOP_SYSPLL_D7 5
+#define CLK_TOP_SYSPLL1_D2 6
+#define CLK_TOP_SYSPLL1_D4 7
+#define CLK_TOP_SYSPLL1_D8 8
+#define CLK_TOP_SYSPLL1_D16 9
+#define CLK_TOP_SYSPLL2_D2 10
+#define CLK_TOP_SYSPLL2_D4 11
+#define CLK_TOP_SYSPLL2_D8 12
+#define CLK_TOP_SYSPLL3_D2 13
+#define CLK_TOP_SYSPLL3_D4 14
+#define CLK_TOP_SYSPLL4_D2 15
+#define CLK_TOP_SYSPLL4_D4 16
+#define CLK_TOP_UNIVPLL 17
+#define CLK_TOP_UNIVPLL_D2 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL_D5 20
+#define CLK_TOP_UNIVPLL_D7 21
+#define CLK_TOP_UNIVPLL_D26 22
+#define CLK_TOP_UNIVPLL_D52 23
+#define CLK_TOP_UNIVPLL_D108 24
+#define CLK_TOP_USB_PHY48M 25
+#define CLK_TOP_UNIVPLL1_D2 26
+#define CLK_TOP_UNIVPLL1_D4 27
+#define CLK_TOP_UNIVPLL1_D8 28
+#define CLK_TOP_UNIVPLL2_D2 29
+#define CLK_TOP_UNIVPLL2_D4 30
+#define CLK_TOP_UNIVPLL2_D8 31
+#define CLK_TOP_UNIVPLL2_D16 32
+#define CLK_TOP_UNIVPLL2_D32 33
+#define CLK_TOP_UNIVPLL3_D2 34
+#define CLK_TOP_UNIVPLL3_D4 35
+#define CLK_TOP_UNIVPLL3_D8 36
+#define CLK_TOP_MSDCPLL 37
+#define CLK_TOP_MSDCPLL_D2 38
+#define CLK_TOP_MSDCPLL_D4 39
+#define CLK_TOP_MSDCPLL_D8 40
+#define CLK_TOP_MMPLL 41
+#define CLK_TOP_MMPLL_D2 42
+#define CLK_TOP_DMPLL 43
+#define CLK_TOP_DMPLL_D2 44
+#define CLK_TOP_DMPLL_D4 45
+#define CLK_TOP_DMPLL_X2 46
+#define CLK_TOP_TVDPLL 47
+#define CLK_TOP_TVDPLL_D2 48
+#define CLK_TOP_TVDPLL_D4 49
+#define CLK_TOP_TVD2PLL 50
+#define CLK_TOP_TVD2PLL_D2 51
+#define CLK_TOP_HADDS2PLL_98M 52
+#define CLK_TOP_HADDS2PLL_294M 53
+#define CLK_TOP_HADDS2_FB 54
+#define CLK_TOP_MIPIPLL_D2 55
+#define CLK_TOP_MIPIPLL_D4 56
+#define CLK_TOP_HDMIPLL 57
+#define CLK_TOP_HDMIPLL_D2 58
+#define CLK_TOP_HDMIPLL_D3 59
+#define CLK_TOP_HDMI_SCL_RX 60
+#define CLK_TOP_HDMI_0_PIX340M 61
+#define CLK_TOP_HDMI_0_DEEP340M 62
+#define CLK_TOP_HDMI_0_PLL340M 63
+#define CLK_TOP_AUD1PLL_98M 64
+#define CLK_TOP_AUD2PLL_90M 65
+#define CLK_TOP_AUDPLL 66
+#define CLK_TOP_AUDPLL_D4 67
+#define CLK_TOP_AUDPLL_D8 68
+#define CLK_TOP_AUDPLL_D16 69
+#define CLK_TOP_AUDPLL_D24 70
+#define CLK_TOP_ETHPLL_500M 71
+#define CLK_TOP_VDECPLL 72
+#define CLK_TOP_VENCPLL 73
+#define CLK_TOP_MIPIPLL 74
+#define CLK_TOP_ARMPLL_1P3G 75
-#define CLK_TOP_DPI 0
-#define CLK_TOP_DMPLL 1
-#define CLK_TOP_VENCPLL 2
-#define CLK_TOP_HDMI_0_PIX340M 3
-#define CLK_TOP_HDMI_0_DEEP340M 4
-#define CLK_TOP_HDMI_0_PLL340M 5
-#define CLK_TOP_HADDS2_FB 6
-#define CLK_TOP_WBG_DIG_416M 7
-#define CLK_TOP_DSI0_LNTC_DSI 8
-#define CLK_TOP_HDMI_SCL_RX 9
-#define CLK_TOP_32K_EXTERNAL 10
-#define CLK_TOP_HDMITX_CLKDIG_CTS 11
-#define CLK_TOP_AUD_EXT1 12
-#define CLK_TOP_AUD_EXT2 13
-#define CLK_TOP_NFI1X_PAD 14
+#define CLK_TOP_MM_SEL 76
+#define CLK_TOP_DDRPHYCFG_SEL 77
+#define CLK_TOP_MEM_SEL 78
+#define CLK_TOP_AXI_SEL 79
+#define CLK_TOP_CAMTG_SEL 80
+#define CLK_TOP_MFG_SEL 81
+#define CLK_TOP_VDEC_SEL 82
+#define CLK_TOP_PWM_SEL 83
+#define CLK_TOP_MSDC30_0_SEL 84
+#define CLK_TOP_USB20_SEL 85
+#define CLK_TOP_SPI0_SEL 86
+#define CLK_TOP_UART_SEL 87
+#define CLK_TOP_AUDINTBUS_SEL 88
+#define CLK_TOP_AUDIO_SEL 89
+#define CLK_TOP_MSDC30_2_SEL 90
+#define CLK_TOP_MSDC30_1_SEL 91
+#define CLK_TOP_DPI1_SEL 92
+#define CLK_TOP_DPI0_SEL 93
+#define CLK_TOP_SCP_SEL 94
+#define CLK_TOP_PMICSPI_SEL 95
+#define CLK_TOP_APLL_SEL 96
+#define CLK_TOP_HDMI_SEL 97
+#define CLK_TOP_TVE_SEL 98
+#define CLK_TOP_EMMC_HCLK_SEL 99
+#define CLK_TOP_NFI2X_SEL 100
+#define CLK_TOP_RTC_SEL 101
+#define CLK_TOP_OSD_SEL 102
+#define CLK_TOP_NR_SEL 103
+#define CLK_TOP_DI_SEL 104
+#define CLK_TOP_FLASH_SEL 105
+#define CLK_TOP_ASM_M_SEL 106
+#define CLK_TOP_ASM_I_SEL 107
+#define CLK_TOP_INTDIR_SEL 108
+#define CLK_TOP_HDMIRX_BIST_SEL 109
+#define CLK_TOP_ETHIF_SEL 110
+#define CLK_TOP_MS_CARD_SEL 111
+#define CLK_TOP_ASM_H_SEL 112
+#define CLK_TOP_SPI1_SEL 113
+#define CLK_TOP_CMSYS_SEL 114
+#define CLK_TOP_MSDC30_3_SEL 115
+#define CLK_TOP_HDMIRX26_24_SEL 116
+#define CLK_TOP_AUD2DVD_SEL 117
+#define CLK_TOP_8BDAC_SEL 118
+#define CLK_TOP_SPI2_SEL 119
+#define CLK_TOP_AUD_MUX1_SEL 120
+#define CLK_TOP_AUD_MUX2_SEL 121
+#define CLK_TOP_AUDPLL_MUX_SEL 122
+#define CLK_TOP_AUD_K1_SRC_SEL 123
+#define CLK_TOP_AUD_K2_SRC_SEL 124
+#define CLK_TOP_AUD_K3_SRC_SEL 125
+#define CLK_TOP_AUD_K4_SRC_SEL 126
+#define CLK_TOP_AUD_K5_SRC_SEL 127
+#define CLK_TOP_AUD_K6_SRC_SEL 128
+#define CLK_TOP_PADMCLK_SEL 129
+#define CLK_TOP_AUD_EXTCK1_DIV 130
+#define CLK_TOP_AUD_EXTCK2_DIV 131
+#define CLK_TOP_AUD_MUX1_DIV 132
+#define CLK_TOP_AUD_MUX2_DIV 133
+#define CLK_TOP_AUD_K1_SRC_DIV 134
+#define CLK_TOP_AUD_K2_SRC_DIV 135
+#define CLK_TOP_AUD_K3_SRC_DIV 136
+#define CLK_TOP_AUD_K4_SRC_DIV 137
+#define CLK_TOP_AUD_K5_SRC_DIV 138
+#define CLK_TOP_AUD_K6_SRC_DIV 139
+#define CLK_TOP_AUD_I2S1_MCLK 140
+#define CLK_TOP_AUD_I2S2_MCLK 141
+#define CLK_TOP_AUD_I2S3_MCLK 142
+#define CLK_TOP_AUD_I2S4_MCLK 143
+#define CLK_TOP_AUD_I2S5_MCLK 144
+#define CLK_TOP_AUD_I2S6_MCLK 145
+#define CLK_TOP_AUD_48K_TIMING 146
+#define CLK_TOP_AUD_44K_TIMING 147
-#define CLK_TOP_SYSPLL 15
-#define CLK_TOP_SYSPLL_D2 16
-#define CLK_TOP_SYSPLL_D3 17
-#define CLK_TOP_SYSPLL_D5 18
-#define CLK_TOP_SYSPLL_D7 19
-#define CLK_TOP_SYSPLL1_D2 20
-#define CLK_TOP_SYSPLL1_D4 21
-#define CLK_TOP_SYSPLL1_D8 22
-#define CLK_TOP_SYSPLL1_D16 23
-#define CLK_TOP_SYSPLL2_D2 24
-#define CLK_TOP_SYSPLL2_D4 25
-#define CLK_TOP_SYSPLL2_D8 26
-#define CLK_TOP_SYSPLL3_D2 27
-#define CLK_TOP_SYSPLL3_D4 28
-#define CLK_TOP_SYSPLL4_D2 29
-#define CLK_TOP_SYSPLL4_D4 30
-#define CLK_TOP_UNIVPLL 31
-#define CLK_TOP_UNIVPLL_D2 32
-#define CLK_TOP_UNIVPLL_D3 33
-#define CLK_TOP_UNIVPLL_D5 34
-#define CLK_TOP_UNIVPLL_D7 35
-#define CLK_TOP_UNIVPLL_D26 36
-#define CLK_TOP_UNIVPLL_D52 37
-#define CLK_TOP_UNIVPLL_D108 38
-#define CLK_TOP_USB_PHY48M 39
-#define CLK_TOP_UNIVPLL1_D2 40
-#define CLK_TOP_UNIVPLL1_D4 41
-#define CLK_TOP_UNIVPLL1_D8 42
-#define CLK_TOP_UNIVPLL2_D2 43
-#define CLK_TOP_UNIVPLL2_D4 44
-#define CLK_TOP_UNIVPLL2_D8 45
-#define CLK_TOP_UNIVPLL2_D16 46
-#define CLK_TOP_UNIVPLL2_D32 47
-#define CLK_TOP_UNIVPLL3_D2 48
-#define CLK_TOP_UNIVPLL3_D4 49
-#define CLK_TOP_UNIVPLL3_D8 50
-#define CLK_TOP_MSDCPLL 51
-#define CLK_TOP_MSDCPLL_D2 52
-#define CLK_TOP_MSDCPLL_D4 53
-#define CLK_TOP_MSDCPLL_D8 54
-#define CLK_TOP_MMPLL 55
-#define CLK_TOP_MMPLL_D2 56
-#define CLK_TOP_DMPLL_D2 57
-#define CLK_TOP_DMPLL_D4 58
-#define CLK_TOP_DMPLL_X2 59
-#define CLK_TOP_TVDPLL 60
-#define CLK_TOP_TVDPLL_D2 61
-#define CLK_TOP_TVDPLL_D4 62
-#define CLK_TOP_VDECPLL 63
-#define CLK_TOP_TVD2PLL 64
-#define CLK_TOP_TVD2PLL_D2 65
-#define CLK_TOP_MIPIPLL 66
-#define CLK_TOP_MIPIPLL_D2 67
-#define CLK_TOP_MIPIPLL_D4 68
-#define CLK_TOP_HDMIPLL 69
-#define CLK_TOP_HDMIPLL_D2 70
-#define CLK_TOP_HDMIPLL_D3 71
-#define CLK_TOP_ARMPLL_1P3G 72
-#define CLK_TOP_AUDPLL 73
-#define CLK_TOP_AUDPLL_D4 74
-#define CLK_TOP_AUDPLL_D8 75
-#define CLK_TOP_AUDPLL_D16 76
-#define CLK_TOP_AUDPLL_D24 77
-#define CLK_TOP_AUD1PLL_98M 78
-#define CLK_TOP_AUD2PLL_90M 79
-#define CLK_TOP_HADDS2PLL_98M 80
-#define CLK_TOP_HADDS2PLL_294M 81
-#define CLK_TOP_ETHPLL_500M 82
-#define CLK_TOP_CLK26M_D8 83
-#define CLK_TOP_32K_INTERNAL 84
-#define CLK_TOP_AXISEL_D4 85
-#define CLK_TOP_8BDAC 86
-
-#define CLK_TOP_AXI_SEL 87
-#define CLK_TOP_MEM_SEL 88
-#define CLK_TOP_DDRPHYCFG_SEL 89
-#define CLK_TOP_MM_SEL 90
-#define CLK_TOP_PWM_SEL 91
-#define CLK_TOP_VDEC_SEL 92
-#define CLK_TOP_MFG_SEL 93
-#define CLK_TOP_CAMTG_SEL 94
-#define CLK_TOP_UART_SEL 95
-#define CLK_TOP_SPI0_SEL 96
-#define CLK_TOP_USB20_SEL 97
-#define CLK_TOP_MSDC30_0_SEL 98
-#define CLK_TOP_MSDC30_1_SEL 99
-#define CLK_TOP_MSDC30_2_SEL 100
-#define CLK_TOP_AUDIO_SEL 101
-#define CLK_TOP_AUDINTBUS_SEL 102
-#define CLK_TOP_PMICSPI_SEL 103
-#define CLK_TOP_SCP_SEL 104
-#define CLK_TOP_DPI0_SEL 105
-#define CLK_TOP_DPI1_SEL 106
-#define CLK_TOP_TVE_SEL 107
-#define CLK_TOP_HDMI_SEL 108
-#define CLK_TOP_APLL_SEL 109
-#define CLK_TOP_RTC_SEL 110
-#define CLK_TOP_NFI2X_SEL 111
-#define CLK_TOP_EMMC_HCLK_SEL 112
-#define CLK_TOP_FLASH_SEL 113
-#define CLK_TOP_DI_SEL 114
-#define CLK_TOP_NR_SEL 115
-#define CLK_TOP_OSD_SEL 116
-#define CLK_TOP_HDMIRX_BIST_SEL 117
-#define CLK_TOP_INTDIR_SEL 118
-#define CLK_TOP_ASM_I_SEL 119
-#define CLK_TOP_ASM_M_SEL 120
-#define CLK_TOP_ASM_H_SEL 121
-#define CLK_TOP_MS_CARD_SEL 122
-#define CLK_TOP_ETHIF_SEL 123
-#define CLK_TOP_HDMIRX26_24_SEL 124
-#define CLK_TOP_MSDC30_3_SEL 125
-#define CLK_TOP_CMSYS_SEL 126
-#define CLK_TOP_SPI1_SEL 127
-#define CLK_TOP_SPI2_SEL 128
-#define CLK_TOP_8BDAC_SEL 129
-#define CLK_TOP_AUD2DVD_SEL 130
-#define CLK_TOP_PADMCLK_SEL 131
-#define CLK_TOP_AUD_MUX1_SEL 132
-#define CLK_TOP_AUD_MUX2_SEL 133
-#define CLK_TOP_AUDPLL_MUX_SEL 134
-#define CLK_TOP_AUD_K1_SRC_SEL 135
-#define CLK_TOP_AUD_K2_SRC_SEL 136
-#define CLK_TOP_AUD_K3_SRC_SEL 137
-#define CLK_TOP_AUD_K4_SRC_SEL 138
-#define CLK_TOP_AUD_K5_SRC_SEL 139
-#define CLK_TOP_AUD_K6_SRC_SEL 140
-
-#define CLK_TOP_AUD_EXTCK1_DIV 141
-#define CLK_TOP_AUD_EXTCK2_DIV 142
-#define CLK_TOP_AUD_MUX1_DIV 143
-#define CLK_TOP_AUD_MUX2_DIV 144
-#define CLK_TOP_AUD_K1_SRC_DIV 145
-#define CLK_TOP_AUD_K2_SRC_DIV 146
-#define CLK_TOP_AUD_K3_SRC_DIV 147
-#define CLK_TOP_AUD_K4_SRC_DIV 148
-#define CLK_TOP_AUD_K5_SRC_DIV 149
-#define CLK_TOP_AUD_K6_SRC_DIV 150
-#define CLK_TOP_AUD_48K_TIMING 151
-#define CLK_TOP_AUD_44K_TIMING 152
-#define CLK_TOP_AUD_I2S1_MCLK 153
-#define CLK_TOP_AUD_I2S2_MCLK 154
-#define CLK_TOP_AUD_I2S3_MCLK 155
-#define CLK_TOP_AUD_I2S4_MCLK 156
-#define CLK_TOP_AUD_I2S5_MCLK 157
-#define CLK_TOP_AUD_I2S6_MCLK 158
+#define CLK_TOP_32K_INTERNAL 148
+#define CLK_TOP_32K_EXTERNAL 149
+#define CLK_TOP_CLK26M_D8 150
+#define CLK_TOP_8BDAC 151
+#define CLK_TOP_WBG_DIG_416M 152
+#define CLK_TOP_DPI 153
+#define CLK_TOP_DSI0_LNTC_DSI 154
+#define CLK_TOP_AUD_EXT1 155
+#define CLK_TOP_AUD_EXT2 156
+#define CLK_TOP_NFI1X_PAD 157
+#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_MAINPLL 1
-#define CLK_APMIXED_UNIVPLL 2
-#define CLK_APMIXED_MMPLL 3
-#define CLK_APMIXED_MSDCPLL 4
-#define CLK_APMIXED_TVDPLL 5
-#define CLK_APMIXED_AUD1PLL 6
-#define CLK_APMIXED_TRGPLL 7
-#define CLK_APMIXED_ETHPLL 8
-#define CLK_APMIXED_VDECPLL 9
-#define CLK_APMIXED_HADDS2PLL 10
-#define CLK_APMIXED_AUD2PLL 11
-#define CLK_APMIXED_TVD2PLL 12
-#define CLK_APMIXED_NR 13
+
+#define CLK_APMIXED_ARMPLL 1
+#define CLK_APMIXED_MAINPLL 2
+#define CLK_APMIXED_UNIVPLL 3
+#define CLK_APMIXED_MMPLL 4
+#define CLK_APMIXED_MSDCPLL 5
+#define CLK_APMIXED_TVDPLL 6
+#define CLK_APMIXED_AUD1PLL 7
+#define CLK_APMIXED_TRGPLL 8
+#define CLK_APMIXED_ETHPLL 9
+#define CLK_APMIXED_VDECPLL 10
+#define CLK_APMIXED_HADDS2PLL 11
+#define CLK_APMIXED_AUD2PLL 12
+#define CLK_APMIXED_TVD2PLL 13
+#define CLK_APMIXED_HDMI_REF 14
+#define CLK_APMIXED_NR 15
+
+/* DDRPHY */
+
+#define CLK_DDRPHY_VENCPLL 1
+#define CLK_DDRPHY_NR 2
/* INFRACFG */
-#define CLK_INFRA_DBG 0
-#define CLK_INFRA_SMI 1
-#define CLK_INFRA_QAXI_CM4 2
-#define CLK_INFRA_AUD_SPLIN_B 3
-#define CLK_INFRA_AUDIO 4
-#define CLK_INFRA_EFUSE 5
-#define CLK_INFRA_L2C_SRAM 6
-#define CLK_INFRA_M4U 7
-#define CLK_INFRA_CONNMCU 8
-#define CLK_INFRA_TRNG 9
-#define CLK_INFRA_RAMBUFIF 10
-#define CLK_INFRA_CPUM 11
-#define CLK_INFRA_KP 12
-#define CLK_INFRA_CEC 13
-#define CLK_INFRA_IRRX 14
-#define CLK_INFRA_PMICSPI 15
-#define CLK_INFRA_PMICWRAP 16
-#define CLK_INFRA_DDCCI 17
-#define CLK_INFRA_CPUSEL 18
-#define CLK_INFRA_NR 19
+
+#define CLK_INFRA_DBG 1
+#define CLK_INFRA_SMI 2
+#define CLK_INFRA_QAXI_CM4 3
+#define CLK_INFRA_AUD_SPLIN_B 4
+#define CLK_INFRA_AUDIO 5
+#define CLK_INFRA_EFUSE 6
+#define CLK_INFRA_L2C_SRAM 7
+#define CLK_INFRA_M4U 8
+#define CLK_INFRA_CONNMCU 9
+#define CLK_INFRA_TRNG 10
+#define CLK_INFRA_RAMBUFIF 11
+#define CLK_INFRA_CPUM 12
+#define CLK_INFRA_KP 13
+#define CLK_INFRA_CEC 14
+#define CLK_INFRA_IRRX 15
+#define CLK_INFRA_PMICSPI 16
+#define CLK_INFRA_PMICWRAP 17
+#define CLK_INFRA_DDCCI 18
+#define CLK_INFRA_CLK_13M 19
+#define CLK_INFRA_CPUSEL 20
+#define CLK_INFRA_NR 21
/* PERICFG */
-#define CLK_PERI_NFI 0
-#define CLK_PERI_THERM 1
-#define CLK_PERI_PWM1 2
-#define CLK_PERI_PWM2 3
-#define CLK_PERI_PWM3 4
-#define CLK_PERI_PWM4 5
-#define CLK_PERI_PWM5 6
-#define CLK_PERI_PWM6 7
-#define CLK_PERI_PWM7 8
-#define CLK_PERI_PWM 9
-#define CLK_PERI_USB0 10
-#define CLK_PERI_USB1 11
-#define CLK_PERI_AP_DMA 12
-#define CLK_PERI_MSDC30_0 13
-#define CLK_PERI_MSDC30_1 14
-#define CLK_PERI_MSDC30_2 15
-#define CLK_PERI_MSDC30_3 16
-#define CLK_PERI_MSDC50_3 17
-#define CLK_PERI_NLI 18
-#define CLK_PERI_UART0 19
-#define CLK_PERI_UART1 20
-#define CLK_PERI_UART2 21
-#define CLK_PERI_UART3 22
-#define CLK_PERI_BTIF 23
-#define CLK_PERI_I2C0 24
-#define CLK_PERI_I2C1 25
-#define CLK_PERI_I2C2 26
-#define CLK_PERI_I2C3 27
-#define CLK_PERI_AUXADC 28
-#define CLK_PERI_SPI0 39
-#define CLK_PERI_ETH 30
-#define CLK_PERI_USB0_MCU 31
+
+#define CLK_PERI_NFI 1
+#define CLK_PERI_THERM 2
+#define CLK_PERI_PWM1 3
+#define CLK_PERI_PWM2 4
+#define CLK_PERI_PWM3 5
+#define CLK_PERI_PWM4 6
+#define CLK_PERI_PWM5 7
+#define CLK_PERI_PWM6 8
+#define CLK_PERI_PWM7 9
+#define CLK_PERI_PWM 10
+#define CLK_PERI_USB0 11
+#define CLK_PERI_USB1 12
+#define CLK_PERI_AP_DMA 13
+#define CLK_PERI_MSDC30_0 14
+#define CLK_PERI_MSDC30_1 15
+#define CLK_PERI_MSDC30_2 16
+#define CLK_PERI_MSDC30_3 17
+#define CLK_PERI_MSDC50_3 18
+#define CLK_PERI_NLI 19
+#define CLK_PERI_UART0 20
+#define CLK_PERI_UART1 21
+#define CLK_PERI_UART2 22
+#define CLK_PERI_UART3 23
+#define CLK_PERI_BTIF 24
+#define CLK_PERI_I2C0 25
+#define CLK_PERI_I2C1 26
+#define CLK_PERI_I2C2 27
+#define CLK_PERI_I2C3 28
+#define CLK_PERI_AUXADC 29
+#define CLK_PERI_SPI0 30
+#define CLK_PERI_ETH 31
+#define CLK_PERI_USB0_MCU 32
+
+#define CLK_PERI_USB1_MCU 33
+#define CLK_PERI_USB_SLV 34
+#define CLK_PERI_GCPU 35
+#define CLK_PERI_NFI_ECC 36
+#define CLK_PERI_NFI_PAD 37
+#define CLK_PERI_FLASH 38
+#define CLK_PERI_HOST89_INT 39
+#define CLK_PERI_HOST89_SPI 40
+#define CLK_PERI_HOST89_DVD 41
+#define CLK_PERI_SPI1 42
+#define CLK_PERI_SPI2 43
+#define CLK_PERI_FCI 44
-#define CLK_PERI_USB1_MCU 32
-#define CLK_PERI_USB_SLV 33
-#define CLK_PERI_GCPU 34
-#define CLK_PERI_NFI_ECC 35
-#define CLK_PERI_NFI_PAD 36
-#define CLK_PERI_FLASH 37
-#define CLK_PERI_HOST89_INT 38
-#define CLK_PERI_HOST89_SPI 39
-#define CLK_PERI_HOST89_DVD 40
-#define CLK_PERI_SPI1 41
-#define CLK_PERI_SPI2 42
-#define CLK_PERI_FCI 43
-#define CLK_PERI_NR 44
+#define CLK_PERI_UART0_SEL 45
+#define CLK_PERI_UART1_SEL 46
+#define CLK_PERI_UART2_SEL 47
+#define CLK_PERI_UART3_SEL 48
+#define CLK_PERI_NR 49
/* AUDIO */
-#define CLK_AUD_AFE 0
-#define CLK_AUD_LRCK_DETECT 1
-#define CLK_AUD_I2S 2
-#define CLK_AUD_APLL_TUNER 3
-#define CLK_AUD_HDMI 4
-#define CLK_AUD_SPDF 5
-#define CLK_AUD_SPDF2 6
-#define CLK_AUD_APLL 7
-#define CLK_AUD_TML 8
-#define CLK_AUD_AHB_IDLE_EXT 9
-#define CLK_AUD_AHB_IDLE_INT 10
-#define CLK_AUD_I2SIN1 11
-#define CLK_AUD_I2SIN2 12
-#define CLK_AUD_I2SIN3 13
-#define CLK_AUD_I2SIN4 14
-#define CLK_AUD_I2SIN5 15
-#define CLK_AUD_I2SIN6 16
-#define CLK_AUD_I2SO1 17
-#define CLK_AUD_I2SO2 18
-#define CLK_AUD_I2SO3 19
-#define CLK_AUD_I2SO4 20
-#define CLK_AUD_I2SO5 21
-#define CLK_AUD_I2SO6 22
-#define CLK_AUD_ASRCI1 23
-#define CLK_AUD_ASRCI2 24
-#define CLK_AUD_ASRCO1 25
-#define CLK_AUD_ASRCO2 26
-#define CLK_AUD_ASRC11 27
-#define CLK_AUD_ASRC12 28
-#define CLK_AUD_HDMIRX 29
-#define CLK_AUD_INTDIR 30
-#define CLK_AUD_A1SYS 31
-#define CLK_AUD_A2SYS 32
-#define CLK_AUD_AFE_CONN 33
-#define CLK_AUD_AFE_PCMIF 34
-#define CLK_AUD_AFE_MRGIF 35
+#define CLK_AUD_AFE 1
+#define CLK_AUD_LRCK_DETECT 2
+#define CLK_AUD_I2S 3
+#define CLK_AUD_APLL_TUNER 4
+#define CLK_AUD_HDMI 5
+#define CLK_AUD_SPDF 6
+#define CLK_AUD_SPDF2 7
+#define CLK_AUD_APLL 8
+#define CLK_AUD_TML 9
+#define CLK_AUD_AHB_IDLE_EXT 10
+#define CLK_AUD_AHB_IDLE_INT 11
-#define CLK_AUD_MMIF_UL1 36
-#define CLK_AUD_MMIF_UL2 37
-#define CLK_AUD_MMIF_UL3 38
-#define CLK_AUD_MMIF_UL4 39
-#define CLK_AUD_MMIF_UL5 40
-#define CLK_AUD_MMIF_UL6 41
-#define CLK_AUD_MMIF_DL1 42
-#define CLK_AUD_MMIF_DL2 43
-#define CLK_AUD_MMIF_DL3 44
-#define CLK_AUD_MMIF_DL4 45
-#define CLK_AUD_MMIF_DL5 46
-#define CLK_AUD_MMIF_DL6 47
-#define CLK_AUD_MMIF_DLMCH 48
-#define CLK_AUD_MMIF_ARB1 49
-#define CLK_AUD_MMIF_AWB1 50
-#define CLK_AUD_MMIF_AWB2 51
-#define CLK_AUD_MMIF_DAI 52
+#define CLK_AUD_I2SIN1 12
+#define CLK_AUD_I2SIN2 13
+#define CLK_AUD_I2SIN3 14
+#define CLK_AUD_I2SIN4 15
+#define CLK_AUD_I2SIN5 16
+#define CLK_AUD_I2SIN6 17
+#define CLK_AUD_I2SO1 18
+#define CLK_AUD_I2SO2 19
+#define CLK_AUD_I2SO3 20
+#define CLK_AUD_I2SO4 21
+#define CLK_AUD_I2SO5 22
+#define CLK_AUD_I2SO6 23
+#define CLK_AUD_ASRCI1 24
+#define CLK_AUD_ASRCI2 25
+#define CLK_AUD_ASRCO1 26
+#define CLK_AUD_ASRCO2 27
+#define CLK_AUD_ASRC11 28
+#define CLK_AUD_ASRC12 29
+#define CLK_AUD_HDMIRX 30
+#define CLK_AUD_INTDIR 31
+#define CLK_AUD_A1SYS 32
+#define CLK_AUD_A2SYS 33
+#define CLK_AUD_AFE_CONN 34
+#define CLK_AUD_AFE_PCMIF 35
+#define CLK_AUD_AFE_MRGIF 36
-#define CLK_AUD_DMIC1 53
-#define CLK_AUD_DMIC2 54
-#define CLK_AUD_ASRCI3 55
-#define CLK_AUD_ASRCI4 56
-#define CLK_AUD_ASRCI5 57
-#define CLK_AUD_ASRCI6 58
-#define CLK_AUD_ASRCO3 59
-#define CLK_AUD_ASRCO4 60
-#define CLK_AUD_ASRCO5 61
-#define CLK_AUD_ASRCO6 62
-#define CLK_AUD_MEM_ASRC1 63
-#define CLK_AUD_MEM_ASRC2 64
-#define CLK_AUD_MEM_ASRC3 65
-#define CLK_AUD_MEM_ASRC4 66
-#define CLK_AUD_MEM_ASRC5 67
-#define CLK_AUD_DSD_ENC 68
-#define CLK_AUD_ASRC_BRG 60
-#define CLK_AUD_NR 70
+#define CLK_AUD_MMIF_UL1 37
+#define CLK_AUD_MMIF_UL2 38
+#define CLK_AUD_MMIF_UL3 39
+#define CLK_AUD_MMIF_UL4 40
+#define CLK_AUD_MMIF_UL5 41
+#define CLK_AUD_MMIF_UL6 42
+#define CLK_AUD_MMIF_DL1 43
+#define CLK_AUD_MMIF_DL2 44
+#define CLK_AUD_MMIF_DL3 45
+#define CLK_AUD_MMIF_DL4 46
+#define CLK_AUD_MMIF_DL5 47
+#define CLK_AUD_MMIF_DL6 48
+#define CLK_AUD_MMIF_DLMCH 49
+#define CLK_AUD_MMIF_ARB1 50
+#define CLK_AUD_MMIF_AWB1 51
+#define CLK_AUD_MMIF_AWB2 52
+#define CLK_AUD_MMIF_DAI 53
+
+#define CLK_AUD_DMIC1 54
+#define CLK_AUD_DMIC2 55
+#define CLK_AUD_ASRCI3 56
+#define CLK_AUD_ASRCI4 57
+#define CLK_AUD_ASRCI5 58
+#define CLK_AUD_ASRCI6 59
+#define CLK_AUD_ASRCO3 60
+#define CLK_AUD_ASRCO4 61
+#define CLK_AUD_ASRCO5 62
+#define CLK_AUD_ASRCO6 63
+#define CLK_AUD_MEM_ASRC1 64
+#define CLK_AUD_MEM_ASRC2 65
+#define CLK_AUD_MEM_ASRC3 66
+#define CLK_AUD_MEM_ASRC4 67
+#define CLK_AUD_MEM_ASRC5 68
+#define CLK_AUD_DSD_ENC 69
+#define CLK_AUD_ASRC_BRG 70
+#define CLK_AUD_NR 71
/* MMSYS */
-#define CLK_MM_SMI_COMMON 0
-#define CLK_MM_SMI_LARB0 1
-#define CLK_MM_CMDQ 2
-#define CLK_MM_MUTEX 3
-#define CLK_MM_DISP_COLOR 4
-#define CLK_MM_DISP_BLS 5
-#define CLK_MM_DISP_WDMA 6
-#define CLK_MM_DISP_RDMA 7
-#define CLK_MM_DISP_OVL 8
-#define CLK_MM_MDP_TDSHP 9
-#define CLK_MM_MDP_WROT 10
-#define CLK_MM_MDP_WDMA 11
-#define CLK_MM_MDP_RSZ1 12
-#define CLK_MM_MDP_RSZ0 13
-#define CLK_MM_MDP_RDMA 14
-#define CLK_MM_MDP_BLS_26M 15
-#define CLK_MM_CAM_MDP 16
-#define CLK_MM_FAKE_ENG 17
-#define CLK_MM_MUTEX_32K 18
-#define CLK_MM_DISP_RDMA1 19
-#define CLK_MM_DISP_UFOE 20
+
+#define CLK_MM_SMI_COMMON 1
+#define CLK_MM_SMI_LARB0 2
+#define CLK_MM_CMDQ 3
+#define CLK_MM_MUTEX 4
+#define CLK_MM_DISP_COLOR 5
+#define CLK_MM_DISP_BLS 6
+#define CLK_MM_DISP_WDMA 7
+#define CLK_MM_DISP_RDMA 8
+#define CLK_MM_DISP_OVL 9
+#define CLK_MM_MDP_TDSHP 10
+#define CLK_MM_MDP_WROT 11
+#define CLK_MM_MDP_WDMA 12
+#define CLK_MM_MDP_RSZ1 13
+#define CLK_MM_MDP_RSZ0 14
+#define CLK_MM_MDP_RDMA 15
+#define CLK_MM_MDP_BLS_26M 16
+#define CLK_MM_CAM_MDP 17
+#define CLK_MM_FAKE_ENG 18
+#define CLK_MM_MUTEX_32K 19
+#define CLK_MM_DISP_RDMA1 20
+#define CLK_MM_DISP_UFOE 21
-#define CLK_MM_DSI_ENGINE 21
-#define CLK_MM_DSI_DIG 22
-#define CLK_MM_DPI_DIGL 23
-#define CLK_MM_DPI_ENGINE 24
-#define CLK_MM_DPI1_DIGL 25
-#define CLK_MM_DPI1_ENGINE 26
-#define CLK_MM_TVE_OUTPUT 27
-#define CLK_MM_TVE_INPUT 28
-#define CLK_MM_HDMI_PIXEL 29
-#define CLK_MM_HDMI_PLL 30
-#define CLK_MM_HDMI_AUDIO 31
-#define CLK_MM_HDMI_SPDIF 32
-#define CLK_MM_TVE_FMM 33
-#define CLK_MM_NR 34
+#define CLK_MM_DSI_ENGINE 22
+#define CLK_MM_DSI_DIG 23
+#define CLK_MM_DPI_DIGL 24
+#define CLK_MM_DPI_ENGINE 25
+#define CLK_MM_DPI1_DIGL 26
+#define CLK_MM_DPI1_ENGINE 27
+#define CLK_MM_TVE_OUTPUT 28
+#define CLK_MM_TVE_INPUT 29
+#define CLK_MM_HDMI_PIXEL 30
+#define CLK_MM_HDMI_PLL 31
+#define CLK_MM_HDMI_AUDIO 32
+#define CLK_MM_HDMI_SPDIF 33
+#define CLK_MM_TVE_FMM 34
+#define CLK_MM_NR 35
/* IMGSYS */
-#define CLK_IMG_SMI_COMM 0
-#define CLK_IMG_RESZ 1
-#define CLK_IMG_JPGDEC_SMI 2
-#define CLK_IMG_JPGDEC 3
-#define CLK_IMG_VENC_LT 4
-#define CLK_IMG_VENC 5
-#define CLK_IMG_NR 6
+
+#define CLK_IMG_SMI_COMM 1
+#define CLK_IMG_RESZ 2
+#define CLK_IMG_JPGDEC_SMI 3
+#define CLK_IMG_JPGDEC 4
+#define CLK_IMG_VENC_LT 5
+#define CLK_IMG_VENC 6
+#define CLK_IMG_NR 7
/* VDEC */
-#define CLK_VDEC_CKGEN 0
-#define CLK_VDEC_LARB 1
-#define CLK_VDEC_NR 2
+
+#define CLK_VDEC_CKGEN 1
+#define CLK_VDEC_LARB 2
+#define CLK_VDEC_NR 3
/* HIFSYS */
-#define CLK_HIFSYS_USB0PHY 0
-#define CLK_HIFSYS_USB1PHY 1
-#define CLK_HIFSYS_PCIE0 2
-#define CLK_HIFSYS_PCIE1 3
-#define CLK_HIFSYS_PCIE2 4
-#define CLK_HIFSYS_NR 5
+
+#define CLK_HIFSYS_USB0PHY 1
+#define CLK_HIFSYS_USB1PHY 2
+#define CLK_HIFSYS_PCIE0 3
+#define CLK_HIFSYS_PCIE1 4
+#define CLK_HIFSYS_PCIE2 5
+#define CLK_HIFSYS_NR 6
/* ETHSYS */
-#define CLK_ETHSYS_HSDMA 0
-#define CLK_ETHSYS_ESW 1
-#define CLK_ETHSYS_GP2 2
-#define CLK_ETHSYS_GP1 3
-#define CLK_ETHSYS_PCM 4
-#define CLK_ETHSYS_GDMA 5
-#define CLK_ETHSYS_I2S 6
-#define CLK_ETHSYS_CRYPTO 7
-#define CLK_ETHSYS_NR 8
+#define CLK_ETHSYS_HSDMA 1
+#define CLK_ETHSYS_ESW 2
+#define CLK_ETHSYS_GP2 3
+#define CLK_ETHSYS_GP1 4
+#define CLK_ETHSYS_PCM 5
+#define CLK_ETHSYS_GDMA 6
+#define CLK_ETHSYS_I2S 7
+#define CLK_ETHSYS_CRYPTO 8
+#define CLK_ETHSYS_NR 9
/* G3DSYS */
-#define CLK_G3DSYS_CORE 0
-#define CLK_G3DSYS_NR 1
+#define CLK_G3DSYS_CORE 1
+#define CLK_G3DSYS_NR 2
+
+/* BDP */
+
+#define CLK_BDP_BRG_BA 1
+#define CLK_BDP_BRG_DRAM 2
+#define CLK_BDP_LARB_DRAM 3
+#define CLK_BDP_WR_VDI_PXL 4
+#define CLK_BDP_WR_VDI_DRAM 5
+#define CLK_BDP_WR_B 6
+#define CLK_BDP_DGI_IN 7
+#define CLK_BDP_DGI_OUT 8
+#define CLK_BDP_FMT_MAST_27 9
+#define CLK_BDP_FMT_B 10
+#define CLK_BDP_OSD_B 11
+#define CLK_BDP_OSD_DRAM 12
+#define CLK_BDP_OSD_AGENT 13
+#define CLK_BDP_OSD_PXL 14
+#define CLK_BDP_RLE_B 15
+#define CLK_BDP_RLE_AGENT 16
+#define CLK_BDP_RLE_DRAM 17
+#define CLK_BDP_F27M 18
+#define CLK_BDP_F27M_VDOUT 19
+#define CLK_BDP_F27_74_74 20
+#define CLK_BDP_F2FS 21
+#define CLK_BDP_F2FS74_148 22
+#define CLK_BDP_FB 23
+#define CLK_BDP_VDO_DRAM 24
+#define CLK_BDP_VDO_2FS 25
+#define CLK_BDP_VDO_B 26
+#define CLK_BDP_WR_DI_PXL 27
+#define CLK_BDP_WR_DI_DRAM 28
+#define CLK_BDP_WR_DI_B 29
+#define CLK_BDP_NR_PXL 30
+#define CLK_BDP_NR_DRAM 31
+#define CLK_BDP_NR_B 32
+
+#define CLK_BDP_RX_F 33
+#define CLK_BDP_RX_X 34
+#define CLK_BDP_RXPDT 35
+#define CLK_BDP_RX_CSCL_N 36
+#define CLK_BDP_RX_CSCL 37
+#define CLK_BDP_RX_DDCSCL_N 38
+#define CLK_BDP_RX_DDCSCL 39
+#define CLK_BDP_RX_VCO 40
+#define CLK_BDP_RX_DP 41
+#define CLK_BDP_RX_P 42
+#define CLK_BDP_RX_M 43
+#define CLK_BDP_RX_PLL 44
+#define CLK_BDP_BRG_RT_B 45
+#define CLK_BDP_BRG_RT_DRAM 46
+#define CLK_BDP_LARBRT_DRAM 47
+#define CLK_BDP_TMDS_SYN 48
+#define CLK_BDP_HDMI_MON 49
+#define CLK_BDP_NR 50
#endif /* _DT_BINDINGS_CLK_MT2701_H */
diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h
index e24c759..5232591 100644
--- a/include/dt-bindings/clock/mt7981-clk.h
+++ b/include/dt-bindings/clock/mt7981-clk.h
@@ -8,260 +8,219 @@
#ifndef _DT_BINDINGS_CLK_MT7981_H
#define _DT_BINDINGS_CLK_MT7981_H
-/* INFRACFG */
-
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_UART 1
-#define CK_INFRA_ISPI0 2
-#define CK_INFRA_I2C 3
-#define CK_INFRA_ISPI1 4
-#define CK_INFRA_PWM 5
-#define CK_INFRA_66M_MCK 6
-#define CK_INFRA_CK_F32K 7
-#define CK_INFRA_PCIE_CK 8
-#define CK_INFRA_PWM_BCK 9
-#define CK_INFRA_PWM_CK1 10
-#define CK_INFRA_PWM_CK2 11
-#define CK_INFRA_133M_HCK 12
-#define CK_INFRA_66M_PHCK 13
-#define CK_INFRA_FAUD_L_CK 14
-#define CK_INFRA_FAUD_AUD_CK 15
-#define CK_INFRA_FAUD_EG2_CK 16
-#define CK_INFRA_I2CS_CK 17
-#define CK_INFRA_MUX_UART0 18
-#define CK_INFRA_MUX_UART1 19
-#define CK_INFRA_MUX_UART2 20
-#define CK_INFRA_NFI_CK 21
-#define CK_INFRA_SPINFI_CK 22
-#define CK_INFRA_MUX_SPI0 23
-#define CK_INFRA_MUX_SPI1 24
-#define CK_INFRA_MUX_SPI2 25
-#define CK_INFRA_RTC_32K 26
-#define CK_INFRA_FMSDC_CK 27
-#define CK_INFRA_FMSDC_HCK_CK 28
-#define CK_INFRA_PERI_133M 29
-#define CK_INFRA_133M_PHCK 30
-#define CK_INFRA_USB_SYS_CK 31
-#define CK_INFRA_USB_CK 32
-#define CK_INFRA_USB_XHCI_CK 33
-#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
-#define CK_INFRA_F26M_CK0 35
-#define CK_INFRA_133M_MCK 36
-#define CLK_INFRA_NR_CLK 37
-
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
-#define CK_TOP_CB_M_416M 1
-#define CK_TOP_CB_M_D2 2
-#define CK_TOP_CB_M_D3 3
-#define CK_TOP_M_D3_D2 4
-#define CK_TOP_CB_M_D4 5
-#define CK_TOP_CB_M_D8 6
-#define CK_TOP_M_D8_D2 7
-#define CK_TOP_CB_MM_720M 8
-#define CK_TOP_CB_MM_D2 9
-#define CK_TOP_CB_MM_D3 10
-#define CK_TOP_CB_MM_D3_D5 11
-#define CK_TOP_CB_MM_D4 12
-#define CK_TOP_CB_MM_D6 13
-#define CK_TOP_MM_D6_D2 14
-#define CK_TOP_CB_MM_D8 15
-#define CK_TOP_CB_APLL2_196M 16
-#define CK_TOP_APLL2_D2 17
-#define CK_TOP_APLL2_D4 18
-#define CK_TOP_NET1_2500M 19
-#define CK_TOP_CB_NET1_D4 20
-#define CK_TOP_CB_NET1_D5 21
-#define CK_TOP_NET1_D5_D2 22
-#define CK_TOP_NET1_D5_D4 23
-#define CK_TOP_CB_NET1_D8 24
-#define CK_TOP_NET1_D8_D2 25
-#define CK_TOP_NET1_D8_D4 26
-#define CK_TOP_CB_NET2_800M 27
-#define CK_TOP_CB_NET2_D2 28
-#define CK_TOP_CB_NET2_D4 29
-#define CK_TOP_NET2_D4_D2 30
-#define CK_TOP_NET2_D4_D4 31
-#define CK_TOP_CB_NET2_D6 32
-#define CK_TOP_CB_WEDMCU_208M 33
-#define CK_TOP_CB_SGM_325M 34
-#define CK_TOP_CKSQ_40M_D2 35
-#define CK_TOP_CB_RTC_32K 36
-#define CK_TOP_CB_RTC_32P7K 37
-#define CK_TOP_USB_TX250M 38
-#define CK_TOP_FAUD 39
-#define CK_TOP_NFI1X 40
-#define CK_TOP_USB_EQ_RX250M 41
-#define CK_TOP_USB_CDR_CK 42
-#define CK_TOP_USB_LN0_CK 43
-#define CK_TOP_SPINFI_BCK 44
-#define CK_TOP_SPI 45
-#define CK_TOP_SPIM_MST 46
-#define CK_TOP_UART_BCK 47
-#define CK_TOP_PWM_BCK 48
-#define CK_TOP_I2C_BCK 49
-#define CK_TOP_PEXTP_TL 50
-#define CK_TOP_EMMC_208M 51
-#define CK_TOP_EMMC_400M 52
-#define CK_TOP_DRAMC_REF 53
-#define CK_TOP_DRAMC_MD32 54
-#define CK_TOP_SYSAXI 55
-#define CK_TOP_SYSAPB 56
-#define CK_TOP_ARM_DB_MAIN 57
-#define CK_TOP_AP2CNN_HOST 58
-#define CK_TOP_NETSYS 59
-#define CK_TOP_NETSYS_500M 60
-#define CK_TOP_NETSYS_WED_MCU 61
-#define CK_TOP_NETSYS_2X 62
-#define CK_TOP_SGM_325M 63
-#define CK_TOP_SGM_REG 64
-#define CK_TOP_F26M 65
-#define CK_TOP_EIP97B 66
-#define CK_TOP_USB3_PHY 67
-#define CK_TOP_AUD 68
-#define CK_TOP_A1SYS 69
-#define CK_TOP_AUD_L 70
-#define CK_TOP_A_TUNER 71
-#define CK_TOP_U2U3_REF 72
-#define CK_TOP_U2U3_SYS 73
-#define CK_TOP_U2U3_XHCI 74
-#define CK_TOP_USB_FRMCNT 75
-#define CK_TOP_NFI1X_SEL 76
-#define CK_TOP_SPINFI_SEL 77
-#define CK_TOP_SPI_SEL 78
-#define CK_TOP_SPIM_MST_SEL 79
-#define CK_TOP_UART_SEL 80
-#define CK_TOP_PWM_SEL 81
-#define CK_TOP_I2C_SEL 82
-#define CK_TOP_PEXTP_TL_SEL 83
-#define CK_TOP_EMMC_208M_SEL 84
-#define CK_TOP_EMMC_400M_SEL 85
-#define CK_TOP_F26M_SEL 86
-#define CK_TOP_DRAMC_SEL 87
-#define CK_TOP_DRAMC_MD32_SEL 88
-#define CK_TOP_SYSAXI_SEL 89
-#define CK_TOP_SYSAPB_SEL 90
-#define CK_TOP_ARM_DB_MAIN_SEL 91
-#define CK_TOP_AP2CNN_HOST_SEL 92
-#define CK_TOP_NETSYS_SEL 93
-#define CK_TOP_NETSYS_500M_SEL 94
-#define CK_TOP_NETSYS_MCU_SEL 95
-#define CK_TOP_NETSYS_2X_SEL 96
-#define CK_TOP_SGM_325M_SEL 97
-#define CK_TOP_SGM_REG_SEL 98
-#define CK_TOP_EIP97B_SEL 99
-#define CK_TOP_USB3_PHY_SEL 100
-#define CK_TOP_AUD_SEL 101
-#define CK_TOP_A1SYS_SEL 102
-#define CK_TOP_AUD_L_SEL 103
-#define CK_TOP_A_TUNER_SEL 104
-#define CK_TOP_U2U3_SEL 105
-#define CK_TOP_U2U3_SYS_SEL 106
-#define CK_TOP_U2U3_XHCI_SEL 107
-#define CK_TOP_USB_FRMCNT_SEL 108
-#define CLK_TOP_NR_CLK 109
+#define CLK_TOP_CB_CKSQ_40M 0
+#define CLK_TOP_CB_M_416M 1
+#define CLK_TOP_CB_M_D2 2
+#define CLK_TOP_CB_M_D3 3
+#define CLK_TOP_M_D3_D2 4
+#define CLK_TOP_CB_M_D4 5
+#define CLK_TOP_CB_M_D8 6
+#define CLK_TOP_M_D8_D2 7
+#define CLK_TOP_CB_MM_720M 8
+#define CLK_TOP_CB_MM_D2 9
+#define CLK_TOP_CB_MM_D3 10
+#define CLK_TOP_CB_MM_D3_D5 11
+#define CLK_TOP_CB_MM_D4 12
+#define CLK_TOP_CB_MM_D6 13
+#define CLK_TOP_MM_D6_D2 14
+#define CLK_TOP_CB_MM_D8 15
+#define CLK_TOP_CB_APLL2_196M 16
+#define CLK_TOP_APLL2_D2 17
+#define CLK_TOP_APLL2_D4 18
+#define CLK_TOP_NET1_2500M 19
+#define CLK_TOP_CB_NET1_D4 20
+#define CLK_TOP_CB_NET1_D5 21
+#define CLK_TOP_NET1_D5_D2 22
+#define CLK_TOP_NET1_D5_D4 23
+#define CLK_TOP_CB_NET1_D8 24
+#define CLK_TOP_NET1_D8_D2 25
+#define CLK_TOP_NET1_D8_D4 26
+#define CLK_TOP_CB_NET2_800M 27
+#define CLK_TOP_CB_NET2_D2 28
+#define CLK_TOP_CB_NET2_D4 29
+#define CLK_TOP_NET2_D4_D2 30
+#define CLK_TOP_NET2_D4_D4 31
+#define CLK_TOP_CB_NET2_D6 32
+#define CLK_TOP_CB_WEDMCU_208M 33
+#define CLK_TOP_CB_SGM_325M 34
+#define CLK_TOP_CKSQ_40M_D2 35
+#define CLK_TOP_CB_RTC_32K 36
+#define CLK_TOP_CB_RTC_32P7K 37
+#define CLK_TOP_USB_TX250M 38
+#define CLK_TOP_FAUD 39
+#define CLK_TOP_NFI1X 40
+#define CLK_TOP_USB_EQ_RX250M 41
+#define CLK_TOP_USB_CDR_CK 42
+#define CLK_TOP_USB_LN0_CK 43
+#define CLK_TOP_SPINFI_BCK 44
+#define CLK_TOP_SPI 45
+#define CLK_TOP_SPIM_MST 46
+#define CLK_TOP_UART_BCK 47
+#define CLK_TOP_PWM_BCK 48
+#define CLK_TOP_I2C_BCK 49
+#define CLK_TOP_PEXTP_TL 50
+#define CLK_TOP_EMMC_208M 51
+#define CLK_TOP_EMMC_400M 52
+#define CLK_TOP_DRAMC_REF 53
+#define CLK_TOP_DRAMC_MD32 54
+#define CLK_TOP_SYSAXI 55
+#define CLK_TOP_SYSAPB 56
+#define CLK_TOP_ARM_DB_MAIN 57
+#define CLK_TOP_AP2CNN_HOST 58
+#define CLK_TOP_NETSYS 59
+#define CLK_TOP_NETSYS_500M 60
+#define CLK_TOP_NETSYS_WED_MCU 61
+#define CLK_TOP_NETSYS_2X 62
+#define CLK_TOP_SGM_325M 63
+#define CLK_TOP_SGM_REG 64
+#define CLK_TOP_F26M 65
+#define CLK_TOP_EIP97B 66
+#define CLK_TOP_USB3_PHY 67
+#define CLK_TOP_AUD 68
+#define CLK_TOP_A1SYS 69
+#define CLK_TOP_AUD_L 70
+#define CLK_TOP_A_TUNER 71
+#define CLK_TOP_U2U3_REF 72
+#define CLK_TOP_U2U3_SYS 73
+#define CLK_TOP_U2U3_XHCI 74
+#define CLK_TOP_USB_FRMCNT 75
+#define CLK_TOP_NFI1X_SEL 76
+#define CLK_TOP_SPINFI_SEL 77
+#define CLK_TOP_SPI_SEL 78
+#define CLK_TOP_SPIM_MST_SEL 79
+#define CLK_TOP_UART_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_I2C_SEL 82
+#define CLK_TOP_PEXTP_TL_SEL 83
+#define CLK_TOP_EMMC_208M_SEL 84
+#define CLK_TOP_EMMC_400M_SEL 85
+#define CLK_TOP_F26M_SEL 86
+#define CLK_TOP_DRAMC_SEL 87
+#define CLK_TOP_DRAMC_MD32_SEL 88
+#define CLK_TOP_SYSAXI_SEL 89
+#define CLK_TOP_SYSAPB_SEL 90
+#define CLK_TOP_ARM_DB_MAIN_SEL 91
+#define CLK_TOP_AP2CNN_HOST_SEL 92
+#define CLK_TOP_NETSYS_SEL 93
+#define CLK_TOP_NETSYS_500M_SEL 94
+#define CLK_TOP_NETSYS_MCU_SEL 95
+#define CLK_TOP_NETSYS_2X_SEL 96
+#define CLK_TOP_SGM_325M_SEL 97
+#define CLK_TOP_SGM_REG_SEL 98
+#define CLK_TOP_EIP97B_SEL 99
+#define CLK_TOP_USB3_PHY_SEL 100
+#define CLK_TOP_AUD_SEL 101
+#define CLK_TOP_A1SYS_SEL 102
+#define CLK_TOP_AUD_L_SEL 103
+#define CLK_TOP_A_TUNER_SEL 104
+#define CLK_TOP_U2U3_SEL 105
+#define CLK_TOP_U2U3_SYS_SEL 106
+#define CLK_TOP_U2U3_XHCI_SEL 107
+#define CLK_TOP_USB_FRMCNT_SEL 108
+#define CLK_TOP_AUD_I2S_M 109
+#define CLK_TOP_NR_CLK 110
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
-#define INFRACFG_AO_OFFSET 10
+/* INFRACFG */
-#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET)
-#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET)
+#define CLK_INFRA_66M_MCK 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_SPI2_SEL 6
+#define CLK_INFRA_PWM1_SEL 7
+#define CLK_INFRA_PWM2_SEL 8
+#define CLK_INFRA_PWM3_SEL 9
+#define CLK_INFRA_PWM_BSEL 10
+#define CLK_INFRA_PCIE_SEL 11
+#define CLK_INFRA_GPT_STA 12
+#define CLK_INFRA_PWM_HCK 13
+#define CLK_INFRA_PWM_STA 14
+#define CLK_INFRA_PWM1_CK 15
+#define CLK_INFRA_PWM2_CK 16
+#define CLK_INFRA_PWM3_CK 17
+#define CLK_INFRA_CQ_DMA_CK 18
+#define CLK_INFRA_AUD_BUS_CK 19
+#define CLK_INFRA_AUD_26M_CK 20
+#define CLK_INFRA_AUD_L_CK 21
+#define CLK_INFRA_AUD_AUD_CK 22
+#define CLK_INFRA_AUD_EG2_CK 23
+#define CLK_INFRA_DRAMC_26M_CK 24
+#define CLK_INFRA_DBG_CK 25
+#define CLK_INFRA_AP_DMA_CK 26
+#define CLK_INFRA_SEJ_CK 27
+#define CLK_INFRA_SEJ_13M_CK 28
+#define CLK_INFRA_THERM_CK 29
+#define CLK_INFRA_I2C0_CK 30
+#define CLK_INFRA_UART0_CK 31
+#define CLK_INFRA_UART1_CK 32
+#define CLK_INFRA_UART2_CK 33
+#define CLK_INFRA_SPI2_CK 34
+#define CLK_INFRA_SPI2_HCK_CK 35
+#define CLK_INFRA_NFI1_CK 36
+#define CLK_INFRA_SPINFI1_CK 37
+#define CLK_INFRA_NFI_HCK_CK 38
+#define CLK_INFRA_SPI0_CK 39
+#define CLK_INFRA_SPI1_CK 40
+#define CLK_INFRA_SPI0_HCK_CK 41
+#define CLK_INFRA_SPI1_HCK_CK 42
+#define CLK_INFRA_FRTC_CK 43
+#define CLK_INFRA_MSDC_CK 44
+#define CLK_INFRA_MSDC_HCK_CK 45
+#define CLK_INFRA_MSDC_133M_CK 46
+#define CLK_INFRA_MSDC_66M_CK 47
+#define CLK_INFRA_ADC_26M_CK 48
+#define CLK_INFRA_ADC_FRC_CK 49
+#define CLK_INFRA_FBIST2FPC_CK 50
+#define CLK_INFRA_I2C_MCK_CK 51
+#define CLK_INFRA_I2C_PCK_CK 52
+#define CLK_INFRA_IUSB_133_CK 53
+#define CLK_INFRA_IUSB_66M_CK 54
+#define CLK_INFRA_IUSB_SYS_CK 55
+#define CLK_INFRA_IUSB_CK 56
+#define CLK_INFRA_IPCIE_CK 57
+#define CLK_INFRA_IPCIE_PIPE_CK 58
+#define CLK_INFRA_IPCIER_CK 59
+#define CLK_INFRA_IPCIEB_CK 60
+#define CLK_INFRA_NR_CLK 61
/* APMIXEDSYS */
-#define CK_APMIXED_ARMPLL 0
-#define CK_APMIXED_NET2PLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_SGMPLL 3
-#define CK_APMIXED_WEDMCUPLL 4
-#define CK_APMIXED_NET1PLL 5
-#define CK_APMIXED_MPLL 6
-#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
#define CLK_APMIXED_NR_CLK 8
/* SGMIISYS_0 */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
-#define CK_SGM0_CK0_EN 2
-#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
#define CLK_SGMII0_NR_CLK 4
/* SGMIISYS_1 */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
-#define CK_SGM1_CK1_EN 2
-#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
#define CLK_SGMII1_NR_CLK 4
/* ETHSYS */
-#define CK_ETH_FE_EN 0
-#define CK_ETH_GP2_EN 1
-#define CK_ETH_GP1_EN 2
-#define CK_ETH_WOCPU0_EN 3
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU0_EN 3
#define CLK_ETH_NR_CLK 4
#endif /* _DT_BINDINGS_CLK_MT7981_H */
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 820f863..5da2603 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -8,240 +8,169 @@
#ifndef _DT_BINDINGS_CLK_MT7986_H
#define _DT_BINDINGS_CLK_MT7986_H
-/* INFRACFG */
-
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_UART 1
-#define CK_INFRA_ISPI0 2
-#define CK_INFRA_I2C 3
-#define CK_INFRA_ISPI1 4
-#define CK_INFRA_PWM 5
-#define CK_INFRA_66M_MCK 6
-#define CK_INFRA_CK_F32K 7
-#define CK_INFRA_PCIE_CK 8
-#define CK_INFRA_PWM_BCK 9
-#define CK_INFRA_PWM_CK1 10
-#define CK_INFRA_PWM_CK2 11
-#define CK_INFRA_133M_HCK 12
-#define CK_INFRA_EIP_CK 13
-#define CK_INFRA_66M_PHCK 14
-#define CK_INFRA_FAUD_L_CK 15
-#define CK_INFRA_FAUD_AUD_CK 17
-#define CK_INFRA_FAUD_EG2_CK 17
-#define CK_INFRA_I2CS_CK 18
-#define CK_INFRA_MUX_UART0 19
-#define CK_INFRA_MUX_UART1 20
-#define CK_INFRA_MUX_UART2 21
-#define CK_INFRA_NFI_CK 22
-#define CK_INFRA_SPINFI_CK 23
-#define CK_INFRA_MUX_SPI0 24
-#define CK_INFRA_MUX_SPI1 25
-#define CK_INFRA_RTC_32K 26
-#define CK_INFRA_FMSDC_CK 27
-#define CK_INFRA_FMSDC_HCK_CK 28
-#define CK_INFRA_PERI_133M 29
-#define CK_INFRA_133M_PHCK 30
-#define CK_INFRA_USB_SYS_CK 31
-#define CK_INFRA_USB_CK 32
-#define CK_INFRA_USB_XHCI_CK 33
-#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
-#define CK_INFRA_F26M_CK0 35
-#define CK_INFRA_HD_133M 36
-#define CLK_INFRA_NR_CLK 37
-
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
-#define CK_TOP_CB_M_416M 1
-#define CK_TOP_CB_M_D2 2
-#define CK_TOP_CB_M_D4 3
-#define CK_TOP_CB_M_D8 4
-#define CK_TOP_M_D8_D2 5
-#define CK_TOP_M_D3_D2 6
-#define CK_TOP_CB_MM_D2 7
-#define CK_TOP_CB_MM_D4 8
-#define CK_TOP_CB_MM_D8 9
-#define CK_TOP_MM_D8_D2 10
-#define CK_TOP_MM_D3_D8 11
-#define CK_TOP_CB_U2_PHYD_CK 12
-#define CK_TOP_CB_APLL2_196M 13
-#define CK_TOP_APLL2_D4 14
-#define CK_TOP_CB_NET1_D4 15
-#define CK_TOP_CB_NET1_D5 16
-#define CK_TOP_NET1_D5_D2 17
-#define CK_TOP_NET1_D5_D4 18
-#define CK_TOP_NET1_D8_D2 19
-#define CK_TOP_NET1_D8_D4 20
-#define CK_TOP_CB_NET2_800M 21
-#define CK_TOP_CB_NET2_D4 22
-#define CK_TOP_NET2_D4_D2 23
-#define CK_TOP_NET2_D3_D2 24
-#define CK_TOP_CB_WEDMCU_760M 25
-#define CK_TOP_WEDMCU_D5_D2 26
-#define CK_TOP_CB_SGM_325M 27
-#define CK_TOP_CB_CKSQ_40M_D2 28
-#define CK_TOP_CB_RTC_32K 29
-#define CK_TOP_CB_RTC_32P7K 30
-#define CK_TOP_NFI1X 31
-#define CK_TOP_USB_EQ_RX250M 32
-#define CK_TOP_USB_TX250M 33
-#define CK_TOP_USB_LN0_CK 34
-#define CK_TOP_USB_CDR_CK 35
-#define CK_TOP_SPINFI_BCK 36
-#define CK_TOP_I2C_BCK 37
-#define CK_TOP_PEXTP_TL 38
-#define CK_TOP_EMMC_250M 39
-#define CK_TOP_EMMC_416M 40
-#define CK_TOP_F_26M_ADC_CK 41
-#define CK_TOP_SYSAXI 42
-#define CK_TOP_NETSYS_WED_MCU 43
-#define CK_TOP_NETSYS_2X 44
-#define CK_TOP_SGM_325M 45
-#define CK_TOP_A1SYS 46
-#define CK_TOP_EIP_B 47
-#define CK_TOP_F26M 48
-#define CK_TOP_AUD_L 49
-#define CK_TOP_A_TUNER 50
-#define CK_TOP_U2U3_REF 51
-#define CK_TOP_U2U3_SYS 52
-#define CK_TOP_U2U3_XHCI 53
-#define CK_TOP_AP2CNN_HOST 54
-#define CK_TOP_NFI1X_SEL 55
-#define CK_TOP_SPINFI_SEL 56
-#define CK_TOP_SPI_SEL 57
-#define CK_TOP_SPIM_MST_SEL 58
-#define CK_TOP_UART_SEL 59
-#define CK_TOP_PWM_SEL 60
-#define CK_TOP_I2C_SEL 61
-#define CK_TOP_PEXTP_TL_SEL 62
-#define CK_TOP_EMMC_250M_SEL 63
-#define CK_TOP_EMMC_416M_SEL 64
-#define CK_TOP_F_26M_ADC_SEL 65
-#define CK_TOP_DRAMC_SEL 66
-#define CK_TOP_DRAMC_MD32_SEL 67
-#define CK_TOP_SYSAXI_SEL 68
-#define CK_TOP_SYSAPB_SEL 69
-#define CK_TOP_ARM_DB_MAIN_SEL 70
-#define CK_TOP_ARM_DB_JTSEL 71
-#define CK_TOP_NETSYS_SEL 72
-#define CK_TOP_NETSYS_500M_SEL 73
-#define CK_TOP_NETSYS_MCU_SEL 74
-#define CK_TOP_NETSYS_2X_SEL 75
-#define CK_TOP_SGM_325M_SEL 76
-#define CK_TOP_SGM_REG_SEL 77
-#define CK_TOP_A1SYS_SEL 78
-#define CK_TOP_CONN_MCUSYS_SEL 79
-#define CK_TOP_EIP_B_SEL 80
-#define CK_TOP_PCIE_PHY_SEL 81
-#define CK_TOP_USB3_PHY_SEL 82
-#define CK_TOP_F26M_SEL 83
-#define CK_TOP_AUD_L_SEL 84
-#define CK_TOP_A_TUNER_SEL 85
-#define CK_TOP_U2U3_SEL 86
-#define CK_TOP_U2U3_SYS_SEL 87
-#define CK_TOP_U2U3_XHCI_SEL 88
-#define CK_TOP_DA_U2_REFSEL 89
-#define CK_TOP_DA_U2_CK_1P_SEL 90
-#define CK_TOP_AP2CNN_HOST_SEL 91
-#define CLK_TOP_NR_CLK 92
+#define CLK_TOP_XTAL 0
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+/* #define CLK_TOP_A_TUNER 4 */
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D4 5
+#define CLK_TOP_MPLL_D8 6
+#define CLK_TOP_MPLL_D8_D2 7
+#define CLK_TOP_MPLL_D3_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D4 10
+#define CLK_TOP_MMPLL_D8 11
+#define CLK_TOP_MMPLL_D8_D2 12
+#define CLK_TOP_MMPLL_D3_D8 13
+#define CLK_TOP_MMPLL_U2PHYD 14
+#define CLK_TOP_APLL2_D4 15
+#define CLK_TOP_NET1PLL_D4 16
+#define CLK_TOP_NET1PLL_D5 17
+#define CLK_TOP_NET1PLL_D5_D2 18
+#define CLK_TOP_NET1PLL_D5_D4 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET2PLL_D4 22
+#define CLK_TOP_NET2PLL_D4_D2 23
+#define CLK_TOP_NET2PLL_D3_D2 24
+#define CLK_TOP_WEDMCUPLL_D5_D2 25
+#define CLK_TOP_NFI1X_SEL 26
+#define CLK_TOP_SPINFI_SEL 27
+#define CLK_TOP_SPI_SEL 28
+#define CLK_TOP_SPIM_MST_SEL 29
+#define CLK_TOP_UART_SEL 30
+#define CLK_TOP_PWM_SEL 31
+#define CLK_TOP_I2C_SEL 32
+#define CLK_TOP_PEXTP_TL_SEL 33
+#define CLK_TOP_EMMC_250M_SEL 34
+#define CLK_TOP_EMMC_416M_SEL 35
+#define CLK_TOP_F_26M_ADC_SEL 36
+#define CLK_TOP_DRAMC_SEL 37
+#define CLK_TOP_DRAMC_MD32_SEL 38
+#define CLK_TOP_SYSAXI_SEL 39
+#define CLK_TOP_SYSAPB_SEL 40
+#define CLK_TOP_ARM_DB_MAIN_SEL 41
+#define CLK_TOP_ARM_DB_JTSEL 42
+#define CLK_TOP_NETSYS_SEL 43
+#define CLK_TOP_NETSYS_500M_SEL 44
+#define CLK_TOP_NETSYS_MCU_SEL 45
+#define CLK_TOP_NETSYS_2X_SEL 46
+#define CLK_TOP_SGM_325M_SEL 47
+#define CLK_TOP_SGM_REG_SEL 48
+#define CLK_TOP_A1SYS_SEL 49
+#define CLK_TOP_CONN_MCUSYS_SEL 50
+#define CLK_TOP_EIP_B_SEL 51
+#define CLK_TOP_PCIE_PHY_SEL 52
+#define CLK_TOP_USB3_PHY_SEL 53
+#define CLK_TOP_F26M_SEL 54
+#define CLK_TOP_AUD_L_SEL 55
+#define CLK_TOP_A_TUNER_SEL 56
+#define CLK_TOP_U2U3_SEL 57
+#define CLK_TOP_U2U3_SYS_SEL 58
+#define CLK_TOP_U2U3_XHCI_SEL 59
+#define CLK_TOP_DA_U2_REFSEL 60
+#define CLK_TOP_DA_U2_CK_1P_SEL 61
+#define CLK_TOP_AP2CNN_HOST_SEL 62
+#define CLK_TOP_NR_CLK 63
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
+/* INFRACFG */
-#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA 0
-#define CK_INFRA_PWM_HCK 1
-#define CK_INFRA_PWM_STA 2
-#define CK_INFRA_PWM1_CK 3
-#define CK_INFRA_PWM2_CK 4
-#define CK_INFRA_CQ_DMA_CK 5
-#define CK_INFRA_EIP97_CK 6
-#define CK_INFRA_AUD_BUS_CK 7
-#define CK_INFRA_AUD_26M_CK 8
-#define CK_INFRA_AUD_L_CK 9
-#define CK_INFRA_AUD_AUD_CK 10
-#define CK_INFRA_AUD_EG2_CK 11
-#define CK_INFRA_DRAMC_26M_CK 12
-#define CK_INFRA_DBG_CK 13
-#define CK_INFRA_AP_DMA_CK 14
-#define CK_INFRA_SEJ_CK 15
-#define CK_INFRA_SEJ_13M_CK 16
-#define CK_INFRA_THERM_CK 17
-#define CK_INFRA_I2CO_CK 18
-#define CK_INFRA_TRNG_CK 19
-#define CK_INFRA_UART0_CK 20
-#define CK_INFRA_UART1_CK 21
-#define CK_INFRA_UART2_CK 22
-#define CK_INFRA_NFI1_CK 23
-#define CK_INFRA_SPINFI1_CK 24
-#define CK_INFRA_NFI_HCK_CK 25
-#define CK_INFRA_SPI0_CK 26
-#define CK_INFRA_SPI1_CK 27
-#define CK_INFRA_SPI0_HCK_CK 28
-#define CK_INFRA_SPI1_HCK_CK 29
-#define CK_INFRA_FRTC_CK 30
-#define CK_INFRA_MSDC_CK 31
-#define CK_INFRA_MSDC_HCK_CK 32
-#define CK_INFRA_MSDC_133M_CK 33
-#define CK_INFRA_MSDC_66M_CK 34
-#define CK_INFRA_ADC_26M_CK 35
-#define CK_INFRA_ADC_FRC_CK 36
-#define CK_INFRA_FBIST2FPC_CK 37
-#define CK_INFRA_IUSB_133_CK 38
-#define CK_INFRA_IUSB_66M_CK 39
-#define CK_INFRA_IUSB_SYS_CK 40
-#define CK_INFRA_IUSB_CK 41
-#define CK_INFRA_IPCIE_CK 42
-#define CK_INFRA_IPCIER_CK 43
-#define CK_INFRA_IPCIEB_CK 44
-#define CLK_INFRA_AO_NR_CLK 45
+#define CLK_INFRA_SYSAXI_D2 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_PWM1_SEL 6
+#define CLK_INFRA_PWM2_SEL 7
+#define CLK_INFRA_PWM_BSEL 8
+#define CLK_INFRA_PCIE_SEL 9
+#define CLK_INFRA_GPT_STA 10
+#define CLK_INFRA_PWM_HCK 11
+#define CLK_INFRA_PWM_STA 12
+#define CLK_INFRA_PWM1_CK 13
+#define CLK_INFRA_PWM2_CK 14
+#define CLK_INFRA_CQ_DMA_CK 15
+#define CLK_INFRA_EIP97_CK 16
+#define CLK_INFRA_AUD_BUS_CK 17
+#define CLK_INFRA_AUD_26M_CK 18
+#define CLK_INFRA_AUD_L_CK 19
+#define CLK_INFRA_AUD_AUD_CK 20
+#define CLK_INFRA_AUD_EG2_CK 21
+#define CLK_INFRA_DRAMC_26M_CK 22
+#define CLK_INFRA_DBG_CK 23
+#define CLK_INFRA_AP_DMA_CK 24
+#define CLK_INFRA_SEJ_CK 25
+#define CLK_INFRA_SEJ_13M_CK 26
+#define CLK_INFRA_THERM_CK 27
+#define CLK_INFRA_I2C0_CK 28
+#define CLK_INFRA_UART0_CK 29
+#define CLK_INFRA_UART1_CK 30
+#define CLK_INFRA_UART2_CK 31
+#define CLK_INFRA_NFI1_CK 32
+#define CLK_INFRA_SPINFI1_CK 33
+#define CLK_INFRA_NFI_HCK_CK 34
+#define CLK_INFRA_SPI0_CK 35
+#define CLK_INFRA_SPI1_CK 36
+#define CLK_INFRA_SPI0_HCK_CK 37
+#define CLK_INFRA_SPI1_HCK_CK 38
+#define CLK_INFRA_FRTC_CK 39
+#define CLK_INFRA_MSDC_CK 40
+#define CLK_INFRA_MSDC_HCK_CK 41
+#define CLK_INFRA_MSDC_133M_CK 42
+#define CLK_INFRA_MSDC_66M_CK 43
+#define CLK_INFRA_ADC_26M_CK 44
+#define CLK_INFRA_ADC_FRC_CK 45
+#define CLK_INFRA_FBIST2FPC_CK 46
+#define CLK_INFRA_IUSB_133_CK 47
+#define CLK_INFRA_IUSB_66M_CK 48
+#define CLK_INFRA_IUSB_SYS_CK 49
+#define CLK_INFRA_IUSB_CK 50
+#define CLK_INFRA_IPCIE_CK 51
+#define CLK_INFRA_IPCIE_PIPE_CK 52
+#define CLK_INFRA_IPCIER_CK 53
+#define CLK_INFRA_IPCIEB_CK 54
+#define CLK_INFRA_TRNG_CK 55
+#define CLK_INFRA_AO_NR_CLK 46
/* APMIXEDSYS */
-#define CK_APMIXED_ARMPLL 0
-#define CK_APMIXED_NET2PLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_SGMPLL 3
-#define CK_APMIXED_WEDMCUPLL 4
-#define CK_APMIXED_NET1PLL 5
-#define CK_APMIXED_MPLL 6
-#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
#define CLK_APMIXED_NR_CLK 8
/* SGMIISYS_0 */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
-#define CK_SGM0_CK0_EN 2
-#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
#define CLK_SGMII0_NR_CLK 4
/* SGMIISYS_1 */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
-#define CK_SGM1_CK1_EN 2
-#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
#define CLK_SGMII1_NR_CLK 4
/* ETHSYS */
-#define CK_ETH_FE_EN 0
-#define CK_ETH_GP2_EN 1
-#define CK_ETH_GP1_EN 2
-#define CK_ETH_WOCPU1_EN 3
-#define CK_ETH_WOCPU0_EN 4
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU1_EN 3
+#define CLK_ETH_WOCPU0_EN 4
#define CLK_ETH_NR_CLK 5
#endif
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 5c21bf6..e6e6978 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -8,342 +8,257 @@
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
-/* INFRACFG */
-/* mtk_fixed_factor */
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_PWM_O 1
-#define CK_INFRA_PCIE_OCC_P0 2
-#define CK_INFRA_PCIE_OCC_P1 3
-#define CK_INFRA_PCIE_OCC_P2 4
-#define CK_INFRA_PCIE_OCC_P3 5
-#define CK_INFRA_133M_HCK 6
-#define CK_INFRA_133M_PHCK 7
-#define CK_INFRA_66M_PHCK 8
-#define CK_INFRA_FAUD_L_O 9
-#define CK_INFRA_FAUD_AUD_O 10
-#define CK_INFRA_FAUD_EG2_O 11
-#define CK_INFRA_I2C_O 12
-#define CK_INFRA_UART_O0 13
-#define CK_INFRA_UART_O1 14
-#define CK_INFRA_UART_O2 15
-#define CK_INFRA_NFI_O 16
-#define CK_INFRA_SPINFI_O 17
-#define CK_INFRA_SPI0_O 18
-#define CK_INFRA_SPI1_O 19
-#define CK_INFRA_LB_MUX_FRTC 20
-#define CK_INFRA_FRTC 21
-#define CK_INFRA_FMSDC400_O 22
-#define CK_INFRA_FMSDC2_HCK_OCC 23
-#define CK_INFRA_PERI_133M 24
-#define CK_INFRA_USB_O 25
-#define CK_INFRA_USB_O_P1 26
-#define CK_INFRA_USB_FRMCNT_O 27
-#define CK_INFRA_USB_FRMCNT_O_P1 28
-#define CK_INFRA_USB_XHCI_O 29
-#define CK_INFRA_USB_XHCI_O_P1 30
-#define CK_INFRA_USB_PIPE_O 31
-#define CK_INFRA_USB_PIPE_O_P1 32
-#define CK_INFRA_USB_UTMI_O 33
-#define CK_INFRA_USB_UTMI_O_P1 34
-#define CK_INFRA_PCIE_PIPE_OCC_P0 35
-#define CK_INFRA_PCIE_PIPE_OCC_P1 36
-#define CK_INFRA_PCIE_PIPE_OCC_P2 37
-#define CK_INFRA_PCIE_PIPE_OCC_P3 38
-#define CK_INFRA_F26M_O0 39
-#define CK_INFRA_F26M_O1 40
-#define CK_INFRA_133M_MCK 41
-#define CK_INFRA_66M_MCK 42
-#define CK_INFRA_PERI_66M_O 43
-#define CK_INFRA_USB_SYS_O 44
-#define CK_INFRA_USB_SYS_O_P1 45
-
/* INFRACFG_AO */
-#define GATE_OFFSET 65
/* mtk_mux */
-#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */
-#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */
-#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */
-#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */
-#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */
-#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */
-#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */
-#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */
-#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */
-#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */
-#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */
-#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */
-#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */
-#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */
-#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
+#define CLK_INFRA_MUX_UART0_SEL 0
+#define CLK_INFRA_MUX_UART1_SEL 1
+#define CLK_INFRA_MUX_UART2_SEL 2
+#define CLK_INFRA_MUX_SPI0_SEL 3
+#define CLK_INFRA_MUX_SPI1_SEL 4
+#define CLK_INFRA_MUX_SPI2_SEL 5
+#define CLK_INFRA_PWM_SEL 6
+#define CLK_INFRA_PWM_CK1_SEL 7
+#define CLK_INFRA_PWM_CK2_SEL 8
+#define CLK_INFRA_PWM_CK3_SEL 9
+#define CLK_INFRA_PWM_CK4_SEL 10
+#define CLK_INFRA_PWM_CK5_SEL 11
+#define CLK_INFRA_PWM_CK6_SEL 12
+#define CLK_INFRA_PWM_CK7_SEL 13
+#define CLK_INFRA_PWM_CK8_SEL 14
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
+
+/* INFRACFG */
/* mtk_gate */
-#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */
-#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */
-#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */
-#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */
-#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */
-#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */
-#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */
-#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */
-#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */
-#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */
-#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */
-#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */
-#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */
-#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */
-#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */
-#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */
-#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */
-#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */
-#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */
-#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */
-#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */
-#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */
-#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */
-#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */
-#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */
-#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */
-#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */
-#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */
-#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
- (146 - GATE_OFFSET) /* Linux CLK ID (100) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
- (147 - GATE_OFFSET) /* Linux CLK ID (101) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
- (148 - GATE_OFFSET) /* Linux CLK ID (102) */
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
+#define CLK_INFRA_66M_GPT_BCK 23
+#define CLK_INFRA_66M_PWM_HCK 24
+#define CLK_INFRA_66M_PWM_BCK 25
+#define CLK_INFRA_66M_PWM_CK1 26
+#define CLK_INFRA_66M_PWM_CK2 27
+#define CLK_INFRA_66M_PWM_CK3 28
+#define CLK_INFRA_66M_PWM_CK4 29
+#define CLK_INFRA_66M_PWM_CK5 30
+#define CLK_INFRA_66M_PWM_CK6 31
+#define CLK_INFRA_66M_PWM_CK7 32
+#define CLK_INFRA_66M_PWM_CK8 33
+#define CLK_INFRA_133M_CQDMA_BCK 34
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
+#define CLK_INFRA_AUD_26M 36
+#define CLK_INFRA_AUD_L 37
+#define CLK_INFRA_AUD_AUD 38
+#define CLK_INFRA_AUD_EG2 39
+#define CLK_INFRA_DRAMC_F26M 40
+#define CLK_INFRA_133M_DBG_ACKM 41
+#define CLK_INFRA_66M_AP_DMA_BCK 42
+#define CLK_INFRA_66M_SEJ_BCK 43
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
+/* #define CLK_INFRA_66M_TRNG 44 */
+#define CLK_INFRA_26M_THERM_SYSTEM 45
+#define CLK_INFRA_I2C_BCK 46
+/* #define CLK_INFRA_66M_UART0_PCK 46 */
+/* #define CLK_INFRA_66M_UART1_PCK 47 */
+/* #define CLK_INFRA_66M_UART2_PCK 48 */
+#define CLK_INFRA_52M_UART0_CK 47
+#define CLK_INFRA_52M_UART1_CK 48
+#define CLK_INFRA_52M_UART2_CK 49
+#define CLK_INFRA_NFI 50
+#define CLK_INFRA_SPINFI 51
+#define CLK_INFRA_66M_NFI_HCK 52
+#define CLK_INFRA_104M_SPI0 53
+#define CLK_INFRA_104M_SPI1 54
+#define CLK_INFRA_104M_SPI2_BCK 55
+#define CLK_INFRA_66M_SPI0_HCK 56
+#define CLK_INFRA_66M_SPI1_HCK 57
+#define CLK_INFRA_66M_SPI2_HCK 58
+#define CLK_INFRA_66M_FLASHIF_AXI 59
+#define CLK_INFRA_RTC 60
+#define CLK_INFRA_26M_ADC_BCK 61
+#define CLK_INFRA_RC_ADC 62
+#define CLK_INFRA_MSDC400 63
+#define CLK_INFRA_MSDC2_HCK 64
+#define CLK_INFRA_133M_MSDC_0_HCK 65
+#define CLK_INFRA_66M_MSDC_0_HCK 66
+#define CLK_INFRA_133M_CPUM_BCK 67
+#define CLK_INFRA_BIST2FPC 68
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
+#define CLK_INFRA_133M_USB_HCK 71
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
+#define CLK_INFRA_66M_USB_HCK 73
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
+#define CLK_INFRA_USB_SYS 75
+#define CLK_INFRA_USB_SYS_CK_P1 76
+#define CLK_INFRA_USB_REF 77
+#define CLK_INFRA_USB_CK_P1 78
+#define CLK_INFRA_USB_FRMCNT 79
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
+#define CLK_INFRA_USB_PIPE 81
+#define CLK_INFRA_USB_PIPE_CK_P1 82
+#define CLK_INFRA_USB_UTMI 83
+#define CLK_INFRA_USB_UTMI_CK_P1 84
+#define CLK_INFRA_USB_XHCI 85
+#define CLK_INFRA_USB_XHCI_CK_P1 86
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
+#define CLK_INFRA_PCIE_PIPE_P0 91
+#define CLK_INFRA_PCIE_PIPE_P1 92
+#define CLK_INFRA_PCIE_PIPE_P2 93
+#define CLK_INFRA_PCIE_PIPE_P3 94
+#define CLK_INFRA_133M_PCIE_CK_P0 95
+#define CLK_INFRA_133M_PCIE_CK_P1 96
+#define CLK_INFRA_133M_PCIE_CK_P2 97
+#define CLK_INFRA_133M_PCIE_CK_P3 98
/* TOPCKGEN */
+/* mtk_fixed_clk */
+#define CLK_TOP_XTAL 0
/* mtk_fixed_factor */
-#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */
-#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
-#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
-#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
-#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */
-#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */
-#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */
-#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */
-#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */
-#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */
-#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */
-#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */
-#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */
-#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
-#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */
-#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */
-#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */
-#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */
-#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */
-#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */
-#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */
-#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */
-#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */
-#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */
-#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */
-#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */
-#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */
-#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */
-#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */
-#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */
-#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */
-#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
-#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
-#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
-#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
-#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */
-#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
-#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
-#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
-#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
-#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
-#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */
-#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
-#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */
-#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */
-#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */
-#define CK_TOP_SPI 46 /* Linux CLK ID (120) */
-#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */
-#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */
-#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */
-#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */
-#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */
-#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */
-#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */
-#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */
-#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */
-#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */
-#define CK_TOP_AUD 57 /* Linux CLK ID (131) */
-#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */
-#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */
-#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */
-#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */
-#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */
-#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */
-#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D3_D2 5
+#define CLK_TOP_MPLL_D4 6
+#define CLK_TOP_MPLL_D8 7
+#define CLK_TOP_MPLL_D8_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D3_D5 10
+#define CLK_TOP_MMPLL_D4 11
+#define CLK_TOP_MMPLL_D6_D2 12
+#define CLK_TOP_MMPLL_D8 13
+#define CLK_TOP_APLL2_D4 14
+#define CLK_TOP_NET1PLL_D4 15
+#define CLK_TOP_NET1PLL_D5 16
+#define CLK_TOP_NET1PLL_D5_D2 17
+#define CLK_TOP_NET1PLL_D5_D4 18
+#define CLK_TOP_NET1PLL_D8 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET1PLL_D8_D8 22
+#define CLK_TOP_NET1PLL_D8_D16 23
+#define CLK_TOP_NET2PLL_D2 24
+#define CLK_TOP_NET2PLL_D4 25
+#define CLK_TOP_NET2PLL_D4_D4 26
+#define CLK_TOP_NET2PLL_D4_D8 27
+#define CLK_TOP_NET2PLL_D6 28
+#define CLK_TOP_NET2PLL_D8 29
/* mtk_mux */
-#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
-#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
-#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */
-#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */
-#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */
-#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */
-#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */
-#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */
-#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */
-#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */
-#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */
-#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */
-#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */
-#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */
-#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */
-#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */
-#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */
-#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */
-#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */
-#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */
-#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */
-#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */
-#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */
-#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */
-#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */
-#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */
-#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */
-#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */
-#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */
-#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */
-#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */
-#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */
-#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */
-#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */
-#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */
-#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */
-#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */
-#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */
-#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */
-#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */
-#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */
-#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */
-#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */
-#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */
-#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */
-#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */
-#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */
-#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */
-#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */
-#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */
-#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */
-#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */
-#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */
-#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */
-#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */
-#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */
-#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */
-#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */
-#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */
-#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */
-#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
-#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
-#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
-#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */
-#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
-#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
-#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
-#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */
-#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */
-#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */
-#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
-#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
-#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
-#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
+#define CLK_TOP_NETSYS_SEL 30
+#define CLK_TOP_NETSYS_500M_SEL 31
+#define CLK_TOP_NETSYS_2X_SEL 32
+#define CLK_TOP_NETSYS_GSW_SEL 33
+#define CLK_TOP_ETH_GMII_SEL 34
+#define CLK_TOP_NETSYS_MCU_SEL 35
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
+#define CLK_TOP_EIP197_SEL 37
+#define CLK_TOP_AXI_INFRA_SEL 38
+#define CLK_TOP_UART_SEL 39
+#define CLK_TOP_EMMC_250M_SEL 40
+#define CLK_TOP_EMMC_400M_SEL 41
+#define CLK_TOP_SPI_SEL 42
+#define CLK_TOP_SPIM_MST_SEL 43
+#define CLK_TOP_NFI1X_SEL 44
+#define CLK_TOP_SPINFI_SEL 45
+#define CLK_TOP_PWM_SEL 46
+#define CLK_TOP_I2C_SEL 47
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
+#define CLK_TOP_PEXTP_TL_SEL 49
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
+#define CLK_TOP_USB_SYS_SEL 53
+#define CLK_TOP_USB_SYS_P1_SEL 54
+#define CLK_TOP_USB_XHCI_SEL 55
+#define CLK_TOP_USB_XHCI_P1_SEL 56
+#define CLK_TOP_USB_FRMCNT_SEL 57
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
+#define CLK_TOP_AUD_SEL 59
+#define CLK_TOP_A1SYS_SEL 60
+#define CLK_TOP_AUD_L_SEL 61
+#define CLK_TOP_A_TUNER_SEL 62
+#define CLK_TOP_SSPXTP_SEL 63
+#define CLK_TOP_USB_PHY_SEL 64
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
+#define CLK_TOP_SGM_0_SEL 67
+#define CLK_TOP_SGM_SBUS_0_SEL 68
+#define CLK_TOP_SGM_1_SEL 69
+#define CLK_TOP_SGM_SBUS_1_SEL 70
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
+#define CLK_TOP_SYSAXI_SEL 73
+#define CLK_TOP_SYSAPB_SEL 74
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
+#define CLK_TOP_ETH_SYS_200M_SEL 76
+#define CLK_TOP_ETH_SYS_SEL 77
+#define CLK_TOP_ETH_XGMII_SEL 78
+#define CLK_TOP_BUS_TOPS_SEL 79
+#define CLK_TOP_NPU_TOPS_SEL 80
+#define CLK_TOP_DRAMC_SEL 81
+#define CLK_TOP_DRAMC_MD32_SEL 82
+#define CLK_TOP_INFRA_F26M_SEL 83
+#define CLK_TOP_PEXTP_P0_SEL 84
+#define CLK_TOP_PEXTP_P1_SEL 85
+#define CLK_TOP_PEXTP_P2_SEL 86
+#define CLK_TOP_PEXTP_P3_SEL 87
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
+#define CLK_TOP_CKM_SEL 92
+#define CLK_TOP_DA_SEL 93
+#define CLK_TOP_PEXTP_SEL 94
+#define CLK_TOP_TOPS_P2_26M_SEL 95
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
+#define CLK_TOP_MACSEC_SEL 98
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
+#define CLK_TOP_NETSYS_WARP_SEL 101
+#define CLK_TOP_ETH_MII_SEL 102
+#define CLK_TOP_NPU_SEL 103
/* APMIXEDSYS */
/* mtk_pll_data */
-#define CK_APMIXED_NETSYSPLL 0
-#define CK_APMIXED_MPLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_APLL2 3
-#define CK_APMIXED_NET1PLL 4
-#define CK_APMIXED_NET2PLL 5
-#define CK_APMIXED_WEDMCUPLL 6
-#define CK_APMIXED_SGMPLL 7
-#define CK_APMIXED_ARM_B 8
-#define CK_APMIXED_CCIPLL2_B 9
-#define CK_APMIXED_USXGMIIPLL 10
-#define CK_APMIXED_MSDCPLL 11
+#define CLK_APMIXED_NETSYSPLL 0
+#define CLK_APMIXED_MPLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_APLL2 3
+#define CLK_APMIXED_NET1PLL 4
+#define CLK_APMIXED_NET2PLL 5
+#define CLK_APMIXED_WEDMCUPLL 6
+#define CLK_APMIXED_SGMPLL 7
+#define CLK_APMIXED_ARM_B 8
+#define CLK_APMIXED_CCIPLL2_B 9
+#define CLK_APMIXED_USXGMIIPLL 10
+#define CLK_APMIXED_MSDCPLL 11
/* ETHSYS ETH DMA */
/* mtk_gate */
-#define CK_ETHDMA_FE_EN 0
+#define CLK_ETHDMA_FE_EN 0
/* SGMIISYS_0 */
/* mtk_gate */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
/* SGMIISYS_1 */
/* mtk_gate */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
/* ETHWARP */
/* mtk_gate */
-#define CK_ETHWARP_WOCPU2_EN 0
-#define CK_ETHWARP_WOCPU1_EN 1
-#define CK_ETHWARP_WOCPU0_EN 2
+#define CLK_ETHWARP_WOCPU2_EN 0
+#define CLK_ETHWARP_WOCPU1_EN 1
+#define CLK_ETHWARP_WOCPU0_EN 2
#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h
new file mode 100644
index 0000000..cfbeca2
--- /dev/null
+++ b/include/dt-bindings/clock/sophgo,cv1800.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Ltd.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+
+#define CLK_MPLL 0
+#define CLK_TPLL 1
+#define CLK_FPLL 2
+#define CLK_MIPIMPLL 3
+#define CLK_A0PLL 4
+#define CLK_DISPPLL 5
+#define CLK_CAM0PLL 6
+#define CLK_CAM1PLL 7
+
+#define CLK_MIPIMPLL_D3 8
+#define CLK_CAM0PLL_D2 9
+#define CLK_CAM0PLL_D3 10
+
+#define CLK_TPU 11
+#define CLK_TPU_FAB 12
+#define CLK_AHB_ROM 13
+#define CLK_DDR_AXI_REG 14
+#define CLK_RTC_25M 15
+#define CLK_SRC_RTC_SYS_0 16
+#define CLK_TEMPSEN 17
+#define CLK_SARADC 18
+#define CLK_EFUSE 19
+#define CLK_APB_EFUSE 20
+#define CLK_DEBUG 21
+#define CLK_AP_DEBUG 22
+#define CLK_XTAL_MISC 23
+#define CLK_AXI4_EMMC 24
+#define CLK_EMMC 25
+#define CLK_EMMC_100K 26
+#define CLK_AXI4_SD0 27
+#define CLK_SD0 28
+#define CLK_SD0_100K 29
+#define CLK_AXI4_SD1 30
+#define CLK_SD1 31
+#define CLK_SD1_100K 32
+#define CLK_SPI_NAND 33
+#define CLK_ETH0_500M 34
+#define CLK_AXI4_ETH0 35
+#define CLK_ETH1_500M 36
+#define CLK_AXI4_ETH1 37
+#define CLK_APB_GPIO 38
+#define CLK_APB_GPIO_INTR 39
+#define CLK_GPIO_DB 40
+#define CLK_AHB_SF 41
+#define CLK_AHB_SF1 42
+#define CLK_A24M 43
+#define CLK_AUDSRC 44
+#define CLK_APB_AUDSRC 45
+#define CLK_SDMA_AXI 46
+#define CLK_SDMA_AUD0 47
+#define CLK_SDMA_AUD1 48
+#define CLK_SDMA_AUD2 49
+#define CLK_SDMA_AUD3 50
+#define CLK_I2C 51
+#define CLK_APB_I2C 52
+#define CLK_APB_I2C0 53
+#define CLK_APB_I2C1 54
+#define CLK_APB_I2C2 55
+#define CLK_APB_I2C3 56
+#define CLK_APB_I2C4 57
+#define CLK_APB_WDT 58
+#define CLK_PWM_SRC 59
+#define CLK_PWM 60
+#define CLK_SPI 61
+#define CLK_APB_SPI0 62
+#define CLK_APB_SPI1 63
+#define CLK_APB_SPI2 64
+#define CLK_APB_SPI3 65
+#define CLK_1M 66
+#define CLK_CAM0_200 67
+#define CLK_PM 68
+#define CLK_TIMER0 69
+#define CLK_TIMER1 70
+#define CLK_TIMER2 71
+#define CLK_TIMER3 72
+#define CLK_TIMER4 73
+#define CLK_TIMER5 74
+#define CLK_TIMER6 75
+#define CLK_TIMER7 76
+#define CLK_UART0 77
+#define CLK_APB_UART0 78
+#define CLK_UART1 79
+#define CLK_APB_UART1 80
+#define CLK_UART2 81
+#define CLK_APB_UART2 82
+#define CLK_UART3 83
+#define CLK_APB_UART3 84
+#define CLK_UART4 85
+#define CLK_APB_UART4 86
+#define CLK_APB_I2S0 87
+#define CLK_APB_I2S1 88
+#define CLK_APB_I2S2 89
+#define CLK_APB_I2S3 90
+#define CLK_AXI4_USB 91
+#define CLK_APB_USB 92
+#define CLK_USB_125M 93
+#define CLK_USB_33K 94
+#define CLK_USB_12M 95
+#define CLK_AXI4 96
+#define CLK_AXI6 97
+#define CLK_DSI_ESC 98
+#define CLK_AXI_VIP 99
+#define CLK_SRC_VIP_SYS_0 100
+#define CLK_SRC_VIP_SYS_1 101
+#define CLK_SRC_VIP_SYS_2 102
+#define CLK_SRC_VIP_SYS_3 103
+#define CLK_SRC_VIP_SYS_4 104
+#define CLK_CSI_BE_VIP 105
+#define CLK_CSI_MAC0_VIP 106
+#define CLK_CSI_MAC1_VIP 107
+#define CLK_CSI_MAC2_VIP 108
+#define CLK_CSI0_RX_VIP 109
+#define CLK_CSI1_RX_VIP 110
+#define CLK_ISP_TOP_VIP 111
+#define CLK_IMG_D_VIP 112
+#define CLK_IMG_V_VIP 113
+#define CLK_SC_TOP_VIP 114
+#define CLK_SC_D_VIP 115
+#define CLK_SC_V1_VIP 116
+#define CLK_SC_V2_VIP 117
+#define CLK_SC_V3_VIP 118
+#define CLK_DWA_VIP 119
+#define CLK_BT_VIP 120
+#define CLK_DISP_VIP 121
+#define CLK_DSI_MAC_VIP 122
+#define CLK_LVDS0_VIP 123
+#define CLK_LVDS1_VIP 124
+#define CLK_PAD_VI_VIP 125
+#define CLK_PAD_VI1_VIP 126
+#define CLK_PAD_VI2_VIP 127
+#define CLK_CFG_REG_VIP 128
+#define CLK_VIP_IP0 129
+#define CLK_VIP_IP1 130
+#define CLK_VIP_IP2 131
+#define CLK_VIP_IP3 132
+#define CLK_IVE_VIP 133
+#define CLK_RAW_VIP 134
+#define CLK_OSDC_VIP 135
+#define CLK_CAM0_VIP 136
+#define CLK_AXI_VIDEO_CODEC 137
+#define CLK_VC_SRC0 138
+#define CLK_VC_SRC1 139
+#define CLK_VC_SRC2 140
+#define CLK_H264C 141
+#define CLK_APB_H264C 142
+#define CLK_H265C 143
+#define CLK_APB_H265C 144
+#define CLK_JPEG 145
+#define CLK_APB_JPEG 146
+#define CLK_CAM0 147
+#define CLK_CAM1 148
+#define CLK_WGN 149
+#define CLK_WGN0 150
+#define CLK_WGN1 151
+#define CLK_WGN2 152
+#define CLK_KEYSCAN 153
+#define CLK_CFG_REG_VC 154
+#define CLK_C906_0 155
+#define CLK_C906_1 156
+#define CLK_A53 157
+#define CLK_CPU_AXI0 158
+#define CLK_CPU_GIC 159
+#define CLK_XTAL_AP 160
+
+// Only for CV181x
+#define CLK_DISP_SRC_VIP 161
+
+#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */
diff --git a/include/dt-bindings/pinctrl/sandbox-pinmux.h b/include/dt-bindings/pinctrl/sandbox-pinmux.h
index 891af07..21c5a17 100644
--- a/include/dt-bindings/pinctrl/sandbox-pinmux.h
+++ b/include/dt-bindings/pinctrl/sandbox-pinmux.h
@@ -13,6 +13,7 @@
#define SANDBOX_PINMUX_GPIO 4
#define SANDBOX_PINMUX_CS 5
#define SANDBOX_PINMUX_PWM 6
+#define SANDBOX_PINMUX_ONEWIRE 7
#define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin))
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 136a95b..6edb9e1 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -15,170 +15,205 @@
#define DWMCI_CTRL 0x000
#define DWMCI_PWREN 0x004
#define DWMCI_CLKDIV 0x008
-#define DWMCI_CLKSRC 0x00C
+#define DWMCI_CLKSRC 0x00c
#define DWMCI_CLKENA 0x010
#define DWMCI_TMOUT 0x014
#define DWMCI_CTYPE 0x018
-#define DWMCI_BLKSIZ 0x01C
+#define DWMCI_BLKSIZ 0x01c
#define DWMCI_BYTCNT 0x020
#define DWMCI_INTMASK 0x024
#define DWMCI_CMDARG 0x028
-#define DWMCI_CMD 0x02C
+#define DWMCI_CMD 0x02c
#define DWMCI_RESP0 0x030
#define DWMCI_RESP1 0x034
#define DWMCI_RESP2 0x038
-#define DWMCI_RESP3 0x03C
+#define DWMCI_RESP3 0x03c
#define DWMCI_MINTSTS 0x040
#define DWMCI_RINTSTS 0x044
#define DWMCI_STATUS 0x048
-#define DWMCI_FIFOTH 0x04C
+#define DWMCI_FIFOTH 0x04c
#define DWMCI_CDETECT 0x050
#define DWMCI_WRTPRT 0x054
#define DWMCI_GPIO 0x058
-#define DWMCI_TCMCNT 0x05C
+#define DWMCI_TCMCNT 0x05c
#define DWMCI_TBBCNT 0x060
#define DWMCI_DEBNCE 0x064
#define DWMCI_USRID 0x068
-#define DWMCI_VERID 0x06C
+#define DWMCI_VERID 0x06c
#define DWMCI_HCON 0x070
#define DWMCI_UHS_REG 0x074
#define DWMCI_BMOD 0x080
#define DWMCI_PLDMND 0x084
+#define DWMCI_DATA 0x200
+/* Registers to support IDMAC 32-bit address mode */
#define DWMCI_DBADDR 0x088
-#define DWMCI_IDSTS 0x08C
+#define DWMCI_IDSTS 0x08c
#define DWMCI_IDINTEN 0x090
#define DWMCI_DSCADDR 0x094
#define DWMCI_BUFADDR 0x098
-#define DWMCI_DATA 0x200
+/* Registers to support IDMAC 64-bit address mode */
+#define DWMCI_DBADDRL 0x088
+#define DWMCI_DBADDRU 0x08c
+#define DWMCI_IDSTS64 0x090
+#define DWMCI_IDINTEN64 0x094
+#define DWMCI_DSCADDRL 0x098
+#define DWMCI_DSCADDRU 0x09c
+#define DWMCI_BUFADDRL 0x0a0
+#define DWMCI_BUFADDRU 0x0a4
/* Interrupt Mask register */
#define DWMCI_INTMSK_ALL 0xffffffff
-#define DWMCI_INTMSK_RE (1 << 1)
-#define DWMCI_INTMSK_CDONE (1 << 2)
-#define DWMCI_INTMSK_DTO (1 << 3)
-#define DWMCI_INTMSK_TXDR (1 << 4)
-#define DWMCI_INTMSK_RXDR (1 << 5)
-#define DWMCI_INTMSK_RCRC (1 << 6)
-#define DWMCI_INTMSK_DCRC (1 << 7)
-#define DWMCI_INTMSK_RTO (1 << 8)
-#define DWMCI_INTMSK_DRTO (1 << 9)
-#define DWMCI_INTMSK_HTO (1 << 10)
-#define DWMCI_INTMSK_FRUN (1 << 11)
-#define DWMCI_INTMSK_HLE (1 << 12)
-#define DWMCI_INTMSK_SBE (1 << 13)
-#define DWMCI_INTMSK_ACD (1 << 14)
-#define DWMCI_INTMSK_EBE (1 << 15)
+#define DWMCI_INTMSK_RE BIT(1)
+#define DWMCI_INTMSK_CDONE BIT(2)
+#define DWMCI_INTMSK_DTO BIT(3)
+#define DWMCI_INTMSK_TXDR BIT(4)
+#define DWMCI_INTMSK_RXDR BIT(5)
+#define DWMCI_INTMSK_RCRC BIT(6)
+#define DWMCI_INTMSK_DCRC BIT(7)
+#define DWMCI_INTMSK_RTO BIT(8)
+#define DWMCI_INTMSK_DRTO BIT(9)
+#define DWMCI_INTMSK_HTO BIT(10)
+#define DWMCI_INTMSK_FRUN BIT(11)
+#define DWMCI_INTMSK_HLE BIT(12)
+#define DWMCI_INTMSK_SBE BIT(13)
+#define DWMCI_INTMSK_ACD BIT(14)
+#define DWMCI_INTMSK_EBE BIT(15)
-/* Raw interrupt Regsiter */
-#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
- DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
-#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+/* Raw interrupt register */
+#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \
+ DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \
+ DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+
/* CTRL register */
-#define DWMCI_CTRL_RESET (1 << 0)
-#define DWMCI_CTRL_FIFO_RESET (1 << 1)
-#define DWMCI_CTRL_DMA_RESET (1 << 2)
-#define DWMCI_DMA_EN (1 << 5)
-#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
-#define DWMCI_IDMAC_EN (1 << 25)
+#define DWMCI_CTRL_RESET BIT(0)
+#define DWMCI_CTRL_FIFO_RESET BIT(1)
+#define DWMCI_CTRL_DMA_RESET BIT(2)
+#define DWMCI_DMA_EN BIT(5)
+#define DWMCI_CTRL_SEND_AS_CCSD BIT(10)
+#define DWMCI_IDMAC_EN BIT(25)
#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
DWMCI_CTRL_DMA_RESET)
/* CMD register */
-#define DWMCI_CMD_RESP_EXP (1 << 6)
-#define DWMCI_CMD_RESP_LENGTH (1 << 7)
-#define DWMCI_CMD_CHECK_CRC (1 << 8)
-#define DWMCI_CMD_DATA_EXP (1 << 9)
-#define DWMCI_CMD_RW (1 << 10)
-#define DWMCI_CMD_SEND_STOP (1 << 12)
-#define DWMCI_CMD_ABORT_STOP (1 << 14)
-#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
-#define DWMCI_CMD_UPD_CLK (1 << 21)
-#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
-#define DWMCI_CMD_START (1 << 31)
+#define DWMCI_CMD_RESP_EXP BIT(6)
+#define DWMCI_CMD_RESP_LENGTH BIT(7)
+#define DWMCI_CMD_CHECK_CRC BIT(8)
+#define DWMCI_CMD_DATA_EXP BIT(9)
+#define DWMCI_CMD_RW BIT(10)
+#define DWMCI_CMD_SEND_STOP BIT(12)
+#define DWMCI_CMD_ABORT_STOP BIT(14)
+#define DWMCI_CMD_PRV_DAT_WAIT BIT(13)
+#define DWMCI_CMD_UPD_CLK BIT(21)
+#define DWMCI_CMD_USE_HOLD_REG BIT(29)
+#define DWMCI_CMD_START BIT(31)
/* CLKENA register */
-#define DWMCI_CLKEN_ENABLE (1 << 0)
-#define DWMCI_CLKEN_LOW_PWR (1 << 16)
+#define DWMCI_CLKEN_ENABLE BIT(0)
+#define DWMCI_CLKEN_LOW_PWR BIT(16)
-/* Card-type registe */
+/* Card type register */
#define DWMCI_CTYPE_1BIT 0
-#define DWMCI_CTYPE_4BIT (1 << 0)
-#define DWMCI_CTYPE_8BIT (1 << 16)
+#define DWMCI_CTYPE_4BIT BIT(0)
+#define DWMCI_CTYPE_8BIT BIT(16)
-/* Status Register */
-#define DWMCI_FIFO_EMPTY (1 << 2)
-#define DWMCI_FIFO_FULL (1 << 3)
-#define DWMCI_BUSY (1 << 9)
+/* Status register */
+#define DWMCI_FIFO_EMPTY BIT(2)
+#define DWMCI_FIFO_FULL BIT(3)
+#define DWMCI_BUSY BIT(9)
#define DWMCI_FIFO_MASK 0x1fff
#define DWMCI_FIFO_SHIFT 17
-/* FIFOTH Register */
+/* FIFOTH register */
#define MSIZE(x) ((x) << 28)
#define RX_WMARK(x) ((x) << 16)
#define TX_WMARK(x) (x)
#define RX_WMARK_SHIFT 16
#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
-#define DWMCI_IDMAC_OWN (1 << 31)
-#define DWMCI_IDMAC_CH (1 << 4)
-#define DWMCI_IDMAC_FS (1 << 3)
-#define DWMCI_IDMAC_LD (1 << 2)
+#define DWMCI_IDMAC_OWN BIT(31)
+#define DWMCI_IDMAC_CH BIT(4)
+#define DWMCI_IDMAC_FS BIT(3)
+#define DWMCI_IDMAC_LD BIT(2)
-/* Bus Mode Register */
-#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
-#define DWMCI_BMOD_IDMAC_FB (1 << 1)
-#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* Bus Mode register */
+#define DWMCI_BMOD_IDMAC_RESET BIT(0)
+#define DWMCI_BMOD_IDMAC_FB BIT(1)
+#define DWMCI_BMOD_IDMAC_EN BIT(7)
/* UHS register */
-#define DWMCI_DDR_MODE (1 << 16)
+#define DWMCI_DDR_MODE BIT(16)
/* Internal IDMAC interrupt defines */
-#define DWMCI_IDINTEN_RI BIT(1)
-#define DWMCI_IDINTEN_TI BIT(0)
+#define DWMCI_IDINTEN_RI BIT(1)
+#define DWMCI_IDINTEN_TI BIT(0)
+#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI)
-#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \
- DWMCI_IDINTEN_RI)
-
-/* quirks */
-#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
+/**
+ * struct dwmci_idmac_regs - Offsets of IDMAC registers
+ *
+ * @dbaddrl: Descriptor base address, lower 32 bits
+ * @dbaddru: Descriptor base address, upper 32 bits
+ * @idsts: Internal DMA status
+ * @idinten: Internal DMA interrupt enable
+ * @dscaddrl: IDMAC descriptor address, lower 32 bits
+ * @dscaddru: IDMAC descriptor address, upper 32 bits
+ * @bufaddrl: Current data buffer address, lower 32 bits
+ * @bufaddru: Current data buffer address, upper 32 bits
+ */
+struct dwmci_idmac_regs {
+ u32 dbaddrl;
+ u32 dbaddru;
+ u32 idsts;
+ u32 idinten;
+ u32 dscaddrl;
+ u32 dscaddru;
+ u32 bufaddrl;
+ u32 bufaddru;
+};
/**
* struct dwmci_host - Information about a designware MMC host
*
* @name: Device name
* @ioaddr: Base I/O address of controller
- * @quirks: Quick flags - see DWMCI_QUIRK_...
* @caps: Capabilities - see MMC_MODE_...
+ * @clock: Current clock frequency (after internal divider), Hz
* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
- * @div: Arbitrary clock divider value for use by controller
* @dev_index: Arbitrary device index for use by controller
* @dev_id: Arbitrary device ID for use by controller
* @buswidth: Bus width in bits (8 or 4)
- * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
+ * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection)
* @mmc: Pointer to generic MMC structure for this device
* @priv: Private pointer for use by controller
+ * @clksel: (Optional) Platform function to run when speed/width is changed
+ * @board_init: (Optional) Platform function to run on init
+ * @cfg: Internal MMC configuration, for !CONFIG_BLK cases
+ * @fifo_mode: Use FIFO mode (not DMA) to read and write data
+ * @dma_64bit_address: Whether DMA supports 64-bit address mode or not
+ * @regs: Registers that can vary for different DW MMC block versions
*/
struct dwmci_host {
const char *name;
void *ioaddr;
- unsigned int quirks;
unsigned int caps;
- unsigned int version;
unsigned int clock;
unsigned int bus_hz;
- unsigned int div;
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
+ u32 fifo_depth;
struct mmc *mmc;
void *priv;
int (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
-
/**
- * Get / set a particular MMC clock frequency
+ * @get_mmc_clk: (Optional) Platform function to get/set a particular
+ * MMC clock frequency
+ *
+ * @host: DWMMC host
+ * @freq: Frequency the host is trying to achieve
*
* This is used to request the current clock frequency of the clock
* that drives the DWMMC peripheral. The caller will then use this
@@ -186,26 +221,18 @@
* required MMC bus clock frequency. If you want to handle the
* clock external to DWMMC, use @freq to select the frequency and
* return that value too. Then DWMMC will put itself in bypass mode.
- *
- * @host: DWMMC host
- * @freq: Frequency the host is trying to achieve
*/
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
+
#ifndef CONFIG_BLK
struct mmc_config cfg;
#endif
- /* use fifo mode to read and write data */
bool fifo_mode;
+ bool dma_64bit_address;
+ const struct dwmci_idmac_regs *regs;
};
-struct dwmci_idmac {
- u32 flags;
- u32 cnt;
- u32 addr;
- u32 next_addr;
-} __aligned(ARCH_DMA_MINALIGN);
-
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
writel(val, host->ioaddr + reg);
@@ -220,6 +247,7 @@
{
writeb(val, host->ioaddr + reg);
}
+
static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
{
return readl(host->ioaddr + reg);
@@ -236,8 +264,13 @@
}
#ifdef CONFIG_BLK
+
/**
* dwmci_setup_cfg() - Set up the configuration for DWMMC
+ * @cfg: Configuration structure to fill in (generally &plat->mmc)
+ * @host: DWMMC host
+ * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
+ * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
*
* This is used to set up a DWMMC device when you are using CONFIG_BLK.
*
@@ -262,44 +295,41 @@
* struct rockchip_mmc_plat *plat = dev_get_plat(dev);
*
* See rockchip_dw_mmc.c for an example.
- *
- * @cfg: Configuration structure to fill in (generally &plat->mmc)
- * @host: DWMMC host
- * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
- * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
*/
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
- u32 max_clk, u32 min_clk);
+ u32 max_clk, u32 min_clk);
/**
* dwmci_bind() - Set up a new MMC block device
+ * @dev: Device to set up
+ * @mmc: Pointer to mmc structure (normally &plat->mmc)
+ * @cfg: Empty configuration structure (generally &plat->cfg). This is
+ * normally all zeroes at this point. The only purpose of passing
+ * this in is to set mmc->cfg to it.
*
* This is used to set up a DWMMC block device when you are using CONFIG_BLK.
* It should be called from your driver's bind() method.
*
* See rockchip_dw_mmc.c for an example.
*
- * @dev: Device to set up
- * @mmc: Pointer to mmc structure (normally &plat->mmc)
- * @cfg: Empty configuration structure (generally &plat->cfg). This is
- * normally all zeroes at this point. The only purpose of passing
- * this in is to set mmc->cfg to it.
* Return: 0 if OK, -ve if the block device could not be created
*/
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
#else
+
/**
* add_dwmci() - Add a new DWMMC interface
+ * @host: DWMMC host structure
+ * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
+ * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
*
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
- * @host: DWMMC host structure
- * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
- * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
* Return: 0 if OK, -ve on error
*/
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+
#endif /* !CONFIG_BLK */
#ifdef CONFIG_DM_MMC
diff --git a/include/efi.h b/include/efi.h
index d5af213..84640cf 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -74,7 +74,7 @@
* struct { u32 a; u16; b; u16 c; u8 d[8]; }; which is 4-byte
* aligned.
*/
-typedef struct {
+typedef struct efi_guid {
u8 b[16];
} efi_guid_t __attribute__((aligned(4)));
diff --git a/include/efi_variable.h b/include/efi_variable.h
index 223bb9a..4065cf4 100644
--- a/include/efi_variable.h
+++ b/include/efi_variable.h
@@ -38,7 +38,7 @@
void *data, u64 *timep);
/**
- * efi_set_variable() - set value of a UEFI variable
+ * efi_set_variable_int() - set value of a UEFI variable
*
* @variable_name: name of the variable
* @vendor: vendor GUID
diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env
index 3d3595c..ad8d3a8 100644
--- a/include/env/phytec/k3_mmc.env
+++ b/include/env/phytec/k3_mmc.env
@@ -7,15 +7,17 @@
/* Logic for TI K3 based SoCs to boot from a MMC device. */
#include <env/phytec/overlays.env>
+#include <env/phytec/rauc.env>
mmcargs=setenv bootargs console=${console} earlycon=${earlycon}
- root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw
-loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image
-loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
-mmcboot=run mmcargs;
+ root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
+mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image
+mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+mmcboot=if test ${doraucboot} = 1; then run raucinit; fi;
+ run mmcargs;
mmc dev ${mmcdev};
mmc rescan;
- run loadimage;
- run loadfdt;
+ run mmcloadimage;
+ run mmcloadfdt;
run mmc_apply_overlays;
- booti ${loadaddr} - ${fdt_addr_r}
+ booti ${kernel_addr_r} - ${fdt_addr_r}
diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env
new file mode 100644
index 0000000..377e406
--- /dev/null
+++ b/include/env/phytec/k3_net.env
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ */
+
+/* Logic for TI K3 based SoCs to boot via network. */
+
+#include <env/phytec/overlays.env>
+
+netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw
+ nfsroot=${serverip}:${nfsroot},vers=4,tcp
+netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image
+netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile}
+netboot=run netargs;
+ setenv autoload no;
+ dhcp;
+ run netloadimage;
+ run netloadfdt;
+ run net_apply_overlays;
+ run net_apply_extensions;
+ booti ${kernel_addr_r} - ${fdt_addr_r}
diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env
new file mode 100644
index 0000000..97d3a15
--- /dev/null
+++ b/include/env/phytec/k3_spi.env
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ */
+
+/* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */
+
+spiargs=setenv bootargs console=${console} earlycon=${earlycon}
+spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern}
+spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt}
+spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs}
+spiboot=run spiargs;
+ sf probe;
+ run spiloadimage;
+ run spiloadfdt;
+ run spiloadramdisk;
+ booti ${kernel_addr_r} ${ramdisk_addr_r}:0x${size_fs} ${fdt_addr_r}
diff --git a/include/env_default.h b/include/env_default.h
index 076ffdd..aa3dd40 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -82,9 +82,6 @@
#ifdef CONFIG_SYS_LOAD_ADDR
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0"
#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
-#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
#ifdef CONFIG_SYS_CPU
diff --git a/include/env_internal.h b/include/env_internal.h
index 0a267e3..c1c0727 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -100,6 +100,7 @@
#include <env_flags.h>
#include <search.h>
+/* this is stored as bits in gd->env_has_init so is limited to 16 entries */
enum env_location {
ENVL_UNKNOWN,
ENVL_EEPROM,
diff --git a/include/event.h b/include/event.h
index fb353ad..75141a1 100644
--- a/include/event.h
+++ b/include/event.h
@@ -385,7 +385,7 @@
int event_uninit(void);
/**
- * event_uninit() - Set up dynamic events
+ * event_init() - Set up dynamic events
*
* Init a list of dynamic event handlers, so that these can be added as
* needed
diff --git a/include/expo.h b/include/expo.h
index 264745f..c235fa2 100644
--- a/include/expo.h
+++ b/include/expo.h
@@ -42,7 +42,7 @@
*
* @type: Action type (EXPOACT_NONE if there is no action)
* @select: Used for EXPOACT_POINT_ITEM and EXPOACT_SELECT
- * @id: ID number of the object affected.
+ * @select.id: ID number of the object affected.
*/
struct expo_action {
enum expoact_type type;
diff --git a/include/ext4fs.h b/include/ext4fs.h
index d96edfd..41f9eb8 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -34,12 +34,63 @@
#define EXT4_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/
#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */
#define EXT4_EXT_MAGIC 0xf30a
-#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
+
+#define EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001
+#define EXT4_FEATURE_RO_COMPAT_LARGE_FILE 0x0002
+#define EXT4_FEATURE_RO_COMPAT_BTREE_DIR 0x0004
+#define EXT4_FEATURE_RO_COMPAT_HUGE_FILE 0x0008
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
+#define EXT4_FEATURE_RO_COMPAT_DIR_NLINK 0x0020
+#define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE 0x0040
+#define EXT4_FEATURE_RO_COMPAT_QUOTA 0x0100
+#define EXT4_FEATURE_RO_COMPAT_BIGALLOC 0x0200
#define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400
+
+#define EXT4_FEATURE_INCOMPAT_FILETYPE 0x0002
+#define EXT4_FEATURE_INCOMPAT_RECOVER 0x0004
#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040
#define EXT4_FEATURE_INCOMPAT_64BIT 0x0080
+#define EXT4_FEATURE_INCOMPAT_MMP 0x0100
+#define EXT4_FEATURE_INCOMPAT_FLEX_BG 0x0200
+#define EXT4_FEATURE_INCOMPAT_CSUM_SEED 0x2000
+#define EXT4_FEATURE_INCOMPAT_ENCRYPT 0x10000
+
#define EXT4_INDIRECT_BLOCKS 12
+/*
+ * Incompat features supported by this implementation.
+ */
+#define EXT4_FEATURE_INCOMPAT_SUPP (EXT4_FEATURE_INCOMPAT_FILETYPE | \
+ EXT4_FEATURE_INCOMPAT_RECOVER | \
+ EXT4_FEATURE_INCOMPAT_EXTENTS | \
+ EXT4_FEATURE_INCOMPAT_64BIT | \
+ EXT4_FEATURE_INCOMPAT_FLEX_BG)
+
+/*
+ * Incompat features supported by this implementation only in a lazy
+ * way, good enough for reading files.
+ *
+ * - Multi mount protection (mmp) is not supported, but for read-only
+ * we get away with it.
+ * - Same for metadata_csum_seed and metadata_csum.
+ * - The implementation has also no clue about fscrypt, but it can read
+ * unencrypted files. Reading encrypted files will read garbage.
+ */
+#define EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO (EXT4_FEATURE_INCOMPAT_MMP | \
+ EXT4_FEATURE_INCOMPAT_CSUM_SEED | \
+ EXT4_FEATURE_INCOMPAT_ENCRYPT)
+
+/*
+ * Read-only compat features we support.
+ * If unknown ro compat features are detected, writing to the fs is denied.
+ */
+#define EXT4_FEATURE_RO_COMPAT_SUPP (EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER | \
+ EXT4_FEATURE_RO_COMPAT_LARGE_FILE | \
+ EXT4_FEATURE_RO_COMPAT_HUGE_FILE | \
+ EXT4_FEATURE_RO_COMPAT_GDT_CSUM | \
+ EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \
+ EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE)
+
#define EXT4_BG_INODE_UNINIT 0x0001
#define EXT4_BG_BLOCK_UNINIT 0x0002
#define EXT4_BG_INODE_ZEROED 0x0004
diff --git a/include/flash.h b/include/flash.h
index 60babe8..32bc65e 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -127,16 +127,16 @@
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
-#define ERR_OK 0
-#define ERR_TIMEOUT 1
-#define ERR_NOT_ERASED 2
-#define ERR_PROTECTED 4
-#define ERR_INVAL 8
-#define ERR_ALIGN 16
-#define ERR_UNKNOWN_FLASH_VENDOR 32
-#define ERR_UNKNOWN_FLASH_TYPE 64
-#define ERR_PROG_ERROR 128
-#define ERR_ABORTED 256
+#define FL_ERR_OK 0
+#define FL_ERR_TIMEOUT 1
+#define FL_ERR_NOT_ERASED 2
+#define FL_ERR_PROTECTED 4
+#define FL_ERR_INVAL 8
+#define FL_ERR_ALIGN 16
+#define FL_ERR_UNKNOWN_FLASH_VENDOR 32
+#define FL_ERR_UNKNOWN_FLASH_TYPE 64
+#define FL_ERR_PROG_ERROR 128
+#define FL_ERR_ABORTED 256
/*-----------------------------------------------------------------------
* Protection Flags for flash_protect():
diff --git a/include/fwu.h b/include/fwu.h
index 77ec65e..6441de3 100644
--- a/include/fwu.h
+++ b/include/fwu.h
@@ -10,7 +10,7 @@
#include <efi.h>
#include <fwu_mdata.h>
#include <mtd.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/types.h>
@@ -417,4 +417,15 @@
*/
int fwu_init(void);
+/**
+ * fwu_bank_accepted() - Has the bank been accepted
+ * @data: Version agnostic FWU metadata information
+ * @bank: Update bank to check
+ *
+ * Check in the given bank if all the images have been accepted.
+ *
+ * Return: true if all images accepted, false otherwise
+ */
+bool fwu_bank_accepted(struct fwu_data *data, uint32_t bank);
+
#endif /* _FWU_H_ */
diff --git a/include/generic-phy.h b/include/generic-phy.h
index eaab749..ba3321f 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -415,10 +415,13 @@
* @dev: The consumer device.
* @phy: A pointer to the PHY port
* @index: The index in the list of available PHYs
+ * @mode: PHY mode
+ * @submode: PHY submode
*
* Return: 0 if OK, or negative error code.
*/
-int generic_setup_phy(struct udevice *dev, struct phy *phy, int index);
+int generic_setup_phy(struct udevice *dev, struct phy *phy, int index,
+ enum phy_mode mode, int submode);
/**
* generic_shutdown_phy() - Power off and de-initialize phy.
@@ -509,7 +512,8 @@
return 0;
}
-static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index)
+static inline int generic_setup_phy(struct udevice *dev, struct phy *phy, int index,
+ enum phy_mode mode, int submode)
{
return 0;
}
diff --git a/include/getopt.h b/include/getopt.h
index 8645082..0cf7ee8 100644
--- a/include/getopt.h
+++ b/include/getopt.h
@@ -20,11 +20,9 @@
* parsed all of @argv, then @index will equal @argc.
*/
int index;
- /* private: */
/** @arg_index: Index within the current argument */
int arg_index;
union {
- /* public: */
/**
* @opt: Option being parsed when an error occurs. @opt is only
* valid when getopt() returns ``?`` or ``:``.
@@ -35,7 +33,6 @@
* is only valid when getopt() returns an option character.
*/
char *arg;
- /* private: */
};
};
diff --git a/include/handoff.h b/include/handoff.h
index c0ae7b1..0072ea8 100644
--- a/include/handoff.h
+++ b/include/handoff.h
@@ -32,6 +32,13 @@
void handoff_load_dram_banks(struct spl_handoff *ho);
/**
+ * handoff_get() - Get the SPL handoff information
+ *
+ * Return: Pointer to SPL handoff if received, else NULL
+ */
+struct spl_handoff *handoff_get(void);
+
+/**
* handoff_arch_save() - Save arch-specific info into the handoff area
*
* This is defined to an empty function by default, but arch-specific code can
diff --git a/include/i2c.h b/include/i2c.h
index 4e59009..91917f5 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -645,20 +645,8 @@
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if !defined(CFG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
-#define CFG_SYS_I2C_DIRECT_BUS 1
-#define CFG_SYS_I2C_MAX_HOPS 0
#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
-#else
-/* we use i2c muxes */
-#undef CFG_SYS_I2C_DIRECT_BUS
-#endif
-
-/* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CFG_SYS_RTC_BUS_NUM)
-#define CFG_SYS_RTC_BUS_NUM 0
-#endif
struct i2c_adapter {
void (*init)(struct i2c_adapter *adap, int speed,
@@ -703,48 +691,13 @@
struct i2c_adapter *i2c_get_adapter(int index);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-struct i2c_mux {
- int id;
- char name[16];
-};
-
-struct i2c_next_hop {
- struct i2c_mux mux;
- uint8_t chip;
- uint8_t channel;
-};
-
-struct i2c_bus_hose {
- int adapter;
- struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS];
-};
-#define I2C_NULL_HOP {{-1, ""}, 0, 0}
-extern struct i2c_bus_hose i2c_bus[];
-
-#define I2C_ADAPTER(bus) i2c_bus[bus].adapter
-#else
#define I2C_ADAPTER(bus) bus
-#endif
#define I2C_BUS gd->cur_i2c_bus
#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-#define I2C_MUX_PCA9540_ID 1
-#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
-#define I2C_MUX_PCA9542_ID 2
-#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
-#define I2C_MUX_PCA9544_ID 3
-#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
-#define I2C_MUX_PCA9547_ID 4
-#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
-#define I2C_MUX_PCA9548_ID 5
-#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"}
-#endif
-
#ifndef I2C_SOFT_DECLARATIONS
# if (defined(CONFIG_AT91RM9200) || \
defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
@@ -938,66 +891,6 @@
unsigned int i2c_get_bus_speed(void);
#endif /* CONFIG_SYS_I2C_LEGACY */
-/*
- * only for backwardcompatibility, should go away if we switched
- * completely to new multibus support.
- */
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS)
-# if !defined(CFG_SYS_MAX_I2C_BUS)
-# define CFG_SYS_MAX_I2C_BUS 2
-# endif
-# define I2C_MULTI_BUS 1
-#else
-# define CFG_SYS_MAX_I2C_BUS 1
-# define I2C_MULTI_BUS 0
-#endif
-
-/* NOTE: These two functions MUST be always_inline to avoid code growth! */
-static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
-static inline unsigned int I2C_GET_BUS(void)
-{
- return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
-}
-
-static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
-static inline void I2C_SET_BUS(unsigned int bus)
-{
- if (I2C_MULTI_BUS)
- i2c_set_bus_num(bus);
-}
-
-/* Multi I2C definitions */
-enum {
- I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
- I2C_8, I2C_9, I2C_10,
-};
-
-/**
- * Get FDT values for i2c bus.
- *
- * @param blob Device tree blbo
- * Return: the number of I2C bus
- */
-void board_i2c_init(const void *blob);
-
-/**
- * Find the I2C bus number by given a FDT I2C node.
- *
- * @param blob Device tree blbo
- * @param node FDT I2C node to find
- * Return: the number of I2C bus (zero based), or -1 on error
- */
-int i2c_get_bus_num_fdt(int node);
-
-/**
- * Reset the I2C bus represented by the given a FDT I2C node.
- *
- * @param blob Device tree blbo
- * @param node FDT I2C node to find
- * Return: 0 if port was reset, -1 if not found
- */
-int i2c_reset_port_fdt(const void *blob, int node);
-
#endif /* !CONFIG_DM_I2C */
#endif /* _I2C_H_ */
diff --git a/include/image.h b/include/image.h
index 2ab1707..c52fced 100644
--- a/include/image.h
+++ b/include/image.h
@@ -20,7 +20,6 @@
#include <stdbool.h>
/* Define this to avoid #ifdefs later on */
-struct lmb;
struct fdt_region;
#ifdef USE_HOSTCC
@@ -412,18 +411,8 @@
#define BOOTM_STATE_PRE_LOAD 0x00000800
#define BOOTM_STATE_MEASURE 0x00001000
int state;
-
-#if defined(CONFIG_LMB) && !defined(USE_HOSTCC)
- struct lmb lmb; /* for memory mgmt */
-#endif
};
-#ifdef CONFIG_LMB
-#define images_lmb(_images) (&(_images)->lmb)
-#else
-#define images_lmb(_images) NULL
-#endif
-
extern struct bootm_headers images;
/*
@@ -835,13 +824,13 @@
struct bootm_headers *images, char **of_flat_tree,
ulong *of_size);
-void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
-int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
+void boot_fdt_add_mem_rsv_regions(void *fdt_blob);
+int boot_relocate_fdt(char **of_flat_tree, ulong *of_size);
-int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
- ulong *initrd_start, ulong *initrd_end);
-int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
-int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd);
+int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start,
+ ulong *initrd_end);
+int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end);
+int boot_get_kbd(struct bd_info **kbd);
/*******************************************************************/
/* Legacy format specific code (prefixed with image_) */
@@ -1029,11 +1018,10 @@
*
* @images: Images information
* @blob: FDT to update
- * @lmb: Points to logical memory block structure
+ * @lmb: Flag indicating use of lmb for reserving FDT memory region
* Return: 0 if ok, <0 on failure
*/
-int image_setup_libfdt(struct bootm_headers *images, void *blob,
- struct lmb *lmb);
+int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb);
/**
* Set up the FDT to use for booting a kernel
diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index 1a30601..8b6ce9c 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -71,6 +71,13 @@
#endif
/*
+ * At least gcc 5.1 or clang 8 are needed.
+ */
+#ifndef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
+#error Unsupported compiler
+#endif
+
+/*
* Some architectures need to provide custom definitions of macros provided
* by linux/compiler-*.h, and can do so using asm/compiler.h. We include that
* conditionally rather than using an asm-generic wrapper in order to avoid
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 537c624..2d85b39 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -247,6 +247,11 @@
* kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
*/
#define NAND_USE_BOUNCE_BUFFER 0x00100000
+/*
+ * Whether the NAND chip is a boot medium. Drivers might use this information
+ * to select ECC algorithms supported by the boot ROM or similar restrictions.
+ */
+#define NAND_IS_BOOT_MEDIUM 0x00400000
/*
* Do not try to tweak the timings at runtime. This is needed when the
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
index c1c8107..37c4f21 100644
--- a/include/linux/usb/atmel_usba_udc.h
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -20,6 +20,8 @@
struct usba_ep_data *ep;
};
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
extern int usba_udc_probe(struct usba_platform_data *pdata);
+#endif
#endif /* __LINUX_USB_USBA_H */
diff --git a/include/lmb.h b/include/lmb.h
index 231b68b..aee2f9f 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -3,8 +3,10 @@
#define _LINUX_LMB_H
#ifdef __KERNEL__
+#include <alist.h>
#include <asm/types.h>
#include <asm/u-boot.h>
+#include <linux/bitops.h>
/*
* Logical memory blocks.
@@ -18,137 +20,101 @@
* @LMB_NOMAP: don't add to mmu configuration
*/
enum lmb_flags {
- LMB_NONE = 0x0,
- LMB_NOMAP = 0x4,
+ LMB_NONE = 0,
+ LMB_NOMAP = BIT(1),
+ LMB_NOOVERWRITE = BIT(2),
};
/**
- * struct lmb_property - Description of one region.
+ * struct lmb_region - Description of one region.
*
* @base: Base address of the region.
* @size: Size of the region
* @flags: memory region attributes
*/
-struct lmb_property {
+struct lmb_region {
phys_addr_t base;
phys_size_t size;
enum lmb_flags flags;
};
-/*
- * For regions size management, see LMB configuration in KConfig
- * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean)
- *
- * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode)
- * => CONFIG_LMB_MAX_REGIONS is used to configure the region size,
- * directly in the array lmb_region.region[], with the same
- * configuration for memory and reserved regions.
+/**
+ * struct lmb - The LMB structure
*
- * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each
- * region is configurated *independently* with
- * => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions
- * => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions
- * lmb_region.region is only a pointer to the correct buffer,
- * initialized in lmb_init(). This configuration is useful to manage
- * more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS.
+ * @free_mem: List of free memory regions
+ * @used_mem: List of used/reserved memory regions
*/
+struct lmb {
+ struct alist free_mem;
+ struct alist used_mem;
+};
/**
- * struct lmb_region - Description of a set of region.
+ * lmb_init() - Initialise the LMB module
+ *
+ * Initialise the LMB lists needed for keeping the memory map. There
+ * are two lists, in form of alloced list data structure. One for the
+ * available memory, and one for the used memory. Initialise the two
+ * lists as part of board init. Add memory to the available memory
+ * list and reserve common areas by adding them to the used memory
+ * list.
*
- * @cnt: Number of regions.
- * @max: Size of the region array, max value of cnt.
- * @region: Array of the region properties
+ * Return: 0 on success, -ve on error
*/
-struct lmb_region {
- unsigned long cnt;
- unsigned long max;
-#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
- struct lmb_property region[CONFIG_LMB_MAX_REGIONS];
-#else
- struct lmb_property *region;
-#endif
-};
+int lmb_init(void);
/**
- * struct lmb - Logical memory block handle.
+ * lmb_add_memory() - Add memory range for LMB allocations
*
- * Clients provide storage for Logical memory block (lmb) handles.
- * The content of the structure is managed by the lmb library.
- * A lmb struct is initialized by lmb_init() functions.
- * The lmb struct is passed to all other lmb APIs.
+ * Add the entire available memory range to the pool of memory that
+ * can be used by the LMB module for allocations.
*
- * @memory: Description of memory regions.
- * @reserved: Description of reserved regions.
- * @memory_regions: Array of the memory regions (statically allocated)
- * @reserved_regions: Array of the reserved regions (statically allocated)
+ * Return: None
*/
-struct lmb {
- struct lmb_region memory;
- struct lmb_region reserved;
-#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
- struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
- struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
-#endif
-};
+void lmb_add_memory(void);
-void lmb_init(struct lmb *lmb);
-void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob);
-void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, void *fdt_blob);
-long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
-long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+long lmb_add(phys_addr_t base, phys_size_t size);
+long lmb_reserve(phys_addr_t base, phys_size_t size);
/**
* lmb_reserve_flags - Reserve one region with a specific flags bitfield.
*
- * @lmb: the logical memory block struct
* @base: base address of the memory region
* @size: size of the memory region
* @flags: flags for the memory region
* Return: 0 if OK, > 0 for coalesced region or a negative error code.
*/
-long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, enum lmb_flags flags);
-phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
-phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
- phys_addr_t max_addr);
-phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
- phys_addr_t max_addr);
-phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size);
-phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
+long lmb_reserve_flags(phys_addr_t base, phys_size_t size,
+ enum lmb_flags flags);
+phys_addr_t lmb_alloc(phys_size_t size, ulong align);
+phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr);
+phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size);
+phys_size_t lmb_get_free_size(phys_addr_t addr);
/**
- * lmb_is_reserved() - test if address is in reserved region
- *
- * The function checks if a reserved region comprising @addr exists.
- *
- * @lmb: the logical memory block struct
- * @addr: address to be tested
- * Return: 1 if reservation exists, 0 otherwise
- */
-int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
-
-/**
* lmb_is_reserved_flags() - test if address is in reserved region with flag bits set
*
* The function checks if a reserved region comprising @addr exists which has
* all flag bits set which are set in @flags.
*
- * @lmb: the logical memory block struct
* @addr: address to be tested
* @flags: bitmap with bits to be tested
* Return: 1 if matching reservation exists, 0 otherwise
*/
-int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
+int lmb_is_reserved_flags(phys_addr_t addr, int flags);
-long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+long lmb_free(phys_addr_t base, phys_size_t size);
-void lmb_dump_all(struct lmb *lmb);
-void lmb_dump_all_force(struct lmb *lmb);
+void lmb_dump_all(void);
+void lmb_dump_all_force(void);
+
+struct lmb *lmb_get(void);
+int lmb_push(struct lmb *store);
+void lmb_pop(struct lmb *store);
-void board_lmb_reserve(struct lmb *lmb);
-void arch_lmb_reserve(struct lmb *lmb);
-void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align);
+static inline int lmb_read_check(phys_addr_t addr, phys_size_t len)
+{
+ return lmb_alloc_addr(addr, len) == addr ? 0 : -1;
+}
#endif /* __KERNEL__ */
diff --git a/include/log.h b/include/log.h
index fc0d598..7c25bf0 100644
--- a/include/log.h
+++ b/include/log.h
@@ -104,6 +104,8 @@
LOGC_FS,
/** @LOGC_EXPO: Related to expo handling */
LOGC_EXPO,
+ /** @LOGC_CONSOLE: Related to the console and stdio */
+ LOGC_CONSOLE,
/** @LOGC_COUNT: Number of log categories */
LOGC_COUNT,
/** @LOGC_END: Sentinel value for lists of log categories */
@@ -125,7 +127,7 @@
* @level: Level of log record (indicating its severity)
* @file: File name of file where log record was generated
* @line: Line number in file where log record was generated
- * @func: Function where log record was generated
+ * @func: Function where log record was generated, NULL if not known
* @fmt: printf() format string for log record
* @...: Optional parameters, according to the format string @fmt
* Return: 0 if log record was emitted, -ve on error
@@ -141,7 +143,7 @@
* @level: Level of log record (indicating its severity)
* @file: File name of file where log record was generated
* @line: Line number in file where log record was generated
- * @func: Function where log record was generated
+ * @func: Function where log record was generated, NULL if not known
* @addr: Starting address to display at start of line
* @data: pointer to data buffer
* @width: data value width. May be 1, 2, or 4.
@@ -193,6 +195,12 @@
#define _LOG_DEBUG 0
#endif
+#ifdef CONFIG_LOGF_FUNC
+#define _log_func __func__
+#else
+#define _log_func NULL
+#endif
+
#if CONFIG_IS_ENABLED(LOG)
/* Emit a log record if the level is less that the maximum */
@@ -201,7 +209,7 @@
if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
_log((enum log_category_t)(_cat), \
(enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
- __LINE__, __func__, \
+ __LINE__, _log_func, \
pr_fmt(_fmt), ##_args); \
})
@@ -211,7 +219,7 @@
if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
_log_buffer((enum log_category_t)(_cat), \
(enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
- __LINE__, __func__, _addr, _data, \
+ __LINE__, _log_func, _addr, _data, \
_width, _count, _linelen); \
})
#else
@@ -314,7 +322,7 @@
#define assert_noisy(x) \
({ bool _val = (x); \
if (!_val) \
- __assert_fail(#x, "?", __LINE__, __func__); \
+ __assert_fail(#x, "?", __LINE__, _log_func); \
_val; \
})
diff --git a/include/mmc.h b/include/mmc.h
index 155a8e9..0044ff8 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -14,6 +14,7 @@
#include <linux/sizes.h>
#include <linux/compiler.h>
#include <linux/dma-direction.h>
+#include <cyclic.h>
#include <part.h>
struct bd_info;
@@ -372,6 +373,32 @@
#define MMC_TIMING_MMC_HS200 9
#define MMC_TIMING_MMC_HS400 10
+/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE values */
+enum emmc_boot_part {
+ EMMC_BOOT_PART_DEFAULT = 0,
+ EMMC_BOOT_PART_BOOT1 = 1,
+ EMMC_BOOT_PART_BOOT2 = 2,
+ EMMC_BOOT_PART_USER = 7,
+};
+
+/* emmc PARTITION_CONFIG BOOT_PARTITION_ENABLE names */
+extern const char *emmc_boot_part_names[8];
+
+/* emmc PARTITION_CONFIG ACCESS_ENABLE values */
+enum emmc_hwpart {
+ EMMC_HWPART_DEFAULT = 0, /* user */
+ EMMC_HWPART_BOOT1 = 1,
+ EMMC_HWPART_BOOT2 = 2,
+ EMMC_HWPART_RPMB = 3,
+ EMMC_HWPART_GP1 = 4,
+ EMMC_HWPART_GP2 = 5,
+ EMMC_HWPART_GP3 = 6,
+ EMMC_HWPART_GP4 = 7,
+};
+
+/* emmc PARTITION_CONFIG ACCESS_ENABLE names */
+extern const char *emmc_hwpart_names[8];
+
/* Driver model support */
/**
@@ -731,6 +758,8 @@
bool hs400_tuning:1;
enum bus_mode user_speed_mode; /* input speed mode from user */
+
+ CONFIG_IS_ENABLED(CYCLIC, (struct cyclic_info cyclic));
};
#if CONFIG_IS_ENABLED(DM_MMC)
diff --git a/include/os.h b/include/os.h
index 877404a..ae3ca6d 100644
--- a/include/os.h
+++ b/include/os.h
@@ -24,32 +24,32 @@
int os_printf(const char *format, ...);
/**
- * Access to the OS read() system call
+ * os_read() - access the OS read() system call
*
* @fd: File descriptor as returned by os_open()
* @buf: Buffer to place data
* @count: Number of bytes to read
- * Return: number of bytes read, or -1 on error
+ * Return: number of bytes read, or -errno on error
*/
ssize_t os_read(int fd, void *buf, size_t count);
/**
- * Access to the OS write() system call
+ * os_write() - access the OS write() system call
*
* @fd: File descriptor as returned by os_open()
* @buf: Buffer containing data to write
* @count: Number of bytes to write
- * Return: number of bytes written, or -1 on error
+ * Return: number of bytes written, or -errno on error
*/
ssize_t os_write(int fd, const void *buf, size_t count);
/**
- * Access to the OS lseek() system call
+ * os_lseek() - access the OS lseek() system call
*
* @fd: File descriptor as returned by os_open()
* @offset: File offset (based on whence)
* @whence: Position offset is relative to (see below)
- * Return: new file offset
+ * Return: new file offset, or -errno on error
*/
off_t os_lseek(int fd, off_t offset, int whence);
@@ -67,7 +67,7 @@
off_t os_filesize(int fd);
/**
- * Access to the OS open() system call
+ * os_open() - access the OS open() system call
*
* @pathname: Pathname of file to open
* @flags: Flags, like OS_O_RDONLY, OS_O_RDWR
@@ -162,7 +162,7 @@
void os_tty_raw(int fd, bool allow_sigs);
/**
- * os_fs_restore() - restore the tty to its original mode
+ * os_fd_restore() - restore the tty to its original mode
*
* Call this to restore the original terminal mode, after it has been changed
* by os_tty_raw(). This is an internal function.
@@ -207,14 +207,14 @@
void os_usleep(unsigned long usec);
/**
- * Gets a monotonic increasing number of nano seconds from the OS
+ * os_get_nsec() - get monotonically increasing number of nano seconds from OS
*
- * Return: a monotonic increasing time scaled in nano seconds
+ * Return: a monotoniccally increasing time scaled in nano seconds
*/
uint64_t os_get_nsec(void);
/**
- * Parse arguments and update sandbox state.
+ * os_parse_args() - parse arguments and update sandbox state.
*
* @state: sandbox state to update
* @argc: argument count
diff --git a/include/part.h b/include/part.h
index 54b986c..797b542 100644
--- a/include/part.h
+++ b/include/part.h
@@ -8,7 +8,7 @@
#include <blk.h>
#include <ide.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linker_lists.h>
#include <linux/errno.h>
#include <linux/list.h>
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 191d277..a8939b1 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2600,6 +2600,15 @@
#define PCI_DEVICE_ID_DCI_PCCOM2 0x0004
#define PCI_VENDOR_ID_INTEL 0x8086
+#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
+#define PCI_DEVICE_ID_INTEL_EHL_SGMII1 0x4b31
+#define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
#define PCI_DEVICE_ID_INTEL_EESSC 0x0008
#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index b8219d5..f896d82 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -54,6 +54,8 @@
PCA9450_REG_NUM,
};
+#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
+
int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
diff --git a/include/power/regulator.h b/include/power/regulator.h
index bb07a81..8a914df 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -415,26 +415,6 @@
int regulator_set_mode(struct udevice *dev, int mode_id);
/**
- * regulators_enable_boot_on() - enable regulators needed for boot
- *
- * This enables all regulators which are marked to be on at boot time. This
- * only works for regulators which don't have a range for voltage/current,
- * since in that case it is not possible to know which value to use.
- *
- * This effectively calls regulator_autoset() for every regulator.
- */
-int regulators_enable_boot_on(bool verbose);
-
-/**
- * regulators_enable_boot_off() - disable regulators needed for boot
- *
- * This disables all regulators which are marked to be off at boot time.
- *
- * This effectively calls regulator_unset() for every regulator.
- */
-int regulators_enable_boot_off(bool verbose);
-
-/**
* regulator_autoset: setup the voltage/current on a regulator
*
* The setup depends on constraints found in device's uclass's platform data
@@ -454,18 +434,6 @@
int regulator_autoset(struct udevice *dev);
/**
- * regulator_unset: turn off a regulator
- *
- * The setup depends on constraints found in device's uclass's platform data
- * (struct dm_regulator_uclass_platdata):
- *
- * - Disable - will set - if 'force_off' is set to true,
- *
- * The function returns on the first-encountered error.
- */
-int regulator_unset(struct udevice *dev);
-
-/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in device's
* uclass's platform data (struct dm_regulator_uclass_plat):
@@ -629,11 +597,6 @@
return -ENOSYS;
}
-static inline int regulators_enable_boot_on(bool verbose)
-{
- return -ENOSYS;
-}
-
static inline int regulator_autoset(struct udevice *dev)
{
return -ENOSYS;
diff --git a/include/rkmtd.h b/include/rkmtd.h
index 145fede..b747903 100644
--- a/include/rkmtd.h
+++ b/include/rkmtd.h
@@ -11,7 +11,7 @@
#define __RKMTD__
#include <part_efi.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#define LBA 64 + 512 + 33
diff --git a/include/sandbox_efi_capsule.h b/include/sandbox_efi_capsule.h
index 3e288e8..84d45ec 100644
--- a/include/sandbox_efi_capsule.h
+++ b/include/sandbox_efi_capsule.h
@@ -6,9 +6,9 @@
#if !defined(_SANDBOX_EFI_CAPSULE_H_)
#define _SANDBOX_EFI_CAPSULE_H_
-#define SANDBOX_UBOOT_IMAGE_GUID "09d7cf52-0720-4710-91d1-08469b7fe9c8"
-#define SANDBOX_UBOOT_ENV_IMAGE_GUID "5a7021f5-fef2-48b4-aaba-832e777418c0"
-#define SANDBOX_FIT_IMAGE_GUID "3673b45d-6a7c-46f3-9e60-adabb03f7937"
+#define SANDBOX_UBOOT_IMAGE_GUID "985f2937-7c2e-5e9a-8a5e-8e063312964b"
+#define SANDBOX_UBOOT_ENV_IMAGE_GUID "9e339473-c2eb-530a-a69b-0cd6bbbed40e"
+#define SANDBOX_FIT_IMAGE_GUID "46610520-469e-59dc-a8dd-c11832b877ea"
#define SANDBOX_INCORRECT_GUID "058b7d83-50d5-4c47-a195-60d86ad341c4"
#define UBOOT_FIT_IMAGE "u-boot_bin_env.itb"
diff --git a/include/spl.h b/include/spl.h
index 1eebea3..de808cc 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -282,55 +282,67 @@
#endif
}
+struct spl_load_info;
+
+/**
+ * spl_load_reader() - Read from device
+ *
+ * @load: Information about the load state
+ * @offset: Offset to read from in bytes. This must be a multiple of
+ * @load->bl_len.
+ * @count: Number of bytes to read. This must be a multiple of
+ * @load->bl_len.
+ * @buf: Buffer to read into
+ * @return number of bytes read, 0 on error
+ */
+typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf);
+
/**
* Information required to load data from a device
*
+ * @read: Function to call to read from the device
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
- * @read: Function to call to read from the device
*/
struct spl_load_info {
+ spl_load_reader read;
void *priv;
- /**
- * read() - Read from device
- *
- * @load: Information about the load state
- * @offset: Offset to read from in bytes. This must be a multiple of
- * @load->bl_len.
- * @count: Number of bytes to read. This must be a multiple of
- * @load->bl_len.
- * @buf: Buffer to read into
- * @return number of bytes read, 0 on error
- */
- ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
- void *buf);
#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
int bl_len;
+#endif
};
static inline int spl_get_bl_len(struct spl_load_info *info)
{
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
return info->bl_len;
+#else
+ return 1;
+#endif
}
static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
{
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
info->bl_len = bl_len;
-}
#else
-};
-
-static inline int spl_get_bl_len(struct spl_load_info *info)
-{
- return 1;
+ if (bl_len != 1)
+ panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+#endif
}
-static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+/**
+ * spl_load_init() - Set up a new spl_load_info structure
+ */
+static inline void spl_load_init(struct spl_load_info *load,
+ spl_load_reader h_read, void *priv,
+ uint bl_len)
{
- if (bl_len != 1)
- panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+ load->read = h_read;
+ load->priv = priv;
+ spl_set_bl_len(load, bl_len);
}
-#endif
/*
* We need to know the position of U-Boot in memory so we can jump to it. We
@@ -1073,4 +1085,20 @@
{
return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
}
+
+/**
+ * spl_write_upl_handoff() - Write a Universal Payload hand-off structure
+ *
+ * @spl_image: Information about the image being booted
+ * Return: 0 if OK, -ve on error
+ */
+int spl_write_upl_handoff(struct spl_image_info *spl_image);
+
+/**
+ * spl_upl_init() - Get UPL ready for information to be added
+ *
+ * This must be called before upl_add_image(), etc.
+ */
+void spl_upl_init(void);
+
#endif
diff --git a/include/spl_load.h b/include/spl_load.h
index 1c2b296..935f7d3 100644
--- a/include/spl_load.h
+++ b/include/spl_load.h
@@ -22,7 +22,7 @@
read = info->read(info, offset, ALIGN(sizeof(*header),
spl_get_bl_len(info)), header);
- if (read < sizeof(*header))
+ if (read < (int)sizeof(*header))
return -EIO;
if (image_get_magic(header) == FDT_MAGIC) {
@@ -83,6 +83,10 @@
read = info->read(info, offset + image_offset, size,
map_sysmem(spl_image->load_addr - overhead, size));
+
+ if (read < 0)
+ return read;
+
return read < spl_image->size ? -EIO : 0;
}
diff --git a/include/test/log.h b/include/test/log.h
index e902891..e3362b8 100644
--- a/include/test/log.h
+++ b/include/test/log.h
@@ -13,7 +13,8 @@
#define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG))
/* Declare a new logging test */
-#define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test)
-#define LOG_TEST_FLAGS(_name, _flags) UNIT_TEST(_name, _flags, log_test)
+#define LOG_TEST(_name) UNIT_TEST(_name, UTF_CONSOLE, log_test)
+#define LOG_TEST_FLAGS(_name, _flags) \
+ UNIT_TEST(_name, _flags | UTF_CONSOLE, log_test)
#endif /* __TEST_LOG_H__ */
diff --git a/include/test/spl.h b/include/test/spl.h
index a2a5f33..5fd28d9 100644
--- a/include/test/spl.h
+++ b/include/test/spl.h
@@ -154,6 +154,6 @@
#define SPL_TEST_DATA_SIZE 4099
/* Flags necessary for accessing DM devices */
-#define DM_FLAGS (UT_TESTF_DM | UT_TESTF_SCAN_FDT)
+#define DM_FLAGS (UTF_DM | UTF_SCAN_FDT)
#endif /* TEST_SPL_H */
diff --git a/include/test/suites.h b/include/test/suites.h
index 365d5f2..2ceef57 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -63,5 +63,6 @@
int do_ut_time(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
+int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
#endif /* __TEST_SUITES_H__ */
diff --git a/include/test/test.h b/include/test/test.h
index 838e3ce..92eec2e 100644
--- a/include/test/test.h
+++ b/include/test/test.h
@@ -24,11 +24,11 @@
* @fdt_chksum: crc8 of the device tree contents
* @fdt_copy: Copy of the device tree
* @fdt_size: Size of the device-tree copy
- * @other_fdt: Buffer for the other FDT (UT_TESTF_OTHER_FDT)
- * @other_fdt_size: Size of the other FDT (UT_TESTF_OTHER_FDT)
+ * @other_fdt: Buffer for the other FDT (UTF_OTHER_FDT)
+ * @other_fdt_size: Size of the other FDT (UTF_OTHER_FDT)
* @of_other: Live tree for the other FDT
* @runs_per_test: Number of times to run each test (typically 1)
- * @force_run: true to run tests marked with the UT_TESTF_MANUAL flag
+ * @force_run: true to run tests marked with the UTF_MANUAL flag
* @expect_str: Temporary string used to hold expected string value
* @actual_str: Temporary string used to hold actual string value
*/
@@ -55,24 +55,24 @@
};
/* Test flags for each test */
-enum {
- UT_TESTF_SCAN_PDATA = BIT(0), /* test needs platform data */
- UT_TESTF_PROBE_TEST = BIT(1), /* probe test uclass */
- UT_TESTF_SCAN_FDT = BIT(2), /* scan device tree */
- UT_TESTF_FLAT_TREE = BIT(3), /* test needs flat DT */
- UT_TESTF_LIVE_TREE = BIT(4), /* needs live device tree */
- UT_TESTF_CONSOLE_REC = BIT(5), /* needs console recording */
+enum ut_flags {
+ UTF_SCAN_PDATA = BIT(0), /* test needs platform data */
+ UTF_PROBE_TEST = BIT(1), /* probe test uclass */
+ UTF_SCAN_FDT = BIT(2), /* scan device tree */
+ UTF_FLAT_TREE = BIT(3), /* test needs flat DT */
+ UTF_LIVE_TREE = BIT(4), /* needs live device tree */
+ UTF_CONSOLE = BIT(5), /* needs console recording */
/* do extra driver model init and uninit */
- UT_TESTF_DM = BIT(6),
- UT_TESTF_OTHER_FDT = BIT(7), /* read in other device tree */
+ UTF_DM = BIT(6),
+ UTF_OTHER_FDT = BIT(7), /* read in other device tree */
/*
* Only run if explicitly requested with 'ut -f <suite> <test>'. The
* test name must end in "_norun" so that pytest detects this also,
* since it cannot access the flags.
*/
- UT_TESTF_MANUAL = BIT(8),
- UT_TESTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */
- UT_TESTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */
+ UTF_MANUAL = BIT(8),
+ UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */
+ UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */
};
/**
@@ -109,7 +109,7 @@
* @_name: concatenation of name of the test suite, "_test_", and the name
* of the test
* @_flags: an integer field that can be evaluated by the test suite
- * implementation
+ * implementation (see enum ut_flags)
* @_suite: name of the test suite concatenated with "_test"
*/
#define UNIT_TEST(_name, _flags, _suite) \
diff --git a/include/test/ut.h b/include/test/ut.h
index d3172af..c8838da 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -495,7 +495,7 @@
* @select_name: Name of a single test to run (from the list provided). If NULL
* then all tests are run
* @runs_per_test: Number of times to run each test (typically 1)
- * @force_run: Run tests that are marked as manual-only (UT_TESTF_MANUAL)
+ * @force_run: Run tests that are marked as manual-only (UTF_MANUAL)
* @test_insert: String describing a test to run after n other tests run, in the
* format n:name where n is the number of tests to run before this one and
* name is the name of the test to run. This is used to find which test causes
diff --git a/include/u-boot/uuid.h b/include/u-boot/uuid.h
new file mode 100644
index 0000000..7f8414d
--- /dev/null
+++ b/include/u-boot/uuid.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+#ifndef __UUID_H__
+#define __UUID_H__
+
+#include <linux/bitops.h>
+#include <linux/kconfig.h>
+
+/*
+ * UUID - Universally Unique IDentifier - 128 bits unique number.
+ * There are 5 versions and one variant of UUID defined by RFC4122
+ * specification. A UUID contains a set of fields. The set varies
+ * depending on the version of the UUID, as shown below:
+ * - time, MAC address(v1),
+ * - user ID(v2),
+ * - MD5 of name or URL(v3),
+ * - random data(v4),
+ * - SHA-1 of name or URL(v5),
+ *
+ * Layout of UUID:
+ * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
+ * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
+ * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
+ * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
+ * node - 48 bit
+ *
+ * source: https://www.ietf.org/rfc/rfc4122.txt
+ *
+ * UUID binary format (16 bytes):
+ *
+ * 4B-2B-2B-2B-6B (big endian - network byte order)
+ *
+ * UUID string is 36 length of characters (36 bytes):
+ *
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * be be be be be
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a binary UUID, le means the field should be converted
+ * to little endian and be means it should be converted to big endian.
+ *
+ * UUID is also used as GUID (Globally Unique Identifier) with the same format
+ * but with some fields stored in little endian.
+ *
+ * GUID:
+ * 0 9 14 19 24
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ * le le le be be
+ *
+ * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
+ */
+
+/* This is structure is in big-endian */
+struct uuid {
+ unsigned int time_low;
+ unsigned short time_mid;
+ unsigned short time_hi_and_version;
+ unsigned char clock_seq_hi_and_reserved;
+ unsigned char clock_seq_low;
+ unsigned char node[6];
+} __packed;
+
+/* Bits of a bitmask specifying the output format for GUIDs */
+#define UUID_STR_FORMAT_STD 0
+#define UUID_STR_FORMAT_GUID 0x1
+#define UUID_STR_UPPER_CASE 0x2
+
+/* Use UUID_STR_LEN + 1 for string space */
+#define UUID_STR_LEN 36
+#define UUID_BIN_LEN sizeof(struct uuid)
+
+#define UUID_VERSION_MASK 0xf000
+#define UUID_VERSION_SHIFT 12
+#define UUID_VERSION 0x4
+
+#define UUID_VARIANT_MASK 0xc0
+#define UUID_VARIANT_SHIFT 7
+#define UUID_VARIANT 0x1
+
+int uuid_str_valid(const char *uuid);
+
+/*
+ * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
+ *
+ * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
+ * @param uuid_bin - pointer to allocated array for big endian output [16B]
+ * @str_format - UUID string format: 0 - UUID; 1 - GUID
+ * Return: 0 if OK, -EINVAL if the string is not a valid UUID
+ */
+int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
+ int str_format);
+
+/*
+ * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
+ *
+ * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
+ * @param uuid_str: pointer to allocated array for output string [37B]
+ * @str_format: bit 0: 0 - UUID; 1 - GUID
+ * bit 1: 0 - lower case; 2 - upper case
+ */
+void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
+ int str_format);
+
+/*
+ * uuid_guid_get_bin() - this function get GUID bin for string
+ *
+ * @param guid_str - pointer to partition type string
+ * @param guid_bin - pointer to allocated array for big endian output [16B]
+ */
+int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
+
+/*
+ * uuid_guid_get_str() - this function get string for GUID.
+ *
+ * @param guid_bin - pointer to string with partition type guid [16B]
+ *
+ * Returns NULL if the type GUID is not known.
+ */
+const char *uuid_guid_get_str(const unsigned char *guid_bin);
+
+/*
+ * gen_rand_uuid() - this function generates a random binary UUID version 4.
+ * In this version all fields beside 4 bits of version and
+ * 2 bits of variant are randomly generated.
+ *
+ * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
+ */
+void gen_rand_uuid(unsigned char *uuid_bin);
+
+/*
+ * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
+ * formats UUID or GUID.
+ *
+ * @param uuid_str - pointer to allocated array [37B].
+ * @param - uuid output type: UUID - 0, GUID - 1
+ */
+void gen_rand_uuid_str(char *uuid_str, int str_format);
+
+struct efi_guid;
+
+/**
+ * gen_v5_guid() - generate little endian v5 GUID from namespace and other seed data.
+ *
+ * @namespace: pointer to UUID namespace salt
+ * @guid: pointer to allocated GUID output
+ * @...: NULL terminated list of seed data as pairs of pointers
+ * to data and their lengths
+ */
+void gen_v5_guid(const struct uuid *namespace, struct efi_guid *guid, ...);
+
+/**
+ * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
+ * @uuid_str: pointer to UUID string
+ * @uuid_bin: pointer to allocated array for little endian output [16B]
+ *
+ * UUID string is 36 characters (36 bytes):
+ *
+ * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
+ *
+ * where x is a hexadecimal character. Fields are separated by '-'s.
+ * When converting to a little endian binary UUID, the string fields are reversed.
+ *
+ * Return:
+ *
+ * uuid_bin filled with little endian UUID data
+ * On success 0 is returned. Otherwise, failure code.
+ */
+int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin);
+
+#endif
diff --git a/include/upl.h b/include/upl.h
new file mode 100644
index 0000000..2ec5ef1
--- /dev/null
+++ b/include/upl.h
@@ -0,0 +1,382 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __UPL_WRITE_H
+#define __UPL_WRITE_H
+
+#ifndef USE_HOSTCC
+
+#include <alist.h>
+#include <image.h>
+#include <dm/ofnode_decl.h>
+
+struct unit_test_state;
+
+#define UPLP_ADDRESS_CELLS "#address-cells"
+#define UPLP_SIZE_CELLS "#size-cells"
+
+#define UPLN_OPTIONS "options"
+#define UPLN_UPL_PARAMS "upl-params"
+#define UPLP_SMBIOS "smbios"
+#define UPLP_ACPI "acpi"
+#define UPLP_BOOTMODE "bootmode"
+#define UPLP_ADDR_WIDTH "addr-width"
+#define UPLP_ACPI_NVS_SIZE "acpi-nvs-size"
+
+#define UPLPATH_UPL_IMAGE "/options/upl-image"
+#define UPLN_UPL_IMAGE "upl-image"
+#define UPLN_IMAGE "image"
+#define UPLP_FIT "fit"
+#define UPLP_CONF_OFFSET "conf-offset"
+#define UPLP_LOAD "load"
+#define UPLP_SIZE "size"
+#define UPLP_OFFSET "offset"
+#define UPLP_DESCRIPTION "description"
+
+#define UPLN_MEMORY "memory"
+#define UPLP_HOTPLUGGABLE "hotpluggable"
+
+#define UPLPATH_MEMORY_MAP "/memory-map"
+#define UPLN_MEMORY_MAP "memory-map"
+#define UPLP_USAGE "usage"
+
+#define UPLN_MEMORY_RESERVED "reserved-memory"
+#define UPLPATH_MEMORY_RESERVED "/reserved-memory"
+#define UPLP_NO_MAP "no-map"
+
+#define UPLN_SERIAL "serial"
+#define UPLP_REG "reg"
+#define UPLP_COMPATIBLE "compatible"
+#define UPLP_CLOCK_FREQUENCY "clock-frequency"
+#define UPLP_CURRENT_SPEED "current-speed"
+#define UPLP_REG_IO_SHIFT "reg-io-shift"
+#define UPLP_REG_OFFSET "reg-offset"
+#define UPLP_REG_IO_WIDTH "reg-io-width"
+#define UPLP_VIRTUAL_REG "virtual-reg"
+#define UPLP_ACCESS_TYPE "access-type"
+
+#define UPLN_GRAPHICS "framebuffer"
+#define UPLC_GRAPHICS "simple-framebuffer"
+#define UPLP_WIDTH "width"
+#define UPLP_HEIGHT "height"
+#define UPLP_STRIDE "stride"
+#define UPLP_GRAPHICS_FORMAT "format"
+
+/**
+ * enum upl_boot_mode - Encodes the boot mode
+ *
+ * Each is a bit number from the boot_mode mask
+ */
+enum upl_boot_mode {
+ UPLBM_FULL,
+ UPLBM_MINIMAL,
+ UPLBM_FAST,
+ UPLBM_DIAG,
+ UPLBM_DEFAULT,
+ UPLBM_S2,
+ UPLBM_S3,
+ UPLBM_S4,
+ UPLBM_S5,
+ UPLBM_FACTORY,
+ UPLBM_FLASH,
+ UPLBM_RECOVERY,
+
+ UPLBM_COUNT,
+};
+
+/**
+ * struct upl_image - UPL image informaiton
+ *
+ * @load: Address image was loaded to
+ * @size: Size of image in bytes
+ * @offset: Offset of the image in the FIT (0=none)
+ * @desc: Description of the iamge (taken from the FIT)
+ */
+struct upl_image {
+ ulong load;
+ ulong size;
+ uint offset;
+ const char *description;
+};
+
+/**
+ * struct memregion - Information about a region of memory
+ *
+ * @base: Base address
+ * @size: Size in bytes
+ */
+struct memregion {
+ ulong base;
+ ulong size;
+};
+
+/**
+ * struct upl_mem - Information about physical-memory layout
+ *
+ * TODO: Figure out initial-mapped-area
+ *
+ * @region: Memory region list (struct memregion)
+ * @hotpluggable: true if hotpluggable
+ */
+struct upl_mem {
+ struct alist region;
+ bool hotpluggable;
+};
+
+/**
+ * enum upl_usage - Encodes the usage
+ *
+ * Each is a bit number from the usage mask
+ */
+enum upl_usage {
+ UPLUS_ACPI_RECLAIM,
+ UPLUS_ACPI_NVS,
+ UPLUS_BOOT_CODE,
+ UPLUS_BOOT_DATA,
+ UPLUS_RUNTIME_CODE,
+ UPLUS_RUNTIME_DATA,
+ UPLUS_COUNT
+};
+
+/**
+ * struct upl_memmap - Information about logical-memory layout
+ *
+ * @name: Node name to use
+ * @region: Memory region list (struct memregion)
+ * @usage: Memory-usage mask (enum upl_usage)
+ */
+struct upl_memmap {
+ const char *name;
+ struct alist region;
+ uint usage;
+};
+
+/**
+ * struct upl_memres - Reserved memory
+ *
+ * @name: Node name to use
+ * @region: Reserved memory region list (struct memregion)
+ * @no_map: true to indicate that a virtual mapping must not be created
+ */
+struct upl_memres {
+ const char *name;
+ struct alist region;
+ bool no_map;
+};
+
+enum upl_serial_access_type {
+ UPLSAT_MMIO,
+ UPLSAT_IO,
+};
+
+/* serial defaults */
+enum {
+ UPLD_REG_IO_SHIFT = 0,
+ UPLD_REG_OFFSET = 0,
+ UPLD_REG_IO_WIDTH = 1,
+};
+
+/**
+ * enum upl_access_type - Access types
+ *
+ * @UPLAT_MMIO: Memory-mapped I/O
+ * @UPLAT_IO: Separate I/O
+ */
+enum upl_access_type {
+ UPLAT_MMIO,
+ UPLAT_IO,
+};
+
+/**
+ * struct upl_serial - Serial console
+ *
+ * @compatible: Compatible string (NULL if there is no serial console)
+ * @clock_frequency: Input clock frequency of UART
+ * @current_speed: Current baud rate of UART
+ * @reg: List of base address and size of registers (struct memregion)
+ * @reg_shift_log2: log2 of distance between each register
+ * @reg_offset: Offset of registers from the base address
+ * @reg_width: Register width in bytes
+ * @virtual_reg: Virtual register access (0 for none)
+ * @access_type: Register access type to use
+ */
+struct upl_serial {
+ const char *compatible;
+ uint clock_frequency;
+ uint current_speed;
+ struct alist reg;
+ uint reg_io_shift;
+ uint reg_offset;
+ uint reg_io_width;
+ ulong virtual_reg;
+ enum upl_serial_access_type access_type;
+};
+
+/**
+ * enum upl_graphics_format - Graphics formats
+ *
+ * @UPLGF_ARGB32: 32bpp format using 0xaarrggbb
+ * @UPLGF_ABGR32: 32bpp format using 0xaabbggrr
+ * @UPLGF_ARGB64: 64bpp format using 0xaaaabbbbggggrrrr
+ */
+enum upl_graphics_format {
+ UPLGF_ARGB32,
+ UPLGF_ABGR32,
+ UPLGF_ABGR64,
+};
+
+/**
+ * @reg: List of base address and size of registers (struct memregion)
+ * @width: Width of display in pixels
+ * @height: Height of display in pixels
+ * @stride: Number of bytes from one line to the next
+ * @format: Pixel format
+ */
+struct upl_graphics {
+ struct alist reg;
+ uint width;
+ uint height;
+ uint stride;
+ enum upl_graphics_format format;
+};
+
+/*
+ * Information about the UPL state
+ *
+ * @addr_cells: Number of address cells used in the handoff
+ * @size_cells: Number of size cells used in the handoff
+ * @bootmode: Boot-mode mask (enum upl_boot_mode)
+ * @fit: Address of FIT image that was loaded
+ * @conf_offset: Offset in FIT of the configuration that was selected
+ * @addr_width: Adress-bus width of machine, e.g. 46 for 46 bits
+ * @acpi_nvs_size: Size of the ACPI non-volatile-storage area in bytes
+ * @image: Information about each image (struct upl_image)
+ * @mem: Information about physical-memory regions (struct upl_mem)
+ * @nennap: Information about logical-memory regions (struct upl_memmap)
+ * @nennap: Information about reserved-memory regions (struct upl_memres)
+ */
+struct upl {
+ int addr_cells;
+ int size_cells;
+
+ ulong smbios;
+ ulong acpi;
+ uint bootmode;
+ ulong fit;
+ uint conf_offset;
+ uint addr_width;
+ uint acpi_nvs_size;
+
+ struct alist image;
+ struct alist mem;
+ struct alist memmap;
+ struct alist memres;
+ struct upl_serial serial;
+ struct upl_graphics graphics;
+};
+
+/**
+ * upl_write_handoff() - Write a Unversal Payload handoff structure
+ *
+ * upl: UPL state to write
+ * @root: root node to write it to
+ * @skip_existing: Avoid recreating any nodes which already exist in the
+ * devicetree. For example, if there is a serial node, just leave it alone,
+ * since don't need to create a new one
+ * Return: 0 on success, -ve on error
+ */
+int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing);
+
+/**
+ * upl_create_handoff_tree() - Write a Unversal Payload handoff structure
+ *
+ * upl: UPL state to write
+ * @treep: Returns a new tree containing the handoff
+ * Return: 0 on success, -ve on error
+ */
+int upl_create_handoff_tree(const struct upl *upl, oftree *treep);
+
+/**
+ * upl_read_handoff() - Read a Unversal Payload handoff structure
+ *
+ * upl: UPL state to read into
+ * @tree: Devicetree containing the data to read
+ * Return: 0 on success, -ve on error
+ */
+int upl_read_handoff(struct upl *upl, oftree tree);
+
+/**
+ * upl_get_test_data() - Fill a UPL with some test data
+ *
+ * @uts: Test state (can be uninited)
+ * @upl: Returns test data
+ * Return: 0 on success, 1 on error
+ */
+int upl_get_test_data(struct unit_test_state *uts, struct upl *upl);
+#endif /* USE_HOSTCC */
+
+#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_SPL_BUILD)
+
+/**
+ * upl_set_fit_info() - Set up basic info about the FIT
+ *
+ * @fit: Address of FIT
+ * @conf_offset: Configuration node being used
+ * @entry_addr: Entry address for next phase
+ */
+void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr);
+
+/**
+ * upl_set_fit_addr() - Set up the address of the FIT
+ *
+ * @fit: Address of FIT
+ */
+void upl_set_fit_addr(ulong fit);
+
+#else
+static inline void upl_set_fit_addr(ulong fit) {}
+static inline void upl_set_fit_info(ulong fit, int conf_offset,
+ ulong entry_addr) {}
+#endif /* UPL && SPL */
+
+/**
+ * _upl_add_image() - Internal function to add a new image to the UPL
+ *
+ * @node: Image node offset in FIT
+ * @load_addr: Address to which images was loaded
+ * @size: Image size in bytes
+ * @desc: Description of image
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc);
+
+/**
+ * upl_add_image() - Add a new image to the UPL
+ *
+ * @fit: Pointer to FIT
+ * @node: Image node offset in FIT
+ * @load_addr: Address to which images was loaded
+ * @size: Image size in bytes
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+static inline int upl_add_image(const void *fit, int node, ulong load_addr,
+ ulong size)
+{
+ if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_SPL_BUILD)) {
+ const char *desc = fdt_getprop(fit, node, FIT_DESC_PROP, NULL);
+
+ return _upl_add_image(node, load_addr, size, desc);
+ }
+
+ return 0;
+}
+
+/** upl_init() - Set up a UPL struct */
+void upl_init(struct upl *upl);
+
+#endif /* __UPL_WRITE_H */
diff --git a/include/usb.h b/include/usb.h
index fcbe214..be37ed2 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -250,20 +250,12 @@
#endif
-#ifdef CONFIG_USB_KEYBOARD
-
/*
* USB Keyboard reports are 8 bytes in boot protocol.
* Appendix B of HID Device Class Definition 1.11
*/
#define USB_KBD_BOOT_REPORT_SIZE 8
-int drv_usb_kbd_init(void);
-int usb_kbd_deregister(int force);
-
-#endif
-/* routines */
-
/*
* usb_init() - initialize the USB Controllers
*
@@ -1100,4 +1092,16 @@
*/
void usb_show_tree(void);
+/**
+ * usb_kbd_remove_for_test() - Remove any USB keyboard
+ *
+ * This can only be called from test_pre_run(). It removes the USB keyboard from
+ * the console system so that the USB device can be dropped
+ */
+#if CONFIG_IS_ENABLED(USB_KEYBOARD)
+int usb_kbd_remove_for_test(void);
+#else
+static inline int usb_kbd_remove_for_test(void) { return 0; }
+#endif
+
#endif /*_USB_H_ */
diff --git a/include/uuid.h b/include/uuid.h
deleted file mode 100644
index f5a9412..0000000
--- a/include/uuid.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014 Samsung Electronics
- * Przemyslaw Marczak <p.marczak@samsung.com>
- * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
- *
- * Authors:
- * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
- */
-#ifndef __UUID_H__
-#define __UUID_H__
-
-#include <linux/bitops.h>
-
-/*
- * UUID - Universally Unique IDentifier - 128 bits unique number.
- * There are 5 versions and one variant of UUID defined by RFC4122
- * specification. A UUID contains a set of fields. The set varies
- * depending on the version of the UUID, as shown below:
- * - time, MAC address(v1),
- * - user ID(v2),
- * - MD5 of name or URL(v3),
- * - random data(v4),
- * - SHA-1 of name or URL(v5),
- *
- * Layout of UUID:
- * timestamp - 60-bit: time_low, time_mid, time_hi_and_version
- * version - 4 bit (bit 4 through 7 of the time_hi_and_version)
- * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low
- * variant: - bit 6 and 7 of clock_seq_hi_and_reserved
- * node - 48 bit
- *
- * source: https://www.ietf.org/rfc/rfc4122.txt
- *
- * UUID binary format (16 bytes):
- *
- * 4B-2B-2B-2B-6B (big endian - network byte order)
- *
- * UUID string is 36 length of characters (36 bytes):
- *
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * be be be be be
- *
- * where x is a hexadecimal character. Fields are separated by '-'s.
- * When converting to a binary UUID, le means the field should be converted
- * to little endian and be means it should be converted to big endian.
- *
- * UUID is also used as GUID (Globally Unique Identifier) with the same binary
- * format but it differs in string format like below.
- *
- * GUID:
- * 0 9 14 19 24
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- * le le le be be
- *
- * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id.
- */
-
-/* This is structure is in big-endian */
-struct uuid {
- unsigned int time_low;
- unsigned short time_mid;
- unsigned short time_hi_and_version;
- unsigned char clock_seq_hi_and_reserved;
- unsigned char clock_seq_low;
- unsigned char node[6];
-} __packed;
-
-/* Bits of a bitmask specifying the output format for GUIDs */
-#define UUID_STR_FORMAT_STD 0
-#define UUID_STR_FORMAT_GUID BIT(0)
-#define UUID_STR_UPPER_CASE BIT(1)
-
-/* Use UUID_STR_LEN + 1 for string space */
-#define UUID_STR_LEN 36
-#define UUID_BIN_LEN sizeof(struct uuid)
-
-#define UUID_VERSION_MASK 0xf000
-#define UUID_VERSION_SHIFT 12
-#define UUID_VERSION 0x4
-
-#define UUID_VARIANT_MASK 0xc0
-#define UUID_VARIANT_SHIFT 7
-#define UUID_VARIANT 0x1
-
-int uuid_str_valid(const char *uuid);
-
-/*
- * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data.
- *
- * @param uuid_str - pointer to UUID or GUID string [37B] or GUID shorcut
- * @param uuid_bin - pointer to allocated array for big endian output [16B]
- * @str_format - UUID string format: 0 - UUID; 1 - GUID
- * Return: 0 if OK, -EINVAL if the string is not a valid UUID
- */
-int uuid_str_to_bin(const char *uuid_str, unsigned char *uuid_bin,
- int str_format);
-
-/*
- * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID.
- *
- * @param uuid_bin: pointer to binary data of UUID (big endian) [16B]
- * @param uuid_str: pointer to allocated array for output string [37B]
- * @str_format: bit 0: 0 - UUID; 1 - GUID
- * bit 1: 0 - lower case; 2 - upper case
- */
-void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
- int str_format);
-
-/*
- * uuid_guid_get_bin() - this function get GUID bin for string
- *
- * @param guid_str - pointer to partition type string
- * @param guid_bin - pointer to allocated array for big endian output [16B]
- */
-int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
-
-/*
- * uuid_guid_get_str() - this function get string for GUID.
- *
- * @param guid_bin - pointer to string with partition type guid [16B]
- *
- * Returns NULL if the type GUID is not known.
- */
-const char *uuid_guid_get_str(const unsigned char *guid_bin);
-
-/*
- * gen_rand_uuid() - this function generates a random binary UUID version 4.
- * In this version all fields beside 4 bits of version and
- * 2 bits of variant are randomly generated.
- *
- * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian.
- */
-void gen_rand_uuid(unsigned char *uuid_bin);
-
-/*
- * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string
- * formats UUID or GUID.
- *
- * @param uuid_str - pointer to allocated array [37B].
- * @param - uuid output type: UUID - 0, GUID - 1
- */
-void gen_rand_uuid_str(char *uuid_str, int str_format);
-
-/**
- * uuid_str_to_le_bin() - Convert string UUID to little endian binary data.
- * @uuid_str: pointer to UUID string
- * @uuid_bin: pointer to allocated array for little endian output [16B]
- *
- * UUID string is 36 characters (36 bytes):
- *
- * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx
- *
- * where x is a hexadecimal character. Fields are separated by '-'s.
- * When converting to a little endian binary UUID, the string fields are reversed.
- *
- * Return:
- *
- * uuid_bin filled with little endian UUID data
- * On success 0 is returned. Otherwise, failure code.
- */
-int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin);
-
-#endif
diff --git a/include/video.h b/include/video.h
index 4013a94..606c8a3 100644
--- a/include/video.h
+++ b/include/video.h
@@ -420,4 +420,15 @@
*/
int video_reserve_from_bloblist(struct video_handoff *ho);
+/**
+ * video_get_fb() - Get the first framebuffer address
+ *
+ * This function does not probe video devices, so can only be used after a video
+ * device has been activated.
+ *
+ * Return: address of the framebuffer of the first video device found, or 0 if
+ * there is no device
+ */
+ulong video_get_fb(void);
+
#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index 2059219..1dd4f27 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -73,6 +73,7 @@
config LIB_UUID
bool
+ select SHA1
config RANDOM_UUID
bool "GPT Random UUID generation"
@@ -403,7 +404,7 @@
config TRACE_EARLY_ADDR
hex "Address of early trace buffer in U-Boot"
depends on TRACE_EARLY
- default 0x00100000
+ default 0x00200000
help
Sets the address of the early trace buffer in U-Boot. This memory
must be accessible before relocation.
@@ -1081,8 +1082,6 @@
help
A simple parser for SMBIOS data.
-source "lib/efi/Kconfig"
-source "lib/efi_loader/Kconfig"
source "lib/optee/Kconfig"
config TEST_FDTDEC
@@ -1102,42 +1101,19 @@
bool "Enable the logical memory blocks library (lmb)"
default y if ARC || ARM || M68K || MICROBLAZE || MIPS || \
NIOS2 || PPC || RISCV || SANDBOX || SH || X86 || XTENSA
- help
- Support the library logical memory blocks.
-
-config LMB_USE_MAX_REGIONS
- bool "Use a common number of memory and reserved regions in lmb lib"
- default y
+ select ARCH_MISC_INIT if PPC
help
- Define the number of supported memory regions in the library logical
- memory blocks.
- This feature allow to reduce the lmb library size by using compiler
- optimization when LMB_MEMORY_REGIONS == LMB_RESERVED_REGIONS.
+ Support the library logical memory blocks. This will require
+ a malloc() implementation for defining the data structures
+ needed for maintaining the LMB memory map.
-config LMB_MAX_REGIONS
- int "Number of memory and reserved regions in lmb lib"
- depends on LMB_USE_MAX_REGIONS
- default 16
- help
- Define the number of supported regions, memory and reserved, in the
- library logical memory blocks.
-
-config LMB_MEMORY_REGIONS
- int "Number of memory regions in lmb lib"
- depends on !LMB_USE_MAX_REGIONS
- default 8
- help
- Define the number of supported memory regions in the library logical
- memory blocks.
- The minimal value is CONFIG_NR_DRAM_BANKS.
-
-config LMB_RESERVED_REGIONS
- int "Number of reserved regions in lmb lib"
- depends on !LMB_USE_MAX_REGIONS
- default 8
+config SPL_LMB
+ bool "Enable LMB module for SPL"
+ depends on SPL && SPL_FRAMEWORK && SPL_SYS_MALLOC
help
- Define the number of supported reserved regions in the library logical
- memory blocks.
+ Enable support for Logical Memory Block library routines in
+ SPL. This will require a malloc() implementation for defining
+ the data structures needed for maintaining the LMB memory map.
config PHANDLE_CHECK_SEQ
bool "Enable phandle check while getting sequence number"
diff --git a/lib/Makefile b/lib/Makefile
index e389ad0..d300249 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -118,7 +118,7 @@
obj-y += hang.o
obj-y += linux_compat.o
obj-y += linux_string.o
-obj-$(CONFIG_LMB) += lmb.o
+obj-$(CONFIG_$(SPL_TPL_)LMB) += lmb.o
obj-y += membuff.o
obj-$(CONFIG_REGEX) += slre.o
obj-y += string.o
@@ -147,6 +147,7 @@
obj-$(CONFIG_$(SPL_)OID_REGISTRY) += oid_registry.o
obj-y += abuf.o
+obj-y += alist.o
obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c
index 6733809..5714acc 100644
--- a/lib/acpi/acpi_dp.c
+++ b/lib/acpi/acpi_dp.c
@@ -9,7 +9,7 @@
#include <dm.h>
#include <log.h>
#include <malloc.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_dp.h>
#include <dm/acpi.h>
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index b95cabb..ecff5a5 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -10,7 +10,7 @@
#include <dm.h>
#include <log.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_table.h>
diff --git a/lib/alist.c b/lib/alist.c
new file mode 100644
index 0000000..b7928ca
--- /dev/null
+++ b/lib/alist.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a contiguous list of pointers which be allocated and freed
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <alist.h>
+#include <display_options.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <string.h>
+
+enum {
+ ALIST_INITIAL_SIZE = 4, /* default size of unsized list */
+};
+
+bool alist_init(struct alist *lst, uint obj_size, uint start_size)
+{
+ /* Avoid realloc for the initial size to help malloc_simple */
+ memset(lst, '\0', sizeof(struct alist));
+ if (start_size) {
+ lst->data = calloc(obj_size, start_size);
+ if (!lst->data) {
+ lst->flags = ALISTF_FAIL;
+ return false;
+ }
+ lst->alloc = start_size;
+ }
+ lst->obj_size = obj_size;
+
+ return true;
+}
+
+void alist_uninit(struct alist *lst)
+{
+ free(lst->data);
+
+ /* Clear fields to avoid any confusion */
+ memset(lst, '\0', sizeof(struct alist));
+}
+
+/**
+ * alist_expand_to() - Expand a list to the given size
+ *
+ * @lst: List to modify
+ * @inc_by: Amount to expand to
+ * Return: true if OK, false if out of memory
+ */
+static bool alist_expand_to(struct alist *lst, uint new_alloc)
+{
+ void *new_data;
+
+ if (lst->flags & ALISTF_FAIL)
+ return false;
+
+ /* avoid using realloc() since it increases code size */
+ new_data = malloc(lst->obj_size * new_alloc);
+ if (!new_data) {
+ lst->flags |= ALISTF_FAIL;
+ return false;
+ }
+
+ memcpy(new_data, lst->data, lst->obj_size * lst->alloc);
+ free(lst->data);
+
+ memset(new_data + lst->obj_size * lst->alloc, '\0',
+ lst->obj_size * (new_alloc - lst->alloc));
+ lst->alloc = new_alloc;
+ lst->data = new_data;
+
+ return true;
+}
+
+bool alist_expand_by(struct alist *lst, uint inc_by)
+{
+ return alist_expand_to(lst, lst->alloc + inc_by);
+}
+
+/**
+ * alist_expand_min() - Expand to at least the provided size
+ *
+ * Expands to the lowest power of two which can incorporate the new size
+ *
+ * @lst: alist to expand
+ * @min_alloc: Minimum new allocated size; if 0 then ALIST_INITIAL_SIZE is used
+ * Return: true if OK, false if out of memory
+ */
+static bool alist_expand_min(struct alist *lst, uint min_alloc)
+{
+ uint new_alloc;
+
+ for (new_alloc = lst->alloc ?: ALIST_INITIAL_SIZE;
+ new_alloc < min_alloc;)
+ new_alloc *= 2;
+
+ return alist_expand_to(lst, new_alloc);
+}
+
+const void *alist_get_ptr(const struct alist *lst, uint index)
+{
+ if (index >= lst->count)
+ return NULL;
+
+ return lst->data + index * lst->obj_size;
+}
+
+void *alist_ensure_ptr(struct alist *lst, uint index)
+{
+ uint minsize = index + 1;
+ void *ptr;
+
+ if (index >= lst->alloc && !alist_expand_min(lst, minsize))
+ return NULL;
+
+ ptr = lst->data + index * lst->obj_size;
+ if (minsize >= lst->count)
+ lst->count = minsize;
+
+ return ptr;
+}
+
+void *alist_add_placeholder(struct alist *lst)
+{
+ return alist_ensure_ptr(lst, lst->count);
+}
+
+void *alist_add_ptr(struct alist *lst, void *obj)
+{
+ void *ptr;
+
+ ptr = alist_add_placeholder(lst);
+ if (!ptr)
+ return NULL;
+ memcpy(ptr, obj, lst->obj_size);
+
+ return ptr;
+}
+
+void *alist_uninit_move_ptr(struct alist *alist, size_t *countp)
+{
+ void *ptr;
+
+ if (countp)
+ *countp = alist->count;
+ if (!alist->count) {
+ alist_uninit(alist);
+ return NULL;
+ }
+
+ ptr = alist->data;
+
+ /* Clear everything out so there is no record of the data */
+ alist_init(alist, alist->obj_size, 0);
+
+ return ptr;
+}
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 4e2dbda..b6bbcbf 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -44,7 +44,9 @@
DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd));
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
DEFINE(GD_ENV_ADDR, offsetof(struct global_data, env_addr));
+#endif
return 0;
}
diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig
index 6e0656a..742f6d9 100644
--- a/lib/crypto/Kconfig
+++ b/lib/crypto/Kconfig
@@ -1,6 +1,6 @@
menuconfig ASYMMETRIC_KEY_TYPE
bool "Asymmetric (public-key cryptographic) key Support"
- depends on FIT_SIGNATURE
+ depends on FIT_SIGNATURE || RSA_VERIFY_WITH_PKEY
help
This option provides support for a key type that holds the data for
the asymmetric keys used for public key cryptographic operations such
diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig
index c2b9bb7..81ed3e6 100644
--- a/lib/efi/Kconfig
+++ b/lib/efi/Kconfig
@@ -1,3 +1,6 @@
+menu "U-Boot as UEFI application"
+ depends on X86
+
config EFI
bool "Support running U-Boot from EFI"
depends on X86
@@ -72,3 +75,5 @@
use. U-Boot allocates this from EFI on start-up (along with a few
other smaller amounts) and it can never be increased after that.
It is used as the RAM size in with U-Boot.
+
+endmenu
diff --git a/lib/efi/efi_app.c b/lib/efi/efi_app.c
index 88332c3..9b94a93 100644
--- a/lib/efi/efi_app.c
+++ b/lib/efi/efi_app.c
@@ -17,7 +17,7 @@
#include <init.h>
#include <malloc.h>
#include <sysreset.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm/global_data.h>
#include <linux/err.h>
#include <linux/types.h>
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 6ffefa9..e58b882 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -1,3 +1,5 @@
+menu "UEFI Support"
+
config EFI_LOADER
bool "Support running UEFI applications"
depends on OF_LIBFDT && ( \
@@ -41,13 +43,58 @@
You may enable CMD_BOOTEFI_BINARY so that you can use bootefi
command to do that.
-config EFI_BOOTMGR
- bool "UEFI Boot Manager"
+config EFI_SECURE_BOOT
+ bool "Enable EFI secure boot support"
+ depends on EFI_LOADER && FIT_SIGNATURE
+ select HASH
+ select SHA256
+ select RSA
+ select RSA_VERIFY_WITH_PKEY
+ select IMAGE_SIGN_INFO
+ select ASYMMETRIC_KEY_TYPE
+ select ASYMMETRIC_PUBLIC_KEY_SUBTYPE
+ select X509_CERTIFICATE_PARSER
+ select PKCS7_MESSAGE_PARSER
+ select PKCS7_VERIFY
+ select MSCODE_PARSER
+ select EFI_SIGNATURE_SUPPORT
+ help
+ Select this option to enable EFI secure boot support.
+ Once SecureBoot mode is enforced, any EFI binary can run only if
+ it is signed with a trusted key. To do that, you need to install,
+ at least, PK, KEK and db.
+
+config EFI_SIGNATURE_SUPPORT
+ bool
+
+menu "UEFI services"
+
+config EFI_GET_TIME
+ bool "GetTime() runtime service"
+ depends on DM_RTC
default y
help
- Select this option if you want to select the UEFI binary to be booted
- via UEFI variables Boot####, BootOrder, and BootNext. You should also
- normally enable CMD_BOOTEFI_BOOTMGR so that the command is available.
+ Provide the GetTime() runtime service at boottime. This service
+ can be used by an EFI application to read the real time clock.
+
+config EFI_SET_TIME
+ bool "SetTime() runtime service"
+ depends on EFI_GET_TIME
+ default y if ARCH_QEMU || SANDBOX
+ help
+ Provide the SetTime() runtime service at boottime. This service
+ can be used by an EFI application to adjust the real time clock.
+
+config EFI_HAVE_RUNTIME_RESET
+ # bool "Reset runtime service is available"
+ bool
+ default y
+ depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \
+ SANDBOX || SYSRESET_SBI || SYSRESET_X86
+
+endmenu
+
+menu "UEFI Variables"
choice
prompt "Store for non-volatile UEFI variables"
@@ -172,30 +219,18 @@
Minimum 4096, default 131072
-config EFI_GET_TIME
- bool "GetTime() runtime service"
- depends on DM_RTC
- default y
+config EFI_PLATFORM_LANG_CODES
+ string "Language codes supported by firmware"
+ default "en-US"
help
- Provide the GetTime() runtime service at boottime. This service
- can be used by an EFI application to read the real time clock.
+ This value is used to initialize the PlatformLangCodes variable. Its
+ value is a semicolon (;) separated list of language codes in native
+ RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
+ to initialize the PlatformLang variable.
-config EFI_SET_TIME
- bool "SetTime() runtime service"
- depends on EFI_GET_TIME
- default y if ARCH_QEMU || SANDBOX
- help
- Provide the SetTime() runtime service at boottime. This service
- can be used by an EFI application to adjust the real time clock.
+endmenu
-config EFI_SCROLL_ON_CLEAR_SCREEN
- bool "Avoid overwriting previous output on clear screen"
- help
- Instead of erasing the screen content when the console screen should
- be cleared, emit blank new lines so that previous output is scrolled
- out of sight rather than overwritten. On serial consoles this allows
- to capture complete boot logs (except for interactive menus etc.)
- and can ease debugging related issues.
+menu "Capsule support"
config EFI_HAVE_CAPSULE_SUPPORT
bool
@@ -237,6 +272,18 @@
executed as part of U-Boot initialisation so that they will
surely take place whatever is set to distro_bootcmd.
+config EFI_CAPSULE_NAMESPACE_GUID
+ string "Namespace for dynamic capsule GUIDs"
+ # v4 UUID as a default for upstream U-Boot boards
+ default "8c9f137e-91dc-427b-b2d6-b420faebaf2a"
+ depends on EFI_HAVE_CAPSULE_SUPPORT
+ help
+ Define the namespace or "salt" GUID used to generate the per-image
+ GUIDs. This should be a GUID in the standard 8-4-4-4-12 format.
+
+ Device vendors are expected to generate their own namespace GUID
+ to avoid conflicts with upstream/community images.
+
config EFI_CAPSULE_FIRMWARE
bool
@@ -309,6 +356,10 @@
embedded in the platform's device tree and used for capsule
authentication at the time of capsule update.
+endmenu
+
+menu "UEFI protocol support"
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
@@ -362,39 +413,6 @@
endif
-config EFI_LOADER_BOUNCE_BUFFER
- bool "EFI Applications use bounce buffers for DMA operations"
- help
- Some hardware does not support DMA to full 64bit addresses. For this
- hardware we can create a bounce buffer so that payloads don't have to
- worry about platform details.
-
-config EFI_PLATFORM_LANG_CODES
- string "Language codes supported by firmware"
- default "en-US"
- help
- This value is used to initialize the PlatformLangCodes variable. Its
- value is a semicolon (;) separated list of language codes in native
- RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
- to initialize the PlatformLang variable.
-
-config EFI_HAVE_RUNTIME_RESET
- # bool "Reset runtime service is available"
- bool
- default y
- depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \
- SANDBOX || SYSRESET_SBI || SYSRESET_X86
-
-config EFI_GRUB_ARM32_WORKAROUND
- bool "Workaround for GRUB on 32bit ARM"
- default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
- default y
- depends on ARM && !ARM64
- help
- GRUB prior to version 2.04 requires U-Boot to disable caches. This
- workaround currently is also needed on systems with caches that
- cannot be managed via CP15.
-
config EFI_RNG_PROTOCOL
bool "EFI_RNG_PROTOCOL support"
depends on DM_RNG
@@ -447,29 +465,36 @@
installed and Linux 5.7+ will ignore any initrd=<ramdisk> command line
argument.
-config EFI_SECURE_BOOT
- bool "Enable EFI secure boot support"
- depends on EFI_LOADER && FIT_SIGNATURE
- select HASH
- select SHA256
- select RSA
- select RSA_VERIFY_WITH_PKEY
- select IMAGE_SIGN_INFO
- select ASYMMETRIC_KEY_TYPE
- select ASYMMETRIC_PUBLIC_KEY_SUBTYPE
- select X509_CERTIFICATE_PARSER
- select PKCS7_MESSAGE_PARSER
- select PKCS7_VERIFY
- select MSCODE_PARSER
- select EFI_SIGNATURE_SUPPORT
+config EFI_RISCV_BOOT_PROTOCOL
+ bool "RISCV_EFI_BOOT_PROTOCOL support"
+ default y
+ depends on RISCV
help
- Select this option to enable EFI secure boot support.
- Once SecureBoot mode is enforced, any EFI binary can run only if
- it is signed with a trusted key. To do that, you need to install,
- at least, PK, KEK and db.
+ The EFI_RISCV_BOOT_PROTOCOL is used to transfer the boot hart ID
+ to the next boot stage. It should be enabled as it is meant to
+ replace the transfer via the device-tree. The latter is not
+ possible on systems using ACPI.
-config EFI_SIGNATURE_SUPPORT
- bool
+endmenu
+
+menu "Misc options"
+config EFI_LOADER_BOUNCE_BUFFER
+ bool "EFI Applications use bounce buffers for DMA operations"
+ depends on ARM64
+ help
+ Some hardware does not support DMA to full 64bit addresses. For this
+ hardware we can create a bounce buffer so that payloads don't have to
+ worry about platform details.
+
+config EFI_GRUB_ARM32_WORKAROUND
+ bool "Workaround for GRUB on 32bit ARM"
+ default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
+ default y
+ depends on ARM && !ARM64
+ help
+ GRUB prior to version 2.04 requires U-Boot to disable caches. This
+ workaround currently is also needed on systems with caches that
+ cannot be managed via CP15.
config EFI_ESRT
bool "Enable the UEFI ESRT generation"
@@ -496,15 +521,26 @@
help
Enabling this option adds the EBBRv2.1 conformance entry to the ECPT UEFI table.
-config EFI_RISCV_BOOT_PROTOCOL
- bool "RISCV_EFI_BOOT_PROTOCOL support"
+config EFI_SCROLL_ON_CLEAR_SCREEN
+ bool "Avoid overwriting previous output on clear screen"
+ help
+ Instead of erasing the screen content when the console screen should
+ be cleared, emit blank new lines so that previous output is scrolled
+ out of sight rather than overwritten. On serial consoles this allows
+ to capture complete boot logs (except for interactive menus etc.)
+ and can ease debugging related issues.
+
+endmenu
+
+menu "EFI bootmanager"
+
+config EFI_BOOTMGR
+ bool "UEFI Boot Manager"
default y
- depends on RISCV
help
- The EFI_RISCV_BOOT_PROTOCOL is used to transfer the boot hart ID
- to the next boot stage. It should be enabled as it is meant to
- replace the transfer via the device-tree. The latter is not
- possible on systems using ACPI.
+ Select this option if you want to select the UEFI binary to be booted
+ via UEFI variables Boot####, BootOrder, and BootNext. You should also
+ normally enable CMD_BOOTEFI_BOOTMGR so that the command is available.
config EFI_HTTP_BOOT
bool "EFI HTTP Boot support"
@@ -514,5 +550,10 @@
help
Enabling this option adds EFI HTTP Boot support. It allows to
directly boot from network.
+endmenu
endif
+
+source "lib/efi/Kconfig"
+
+endmenu
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 589d399..a3aa2b8 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -380,14 +380,15 @@
}
/**
- * efi_bootmgr_release_uridp_resource() - cleanup uri device path resource
+ * efi_bootmgr_release_uridp() - cleanup uri device path resource
*
* @ctx: event context
* Return: status code
*/
-efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx)
+efi_status_t efi_bootmgr_release_uridp(struct uridp_context *ctx)
{
efi_status_t ret = EFI_SUCCESS;
+ efi_status_t ret2 = EFI_SUCCESS;
if (!ctx)
return ret;
@@ -407,32 +408,33 @@
/* cleanup for PE-COFF image */
if (ctx->mem_handle) {
- ret = efi_uninstall_multiple_protocol_interfaces(
- ctx->mem_handle, &efi_guid_device_path, ctx->loaded_dp,
- NULL);
- if (ret != EFI_SUCCESS)
+ ret2 = efi_uninstall_multiple_protocol_interfaces(ctx->mem_handle,
+ &efi_guid_device_path,
+ ctx->loaded_dp,
+ NULL);
+ if (ret2 != EFI_SUCCESS)
log_err("Uninstall device_path protocol failed\n");
}
efi_free_pool(ctx->loaded_dp);
free(ctx);
- return ret;
+ return ret == EFI_SUCCESS ? ret2 : ret;
}
/**
- * efi_bootmgr_image_return_notify() - return to efibootmgr callback
+ * efi_bootmgr_http_return() - return to efibootmgr callback
*
* @event: the event for which this notification function is registered
* @context: event context
*/
-static void EFIAPI efi_bootmgr_image_return_notify(struct efi_event *event,
- void *context)
+static void EFIAPI efi_bootmgr_http_return(struct efi_event *event,
+ void *context)
{
efi_status_t ret;
EFI_ENTRY("%p, %p", event, context);
- ret = efi_bootmgr_release_uridp_resource(context);
+ ret = efi_bootmgr_release_uridp(context);
EFI_EXIT(ret);
}
@@ -533,7 +535,7 @@
/* create event for cleanup when the image returns or error occurs */
ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
- efi_bootmgr_image_return_notify, ctx,
+ efi_bootmgr_http_return, ctx,
&efi_guid_event_group_return_to_efibootmgr,
&event);
if (ret != EFI_SUCCESS) {
@@ -544,7 +546,7 @@
return ret;
err:
- efi_bootmgr_release_uridp_resource(ctx);
+ efi_bootmgr_release_uridp(ctx);
return ret;
}
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 635088f..f8a4a7c 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -20,6 +20,7 @@
#include <sort.h>
#include <sysreset.h>
#include <asm/global_data.h>
+#include <u-boot/uuid.h>
#include <crypto/pkcs7.h>
#include <crypto/pkcs7_parser.h>
@@ -563,9 +564,14 @@
bool fw_accept_os;
if (IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) {
- if (fwu_empty_capsule_checks_pass() &&
- fwu_empty_capsule(capsule_data))
- return fwu_empty_capsule_process(capsule_data);
+ if (fwu_empty_capsule(capsule_data)) {
+ if (fwu_empty_capsule_checks_pass()) {
+ return fwu_empty_capsule_process(capsule_data);
+ } else {
+ log_err("FWU empty capsule checks failed. Cannot start update\n");
+ return EFI_INVALID_PARAMETER;
+ }
+ }
if (!fwu_update_checks_pass()) {
log_err("FWU checks failed. Cannot start update\n");
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index c944c10..9d9f786 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -100,7 +100,7 @@
}
/**
- * Receive and parse a reply from the terminal.
+ * term_read_reply() - receive and parse a reply from the terminal
*
* @n: array of return values
* @num: number of return values expected
@@ -181,7 +181,7 @@
}
pos = buf;
utf16_utf8_strcpy(&pos, string);
- fputs(stdout, buf);
+ puts(buf);
free(buf);
/*
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 0f68459..9de3b95 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -17,7 +17,7 @@
#include <nvme.h>
#include <efi_loader.h>
#include <part.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <asm-generic/unaligned.h>
#include <linux/compat.h> /* U16_MAX */
diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c
index 9886e68..9d01780 100644
--- a/lib/efi_loader/efi_dt_fixup.c
+++ b/lib/efi_loader/efi_dt_fixup.c
@@ -172,7 +172,7 @@
}
fdt_set_totalsize(dtb, *buffer_size);
- if (image_setup_libfdt(&img, dtb, NULL)) {
+ if (image_setup_libfdt(&img, dtb, false)) {
log_err("failed to process device tree\n");
ret = EFI_INVALID_PARAMETER;
goto out;
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 222001d..c92d8cc 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -295,7 +295,7 @@
}
/**
- * efi_file_open_()
+ * efi_file_open() - open file synchronously
*
* This function implements the Open service of the File Protocol.
* See the UEFI spec for details.
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index ba5aba0..6650c2b 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -246,6 +246,55 @@
}
/**
+ * efi_gen_capsule_guids - generate GUIDs for the images
+ *
+ * Generate the image_type_id for each image in the update_info.images array
+ * using the first compatible from the device tree and a salt
+ * UUID defined at build time.
+ *
+ * Returns: status code
+ */
+static efi_status_t efi_gen_capsule_guids(void)
+{
+ int ret, i;
+ struct uuid namespace;
+ const char *compatible; /* Full array including null bytes */
+ struct efi_fw_image *fw_array;
+
+ fw_array = update_info.images;
+ /* Check if we need to run (there are images and we didn't already generate their IDs) */
+ if (!update_info.num_images ||
+ memchr_inv(&fw_array[0].image_type_id, 0, sizeof(fw_array[0].image_type_id)))
+ return EFI_SUCCESS;
+
+ ret = uuid_str_to_bin(CONFIG_EFI_CAPSULE_NAMESPACE_GUID,
+ (unsigned char *)&namespace, UUID_STR_FORMAT_GUID);
+ if (ret) {
+ log_debug("%s: EFI_CAPSULE_NAMESPACE_GUID is invalid: %d\n", __func__, ret);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ compatible = ofnode_read_string(ofnode_root(), "compatible");
+ if (!compatible) {
+ log_debug("%s: model or compatible not defined\n", __func__);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ for (i = 0; i < update_info.num_images; i++) {
+ gen_v5_guid(&namespace,
+ &fw_array[i].image_type_id,
+ compatible, strlen(compatible),
+ fw_array[i].fw_name, u16_strlen(fw_array[i].fw_name) * sizeof(uint16_t),
+ NULL);
+
+ log_debug("Image %ls UUID %pUl\n", fw_array[i].fw_name,
+ &fw_array[i].image_type_id);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
* efi_fill_image_desc_array - populate image descriptor array
* @image_info_size: Size of @image_info
* @image_info: Image information
@@ -272,7 +321,7 @@
{
size_t total_size;
struct efi_fw_image *fw_array;
- int i;
+ int i, ret;
total_size = sizeof(*image_info) * update_info.num_images;
@@ -283,6 +332,10 @@
}
*image_info_size = total_size;
+ ret = efi_gen_capsule_guids();
+ if (ret != EFI_SUCCESS)
+ return ret;
+
fw_array = update_info.images;
*descriptor_count = update_info.num_images;
*descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION;
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 916f43d..96f8476 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -514,7 +514,7 @@
return EFI_OUT_OF_RESOURCES;
}
- if (image_setup_libfdt(&img, fdt, NULL)) {
+ if (image_setup_libfdt(&img, fdt, false)) {
log_err("ERROR: failed to process device tree\n");
return EFI_LOAD_ERROR;
}
diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c
index 9bad7ed..4734f95 100644
--- a/lib/efi_loader/efi_rng.c
+++ b/lib/efi_loader/efi_rng.c
@@ -91,7 +91,7 @@
}
/**
- * rng_getrng() - get random value
+ * getrng() - get random value
*
* This function implement the GetRng() service of the EFI random number
* generator protocol. See the UEFI spec for details.
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index 627bb91..d48700a 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -266,7 +266,7 @@
}
/**
- * efi_fat_to_str() - convert a utf-16 string to legal characters for a FAT
+ * efi_str_to_fat() - convert a utf-16 string to legal characters for a FAT
* file name in an OEM code page
*
* @this: unicode collation protocol instance
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index e888c52..f3533f4 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -16,7 +16,7 @@
#include <malloc.h>
#include <rtc.h>
#include <search.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <crypto/pkcs7_parser.h>
#include <linux/compat.h>
#include <u-boot/crc.h>
diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
index bd72822..586177d 100644
--- a/lib/efi_loader/helloworld.c
+++ b/lib/efi_loader/helloworld.c
@@ -2,6 +2,9 @@
/*
* Hello world EFI application
*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
* Copyright 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
*
* This test program is used to test the invocation of an EFI application.
diff --git a/lib/elf.c b/lib/elf.c
index dc13935..e767a42a 100644
--- a/lib/elf.c
+++ b/lib/elf.c
@@ -86,10 +86,14 @@
phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff);
/* Load each program header */
- for (i = 0; i < ehdr->e_phnum; ++i) {
+ for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) {
void *dst = (void *)(ulong)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
+ /* Only load PT_LOAD program header */
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
debug("Loading phdr %i to 0x%p (%lu bytes)\n",
i, dst, (ulong)phdr->p_filesz);
if (phdr->p_filesz)
@@ -99,7 +103,6 @@
phdr->p_memsz - phdr->p_filesz);
flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
roundup(phdr->p_memsz, ARCH_DMA_MINALIGN));
- ++phdr;
}
if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
@@ -201,10 +204,14 @@
phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
/* Load each program header */
- for (i = 0; i < ehdr->e_phnum; ++i) {
+ for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) {
void *dst = (void *)(uintptr_t)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
+ /* Only load PT_LOAD program header */
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
@@ -214,7 +221,6 @@
phdr->p_memsz - phdr->p_filesz);
flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
roundup(phdr->p_memsz, ARCH_DMA_MINALIGN));
- ++phdr;
}
return ehdr->e_entry;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 6865f78..5edc8dd 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1685,6 +1685,7 @@
gd->fdt_src = FDTSRC_BLOBLIST;
log_debug("Devicetree is in bloblist at %p\n",
gd->fdt_blob);
+ ret = 0;
} else {
log_debug("No FDT found in bloblist\n");
ret = -ENOENT;
diff --git a/lib/fwu_updates/Kconfig b/lib/fwu_updates/Kconfig
index 51b7fbb..a722107 100644
--- a/lib/fwu_updates/Kconfig
+++ b/lib/fwu_updates/Kconfig
@@ -40,6 +40,7 @@
config FWU_MDATA_V2
bool "Enable support FWU Metadata version 2"
+ depends on !FWU_MDATA_V1
help
The FWU specification supports two versions of the
metadata structure. This option enables support for FWU
diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c
index c7fc898..7f085a0 100644
--- a/lib/fwu_updates/fwu.c
+++ b/lib/fwu_updates/fwu.c
@@ -28,6 +28,31 @@
IMAGE_ACCEPT_CLEAR,
};
+/**
+ * fwu_bank_accepted() - Has the bank been accepted
+ * @data: Version agnostic FWU metadata information
+ * @bank: Update bank to check
+ *
+ * Check in the given bank if all the images have been accepted.
+ *
+ * Return: true if all images accepted, false otherwise
+ */
+bool fwu_bank_accepted(struct fwu_data *data, uint32_t bank)
+{
+ u32 i;
+ struct fwu_image_entry *img_entry;
+ struct fwu_image_bank_info *img_bank_info;
+
+ img_entry = &data->fwu_images[0];
+ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) {
+ img_bank_info = &img_entry[i].img_bank_info[bank];
+ if (!img_bank_info->accepted)
+ return false;
+ }
+
+ return true;
+}
+
static int trial_counter_update(u16 *trial_state_ctr)
{
bool delete;
@@ -88,6 +113,8 @@
ret = fwu_revert_boot_index();
if (ret)
log_err("Unable to revert active_index\n");
+
+ trial_counter_update(NULL);
ret = 1;
} else {
log_info("Trial State count: attempt %d out of %d\n",
@@ -737,8 +764,8 @@
return 0;
in_trial = in_trial_state();
- if (!in_trial || (ret = fwu_trial_count_update()) > 0)
- ret = trial_counter_update(NULL);
+
+ ret = in_trial ? fwu_trial_count_update() : trial_counter_update(NULL);
if (!ret)
boottime_check = 1;
diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c
index ccaba3f..5547230 100644
--- a/lib/fwu_updates/fwu_mtd.c
+++ b/lib/fwu_updates/fwu_mtd.c
@@ -10,7 +10,7 @@
#include <log.h>
#include <malloc.h>
#include <mtd.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <stdio.h>
#include <dm/ofnode.h>
@@ -60,10 +60,7 @@
if (ret)
return -ENOENT;
- nalt = 0;
- list_for_each_entry(dfu, &dfu_list, list)
- nalt++;
-
+ nalt = list_count_nodes(&dfu_list);
if (!nalt) {
log_warning("No entities in dfu_alt_info\n");
dfu_free_entities();
diff --git a/lib/fwu_updates/fwu_v1.c b/lib/fwu_updates/fwu_v1.c
index efb8d51..c311a88 100644
--- a/lib/fwu_updates/fwu_v1.c
+++ b/lib/fwu_updates/fwu_v1.c
@@ -52,11 +52,14 @@
memcpy(dst_img_info, src_img_info, image_info_size);
}
-static int fwu_trial_state_update(bool trial_state)
+static int fwu_trial_state_update(bool trial_state, uint32_t bank)
{
int ret;
struct fwu_data *data = fwu_get_data();
+ if (!trial_state && !fwu_bank_accepted(data, bank))
+ return 0;
+
if (trial_state) {
ret = fwu_trial_state_ctr_start();
if (ret)
@@ -112,9 +115,9 @@
* Return: 0 if OK, -ve on error
*/
int fwu_state_machine_updates(bool trial_state,
- __maybe_unused uint32_t update_index)
+ uint32_t update_index)
{
- return fwu_trial_state_update(trial_state);
+ return fwu_trial_state_update(trial_state, update_index);
}
/**
@@ -146,6 +149,7 @@
{
int ret;
uint32_t mdata_size;
+ struct fwu_mdata mdata = {0};
fwu_get_mdata_size(&mdata_size);
@@ -157,10 +161,16 @@
* Now read the entire structure, both copies, and
* validate that the copies.
*/
- ret = fwu_get_mdata(NULL);
+ ret = fwu_get_mdata(&mdata);
if (ret)
return ret;
+ if (mdata.version != 0x1) {
+ log_err("FWU metadata version %u. Expected value of %u\n",
+ mdata.version, FWU_MDATA_VERSION);
+ return -EINVAL;
+ }
+
fwu_data_init();
return 0;
diff --git a/lib/fwu_updates/fwu_v2.c b/lib/fwu_updates/fwu_v2.c
index 108bc9b..ce46904 100644
--- a/lib/fwu_updates/fwu_v2.c
+++ b/lib/fwu_updates/fwu_v2.c
@@ -10,6 +10,9 @@
#include <linux/types.h>
#define FWU_MDATA_VERSION 0x2U
+#define FWU_IMG_DESC_OFFSET 0x20U
+
+static struct fwu_mdata g_mdata;
static inline struct fwu_fw_store_desc *fwu_get_fw_desc(struct fwu_mdata *mdata)
{
@@ -58,24 +61,6 @@
struct fwu_data *data = fwu_get_data();
struct fwu_mdata *mdata = data->fwu_mdata;
- if (mdata->version != FWU_MDATA_VERSION) {
- log_err("FWU metadata version %u. Expected value of %u\n",
- mdata->version, FWU_MDATA_VERSION);
- return -EINVAL;
- }
-
- if (!mdata->desc_offset) {
- log_err("No image information provided with the Metadata. ");
- log_err("Image information expected in the metadata\n");
- return -EINVAL;
- }
-
- if (mdata->desc_offset != 0x20) {
- log_err("Descriptor Offset(0x%x) in the FWU Metadata not equal to 0x20\n",
- mdata->desc_offset);
- return -EINVAL;
- }
-
num_banks = fwu_get_fw_desc(mdata)->num_banks;
num_images = fwu_get_fw_desc(mdata)->num_images;
@@ -100,6 +85,9 @@
struct fwu_data *data = fwu_get_data();
struct fwu_mdata *mdata = data->fwu_mdata;
+ if (!trial_state && !fwu_bank_accepted(data, bank))
+ return 0;
+
mdata->bank_state[bank] = data->bank_state[bank] = trial_state ?
FWU_BANK_VALID : FWU_BANK_ACCEPTED;
@@ -127,6 +115,35 @@
return 0;
}
+static bool fwu_get_mdata_mandatory(uint part)
+{
+ int ret = 0;
+ struct udevice *fwu_dev = fwu_get_dev();
+
+ memset(&g_mdata, 0, sizeof(struct fwu_mdata));
+
+ ret = fwu_read_mdata(fwu_dev, &g_mdata,
+ part == PRIMARY_PART ? true : false,
+ sizeof(struct fwu_mdata));
+ if (ret)
+ return false;
+
+ if (g_mdata.version != FWU_MDATA_VERSION) {
+ log_err("FWU partition %u has metadata version %u. Expected value of %u\n",
+ part, g_mdata.version, FWU_MDATA_VERSION);
+ return false;
+ }
+
+ if (g_mdata.desc_offset != FWU_IMG_DESC_OFFSET) {
+ log_err("Descriptor Offset(0x%x) in the FWU Metadata partition %u not equal to 0x20\n",
+ g_mdata.desc_offset, part);
+ log_err("Image information expected in the metadata\n");
+ return false;
+ }
+
+ return true;
+}
+
/**
* fwu_populate_mdata_image_info() - Populate the image information
* of the metadata
@@ -187,24 +204,14 @@
*/
int fwu_get_mdata_size(uint32_t *mdata_size)
{
- int ret = 0;
- struct fwu_mdata mdata = { 0 };
struct fwu_data *data = fwu_get_data();
- struct udevice *fwu_dev = fwu_get_dev();
if (data->metadata_size) {
*mdata_size = data->metadata_size;
return 0;
}
- ret = fwu_read_mdata(fwu_dev, &mdata, 1,
- sizeof(struct fwu_mdata));
- if (ret) {
- log_err("FWU metadata read failed\n");
- return ret;
- }
-
- *mdata_size = mdata.metadata_size;
+ *mdata_size = g_mdata.metadata_size;
if (!*mdata_size)
return -EINVAL;
@@ -224,21 +231,23 @@
int fwu_init(void)
{
int ret;
- struct fwu_mdata mdata = { 0 };
- struct udevice *fwu_dev = fwu_get_dev();
/*
* First we read only the top level structure
* and get the size of the complete structure.
+ * Try reading the first partition first, if
+ * that does not work, try the secondary
+ * partition. The idea is, if one of the
+ * partitions is corrupted, it should be restored
+ * from the intact partition.
*/
- ret = fwu_read_mdata(fwu_dev, &mdata, 1,
- sizeof(struct fwu_mdata));
- if (ret) {
+ if (!fwu_get_mdata_mandatory(PRIMARY_PART) &&
+ !fwu_get_mdata_mandatory(SECONDARY_PART)) {
log_err("FWU metadata read failed\n");
- return ret;
+ return -1;
}
- ret = fwu_mdata_copies_allocate(mdata.metadata_size);
+ ret = fwu_mdata_copies_allocate(g_mdata.metadata_size);
if (ret)
return ret;
diff --git a/lib/lmb.c b/lib/lmb.c
index 44f9820..3ed570f 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -6,50 +6,72 @@
* Copyright (C) 2001 Peter Bergner.
*/
+#include <alist.h>
#include <efi_loader.h>
#include <image.h>
#include <mapmem.h>
#include <lmb.h>
#include <log.h>
#include <malloc.h>
+#include <spl.h>
#include <asm/global_data.h>
#include <asm/sections.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
#define LMB_ALLOC_ANYWHERE 0
+#define LMB_ALIST_INITIAL_SIZE 4
-static void lmb_dump_region(struct lmb_region *rgn, char *name)
+static struct lmb lmb;
+
+static void lmb_print_region_flags(enum lmb_flags flags)
+{
+ u64 bitpos;
+ const char *flag_str[] = { "none", "no-map", "no-overwrite" };
+
+ do {
+ bitpos = flags ? fls(flags) - 1 : 0;
+ printf("%s", flag_str[bitpos]);
+ flags &= ~(1ull << bitpos);
+ puts(flags ? ", " : "\n");
+ } while (flags);
+}
+
+static void lmb_dump_region(struct alist *lmb_rgn_lst, char *name)
{
+ struct lmb_region *rgn = lmb_rgn_lst->data;
unsigned long long base, size, end;
enum lmb_flags flags;
int i;
- printf(" %s.cnt = 0x%lx / max = 0x%lx\n", name, rgn->cnt, rgn->max);
+ printf(" %s.count = 0x%x\n", name, lmb_rgn_lst->count);
- for (i = 0; i < rgn->cnt; i++) {
- base = rgn->region[i].base;
- size = rgn->region[i].size;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ base = rgn[i].base;
+ size = rgn[i].size;
end = base + size - 1;
- flags = rgn->region[i].flags;
+ flags = rgn[i].flags;
- printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n",
- name, i, base, end, size, flags);
+ printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
+ name, i, base, end, size);
+ lmb_print_region_flags(flags);
}
}
-void lmb_dump_all_force(struct lmb *lmb)
+void lmb_dump_all_force(void)
{
printf("lmb_dump_all:\n");
- lmb_dump_region(&lmb->memory, "memory");
- lmb_dump_region(&lmb->reserved, "reserved");
+ lmb_dump_region(&lmb.free_mem, "memory");
+ lmb_dump_region(&lmb.used_mem, "reserved");
}
-void lmb_dump_all(struct lmb *lmb)
+void lmb_dump_all(void)
{
#ifdef DEBUG
- lmb_dump_all_force(lmb);
+ lmb_dump_all_force();
#endif
}
@@ -73,111 +95,71 @@
return 0;
}
-static long lmb_regions_overlap(struct lmb_region *rgn, unsigned long r1,
+static long lmb_regions_overlap(struct alist *lmb_rgn_lst, unsigned long r1,
unsigned long r2)
{
- phys_addr_t base1 = rgn->region[r1].base;
- phys_size_t size1 = rgn->region[r1].size;
- phys_addr_t base2 = rgn->region[r2].base;
- phys_size_t size2 = rgn->region[r2].size;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
+
+ phys_addr_t base1 = rgn[r1].base;
+ phys_size_t size1 = rgn[r1].size;
+ phys_addr_t base2 = rgn[r2].base;
+ phys_size_t size2 = rgn[r2].size;
return lmb_addrs_overlap(base1, size1, base2, size2);
}
-static long lmb_regions_adjacent(struct lmb_region *rgn, unsigned long r1,
+
+static long lmb_regions_adjacent(struct alist *lmb_rgn_lst, unsigned long r1,
unsigned long r2)
{
- phys_addr_t base1 = rgn->region[r1].base;
- phys_size_t size1 = rgn->region[r1].size;
- phys_addr_t base2 = rgn->region[r2].base;
- phys_size_t size2 = rgn->region[r2].size;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
+
+ phys_addr_t base1 = rgn[r1].base;
+ phys_size_t size1 = rgn[r1].size;
+ phys_addr_t base2 = rgn[r2].base;
+ phys_size_t size2 = rgn[r2].size;
return lmb_addrs_adjacent(base1, size1, base2, size2);
}
-static void lmb_remove_region(struct lmb_region *rgn, unsigned long r)
+static void lmb_remove_region(struct alist *lmb_rgn_lst, unsigned long r)
{
unsigned long i;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
- for (i = r; i < rgn->cnt - 1; i++) {
- rgn->region[i].base = rgn->region[i + 1].base;
- rgn->region[i].size = rgn->region[i + 1].size;
- rgn->region[i].flags = rgn->region[i + 1].flags;
+ for (i = r; i < lmb_rgn_lst->count - 1; i++) {
+ rgn[i].base = rgn[i + 1].base;
+ rgn[i].size = rgn[i + 1].size;
+ rgn[i].flags = rgn[i + 1].flags;
}
- rgn->cnt--;
+ lmb_rgn_lst->count--;
}
/* Assumption: base addr of region 1 < base addr of region 2 */
-static void lmb_coalesce_regions(struct lmb_region *rgn, unsigned long r1,
+static void lmb_coalesce_regions(struct alist *lmb_rgn_lst, unsigned long r1,
unsigned long r2)
{
- rgn->region[r1].size += rgn->region[r2].size;
- lmb_remove_region(rgn, r2);
+ struct lmb_region *rgn = lmb_rgn_lst->data;
+
+ rgn[r1].size += rgn[r2].size;
+ lmb_remove_region(lmb_rgn_lst, r2);
}
/*Assumption : base addr of region 1 < base addr of region 2*/
-static void lmb_fix_over_lap_regions(struct lmb_region *rgn, unsigned long r1,
- unsigned long r2)
+static void lmb_fix_over_lap_regions(struct alist *lmb_rgn_lst,
+ unsigned long r1, unsigned long r2)
{
- phys_addr_t base1 = rgn->region[r1].base;
- phys_size_t size1 = rgn->region[r1].size;
- phys_addr_t base2 = rgn->region[r2].base;
- phys_size_t size2 = rgn->region[r2].size;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
+
+ phys_addr_t base1 = rgn[r1].base;
+ phys_size_t size1 = rgn[r1].size;
+ phys_addr_t base2 = rgn[r2].base;
+ phys_size_t size2 = rgn[r2].size;
if (base1 + size1 > base2 + size2) {
printf("This will not be a case any time\n");
return;
}
- rgn->region[r1].size = base2 + size2 - base1;
- lmb_remove_region(rgn, r2);
-}
-
-void lmb_init(struct lmb *lmb)
-{
-#if IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
- lmb->memory.max = CONFIG_LMB_MAX_REGIONS;
- lmb->reserved.max = CONFIG_LMB_MAX_REGIONS;
-#else
- lmb->memory.max = CONFIG_LMB_MEMORY_REGIONS;
- lmb->reserved.max = CONFIG_LMB_RESERVED_REGIONS;
- lmb->memory.region = lmb->memory_regions;
- lmb->reserved.region = lmb->reserved_regions;
-#endif
- lmb->memory.cnt = 0;
- lmb->reserved.cnt = 0;
-}
-
-void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align)
-{
- ulong bank_end;
- int bank;
-
- /*
- * Reserve memory from aligned address below the bottom of U-Boot stack
- * until end of U-Boot area using LMB to prevent U-Boot from overwriting
- * that memory.
- */
- debug("## Current stack ends at 0x%08lx ", sp);
-
- /* adjust sp by 4K to be safe */
- sp -= align;
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
- if (!gd->bd->bi_dram[bank].size ||
- sp < gd->bd->bi_dram[bank].start)
- continue;
- /* Watch out for RAM at end of address space! */
- bank_end = gd->bd->bi_dram[bank].start +
- gd->bd->bi_dram[bank].size - 1;
- if (sp > bank_end)
- continue;
- if (bank_end > end)
- bank_end = end - 1;
-
- lmb_reserve(lmb, sp, bank_end - sp + 1);
-
- if (gd->flags & GD_FLG_SKIP_RELOC)
- lmb_reserve(lmb, (phys_addr_t)(uintptr_t)_start, gd->mon_len);
-
- break;
- }
+ rgn[r1].size = base2 + size2 - base1;
+ lmb_remove_region(lmb_rgn_lst, r2);
}
/**
@@ -186,10 +168,9 @@
* Add reservations for all EFI memory areas that are not
* EFI_CONVENTIONAL_MEMORY.
*
- * @lmb: lmb environment
* Return: 0 on success, 1 on failure
*/
-static __maybe_unused int efi_lmb_reserve(struct lmb *lmb)
+static __maybe_unused int efi_lmb_reserve(void)
{
struct efi_mem_desc *memmap = NULL, *map;
efi_uintn_t i, map_size = 0;
@@ -201,8 +182,7 @@
for (i = 0, map = memmap; i < map_size / sizeof(*map); ++map, ++i) {
if (map->type != EFI_CONVENTIONAL_MEMORY) {
- lmb_reserve_flags(lmb,
- map_to_sysmem((void *)(uintptr_t)
+ lmb_reserve_flags(map_to_sysmem((void *)(uintptr_t)
map->physical_start),
map->num_pages * EFI_PAGE_SIZE,
map->type == EFI_RESERVED_MEMORY_TYPE
@@ -214,64 +194,199 @@
return 0;
}
+static void lmb_reserve_uboot_region(void)
+{
+ int bank;
+ ulong end, bank_end;
+ phys_addr_t rsv_start;
+
+ rsv_start = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ end = gd->ram_top;
+
+ /*
+ * Reserve memory from aligned address below the bottom of U-Boot stack
+ * until end of RAM area to prevent LMB from overwriting that memory.
+ */
+ debug("## Current stack ends at 0x%08lx ", (ulong)rsv_start);
+
+ /* adjust sp by 16K to be safe */
+ rsv_start -= SZ_16K;
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (!gd->bd->bi_dram[bank].size ||
+ rsv_start < gd->bd->bi_dram[bank].start)
+ continue;
+ /* Watch out for RAM at end of address space! */
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size - 1;
+ if (rsv_start > bank_end)
+ continue;
+ if (bank_end > end)
+ bank_end = end - 1;
+
+ lmb_reserve_flags(rsv_start, bank_end - rsv_start + 1,
+ LMB_NOOVERWRITE);
+
+ if (gd->flags & GD_FLG_SKIP_RELOC)
+ lmb_reserve_flags((phys_addr_t)(uintptr_t)_start,
+ gd->mon_len, LMB_NOOVERWRITE);
+
+ break;
+ }
+}
+
-static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
+static void lmb_reserve_common(void *fdt_blob)
{
- arch_lmb_reserve(lmb);
- board_lmb_reserve(lmb);
+ lmb_reserve_uboot_region();
if (CONFIG_IS_ENABLED(OF_LIBFDT) && fdt_blob)
- boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
+ boot_fdt_add_mem_rsv_regions(fdt_blob);
if (CONFIG_IS_ENABLED(EFI_LOADER))
- efi_lmb_reserve(lmb);
+ efi_lmb_reserve();
+}
+
+static __maybe_unused void lmb_reserve_common_spl(void)
+{
+ phys_addr_t rsv_start;
+ phys_size_t rsv_size;
+
+ /*
+ * Assume a SPL stack of 16KB. This must be
+ * more than enough for the SPL stage.
+ */
+ if (IS_ENABLED(CONFIG_SPL_STACK_R_ADDR)) {
+ rsv_start = gd->start_addr_sp - 16384;
+ rsv_size = 16384;
+ lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) {
+ /* Reserve the bss region */
+ rsv_start = (phys_addr_t)(uintptr_t)__bss_start;
+ rsv_size = (phys_addr_t)(uintptr_t)__bss_end -
+ (phys_addr_t)(uintptr_t)__bss_start;
+ lmb_reserve_flags(rsv_start, rsv_size, LMB_NOOVERWRITE);
+ }
}
-/* Initialize the struct, add memory and call arch/board reserve functions */
-void lmb_init_and_reserve(struct lmb *lmb, struct bd_info *bd, void *fdt_blob)
+/**
+ * lmb_add_memory() - Add memory range for LMB allocations
+ *
+ * Add the entire available memory range to the pool of memory that
+ * can be used by the LMB module for allocations.
+ *
+ * Return: None
+ */
+void lmb_add_memory(void)
{
int i;
+ phys_size_t size;
+ phys_addr_t rgn_top;
+ u64 ram_top = gd->ram_top;
+ struct bd_info *bd = gd->bd;
- lmb_init(lmb);
+ /* Assume a 4GB ram_top if not defined */
+ if (!ram_top)
+ ram_top = 0x100000000ULL;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- if (bd->bi_dram[i].size) {
- lmb_add(lmb, bd->bi_dram[i].start,
- bd->bi_dram[i].size);
+ size = bd->bi_dram[i].size;
+ if (size) {
+ if (bd->bi_dram[i].start > ram_top)
+ continue;
+
+ rgn_top = bd->bi_dram[i].start +
+ bd->bi_dram[i].size;
+
+ if (rgn_top > ram_top)
+ size -= rgn_top - ram_top;
+
+ lmb_add(bd->bi_dram[i].start, size);
}
}
-
- lmb_reserve_common(lmb, fdt_blob);
}
-/* Initialize the struct, add memory and call arch/board reserve functions */
-void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, void *fdt_blob)
+static long lmb_resize_regions(struct alist *lmb_rgn_lst,
+ unsigned long idx_start,
+ phys_addr_t base, phys_size_t size)
{
- lmb_init(lmb);
- lmb_add(lmb, base, size);
- lmb_reserve_common(lmb, fdt_blob);
+ phys_size_t rgnsize;
+ unsigned long rgn_cnt, idx, idx_end;
+ phys_addr_t rgnbase, rgnend;
+ phys_addr_t mergebase, mergeend;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
+
+ rgn_cnt = 0;
+ idx = idx_start;
+ idx_end = idx_start;
+
+ /*
+ * First thing to do is to identify how many regions
+ * the requested region overlaps.
+ * If the flags match, combine all these overlapping
+ * regions into a single region, and remove the merged
+ * regions.
+ */
+ while (idx <= lmb_rgn_lst->count - 1) {
+ rgnbase = rgn[idx].base;
+ rgnsize = rgn[idx].size;
+
+ if (lmb_addrs_overlap(base, size, rgnbase,
+ rgnsize)) {
+ if (rgn[idx].flags != LMB_NONE)
+ return -1;
+ rgn_cnt++;
+ idx_end = idx;
+ }
+ idx++;
+ }
+
+ /* The merged region's base and size */
+ rgnbase = rgn[idx_start].base;
+ mergebase = min(base, rgnbase);
+ rgnend = rgn[idx_end].base + rgn[idx_end].size;
+ mergeend = max(rgnend, (base + size));
+
+ rgn[idx_start].base = mergebase;
+ rgn[idx_start].size = mergeend - mergebase;
+
+ /* Now remove the merged regions */
+ while (--rgn_cnt)
+ lmb_remove_region(lmb_rgn_lst, idx_start + 1);
+
+ return 0;
}
-/* This routine called with relocation disabled. */
-static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base,
+/**
+ * lmb_add_region_flags() - Add an lmb region to the given list
+ * @lmb_rgn_lst: LMB list to which region is to be added(free/used)
+ * @base: Start address of the region
+ * @size: Size of the region to be added
+ * @flags: Attributes of the LMB region
+ *
+ * Add a region of memory to the list. If the region does not exist, add
+ * it to the list. Depending on the attributes of the region to be added,
+ * the function might resize an already existing region or coalesce two
+ * adjacent regions.
+ *
+ *
+ * Returns: 0 if the region addition successful, -1 on failure
+ */
+static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base,
phys_size_t size, enum lmb_flags flags)
{
unsigned long coalesced = 0;
- long adjacent, i;
+ long ret, i;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
- if (rgn->cnt == 0) {
- rgn->region[0].base = base;
- rgn->region[0].size = size;
- rgn->region[0].flags = flags;
- rgn->cnt = 1;
- return 0;
- }
+ if (alist_err(lmb_rgn_lst))
+ return -1;
/* First try and coalesce this LMB with another. */
- for (i = 0; i < rgn->cnt; i++) {
- phys_addr_t rgnbase = rgn->region[i].base;
- phys_size_t rgnsize = rgn->region[i].size;
- phys_size_t rgnflags = rgn->region[i].flags;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ phys_addr_t rgnbase = rgn[i].base;
+ phys_size_t rgnsize = rgn[i].size;
+ phys_size_t rgnflags = rgn[i].flags;
phys_addr_t end = base + size - 1;
phys_addr_t rgnend = rgnbase + rgnsize - 1;
if (rgnbase <= base && end <= rgnend) {
@@ -282,119 +397,127 @@
return -1; /* regions with new flags */
}
- adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
- if (adjacent > 0) {
+ ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
+ if (ret > 0) {
if (flags != rgnflags)
break;
- rgn->region[i].base -= size;
- rgn->region[i].size += size;
+ rgn[i].base -= size;
+ rgn[i].size += size;
coalesced++;
break;
- } else if (adjacent < 0) {
+ } else if (ret < 0) {
if (flags != rgnflags)
break;
- rgn->region[i].size += size;
+ rgn[i].size += size;
coalesced++;
break;
} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
- /* regions overlap */
- return -1;
+ if (flags == LMB_NONE) {
+ ret = lmb_resize_regions(lmb_rgn_lst, i, base,
+ size);
+ if (ret < 0)
+ return -1;
+
+ coalesced++;
+ break;
+ } else {
+ return -1;
+ }
}
}
- if (i < rgn->cnt - 1 && rgn->region[i].flags == rgn->region[i + 1].flags) {
- if (lmb_regions_adjacent(rgn, i, i + 1)) {
- lmb_coalesce_regions(rgn, i, i + 1);
- coalesced++;
- } else if (lmb_regions_overlap(rgn, i, i + 1)) {
- /* fix overlapping area */
- lmb_fix_over_lap_regions(rgn, i, i + 1);
- coalesced++;
+ if (lmb_rgn_lst->count && i < lmb_rgn_lst->count - 1) {
+ rgn = lmb_rgn_lst->data;
+ if (rgn[i].flags == rgn[i + 1].flags) {
+ if (lmb_regions_adjacent(lmb_rgn_lst, i, i + 1)) {
+ lmb_coalesce_regions(lmb_rgn_lst, i, i + 1);
+ coalesced++;
+ } else if (lmb_regions_overlap(lmb_rgn_lst, i, i + 1)) {
+ /* fix overlapping area */
+ lmb_fix_over_lap_regions(lmb_rgn_lst, i, i + 1);
+ coalesced++;
+ }
}
}
if (coalesced)
return coalesced;
- if (rgn->cnt >= rgn->max)
+
+ if (alist_full(lmb_rgn_lst) &&
+ !alist_expand_by(lmb_rgn_lst, lmb_rgn_lst->alloc))
return -1;
+ rgn = lmb_rgn_lst->data;
/* Couldn't coalesce the LMB, so add it to the sorted table. */
- for (i = rgn->cnt-1; i >= 0; i--) {
- if (base < rgn->region[i].base) {
- rgn->region[i + 1].base = rgn->region[i].base;
- rgn->region[i + 1].size = rgn->region[i].size;
- rgn->region[i + 1].flags = rgn->region[i].flags;
+ for (i = lmb_rgn_lst->count; i >= 0; i--) {
+ if (i && base < rgn[i - 1].base) {
+ rgn[i] = rgn[i - 1];
} else {
- rgn->region[i + 1].base = base;
- rgn->region[i + 1].size = size;
- rgn->region[i + 1].flags = flags;
+ rgn[i].base = base;
+ rgn[i].size = size;
+ rgn[i].flags = flags;
break;
}
}
- if (base < rgn->region[0].base) {
- rgn->region[0].base = base;
- rgn->region[0].size = size;
- rgn->region[0].flags = flags;
- }
-
- rgn->cnt++;
+ lmb_rgn_lst->count++;
return 0;
}
-static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base,
+static long lmb_add_region(struct alist *lmb_rgn_lst, phys_addr_t base,
phys_size_t size)
{
- return lmb_add_region_flags(rgn, base, size, LMB_NONE);
+ return lmb_add_region_flags(lmb_rgn_lst, base, size, LMB_NONE);
}
/* This routine may be called with relocation disabled. */
-long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+long lmb_add(phys_addr_t base, phys_size_t size)
{
- struct lmb_region *_rgn = &(lmb->memory);
+ struct alist *lmb_rgn_lst = &lmb.free_mem;
- return lmb_add_region(_rgn, base, size);
+ return lmb_add_region(lmb_rgn_lst, base, size);
}
-long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+long lmb_free(phys_addr_t base, phys_size_t size)
{
- struct lmb_region *rgn = &(lmb->reserved);
+ struct lmb_region *rgn;
+ struct alist *lmb_rgn_lst = &lmb.used_mem;
phys_addr_t rgnbegin, rgnend;
phys_addr_t end = base + size - 1;
int i;
rgnbegin = rgnend = 0; /* supress gcc warnings */
-
+ rgn = lmb_rgn_lst->data;
/* Find the region where (base, size) belongs to */
- for (i = 0; i < rgn->cnt; i++) {
- rgnbegin = rgn->region[i].base;
- rgnend = rgnbegin + rgn->region[i].size - 1;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ rgnbegin = rgn[i].base;
+ rgnend = rgnbegin + rgn[i].size - 1;
if ((rgnbegin <= base) && (end <= rgnend))
break;
}
/* Didn't find the region */
- if (i == rgn->cnt)
+ if (i == lmb_rgn_lst->count)
return -1;
/* Check to see if we are removing entire region */
if ((rgnbegin == base) && (rgnend == end)) {
- lmb_remove_region(rgn, i);
+ lmb_remove_region(lmb_rgn_lst, i);
return 0;
}
/* Check to see if region is matching at the front */
if (rgnbegin == base) {
- rgn->region[i].base = end + 1;
- rgn->region[i].size -= size;
+ rgn[i].base = end + 1;
+ rgn[i].size -= size;
return 0;
}
/* Check to see if the region is matching at the end */
if (rgnend == end) {
- rgn->region[i].size -= size;
+ rgn[i].size -= size;
return 0;
}
@@ -402,71 +525,56 @@
* We need to split the entry - adjust the current one to the
* beginging of the hole and add the region after hole.
*/
- rgn->region[i].size = base - rgn->region[i].base;
- return lmb_add_region_flags(rgn, end + 1, rgnend - end,
- rgn->region[i].flags);
+ rgn[i].size = base - rgn[i].base;
+ return lmb_add_region_flags(lmb_rgn_lst, end + 1, rgnend - end,
+ rgn[i].flags);
}
-long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size,
- enum lmb_flags flags)
+long lmb_reserve_flags(phys_addr_t base, phys_size_t size, enum lmb_flags flags)
{
- struct lmb_region *_rgn = &(lmb->reserved);
+ struct alist *lmb_rgn_lst = &lmb.used_mem;
- return lmb_add_region_flags(_rgn, base, size, flags);
+ return lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
}
-long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+long lmb_reserve(phys_addr_t base, phys_size_t size)
{
- return lmb_reserve_flags(lmb, base, size, LMB_NONE);
+ return lmb_reserve_flags(base, size, LMB_NONE);
}
-static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
+static long lmb_overlaps_region(struct alist *lmb_rgn_lst, phys_addr_t base,
phys_size_t size)
{
unsigned long i;
+ struct lmb_region *rgn = lmb_rgn_lst->data;
- for (i = 0; i < rgn->cnt; i++) {
- phys_addr_t rgnbase = rgn->region[i].base;
- phys_size_t rgnsize = rgn->region[i].size;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ phys_addr_t rgnbase = rgn[i].base;
+ phys_size_t rgnsize = rgn[i].size;
if (lmb_addrs_overlap(base, size, rgnbase, rgnsize))
break;
}
- return (i < rgn->cnt) ? i : -1;
+ return (i < lmb_rgn_lst->count) ? i : -1;
}
-phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align)
-{
- return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE);
-}
-
-phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr)
-{
- phys_addr_t alloc;
-
- alloc = __lmb_alloc_base(lmb, size, align, max_addr);
-
- if (alloc == 0)
- printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
- (ulong)size, (ulong)max_addr);
-
- return alloc;
-}
-
static phys_addr_t lmb_align_down(phys_addr_t addr, phys_size_t size)
{
return addr & ~(size - 1);
}
-phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr)
+static phys_addr_t __lmb_alloc_base(phys_size_t size, ulong align,
+ phys_addr_t max_addr, enum lmb_flags flags)
{
long i, rgn;
phys_addr_t base = 0;
phys_addr_t res_base;
+ struct lmb_region *lmb_used = lmb.used_mem.data;
+ struct lmb_region *lmb_memory = lmb.free_mem.data;
- for (i = lmb->memory.cnt - 1; i >= 0; i--) {
- phys_addr_t lmbbase = lmb->memory.region[i].base;
- phys_size_t lmbsize = lmb->memory.region[i].size;
+ for (i = lmb.free_mem.count - 1; i >= 0; i--) {
+ phys_addr_t lmbbase = lmb_memory[i].base;
+ phys_size_t lmbsize = lmb_memory[i].size;
if (lmbsize < size)
continue;
@@ -482,15 +590,16 @@
continue;
while (base && lmbbase <= base) {
- rgn = lmb_overlaps_region(&lmb->reserved, base, size);
+ rgn = lmb_overlaps_region(&lmb.used_mem, base, size);
if (rgn < 0) {
/* This area isn't reserved, take it */
- if (lmb_add_region(&lmb->reserved, base,
- size) < 0)
+ if (lmb_add_region_flags(&lmb.used_mem, base,
+ size, flags) < 0)
return 0;
return base;
}
- res_base = lmb->reserved.region[rgn].base;
+
+ res_base = lmb_used[rgn].base;
if (res_base < size)
break;
base = lmb_align_down(res_base - size, align);
@@ -499,83 +608,177 @@
return 0;
}
-/*
- * Try to allocate a specific address range: must be in defined memory but not
- * reserved
- */
-phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+phys_addr_t lmb_alloc(phys_size_t size, ulong align)
+{
+ return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE);
+}
+
+phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr)
+{
+ phys_addr_t alloc;
+
+ alloc = __lmb_alloc_base(size, align, max_addr, LMB_NONE);
+
+ if (alloc == 0)
+ printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
+ (ulong)size, (ulong)max_addr);
+
+ return alloc;
+}
+
+static phys_addr_t __lmb_alloc_addr(phys_addr_t base, phys_size_t size,
+ enum lmb_flags flags)
{
long rgn;
+ struct lmb_region *lmb_memory = lmb.free_mem.data;
/* Check if the requested address is in one of the memory regions */
- rgn = lmb_overlaps_region(&lmb->memory, base, size);
+ rgn = lmb_overlaps_region(&lmb.free_mem, base, size);
if (rgn >= 0) {
/*
* Check if the requested end address is in the same memory
* region we found.
*/
- if (lmb_addrs_overlap(lmb->memory.region[rgn].base,
- lmb->memory.region[rgn].size,
+ if (lmb_addrs_overlap(lmb_memory[rgn].base,
+ lmb_memory[rgn].size,
base + size - 1, 1)) {
/* ok, reserve the memory */
- if (lmb_reserve(lmb, base, size) >= 0)
+ if (lmb_reserve_flags(base, size, flags) >= 0)
return base;
}
}
+
return 0;
}
+/*
+ * Try to allocate a specific address range: must be in defined memory but not
+ * reserved
+ */
+phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size)
+{
+ return __lmb_alloc_addr(base, size, LMB_NONE);
+}
+
/* Return number of bytes from a given address that are free */
-phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr)
+phys_size_t lmb_get_free_size(phys_addr_t addr)
{
int i;
long rgn;
+ struct lmb_region *lmb_used = lmb.used_mem.data;
+ struct lmb_region *lmb_memory = lmb.free_mem.data;
/* check if the requested address is in the memory regions */
- rgn = lmb_overlaps_region(&lmb->memory, addr, 1);
+ rgn = lmb_overlaps_region(&lmb.free_mem, addr, 1);
if (rgn >= 0) {
- for (i = 0; i < lmb->reserved.cnt; i++) {
- if (addr < lmb->reserved.region[i].base) {
+ for (i = 0; i < lmb.used_mem.count; i++) {
+ if (addr < lmb_used[i].base) {
/* first reserved range > requested address */
- return lmb->reserved.region[i].base - addr;
+ return lmb_used[i].base - addr;
}
- if (lmb->reserved.region[i].base +
- lmb->reserved.region[i].size > addr) {
+ if (lmb_used[i].base +
+ lmb_used[i].size > addr) {
/* requested addr is in this reserved range */
return 0;
}
}
/* if we come here: no reserved ranges above requested addr */
- return lmb->memory.region[lmb->memory.cnt - 1].base +
- lmb->memory.region[lmb->memory.cnt - 1].size - addr;
+ return lmb_memory[lmb.free_mem.count - 1].base +
+ lmb_memory[lmb.free_mem.count - 1].size - addr;
}
return 0;
}
-int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags)
+int lmb_is_reserved_flags(phys_addr_t addr, int flags)
{
int i;
+ struct lmb_region *lmb_used = lmb.used_mem.data;
+
+ for (i = 0; i < lmb.used_mem.count; i++) {
+ phys_addr_t upper = lmb_used[i].base +
+ lmb_used[i].size - 1;
+ if (addr >= lmb_used[i].base && addr <= upper)
+ return (lmb_used[i].flags & flags) == flags;
+ }
+ return 0;
+}
+
+static int lmb_setup(void)
+{
+ bool ret;
+
+ ret = alist_init(&lmb.free_mem, sizeof(struct lmb_region),
+ (uint)LMB_ALIST_INITIAL_SIZE);
+ if (!ret) {
+ log_debug("Unable to initialise the list for LMB free memory\n");
+ return -ENOMEM;
+ }
+
+ ret = alist_init(&lmb.used_mem, sizeof(struct lmb_region),
+ (uint)LMB_ALIST_INITIAL_SIZE);
+ if (!ret) {
+ log_debug("Unable to initialise the list for LMB used memory\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/**
+ * lmb_init() - Initialise the LMB module
+ *
+ * Initialise the LMB lists needed for keeping the memory map. There
+ * are two lists, in form of alloced list data structure. One for the
+ * available memory, and one for the used memory. Initialise the two
+ * lists as part of board init. Add memory to the available memory
+ * list and reserve common areas by adding them to the used memory
+ * list.
+ *
+ * Return: 0 on success, -ve on error
+ */
+int lmb_init(void)
+{
+ int ret;
- for (i = 0; i < lmb->reserved.cnt; i++) {
- phys_addr_t upper = lmb->reserved.region[i].base +
- lmb->reserved.region[i].size - 1;
- if ((addr >= lmb->reserved.region[i].base) && (addr <= upper))
- return (lmb->reserved.region[i].flags & flags) == flags;
+ ret = lmb_setup();
+ if (ret) {
+ log_info("Unable to init LMB\n");
+ return ret;
}
+
+ lmb_add_memory();
+
+ /* Reserve the U-Boot image region once U-Boot has relocated */
+ if (spl_phase() == PHASE_SPL)
+ lmb_reserve_common_spl();
+ else if (spl_phase() == PHASE_BOARD_R)
+ lmb_reserve_common((void *)gd->fdt_blob);
+
return 0;
}
-int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
+#if CONFIG_IS_ENABLED(UNIT_TEST)
+struct lmb *lmb_get(void)
{
- return lmb_is_reserved_flags(lmb, addr, LMB_NONE);
+ return &lmb;
}
-__weak void board_lmb_reserve(struct lmb *lmb)
+int lmb_push(struct lmb *store)
{
- /* please define platform specific board_lmb_reserve() */
+ int ret;
+
+ *store = lmb;
+ ret = lmb_setup();
+ if (ret)
+ return ret;
+
+ return 0;
}
-__weak void arch_lmb_reserve(struct lmb *lmb)
+void lmb_pop(struct lmb *store)
{
- /* please define platform specific arch_lmb_reserve() */
+ alist_uninit(&lmb.free_mem);
+ alist_uninit(&lmb.used_mem);
+ lmb = *store;
}
+#endif /* UNIT_TEST */
diff --git a/lib/strto.c b/lib/strto.c
index 5157332..f83ac67 100644
--- a/lib/strto.c
+++ b/lib/strto.c
@@ -236,12 +236,14 @@
return NULL;
/* count the number of space-separated strings */
- for (count = *str != '\0', p = str; *p; p++) {
+ for (count = 0, p = str; *p; p++) {
if (*p == ' ') {
count++;
*p = '\0';
}
}
+ if (p != str && p[-1])
+ count++;
/* allocate the pointer array, allowing for a NULL terminator */
ptr = calloc(count + 1, sizeof(char *));
diff --git a/lib/uuid.c b/lib/uuid.c
index dfa2320..11b86ff 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -7,21 +7,35 @@
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
-#define LOG_CATEGOT LOGC_CORE
-
+#ifndef USE_HOSTCC
#include <command.h>
#include <efi_api.h>
#include <env.h>
#include <rand.h>
#include <time.h>
-#include <uuid.h>
-#include <linux/ctype.h>
-#include <errno.h>
#include <asm/io.h>
#include <part_efi.h>
#include <malloc.h>
#include <dm/uclass.h>
#include <rng.h>
+#include <linux/ctype.h>
+#include <hexdump.h>
+#else
+#include <stdarg.h>
+#include <stdint.h>
+#include <eficapsule.h>
+#include <ctype.h>
+#endif
+#include <linux/types.h>
+#include <errno.h>
+#include <linux/kconfig.h>
+#include <u-boot/uuid.h>
+#include <u-boot/sha1.h>
+
+#ifdef USE_HOSTCC
+/* polyfill hextoul to avoid pulling in strto.c */
+#define hextoul(cp, endp) strtoul(cp, endp, 16)
+#endif
int uuid_str_valid(const char *uuid)
{
@@ -51,6 +65,7 @@
const char *string;
efi_guid_t guid;
} list_guid[] = {
+#ifndef USE_HOSTCC
#ifdef CONFIG_PARTITION_TYPE_GUID
{"system", PARTITION_SYSTEM_GUID},
{"mbr", LEGACY_MBR_PARTITION_GUID},
@@ -231,6 +246,7 @@
{ "EFI_MEM_STATUS_CODE_REC", EFI_MEM_STATUS_CODE_REC },
{ "EFI_GUID_EFI_ACPI1", EFI_GUID_EFI_ACPI1 },
#endif
+#endif /* !USE_HOSTCC */
};
int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin)
@@ -266,7 +282,6 @@
uint64_t tmp64;
if (!uuid_str_valid(uuid_str)) {
- log_debug("not valid\n");
#ifdef CONFIG_PARTITION_TYPE_GUID
if (!uuid_guid_get_bin(uuid_str, uuid_bin))
return 0;
@@ -297,7 +312,7 @@
tmp16 = cpu_to_be16(hextoul(uuid_str + 19, NULL));
memcpy(uuid_bin + 8, &tmp16, 2);
- tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16));
+ tmp64 = cpu_to_be64(hextoul(uuid_str + 24, NULL));
memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6);
return 0;
@@ -305,9 +320,9 @@
int uuid_str_to_le_bin(const char *uuid_str, unsigned char *uuid_bin)
{
- u16 tmp16;
- u32 tmp32;
- u64 tmp64;
+ uint16_t tmp16;
+ uint32_t tmp32;
+ uint64_t tmp64;
if (!uuid_str_valid(uuid_str) || !uuid_bin)
return -EINVAL;
@@ -324,7 +339,7 @@
tmp16 = cpu_to_le16(hextoul(uuid_str + 19, NULL));
memcpy(uuid_bin + 8, &tmp16, 2);
- tmp64 = cpu_to_le64(simple_strtoull(uuid_str + 24, NULL, 16));
+ tmp64 = cpu_to_le64(hextoul(uuid_str + 24, NULL));
memcpy(uuid_bin + 10, &tmp64, 6);
return 0;
@@ -333,11 +348,11 @@
void uuid_bin_to_str(const unsigned char *uuid_bin, char *uuid_str,
int str_format)
{
- const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8,
+ const uint8_t uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15};
- const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
+ const uint8_t guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8,
9, 10, 11, 12, 13, 14, 15};
- const u8 *char_order;
+ const uint8_t *char_order;
const char *format;
int i;
@@ -367,8 +382,59 @@
break;
}
}
+}
+
+static void configure_uuid(struct uuid *uuid, unsigned char version)
+{
+ uint16_t tmp;
+
+ /* Configure variant/version bits */
+ tmp = be16_to_cpu(uuid->time_hi_and_version);
+ tmp = (tmp & ~UUID_VERSION_MASK) | (version << UUID_VERSION_SHIFT);
+ uuid->time_hi_and_version = cpu_to_be16(tmp);
+
+ uuid->clock_seq_hi_and_reserved &= ~UUID_VARIANT_MASK;
+ uuid->clock_seq_hi_and_reserved |= (UUID_VARIANT << UUID_VARIANT_SHIFT);
+}
+
+void gen_v5_guid(const struct uuid *namespace, struct efi_guid *guid, ...)
+{
+ sha1_context ctx;
+ va_list args;
+ const uint8_t *data;
+ uint32_t *tmp32;
+ uint16_t *tmp16;
+ uint8_t hash[SHA1_SUM_LEN];
+
+ sha1_starts(&ctx);
+ /* Hash the namespace UUID as salt */
+ sha1_update(&ctx, (unsigned char *)namespace, UUID_BIN_LEN);
+ va_start(args, guid);
+
+ while ((data = va_arg(args, const uint8_t *))) {
+ unsigned int len = va_arg(args, size_t);
+
+ sha1_update(&ctx, data, len);
+ }
+
+ va_end(args);
+ sha1_finish(&ctx, hash);
+
+ /* Truncate the hash into output UUID, it is already big endian */
+ memcpy(guid, hash, sizeof(*guid));
+
+ configure_uuid((struct uuid *)guid, 5);
+
+ /* Make little endian */
+ tmp32 = (uint32_t *)&guid->b[0];
+ *tmp32 = cpu_to_le32(be32_to_cpu(*tmp32));
+ tmp16 = (uint16_t *)&guid->b[4];
+ *tmp16 = cpu_to_le16(be16_to_cpu(*tmp16));
+ tmp16 = (uint16_t *)&guid->b[6];
+ *tmp16 = cpu_to_le16(be16_to_cpu(*tmp16));
}
+#ifndef USE_HOSTCC
#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
void gen_rand_uuid(unsigned char *uuid_bin)
{
@@ -395,13 +461,7 @@
for (i = 0; i < 4; i++)
ptr[i] = rand();
- clrsetbits_be16(&uuid->time_hi_and_version,
- UUID_VERSION_MASK,
- UUID_VERSION << UUID_VERSION_SHIFT);
-
- clrsetbits_8(&uuid->clock_seq_hi_and_reserved,
- UUID_VARIANT_MASK,
- UUID_VARIANT << UUID_VARIANT_SHIFT);
+ configure_uuid(uuid, UUID_VERSION);
memcpy(uuid_bin, uuid, 16);
}
@@ -458,3 +518,4 @@
);
#endif /* CONFIG_CMD_UUID */
#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */
+#endif /* !USE_HOSTCC */
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index cfd1f19..e580286 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -18,7 +18,7 @@
#include <div64.h>
#include <hexdump.h>
#include <stdarg.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <stdio.h>
#include <vsprintf.h>
#include <linux/ctype.h>
diff --git a/net/bootp.c b/net/bootp.c
index 9dfb507..512ab2e 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -15,7 +15,7 @@
#include <log.h>
#include <net.h>
#include <rand.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <linux/delay.h>
#include <net/tftp.h>
#include "bootp.h"
diff --git a/net/net.c b/net/net.c
index d9bc9df..1e0b7c8 100644
--- a/net/net.c
+++ b/net/net.c
@@ -334,17 +334,22 @@
net_set_state(NETLOOP_SUCCESS);
return;
}
- if (net_check_prereq(TFTPGET)) {
-/* We aren't expecting to get a serverip, so just accept the assigned IP */
- if (IS_ENABLED(CONFIG_BOOTP_SERVERIP)) {
- net_set_state(NETLOOP_SUCCESS);
- } else {
- printf("Cannot autoload with TFTPGET\n");
- net_set_state(NETLOOP_FAIL);
+ if (IS_ENABLED(CONFIG_CMD_TFTPBOOT)) {
+ if (net_check_prereq(TFTPGET)) {
+ /*
+ * We aren't expecting to get a serverip, so just
+ * accept the assigned IP
+ */
+ if (IS_ENABLED(CONFIG_BOOTP_SERVERIP)) {
+ net_set_state(NETLOOP_SUCCESS);
+ } else {
+ printf("Cannot autoload with TFTPGET\n");
+ net_set_state(NETLOOP_FAIL);
+ }
+ return;
}
- return;
+ tftp_start(TFTPGET);
}
- tftp_start(TFTPGET);
}
static int net_init_loop(void)
diff --git a/net/tftp.c b/net/tftp.c
index 2e07318..d6744bc 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -82,9 +82,6 @@
static ulong tftp_block_wrap_offset;
static int tftp_state;
static ulong tftp_load_addr;
-#ifdef CONFIG_LMB
-static ulong tftp_load_size;
-#endif
#ifdef CONFIG_TFTP_TSIZE
/* The file size reported by the server */
static int tftp_tsize;
@@ -160,19 +157,15 @@
ulong store_addr = tftp_load_addr + offset;
void *ptr;
-#ifdef CONFIG_LMB
- ulong end_addr = tftp_load_addr + tftp_load_size;
-
- if (!end_addr)
- end_addr = ULONG_MAX;
-
- if (store_addr < tftp_load_addr ||
- store_addr + len > end_addr) {
- puts("\nTFTP error: ");
- puts("trying to overwrite reserved memory...\n");
- return -1;
+ if (CONFIG_IS_ENABLED(LMB)) {
+ if (store_addr < tftp_load_addr ||
+ lmb_read_check(store_addr, len)) {
+ puts("\nTFTP error: ");
+ puts("trying to overwrite reserved memory...\n");
+ return -1;
+ }
}
-#endif
+
ptr = map_sysmem(store_addr, len);
memcpy(ptr, src, len);
unmap_sysmem(ptr);
@@ -713,21 +706,8 @@
}
}
-/* Initialize tftp_load_addr and tftp_load_size from image_load_addr and lmb */
static int tftp_init_load_addr(void)
{
-#ifdef CONFIG_LMB
- struct lmb lmb;
- phys_size_t max_size;
-
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
- max_size = lmb_get_free_size(&lmb, image_load_addr);
- if (!max_size)
- return -1;
-
- tftp_load_size = max_size;
-#endif
tftp_load_addr = image_load_addr;
return 0;
}
diff --git a/net/wget.c b/net/wget.c
index f1dd7ab..b4251e0 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -8,6 +8,7 @@
#include <command.h>
#include <display_options.h>
#include <env.h>
+#include <efi_loader.h>
#include <image.h>
#include <lmb.h>
#include <mapmem.h>
@@ -64,29 +65,6 @@
static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */
static int retry_len; /* TCP retry length */
-static ulong wget_load_size;
-
-/**
- * wget_init_max_size() - initialize maximum load size
- *
- * Return: 0 if success, -1 if fails
- */
-static int wget_init_load_size(void)
-{
- struct lmb lmb;
- phys_size_t max_size;
-
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
- max_size = lmb_get_free_size(&lmb, image_load_addr);
- if (!max_size)
- return -1;
-
- wget_load_size = max_size;
-
- return 0;
-}
-
/**
* store_block() - store block in memory
* @src: source of data
@@ -99,14 +77,9 @@
ulong newsize = offset + len;
uchar *ptr;
- if (IS_ENABLED(CONFIG_LMB)) {
- ulong end_addr = image_load_addr + wget_load_size;
-
- if (!end_addr)
- end_addr = ULONG_MAX;
-
+ if (CONFIG_IS_ENABLED(LMB)) {
if (store_addr < image_load_addr ||
- store_addr + len > end_addr) {
+ lmb_read_check(store_addr, len)) {
printf("\nwget error: ");
printf("trying to overwrite reserved memory...\n");
return -1;
@@ -199,13 +172,6 @@
wget_send(action, tcp_seq_num, tcp_ack_num, 0);
}
-void wget_success(u8 action, unsigned int tcp_seq_num,
- unsigned int tcp_ack_num, int len, int packets)
-{
- printf("Packets received %d, Transfer Successful\n", packets);
- wget_send(action, tcp_seq_num, tcp_ack_num, len);
-}
-
/*
* Interfaces of U-BOOT
*/
@@ -244,7 +210,7 @@
pkt_in_q = (void *)image_load_addr + PKT_QUEUE_OFFSET +
(pkt_q_idx * PKT_QUEUE_PACKET_SIZE);
- ptr1 = map_sysmem((phys_addr_t)pkt_in_q, len);
+ ptr1 = map_sysmem((ulong)pkt_in_q, len);
memcpy(ptr1, pkt, len);
unmap_sysmem(ptr1);
@@ -314,9 +280,8 @@
for (i = 0; i < pkt_q_idx; i++) {
int err;
- ptr1 = map_sysmem(
- (phys_addr_t)(pkt_q[i].pkt),
- pkt_q[i].len);
+ ptr1 = map_sysmem((ulong)pkt_q[i].pkt,
+ pkt_q[i].len);
err = store_block(ptr1,
pkt_q[i].tcp_seq_num -
initial_data_seq_num,
@@ -436,6 +401,9 @@
case WGET_TRANSFERRED:
printf("Packets received %d, Transfer Successful\n", packets);
net_set_state(wget_loop_state);
+ efi_set_bootdev("Net", "", image_url,
+ map_sysmem(image_load_addr, 0),
+ net_boot_file_size);
break;
}
}
@@ -497,15 +465,6 @@
debug_cond(DEBUG_WGET,
"\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr);
- if (IS_ENABLED(CONFIG_LMB)) {
- if (wget_init_load_size()) {
- printf("\nwget error: ");
- printf("trying to overwrite reserved memory...\n");
- net_set_state(NETLOOP_FAIL);
- return;
- }
- }
-
net_set_timeout_handler(wget_timeout, wget_timeout_handler);
tcp_set_tcp_handler(wget_handler);
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 62e0207..5daceb2 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -32,6 +32,10 @@
escsq = $(subst $(squote),'\$(squote)',$1)
###
+# real prerequisites without phony targets
+real-prereqs = $(filter-out $(PHONY), $^)
+
+###
# Easy method for doing a status message
kecho := :
quiet_kecho := echo
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 99cc295..90aed14 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -293,6 +293,7 @@
targets += $(real-objs-y) $(real-objs-m) $(lib-y)
targets += $(extra-y) $(MAKECMDGOALS) $(always)
+targets += $(real-dtb-y) $(lib-y) $(always-y)
# Linker scripts preprocessor (.lds.S -> .lds)
# ---------------------------------------------------------------------------
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index df754d1..5440304 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -47,6 +47,13 @@
subdir-ym := $(sort $(subdir-y) $(subdir-m))
+# Expand $(foo-objs) $(foo-y) etc. by replacing their individuals
+suffix-search = $(strip $(foreach s, $3, $($(1:%$(strip $2)=%$s))))
+# List composite targets that are constructed by combining other targets
+multi-search = $(sort $(foreach m, $1, $(if $(call suffix-search, $m, $2, $3 -), $m)))
+# List primitive targets that are compiled from source files
+real-search = $(foreach m, $1, $(if $(call suffix-search, $m, $2, $3 -), $(call suffix-search, $m, $2, $3), $m))
+
# if $(foo-objs) exists, foo.o is a composite object
multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
@@ -58,6 +65,13 @@
multi-objs-y := $(foreach m, $(multi-used-y), $($(m:.o=-objs)) $($(m:.o=-y)))
multi-objs-m := $(foreach m, $(multi-used-m), $($(m:.o=-objs)) $($(m:.o=-y)))
+# Composite DTB (i.e. DTB constructed by overlay)
+multi-dtb-y := $(call multi-search, $(dtb-y), .dtb, -dtbs)
+# Primitive DTB compiled from *.dts
+real-dtb-y := $(call real-search, $(dtb-y), .dtb, -dtbs)
+# Base DTB that overlay is applied onto (each first word of $(*-dtbs) expansion)
+base-dtb-y := $(foreach m, $(multi-dtb-y), $(firstword $(call suffix-search, $m, .dtb, -dtbs)))
+
# $(subdir-obj-y) is the list of objects in $(obj-y) which uses dir/ to
# tell kbuild to descend
subdir-obj-y := $(filter %/built-in.o, $(obj-y))
@@ -69,6 +83,7 @@
# Add subdir path
extra-y := $(addprefix $(obj)/,$(extra-y))
+always-y := $(addprefix $(obj)/,$(always-y))
always := $(addprefix $(obj)/,$(always))
targets := $(addprefix $(obj)/,$(targets))
modorder := $(addprefix $(obj)/,$(modorder))
@@ -83,6 +98,8 @@
multi-used-m := $(addprefix $(obj)/,$(multi-used-m))
multi-objs-y := $(addprefix $(obj)/,$(multi-objs-y))
multi-objs-m := $(addprefix $(obj)/,$(multi-objs-m))
+multi-dtb-y := $(addprefix $(obj)/,$(multi-dtb-y))
+real-dtb-y := $(addprefix $(obj)/,$(real-dtb-y))
subdir-ym := $(addprefix $(obj)/,$(subdir-ym))
# These flags are needed for modversions and compiling, so we define them here
@@ -185,9 +202,6 @@
dtsi_include_list = $(strip $(u_boot_dtsi_options_debug) \
$(notdir $(firstword $(u_boot_dtsi_options))))
-# The CONFIG_DEVICE_TREE_INCLUDES also need to be included
-dtsi_include_list += $(CONFIG_DEVICE_TREE_INCLUDES)
-
# Modified for U-Boot
upstream_dtsi_include = $(addprefix -I, $(srctree)/dts/upstream/src/ \
$(sort $(dir $(wildcard $(srctree)/dts/upstream/src/$(ARCH)/*/*))) \
@@ -304,6 +318,9 @@
DTC_FLAGS += $(DTC_FLAGS_$(basetarget))
+# Set -@ if the target is a base DTB that overlay is applied onto
+DTC_FLAGS += $(if $(filter $(patsubst $(obj)/%,%,$@), $(base-dtb-y)), -@)
+
# Generate an assembly file to wrap the output of the device tree compiler
quiet_cmd_dt_S_dtb= DTBS $@
# Modified for U-Boot
@@ -350,7 +367,7 @@
# And finally any custom .dtsi fragments specified with CONFIG_DEVICE_TREE_INCLUDES
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
(cat $< > $(pre-tmp)); \
- $(foreach f,$(subst $(quote),,$(dtsi_include_list)), \
+ $(foreach f,$(subst $(quote),,$(dtsi_include_list) $(CONFIG_DEVICE_TREE_INCLUDES)), \
echo '$(pound)include "$(f)"' >> $(pre-tmp);) \
$(HOSTCC) -E $(dtc_cpp_flags) -I$(obj) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \
$(DTC) -O dtb -o $@ -b 0 \
@@ -425,6 +442,13 @@
$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
$(call if_changed_dep,dtco)
+quiet_cmd_fdtoverlay = DTOVL $@
+ cmd_fdtoverlay = fdtoverlay -o $@ -i $(real-prereqs)
+
+$(multi-dtb-y): FORCE
+ $(call if_changed,fdtoverlay)
+$(call multi_depend, $(multi-dtb-y), .dtb, -dtbs)
+
# Fonts
# ---------------------------------------------------------------------------
diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c
index 703b9b8..5245804 100644
--- a/scripts/kconfig/symbol.c
+++ b/scripts/kconfig/symbol.c
@@ -1117,7 +1117,7 @@
}
fprintf(stderr,
- "For a resolution refer to Documentation/kbuild/kconfig-language.txt\n"
+ "For a resolution refer to Documentation/kbuild/kconfig-language.rst\n"
"subsection \"Kconfig recursive dependency limitations\"\n"
"\n");
diff --git a/scripts/kconfig/tests/err_recursive_dep/expected_stderr b/scripts/kconfig/tests/err_recursive_dep/expected_stderr
index 84679b1..c9f4abf 100644
--- a/scripts/kconfig/tests/err_recursive_dep/expected_stderr
+++ b/scripts/kconfig/tests/err_recursive_dep/expected_stderr
@@ -1,38 +1,38 @@
Kconfig:11:error: recursive dependency detected!
Kconfig:11: symbol B is selected by B
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:5:error: recursive dependency detected!
Kconfig:5: symbol A depends on A
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:17:error: recursive dependency detected!
Kconfig:17: symbol C1 depends on C2
Kconfig:21: symbol C2 depends on C1
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:32:error: recursive dependency detected!
Kconfig:32: symbol D2 is selected by D1
Kconfig:27: symbol D1 depends on D2
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:37:error: recursive dependency detected!
Kconfig:37: symbol E1 depends on E2
Kconfig:42: symbol E2 is implied by E1
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:60:error: recursive dependency detected!
Kconfig:60: symbol G depends on G
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
Kconfig:51:error: recursive dependency detected!
Kconfig:51: symbol F2 depends on F1
Kconfig:49: symbol F1 default value contains F2
-For a resolution refer to Documentation/kbuild/kconfig-language.txt
+For a resolution refer to Documentation/kbuild/kconfig-language.rst
subsection "Kconfig recursive dependency limitations"
diff --git a/scripts/pylint.base b/scripts/pylint.base
index c7d141e..bc39e23 100644
--- a/scripts/pylint.base
+++ b/scripts/pylint.base
@@ -1,229 +1,311 @@
-test_conftest.py 6.56
-test_multiplexed_log.py 7.49
-test_test.py 8.18
+test_conftest.py 6.78
+test_multiplexed_log.py 7.68
+test_test.py 9.00
+test_tests_fit_util.py 7.19
+test_tests_fs_helper.py 10.00
test_tests_test_000_version.py 7.50
-test_tests_test_android_test_ab.py 6.50
-test_tests_test_android_test_abootimg.py 6.09
-test_tests_test_android_test_avb.py 5.52
-test_tests_test_bind.py -2.99
+test_tests_test_android_test_ab.py 7.00
+test_tests_test_android_test_abootimg.py 6.52
+test_tests_test_android_test_avb.py 6.38
+test_tests_test_bind.py 8.89
test_tests_test_bootmenu.py 10.00
+test_tests_test_bootstage.py 7.14
test_tests_test_button.py 3.33
-test_tests_test_dfu.py 5.45
-test_tests_test_dm.py 9.52
-test_tests_test_efi_capsule_capsule_defs.py 6.67
-test_tests_test_efi_capsule_conftest.py 1.86
-test_tests_test_efi_capsule_test_capsule_firmware.py 4.52
-test_tests_test_efi_capsule_test_capsule_firmware_signed.py 4.85
-test_tests_test_efi_fit.py 8.16
-test_tests_test_efi_loader.py 7.38
-test_tests_test_efi_secboot_conftest.py -3.29
-test_tests_test_efi_secboot_defs.py 6.67
-test_tests_test_efi_secboot_test_authvar.py 8.93
-test_tests_test_efi_secboot_test_signed.py 8.41
-test_tests_test_efi_secboot_test_signed_intca.py 8.10
-test_tests_test_efi_secboot_test_unsigned.py 8.00
-test_tests_test_efi_selftest.py 6.36
-test_tests_test_env.py 7.15
-test_tests_test_extension.py 2.14
-test_tests_test_fit.py 6.83
-test_tests_test_fit_ecdsa.py 7.94
-test_tests_test_fit_hashes.py 7.70
-test_tests_test_fpga.py 1.81
-test_tests_test_fs_conftest.py 5.13
+test_tests_test_cat_conftest.py 10.00
+test_tests_test_cat_test_cat.py 10.00
+test_tests_test_cleanup_build.py 10.00
+test_tests_test_dfu.py 6.23
+test_tests_test_dm.py 8.98
+test_tests_test_efi_bootmgr_conftest.py 10.00
+test_tests_test_efi_bootmgr_test_efi_bootmgr.py 10.00
+test_tests_test_efi_capsule_capsule_common.py 10.00
+test_tests_test_efi_capsule_capsule_defs.py 10.00
+test_tests_test_efi_capsule_conftest.py 3.26
+test_tests_test_efi_capsule_test_capsule_firmware_fit.py 10.00
+test_tests_test_efi_capsule_test_capsule_firmware_raw.py 9.62
+test_tests_test_efi_capsule_test_capsule_firmware_signed_fit.py 9.74
+test_tests_test_efi_capsule_test_capsule_firmware_signed_raw.py 9.75
+test_tests_test_efi_fit.py 8.84
+test_tests_test_efi_loader.py 8.00
+test_tests_test_efi_secboot_conftest.py 0.00
+test_tests_test_efi_secboot_defs.py 10.00
+test_tests_test_efi_secboot_test_authvar.py 9.38
+test_tests_test_efi_secboot_test_signed.py 8.60
+test_tests_test_efi_secboot_test_signed_intca.py 8.81
+test_tests_test_efi_secboot_test_unsigned.py 8.75
+test_tests_test_efi_selftest.py 8.07
+test_tests_test_eficonfig_conftest.py 10.00
+test_tests_test_eficonfig_test_eficonfig.py 9.47
+test_tests_test_env.py 7.76
+test_tests_test_event_dump.py 2.22
+test_tests_test_extension.py 2.50
+test_tests_test_fit.py 7.54
+test_tests_test_fit_auto_signed.py 9.09
+test_tests_test_fit_ecdsa.py 8.29
+test_tests_test_fit_hashes.py 7.94
+test_tests_test_fpga.py 2.94
+test_tests_test_fs_conftest.py 5.21
test_tests_test_fs_fstest_defs.py 8.33
test_tests_test_fs_fstest_helpers.py 4.29
-test_tests_test_fs_test_basic.py 0.60
-test_tests_test_fs_test_ext.py 0.00
+test_tests_test_fs_test_basic.py 1.90
+test_tests_test_fs_test_erofs.py 8.97
+test_tests_test_fs_test_ext.py 1.48
test_tests_test_fs_test_fs_cmd.py 8.00
-test_tests_test_fs_test_mkdir.py 1.96
-test_tests_test_fs_test_squashfs_sqfs_common.py 8.41
-test_tests_test_fs_test_squashfs_test_sqfs_load.py 7.46
-test_tests_test_fs_test_squashfs_test_sqfs_ls.py 8.00
-test_tests_test_fs_test_symlink.py 1.22
-test_tests_test_fs_test_unlink.py 2.78
-test_tests_test_gpio.py 6.09
-test_tests_test_gpt.py 7.67
+test_tests_test_fs_test_fs_fat.py 2.50
+test_tests_test_fs_test_mkdir.py 3.04
+test_tests_test_fs_test_squashfs_sqfs_common.py 8.38
+test_tests_test_fs_test_squashfs_test_sqfs_load.py 7.63
+test_tests_test_fs_test_squashfs_test_sqfs_ls.py 8.04
+test_tests_test_fs_test_symlink.py 2.04
+test_tests_test_fs_test_unlink.py 4.07
+test_tests_test_gpio.py 7.60
+test_tests_test_gpt.py 8.55
test_tests_test_handoff.py 5.00
-test_tests_test_help.py 5.00
-test_tests_test_hush_if_test.py 9.27
-test_tests_test_log.py 8.64
+test_tests_test_help.py 8.64
+test_tests_test_i2c.py 7.42
+test_tests_test_kconfig.py 5.38
+test_tests_test_log.py 8.75
test_tests_test_lsblk.py 8.00
test_tests_test_md.py 3.64
+test_tests_test_mdio.py 6.82
+test_tests_test_memtest.py 8.39
+test_tests_test_mii.py 8.55
+test_tests_test_mmc.py 7.01
test_tests_test_mmc_rd.py 6.05
test_tests_test_mmc_wr.py 3.33
-test_tests_test_net.py 6.84
+test_tests_test_net.py 8.43
+test_tests_test_net_boot.py 8.23
+test_tests_test_of_migrate.py 7.86
test_tests_test_ofplatdata.py 5.71
+test_tests_test_optee_rpmb.py 0.00
test_tests_test_part.py 8.00
-test_tests_test_pinmux.py 3.27
+test_tests_test_pinmux.py 3.40
test_tests_test_pstore.py 2.31
test_tests_test_qfw.py 8.75
+test_tests_test_reset.py 9.55
test_tests_test_sandbox_exit.py 6.50
+test_tests_test_sandbox_opts.py 1.11
+test_tests_test_saveenv.py 7.87
test_tests_test_scp03.py 3.33
-test_tests_test_sf.py 7.13
+test_tests_test_scsi.py 8.47
+test_tests_test_semihosting_conftest.py 10.00
+test_tests_test_semihosting_test_hostfs.py 10.00
+test_tests_test_sf.py 7.45
test_tests_test_shell_basics.py 9.58
-test_tests_test_sleep.py 7.78
-test_tests_test_spl.py 2.22
+test_tests_test_sleep.py 8.28
+test_tests_test_smbios.py 9.47
+test_tests_test_source.py 7.20
+test_tests_test_spl.py 6.67
test_tests_test_stackprotector.py 5.71
-test_tests_test_tpm2.py 8.51
-test_tests_test_ums.py 6.32
+test_tests_test_tpm2.py 8.45
+test_tests_test_trace.py 8.70
+test_tests_test_ums.py 5.92
test_tests_test_unknown_cmd.py 5.00
-test_tests_test_ut.py 7.06
-test_tests_test_vboot.py 6.01
-test_tests_vboot_evil.py 8.95
+test_tests_test_upl.py 5.33
+test_tests_test_usb.py 7.08
+test_tests_test_ut.py 9.44
+test_tests_test_vbe.py 7.22
+test_tests_test_vbe_vpl.py 6.11
+test_tests_test_vboot.py 5.37
+test_tests_test_vpl.py 2.22
+test_tests_test_xxd_conftest.py 10.00
+test_tests_test_xxd_test_xxd.py 10.00
+test_tests_test_zynq_secure.py 7.60
+test_tests_test_zynqmp_rpu.py 7.54
+test_tests_test_zynqmp_secure.py 7.68
+test_tests_vboot_evil.py 9.45
test_tests_vboot_forge.py 9.22
-test_u_boot_console_base.py 7.08
-test_u_boot_console_exec_attach.py 9.23
-test_u_boot_console_sandbox.py 8.06
-test_u_boot_spawn.py 7.65
-test_u_boot_utils.py 6.94
-tools_binman_bintool 8.59
+test_u_boot_console_base.py 7.73
+test_u_boot_console_exec_attach.py 9.62
+test_u_boot_console_sandbox.py 8.64
+test_u_boot_spawn.py 8.57
+test_u_boot_utils.py 7.83
+tools_binman_bintool 9.16
tools_binman_bintool_test 9.87
-tools_binman_btool__testing 6.09
+tools_binman_btool__testing 6.52
+tools_binman_btool_bootgen 4.50
+tools_binman_btool_btool_gzip 0.00
+tools_binman_btool_bzip2 0.00
tools_binman_btool_cbfstool 7.83
-tools_binman_btool_fiptool 7.62
-tools_binman_btool_futility 7.39
+tools_binman_btool_cst 5.00
+tools_binman_btool_fdt_add_pubkey 7.00
+tools_binman_btool_fdtgrep 5.20
+tools_binman_btool_fiptool 7.22
+tools_binman_btool_futility 6.67
tools_binman_btool_ifwitool 3.81
-tools_binman_btool_lz4 6.30
+tools_binman_btool_lz4 4.76
tools_binman_btool_lzma_alone 6.97
-tools_binman_btool_mkimage 7.86
-tools_binman_cbfs_util 8.46
-tools_binman_cbfs_util_test 9.38
-tools_binman_cmdline 9.03
-tools_binman_comp_util 6.88
-tools_binman_control 5.01
-tools_binman_elf 6.98
-tools_binman_elf_test 5.62
-tools_binman_entry 3.55
-tools_binman_entry_test 5.34
-tools_binman_etype__testing 0.83
-tools_binman_etype_atf_bl31 -6.00
-tools_binman_etype_atf_fip 0.29
-tools_binman_etype_blob -1.58
-tools_binman_etype_blob_dtb -10.00
-tools_binman_etype_blob_ext -19.09
+tools_binman_btool_lzop 0.00
+tools_binman_btool_mkeficapsule 7.69
+tools_binman_btool_mkimage 6.36
+tools_binman_btool_openssl 4.63
+tools_binman_btool_xz 0.00
+tools_binman_btool_zstd 0.00
+tools_binman_cbfs_util 8.93
+tools_binman_cbfs_util_test 9.81
+tools_binman_cmdline 9.33
+tools_binman_control 6.92
+tools_binman_elf 7.52
+tools_binman_elf_test 8.40
+tools_binman_entry 6.40
+tools_binman_entry_test 6.99
+tools_binman_etype__testing 2.02
+tools_binman_etype_alternates_fdt 5.09
+tools_binman_etype_atf_bl31 0.00
+tools_binman_etype_atf_fip 0.44
+tools_binman_etype_blob 0.41
+tools_binman_etype_blob_dtb 0.21
+tools_binman_etype_blob_ext 0.00
tools_binman_etype_blob_ext_list 0.00
-tools_binman_etype_blob_named_by_arg -7.78
-tools_binman_etype_blob_phase -5.00
-tools_binman_etype_cbfs -1.44
+tools_binman_etype_blob_named_by_arg 0.00
+tools_binman_etype_blob_phase 0.50
+tools_binman_etype_cbfs 1.86
tools_binman_etype_collection 2.67
-tools_binman_etype_cros_ec_rw -6.00
-tools_binman_etype_fdtmap -3.28
-tools_binman_etype_files -7.43
-tools_binman_etype_fill -6.43
-tools_binman_etype_fit 6.31
-tools_binman_etype_fmap -0.29
-tools_binman_etype_gbb 0.83
-tools_binman_etype_image_header 5.77
-tools_binman_etype_intel_cmc -12.50
+tools_binman_etype_cros_ec_rw 0.00
+tools_binman_etype_efi_capsule 3.33
+tools_binman_etype_efi_empty_capsule 0.00
+tools_binman_etype_encrypted 1.43
+tools_binman_etype_fdtmap 0.16
+tools_binman_etype_files 0.00
+tools_binman_etype_fill 0.00
+tools_binman_etype_fit 7.52
+tools_binman_etype_fmap 0.54
+tools_binman_etype_gbb 1.35
+tools_binman_etype_image_header 4.81
+tools_binman_etype_intel_cmc 0.00
tools_binman_etype_intel_descriptor 4.62
tools_binman_etype_intel_fit 0.00
tools_binman_etype_intel_fit_ptr 2.35
-tools_binman_etype_intel_fsp -12.50
-tools_binman_etype_intel_fsp_m -12.50
-tools_binman_etype_intel_fsp_s -12.50
-tools_binman_etype_intel_fsp_t -12.50
-tools_binman_etype_intel_ifwi 2.88
-tools_binman_etype_intel_me -12.50
-tools_binman_etype_intel_mrc -10.00
-tools_binman_etype_intel_refcode -10.00
-tools_binman_etype_intel_vbt -12.50
-tools_binman_etype_intel_vga -12.50
-tools_binman_etype_mkimage 1.47
-tools_binman_etype_opensbi -6.00
-tools_binman_etype_powerpc_mpc85xx_bootpg_resetvec -10.00
-tools_binman_etype_scp -6.00
-tools_binman_etype_section 4.57
-tools_binman_etype_tee_os -6.00
-tools_binman_etype_text -0.48
-tools_binman_etype_u_boot -15.71
-tools_binman_etype_u_boot_dtb -12.22
-tools_binman_etype_u_boot_dtb_with_ucode 0.39
-tools_binman_etype_u_boot_elf -8.42
+tools_binman_etype_intel_fsp 0.00
+tools_binman_etype_intel_fsp_m 0.00
+tools_binman_etype_intel_fsp_s 0.00
+tools_binman_etype_intel_fsp_t 0.00
+tools_binman_etype_intel_ifwi 3.13
+tools_binman_etype_intel_me 0.00
+tools_binman_etype_intel_mrc 0.00
+tools_binman_etype_intel_refcode 0.00
+tools_binman_etype_intel_vbt 0.00
+tools_binman_etype_intel_vga 0.00
+tools_binman_etype_mkimage 4.88
+tools_binman_etype_null 0.00
+tools_binman_etype_nxp_imx8mcst 2.44
+tools_binman_etype_nxp_imx8mimage 0.00
+tools_binman_etype_opensbi 0.00
+tools_binman_etype_powerpc_mpc85xx_bootpg_resetvec 0.00
+tools_binman_etype_pre_load 3.68
+tools_binman_etype_rockchip_tpl 0.00
+tools_binman_etype_scp 0.00
+tools_binman_etype_section 6.04
+tools_binman_etype_tee_os 4.00
+tools_binman_etype_text 0.00
+tools_binman_etype_ti_board_config 5.40
+tools_binman_etype_ti_dm 0.00
+tools_binman_etype_ti_secure 4.22
+tools_binman_etype_ti_secure_rom 2.22
+tools_binman_etype_u_boot 0.00
+tools_binman_etype_u_boot_dtb 0.00
+tools_binman_etype_u_boot_dtb_with_ucode 1.73
+tools_binman_etype_u_boot_elf 0.00
tools_binman_etype_u_boot_env 0.74
-tools_binman_etype_u_boot_expanded -10.00
-tools_binman_etype_u_boot_img -15.71
-tools_binman_etype_u_boot_nodtb -15.71
-tools_binman_etype_u_boot_spl -10.91
-tools_binman_etype_u_boot_spl_bss_pad -9.29
-tools_binman_etype_u_boot_spl_dtb -12.22
-tools_binman_etype_u_boot_spl_elf -15.71
-tools_binman_etype_u_boot_spl_expanded -9.09
-tools_binman_etype_u_boot_spl_nodtb -10.91
-tools_binman_etype_u_boot_spl_with_ucode_ptr -5.00
-tools_binman_etype_u_boot_tpl -10.91
-tools_binman_etype_u_boot_tpl_bss_pad -9.29
-tools_binman_etype_u_boot_tpl_dtb -12.22
-tools_binman_etype_u_boot_tpl_dtb_with_ucode -7.50
-tools_binman_etype_u_boot_tpl_elf -15.71
-tools_binman_etype_u_boot_tpl_expanded -9.09
-tools_binman_etype_u_boot_tpl_nodtb -10.91
-tools_binman_etype_u_boot_tpl_with_ucode_ptr -20.83
+tools_binman_etype_u_boot_expanded 0.00
+tools_binman_etype_u_boot_img 0.00
+tools_binman_etype_u_boot_nodtb 0.00
+tools_binman_etype_u_boot_spl 0.00
+tools_binman_etype_u_boot_spl_bss_pad 0.00
+tools_binman_etype_u_boot_spl_dtb 0.00
+tools_binman_etype_u_boot_spl_elf 0.00
+tools_binman_etype_u_boot_spl_expanded 0.00
+tools_binman_etype_u_boot_spl_nodtb 0.00
+tools_binman_etype_u_boot_spl_pubkey_dtb 1.21
+tools_binman_etype_u_boot_spl_with_ucode_ptr 0.00
+tools_binman_etype_u_boot_tpl 0.00
+tools_binman_etype_u_boot_tpl_bss_pad 0.00
+tools_binman_etype_u_boot_tpl_dtb 0.00
+tools_binman_etype_u_boot_tpl_dtb_with_ucode 0.00
+tools_binman_etype_u_boot_tpl_elf 0.00
+tools_binman_etype_u_boot_tpl_expanded 0.00
+tools_binman_etype_u_boot_tpl_nodtb 0.00
+tools_binman_etype_u_boot_tpl_with_ucode_ptr 0.00
tools_binman_etype_u_boot_ucode 1.52
-tools_binman_etype_u_boot_with_ucode_ptr -0.71
-tools_binman_etype_vblock 0.27
-tools_binman_etype_x86_reset16 -15.71
-tools_binman_etype_x86_reset16_spl -15.71
-tools_binman_etype_x86_reset16_tpl -15.71
-tools_binman_etype_x86_start16 -15.71
-tools_binman_etype_x86_start16_spl -15.71
-tools_binman_etype_x86_start16_tpl -15.71
-tools_binman_fdt_test 10.00
+tools_binman_etype_u_boot_vpl 0.00
+tools_binman_etype_u_boot_vpl_bss_pad 0.00
+tools_binman_etype_u_boot_vpl_dtb 0.00
+tools_binman_etype_u_boot_vpl_elf 0.00
+tools_binman_etype_u_boot_vpl_expanded 0.00
+tools_binman_etype_u_boot_vpl_nodtb 0.00
+tools_binman_etype_u_boot_with_ucode_ptr 0.00
+tools_binman_etype_vblock 0.79
+tools_binman_etype_x509_cert 3.10
+tools_binman_etype_x86_reset16 0.00
+tools_binman_etype_x86_reset16_spl 0.00
+tools_binman_etype_x86_reset16_tpl 0.00
+tools_binman_etype_x86_start16 0.00
+tools_binman_etype_x86_start16_spl 0.00
+tools_binman_etype_x86_start16_tpl 0.00
+tools_binman_etype_xilinx_bootgen 6.06
+tools_binman_fdt_test 7.74
tools_binman_fip_util 9.85
tools_binman_fip_util_test 10.00
-tools_binman_fmap_util 6.88
-tools_binman_ftest 7.46
-tools_binman_image 7.12
-tools_binman_image_test 4.48
-tools_binman_main 4.86
-tools_binman_setup 5.00
-tools_binman_state 4.15
-tools_buildman_board 7.82
-tools_buildman_bsettings 1.71
-tools_buildman_builder 6.92
-tools_buildman_builderthread 7.48
-tools_buildman_cfgutil 7.83
-tools_buildman_cmdline 8.89
-tools_buildman_control 8.12
-tools_buildman_func_test 7.18
-tools_buildman_kconfiglib 7.49
-tools_buildman_main -1.11
-tools_buildman_test 6.56
-tools_buildman_toolchain 6.44
-tools_concurrencytest_concurrencytest 7.26
-tools_dtoc_dtb_platdata 7.90
-tools_dtoc_fdt 4.46
-tools_dtoc_fdt_util 6.80
-tools_dtoc_main 7.78
-tools_dtoc_setup 5.00
-tools_dtoc_src_scan 8.91
-tools_dtoc_test_dtoc 8.56
-tools_dtoc_test_fdt 6.88
-tools_dtoc_test_src_scan 9.43
-tools_efivar 6.71
+tools_binman_fmap_util 6.94
+tools_binman_ftest 8.04
+tools_binman_image 7.29
+tools_binman_image_test 5.52
+tools_binman_main 5.63
+tools_binman_setup 0.00
+tools_binman_state 4.88
+tools_buildman_board 6.36
+tools_buildman_boards 9.72
+tools_buildman_bsettings 5.00
+tools_buildman_builder 7.66
+tools_buildman_builderthread 9.63
+tools_buildman_cfgutil 10.00
+tools_buildman_cmdline 10.00
+tools_buildman_control 9.26
+tools_buildman_func_test 8.38
+tools_buildman_kconfiglib 8.33
+tools_buildman_main 8.10
+tools_buildman_test 7.16
+tools_buildman_toolchain 6.99
+tools_dtoc_dtb_platdata 8.10
+tools_dtoc_fdt 6.31
+tools_dtoc_fdt_util 7.62
+tools_dtoc_main 8.54
+tools_dtoc_setup 0.00
+tools_dtoc_src_scan 9.14
+tools_dtoc_test_dtoc 8.97
+tools_dtoc_test_fdt 9.93
+tools_dtoc_test_src_scan 9.46
+tools_efivar 7.39
tools_endian-swap 9.29
-tools_microcode-tool 7.25
-tools_moveconfig 8.34
+tools_expo 9.72
+tools_key2dtsi 7.14
+tools_microcode-tool 6.55
tools_patman___init__ 0.00
-tools_patman_checkpatch 8.48
-tools_patman_command 5.51
-tools_patman_commit 4.50
-tools_patman_control 8.14
-tools_patman_cros_subprocess 7.76
-tools_patman_func_test 8.51
-tools_patman_get_maintainer 7.06
-tools_patman_gitutil 6.65
-tools_patman_main 7.90
-tools_patman_patchstream 9.11
+tools_patman___main__ 9.44
+tools_patman_checkpatch 8.90
+tools_patman_cmdline 10.00
+tools_patman_commit 6.43
+tools_patman_control 8.29
+tools_patman_func_test 9.02
+tools_patman_get_maintainer 7.50
+tools_patman_gitutil 7.37
+tools_patman_patchstream 9.21
tools_patman_project 7.78
-tools_patman_series 6.16
-tools_patman_settings 5.89
+tools_patman_series 7.54
+tools_patman_settings 7.94
tools_patman_setup 5.00
-tools_patman_status 8.62
-tools_patman_terminal 8.00
-tools_patman_test_checkpatch 7.75
-tools_patman_test_util 7.64
-tools_patman_tools 5.68
-tools_patman_tout 5.31
-tools_rkmux 6.90
-tools_rmboard 7.76
+tools_patman_status 8.52
+tools_patman_test_checkpatch 8.51
+tools_patman_test_settings 8.78
+tools_qconfig 9.79
+tools_rkmux 7.10
+tools_rmboard 8.06
+tools_u_bootlib___init__.py 0.00
+tools_u_bootlib___main__.py 7.78
+tools_u_bootlib_command.py 6.48
+tools_u_bootlib_cros_subprocess.py 9.25
+tools_u_bootlib_terminal.py 8.50
+tools_u_bootlib_test_util.py 7.31
+tools_u_bootlib_tools.py 6.97
+tools_u_bootlib_tout.py 6.56
tools_zynqmp_pm_cfg_obj_convert 6.67
diff --git a/test/bloblist.c b/test/bloblist.c
index 7c63682..fd85c7a 100644
--- a/test/bloblist.c
+++ b/test/bloblist.c
@@ -270,20 +270,15 @@
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
- console_record_reset_enable();
- ut_silence_console(uts);
- console_record_reset();
run_command("bloblist info", 0);
ut_assert_nextline("base: %lx", (ulong)map_to_sysmem(hdr));
ut_assert_nextline("total size: 400 1 KiB");
ut_assert_nextline("used size: 50 80 Bytes");
ut_assert_nextline("free: 3b0 944 Bytes");
- ut_assert_console_end();
- ut_unsilence_console(uts);
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_info, 0);
+BLOBLIST_TEST(bloblist_test_cmd_info, UTF_CONSOLE);
/* Test the 'bloblist list' command */
static int bloblist_test_cmd_list(struct unit_test_state *uts)
@@ -296,21 +291,16 @@
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
- console_record_reset_enable();
- ut_silence_console(uts);
- console_record_reset();
run_command("bloblist list", 0);
ut_assert_nextline("Address Size Tag Name");
ut_assert_nextline("%08lx %8x fff000 SPL hand-off",
(ulong)map_to_sysmem(data), TEST_SIZE);
ut_assert_nextline("%08lx %8x 202 Chrome OS vboot context",
(ulong)map_to_sysmem(data2), TEST_SIZE2);
- ut_assert_console_end();
- ut_unsilence_console(uts);
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_list, 0);
+BLOBLIST_TEST(bloblist_test_cmd_list, UTF_CONSOLE);
/* Test alignment of bloblist blobs */
static int bloblist_test_align(struct unit_test_state *uts)
diff --git a/test/boot/Makefile b/test/boot/Makefile
index 068522c..d8eded2 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -2,14 +2,19 @@
#
# Copyright 2021 Google LLC
+ifdef CONFIG_UT_BOOTSTD
obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o
obj-$(CONFIG_FIT) += image.o
-obj-$(CONFIG_MEASURED_BOOT) += measurement.o
obj-$(CONFIG_EXPO) += expo.o
obj-$(CONFIG_CEDIT) += cedit.o
+endif
+
+obj-$(CONFIG_MEASURED_BOOT) += measurement.o
ifdef CONFIG_OF_LIVE
obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o
endif
obj-$(CONFIG_BOOTMETH_VBE) += vbe_fixup.o
+
+obj-$(CONFIG_UPL) += upl.o
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 1bf5929..c635d06 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -16,19 +16,11 @@
#include <test/ut.h>
#include "bootstd_common.h"
-/* Allow reseting the USB-started flag */
-#if defined(CONFIG_USB_HOST) || defined(CONFIG_USB_GADGET)
-extern bool usb_started;
-#else
-#include <usb.h>
-#endif
-
/* Check 'bootdev list' command */
static int bootdev_test_cmd_list(struct unit_test_state *uts)
{
int probed;
- console_record_reset_enable();
for (probed = 0; probed < 2; probed++) {
int probe_ch = probed ? '+' : ' ';
@@ -49,7 +41,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_list, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_cmd_list, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootdev select' and 'info' commands */
static int bootdev_test_cmd_select(struct unit_test_state *uts)
@@ -59,7 +51,6 @@
/* get access to the CLI's cur_bootdev */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
ut_asserteq(1, run_command("bootdev info", 0));
ut_assert_nextlinen("Please use");
ut_assert_console_end();
@@ -99,7 +90,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_select, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_cmd_select, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check bootdev labels */
static int bootdev_test_labels(struct unit_test_state *uts)
@@ -131,8 +122,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_labels, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_labels, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV);
/* Check bootdev_find_by_any() */
static int bootdev_test_any(struct unit_test_state *uts)
@@ -158,7 +148,6 @@
* 9 [ + ] OK mmc mmc1.bootdev
* a [ ] OK mmc mmc0.bootdev
*/
- console_record_reset_enable();
ut_assertok(bootdev_find_by_any("8", &dev, &mflags));
ut_asserteq(UCLASS_BOOTDEV, device_get_uclass_id(dev));
ut_asserteq(BOOTFLOW_METHF_SINGLE_DEV, mflags);
@@ -186,8 +175,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_any, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_any, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/*
* Check bootdev ordering with the bootdev-order property and boot_targets
@@ -201,7 +190,7 @@
test_set_skip_delays(true);
/* Start up USB which gives us three additional bootdevs */
- usb_started = false;
+ bootstd_reset_usb();
ut_assertok(run_command("usb start", 0));
/*
@@ -274,7 +263,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_order, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_order, UTF_DM | UTF_SCAN_FDT);
/* Check default bootdev ordering */
static int bootdev_test_order_default(struct unit_test_state *uts)
@@ -301,7 +290,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_order_default, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_order_default, UTF_DM | UTF_SCAN_FDT);
/* Check bootdev ordering with the uclass priority */
static int bootdev_test_prio(struct unit_test_state *uts)
@@ -317,13 +306,12 @@
test_set_eth_enable(false);
/* Start up USB which gives us three additional bootdevs */
- usb_started = false;
+ bootstd_reset_usb();
ut_assertok(run_command("usb start", 0));
ut_assertok(bootstd_test_drop_bootdev_order(uts));
/* 3 MMC and 3 USB bootdevs: MMC should come before USB */
- console_record_reset_enable();
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(6, iter.num_devs);
@@ -350,20 +338,19 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_prio, UTF_DM | UTF_SCAN_FDT);
/* Check listing hunters */
static int bootdev_test_hunter(struct unit_test_state *uts)
{
struct bootstd_priv *std;
- usb_started = false;
+ bootstd_reset_usb();
test_set_skip_delays(true);
/* get access to the used hunters */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
bootdev_list_hunters(std);
ut_assert_nextline("Prio Used Uclass Hunter");
ut_assert_nextlinen("----");
@@ -390,7 +377,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunter, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunter, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootdev hunt' command */
static int bootdev_test_cmd_hunt(struct unit_test_state *uts)
@@ -398,12 +385,11 @@
struct bootstd_priv *std;
test_set_skip_delays(true);
- usb_started = false;
+ bootstd_reset_usb();
/* get access to the used hunters */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
ut_assertok(run_command("bootdev hunt -l", 0));
ut_assert_nextline("Prio Used Uclass Hunter");
ut_assert_nextlinen("----");
@@ -464,8 +450,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_hunt, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_cmd_hunt, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/* Check searching for bootdevs using the hunters */
static int bootdev_test_hunt_scan(struct unit_test_state *uts)
@@ -485,7 +471,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_scan, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_scan, UTF_DM | UTF_SCAN_FDT);
/* Check that only bootable partitions are processed */
static int bootdev_test_bootable(struct unit_test_state *uts)
@@ -522,15 +508,14 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_bootable, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_bootable, UTF_DM | UTF_SCAN_FDT);
/* Check hunting for bootdev of a particular priority */
static int bootdev_test_hunt_prio(struct unit_test_state *uts)
{
- usb_started = false;
+ bootstd_reset_usb();
test_set_skip_delays(true);
- console_record_reset_enable();
ut_assertok(bootdev_hunt_prio(BOOTDEVP_4_SCAN_FAST, false));
ut_assert_nextline("scanning bus for devices...");
ut_assert_skip_to_line(" Type: Hard Disk");
@@ -547,7 +532,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_prio, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check hunting for bootdevs with a particular label */
static int bootdev_test_hunt_label(struct unit_test_state *uts)
@@ -556,13 +541,12 @@
struct bootstd_priv *std;
int mflags;
- usb_started = false;
+ bootstd_reset_usb();
/* get access to the used hunters */
ut_assertok(bootstd_get_priv(&std));
/* scan an unknown uclass */
- console_record_reset_enable();
old = (void *)&mflags; /* arbitrary pointer to check against dev */
dev = old;
mflags = 123;
@@ -600,7 +584,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_label, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check iterating to the next label in a list */
static int bootdev_test_next_label(struct unit_test_state *uts)
@@ -627,7 +611,6 @@
dev = NULL;
mflags = 123;
ut_assertok(bootdev_next_label(&iter, &dev, &mflags));
- console_record_reset_enable();
ut_assert_console_end();
ut_assertnonnull(dev);
ut_asserteq_str("mmc0.bootdev", dev->name);
@@ -677,8 +660,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_next_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV | UT_TESTF_SF_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_next_label, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_SF_BOOTDEV | UTF_CONSOLE);
/* Check iterating to the next prioirty in a list */
static int bootdev_test_next_prio(struct unit_test_state *uts)
@@ -703,7 +686,6 @@
iter.flags = BOOTFLOWIF_SHOW;
dev = NULL;
- console_record_reset_enable();
ut_assertok(bootdev_next_prio(&iter, &dev));
ut_assertnonnull(dev);
ut_asserteq_str("mmc2.bootdev", dev->name);
@@ -762,5 +744,5 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_next_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_SF_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_next_prio, UTF_DM | UTF_SCAN_FDT | UTF_SF_BOOTDEV |
+ UTF_CONSOLE);
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 8b46256..6ad63af 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -50,7 +50,6 @@
/* Check 'bootflow scan/list' commands */
static int bootflow_cmd(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan -lH", 0));
@@ -76,14 +75,13 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan' with a label / seq */
static int bootflow_cmd_label(struct unit_test_state *uts)
{
test_set_eth_enable(false);
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH mmc1", 0));
ut_assert_nextline("Scanning for bootflows with label 'mmc1'");
ut_assert_skip_to_line("(1 bootflow, 1 valid)");
@@ -123,15 +121,14 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootflow_cmd_label, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/* Check 'bootflow scan/list' commands using all bootdevs */
static int bootflow_cmd_glob(struct unit_test_state *uts)
{
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
@@ -156,14 +153,13 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_glob, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_glob, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -e' */
static int bootflow_cmd_scan_e(struct unit_test_state *uts)
{
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -aleGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
@@ -207,12 +203,11 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_scan_e, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_scan_e, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow info' */
static int bootflow_cmd_info(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan", 0));
@@ -248,12 +243,11 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_info, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_info, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -b' to boot the first available bootdev */
static int bootflow_scan_boot(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(inject_response(uts));
ut_assertok(run_command("bootflow scan -b", 0));
ut_assert_nextline(
@@ -270,7 +264,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_scan_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check iterating through available bootflows */
static int bootflow_iter(struct unit_test_state *uts)
@@ -368,7 +362,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_iter, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_iter, UTF_DM | UTF_SCAN_FDT);
#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL)
/* Check using the system bootdev */
@@ -386,7 +380,6 @@
/* We should get a single 'bootmgr' method right at the end */
bootstd_clear_glob();
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH", 0));
ut_assert_skip_to_line(
" 0 efi_mgr ready (none) 0 <NULL> ");
@@ -396,8 +389,8 @@
return 0;
}
-BOOTSTD_TEST(bootflow_system, UT_TESTF_DM | UT_TESTF_SCAN_PDATA |
- UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_system, UTF_DM | UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_CONSOLE);
#endif
/* Check disabling a bootmethod if it requests it */
@@ -416,7 +409,6 @@
ut_assertok(bootstd_test_drop_bootdev_order(uts));
bootstd_clear_glob();
- console_record_reset_enable();
ut_assertok(inject_response(uts));
ut_assertok(run_command("bootflow scan -lbH", 0));
@@ -438,7 +430,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_iter_disable, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_iter_disable, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan' with a bootmeth ordering including a global bootmeth */
static int bootflow_scan_glob_bootmeth(struct unit_test_state *uts)
@@ -452,7 +444,6 @@
* Make sure that the -G flag makes the scan fail, since this is not
* supported when an ordering is provided
*/
- console_record_reset_enable();
ut_assertok(bootmeth_set_order("efi firmware0"));
ut_assertok(run_command("bootflow scan -lGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
@@ -479,12 +470,12 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_glob_bootmeth, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_scan_glob_bootmeth, UTF_DM | UTF_SCAN_FDT |
+ UTF_CONSOLE);
/* Check 'bootflow boot' to boot a selected bootflow */
static int bootflow_cmd_boot(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan", 0));
@@ -508,7 +499,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* prep_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
@@ -585,7 +576,6 @@
ut_assertok(prep_mmc_bootdev(uts, mmc_dev, bind_cros, &old_order));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
ut_assert_console_end();
@@ -613,7 +603,6 @@
ut_assertok(prep_mmc_bootdev(uts, mmc_dev, true, &old_order));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
/* Android bootflow might print one or two 'ANDROID:*' logs */
ut_check_skipline(uts);
@@ -675,7 +664,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_menu, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -m' to select a bootflow using a menu */
static int bootflow_scan_menu(struct unit_test_state *uts)
@@ -723,8 +712,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_menu,
- UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+BOOTSTD_TEST(bootflow_scan_menu, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -mb' to select and boot a bootflow using a menu */
static int bootflow_scan_menu_boot(struct unit_test_state *uts)
@@ -770,8 +758,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_menu_boot,
- UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+BOOTSTD_TEST(bootflow_scan_menu_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check searching for a single bootdev using the hunters */
static int bootflow_cmd_hunt_single(struct unit_test_state *uts)
@@ -783,7 +770,6 @@
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -l mmc1", 0));
ut_assert_nextline("Scanning for bootflows with label 'mmc1'");
ut_assert_skip_to_line("(1 bootflow, 1 valid)");
@@ -794,7 +780,8 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_hunt_single, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_hunt_single, UTF_DM | UTF_SCAN_FDT |
+ UTF_CONSOLE);
/* Check searching for a uclass label using the hunters */
static int bootflow_cmd_hunt_label(struct unit_test_state *uts)
@@ -808,7 +795,6 @@
test_set_eth_enable(false);
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -l mmc", 0));
/* check that the hunter was used */
@@ -831,7 +817,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_hunt_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_hunt_label, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* check_font() - Check that the font size for an item matches expectations
@@ -891,7 +877,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_menu_theme, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_menu_theme, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* check_arg() - Check both the normal case and the buffer-overflow case
@@ -1127,7 +1113,6 @@
{
ut_assertok(run_command("bootflow scan mmc", 0));
ut_assertok(run_command("bootflow sel 0", 0));
- console_record_reset_enable();
ut_asserteq(1, run_command("bootflow cmdline get fred", 0));
ut_assert_nextline("Argument not found");
@@ -1151,13 +1136,11 @@
ut_asserteq(0, run_command("bootflow cmdline set mary abc", 0));
ut_asserteq(0, run_command("bootflow cmdline set mary", 0));
- ut_assert_nextline_empty();
-
ut_assert_console_end();
return 0;
}
-BOOTSTD_TEST(bootflow_cmdline, 0);
+BOOTSTD_TEST(bootflow_cmdline, UTF_CONSOLE);
/* test a few special changes to a long command line */
static int bootflow_cmdline_special(struct unit_test_state *uts)
@@ -1198,7 +1181,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cros, 0);
+BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE);
/* Test Android bootmeth */
static int bootflow_android(struct unit_test_state *uts)
@@ -1221,4 +1204,4 @@
return 0;
}
-BOOTSTD_TEST(bootflow_android, 0);
+BOOTSTD_TEST(bootflow_android, UTF_CONSOLE);
diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c
index 113b789..518d99c 100644
--- a/test/boot/bootmeth.c
+++ b/test/boot/bootmeth.c
@@ -16,7 +16,6 @@
/* Check 'bootmeth list' command */
static int bootmeth_cmd_list(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootmeth list", 0));
ut_assert_nextline("Order Seq Name Description");
ut_assert_nextlinen("---");
@@ -31,13 +30,12 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_list, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_list, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeth order' command */
static int bootmeth_cmd_order(struct unit_test_state *uts)
{
/* Select just one bootmethod */
- console_record_reset_enable();
ut_assertok(run_command("bootmeth order extlinux", 0));
ut_assert_console_end();
ut_assertnonnull(env_get("bootmeths"));
@@ -104,7 +102,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_order, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_order, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeth order' command with global bootmeths */
static int bootmeth_cmd_order_glob(struct unit_test_state *uts)
@@ -112,7 +110,6 @@
if (!IS_ENABLED(CONFIG_BOOTMETH_GLOBAL))
return -EAGAIN;
- console_record_reset_enable();
ut_assertok(run_command("bootmeth order \"efi firmware0\"", 0));
ut_assert_console_end();
ut_assertok(run_command("bootmeth list", 0));
@@ -128,7 +125,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_order_glob, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_order_glob, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeths' env var */
static int bootmeth_env(struct unit_test_state *uts)
@@ -138,7 +135,6 @@
ut_assertok(bootstd_get_priv(&std));
/* Select just one bootmethod */
- console_record_reset_enable();
ut_assertok(env_set("bootmeths", "extlinux"));
ut_asserteq(1, std->bootmeth_count);
@@ -154,7 +150,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_env, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_env, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check the get_state_desc() method */
static int bootmeth_state(struct unit_test_state *uts)
@@ -170,4 +166,4 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_state, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_state, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c
index e505395..ff8ed23 100644
--- a/test/boot/bootstd_common.c
+++ b/test/boot/bootstd_common.c
@@ -11,6 +11,7 @@
#include <dm.h>
#include <memalign.h>
#include <mmc.h>
+#include <usb.h>
#include <linux/log2.h>
#include <test/suites.h>
#include <test/ut.h>
@@ -88,6 +89,11 @@
return 0;
}
+void bootstd_reset_usb(void)
+{
+ usb_started = false;
+}
+
int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct unit_test *tests = UNIT_TEST_SUITE_START(bootstd_test);
diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h
index 4a126e4..e29036c 100644
--- a/test/boot/bootstd_common.h
+++ b/test/boot/bootstd_common.h
@@ -53,4 +53,12 @@
*/
int bootstd_test_check_mmc_hunter(struct unit_test_state *uts);
+/**
+ * bootstd_reset_usb() - Reset the USB subsystem
+ *
+ * Resets USB so that it can be started (and scanning) again. This is useful in
+ * tests which need to use USB.
+ */
+void bootstd_reset_usb(void);
+
#endif
diff --git a/test/boot/cedit.c b/test/boot/cedit.c
index fd19da0..1f7af8e 100644
--- a/test/boot/cedit.c
+++ b/test/boot/cedit.c
@@ -25,8 +25,6 @@
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
- console_record_reset_enable();
-
/*
* ^N Move down to second menu
* ^M Open menu
@@ -52,7 +50,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_base, 0);
+BOOTSTD_TEST(cedit_base, UTF_CONSOLE);
/* Check the cedit write_fdt and read_fdt commands */
static int cedit_fdt(struct unit_test_state *uts)
@@ -70,7 +68,6 @@
void *fdt;
int i;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -122,7 +119,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_fdt, 0);
+BOOTSTD_TEST(cedit_fdt, UTF_CONSOLE);
/* Check the cedit write_env and read_env commands */
static int cedit_env(struct unit_test_state *uts)
@@ -134,7 +131,6 @@
struct scene *scn;
char *str;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -177,7 +173,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_env, 0);
+BOOTSTD_TEST(cedit_env, UTF_CONSOLE);
/* Check the cedit write_cmos and read_cmos commands */
static int cedit_cmos(struct unit_test_state *uts)
@@ -187,7 +183,6 @@
extern struct expo *cur_exp;
struct scene *scn;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -218,4 +213,4 @@
return 0;
}
-BOOTSTD_TEST(cedit_cmos, 0);
+BOOTSTD_TEST(cedit_cmos, UTF_CONSOLE);
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 6ea0184..9b4aa80 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -114,7 +114,7 @@
return 0;
}
-BOOTSTD_TEST(expo_base, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_base, UTF_DM | UTF_SCAN_FDT);
/* Check creating a scene */
static int expo_scene(struct unit_test_state *uts)
@@ -165,7 +165,7 @@
return 0;
}
-BOOTSTD_TEST(expo_scene, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_scene, UTF_DM | UTF_SCAN_FDT);
/* Check creating a scene with objects */
static int expo_object(struct unit_test_state *uts)
@@ -225,7 +225,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object, UTF_DM | UTF_SCAN_FDT);
/* Check setting object attributes and using themes */
static int expo_object_attr(struct unit_test_state *uts)
@@ -286,7 +286,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object_attr, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object_attr, UTF_DM | UTF_SCAN_FDT);
/**
* struct test_iter_priv - private data for expo-iterator test
@@ -432,7 +432,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object_menu, UTF_DM | UTF_SCAN_FDT);
/* Check rendering a scene */
static int expo_render_image(struct unit_test_state *uts)
@@ -445,7 +445,6 @@
struct expo *exp;
int id;
- console_record_reset_enable();
ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
ut_assertok(expo_new(EXPO_NAME, NULL, &exp));
@@ -633,7 +632,7 @@
return 0;
}
-BOOTSTD_TEST(expo_render_image, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_render_image, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check building an expo from a devicetree description */
static int expo_test_build(struct unit_test_state *uts)
@@ -703,13 +702,11 @@
txt = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE);
ut_asserteq_str("2 GHz", expo_get_str(exp, txt->str_id));
- count = 0;
- list_for_each_entry(item, &menu->item_head, sibling)
- count++;
+ count = list_count_nodes(&menu->item_head);
ut_asserteq(3, count);
expo_destroy(exp);
return 0;
}
-BOOTSTD_TEST(expo_test_build, UT_TESTF_DM);
+BOOTSTD_TEST(expo_test_build, UTF_DM);
diff --git a/test/boot/upl.c b/test/boot/upl.c
new file mode 100644
index 0000000..99f02b7
--- /dev/null
+++ b/test/boot/upl.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff testing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <abuf.h>
+#include <mapmem.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include <test/suites.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include "bootstd_common.h"
+
+/* Declare a new upl test */
+#define UPL_TEST(_name, _flags) UNIT_TEST(_name, _flags, upl_test)
+
+static int add_region(struct unit_test_state *uts, struct alist *lst,
+ ulong base, ulong size)
+{
+ struct memregion region;
+
+ region.base = base;
+ region.size = size;
+ ut_assertnonnull(alist_add(lst, region));
+
+ return 0;
+}
+
+int upl_get_test_data(struct unit_test_state *uts, struct upl *upl)
+{
+ struct upl_memmap memmap;
+ struct upl_memres memres;
+ struct upl_image img;
+ struct upl_mem mem;
+
+ upl_init(upl);
+
+ upl->addr_cells = 1;
+ upl->size_cells = 1;
+ upl->smbios = 0x123;
+ upl->acpi = 0x456;
+ upl->bootmode = BIT(UPLBM_DEFAULT) | BIT(UPLBM_S3);
+ upl->fit = 0x789;
+ upl->conf_offset = 0x234;
+ upl->addr_width = 46;
+ upl->acpi_nvs_size = 0x100;
+
+ /* image[0] */
+ img.load = 0x1;
+ img.size = 0x2;
+ img.offset = 0x3;
+ img.description = "U-Boot";
+ ut_assertnonnull(alist_add(&upl->image, img));
+
+ /* image[1] */
+ img.load = 0x4;
+ img.size = 0x5;
+ img.offset = 0x6;
+ img.description = "ATF";
+ ut_assertnonnull(alist_add(&upl->image, img));
+
+ /* mem[0] : 3 regions */
+ memset(&mem, '\0', sizeof(mem));
+ alist_init_struct(&mem.region, struct memregion);
+ ut_assertok(add_region(uts, &mem.region, 0x10, 0x20));
+ ut_assertok(add_region(uts, &mem.region, 0x30, 0x40));
+ ut_assertok(add_region(uts, &mem.region, 0x40, 0x50));
+ ut_assertnonnull(alist_add(&upl->mem, mem));
+
+ /* mem[0] : 1 region */
+ alist_init_struct(&mem.region, struct memregion);
+ ut_assertok(add_region(uts, &mem.region, 0x70, 0x80));
+ mem.hotpluggable = true;
+ ut_assertnonnull(alist_add(&upl->mem, mem));
+ mem.hotpluggable = false;
+
+ /* memmap[0] : 5 regions */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "acpi";
+ memmap.usage = BIT(UPLUS_ACPI_RECLAIM);
+ ut_assertok(add_region(uts, &memmap.region, 0x11, 0x12));
+ ut_assertok(add_region(uts, &memmap.region, 0x13, 0x14));
+ ut_assertok(add_region(uts, &memmap.region, 0x15, 0x16));
+ ut_assertok(add_region(uts, &memmap.region, 0x17, 0x18));
+ ut_assertok(add_region(uts, &memmap.region, 0x19, 0x1a));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[1] : 1 region */
+ memmap.name = "u-boot";
+ memmap.usage = BIT(UPLUS_BOOT_DATA);
+ alist_init_struct(&memmap.region, struct memregion);
+ ut_assertok(add_region(uts, &memmap.region, 0x21, 0x22));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[2] : 1 region */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "efi";
+ memmap.usage = BIT(UPLUS_RUNTIME_CODE);
+ ut_assertok(add_region(uts, &memmap.region, 0x23, 0x24));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[3]: 2 regions */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "empty";
+ memmap.usage = 0;
+ ut_assertok(add_region(uts, &memmap.region, 0x25, 0x26));
+ ut_assertok(add_region(uts, &memmap.region, 0x27, 0x28));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[4]: 1 region */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "acpi-things";
+ memmap.usage = BIT(UPLUS_RUNTIME_CODE) | BIT(UPLUS_ACPI_NVS);
+ ut_assertok(add_region(uts, &memmap.region, 0x29, 0x2a));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memres[0]: 1 region */
+ alist_init_struct(&memres.region, struct memregion);
+ memset(&memres, '\0', sizeof(memres));
+ memres.name = "mmio";
+ ut_assertok(add_region(uts, &memres.region, 0x2b, 0x2c));
+ ut_assertnonnull(alist_add(&upl->memres, memres));
+
+ /* memres[1]: 2 regions */
+ alist_init_struct(&memres.region, struct memregion);
+ memres.name = "memory";
+ ut_assertok(add_region(uts, &memres.region, 0x2d, 0x2e));
+ ut_assertok(add_region(uts, &memres.region, 0x2f, 0x30));
+ memres.no_map = true;
+ ut_assertnonnull(alist_add(&upl->memres, memres));
+
+ upl->serial.compatible = "ns16550a";
+ upl->serial.clock_frequency = 1843200;
+ upl->serial.current_speed = 115200;
+ alist_init_struct(&upl->serial.reg, struct memregion);
+ ut_assertok(add_region(uts, &upl->serial.reg, 0xf1de0000, 0x100));
+ upl->serial.reg_io_shift = 2;
+ upl->serial.reg_offset = 0x40;
+ upl->serial.reg_io_width = 1;
+ upl->serial.virtual_reg = 0x20000000;
+ upl->serial.access_type = UPLSAT_MMIO;
+
+ alist_init_struct(&upl->graphics.reg, struct memregion);
+ ut_assertok(add_region(uts, &upl->graphics.reg, 0xd0000000, 0x10000000));
+ upl->graphics.width = 1280;
+ upl->graphics.height = 1280;
+ upl->graphics.stride = upl->graphics.width * 4;
+ upl->graphics.format = UPLGF_ARGB32;
+
+ return 0;
+}
+
+static int compare_upl_image(struct unit_test_state *uts,
+ const struct upl_image *base,
+ const struct upl_image *cmp)
+{
+ ut_asserteq(base->load, cmp->load);
+ ut_asserteq(base->size, cmp->size);
+ ut_asserteq(base->offset, cmp->offset);
+ ut_asserteq_str(base->description, cmp->description);
+
+ return 0;
+}
+
+static int compare_upl_memregion(struct unit_test_state *uts,
+ const struct memregion *base,
+ const struct memregion *cmp)
+{
+ ut_asserteq(base->base, cmp->base);
+ ut_asserteq(base->size, cmp->size);
+
+ return 0;
+}
+
+static int compare_upl_mem(struct unit_test_state *uts,
+ const struct upl_mem *base,
+ const struct upl_mem *cmp)
+{
+ int i;
+
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->hotpluggable, cmp->hotpluggable);
+ for (i = 0; i < base->region.count; i++) {
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+ }
+
+ return 0;
+}
+
+static int check_device_name(struct unit_test_state *uts, const char *base,
+ const char *cmp)
+{
+ const char *p;
+
+ p = strchr(cmp, '@');
+ if (p) {
+ ut_assertnonnull(p);
+ ut_asserteq_strn(base, cmp);
+ ut_asserteq(p - cmp, strlen(base));
+ } else {
+ ut_asserteq_str(base, cmp);
+ }
+
+ return 0;
+}
+
+static int compare_upl_memmap(struct unit_test_state *uts,
+ const struct upl_memmap *base,
+ const struct upl_memmap *cmp)
+{
+ int i;
+
+ ut_assertok(check_device_name(uts, base->name, cmp->name));
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->usage, cmp->usage);
+ for (i = 0; i < base->region.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+
+ return 0;
+}
+
+static int compare_upl_memres(struct unit_test_state *uts,
+ const struct upl_memres *base,
+ const struct upl_memres *cmp)
+{
+ int i;
+
+ ut_assertok(check_device_name(uts, base->name, cmp->name));
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->no_map, cmp->no_map);
+ for (i = 0; i < base->region.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+
+ return 0;
+}
+
+static int compare_upl_serial(struct unit_test_state *uts,
+ struct upl_serial *base, struct upl_serial *cmp)
+{
+ int i;
+
+ ut_asserteq_str(base->compatible, cmp->compatible);
+ ut_asserteq(base->clock_frequency, cmp->clock_frequency);
+ ut_asserteq(base->current_speed, cmp->current_speed);
+ for (i = 0; i < base->reg.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->reg, i, struct memregion),
+ alist_get(&cmp->reg, i, struct memregion)));
+ ut_asserteq(base->reg_io_shift, cmp->reg_io_shift);
+ ut_asserteq(base->reg_offset, cmp->reg_offset);
+ ut_asserteq(base->reg_io_width, cmp->reg_io_width);
+ ut_asserteq(base->virtual_reg, cmp->virtual_reg);
+ ut_asserteq(base->access_type, cmp->access_type);
+
+ return 0;
+}
+
+static int compare_upl_graphics(struct unit_test_state *uts,
+ struct upl_graphics *base,
+ struct upl_graphics *cmp)
+{
+ int i;
+
+ for (i = 0; i < base->reg.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->reg, i, struct memregion),
+ alist_get(&cmp->reg, i, struct memregion)));
+ ut_asserteq(base->width, cmp->width);
+ ut_asserteq(base->height, cmp->height);
+ ut_asserteq(base->stride, cmp->stride);
+ ut_asserteq(base->format, cmp->format);
+
+ return 0;
+}
+
+static int compare_upl(struct unit_test_state *uts, struct upl *base,
+ struct upl *cmp)
+{
+ int i;
+
+ ut_asserteq(base->addr_cells, cmp->addr_cells);
+ ut_asserteq(base->size_cells, cmp->size_cells);
+
+ ut_asserteq(base->smbios, cmp->smbios);
+ ut_asserteq(base->acpi, cmp->acpi);
+ ut_asserteq(base->bootmode, cmp->bootmode);
+ ut_asserteq(base->fit, cmp->fit);
+ ut_asserteq(base->conf_offset, cmp->conf_offset);
+ ut_asserteq(base->addr_width, cmp->addr_width);
+ ut_asserteq(base->acpi_nvs_size, cmp->acpi_nvs_size);
+
+ ut_asserteq(base->image.count, cmp->image.count);
+ for (i = 0; i < base->image.count; i++)
+ ut_assertok(compare_upl_image(uts,
+ alist_get(&base->image, i, struct upl_image),
+ alist_get(&cmp->image, i, struct upl_image)));
+
+ ut_asserteq(base->mem.count, cmp->mem.count);
+ for (i = 0; i < base->mem.count; i++)
+ ut_assertok(compare_upl_mem(uts,
+ alist_get(&base->mem, i, struct upl_mem),
+ alist_get(&cmp->mem, i, struct upl_mem)));
+
+ ut_asserteq(base->memmap.count, cmp->memmap.count);
+ for (i = 0; i < base->memmap.count; i++)
+ ut_assertok(compare_upl_memmap(uts,
+ alist_get(&base->memmap, i, struct upl_memmap),
+ alist_get(&cmp->memmap, i, struct upl_memmap)));
+
+ ut_asserteq(base->memres.count, cmp->memres.count);
+ for (i = 0; i < base->memres.count; i++)
+ ut_assertok(compare_upl_memres(uts,
+ alist_get(&base->memres, i, struct upl_memres),
+ alist_get(&cmp->memres, i, struct upl_memres)));
+
+ ut_assertok(compare_upl_serial(uts, &base->serial, &cmp->serial));
+ ut_assertok(compare_upl_graphics(uts, &base->graphics, &cmp->graphics));
+
+ return 0;
+}
+
+/* Basic test of writing and reading UPL handoff */
+static int upl_test_base(struct unit_test_state *uts)
+{
+ oftree tree, check_tree;
+ struct upl upl, check;
+ struct abuf buf;
+
+ if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE))
+ return -EAGAIN; /* skip test */
+ ut_assertok(upl_get_test_data(uts, &upl));
+
+ ut_assertok(upl_create_handoff_tree(&upl, &tree));
+ ut_assertok(oftree_to_fdt(tree, &buf));
+
+ /*
+ * strings in check_tree and therefore check are only valid so long as
+ * buf stays around. As soon as we call abuf_uninit they go away
+ */
+ check_tree = oftree_from_fdt(abuf_data(&buf));
+ ut_assert(ofnode_valid(oftree_path(check_tree, "/")));
+
+ ut_assertok(upl_read_handoff(&check, check_tree));
+ ut_assertok(compare_upl(uts, &upl, &check));
+ abuf_uninit(&buf);
+
+ return 0;
+}
+UPL_TEST(upl_test_base, 0);
+
+/* Test 'upl info' command */
+static int upl_test_info(struct unit_test_state *uts)
+{
+ gd_set_upl(NULL);
+ ut_assertok(run_command("upl info", 0));
+ ut_assert_nextline("UPL state: inactive");
+ ut_assert_console_end();
+
+ gd_set_upl((struct upl *)uts); /* set it to any non-zero value */
+ ut_assertok(run_command("upl info", 0));
+ ut_assert_nextline("UPL state: active");
+ ut_assert_console_end();
+ gd_set_upl(NULL);
+
+ return 0;
+}
+UPL_TEST(upl_test_info, UTF_CONSOLE);
+
+/* Test 'upl read' and 'upl_write' commands */
+static int upl_test_read_write(struct unit_test_state *uts)
+{
+ ulong addr;
+
+ if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE))
+ return -EAGAIN; /* skip test */
+ ut_assertok(run_command("upl write", 0));
+
+ addr = env_get_hex("upladdr", 0);
+ ut_assert_nextline("UPL handoff written to %lx size %lx", addr,
+ env_get_hex("uplsize", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("upl read ${upladdr}", 0));
+ ut_assert_nextline("Reading UPL at %lx", addr);
+ ut_assert_console_end();
+
+ return 0;
+}
+UPL_TEST(upl_test_read_write, UTF_CONSOLE);
+
+/* Test UPL passthrough */
+static int upl_test_info_norun(struct unit_test_state *uts)
+{
+ const struct upl_image *img;
+ struct upl *upl = gd_upl();
+ const void *fit;
+
+ ut_assertok(run_command("upl info -v", 0));
+ ut_assert_nextline("UPL state: active");
+ ut_assert_nextline("fit %lx", upl->fit);
+ ut_assert_nextline("conf_offset %x", upl->conf_offset);
+ ut_assert_nextlinen("image 0");
+ ut_assert_nextlinen("image 1");
+ ut_assert_console_end();
+
+ /* check the offsets */
+ fit = map_sysmem(upl->fit, 0);
+ ut_asserteq_str("conf-1", fdt_get_name(fit, upl->conf_offset, NULL));
+
+ ut_asserteq(2, upl->image.count);
+
+ img = alist_get(&upl->image, 1, struct upl_image);
+ ut_asserteq_str("firmware-1", fdt_get_name(fit, img->offset, NULL));
+ ut_asserteq(CONFIG_TEXT_BASE, img->load);
+
+ return 0;
+}
+UPL_TEST(upl_test_info_norun, UTF_CONSOLE | UTF_MANUAL);
+
+int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(upl_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(upl_test);
+
+ return cmd_ut_category("cmd_upl", "cmd_upl_", tests, n_ents, argc,
+ argv);
+}
diff --git a/test/boot/vbe_fixup.c b/test/boot/vbe_fixup.c
index 540816e..5bc026d 100644
--- a/test/boot/vbe_fixup.c
+++ b/test/boot/vbe_fixup.c
@@ -51,5 +51,5 @@
return 0;
}
-BOOTSTD_TEST(vbe_test_fixup_norun, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_FLAT_TREE | UT_TESTF_MANUAL);
+BOOTSTD_TEST(vbe_test_fixup_norun, UTF_DM | UTF_SCAN_FDT | UTF_FLAT_TREE |
+ UTF_MANUAL);
diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c
index 3672b74..4fe4323 100644
--- a/test/boot/vbe_simple.c
+++ b/test/boot/vbe_simple.c
@@ -85,4 +85,4 @@
return 0;
}
-BOOTSTD_TEST(vbe_simple_test_base, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(vbe_simple_test_base, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 478ef4c..8f21349 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -30,7 +30,7 @@
obj-$(CONFIG_CMD_MBR) += mbr.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_CMD_WGET) += wget.o
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
-obj-$(CONFIG_CMD_WGET) += wget.o
diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c
index 7b8f49f..b34be89 100644
--- a/test/cmd/addrmap.c
+++ b/test/cmd/addrmap.c
@@ -15,7 +15,6 @@
/* Test 'addrmap' command output */
static int addrmap_test_basic(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("addrmap", 0));
ut_assert_nextline(" vaddr paddr size");
ut_assert_nextline("================ ================ ================");
@@ -24,7 +23,7 @@
return 0;
}
-ADDRMAP_TEST(addrmap_test_basic, UT_TESTF_CONSOLE_REC);
+ADDRMAP_TEST(addrmap_test_basic, UTF_CONSOLE);
int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c
index 38f40b7..fd578f3 100644
--- a/test/cmd/armffa.c
+++ b/test/cmd/armffa.c
@@ -28,5 +28,4 @@
return 0;
}
-
-DM_TEST(dm_test_armffa_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_armffa_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
index 027848c..770b3bf 100644
--- a/test/cmd/bdinfo.c
+++ b/test/cmd/bdinfo.c
@@ -5,6 +5,7 @@
* Copyright 2023 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
+#include <alist.h>
#include <console.h>
#include <mapmem.h>
#include <asm/global_data.h>
@@ -99,44 +100,39 @@
}
static int lmb_test_dump_region(struct unit_test_state *uts,
- struct lmb_region *rgn, char *name)
+ struct alist *lmb_rgn_lst, char *name)
{
+ struct lmb_region *rgn = lmb_rgn_lst->data;
unsigned long long base, size, end;
enum lmb_flags flags;
int i;
- ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, rgn->max);
+ ut_assert_nextline(" %s.count = 0x%hx", name, lmb_rgn_lst->count);
- for (i = 0; i < rgn->cnt; i++) {
- base = rgn->region[i].base;
- size = rgn->region[i].size;
+ for (i = 0; i < lmb_rgn_lst->count; i++) {
+ base = rgn[i].base;
+ size = rgn[i].size;
end = base + size - 1;
- flags = rgn->region[i].flags;
+ flags = rgn[i].flags;
- /*
- * this entry includes the stack (get_sp()) on many platforms
- * so will different each time lmb_init_and_reserve() is called.
- * We could instead have the bdinfo command put its lmb region
- * in a known location, so we can check it directly, rather than
- * calling lmb_init_and_reserve() to create a new (and hopefully
- * identical one). But for now this seems good enough.
- */
if (!IS_ENABLED(CONFIG_SANDBOX) && i == 3) {
ut_assert_nextlinen(" %s[%d]\t[", name, i);
continue;
}
- ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x",
- name, i, base, end, size, flags);
+ ut_assert_nextlinen(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: ",
+ name, i, base, end, size);
}
return 0;
}
-static int lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb)
+static int lmb_test_dump_all(struct unit_test_state *uts)
{
+ struct lmb *lmb = lmb_get();
+
ut_assert_nextline("lmb_dump_all:");
- ut_assertok(lmb_test_dump_region(uts, &lmb->memory, "memory"));
- ut_assertok(lmb_test_dump_region(uts, &lmb->reserved, "reserved"));
+ ut_assertok(lmb_test_dump_region(uts, &lmb->free_mem, "memory"));
+ ut_assertok(lmb_test_dump_region(uts, &lmb->used_mem, "reserved"));
return 0;
}
@@ -185,9 +181,6 @@
ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234));
ut_assertok(test_num_l(uts, "fdt_blob",
(ulong)map_to_sysmem(gd->fdt_blob)));
- ut_assertok(test_num_l(uts, "new_fdt",
- (ulong)map_to_sysmem(gd->new_fdt)));
- ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size));
if (IS_ENABLED(CONFIG_VIDEO))
ut_assertok(test_video_info(uts));
@@ -198,10 +191,7 @@
#endif
if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) {
- struct lmb lmb;
-
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
- ut_assertok(lmb_test_dump_all(uts, &lmb));
+ ut_assertok(lmb_test_dump_all(uts));
if (IS_ENABLED(CONFIG_OF_REAL))
ut_assert_nextline("devicetree = %s", fdtdec_get_srcname());
}
@@ -235,22 +225,19 @@
static int bdinfo_test_full(struct unit_test_state *uts)
{
/* Test BDINFO full print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo"));
ut_assertok(bdinfo_test_all(uts));
ut_assertok(run_commandf("bdinfo -a"));
ut_assertok(bdinfo_test_all(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_full, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_full, UTF_CONSOLE);
static int bdinfo_test_help(struct unit_test_state *uts)
{
/* Test BDINFO unknown option help text print */
- ut_assertok(console_record_reset_enable());
if (!CONFIG_IS_ENABLED(GETOPT)) {
ut_asserteq(0, run_commandf("bdinfo -h"));
ut_assertok(bdinfo_test_all(uts));
@@ -262,44 +249,39 @@
ut_assert_nextlinen("Usage:");
ut_assert_nextlinen("bdinfo");
}
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_help, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_help, UTF_CONSOLE);
static int bdinfo_test_memory(struct unit_test_state *uts)
{
/* Test BDINFO memory layout only print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo -m"));
if (!CONFIG_IS_ENABLED(GETOPT))
ut_assertok(bdinfo_test_all(uts));
else
ut_assertok(bdinfo_check_mem(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_memory, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_memory, UTF_CONSOLE);
static int bdinfo_test_eth(struct unit_test_state *uts)
{
/* Test BDINFO ethernet settings only print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo -e"));
if (!CONFIG_IS_ENABLED(GETOPT))
ut_assertok(bdinfo_test_all(uts));
else if (IS_ENABLED(CONFIG_CMD_NET))
ut_assertok(test_eth(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_eth, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_eth, UTF_CONSOLE);
int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/exit.c b/test/cmd/exit.c
index d310ec8..af58a57 100644
--- a/test/cmd/exit.c
+++ b/test/cmd/exit.c
@@ -33,96 +33,83 @@
* - return value can be printed outside of 'run' command
*/
for (i = -3; i <= 3; i++) {
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo ; echo $?", i));
ut_assert_nextline("bar");
ut_assert_nextline("%d", i > 0 ? i : 0);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo && echo quux ; echo $?", i));
ut_assert_nextline("bar");
if (i <= 0)
ut_assert_nextline("quux");
ut_assert_nextline("%d", i > 0 ? i : 0);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo || echo quux ; echo $?", i));
ut_assert_nextline("bar");
if (i > 0)
ut_assert_nextline("quux");
/* Either 'exit' returns 0, or 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
/* Validate that 'exit' behaves the same way as 'exit 0' */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
/* Either 'exit' returns 0, or 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Validate that return value still propagates from 'run' command */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
/* The 'true' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("1");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("1");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
/* The 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-EXIT_TEST(cmd_exit_test, UT_TESTF_CONSOLE_REC);
+EXIT_TEST(cmd_exit_test, UTF_CONSOLE);
int do_ut_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index e09a929..e647851 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -28,35 +28,49 @@
/**
* make_test_fdt() - Create an FDT with just a root node
*
- * The size is set to the minimum needed
+ * The size is set to the minimum needed. This also sets the working FDT and
+ * checks that the expected output is received from doing so.
*
* @uts: Test state
* @fdt: Place to write FDT
* @size: Maximum size of space for fdt
+ * @addrp: Returns address of the devicetree
*/
-static int make_test_fdt(struct unit_test_state *uts, void *fdt, int size)
+static int make_test_fdt(struct unit_test_state *uts, void *fdt, int size,
+ ulong *addrp)
{
+ ulong addr;
+
ut_assertok(fdt_create(fdt, size));
ut_assertok(fdt_finish_reservemap(fdt));
ut_assert(fdt_begin_node(fdt, "") >= 0);
ut_assertok(fdt_end_node(fdt));
ut_assertok(fdt_finish(fdt));
+ addr = map_to_sysmem(fdt);
+ set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
+ *addrp = addr;
+
return 0;
}
/**
* make_fuller_fdt() - Create an FDT with root node and properties
*
- * The size is set to the minimum needed
+ * The size is set to the minimum needed. This also sets the working FDT and
+ * checks that the expected output is received from doing so.
*
* @uts: Test state
* @fdt: Place to write FDT
* @size: Maximum size of space for fdt
+ * @addrp: Returns address of the devicetree
*/
-static int make_fuller_fdt(struct unit_test_state *uts, void *fdt, int size)
+static int make_fuller_fdt(struct unit_test_state *uts, void *fdt, int size,
+ ulong *addrp)
{
fdt32_t regs[2] = { cpu_to_fdt32(0x1234), cpu_to_fdt32(0x1000) };
+ ulong addr;
/*
* Assemble the following DT for test purposes:
@@ -138,6 +152,11 @@
ut_assertok(fdt_end_node(fdt));
ut_assertok(fdt_finish(fdt));
+ addr = map_to_sysmem(fdt);
+ set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
+ *addrp = addr;
+
return 0;
}
@@ -149,11 +168,10 @@
ulong addr;
int ret;
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt addr -c", 0));
ut_assert_nextline("Control fdt: %08lx",
(ulong)map_to_sysmem(gd->fdt_blob));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* The working fdt is not set, so this should fail */
set_working_fdt_addr(0);
@@ -166,16 +184,13 @@
*/
if (IS_ENABLED(CONFIG_SANDBOX))
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Set up a working FDT and try again */
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
- ut_assert_nextline("Working FDT set to %lx", addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
ut_assertok(run_command("fdt addr", 0));
ut_assert_nextline("Working fdt: %08lx", (ulong)map_to_sysmem(fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Set the working FDT */
set_working_fdt_addr(0);
@@ -183,7 +198,7 @@
ut_assertok(run_commandf("fdt addr %08lx", addr));
ut_assert_nextline("Working FDT set to %lx", addr);
ut_asserteq(addr, map_to_sysmem(working_fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
set_working_fdt_addr(0);
ut_assert_nextline("Working FDT set to 0");
@@ -195,13 +210,13 @@
gd->fdt_blob = fdt_blob;
ut_assertok(ret);
ut_asserteq(addr, map_to_sysmem(new_fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting an invalid FDT */
fdt[0] = 123;
ut_asserteq(1, run_commandf("fdt addr %08lx", addr));
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test detecting an invalid FDT */
fdt[0] = 123;
@@ -209,11 +224,11 @@
ut_assert_nextline("Working FDT set to %lx", addr);
ut_asserteq(1, run_commandf("fdt addr"));
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_addr, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_addr, UTF_CONSOLE);
/* Test 'fdt addr' resizing an fdt */
static int fdt_test_addr_resize(struct unit_test_state *uts)
@@ -222,32 +237,29 @@
const int newsize = sizeof(fdt) / 2;
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test setting and resizing the working FDT to a larger size */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt addr %08lx %x", addr, newsize));
ut_assert_nextline("Working FDT set to %lx", addr);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Try shrinking it */
ut_assertok(run_commandf("fdt addr %08lx %zx", addr, sizeof(fdt) / 4));
ut_assert_nextline("Working FDT set to %lx", addr);
ut_assert_nextline("New length %d < existing length %d, ignoring",
(int)sizeof(fdt) / 4, newsize);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* ...quietly */
ut_assertok(run_commandf("fdt addr -q %08lx %zx", addr, sizeof(fdt) / 4));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* We cannot easily provoke errors in fdt_open_into(), so ignore that */
return 0;
}
-FDT_TEST(fdt_test_addr_resize, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_addr_resize, UTF_CONSOLE);
static int fdt_test_move(struct unit_test_state *uts)
{
@@ -258,30 +270,26 @@
void *buf;
/* Original source DT */
- ut_assertok(make_test_fdt(uts, fdt, size));
+ ut_assertok(make_test_fdt(uts, fdt, size, &addr));
ts = fdt_totalsize(fdt);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Moved target DT location */
buf = map_sysmem(newaddr, size);
memset(buf, 0, size);
/* Test moving the working FDT to a new location */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt move %08lx %08lx %x", addr, newaddr, ts));
ut_assert_nextline("Working FDT set to %lx", newaddr);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Compare the source and destination DTs */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("cmp.b %08lx %08lx %x", addr, newaddr, ts));
ut_assert_nextline("Total of %d byte(s) were the same", ts);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_move, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_move, UTF_CONSOLE);
static int fdt_test_resize(struct unit_test_state *uts)
{
@@ -291,21 +299,18 @@
ulong addr;
/* Original source DT */
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 0); /* Resize with 0 extra bytes */
ts = fdt_totalsize(fdt);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test resizing the working FDT and verify the new space was added */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt resize %x", newsize));
ut_asserteq(ts + newsize, fdt_totalsize(fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_resize, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_resize, UTF_CONSOLE);
static int fdt_test_print_list_common(struct unit_test_state *uts,
const char *opc, const char *node)
@@ -314,56 +319,50 @@
* Test printing/listing the working FDT
* subnode $node/subnode
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s/subnode", opc, node));
ut_assert_nextline("subnode {");
ut_assert_nextline("\t#address-cells = <0x00000000>;");
ut_assert_nextline("\t#size-cells = <0x00000000>;");
ut_assert_nextline("\tcompatible = \"u-boot,fdt-subnode-test-device\";");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path / string property model
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s / model", opc));
ut_assert_nextline("model = \"U-Boot FDT test\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node string property compatible
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s compatible", opc, node));
ut_assert_nextline("compatible = \"u-boot,fdt-test-device1\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node stringlist property clock-names
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s clock-names", opc, node));
ut_assert_nextline("clock-names = \"fixed\", \"i2c\", \"spi\", \"uart2\", \"uart1\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node u32 property clock-frequency
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s clock-frequency", opc, node));
ut_assert_nextline("clock-frequency = <0x00fde800>");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node empty property u-boot,empty-property
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s u-boot,empty-property", opc, node));
/*
* This is the only 'fdt print' / 'fdt list' incantation which
@@ -371,16 +370,15 @@
* since the beginning of the command 'fdt', keep it.
*/
ut_assert_nextline("%s u-boot,empty-property", node);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node prop-encoded array property regs
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s regs", opc, node));
ut_assert_nextline("regs = <0x00001234 0x00001000>");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -393,12 +391,9 @@
int ret;
/* Original source DT */
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test printing/listing the working FDT -- node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s", opc));
ut_assert_nextline("/ {");
ut_assert_nextline("\t#address-cells = <0x00000001>;");
@@ -429,7 +424,7 @@
}
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ret = fdt_test_print_list_common(uts, opc, "/test-node@1234");
if (!ret)
@@ -442,13 +437,13 @@
{
return fdt_test_print_list(uts, true);
}
-FDT_TEST(fdt_test_print, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_print, UTF_CONSOLE);
static int fdt_test_list(struct unit_test_state *uts)
{
return fdt_test_print_list(uts, false);
}
-FDT_TEST(fdt_test_list, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_list, UTF_CONSOLE);
/* Test 'fdt get value' reading an fdt */
static int fdt_test_get_value_string(struct unit_test_state *uts,
@@ -456,15 +451,13 @@
const char *idx, const char *strres,
const int intres)
{
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt get value var %s %s %s",
node, prop, idx ? : ""));
- if (strres) {
+ if (strres)
ut_asserteq_str(strres, env_get("var"));
- } else {
+ else
ut_asserteq(intres, env_get_hex("var", 0x1234));
- }
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -473,16 +466,20 @@
const char *node)
{
/* Test getting default element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", NULL, "fixed", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", NULL,
+ "fixed", 0));
/* Test getting 0th element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "0", "fixed", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "0",
+ "fixed", 0));
/* Test getting 1st element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "1", "i2c", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "1",
+ "i2c", 0));
/* Test getting 2nd element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "2", "spi", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "2",
+ "spi", 0));
/*
* Test getting default element of $node node regs property.
@@ -491,29 +488,29 @@
* but only if the array is shorter than 40 characters. Anything
* longer is an error. This is a special case for handling hashes.
*/
- fdt_test_get_value_string(uts, node, "regs", NULL, "3412000000100000", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", NULL,
+ "3412000000100000", 0));
/* Test getting 0th element of $node node regs property */
- fdt_test_get_value_string(uts, node, "regs", "0", NULL, 0x1234);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", "0", NULL,
+ 0x1234));
/* Test getting 1st element of $node node regs property */
- fdt_test_get_value_string(uts, node, "regs", "1", NULL, 0x1000);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", "1", NULL,
+ 0x1000));
/* Test missing 10th element of $node node clock-names property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value ften %s clock-names 10", node));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test missing 10th element of $node node regs property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value ften %s regs 10", node));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of $node node nonexistent property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value fnone %s nonexistent", node));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -522,118 +519,97 @@
{
char fdt[4096];
ulong addr;
- int ret;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
- ret = fdt_test_get_value_common(uts, "/test-node@1234");
- if (!ret)
- ret = fdt_test_get_value_common(uts, "testnodealias");
- if (ret)
- return ret;
+ ut_assertok(fdt_test_get_value_common(uts, "/test-node@1234"));
+ ut_assertok(fdt_test_get_value_common(uts, "testnodealias"));
/* Test getting default element of /nonexistent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value fnode /nonexistent nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value vbadalias badalias nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of nonexistent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value vnoalias noalias nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_value, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_value, UTF_CONSOLE);
static int fdt_test_get_name(struct unit_test_state *uts)
{
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting name of node 0 in /, which is /aliases node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name nzero / 0", 0));
ut_asserteq_str("aliases", env_get("nzero"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 1 in /, which is /test-node@1234 node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name none / 1", 0));
ut_asserteq_str("test-node@1234", env_get("none"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node -1 in /, which is /aliases node, same as 0 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name nmone / -1", 0));
ut_asserteq_str("aliases", env_get("nmone"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 2 in /, which does not exist */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name ntwo / 2", 1));
ut_assert_nextline("libfdt node not found");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 0 in /test-node@1234, which is /subnode node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name snzero /test-node@1234 0", 0));
ut_asserteq_str("subnode", env_get("snzero"));
ut_assertok(run_command("fdt get name asnzero testnodealias 0", 0));
ut_asserteq_str("subnode", env_get("asnzero"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 1 in /test-node@1234, which does not exist */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name snone /test-node@1234 1", 1));
ut_assert_nextline("libfdt node not found");
ut_asserteq(1, run_command("fdt get name asnone testnodealias 1", 1));
ut_assert_nextline("libfdt node not found");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node -1 in /test-node@1234, which is /subnode node, same as 0 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name snmone /test-node@1234 -1", 0));
ut_asserteq_str("subnode", env_get("snmone"));
ut_assertok(run_command("fdt get name asnmone testnodealias -1", 0));
ut_asserteq_str("subnode", env_get("asnmone"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of nonexistent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name nonode /nonexistent 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name vbadalias badalias 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of nonexistent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name vnoalias noalias 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_name, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_name, UTF_CONSOLE);
static int fdt_test_get_addr_common(struct unit_test_state *uts, char *fdt,
const char *path, const char *prop)
@@ -649,11 +625,10 @@
ut_assertnonnull(prop_ptr);
offset = (char *)prop_ptr - fdt;
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt get addr pstr %s %s", path, prop));
ut_asserteq((ulong)map_sysmem(env_get_hex("fdtaddr", 0x1234), 0),
(ulong)(map_sysmem(env_get_hex("pstr", 0x1234), 0) - offset));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -663,57 +638,60 @@
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting address of root node / string property "compatible" */
- fdt_test_get_addr_common(uts, fdt, "/", "compatible");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/", "compatible"));
/* Test getting address of node /test-node@1234 stringlist property "clock-names" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "clock-names");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "clock-names");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "clock-names"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "clock-names"));
/* Test getting address of node /test-node@1234 u32 property "clock-frequency" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "clock-frequency");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "clock-frequency");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "clock-frequency"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "clock-frequency"));
/* Test getting address of node /test-node@1234 empty property "u-boot,empty-property" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "u-boot,empty-property");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "u-boot,empty-property");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "u-boot,empty-property"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "u-boot,empty-property"));
/* Test getting address of node /test-node@1234 array property "regs" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "regs");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "regs");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "regs"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "regs"));
/* Test getting address of node /test-node@1234/subnode non-existent property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get addr pnoprop /test-node@1234/subnode noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting address of non-existent node /test-node@1234/nonode@1 property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get addr pnonode /test-node@1234/nonode@1 noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_addr, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_addr, UTF_CONSOLE);
static int fdt_test_get_size_common(struct unit_test_state *uts,
const char *path, const char *prop,
const unsigned int val)
{
- ut_assertok(console_record_reset_enable());
if (prop) {
ut_assertok(run_commandf("fdt get size sstr %s %s", path, prop));
} else {
ut_assertok(run_commandf("fdt get size sstr %s", path));
}
ut_asserteq(val, env_get_hex("sstr", 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -723,71 +701,72 @@
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting size of root node / string property "compatible" */
- fdt_test_get_size_common(uts, "/", "compatible", 16);
+ ut_assertok(fdt_test_get_size_common(uts, "/", "compatible", 16));
/* Test getting size of node /test-node@1234 stringlist property "clock-names" */
- fdt_test_get_size_common(uts, "/test-node@1234", "clock-names", 26);
- fdt_test_get_size_common(uts, "testnodealias", "clock-names", 26);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "clock-names", 26));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "clock-names", 26));
/* Test getting size of node /test-node@1234 u32 property "clock-frequency" */
- fdt_test_get_size_common(uts, "/test-node@1234", "clock-frequency", 4);
- fdt_test_get_size_common(uts, "testnodealias", "clock-frequency", 4);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "clock-frequency", 4));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "clock-frequency", 4));
/* Test getting size of node /test-node@1234 empty property "u-boot,empty-property" */
- fdt_test_get_size_common(uts, "/test-node@1234", "u-boot,empty-property", 0);
- fdt_test_get_size_common(uts, "testnodealias", "u-boot,empty-property", 0);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "u-boot,empty-property", 0));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "u-boot,empty-property", 0));
/* Test getting size of node /test-node@1234 array property "regs" */
- fdt_test_get_size_common(uts, "/test-node@1234", "regs", 8);
- fdt_test_get_size_common(uts, "testnodealias", "regs", 8);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234", "regs",
+ 8));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias", "regs", 8));
/* Test getting node count of node / */
- fdt_test_get_size_common(uts, "/", NULL, 2);
+ ut_assertok(fdt_test_get_size_common(uts, "/", NULL, 2));
/* Test getting node count of node /test-node@1234/subnode */
- fdt_test_get_size_common(uts, "/test-node@1234/subnode", NULL, 0);
- fdt_test_get_size_common(uts, "subnodealias", NULL, 0);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234/subnode",
+ NULL, 0));
+ ut_assertok(fdt_test_get_size_common(uts, "subnodealias", NULL, 0));
/* Test getting size of node /test-node@1234/subnode non-existent property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnoprop /test-node@1234/subnode noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
ut_asserteq(1, run_command("fdt get size pnoprop subnodealias noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting size of non-existent node /test-node@1234/nonode@1 property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1 noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of non-existent node /test-node@1234/nonode@1 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of bad alias badalias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode badalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of non-existent alias noalias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode noalias", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_size, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_size, UTF_CONSOLE);
static int fdt_test_set_single(struct unit_test_state *uts,
const char *path, const char *prop,
@@ -799,7 +778,6 @@
* => fdt set /path property integer
* => fdt set /path property
*/
- ut_assertok(console_record_reset_enable());
if (sval)
ut_assertok(run_commandf("fdt set %s %s %s", path, prop, sval));
else if (integer)
@@ -815,7 +793,7 @@
ut_asserteq(ival, env_get_hex("svar", 0x1234));
else
ut_assertnull(env_get("svar"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -837,7 +815,6 @@
* new array is correctly sized and read past the new array length
* triggers failure.
*/
- ut_assertok(console_record_reset_enable());
if (sval1 && sval2) {
ut_assertok(run_commandf("fdt set %s %s %s %s end", path, prop, sval1, sval2));
ut_assertok(run_commandf("fdt set %s %s %s %s", path, prop, sval1, sval2));
@@ -865,7 +842,7 @@
ut_asserteq(ival2, env_get_hex("svar2", 0x1234));
ut_assertnull(env_get("svarn"));
}
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -873,14 +850,14 @@
static int fdt_test_set_node(struct unit_test_state *uts,
const char *path, const char *prop)
{
- fdt_test_set_single(uts, path, prop, "new", 0, false);
- fdt_test_set_single(uts, path, prop, "rewrite", 0, false);
- fdt_test_set_single(uts, path, prop, NULL, 42, true);
- fdt_test_set_single(uts, path, prop, NULL, 0, false);
- fdt_test_set_multi(uts, path, prop, NULL, NULL, 42, 1701);
- fdt_test_set_multi(uts, path, prop, NULL, NULL, 74656, 9);
- fdt_test_set_multi(uts, path, prop, "42", "1701", 0, 0);
- fdt_test_set_multi(uts, path, prop, "74656", "9", 0, 0);
+ ut_assertok(fdt_test_set_single(uts, path, prop, "new", 0, false));
+ ut_assertok(fdt_test_set_single(uts, path, prop, "rewrite", 0, false));
+ ut_assertok(fdt_test_set_single(uts, path, prop, NULL, 42, true));
+ ut_assertok(fdt_test_set_single(uts, path, prop, NULL, 0, false));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, NULL, NULL, 42, 1701));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, NULL, NULL, 74656, 9));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, "42", "1701", 0, 0));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, "74656", "9", 0, 0));
return 0;
}
@@ -890,198 +867,173 @@
char fdt[8192];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test setting of root node / existing property "compatible" */
- fdt_test_set_node(uts, "/", "compatible");
+ ut_assertok(fdt_test_set_node(uts, "/", "compatible"));
/* Test setting of root node / new property "newproperty" */
- fdt_test_set_node(uts, "/", "newproperty");
+ ut_assertok(fdt_test_set_node(uts, "/", "newproperty"));
/* Test setting of subnode existing property "compatible" */
- fdt_test_set_node(uts, "/test-node@1234/subnode", "compatible");
- fdt_test_set_node(uts, "subnodealias", "compatible");
+ ut_assertok(fdt_test_set_node(uts, "/test-node@1234/subnode",
+ "compatible"));
+ ut_assertok(fdt_test_set_node(uts, "subnodealias", "compatible"));
/* Test setting of subnode new property "newproperty" */
- fdt_test_set_node(uts, "/test-node@1234/subnode", "newproperty");
- fdt_test_set_node(uts, "subnodealias", "newproperty");
+ ut_assertok(fdt_test_set_node(uts, "/test-node@1234/subnode",
+ "newproperty"));
+ ut_assertok(fdt_test_set_node(uts, "subnodealias", "newproperty"));
/* Test setting property of non-existent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set /no-node noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting property of non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set noalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting property of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set badalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_set, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_set, UTF_CONSOLE);
static int fdt_test_mknode(struct unit_test_state *uts)
{
char fdt[8192];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test creation of new node in / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode / newnode"));
ut_assertok(run_commandf("fdt list /newnode"));
ut_assert_nextline("newnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode /test-node@1234 newsubnode"));
ut_assertok(run_commandf("fdt list /test-node@1234/newsubnode"));
ut_assert_nextline("newsubnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode testnodealias newersubnode"));
ut_assertok(run_commandf("fdt list testnodealias/newersubnode"));
ut_assert_nextline("newersubnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 over existing node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode testnodealias newsubnode"));
ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 by alias over existing node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode testnodealias newersubnode"));
ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in non-existent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode /no-node newnosubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode noalias newfailsubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode badalias newbadsubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_mknode, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_mknode, UTF_CONSOLE);
static int fdt_test_rm(struct unit_test_state *uts)
{
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test removal of property in root node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print / compatible"));
ut_assert_nextline("compatible = \"u-boot,fdt-test\"");
ut_assertok(run_commandf("fdt rm / compatible"));
ut_asserteq(1, run_commandf("fdt print / compatible"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of property clock-names in subnode /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print /test-node@1234 clock-names"));
ut_assert_nextline("clock-names = \"fixed\", \"i2c\", \"spi\", \"uart2\", \"uart1\"");
ut_assertok(run_commandf("fdt rm /test-node@1234 clock-names"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234 clock-names"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of property u-boot,empty-property in subnode /test-node@1234 by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print testnodealias u-boot,empty-property"));
ut_assert_nextline("testnodealias u-boot,empty-property");
ut_assertok(run_commandf("fdt rm testnodealias u-boot,empty-property"));
ut_asserteq(1, run_commandf("fdt print testnodealias u-boot,empty-property"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of non-existent property noprop in subnode /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm /test-node@1234 noprop"));
ut_assert_nextline("libfdt fdt_delprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of non-existent node /no-node@5678 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm /no-node@5678"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of subnode /test-node@1234/subnode by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm subnodealias"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234/subnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node by non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm noalias"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node by bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm noalias"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm /test-node@1234"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm /"));
ut_asserteq(1, run_commandf("fdt print /"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_rm, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_rm, UTF_CONSOLE);
static int fdt_test_bootcpu(struct unit_test_state *uts)
{
@@ -1089,46 +1041,39 @@
ulong addr;
int i;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting default bootcpu entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys"));
ut_asserteq(0, env_get_ulong("bootcpu", 10, 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting and getting new bootcpu entry, twice, to test overwrite */
for (i = 42; i <= 43; i++) {
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt bootcpu %d", i));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting new bootcpu entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys"));
ut_asserteq(i, env_get_ulong("bootcpu", 10, 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
return 0;
}
-FDT_TEST(fdt_test_bootcpu, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_bootcpu, UTF_CONSOLE);
static int fdt_test_header_get(struct unit_test_state *uts,
const char *field, const unsigned long val)
{
/* Test getting valid header entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get fvar %s", field));
ut_asserteq(val, env_get_hex("fvar", 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting malformed header entry */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt header get fvar typo%stypo", field));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -1138,12 +1083,9 @@
char fdt[256];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test header print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header"));
ut_assert_nextline("magic:\t\t\t0x%x", fdt_magic(fdt));
ut_assert_nextline("totalsize:\t\t0x%x (%d)", fdt_totalsize(fdt), fdt_totalsize(fdt));
@@ -1157,23 +1099,30 @@
ut_assert_nextline("size_dt_struct:\t\t0x%x", fdt_size_dt_struct(fdt));
ut_assert_nextline("number mem_rsv:\t\t0x%x", fdt_num_mem_rsv(fdt));
ut_assert_nextline_empty();
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test header get */
- fdt_test_header_get(uts, "magic", fdt_magic(fdt));
- fdt_test_header_get(uts, "totalsize", fdt_totalsize(fdt));
- fdt_test_header_get(uts, "off_dt_struct", fdt_off_dt_struct(fdt));
- fdt_test_header_get(uts, "off_dt_strings", fdt_off_dt_strings(fdt));
- fdt_test_header_get(uts, "off_mem_rsvmap", fdt_off_mem_rsvmap(fdt));
- fdt_test_header_get(uts, "version", fdt_version(fdt));
- fdt_test_header_get(uts, "last_comp_version", fdt_last_comp_version(fdt));
- fdt_test_header_get(uts, "boot_cpuid_phys", fdt_boot_cpuid_phys(fdt));
- fdt_test_header_get(uts, "size_dt_strings", fdt_size_dt_strings(fdt));
- fdt_test_header_get(uts, "size_dt_struct", fdt_size_dt_struct(fdt));
+ ut_assertok(fdt_test_header_get(uts, "magic", fdt_magic(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "totalsize", fdt_totalsize(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_dt_struct",
+ fdt_off_dt_struct(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_dt_strings",
+ fdt_off_dt_strings(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_mem_rsvmap",
+ fdt_off_mem_rsvmap(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "version", fdt_version(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "last_comp_version",
+ fdt_last_comp_version(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "boot_cpuid_phys",
+ fdt_boot_cpuid_phys(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "size_dt_strings",
+ fdt_size_dt_strings(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "size_dt_struct",
+ fdt_size_dt_struct(fdt)));
return 0;
}
-FDT_TEST(fdt_test_header, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_header, UTF_CONSOLE);
static int fdt_test_memory_cells(struct unit_test_state *uts,
const unsigned int cells)
@@ -1217,16 +1166,16 @@
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
addr = map_to_sysmem(fdt);
set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
/* Test updating the memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt memory 0x%s 0x%s", seta, sets));
ut_assertok(run_commandf("fdt print /memory"));
ut_assert_nextline("memory {");
ut_assert_nextline("\tdevice_type = \"memory\";");
ut_assert_nextline("\treg = <%s %s>;", pada, pads);
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
free(sets);
free(seta);
@@ -1244,8 +1193,8 @@
* so far unsupported and fails because of simple_stroull() being
* 64bit tops in the 'fdt memory' command implementation.
*/
- fdt_test_memory_cells(uts, 1);
- fdt_test_memory_cells(uts, 2);
+ ut_assertok(fdt_test_memory_cells(uts, 1));
+ ut_assertok(fdt_test_memory_cells(uts, 2));
/*
* The 'fdt memory' command is limited to /memory node, it does
@@ -1256,31 +1205,27 @@
return 0;
}
-FDT_TEST(fdt_test_memory, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_memory, UTF_CONSOLE);
static int fdt_test_rsvmem(struct unit_test_state *uts)
{
char fdt[8192];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
fdt_add_mem_rsv(fdt, 0x42, 0x1701);
fdt_add_mem_rsv(fdt, 0x74656, 0x9);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test default reserved memory node presence */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
ut_assert_nextline("------------------------------------------------");
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem add 0x1234 0x5678"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
@@ -1288,20 +1233,18 @@
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x1234, 0x5678);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test delete reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem delete 0"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
ut_assert_nextline("------------------------------------------------");
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test re-add new reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem add 0x42 0x1701"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
@@ -1309,17 +1252,16 @@
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678);
ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x42, 0x1701);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test delete nonexistent reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rsvmem delete 10"));
ut_assert_nextline("libfdt fdt_del_mem_rsv(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_rsvmem, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_rsvmem, UTF_CONSOLE);
static int fdt_test_chosen(struct unit_test_state *uts)
{
@@ -1327,19 +1269,15 @@
char fdt[8192];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test default chosen node presence, fail as there is no /chosen node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt print /chosen"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new chosen node without initrd */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt chosen"));
ut_assertok(run_commandf("fdt print /chosen"));
ut_assert_nextline("chosen {");
@@ -1351,10 +1289,9 @@
!IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new chosen node with initrd */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt chosen 0x1234 0x5678"));
ut_assertok(run_commandf("fdt print /chosen"));
ut_assert_nextline("chosen {");
@@ -1371,11 +1308,11 @@
!IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_chosen, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_chosen, UTF_CONSOLE);
static int fdt_test_apply(struct unit_test_state *uts)
{
@@ -1393,6 +1330,7 @@
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
addr = map_to_sysmem(fdt);
set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
/* Create DTO which adds single property to root node / */
ut_assertok(fdt_create(fdto, sizeof(fdto)));
@@ -1408,16 +1346,14 @@
addro = map_to_sysmem(fdto);
/* Test default DT print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
ut_assert_nextline("\t__symbols__ {");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test simple DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1425,7 +1361,7 @@
ut_assert_nextline("\t__symbols__ {");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Create complex DTO which:
@@ -1462,7 +1398,6 @@
addro = map_to_sysmem(fdto);
/* Test complex DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1479,7 +1414,7 @@
ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Create complex DTO which:
@@ -1506,7 +1441,6 @@
addro = map_to_sysmem(fdto);
/* Test complex DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1523,11 +1457,11 @@
ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_apply, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_apply, UTF_CONSOLE);
int do_ut_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/font.c b/test/cmd/font.c
index a8905ce..25d365d 100644
--- a/test/cmd/font.c
+++ b/test/cmd/font.c
@@ -26,12 +26,11 @@
ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
ut_assertok(uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev));
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("font list", 0));
ut_assert_nextline("nimbus_sans_l_regular");
if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
ut_assert_nextline("cantoraone_regular");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("nimbus_sans_l_regular", name);
@@ -49,19 +48,19 @@
if (max_metrics < 2) {
ut_asserteq(1, ret);
ut_assert_nextline("Failed (error -7)");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
ut_assertok(ret);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
ut_asserteq(40, size);
ut_assertok(run_command("font size 30", 0));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
@@ -69,8 +68,8 @@
return 0;
}
-FONT_TEST(font_test_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_CONSOLE_REC | UT_TESTF_DM);
+FONT_TEST(font_test_base, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE |
+ UTF_DM);
int do_ut_font(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/history.c b/test/cmd/history.c
index 6964bfa..6d9d228 100644
--- a/test/cmd/history.c
+++ b/test/cmd/history.c
@@ -45,4 +45,4 @@
return 0;
}
-LIB_TEST(lib_test_history, UT_TESTF_CONSOLE_REC);
+LIB_TEST(lib_test_history, UTF_CONSOLE);
diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c
index dff8a97..dedb4f7 100644
--- a/test/cmd/loadm.c
+++ b/test/cmd/loadm.c
@@ -23,7 +23,6 @@
static int loadm_test_params(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
run_command("loadm", 0);
ut_assert_nextline("loadm - load binary blob from source address to destination address");
@@ -41,7 +40,7 @@
return 0;
}
-LOADM_TEST(loadm_test_params, UT_TESTF_CONSOLE_REC);
+LOADM_TEST(loadm_test_params, UTF_CONSOLE);
static int loadm_test_load (struct unit_test_state *uts)
{
@@ -51,7 +50,6 @@
memset(buf, '\0', BUF_SIZE);
memset(buf, 0xaa, BUF_SIZE / 2);
- ut_assertok(console_record_reset_enable());
run_command("loadm 0x0 0x80 0x80", 0);
ut_assert_nextline("loaded bin to memory: size: 128");
@@ -59,7 +57,7 @@
return 0;
}
-LOADM_TEST(loadm_test_load, UT_TESTF_CONSOLE_REC);
+LOADM_TEST(loadm_test_load, UTF_CONSOLE);
int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
index 235b363..b14137e 100644
--- a/test/cmd/mbr.c
+++ b/test/cmd/mbr.c
@@ -14,10 +14,14 @@
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
+#include <linux/sizes.h>
#include <test/suites.h>
#include <test/ut.h>
DECLARE_GLOBAL_DATA_PTR;
+
+#define BLKSZ SZ_512 /* block size */
+
/*
* Requirements for running test manually:
* mmc6.img - File size needs to be at least 12 MiB
@@ -50,7 +54,7 @@
000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
*/
-static unsigned mbr_cmp_start = 0x1B8;
+static unsigned int mbr_cmp_start = 0x1b8;
static unsigned mbr_cmp_size = 0x48;
static unsigned char mbr_parts_ref_p1[] = {
0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05,
@@ -228,9 +232,11 @@
static int mbr_test_run(struct unit_test_state *uts)
{
struct blk_desc *mmc_dev_desc;
- unsigned char mbr_wbuf[512], ebr_wbuf[512], rbuf[512];
+ unsigned char *mbr_wbuf, *ebr_wbuf, *rbuf;
char mbr_parts_buf[256];
- ulong mbr_wa, ebr_wa, ra, ebr_blk, mbr_parts_max;
+ ulong addr = 0x1000; /* start address for buffers */
+ ulong mbr_wa = addr, ebr_wa = addr + BLKSZ, ra = addr + BLKSZ * 2;
+ ulong ebr_blk, mbr_parts_max;
struct udevice *dev;
ofnode root, node;
@@ -254,43 +260,43 @@
ut_assertf(sizeof(mbr_parts_buf) >= mbr_parts_max, "Buffer avail: %ld; buffer req: %ld\n",
sizeof(mbr_parts_buf), mbr_parts_max);
- mbr_wa = map_to_sysmem(mbr_wbuf);
- ebr_wa = map_to_sysmem(ebr_wbuf);
- ra = map_to_sysmem(rbuf);
- ebr_blk = (ulong)0xB00000 / 0x200;
+ mbr_wbuf = map_sysmem(mbr_wa, BLKSZ);
+ ebr_wbuf = map_sysmem(ebr_wa, BLKSZ);
+ rbuf = map_sysmem(ra, BLKSZ);
+ ebr_blk = (ulong)0xb00000 / BLKSZ;
/* Make sure mmc6 exists */
ut_asserteq(6, blk_get_device_by_str("mmc", "6", &mmc_dev_desc));
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("mmc dev 6"));
ut_assert_nextline("switch to partitions #0, OK");
ut_assert_nextline("mmc6 is current device");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Make sure mmc6 is 12+ MiB in size */
- ut_assertok(run_commandf("mmc read 0x%lx 0x%lx 1", ra, (ulong)0xBFFE00 / 0x200));
+ ut_assertok(run_commandf("mmc read %lx %lx 1", ra,
+ (ulong)0xbffe00 / BLKSZ));
/* Test one MBR partition */
init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 1));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
- ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, BLKSZ));
+ ut_assertok(run_commandf("write mmc 6:0 %lx %lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextlinen("MMC read: dev # 6");
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........|
@@ -298,35 +304,34 @@
000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
for (unsigned i = 0; i < mbr_cmp_size; i++) {
ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p1[i],
- "1P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "1P MBR+0x%04X: expected %#02X, actual: %#02X\n",
mbr_cmp_start + i, mbr_parts_ref_p1[i], rbuf[mbr_cmp_start + i]);
}
/* Test two MBR partitions */
init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 2));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
- ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, BLKSZ));
+ ut_assertok(run_commandf("write mmc 6:0 %lx %lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -334,35 +339,34 @@
000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
for (unsigned i = 0; i < mbr_cmp_size; i++) {
ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p2[i],
- "2P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "2P MBR+0x%04X: expected %#02X, actual: %#02X\n",
mbr_cmp_start + i, mbr_parts_ref_p2[i], rbuf[mbr_cmp_start + i]);
}
/* Test three MBR partitions */
init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 3));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
- ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, BLKSZ));
+ ut_assertok(run_commandf("write mmc 6:0 %lx %lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -370,35 +374,34 @@
000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 00 |...f%..P........|
000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
for (unsigned i = 0; i < mbr_cmp_size; i++) {
ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p3[i],
- "3P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "3P MBR+0x%04X: expected %#02X, actual: %#02X\n",
mbr_cmp_start + i, mbr_parts_ref_p3[i], rbuf[mbr_cmp_start + i]);
}
/* Test four MBR partitions */
init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 4));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
- ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, BLKSZ));
+ ut_assertok(run_commandf("write mmc 6:0 %lx %lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -406,32 +409,31 @@
000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
000001f0 26 01 0e 87 06 01 00 58 00 00 00 08 00 00 55 aa |&......X......U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
for (unsigned i = 0; i < mbr_cmp_size; i++) {
ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p4[i],
- "4P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "4P MBR+0x%04X: expected %#02X, actual: %#02X\n",
mbr_cmp_start + i, mbr_parts_ref_p4[i], rbuf[mbr_cmp_start + i]);
}
/* Test five MBR partitions */
init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__);
ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 5));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
- ut_assertok(memcmp(mbr_wbuf, rbuf, 512));
- ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk));
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
- ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("write mmc 6:0 %lx 0 1", mbr_wa));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
+ ut_assertok(memcmp(mbr_wbuf, rbuf, BLKSZ));
+ ut_assertok(run_commandf("write mmc 6:0 %lx %lx 1", ebr_wa, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
+ ut_assertok(memcmp(ebr_wbuf, rbuf, BLKSZ));
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertf(0 == run_commandf("mbr write mmc 6"), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -439,11 +441,11 @@
000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f|
000001f0 26 01 05 a7 26 01 00 58 00 00 00 10 00 00 55 aa |&...&..X......U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx 0 1", ra));
for (unsigned i = 0; i < mbr_cmp_size; i++) {
ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p5[i],
- "5P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "5P MBR+0x%04X: expected %#02X, actual: %#02X\n",
mbr_cmp_start + i, mbr_parts_ref_p5[i], rbuf[mbr_cmp_start + i]);
}
/*
@@ -453,19 +455,22 @@
00b001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00b001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.|
*/
- memset(rbuf, 0, sizeof(rbuf));
- ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
+ memset(rbuf, '\0', BLKSZ);
+ ut_assertok(run_commandf("read mmc 6:0 %lx %lx 1", ra, ebr_blk));
for (unsigned i = 0; i < ebr_cmp_size; i++) {
ut_assertf(rbuf[ebr_cmp_start + i] == ebr_parts_ref_p5[i],
- "5P EBR+0x%04X: expected 0x%02X, actual: 0x%02X\n",
+ "5P EBR+0x%04X: expected %#02X, actual: %#02X\n",
ebr_cmp_start + i, ebr_parts_ref_p5[i], rbuf[ebr_cmp_start + i]);
}
+ unmap_sysmem(mbr_wbuf);
+ unmap_sysmem(ebr_wbuf);
+ unmap_sysmem(rbuf);
return 0;
}
/* Declare mbr test */
-UNIT_TEST(mbr_test_run, UT_TESTF_CONSOLE_REC, mbr_test);
+UNIT_TEST(mbr_test_run, UTF_CONSOLE, mbr_test);
int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
@@ -474,10 +479,3 @@
return cmd_ut_category("mbr", "mbr_test_", tests, n_ents, argc, argv);
}
-
-static int dm_test_cmd_mbr(struct unit_test_state *uts)
-{
- return mbr_test_run(uts);
-}
-
-DM_TEST(dm_test_cmd_mbr, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c
index 55ad2fa..3a031ee 100644
--- a/test/cmd/mem_search.c
+++ b/test/cmd/mem_search.c
@@ -27,7 +27,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -43,7 +42,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_b, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_b, UTF_CONSOLE);
/* Test 'ms' command with 16-bit values */
static int mem_test_ms_w(struct unit_test_state *uts)
@@ -54,7 +53,6 @@
memset(buf, '\0', BUF_SIZE);
buf[0x34 / 2] = 0x1234;
buf[BUF_SIZE / 2] = 0x1234;
- ut_assertok(console_record_reset_enable());
run_command("ms.w 0 80 1234", 0);
ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4...........");
ut_assert_nextline("1 match");
@@ -68,7 +66,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_w, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_w, UTF_CONSOLE);
/* Test 'ms' command with 32-bit values */
static int mem_test_ms_l(struct unit_test_state *uts)
@@ -79,7 +77,6 @@
memset(buf, '\0', BUF_SIZE);
buf[0x38 / 4] = 0x12345678;
buf[BUF_SIZE / 4] = 0x12345678;
- ut_assertok(console_record_reset_enable());
run_command("ms 0 40 12345678", 0);
ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4.....");
ut_assert_nextline("1 match");
@@ -89,7 +86,6 @@
ut_asserteq(0x38, env_get_hex("memaddr", 0));
ut_asserteq(0x38 / 4, env_get_hex("mempos", 0));
- ut_assertok(console_record_reset_enable());
run_command("ms 0 80 12345679", 0);
ut_assert_nextline("0 matches");
ut_assert_console_end();
@@ -102,7 +98,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_l, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_l, UTF_CONSOLE);
/* Test 'ms' command with continuation */
static int mem_test_ms_cont(struct unit_test_state *uts)
@@ -116,7 +112,6 @@
memset(buf, '\0', BUF_SIZE);
for (i = 5; i < 0x33; i += 3)
buf[i] = 0x34;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 0 100 34", 0);
ut_assert_nextlinen("00000000: 00 00 00 00 00 34 00 00 34 00 00 34 00 00 34 00");
ut_assert_nextline("--");
@@ -134,7 +129,6 @@
* run_command() ignoes the repeatable flag when using hush, so call
* cmd_process() directly
*/
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("00000020: 34 00 00 34 00 00 34 00 00 34 00 00 34 00 00 34");
ut_assert_nextline("--");
@@ -152,7 +146,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_cont, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_cont, UTF_CONSOLE);
/* Test that an 'ms' command with continuation stops at the end of the range */
static int mem_test_ms_cont_end(struct unit_test_state *uts)
@@ -167,7 +161,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextlinen("00000030");
ut_assert_nextlinen("--");
@@ -181,13 +174,11 @@
*
* This should produce no matches.
*/
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("0 matches");
ut_assert_console_end();
/* One more time */
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("0 matches");
ut_assert_console_end();
@@ -196,7 +187,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_cont_end, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_cont_end, UTF_CONSOLE);
/* Test 'ms' command with multiple values */
static int mem_test_ms_mult(struct unit_test_state *uts)
@@ -225,7 +216,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_mult, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_mult, UTF_CONSOLE);
/* Test 'ms' command with string */
static int mem_test_ms_s(struct unit_test_state *uts)
@@ -239,7 +230,6 @@
strcpy(buf + 0x1e, str);
strcpy(buf + 0x63, str);
strcpy(buf + 0xa1, str2);
- ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello", 0);
ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
@@ -254,7 +244,6 @@
ut_asserteq(0xa1, env_get_hex("memaddr", 0));
ut_asserteq(0xa1, env_get_hex("mempos", 0));
- ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello there", 0);
ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
ut_assert_nextline("1 match");
@@ -268,7 +257,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_s, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_s, UTF_CONSOLE);
/* Test 'ms' command with limit */
static int mem_test_ms_limit(struct unit_test_state *uts)
@@ -281,7 +270,6 @@
buf[0x31] = 0x12;
buf[0x62] = 0x12;
buf[0x76] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b -l2 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -297,7 +285,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_limit, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_limit, UTF_CONSOLE);
/* Test 'ms' command in quiet mode */
static int mem_test_ms_quiet(struct unit_test_state *uts)
@@ -310,7 +298,6 @@
buf[0x31] = 0x12;
buf[0x62] = 0x12;
buf[0x76] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b -q -l2 1 ff 12", 0);
ut_assert_console_end();
unmap_sysmem(buf);
@@ -321,4 +308,4 @@
return 0;
}
-MEM_TEST(mem_test_ms_quiet, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_quiet, UTF_CONSOLE);
diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c
index 2a64143..a265105 100644
--- a/test/cmd/pci_mps.c
+++ b/test/cmd/pci_mps.c
@@ -27,8 +27,7 @@
return 0;
}
-
-PCI_MPS_TEST(test_pci_mps_safe, UT_TESTF_CONSOLE_REC);
+PCI_MPS_TEST(test_pci_mps_safe, UTF_CONSOLE);
int do_ut_pci_mps(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c
index 4253baa..65974d0 100644
--- a/test/cmd/pinmux.c
+++ b/test/cmd/pinmux.c
@@ -18,23 +18,26 @@
ut_assertok(uclass_get_device(UCLASS_LED, 2, &dev));
/* Test that 'pinmux status <pinname>' displays the selected pin. */
- console_record_reset();
run_command("pinmux status a5", 0);
ut_assert_nextlinen("a5 : gpio output .");
ut_assert_console_end();
- console_record_reset();
run_command("pinmux status P7", 0);
ut_assert_nextlinen("P7 : GPIO2 bias-pull-down input-enable.");
ut_assert_console_end();
- console_record_reset();
run_command("pinmux status P9", 0);
- ut_assert_nextlinen("single-pinctrl pinctrl-single-no-width: missing register width");
+ if (IS_ENABLED(CONFIG_LOGF_FUNC)) {
+ ut_assert_nextlinen(
+ " single_of_to_plat() single-pinctrl pinctrl-single-no-width: missing register width");
+ } else {
+ ut_assert_nextlinen(
+ "single-pinctrl pinctrl-single-no-width: missing register width");
+ }
ut_assert_nextlinen("P9 not found");
ut_assert_console_end();
return 0;
}
-
-DM_TEST(dm_test_cmd_pinmux_status_pinname, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_pinmux_status_pinname, UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_CONSOLE);
diff --git a/test/cmd/pwm.c b/test/cmd/pwm.c
index cf7ee0e..0d47e2d 100644
--- a/test/cmd/pwm.c
+++ b/test/cmd/pwm.c
@@ -22,8 +22,6 @@
ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* pwm <invert> <pwm_dev_num> <channel> <polarity> */
/* cros-ec-pwm doesn't support invert */
ut_asserteq(1, run_command("pwm invert 0 0 1", 0));
@@ -49,8 +47,6 @@
ut_assertok(uclass_get_device(UCLASS_PWM, 1, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* pwm <invert> <pwm_dev_num> <channel> <polarity> */
ut_assertok(run_command("pwm invert 1 0 1", 0));
ut_assert_console_end();
@@ -71,5 +67,4 @@
return 0;
}
-
-DM_TEST(dm_test_pwm_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_pwm_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/rw.c b/test/cmd/rw.c
index edd762e..0a856c4 100644
--- a/test/cmd/rw.c
+++ b/test/cmd/rw.c
@@ -87,17 +87,14 @@
ut_assertok(memcmp(wbuf, rbuf, sizeof(wbuf)));
/* Read/write outside partition bounds should be rejected upfront. */
- console_record_reset_enable();
ut_asserteq(1, run_commandf("read mmc 2#data 0x%lx 3 2", ra));
ut_assert_nextlinen("read out of range");
ut_assert_console_end();
- console_record_reset_enable();
ut_asserteq(1, run_commandf("write mmc 2#log 0x%lx 9 2", wa));
ut_assert_nextlinen("write out of range");
ut_assert_console_end();
return 0;
}
-
-DM_TEST(dm_test_read_write, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_read_write, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/seama.c b/test/cmd/seama.c
index b60f655..28d6b9a 100644
--- a/test/cmd/seama.c
+++ b/test/cmd/seama.c
@@ -16,7 +16,6 @@
static int seama_test_noargs(struct unit_test_state *uts)
{
/* Test that 'seama' with no arguments fails gracefully */
- console_record_reset();
run_command("seama", 0);
ut_assert_nextlinen("seama - Load the SEAMA image and sets envs");
ut_assert_skipline();
@@ -26,12 +25,11 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_noargs, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_noargs, UTF_CONSOLE);
static int seama_test_addr(struct unit_test_state *uts)
{
/* Test that loads SEAMA image 0 to address 0x01000000 */
- console_record_reset();
run_command("seama 0x01000000", 0);
ut_assert_nextlinen("Loading SEAMA image 0 from nand0");
ut_assert_nextlinen("SEMA IMAGE:");
@@ -42,12 +40,11 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_addr, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_addr, UTF_CONSOLE);
static int seama_test_index(struct unit_test_state *uts)
{
/* Test that loads SEAMA image 0 exlicitly specified */
- console_record_reset();
run_command("seama 0x01000000 0", 0);
ut_assert_nextlinen("Loading SEAMA image 0 from nand0");
ut_assert_nextlinen("SEMA IMAGE:");
@@ -58,7 +55,7 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_index, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_index, UTF_CONSOLE);
int do_ut_seama(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
index 4c6cc3c..21a3268 100644
--- a/test/cmd/setexpr.c
+++ b/test/cmd/setexpr.c
@@ -63,7 +63,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_int, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_int, UTF_CONSOLE);
/* Test 'setexpr' command with + operator */
static int setexpr_test_plus(struct unit_test_state *uts)
@@ -105,7 +105,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_plus, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_plus, UTF_CONSOLE);
/* Test 'setexpr' command with other operators */
static int setexpr_test_oper(struct unit_test_state *uts)
@@ -148,7 +148,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_oper, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_oper, UTF_CONSOLE);
/* Test 'setexpr' command with regex */
static int setexpr_test_regex(struct unit_test_state *uts)
@@ -192,7 +192,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_regex, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_regex, UTF_CONSOLE);
/* Test 'setexpr' command with regex replacement that expands the string */
static int setexpr_test_regex_inc(struct unit_test_state *uts)
@@ -209,7 +209,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_regex_inc, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_regex_inc, UTF_CONSOLE);
/* Test setexpr_regex_sub() directly to check buffer usage */
static int setexpr_test_sub(struct unit_test_state *uts)
@@ -249,7 +249,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_sub, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_sub, UTF_CONSOLE);
/* Test setexpr_regex_sub() with back references */
static int setexpr_test_backref(struct unit_test_state *uts)
@@ -292,7 +292,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_backref, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_backref, UTF_CONSOLE);
/* Test 'setexpr' command with setting strings */
static int setexpr_test_str(struct unit_test_state *uts)
@@ -327,7 +327,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str, UTF_CONSOLE);
/* Test 'setexpr' command with concatenating strings */
static int setexpr_test_str_oper(struct unit_test_state *uts)
@@ -340,7 +340,6 @@
strcpy(buf, "hello");
strcpy(buf + 0x10, " there");
- ut_assertok(console_record_reset_enable());
start_mem = ut_check_free();
ut_asserteq(1, run_command("setexpr.s fred *0 * *10", 0));
ut_assertok(ut_check_delta(start_mem));
@@ -376,7 +375,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str_oper, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str_oper, UTF_CONSOLE);
/* Test 'setexpr' command with a string that is too long */
static int setexpr_test_str_long(struct unit_test_state *uts)
@@ -396,7 +395,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str_long, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str_long, UTF_CONSOLE);
#ifdef CONFIG_CMD_SETEXPR_FMT
/* Test 'setexpr' command with simply setting integers */
@@ -478,8 +477,7 @@
return 0;
}
-
-SETEXPR_TEST(setexpr_test_fmt, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_fmt, UTF_CONSOLE);
#endif
int do_ut_setexpr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
diff --git a/test/cmd/temperature.c b/test/cmd/temperature.c
index 3649726..309693a 100644
--- a/test/cmd/temperature.c
+++ b/test/cmd/temperature.c
@@ -18,8 +18,6 @@
ut_assertok(uclass_get_device(UCLASS_THERMAL, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* Test that "temperature list" shows the sandbox device */
ut_assertok(run_command("temperature list", 0));
ut_assert_nextline("| Device | Driver | Parent");
@@ -34,5 +32,4 @@
return 0;
}
-
-DM_TEST(dm_test_cmd_temperature, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_cmd_temperature, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c
index cde74eb..8b306cc 100644
--- a/test/cmd/test_echo.c
+++ b/test/cmd/test_echo.c
@@ -45,16 +45,12 @@
int i;
for (i = 0; i < ARRAY_SIZE(echo_data); ++i) {
- ut_silence_console(uts);
- console_record_reset_enable();
ut_assertok(run_command(echo_data[i].cmd, 0));
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str,
sizeof(uts->actual_str));
ut_asserteq_str(echo_data[i].expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
return 0;
}
-
-LIB_TEST(lib_test_hush_echo, 0);
+LIB_TEST(lib_test_hush_echo, UTF_CONSOLE);
diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c
index 3703290..174c31a 100644
--- a/test/cmd/test_pause.c
+++ b/test/cmd/test_pause.c
@@ -14,25 +14,22 @@
static int lib_test_hush_pause(struct unit_test_state *uts)
{
/* Test default message */
- console_record_reset_enable();
/* Cook a newline when the command is expected to pause */
console_in_puts("\n");
ut_assertok(run_command("pause", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str("Press any key to continue...", uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test provided message */
- console_record_reset_enable();
/* Cook a newline when the command is expected to pause */
console_in_puts("\n");
ut_assertok(run_command("pause 'Prompt for pause...'", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str("Prompt for pause...", uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test providing more than one params */
- console_record_reset_enable();
/* No newline cooked here since the command is expected to fail */
ut_asserteq(1, run_command("pause a b", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
@@ -41,4 +38,4 @@
return 0;
}
-LIB_TEST(lib_test_hush_pause, 0);
+LIB_TEST(lib_test_hush_pause, UTF_CONSOLE);
diff --git a/test/cmd/wget.c b/test/cmd/wget.c
index 356a4dc..fe26fee 100644
--- a/test/cmd/wget.c
+++ b/test/cmd/wget.c
@@ -26,6 +26,8 @@
#define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4)
#define LEN_B_TO_DW(x) ((x) >> 2)
+int net_set_ack_options(union tcp_build_pkt *b);
+
static int sb_arp_handler(struct udevice *dev, void *packet,
unsigned int len)
{
@@ -105,6 +107,10 @@
const char *payload1 = "HTTP/1.1 200 OK\r\n"
"Content-Length: 30\r\n\r\n\r\n"
"<html><body>Hi</body></html>\r\n";
+ union tcp_build_pkt *b = (union tcp_build_pkt *)tcp;
+ const int recv_payload_len = len - net_set_ack_options(b) - IP_HDR_SIZE - ETHER_HDR_SIZE;
+ static int next_seq;
+ const int bottom_payload_len = 10;
/* Don't allow the buffer to overrun */
if (priv->recv_packets >= PKTBUFSRX)
@@ -119,13 +125,31 @@
tcp_send->tcp_dst = tcp->tcp_src;
data = (void *)tcp_send + IP_TCP_HDR_SIZE;
- if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) {
+ if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1 && recv_payload_len == 0) {
+ // ignore ACK for three-way handshaking
+ return 0;
+ } else if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) {
+ // recv HTTP request message and reply top half data
tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack));
- tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1);
- payload_len = strlen(payload1);
+ tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len);
+
+ payload_len = strlen(payload1) - bottom_payload_len;
memcpy(data, payload1, payload_len);
tcp_send->tcp_flags = TCP_ACK;
+
+ next_seq = ntohl(tcp_send->tcp_seq) + payload_len;
+ } else if (ntohl(tcp->tcp_ack) == next_seq) {
+ // reply bottom half data
+ const int top_payload_len = strlen(payload1) - bottom_payload_len;
+
+ tcp_send->tcp_seq = htonl(next_seq);
+ tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len);
+
+ payload_len = bottom_payload_len;
+ memcpy(data, payload1 + top_payload_len, payload_len);
+ tcp_send->tcp_flags = TCP_ACK;
- } else if (ntohl(tcp->tcp_seq) == 2) {
+ } else {
+ // close connection
tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack));
tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1);
payload_len = 0;
@@ -148,11 +172,9 @@
pkt_len,
IPPROTO_TCP);
- if (ntohl(tcp->tcp_seq) == 1 || ntohl(tcp->tcp_seq) == 2) {
- priv->recv_packet_length[priv->recv_packets] =
- ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len;
- ++priv->recv_packets;
- }
+ priv->recv_packet_length[priv->recv_packets] =
+ ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len;
+ ++priv->recv_packets;
return 0;
}
@@ -191,15 +213,16 @@
env_set("ethrotate", "no");
env_set("loadaddr", "0x20000");
ut_assertok(run_command("wget ${loadaddr} 1.1.2.2:/index.html", 0));
+ ut_assert_nextline("HTTP/1.1 200 OK");
+ ut_assert_nextline("Packets received 5, Transfer Successful");
+ ut_assert_nextline("Bytes transferred = 32 (20 hex)");
sandbox_eth_set_tx_handler(0, NULL);
- ut_assertok(console_record_reset_enable());
run_command("md5sum ${loadaddr} ${filesize}", 0);
ut_assert_nextline("md5 for 00020000 ... 0002001f ==> 234af48e94b0085060249ecb5942ab57");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-LIB_TEST(net_test_wget, 0);
+LIB_TEST(net_test_wget, UTF_CONSOLE);
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 4e4aa8f..38ba89e 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -133,6 +133,9 @@
#ifdef CONFIG_CMD_SEAMA
U_BOOT_CMD_MKENT(seama, CONFIG_SYS_MAXARGS, 1, do_ut_seama, "", ""),
#endif
+#ifdef CONFIG_CMD_UPL
+ U_BOOT_CMD_MKENT(upl, CONFIG_SYS_MAXARGS, 1, do_ut_upl, "", ""),
+#endif
};
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/test/common/cread.c b/test/common/cread.c
index e159cae..4926c21 100644
--- a/test/common/cread.c
+++ b/test/common/cread.c
@@ -66,8 +66,6 @@
* print_buffer(0, buf, 1, 7, 0);
*/
- console_record_reset_enable();
-
/* simple input */
*buf = '\0';
ut_asserteq(4, console_in_puts("abc\n"));
@@ -102,4 +100,4 @@
return 0;
}
-COMMON_TEST(cread_test, 0);
+COMMON_TEST(cread_test, UTF_CONSOLE);
diff --git a/test/common/event.c b/test/common/event.c
index de433d3..bfbbf01 100644
--- a/test/common/event.c
+++ b/test/common/event.c
@@ -106,4 +106,4 @@
return 0;
}
-COMMON_TEST(test_event_probe, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+COMMON_TEST(test_event_probe, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/common/test_autoboot.c b/test/common/test_autoboot.c
index 4ba1dcc..e3050d0 100644
--- a/test/common/test_autoboot.c
+++ b/test/common/test_autoboot.c
@@ -20,7 +20,6 @@
const char *autoboot_prompt =
"Enter password \"a\" in 1 seconds to stop autoboot";
- console_record_reset_enable();
console_in_puts(in);
/* turn on keyed autoboot for the test, if possible */
@@ -91,5 +90,4 @@
return CMD_RET_SUCCESS;
}
-
-COMMON_TEST(test_autoboot, 0);
+COMMON_TEST(test_autoboot, UTF_CONSOLE);
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 7da381f..7ccd7f8 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -195,7 +195,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_get_name, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_get_name, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_get_table_revision() */
static int dm_test_acpi_get_table_revision(struct unit_test_state *uts)
@@ -207,8 +207,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_get_table_revision,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_get_table_revision, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_create_dmar() */
static int dm_test_acpi_create_dmar(struct unit_test_state *uts)
@@ -225,7 +224,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_create_dmar, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_create_dmar, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_fill_header() */
static int dm_test_acpi_fill_header(struct unit_test_state *uts)
@@ -251,7 +250,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_fill_header, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_fill_header, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test ACPI write_tables() */
static int dm_test_acpi_write_tables(struct unit_test_state *uts)
@@ -297,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_write_tables, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_write_tables, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test basic ACPI functions */
static int dm_test_acpi_basic(struct unit_test_state *uts)
@@ -325,7 +324,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_basic, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_basic, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test setup_ctx_and_base_tables */
static int dm_test_acpi_ctx_and_base_tables(struct unit_test_state *uts)
@@ -374,8 +373,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_ctx_and_base_tables,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_ctx_and_base_tables, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'acpi list' command */
static int dm_test_acpi_cmd_list(struct unit_test_state *uts)
@@ -391,7 +389,6 @@
ut_assertok(acpi_write_dev_tables(&ctx));
- console_record_reset();
run_command("acpi list", 0);
ut_assert_nextline("Name Base Size Detail");
ut_assert_nextline("---- ---------------- ----- ----------------------------");
@@ -418,7 +415,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'acpi dump' command */
static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
@@ -435,13 +432,11 @@
ut_assertok(acpi_write_dev_tables(&ctx));
/* First search for a non-existent table */
- console_record_reset();
run_command("acpi dump rdst", 0);
ut_assert_nextline("Table 'RDST' not found");
ut_assert_console_end();
/* Now a real table */
- console_record_reset();
run_command("acpi dump dmar", 0);
addr = ALIGN(nomap_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64);
ut_assert_nextline("DMAR @ %16lx", addr);
@@ -450,7 +445,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_dump, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_dump, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test acpi_device_path() */
static int dm_test_acpi_device_path(struct unit_test_state *uts)
@@ -487,7 +482,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_device_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_device_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_device_status() */
static int dm_test_acpi_device_status(struct unit_test_state *uts)
@@ -499,7 +494,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_device_status, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_device_status, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_fill_ssdt() */
static int dm_test_acpi_fill_ssdt(struct unit_test_state *uts)
@@ -530,7 +525,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_fill_ssdt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_fill_ssdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_inject_dsdt() */
static int dm_test_acpi_inject_dsdt(struct unit_test_state *uts)
@@ -561,7 +556,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_inject_dsdt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_inject_dsdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'acpi items' command */
static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
@@ -577,7 +572,6 @@
acpi_reset_items();
ctx.current = buf;
ut_assertok(acpi_fill_ssdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("Seq Type Base Size Device/Writer");
ut_assert_nextline("--- ----- -------- ---- -------------");
@@ -588,7 +582,6 @@
acpi_reset_items();
ctx.current = buf;
ut_assertok(acpi_inject_dsdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextlinen("Seq");
ut_assert_nextlinen("---");
@@ -596,7 +589,6 @@
ut_assert_nextline(" 1 dsdt %8lx 2 acpi-test2", addr + 2);
ut_assert_console_end();
- console_record_reset();
run_command("acpi items -d", 0);
ut_assert_nextlinen("Seq");
ut_assert_nextlinen("---");
@@ -610,7 +602,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'acpi set' command */
static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
@@ -621,7 +613,6 @@
gd_set_acpi_start(0);
- console_record_reset();
ut_asserteq(0, gd_acpi_start());
ut_assertok(run_command("acpi set", 0));
ut_assert_nextline("ACPI pointer: 0");
@@ -648,7 +639,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_set, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* dm_test_write_test_table() - create test ACPI table
diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c
index 87bd8ae..0388060 100644
--- a/test/dm/acpi_dp.c
+++ b/test/dm/acpi_dp.c
@@ -7,7 +7,7 @@
*/
#include <dm.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_dp.h>
#include <asm/unaligned.h>
@@ -488,4 +488,4 @@
return 0;
}
-DM_TEST(dm_test_acpi_dp_copy, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_dp_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 7113219..23c16bd 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -9,7 +9,7 @@
#include <dm.h>
#include <irq.h>
#include <malloc.h>
-#include <uuid.h>
+#include <u-boot/uuid.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include <acpi/acpi_table.h>
@@ -167,7 +167,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_interrupt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_interrupt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a GPIO descriptor */
static int dm_test_acpi_gpio(struct unit_test_state *uts)
@@ -212,7 +212,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a GPIO descriptor with an interrupt */
static int dm_test_acpi_gpio_irq(struct unit_test_state *uts)
@@ -257,7 +257,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio_irq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio_irq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting either a GPIO or interrupt descriptor */
static int dm_test_acpi_interrupt_or_gpio(struct unit_test_state *uts)
@@ -296,8 +296,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_interrupt_or_gpio,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_interrupt_or_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting an I2C descriptor */
static int dm_test_acpi_i2c(struct unit_test_state *uts)
@@ -329,7 +328,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_i2c, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_i2c, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a SPI descriptor */
static int dm_test_acpi_spi(struct unit_test_state *uts)
@@ -365,7 +364,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_spi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_spi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a length */
static int dm_test_acpi_len(struct unit_test_state *uts)
@@ -806,7 +805,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio_toggle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio_toggle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing ACPI code to output power-sequence info */
static int dm_test_acpi_power_seq(struct unit_test_state *uts)
@@ -873,7 +872,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_power_seq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_power_seq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing values */
static int dm_test_acpi_write_values(struct unit_test_state *uts)
@@ -947,7 +946,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_scope, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_scope, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing a resource template */
static int dm_test_acpi_resource_template(struct unit_test_state *uts)
diff --git a/test/dm/adc.c b/test/dm/adc.c
index a26a677..e27302b 100644
--- a/test/dm/adc.c
+++ b/test/dm/adc.c
@@ -32,7 +32,7 @@
return 0;
}
-DM_TEST(dm_test_adc_bind, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_bind, UTF_SCAN_FDT);
static int dm_test_adc_wrong_channel_selection(struct unit_test_state *uts)
{
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_adc_wrong_channel_selection, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_wrong_channel_selection, UTF_SCAN_FDT);
static int dm_test_adc_supply(struct unit_test_state *uts)
{
@@ -79,7 +79,7 @@
return 0;
}
-DM_TEST(dm_test_adc_supply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_supply, UTF_SCAN_FDT);
struct adc_channel adc_channel_test_data[] = {
{ 0, SANDBOX_ADC_CHANNEL0_DATA },
@@ -104,7 +104,7 @@
return 0;
}
-DM_TEST(dm_test_adc_single_channel_conversion, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_single_channel_conversion, UTF_SCAN_FDT);
static int dm_test_adc_multi_channel_conversion(struct unit_test_state *uts)
{
@@ -127,7 +127,7 @@
return 0;
}
-DM_TEST(dm_test_adc_multi_channel_conversion, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_multi_channel_conversion, UTF_SCAN_FDT);
static int dm_test_adc_single_channel_shot(struct unit_test_state *uts)
{
@@ -143,7 +143,7 @@
return 0;
}
-DM_TEST(dm_test_adc_single_channel_shot, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_single_channel_shot, UTF_SCAN_FDT);
static int dm_test_adc_multi_channel_shot(struct unit_test_state *uts)
{
@@ -163,7 +163,7 @@
return 0;
}
-DM_TEST(dm_test_adc_multi_channel_shot, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_multi_channel_shot, UTF_SCAN_FDT);
static const int dm_test_adc_uV_data[SANDBOX_ADC_CHANNELS] = {
((u64)SANDBOX_ADC_CHANNEL0_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) /
@@ -194,4 +194,4 @@
return 0;
}
-DM_TEST(dm_test_adc_raw_to_uV, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_raw_to_uV, UTF_SCAN_FDT);
diff --git a/test/dm/audio.c b/test/dm/audio.c
index 3d1d821..f4d3346 100644
--- a/test/dm/audio.c
+++ b/test/dm/audio.c
@@ -31,4 +31,4 @@
return 0;
}
-DM_TEST(dm_test_audio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_audio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/axi.c b/test/dm/axi.c
index 0900a9b..45c46a1 100644
--- a/test/dm/axi.c
+++ b/test/dm/axi.c
@@ -21,8 +21,7 @@
return 0;
}
-
-DM_TEST(dm_test_axi_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox PCI bus numbering works correctly */
static int dm_test_axi_busnum(struct unit_test_state *uts)
@@ -33,8 +32,7 @@
return 0;
}
-
-DM_TEST(dm_test_axi_busnum, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_busnum, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can use the store device correctly */
static int dm_test_axi_store(struct unit_test_state *uts)
@@ -74,5 +72,4 @@
return 0;
}
-
-DM_TEST(dm_test_axi_store, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_store, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/blk.c b/test/dm/blk.c
index d03aec3..aa5cbc6 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_blk_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int count_blk_devices(void)
{
@@ -92,7 +92,7 @@
return 0;
}
-DM_TEST(dm_test_blk_usb, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_usb, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find block devices without probing them */
static int dm_test_blk_find(struct unit_test_state *uts)
@@ -114,7 +114,7 @@
return 0;
}
-DM_TEST(dm_test_blk_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that block device numbering works as expected */
static int dm_test_blk_devnum(struct unit_test_state *uts)
@@ -149,7 +149,7 @@
return 0;
}
-DM_TEST(dm_test_blk_devnum, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_devnum, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can get a block from its parent */
static int dm_test_blk_get_from_parent(struct unit_test_state *uts)
@@ -167,7 +167,7 @@
return 0;
}
-DM_TEST(dm_test_blk_get_from_parent, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_get_from_parent, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through block devices */
static int dm_test_blk_iter(struct unit_test_state *uts)
@@ -222,7 +222,7 @@
return 0;
}
-DM_TEST(dm_test_blk_iter, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_iter, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test finding fixed/removable block devices */
static int dm_test_blk_flags(struct unit_test_state *uts)
@@ -287,7 +287,7 @@
return 0;
}
-DM_TEST(dm_test_blk_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test blk_foreach() and friend */
static int dm_test_blk_foreach(struct unit_test_state *uts)
@@ -333,4 +333,4 @@
return 0;
}
-DM_TEST(dm_test_blk_foreach, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_foreach, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/blkmap.c b/test/dm/blkmap.c
index 7581e62..a6a0b4d 100644
--- a/test/dm/blkmap.c
+++ b/test/dm/blkmap.c
@@ -165,8 +165,6 @@
ulong loadaddr = env_get_hex("loadaddr", 0);
struct udevice *dev;
- console_record_reset();
-
ut_assertok(run_command("blkmap info", 0));
ut_assert_console_end();
@@ -197,4 +195,4 @@
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cmd_blkmap, 0);
+DM_TEST(dm_test_cmd_blkmap, UTF_CONSOLE);
diff --git a/test/dm/bootcount.c b/test/dm/bootcount.c
index 9cfc7d4..f66927a 100644
--- a/test/dm/bootcount.c
+++ b/test/dm/bootcount.c
@@ -35,8 +35,7 @@
return 0;
}
-
-DM_TEST(dm_test_bootcount_rtc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bootcount_rtc, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bootcount_syscon_four_bytes(struct unit_test_state *uts)
{
@@ -55,9 +54,8 @@
return 0;
}
-
DM_TEST(dm_test_bootcount_syscon_four_bytes,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bootcount_syscon_two_bytes(struct unit_test_state *uts)
{
@@ -76,6 +74,4 @@
return 0;
}
-
-DM_TEST(dm_test_bootcount_syscon_two_bytes,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bootcount_syscon_two_bytes, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 95326f2..166a842 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -41,7 +41,7 @@
return 0;
}
-DM_TEST(dm_test_bus_children, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_children, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test our functions for accessing children */
static int dm_test_bus_children_funcs(struct unit_test_state *uts)
@@ -81,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_bus_children_funcs, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_children_funcs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bus_children_of_offset(struct unit_test_state *uts)
{
@@ -105,7 +105,7 @@
return 0;
}
DM_TEST(dm_test_bus_children_of_offset,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
/* Test that we can iterate through children */
static int dm_test_bus_children_iterators(struct unit_test_state *uts)
@@ -136,7 +136,7 @@
return 0;
}
DM_TEST(dm_test_bus_children_iterators,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the bus can store data about each child */
static int test_bus_parent_data(struct unit_test_state *uts)
@@ -203,7 +203,7 @@
{
return test_bus_parent_data(uts);
}
-DM_TEST(dm_test_bus_parent_data, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_data, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* As above but the size is controlled by the uclass */
static int dm_test_bus_parent_data_uclass(struct unit_test_state *uts)
@@ -233,7 +233,7 @@
return 0;
}
DM_TEST(dm_test_bus_parent_data_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the bus ops are called when a child is probed/removed */
static int dm_test_bus_parent_ops(struct unit_test_state *uts)
@@ -270,7 +270,7 @@
return 0;
}
-DM_TEST(dm_test_bus_parent_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int test_bus_parent_plat(struct unit_test_state *uts)
{
@@ -345,7 +345,7 @@
{
return test_bus_parent_plat(uts);
}
-DM_TEST(dm_test_bus_parent_plat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_plat, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* As above but the size is controlled by the uclass */
static int dm_test_bus_parent_plat_uclass(struct unit_test_state *uts)
@@ -374,7 +374,7 @@
return 0;
}
DM_TEST(dm_test_bus_parent_plat_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind(struct unit_test_state *uts)
@@ -395,7 +395,7 @@
return 0;
}
-DM_TEST(dm_test_bus_child_post_bind, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_child_post_bind, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind_uclass(struct unit_test_state *uts)
@@ -417,7 +417,7 @@
return 0;
}
DM_TEST(dm_test_bus_child_post_bind_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that the bus' uclass' child_pre_probe() is called before the
@@ -451,7 +451,7 @@
return 0;
}
DM_TEST(dm_test_bus_child_pre_probe_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that the bus' uclass' child_post_probe() is called after the
@@ -484,4 +484,4 @@
return 0;
}
DM_TEST(dm_test_bus_child_post_probe_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/button.c b/test/dm/button.c
index 9157ec9..3612f30 100644
--- a/test/dm/button.c
+++ b/test/dm/button.c
@@ -37,7 +37,7 @@
return 0;
}
-DM_TEST(dm_test_button_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the button uclass using the button_gpio driver */
static int dm_test_button_gpio(struct unit_test_state *uts)
@@ -62,7 +62,7 @@
return 0;
}
-DM_TEST(dm_test_button_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test obtaining a BUTTON by label */
static int dm_test_button_label(struct unit_test_state *uts)
@@ -83,7 +83,7 @@
return 0;
}
-DM_TEST(dm_test_button_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_label, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test button has linux,code */
static int dm_test_button_linux_code(struct unit_test_state *uts)
@@ -95,7 +95,7 @@
return 0;
}
-DM_TEST(dm_test_button_linux_code, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_linux_code, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test adc-keys driver */
static int dm_test_button_keys_adc(struct unit_test_state *uts)
@@ -129,7 +129,7 @@
return 0;
}
-DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_keys_adc, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the button uclass using the button_gpio driver */
static int dm_test_button_cmd(struct unit_test_state *uts)
@@ -225,4 +225,4 @@
return 0;
}
-DM_TEST(dm_test_button_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d2f3bfe..e03e029 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -18,4 +18,4 @@
return 0;
}
-DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset, UTF_SCAN_FDT);
diff --git a/test/dm/clk.c b/test/dm/clk.c
index a966471..790968e 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -46,8 +46,7 @@
return 0;
}
-
-DM_TEST(dm_test_clk_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_base, UTF_SCAN_FDT);
static int dm_test_clk(struct unit_test_state *uts)
{
@@ -187,7 +186,7 @@
ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
return 0;
}
-DM_TEST(dm_test_clk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk, UTF_SCAN_FDT);
static int dm_test_clk_bulk(struct unit_test_state *uts)
{
@@ -225,4 +224,4 @@
return 0;
}
-DM_TEST(dm_test_clk_bulk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_bulk, UTF_SCAN_FDT);
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index 15fba31..ac56f17 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -208,5 +208,4 @@
return 1;
}
-
-DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_ccf, UTF_SCAN_FDT);
diff --git a/test/dm/core.c b/test/dm/core.c
index 5bc5e8e..e0c5b9e 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -175,7 +175,7 @@
return 0;
}
-DM_TEST(dm_test_autobind_uclass_pdata_alloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autobind_uclass_pdata_alloc, UTF_SCAN_PDATA);
/* compare node names ignoring the unit address */
static int dm_test_compare_node_name(struct unit_test_state *uts)
@@ -188,8 +188,7 @@
return 0;
}
-
-DM_TEST(dm_test_compare_node_name, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_compare_node_name, UTF_SCAN_PDATA);
/* Test that binding with uclass plat setting occurs correctly */
static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts)
@@ -215,7 +214,7 @@
return 0;
}
-DM_TEST(dm_test_autobind_uclass_pdata_valid, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autobind_uclass_pdata_valid, UTF_SCAN_PDATA);
/* Test that autoprobe finds all the expected devices */
static int dm_test_autoprobe(struct unit_test_state *uts)
@@ -282,7 +281,7 @@
return 0;
}
-DM_TEST(dm_test_autoprobe, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autoprobe, UTF_SCAN_PDATA);
/* Check that we see the correct plat in each device */
static int dm_test_plat(struct unit_test_state *uts)
@@ -300,7 +299,7 @@
return 0;
}
-DM_TEST(dm_test_plat, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_plat, UTF_SCAN_PDATA);
/* Test that we can bind, probe, remove, unbind a driver */
static int dm_test_lifecycle(struct unit_test_state *uts)
@@ -369,7 +368,7 @@
return 0;
}
-DM_TEST(dm_test_lifecycle, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
+DM_TEST(dm_test_lifecycle, UTF_SCAN_PDATA | UTF_PROBE_TEST);
/* Test that we can bind/unbind and the lists update correctly */
static int dm_test_ordering(struct unit_test_state *uts)
@@ -424,7 +423,7 @@
return 0;
}
-DM_TEST(dm_test_ordering, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_ordering, UTF_SCAN_PDATA);
/* Check that we can perform operations on a device (do a ping) */
int dm_check_operations(struct unit_test_state *uts, struct udevice *dev,
@@ -482,7 +481,7 @@
return 0;
}
-DM_TEST(dm_test_operations, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_operations, UTF_SCAN_PDATA);
/* Remove all drivers and check that things work */
static int dm_test_remove(struct unit_test_state *uts)
@@ -504,7 +503,7 @@
return 0;
}
-DM_TEST(dm_test_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
+DM_TEST(dm_test_remove, UTF_SCAN_PDATA | UTF_PROBE_TEST);
/* Remove and recreate everything, check for memory leaks */
static int dm_test_leak(struct unit_test_state *uts)
@@ -1033,7 +1032,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_find, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_devices_find, UTF_SCAN_PDATA);
static int dm_test_uclass_devices_find_by_name(struct unit_test_state *uts)
{
@@ -1070,7 +1069,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_find_by_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_devices_find_by_name, UTF_SCAN_FDT);
static int dm_test_uclass_devices_get(struct unit_test_state *uts)
{
@@ -1086,7 +1085,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_get, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_devices_get, UTF_SCAN_PDATA);
static int dm_test_uclass_devices_get_by_name(struct unit_test_state *uts)
{
@@ -1129,7 +1128,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_get_by_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_devices_get_by_name, UTF_SCAN_FDT);
static int dm_test_device_get_uclass_id(struct unit_test_state *uts)
{
@@ -1140,7 +1139,7 @@
return 0;
}
-DM_TEST(dm_test_device_get_uclass_id, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_device_get_uclass_id, UTF_SCAN_PDATA);
static int dm_test_uclass_names(struct unit_test_state *uts)
{
@@ -1151,7 +1150,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_names, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_names, UTF_SCAN_PDATA);
static int dm_test_inactive_child(struct unit_test_state *uts)
{
@@ -1181,7 +1180,7 @@
return 0;
}
-DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_inactive_child, UTF_SCAN_PDATA);
/* Make sure all bound devices have a sequence number */
static int dm_test_all_have_seq(struct unit_test_state *uts)
@@ -1200,7 +1199,7 @@
return 0;
}
-DM_TEST(dm_test_all_have_seq, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_all_have_seq, UTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(DM_DMA)
static int dm_test_dma_offset(struct unit_test_state *uts)
@@ -1231,7 +1230,7 @@
return 0;
}
-DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
/* Test dm_get_stats() */
@@ -1245,7 +1244,7 @@
return 0;
}
-DM_TEST(dm_test_get_stats, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_get_stats, UTF_SCAN_FDT);
/* Test uclass_find_device_by_name() */
static int dm_test_uclass_find_device(struct unit_test_state *uts)
@@ -1260,7 +1259,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_find_device, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_find_device, UTF_SCAN_FDT);
/* Test getting information about tags attached to devices */
static int dm_test_dev_get_attach(struct unit_test_state *uts)
@@ -1288,7 +1287,7 @@
return 0;
}
-DM_TEST(dm_test_dev_get_attach, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_attach, UTF_SCAN_FDT);
/* Test getting information about tags attached to bus devices */
static int dm_test_dev_get_attach_bus(struct unit_test_state *uts)
@@ -1340,7 +1339,7 @@
return 0;
}
-DM_TEST(dm_test_dev_get_attach_bus, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_attach_bus, UTF_SCAN_FDT);
/* Test getting information about tags attached to bus devices */
static int dm_test_dev_get_mem(struct unit_test_state *uts)
@@ -1351,4 +1350,4 @@
return 0;
}
-DM_TEST(dm_test_dev_get_mem, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_mem, UTF_SCAN_FDT);
diff --git a/test/dm/cpu.c b/test/dm/cpu.c
index 8af2531..9b2f90e 100644
--- a/test/dm/cpu.c
+++ b/test/dm/cpu.c
@@ -47,5 +47,4 @@
return 0;
}
-
-DM_TEST(dm_test_cpu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cpu, UTF_SCAN_FDT);
diff --git a/test/dm/cros_ec.c b/test/dm/cros_ec.c
index ac0055f..089f667 100644
--- a/test/dm/cros_ec.c
+++ b/test/dm/cros_ec.c
@@ -28,7 +28,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_hello, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_hello, UTF_SCAN_FDT);
static int dm_test_cros_ec_sku_id(struct unit_test_state *uts)
{
@@ -38,14 +38,13 @@
ut_asserteq(1234, cros_ec_get_sku_id(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec sku", 0));
ut_assert_nextline("1234");
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cros_ec_sku_id, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_sku_id, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_features(struct unit_test_state *uts)
{
@@ -64,7 +63,6 @@
ut_asserteq(true, cros_ec_check_feature(dev, EC_FEATURE_ISH));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec features", 0));
ut_assert_nextline("flash");
ut_assert_nextline("i2c");
@@ -75,7 +73,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_features, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_features, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_switches(struct unit_test_state *uts)
{
@@ -85,7 +83,6 @@
ut_asserteq(0, cros_ec_get_switches(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec switches", 0));
ut_assert_console_end();
@@ -94,14 +91,13 @@
ut_asserteq(EC_SWITCH_LID_OPEN, cros_ec_get_switches(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec switches", 0));
ut_assert_nextline("lid open");
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cros_ec_switches, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_switches, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_events(struct unit_test_state *uts)
{
@@ -113,7 +109,6 @@
ut_asserteq(0, events);
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec events", 0));
ut_assert_nextline("00000000");
ut_assert_console_end();
@@ -124,7 +119,6 @@
ut_asserteq(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN), events);
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec events", 0));
ut_assert_nextline("00000002");
ut_assert_nextline("lid_open");
@@ -138,7 +132,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_events, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_events, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_vstore(struct unit_test_state *uts)
{
@@ -174,4 +168,4 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_vstore, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_vstore, UTF_SCAN_FDT);
diff --git a/test/dm/cros_ec_pwm.c b/test/dm/cros_ec_pwm.c
index f68ee6f..0b6ca8b 100644
--- a/test/dm/cros_ec_pwm.c
+++ b/test/dm/cros_ec_pwm.c
@@ -56,4 +56,4 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_pwm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_pwm, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/devres.c b/test/dm/devres.c
index 7a3a669..efc5c72 100644
--- a/test/dm/devres.c
+++ b/test/dm/devres.c
@@ -39,7 +39,7 @@
return 0;
}
-DM_TEST(dm_test_devres_alloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_alloc, UTF_SCAN_PDATA);
/* Test devm_kfree() can be used to free memory too */
static int dm_test_devres_free(struct unit_test_state *uts)
@@ -67,7 +67,7 @@
return 0;
}
-DM_TEST(dm_test_devres_free, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_free, UTF_SCAN_PDATA);
/* Test that kzalloc() returns memory that is zeroed */
static int dm_test_devres_kzalloc(struct unit_test_state *uts)
@@ -86,7 +86,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kzalloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kzalloc, UTF_SCAN_PDATA);
/* Test that devm_kmalloc_array() allocates an array that can be set */
static int dm_test_devres_kmalloc_array(struct unit_test_state *uts)
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kmalloc_array, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kmalloc_array, UTF_SCAN_PDATA);
/* Test that devm_kcalloc() allocates a zeroed array */
static int dm_test_devres_kcalloc(struct unit_test_state *uts)
@@ -138,7 +138,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kcalloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kcalloc, UTF_SCAN_PDATA);
/* Test devres releases resources automatically as expected */
static int dm_test_devres_phase(struct unit_test_state *uts)
@@ -181,4 +181,4 @@
return 0;
}
-DM_TEST(dm_test_devres_phase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devres_phase, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/dma.c b/test/dm/dma.c
index 949710f..be38629 100644
--- a/test/dm/dma.c
+++ b/test/dm/dma.c
@@ -34,7 +34,7 @@
return 0;
}
-DM_TEST(dm_test_dma_m2m, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_m2m, UTF_SCAN_FDT);
static int dm_test_dma(struct unit_test_state *uts)
{
@@ -76,7 +76,7 @@
return 0;
}
-DM_TEST(dm_test_dma, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma, UTF_SCAN_FDT);
static int dm_test_dma_rx(struct unit_test_state *uts)
{
@@ -121,4 +121,4 @@
return 0;
}
-DM_TEST(dm_test_dma_rx, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_rx, UTF_SCAN_FDT);
diff --git a/test/dm/dsa.c b/test/dm/dsa.c
index c857106..c6b4e12 100644
--- a/test/dm/dsa.c
+++ b/test/dm/dsa.c
@@ -56,8 +56,7 @@
return 0;
}
-
-DM_TEST(dm_test_dsa_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsa_probe, UTF_SCAN_FDT);
/* This test sends ping requests with the local address through each DSA port
* via the sandbox DSA master Eth.
@@ -78,5 +77,4 @@
return 0;
}
-
-DM_TEST(dm_test_dsa, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsa, UTF_SCAN_FDT);
diff --git a/test/dm/dsi_host.c b/test/dm/dsi_host.c
index 68686a4..b927424 100644
--- a/test/dm/dsi_host.c
+++ b/test/dm/dsi_host.c
@@ -54,5 +54,4 @@
return 0;
}
-
-DM_TEST(dm_test_dsi_host, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsi_host, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/ecdsa.c b/test/dm/ecdsa.c
index da535c9..d7eac71 100644
--- a/test/dm/ecdsa.c
+++ b/test/dm/ecdsa.c
@@ -35,4 +35,4 @@
return 0;
}
-DM_TEST(dm_test_ecdsa_verify, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ecdsa_verify, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/efi_media.c b/test/dm/efi_media.c
index 9d0ed0f..0cf7e37 100644
--- a/test/dm/efi_media.c
+++ b/test/dm/efi_media.c
@@ -20,4 +20,4 @@
return 0;
}
-DM_TEST(dm_test_efi_media, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_efi_media, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 820b8cb..4674958 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -166,7 +166,7 @@
return 0;
}
-DM_TEST(dm_test_ip6_make_lladdr, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ip6_make_lladdr, UTF_SCAN_FDT);
#endif
static int dm_test_eth(struct unit_test_state *uts)
@@ -187,7 +187,7 @@
return 0;
}
-DM_TEST(dm_test_eth, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth, UTF_SCAN_FDT);
static int dm_test_eth_alias(struct unit_test_state *uts)
{
@@ -211,7 +211,7 @@
return 0;
}
-DM_TEST(dm_test_eth_alias, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_alias, UTF_SCAN_FDT);
static int dm_test_eth_prime(struct unit_test_state *uts)
{
@@ -231,7 +231,7 @@
return 0;
}
-DM_TEST(dm_test_eth_prime, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_prime, UTF_SCAN_FDT);
/**
* This test case is trying to test the following scenario:
@@ -296,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_eth_act, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_act, UTF_SCAN_FDT);
/* Ensure that all addresses are loaded properly */
static int dm_test_ethaddr(struct unit_test_state *uts)
@@ -329,7 +329,7 @@
return 0;
}
-DM_TEST(dm_test_ethaddr, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ethaddr, UTF_SCAN_FDT);
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_eth_rotate1(struct unit_test_state *uts)
@@ -401,7 +401,7 @@
return retval;
}
-DM_TEST(dm_test_eth_rotate, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_rotate, UTF_SCAN_FDT);
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_net_retry(struct unit_test_state *uts)
@@ -444,7 +444,7 @@
return retval;
}
-DM_TEST(dm_test_net_retry, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_net_retry, UTF_SCAN_FDT);
static int sb_check_arp_reply(struct udevice *dev, void *packet,
unsigned int len)
@@ -528,8 +528,7 @@
return 0;
}
-
-DM_TEST(dm_test_eth_async_arp_reply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_async_arp_reply, UTF_SCAN_FDT);
static int sb_check_ping_reply(struct udevice *dev, void *packet,
unsigned int len)
@@ -613,8 +612,7 @@
return 0;
}
-
-DM_TEST(dm_test_eth_async_ping_reply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_async_ping_reply, UTF_SCAN_FDT);
#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)
@@ -659,7 +657,6 @@
return 0;
}
-
DM_TEST(dm_test_validate_ra, 0);
static int dm_test_process_ra(struct unit_test_state *uts)
@@ -698,7 +695,6 @@
return 0;
}
-
DM_TEST(dm_test_process_ra, 0);
#endif
diff --git a/test/dm/extcon.c b/test/dm/extcon.c
index 6a4e22b..91358ab 100644
--- a/test/dm/extcon.c
+++ b/test/dm/extcon.c
@@ -17,5 +17,4 @@
return 0;
}
-
-DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_extcon, UTF_SCAN_FDT);
diff --git a/test/dm/fastboot.c b/test/dm/fastboot.c
index 5d938eb..73c43f8 100644
--- a/test/dm/fastboot.c
+++ b/test/dm/fastboot.c
@@ -91,4 +91,4 @@
return 0;
}
-DM_TEST(dm_test_fastboot_mmc_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fastboot_mmc_part, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index b484414..1f24f1d 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -55,7 +55,7 @@
return 0;
}
DM_TEST(dm_test_fdtdec_set_carveout,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts)
{
@@ -128,4 +128,4 @@
return 0;
}
DM_TEST(dm_test_fdtdec_add_reserved_memory,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/ffa.c b/test/dm/ffa.c
index fa6d54d..593b717 100644
--- a/test/dm/ffa.c
+++ b/test/dm/ffa.c
@@ -197,8 +197,7 @@
return 0;
}
-
-DM_TEST(dm_test_ffa_ack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_ffa_ack, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_ffa_nack(struct unit_test_state *uts)
{
@@ -256,5 +255,4 @@
return 0;
}
-
-DM_TEST(dm_test_ffa_nack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_ffa_nack, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/firmware.c b/test/dm/firmware.c
index ec68e81..795f6d5 100644
--- a/test/dm/firmware.c
+++ b/test/dm/firmware.c
@@ -19,4 +19,4 @@
"sandbox-firmware", &dev));
return 0;
}
-DM_TEST(dm_test_firmware_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_firmware_probe, UTF_SCAN_FDT);
diff --git a/test/dm/fpga.c b/test/dm/fpga.c
index 8bb3535..fe9f287 100644
--- a/test/dm/fpga.c
+++ b/test/dm/fpga.c
@@ -16,5 +16,4 @@
return 0;
}
-
-DM_TEST(dm_test_fpga, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fpga, UTF_SCAN_FDT);
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index 6154480..b768063 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -111,7 +111,7 @@
return 0;
}
-DM_TEST(dm_test_fwu_mdata_read, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fwu_mdata_read, UTF_SCAN_FDT);
static int dm_test_fwu_mdata_write(struct unit_test_state *uts)
{
@@ -142,4 +142,4 @@
return 0;
}
-DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fwu_mdata_write, UTF_SCAN_FDT);
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 957ab25..b45946c 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -145,7 +145,7 @@
return 0;
}
-DM_TEST(dm_test_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that GPIO open-drain/open-source emulation works correctly */
static int dm_test_gpio_opendrain_opensource(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
return 0;
}
DM_TEST(dm_test_gpio_opendrain_opensource,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox anonymous GPIOs work correctly */
static int dm_test_gpio_anon(struct unit_test_state *uts)
@@ -266,7 +266,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_anon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_anon, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that gpio_requestf() works as expected */
static int dm_test_gpio_requestf(struct unit_test_state *uts)
@@ -284,7 +284,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_requestf, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_requestf, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that gpio_request() copies its string */
static int dm_test_gpio_copy(struct unit_test_state *uts)
@@ -306,7 +306,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_copy, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we don't leak memory with GPIOs */
static int dm_test_gpio_leak(struct unit_test_state *uts)
@@ -318,7 +318,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_leak, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_leak, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find GPIOs using phandles */
static int dm_test_gpio_phandles(struct unit_test_state *uts)
@@ -392,7 +392,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_phandles, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_phandles, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check the gpio pin configuration get from device tree information */
static int dm_test_gpio_get_dir_flags(struct unit_test_state *uts)
@@ -428,7 +428,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_dir_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_dir_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of gpio_get_acpi() */
static int dm_test_gpio_get_acpi(struct unit_test_state *uts)
@@ -457,7 +457,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_acpi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_acpi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of gpio_get_acpi() with an interrupt GPIO */
static int dm_test_gpio_get_acpi_irq(struct unit_test_state *uts)
@@ -489,7 +489,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_acpi_irq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_acpi_irq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can get/release GPIOs using managed API */
static int dm_test_gpio_devm(struct unit_test_state *uts)
@@ -590,7 +590,7 @@
device_remove(dev2, DM_REMOVE_NORMAL);
return 0;
}
-DM_TEST(dm_test_gpio_devm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_devm, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_clrset_flags(struct unit_test_state *uts)
{
@@ -631,7 +631,7 @@
return 0;
}
-DM_TEST(dm_test_clrset_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clrset_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that an active-low GPIO works as expected */
static int dm_test_clrset_flags_invert(struct unit_test_state *uts)
@@ -678,7 +678,7 @@
return 0;
}
-DM_TEST(dm_test_clrset_flags_invert, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clrset_flags_invert, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int set_gpios(struct unit_test_state *uts, struct gpio_desc *desc,
int count, uint value)
@@ -719,7 +719,7 @@
return 0;
}
DM_TEST(dm_test_gpio_get_values_as_int,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that an active-low GPIO works as expected */
static int dm_test_gpio_get_values_as_int_base3(struct unit_test_state *uts)
@@ -776,7 +776,7 @@
return 0;
}
DM_TEST(dm_test_gpio_get_values_as_int_base3,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that gpio_get_status return the label of a GPIO configured as GPIOD_AF */
static int dm_test_gpio_function(struct unit_test_state *uts)
@@ -806,4 +806,4 @@
return 0;
}
DM_TEST(dm_test_gpio_function,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/host.c b/test/dm/host.c
index e514f84..f577377 100644
--- a/test/dm/host.c
+++ b/test/dm/host.c
@@ -72,7 +72,7 @@
return 0;
}
-DM_TEST(dm_test_host, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_host, UTF_SCAN_FDT);
/* reusing the same label should work */
static int dm_test_host_dup(struct unit_test_state *uts)
@@ -106,7 +106,7 @@
return 0;
}
-DM_TEST(dm_test_host_dup, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_host_dup, UTF_SCAN_FDT);
/* Basic test of 'host' command */
static int dm_test_cmd_host(struct unit_test_state *uts)
@@ -115,8 +115,6 @@
struct blk_desc *desc;
char fname[256];
- console_record_reset();
-
/* first check 'host info' with binding */
ut_assertok(run_command("host info", 0));
ut_assert_nextline("dev blocks blksz label path");
@@ -199,4 +197,4 @@
return 0;
}
-DM_TEST(dm_test_cmd_host, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_host, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c
index a05b183..58bba52 100644
--- a/test/dm/hwspinlock.c
+++ b/test/dm/hwspinlock.c
@@ -36,5 +36,4 @@
return 0;
}
-
-DM_TEST(dm_test_hwspinlock_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_hwspinlock_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index e9cf9f7..40f1f26 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -38,7 +38,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_read_write(struct unit_test_state *uts)
{
@@ -55,7 +55,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_read_write, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_read_write, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_speed(struct unit_test_state *uts)
{
@@ -77,7 +77,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_speed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_speed, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_offset_len(struct unit_test_state *uts)
{
@@ -94,7 +94,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_offset_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_offset_len, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_probe_empty(struct unit_test_state *uts)
{
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_probe_empty, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_probe_empty, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_bytewise(struct unit_test_state *uts)
{
@@ -164,7 +164,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_bytewise, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_bytewise, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_offset(struct unit_test_state *uts)
{
@@ -237,7 +237,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_addr_offset(struct unit_test_state *uts)
{
@@ -301,8 +301,7 @@
return 0;
}
-
-DM_TEST(dm_test_i2c_addr_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_addr_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_reg_clrset(struct unit_test_state *uts)
{
@@ -331,4 +330,4 @@
return 0;
}
-DM_TEST(dm_test_i2c_reg_clrset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_reg_clrset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/i2s.c b/test/dm/i2s.c
index a3d3a31..cc33669 100644
--- a/test/dm/i2s.c
+++ b/test/dm/i2s.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_i2s, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2s, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/iommu.c b/test/dm/iommu.c
index acea5f2..c5dd917 100644
--- a/test/dm/iommu.c
+++ b/test/dm/iommu.c
@@ -38,7 +38,7 @@
return 0;
}
-DM_TEST(dm_test_iommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu, UTF_SCAN_FDT);
static int dm_test_iommu_noiommu(struct unit_test_state *uts)
{
@@ -66,7 +66,7 @@
return 0;
}
-DM_TEST(dm_test_iommu_noiommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_noiommu, UTF_SCAN_FDT);
static int dm_test_iommu_pci(struct unit_test_state *uts)
{
@@ -81,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_iommu_pci, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_pci, UTF_SCAN_FDT);
static int dm_test_iommu_pci_noiommu(struct unit_test_state *uts)
{
@@ -96,4 +96,4 @@
return 0;
}
-DM_TEST(dm_test_iommu_pci_noiommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_pci_noiommu, UTF_SCAN_FDT);
diff --git a/test/dm/irq.c b/test/dm/irq.c
index d22772a..836f2d8 100644
--- a/test/dm/irq.c
+++ b/test/dm/irq.c
@@ -30,7 +30,7 @@
return 0;
}
-DM_TEST(dm_test_irq_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_first_device_type() */
static int dm_test_irq_type(struct unit_test_state *uts)
@@ -42,7 +42,7 @@
return 0;
}
-DM_TEST(dm_test_irq_type, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_type, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_read_and_clear() */
static int dm_test_read_and_clear(struct unit_test_state *uts)
@@ -59,7 +59,7 @@
return 0;
}
-DM_TEST(dm_test_read_and_clear, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_and_clear, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_request() */
static int dm_test_request(struct unit_test_state *uts)
@@ -74,7 +74,7 @@
return 0;
}
-DM_TEST(dm_test_request, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_request, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_get_acpi() */
static int dm_test_irq_get_acpi(struct unit_test_state *uts)
@@ -96,4 +96,4 @@
return 0;
}
-DM_TEST(dm_test_irq_get_acpi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_get_acpi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/led.c b/test/dm/led.c
index c28fa04..e1509c3 100644
--- a/test/dm/led.c
+++ b/test/dm/led.c
@@ -24,7 +24,7 @@
return 0;
}
-DM_TEST(dm_test_led_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the LED 'default-state' device tree property */
static int dm_test_led_default_state(struct unit_test_state *uts)
@@ -41,7 +41,7 @@
return 0;
}
-DM_TEST(dm_test_led_default_state, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_default_state, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the led uclass using the led_gpio driver */
static int dm_test_led_gpio(struct unit_test_state *uts)
@@ -66,7 +66,7 @@
return 0;
}
-DM_TEST(dm_test_led_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can toggle LEDs */
static int dm_test_led_toggle(struct unit_test_state *uts)
@@ -91,7 +91,7 @@
return 0;
}
-DM_TEST(dm_test_led_toggle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_toggle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test obtaining an LED by label */
static int dm_test_led_label(struct unit_test_state *uts)
@@ -112,7 +112,7 @@
return 0;
}
-DM_TEST(dm_test_led_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_label, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test LED blinking */
#ifdef CONFIG_LED_BLINK
@@ -135,5 +135,5 @@
return 0;
}
-DM_TEST(dm_test_led_blink, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c
index 14f72d5..4a0648b 100644
--- a/test/dm/mailbox.c
+++ b/test/dm/mailbox.c
@@ -28,4 +28,4 @@
return 0;
}
-DM_TEST(dm_test_mailbox, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mailbox, UTF_SCAN_FDT);
diff --git a/test/dm/mdio.c b/test/dm/mdio.c
index 7ececf3..6760c98 100644
--- a/test/dm/mdio.c
+++ b/test/dm/mdio.c
@@ -53,5 +53,4 @@
return 0;
}
-
-DM_TEST(dm_test_mdio, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mdio, UTF_SCAN_FDT);
diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c
index 33a7e97..866feb2 100644
--- a/test/dm/mdio_mux.c
+++ b/test/dm/mdio_mux.c
@@ -76,5 +76,4 @@
return 0;
}
-
-DM_TEST(dm_test_mdio_mux, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mdio_mux, UTF_SCAN_FDT);
diff --git a/test/dm/memory.c b/test/dm/memory.c
index 7d9500a..34e64ba 100644
--- a/test/dm/memory.c
+++ b/test/dm/memory.c
@@ -17,5 +17,4 @@
return 0;
}
-
-DM_TEST(dm_test_memory, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_memory, UTF_SCAN_FDT);
diff --git a/test/dm/misc.c b/test/dm/misc.c
index ad856fd..250885d 100644
--- a/test/dm/misc.c
+++ b/test/dm/misc.c
@@ -79,5 +79,4 @@
return 0;
}
-
-DM_TEST(dm_test_misc, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_misc, UTF_SCAN_FDT);
diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index c0abea7..cdebb95 100644
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -22,7 +22,7 @@
return 0;
}
-DM_TEST(dm_test_mmc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mmc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_mmc_blk(struct unit_test_state *uts)
{
@@ -50,4 +50,4 @@
return 0;
}
-DM_TEST(dm_test_mmc_blk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mmc_blk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c
index d4bb8be..6eb3b28 100644
--- a/test/dm/mux-cmd.c
+++ b/test/dm/mux-cmd.c
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cmd_mux_select(struct unit_test_state *uts)
{
@@ -143,7 +143,7 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_select, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_select, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_cmd_mux_deselect(struct unit_test_state *uts)
{
@@ -174,4 +174,4 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_deselect, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_deselect, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c
index febd521..de231e4 100644
--- a/test/dm/mux-emul.c
+++ b/test/dm/mux-emul.c
@@ -79,7 +79,7 @@
return 0;
}
-DM_TEST(dm_test_mux_emul_default_state, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_emul_default_state, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_mux_emul_select_deselect(struct unit_test_state *uts)
{
@@ -102,4 +102,4 @@
return 0;
}
-DM_TEST(dm_test_mux_emul_select_deselect, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_emul_select_deselect, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c
index 3a871a1..3bb1e49 100644
--- a/test/dm/mux-mmio.c
+++ b/test/dm/mux-mmio.c
@@ -85,7 +85,7 @@
return 0;
}
-DM_TEST(dm_test_mux_mmio_select, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_mmio_select, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that managed API for mux work correctly */
static int dm_test_devm_mux_mmio(struct unit_test_state *uts)
@@ -134,4 +134,4 @@
device_remove(dev_b, DM_REMOVE_NORMAL);
return 0;
}
-DM_TEST(dm_test_devm_mux_mmio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_mux_mmio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/nand.c b/test/dm/nand.c
index 0b992fd..c7e0985 100644
--- a/test/dm/nand.c
+++ b/test/dm/nand.c
@@ -12,7 +12,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
-static int dm_test_nand(struct unit_test_state *uts, int dev, bool end)
+static int run_test_nand(struct unit_test_state *uts, int dev, bool end)
{
nand_erase_options_t opts = { };
struct mtd_info *mtd;
@@ -88,17 +88,34 @@
return 0;
}
-#define DM_NAND_TEST(dev) \
-static int dm_test_nand##dev##_start(struct unit_test_state *uts) \
-{ \
- return dm_test_nand(uts, dev, false); \
-} \
-DM_TEST(dm_test_nand##dev##_start, UT_TESTF_SCAN_FDT); \
-static int dm_test_nand##dev##_end(struct unit_test_state *uts) \
-{ \
- return dm_test_nand(uts, dev, true); \
-} \
-DM_TEST(dm_test_nand##dev##_end, UT_TESTF_SCAN_FDT)
+static int dm_test_nand0_start(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 0, false));
+
+ return 0;
+}
+DM_TEST(dm_test_nand0_start, UTF_SCAN_FDT);
+
+static int dm_test_nand1_start(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 1, false));
+
+ return 0;
+}
+DM_TEST(dm_test_nand1_start, UTF_SCAN_FDT);
-DM_NAND_TEST(0);
-DM_NAND_TEST(1);
+static int dm_test_nand0_end(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 0, true));
+
+ return 0;
+}
+DM_TEST(dm_test_nand0_end, UTF_SCAN_FDT);
+
+static int dm_test_nand1_end(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 1, true));
+
+ return 0;
+}
+DM_TEST(dm_test_nand1_end, UTF_SCAN_FDT);
diff --git a/test/dm/nop.c b/test/dm/nop.c
index 0c79431..a6f5f82 100644
--- a/test/dm/nop.c
+++ b/test/dm/nop.c
@@ -69,5 +69,4 @@
return 0;
}
-
-DM_TEST(dm_test_nop, UT_TESTF_FLAT_TREE | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_nop, UTF_FLAT_TREE | UTF_SCAN_FDT);
diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
index 537959a..a702d0a 100644
--- a/test/dm/nvmxip.c
+++ b/test/dm/nvmxip.c
@@ -142,5 +142,4 @@
return CMD_RET_SUCCESS;
}
-
-DM_TEST(dm_test_nvmxip, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_nvmxip, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c
index d4939e8..6e35bca 100644
--- a/test/dm/of_platdata.c
+++ b/test/dm/of_platdata.c
@@ -20,7 +20,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_base, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_base, UTF_SCAN_PDATA);
/* Test that we can read properties from a device */
static int dm_test_of_plat_props(struct unit_test_state *uts)
@@ -91,7 +91,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_props, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_props, UTF_SCAN_PDATA);
/*
* find_driver_info - recursively find the driver_info for a device
@@ -173,7 +173,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_dev, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_dev, UTF_SCAN_PDATA);
/* Test handling of phandles that point to other devices */
static int dm_test_of_plat_phandle(struct unit_test_state *uts)
@@ -206,7 +206,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_phandle, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_phandle, UTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)
/* Test that device parents are correctly set up */
@@ -220,7 +220,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_parent, UTF_SCAN_PDATA);
#endif
/* Test clocks with of-platdata */
@@ -239,7 +239,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_clk, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_clk, UTF_SCAN_PDATA);
/* Test irqs with of-platdata */
static int dm_test_of_plat_irq(struct unit_test_state *uts)
@@ -258,7 +258,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_irq, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_irq, UTF_SCAN_PDATA);
/* Test GPIOs with of-platdata */
static int dm_test_of_plat_gpio(struct unit_test_state *uts)
@@ -277,4 +277,4 @@
return 0;
}
-DM_TEST(dm_test_of_plat_gpio, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_gpio, UTF_SCAN_PDATA);
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 39191d7..859fc3a 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -47,7 +47,7 @@
/* An invalid tree may cause failure or crashes */
if (!oftree_valid(tree))
- ut_reportf("test needs the UT_TESTF_OTHER_FDT flag");
+ ut_reportf("test needs the UTF_OTHER_FDT flag");
return tree;
}
@@ -103,7 +103,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_compatible,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* check ofnode_device_is_compatible() with the 'other' FDT */
static int dm_test_ofnode_compatible_ot(struct unit_test_state *uts)
@@ -116,7 +116,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_compatible_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_get_by_phandle(struct unit_test_state *uts)
{
@@ -134,7 +134,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_by_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_by_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test oftree_get_by_phandle() with a the 'other' oftree */
static int dm_test_ofnode_get_by_phandle_ot(struct unit_test_state *uts)
@@ -150,7 +150,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_by_phandle_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
static int check_prop_values(struct unit_test_state *uts, ofnode start,
const char *propname, const char *propval,
@@ -189,7 +189,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_prop_value, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_by_prop_value, UTF_SCAN_FDT);
/* test ofnode_by_prop_value() with a the 'other' oftree */
static int dm_test_ofnode_by_prop_value_ot(struct unit_test_state *uts)
@@ -202,7 +202,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_by_prop_value_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_read_fmap_entry() */
static int dm_test_ofnode_fmap(struct unit_test_state *uts)
@@ -218,7 +218,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_fmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_fmap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_prop() */
static int dm_test_ofnode_read(struct unit_test_state *uts)
@@ -248,7 +248,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read, UTF_SCAN_FDT);
/* test ofnode_read_prop() with the 'other' tree */
static int dm_test_ofnode_read_ot(struct unit_test_state *uts)
@@ -271,7 +271,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_read_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_count_/parse_phandle_with_args() */
static int dm_test_ofnode_phandle(struct unit_test_state *uts)
@@ -347,7 +347,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_count_/parse_phandle_with_args() with 'other' tree */
static int dm_test_ofnode_phandle_ot(struct unit_test_state *uts)
@@ -376,7 +376,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_phandle_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_phandle_ot, UTF_OTHER_FDT);
/* test ofnode_read_chosen_string/node/prop() */
static int dm_test_ofnode_read_chosen(struct unit_test_state *uts)
@@ -406,7 +406,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_chosen, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_chosen, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_aliases_node/prop() */
static int dm_test_ofnode_read_aliases(struct unit_test_state *uts)
@@ -429,7 +429,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_aliases, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_aliases, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_ofnode_get_child_count(struct unit_test_state *uts)
{
@@ -450,7 +450,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_child_count,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_child_count() with 'other' tree */
static int dm_test_ofnode_get_child_count_ot(struct unit_test_state *uts)
@@ -473,7 +473,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_child_count_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_is_enabled(struct unit_test_state *uts)
{
@@ -485,7 +485,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_is_enabled, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_is_enabled() with 'other' tree */
static int dm_test_ofnode_is_enabled_ot(struct unit_test_state *uts)
@@ -499,7 +499,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_is_enabled_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_is_enabled_ot, UTF_OTHER_FDT);
/* test ofnode_get_addr/size() */
static int dm_test_ofnode_get_reg(struct unit_test_state *uts)
@@ -536,7 +536,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_reg, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_addr() with 'other' tree */
static int dm_test_ofnode_get_reg_ot(struct unit_test_state *uts)
@@ -550,7 +550,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_reg_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_reg_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_get_path(struct unit_test_state *uts)
{
@@ -571,7 +571,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_path() with 'other' tree */
static int dm_test_ofnode_get_path_ot(struct unit_test_state *uts)
@@ -591,7 +591,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_path_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_path_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_conf_read_bool/int/str() */
static int dm_test_ofnode_conf(struct unit_test_state *uts)
@@ -607,7 +607,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_conf, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_conf, UTF_SCAN_FDT);
static int dm_test_ofnode_options(struct unit_test_state *uts)
{
@@ -644,7 +644,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_for_each_compatible_node, UTF_SCAN_FDT);
/* test dm_test_ofnode_string_count/index/list() */
static int dm_test_ofnode_string(struct unit_test_state *uts)
@@ -692,7 +692,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_string, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_string, UTF_SCAN_FDT);
/* test error returns from ofnode_read_string_count/index/list() */
static int dm_test_ofnode_string_err(struct unit_test_state *uts)
@@ -742,7 +742,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_string_err, UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_ofnode_string_err, UTF_LIVE_TREE);
static int dm_test_ofnode_read_phy_mode(struct unit_test_state *uts)
{
@@ -764,7 +764,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_phy_mode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_phy_mode, UTF_SCAN_FDT);
/**
* make_ofnode_fdt() - Create an FDT for testing with ofnode
@@ -811,7 +811,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_aliases, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_aliases, UTF_SCAN_FDT);
/**
* dm_test_ofnode_root_mult() - Check aliaes on control and 'other' tree
@@ -850,7 +850,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_root_mult, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_root_mult, UTF_SCAN_FDT);
/* test ofnode_set_enabled(), ofnode_write_prop() on a livetree */
static int dm_test_ofnode_livetree_writing(struct unit_test_state *uts)
@@ -897,7 +897,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_livetree_writing,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int check_write_prop(struct unit_test_state *uts, ofnode node)
{
@@ -940,7 +940,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_write_copy, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_write_copy, UTF_SCAN_FDT);
/* test writing a property to the 'other' tree */
static int dm_test_ofnode_write_copy_ot(struct unit_test_state *uts)
@@ -957,7 +957,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_write_copy_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_write_copy_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_read_u32_index/default() */
static int dm_test_ofnode_u32(struct unit_test_state *uts)
@@ -985,7 +985,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_u32_array() */
static int dm_test_ofnode_u32_array(struct unit_test_state *uts)
@@ -1012,7 +1012,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u32_array, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u32_array, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_u64() and ofnode_write_u64() */
static int dm_test_ofnode_u64(struct unit_test_state *uts)
@@ -1046,7 +1046,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u64, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u64, UTF_SCAN_FDT);
static int dm_test_ofnode_add_subnode(struct unit_test_state *uts)
{
@@ -1115,7 +1115,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_add_subnode, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_add_subnode, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_ofnode_for_each_prop(struct unit_test_state *uts)
{
@@ -1139,7 +1139,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_for_each_prop, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_for_each_prop, UTF_SCAN_FDT);
static int dm_test_ofnode_by_compatible(struct unit_test_state *uts)
{
@@ -1155,7 +1155,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_compatible, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_by_compatible, UTF_SCAN_FDT);
/* check ofnode_by_compatible() on the 'other' tree */
static int dm_test_ofnode_by_compatible_ot(struct unit_test_state *uts)
@@ -1173,7 +1173,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_by_compatible_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_find_subnode(struct unit_test_state *uts)
{
@@ -1190,7 +1190,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_find_subnode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_find_subnode, UTF_SCAN_FDT);
/* test ofnode_find_subnode() on the 'other' tree */
static int dm_test_ofnode_find_subnode_ot(struct unit_test_state *uts)
@@ -1209,7 +1209,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_find_subnode_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_find_subnode_ot, UTF_OTHER_FDT);
static int dm_test_ofnode_get_name(struct unit_test_state *uts)
{
@@ -1222,7 +1222,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_name, UTF_SCAN_FDT);
/* try to access more FDTs than is supported */
static int dm_test_ofnode_too_many(struct unit_test_state *uts)
@@ -1259,7 +1259,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_too_many, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_too_many, UTF_SCAN_FDT);
static int check_copy_props(struct unit_test_state *uts, ofnode dst, ofnode src)
{
@@ -1304,7 +1304,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_props, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_copy_props, UTF_SCAN_FDT);
/* test ofnode_copy_props() with the 'other' tree */
static int dm_test_ofnode_copy_props_ot(struct unit_test_state *uts)
@@ -1318,7 +1318,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_props_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_copy_props_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* check that the livetree is aligned to a structure boundary */
static int dm_test_livetree_align(struct unit_test_state *uts)
@@ -1344,7 +1344,7 @@
return 0;
}
-DM_TEST(dm_test_livetree_align, UT_TESTF_SCAN_FDT | UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_livetree_align, UTF_SCAN_FDT | UTF_LIVE_TREE);
/* check that it is possible to load an arbitrary livetree */
static int dm_test_livetree_ensure(struct unit_test_state *uts)
@@ -1363,7 +1363,7 @@
return 0;
}
-DM_TEST(dm_test_livetree_ensure, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_livetree_ensure, UTF_SCAN_FDT);
static int dm_test_oftree_new(struct unit_test_state *uts)
{
@@ -1379,7 +1379,7 @@
return 0;
}
-DM_TEST(dm_test_oftree_new, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_oftree_new, UTF_SCAN_FDT);
static int check_copy_node(struct unit_test_state *uts, ofnode dst, ofnode src,
ofnode *nodep)
@@ -1428,7 +1428,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_node, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_copy_node, UTF_SCAN_FDT);
/* test ofnode_copy_node() with the 'other' tree */
static int dm_test_ofnode_copy_node_ot(struct unit_test_state *uts)
@@ -1442,7 +1442,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_node_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_copy_node_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_delete(struct unit_test_state *uts)
{
@@ -1473,7 +1473,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_delete, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_delete, UTF_SCAN_FDT);
static int dm_test_oftree_to_fdt(struct unit_test_state *uts)
{
@@ -1495,7 +1495,7 @@
return 0;
}
-DM_TEST(dm_test_oftree_to_fdt, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_oftree_to_fdt, UTF_SCAN_FDT);
/* test ofnode_read_bool() and ofnode_write_bool() */
static int dm_test_bool(struct unit_test_state *uts)
@@ -1520,4 +1520,4 @@
return 0;
}
-DM_TEST(dm_test_bool, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bool, UTF_SCAN_FDT);
diff --git a/test/dm/ofread.c b/test/dm/ofread.c
index 69d03c4..069551a 100644
--- a/test/dm/ofread.c
+++ b/test/dm/ofread.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_ofprop_get_property, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofprop_get_property, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/osd.c b/test/dm/osd.c
index cf4a3a5..5fb27a3 100644
--- a/test/dm/osd.c
+++ b/test/dm/osd.c
@@ -130,8 +130,7 @@
return 0;
}
-
-DM_TEST(dm_test_osd_basics, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_osd_basics, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_osd_extended(struct unit_test_state *uts)
{
@@ -214,5 +213,4 @@
return 0;
}
-
-DM_TEST(dm_test_osd_extended, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_osd_extended, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c
index 3ada1fc..4cc374e 100644
--- a/test/dm/p2sb.c
+++ b/test/dm/p2sb.c
@@ -24,4 +24,4 @@
return 0;
}
-DM_TEST(dm_test_p2sb_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_p2sb_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/panel.c b/test/dm/panel.c
index 8be7c39..ec85a9b 100644
--- a/test/dm/panel.c
+++ b/test/dm/panel.c
@@ -33,7 +33,7 @@
ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
&enable, &polarity));
ut_asserteq(false, enable);
- ut_asserteq(false, regulator_get_enable(reg));
+ ut_asserteq(true, regulator_get_enable(reg));
ut_assertok(panel_enable_backlight(dev));
ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
@@ -76,4 +76,4 @@
return 0;
}
-DM_TEST(dm_test_panel, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_panel, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/part.c b/test/dm/part.c
index cabb31d..c5c4b3f 100644
--- a/test/dm/part.c
+++ b/test/dm/part.c
@@ -93,7 +93,7 @@
env_set("bootdevice", oldbootdevice);
return ret;
}
-DM_TEST(dm_test_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_part_bootable(struct unit_test_state *uts)
{
@@ -106,7 +106,7 @@
return 0;
}
-DM_TEST(dm_test_part_bootable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part_bootable, UTF_SCAN_FDT);
static int do_get_info_test(struct unit_test_state *uts,
struct blk_desc *dev_desc, int part, int part_type,
@@ -193,4 +193,4 @@
return 0;
}
-DM_TEST(dm_test_part_get_info_by_type, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part_get_info_by_type, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pch.c b/test/dm/pch.c
index b37b856..88e924d 100644
--- a/test/dm/pch.c
+++ b/test/dm/pch.c
@@ -33,7 +33,7 @@
return 0;
}
-DM_TEST(dm_test_pch_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pch_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test sandbox PCH ioctl */
static int dm_test_pch_ioctl(struct unit_test_state *uts)
@@ -52,4 +52,4 @@
return 0;
}
-DM_TEST(dm_test_pch_ioctl, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pch_ioctl, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pci.c b/test/dm/pci.c
index 9b97f2e..6eb19f6 100644
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -19,7 +19,7 @@
return 0;
}
-DM_TEST(dm_test_pci_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox PCI bus numbering and device works correctly */
static int dm_test_pci_busdev(struct unit_test_state *uts)
@@ -54,7 +54,7 @@
return 0;
}
-DM_TEST(dm_test_pci_busdev, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_busdev, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
@@ -107,7 +107,7 @@
return 0;
}
-DM_TEST(dm_test_pci_swapcase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_swapcase, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can dynamically bind the device driver correctly */
static int dm_test_pci_drvdata(struct unit_test_state *uts)
@@ -129,7 +129,7 @@
return 0;
}
-DM_TEST(dm_test_pci_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_drvdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that devices on PCI bus#2 can be accessed correctly */
static int dm_test_pci_mixed(struct unit_test_state *uts)
@@ -192,7 +192,7 @@
return 0;
}
-DM_TEST(dm_test_pci_mixed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_mixed, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test looking up PCI capability and extended capability */
static int dm_test_pci_cap(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
return 0;
}
-DM_TEST(dm_test_pci_cap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_cap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test looking up BARs in EA capability structure */
static int dm_test_pci_ea(struct unit_test_state *uts)
@@ -293,7 +293,7 @@
return 0;
}
-DM_TEST(dm_test_pci_ea, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_ea, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test the dev_read_addr_pci() function */
static int dm_test_pci_addr_flat(struct unit_test_state *uts)
@@ -318,14 +318,14 @@
return 0;
}
-DM_TEST(dm_test_pci_addr_flat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_FLAT_TREE);
+DM_TEST(dm_test_pci_addr_flat, UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_FLAT_TREE);
/*
* Test the dev_read_addr_pci() function with livetree. That function is
* not currently fully implemented, in that it fails to return the BAR address.
* Once that is implemented this test can be removed and dm_test_pci_addr_flat()
- * can be used for both flattree and livetree by removing the UT_TESTF_FLAT_TREE
+ * can be used for both flattree and livetree by removing the UTF_FLAT_TREE
* flag above.
*/
static int dm_test_pci_addr_live(struct unit_test_state *uts)
@@ -343,8 +343,7 @@
return 0;
}
-DM_TEST(dm_test_pci_addr_live, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_pci_addr_live, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_LIVE_TREE);
/* Test device_is_on_pci_bus() */
static int dm_test_pci_on_bus(struct unit_test_state *uts)
@@ -358,7 +357,7 @@
return 0;
}
-DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_on_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test support for multiple memory regions enabled via
@@ -380,7 +379,7 @@
return 0;
}
-DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_region_multi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test the translation of PCI bus addresses to physical addresses using the
@@ -433,7 +432,7 @@
return 0;
}
-DM_TEST(dm_test_pci_bus_to_phys, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_bus_to_phys, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test the translation of physical addresses to PCI bus addresses using the
@@ -486,4 +485,4 @@
return 0;
}
-DM_TEST(dm_test_pci_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c
index e82fc53..068b72a 100644
--- a/test/dm/pci_ep.c
+++ b/test/dm/pci_ep.c
@@ -59,5 +59,4 @@
ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10);
return 0;
}
-
-DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_ep_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/phy.c b/test/dm/phy.c
index d14117f..194cad0 100644
--- a/test/dm/phy.c
+++ b/test/dm/phy.c
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_phy_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the phy uclass using the sandbox phy driver operations */
static int dm_test_phy_ops(struct unit_test_state *uts)
@@ -140,7 +140,7 @@
return 0;
}
-DM_TEST(dm_test_phy_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_bulk(struct unit_test_state *uts)
{
@@ -173,7 +173,7 @@
return 0;
}
-DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_bulk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_multi_exit(struct unit_test_state *uts)
{
@@ -232,7 +232,7 @@
return 0;
}
-DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_multi_exit, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_setup(struct unit_test_state *uts)
{
@@ -243,22 +243,29 @@
"gen_phy_user", &parent));
/* normal */
- ut_assertok(generic_setup_phy(parent, &phy, 0));
+ ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0));
ut_assertok(generic_shutdown_phy(&phy));
+ /* set_mode as USB Host passes, anything else is not supported */
+ ut_assertok(generic_setup_phy(parent, &phy, 0, PHY_MODE_USB_HOST, 0));
+ ut_assertok(generic_phy_set_mode(&phy, PHY_MODE_USB_HOST, 0));
+ ut_asserteq(-EOPNOTSUPP, generic_phy_set_mode(&phy, PHY_MODE_USB_HOST, 1));
+ ut_asserteq(-EINVAL, generic_phy_set_mode(&phy, PHY_MODE_USB_DEVICE, 0));
+ ut_assertok(generic_shutdown_phy(&phy));
+
/* power_off fail with -EIO */
- ut_assertok(generic_setup_phy(parent, &phy, 1));
+ ut_assertok(generic_setup_phy(parent, &phy, 1, PHY_MODE_USB_HOST, 0));
ut_asserteq(-EIO, generic_shutdown_phy(&phy));
/* power_on fail with -EIO */
- ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2));
+ ut_asserteq(-EIO, generic_setup_phy(parent, &phy, 2, PHY_MODE_USB_HOST, 0));
ut_assertok(generic_shutdown_phy(&phy));
/* generic_phy_get_by_index fail with -ENOENT */
ut_asserteq(-ENOENT, generic_phy_get_by_index(parent, 3, &phy));
- ut_assertok(generic_setup_phy(parent, &phy, 3));
+ ut_assertok(generic_setup_phy(parent, &phy, 3, PHY_MODE_USB_HOST, 0));
ut_assertok(generic_shutdown_phy(&phy));
return 0;
}
-DM_TEST(dm_test_phy_setup, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_setup, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c
index 1ee2150..0f30c7e 100644
--- a/test/dm/phys2bus.c
+++ b/test/dm/phys2bus.c
@@ -33,4 +33,4 @@
return 0;
}
-DM_TEST(dm_test_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c
index cfbe3ef..92e5bc8 100644
--- a/test/dm/pinmux.c
+++ b/test/dm/pinmux.c
@@ -68,8 +68,7 @@
return 0;
}
-
-DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pinmux, UTF_SCAN_FDT);
static int dm_test_pinctrl_single(struct unit_test_state *uts)
{
@@ -143,5 +142,4 @@
ut_asserteq(-EINVAL, ret);
return 0;
}
-
-DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pinctrl_single, UTF_SCAN_FDT);
diff --git a/test/dm/pmc.c b/test/dm/pmc.c
index bbad1ee..0012279 100644
--- a/test/dm/pmc.c
+++ b/test/dm/pmc.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_pmc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pmc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pmic.c b/test/dm/pmic.c
index 53a6f03..70dd18f 100644
--- a/test/dm/pmic.c
+++ b/test/dm/pmic.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_power_pmic_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_get, UTF_SCAN_FDT);
/* PMIC get method - MC34708 - for 3 bytes transmission */
static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
@@ -52,8 +52,7 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_get, UTF_SCAN_FDT);
/* Test PMIC I/O */
static int dm_test_power_pmic_io(struct unit_test_state *uts)
@@ -82,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_power_pmic_io, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_io, UTF_SCAN_FDT);
#define MC34708_PMIC_REG_COUNT 64
#define MC34708_PMIC_TEST_VAL 0x125534
@@ -99,8 +98,7 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_regs_check, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_regs_check, UTF_SCAN_FDT);
static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
{
@@ -126,5 +124,4 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_rw_val, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_rw_val, UTF_SCAN_FDT);
diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
index 120a905..896cf5b 100644
--- a/test/dm/power-domain.c
+++ b/test/dm/power-domain.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_power_domain, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_domain, UTF_SCAN_FDT);
diff --git a/test/dm/pwm.c b/test/dm/pwm.c
index 8013334..5ccd8bc 100644
--- a/test/dm/pwm.c
+++ b/test/dm/pwm.c
@@ -41,4 +41,4 @@
return 0;
}
-DM_TEST(dm_test_pwm_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pwm_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/qfw.c b/test/dm/qfw.c
index 3c35416..b6be5c5 100644
--- a/test/dm/qfw.c
+++ b/test/dm/qfw.c
@@ -23,8 +23,7 @@
return 0;
}
-
-DM_TEST(dm_test_qfw_cpus, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_qfw_cpus, UTF_SCAN_PDATA);
static int dm_test_qfw_firmware_list(struct unit_test_state *uts)
{
@@ -37,5 +36,4 @@
return 0;
}
-
-DM_TEST(dm_test_qfw_firmware_list, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_qfw_firmware_list, UTF_SCAN_PDATA);
diff --git a/test/dm/ram.c b/test/dm/ram.c
index 188c7c3..f3710b1 100644
--- a/test/dm/ram.c
+++ b/test/dm/ram.c
@@ -25,4 +25,4 @@
return 0;
}
-DM_TEST(dm_test_ram_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ram_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/read.c b/test/dm/read.c
index 4ecf181..0aa8221 100644
--- a/test/dm/read.c
+++ b/test/dm/read.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_dma_ranges, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_ranges, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/reboot-mode.c b/test/dm/reboot-mode.c
index 160b4da..9a3b2bf 100644
--- a/test/dm/reboot-mode.c
+++ b/test/dm/reboot-mode.c
@@ -39,9 +39,8 @@
return 0;
}
-
DM_TEST(dm_test_reboot_mode_gpio,
- UT_TESTF_PROBE_TEST | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_reboot_mode_rtc(struct unit_test_state *uts)
{
@@ -65,6 +64,5 @@
return 0;
}
-
DM_TEST(dm_test_reboot_mode_rtc,
- UT_TESTF_PROBE_TEST | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/regmap.c b/test/dm/regmap.c
index 1398f8f..5024b47 100644
--- a/test/dm/regmap.c
+++ b/test/dm/regmap.c
@@ -69,7 +69,7 @@
return 0;
}
-DM_TEST(dm_test_regmap_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test we can access a regmap through syscon */
static int dm_test_regmap_syscon(struct unit_test_state *uts)
@@ -94,8 +94,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_syscon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_syscon, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read/Write/Modify test */
static int dm_test_regmap_rw(struct unit_test_state *uts)
@@ -128,8 +127,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_rw, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Get/Set test */
static int dm_test_regmap_getset(struct unit_test_state *uts)
@@ -159,8 +157,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_getset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_getset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read polling test */
static int dm_test_regmap_poll(struct unit_test_state *uts)
@@ -187,8 +184,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_poll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_poll, UTF_SCAN_PDATA | UTF_SCAN_FDT);
struct regmaptest_priv {
struct regmap *cfg_regmap; /* For testing regmap_config options. */
@@ -324,7 +320,7 @@
return 0;
}
-DM_TEST(dm_test_devm_regmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_regmap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int test_one_field(struct unit_test_state *uts,
struct regmap *regmap,
@@ -383,4 +379,4 @@
return 0;
}
-DM_TEST(dm_test_devm_regmap_field, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_regmap_field, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/regulator.c b/test/dm/regulator.c
index 9e45fd1..449748a 100644
--- a/test/dm/regulator.c
+++ b/test/dm/regulator.c
@@ -89,7 +89,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_get, UTF_SCAN_FDT);
/* Test regulator set and get Voltage method */
static int dm_test_power_regulator_set_get_voltage(struct unit_test_state *uts)
@@ -116,7 +116,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_voltage, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_voltage, UTF_SCAN_FDT);
/* Test regulator set and get Current method */
static int dm_test_power_regulator_set_get_current(struct unit_test_state *uts)
@@ -155,7 +155,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_current, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_current, UTF_SCAN_FDT);
/* Test regulator set and get Enable method */
static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts)
@@ -174,7 +174,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_enable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_enable, UTF_SCAN_FDT);
/* Test regulator set and get enable if allowed method */
static
@@ -186,7 +186,7 @@
/* Get BUCK1 - always on regulator */
platname = regulator_names[BUCK1][PLATNAME];
- ut_assertok(regulator_autoset_by_name(platname, &dev_autoset));
+ ut_asserteq(-EALREADY, regulator_autoset_by_name(platname, &dev_autoset));
ut_assertok(regulator_get_by_platname(platname, &dev));
/* Try disabling always-on regulator */
@@ -195,7 +195,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_enable_if_allowed, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_enable_if_allowed, UTF_SCAN_FDT);
/* Test regulator set and get mode method */
static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts)
@@ -214,7 +214,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_mode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_mode, UTF_SCAN_FDT);
/* Test regulator set and get suspend Voltage method */
static int dm_test_power_regulator_set_get_suspend_voltage(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
}
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_suspend_voltage, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_suspend_voltage, UTF_SCAN_FDT);
/* Test regulator set and get suspend Enable method */
static int dm_test_power_regulator_set_get_suspend_enable(struct unit_test_state *uts)
@@ -271,7 +271,7 @@
}
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_suspend_enable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_suspend_enable, UTF_SCAN_FDT);
/* Test regulator autoset method */
static int dm_test_power_regulator_autoset(struct unit_test_state *uts)
@@ -288,7 +288,7 @@
* Expected output state: uV=1200000; uA=200000; output enabled
*/
platname = regulator_names[BUCK1][PLATNAME];
- ut_assertok(regulator_autoset_by_name(platname, &dev_autoset));
+ ut_asserteq(-EALREADY, regulator_autoset_by_name(platname, &dev_autoset));
/* Check, that the returned device is proper */
ut_assertok(regulator_get_by_platname(platname, &dev));
@@ -304,7 +304,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_autoset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_autoset, UTF_SCAN_FDT);
/*
* Struct setting: to keep the expected output settings.
@@ -400,4 +400,4 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_autoset_list, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_autoset_list, UTF_SCAN_FDT);
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 444c4dc..921314b 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_remoteproc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_remoteproc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#define DEVICE_TO_PHYSICAL_OFFSET 0x1000
/**
@@ -256,4 +256,4 @@
return 0;
}
-DM_TEST(dm_test_remoteproc_elf, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_remoteproc_elf, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/reset.c b/test/dm/reset.c
index d3158bf..dceb6a1 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -66,8 +66,7 @@
return 0;
}
-
-DM_TEST(dm_test_reset_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_base, UTF_SCAN_FDT);
static int dm_test_reset(struct unit_test_state *uts)
{
@@ -94,7 +93,7 @@
return 0;
}
-DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset, UTF_SCAN_FDT);
static int dm_test_reset_devm(struct unit_test_state *uts)
{
@@ -119,7 +118,7 @@
return 0;
}
-DM_TEST(dm_test_reset_devm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_devm, UTF_SCAN_FDT);
static int dm_test_reset_bulk(struct unit_test_state *uts)
{
@@ -149,7 +148,7 @@
return 0;
}
-DM_TEST(dm_test_reset_bulk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_bulk, UTF_SCAN_FDT);
static int dm_test_reset_bulk_devm(struct unit_test_state *uts)
{
@@ -181,4 +180,4 @@
return 0;
}
-DM_TEST(dm_test_reset_bulk_devm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_bulk_devm, UTF_SCAN_FDT);
diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c
index 3dc9ca1..d1ca5d1 100644
--- a/test/dm/rkmtd.c
+++ b/test/dm/rkmtd.c
@@ -85,7 +85,7 @@
return 0;
}
-DM_TEST(dm_test_rkmtd, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rkmtd, UTF_SCAN_FDT);
/* Reusing the same label should work */
static int dm_test_rkmtd_dup(struct unit_test_state *uts)
@@ -112,7 +112,7 @@
return 0;
}
-DM_TEST(dm_test_rkmtd_dup, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rkmtd_dup, UTF_SCAN_FDT);
/* Basic test of the 'rkmtd' command */
static int dm_test_rkmtd_cmd(struct unit_test_state *uts)
@@ -196,4 +196,4 @@
return 0;
}
-DM_TEST(dm_test_rkmtd_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_rkmtd_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/rng.c b/test/dm/rng.c
index c8ed6ca..d7ef072 100644
--- a/test/dm/rng.c
+++ b/test/dm/rng.c
@@ -23,7 +23,7 @@
return 0;
}
-DM_TEST(dm_test_rng_read, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rng_read, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test the rng command */
static int dm_test_rng_cmd(struct unit_test_state *uts)
@@ -33,8 +33,6 @@
ut_assertok(uclass_get_device(UCLASS_RNG, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
run_command("rng", 0);
ut_assert_nextlinen("00000000:");
ut_assert_nextlinen("00000010:");
@@ -52,4 +50,4 @@
return 0;
}
-DM_TEST(dm_test_rng_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_rng_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index a8aa419..88f080b 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -27,7 +27,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static void show_time(const char *msg, struct rtc_time *time)
{
@@ -142,7 +142,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_set_get, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_set_get, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_rtc_read_write(struct unit_test_state *uts)
{
@@ -186,13 +186,11 @@
return 0;
}
-DM_TEST(dm_test_rtc_read_write, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_read_write, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'rtc list' command */
static int dm_test_rtc_cmd_list(struct unit_test_state *uts)
{
- console_record_reset();
-
run_command("rtc list", 0);
ut_assert_nextline("RTC #0 - rtc@43");
ut_assert_nextline("RTC #1 - rtc@61");
@@ -200,13 +198,11 @@
return 0;
}
-DM_TEST(dm_test_rtc_cmd_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'rtc read' and 'rtc write' commands */
static int dm_test_rtc_cmd_rw(struct unit_test_state *uts)
{
- console_record_reset();
-
run_command("rtc dev 0", 0);
ut_assert_nextline("RTC #0 - rtc@43");
ut_assert_console_end();
@@ -243,7 +239,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_cmd_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_cmd_rw, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Reset the time */
static int dm_test_rtc_reset(struct unit_test_state *uts)
@@ -280,7 +276,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_reset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_reset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that two RTC devices can be used independently */
static int dm_test_rtc_dual(struct unit_test_state *uts)
@@ -312,4 +308,4 @@
return 0;
}
-DM_TEST(dm_test_rtc_dual, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_dual, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index c9a0352..3655594 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -95,7 +95,7 @@
return ret;
}
-DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_sandbox_agent, UTF_SCAN_FDT);
static int dm_test_scmi_base(struct unit_test_state *uts)
{
@@ -202,8 +202,7 @@
return 0;
}
-
-DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_base, UTF_SCAN_FDT);
static int dm_test_scmi_cmd(struct unit_test_state *uts)
{
@@ -282,8 +281,7 @@
return 0;
}
-
-DM_TEST(dm_test_scmi_cmd, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_scmi_power_domains(struct unit_test_state *uts)
{
@@ -388,8 +386,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-
-DM_TEST(dm_test_scmi_power_domains, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_power_domains, UTF_SCAN_FDT);
static int dm_test_scmi_clocks(struct unit_test_state *uts)
{
@@ -458,7 +455,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_clocks, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_clocks, UTF_SCAN_FDT);
static int dm_test_scmi_resets(struct unit_test_state *uts)
{
@@ -496,7 +493,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_resets, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_resets, UTF_SCAN_FDT);
static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
{
@@ -551,4 +548,4 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_voltage_domains, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_voltage_domains, UTF_SCAN_FDT);
diff --git a/test/dm/scsi.c b/test/dm/scsi.c
index 5180159..fbc36a7 100644
--- a/test/dm/scsi.c
+++ b/test/dm/scsi.c
@@ -35,4 +35,4 @@
return 0;
}
-DM_TEST(dm_test_scsi_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scsi_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/serial.c b/test/dm/serial.c
index 34c0d4d..4acb14f 100644
--- a/test/dm/serial.c
+++ b/test/dm/serial.c
@@ -87,5 +87,4 @@
return 0;
}
-
-DM_TEST(dm_test_serial, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_serial, UTF_SCAN_FDT);
diff --git a/test/dm/sf.c b/test/dm/sf.c
index 0e3a0f1..3684d02 100644
--- a/test/dm/sf.c
+++ b/test/dm/sf.c
@@ -72,7 +72,7 @@
return 0;
}
-DM_TEST(dm_test_spi_flash, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_flash, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Functional test that sandbox SPI flash works correctly */
static int dm_test_spi_flash_func(struct unit_test_state *uts)
@@ -100,4 +100,4 @@
return 0;
}
-DM_TEST(dm_test_spi_flash_func, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_flash_func, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/simple-bus.c b/test/dm/simple-bus.c
index 8a730ba..d953483 100644
--- a/test/dm/simple-bus.c
+++ b/test/dm/simple-bus.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_simple_bus, UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+DM_TEST(dm_test_simple_bus, UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c
index 9949cb3..8ae5e77 100644
--- a/test/dm/simple-pm-bus.c
+++ b/test/dm/simple-pm-bus.c
@@ -41,4 +41,4 @@
return 0;
}
-DM_TEST(dm_test_simple_pm_bus, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_simple_pm_bus, UTF_SCAN_FDT);
diff --git a/test/dm/sm.c b/test/dm/sm.c
index 4d95c2a..cf4dab6 100644
--- a/test/dm/sm.c
+++ b/test/dm/sm.c
@@ -60,5 +60,4 @@
return 0;
}
-
-DM_TEST(dm_test_sm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sm, UTF_SCAN_FDT);
diff --git a/test/dm/smem.c b/test/dm/smem.c
index adcbfe5..89e74cc 100644
--- a/test/dm/smem.c
+++ b/test/dm/smem.c
@@ -23,4 +23,4 @@
return 0;
}
-DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_smem_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/soc.c b/test/dm/soc.c
index cb0ac15..a6b82e5 100644
--- a/test/dm/soc.c
+++ b/test/dm/soc.c
@@ -115,5 +115,4 @@
return 0;
}
-
-DM_TEST(dm_test_soc, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_soc, UTF_SCAN_FDT);
diff --git a/test/dm/sound.c b/test/dm/sound.c
index f4e6215..7b55567 100644
--- a/test/dm/sound.c
+++ b/test/dm/sound.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_sound, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sound, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the 'start beep' operations */
static int dm_test_sound_beep(struct unit_test_state *uts)
@@ -64,4 +64,4 @@
return 0;
}
-DM_TEST(dm_test_sound_beep, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sound_beep, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/spi.c b/test/dm/spi.c
index 1ab2dd7..249a923 100644
--- a/test/dm/spi.c
+++ b/test/dm/spi.c
@@ -89,7 +89,7 @@
return 0;
}
-DM_TEST(dm_test_spi_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* dm_test_spi_switch_slaves - Helper function to check whether spi_claim_bus
* operates correctly with two spi slaves.
@@ -168,7 +168,7 @@
return 0;
}
-DM_TEST(dm_test_spi_claim_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_claim_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox SPI works correctly */
static int dm_test_spi_xfer(struct unit_test_state *uts)
@@ -199,4 +199,4 @@
return 0;
}
-DM_TEST(dm_test_spi_xfer, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_xfer, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/spmi.c b/test/dm/spmi.c
index ee444f3..d706fc9 100644
--- a/test/dm/spmi.c
+++ b/test/dm/spmi.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_spmi_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_probe, UTF_SCAN_FDT);
/* Test if it's possible to read bus directly and indirectly */
static int dm_test_spmi_access(struct unit_test_state *uts)
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_spmi_access, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_access, UTF_SCAN_FDT);
/* Test if it's possible to access GPIO that should be in pmic */
static int dm_test_spmi_access_peripheral(struct unit_test_state *uts)
@@ -108,4 +108,4 @@
return 0;
}
-DM_TEST(dm_test_spmi_access_peripheral, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_access_peripheral, UTF_SCAN_FDT);
diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c
index ba19504..5f51c1b 100644
--- a/test/dm/syscon-reset.c
+++ b/test/dm/syscon-reset.c
@@ -55,4 +55,4 @@
return 0;
}
-DM_TEST(dm_test_syscon_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_reset, UTF_SCAN_FDT);
diff --git a/test/dm/syscon.c b/test/dm/syscon.c
index 04d324e..9855859 100644
--- a/test/dm/syscon.c
+++ b/test/dm/syscon.c
@@ -28,7 +28,7 @@
return 0;
}
-DM_TEST(dm_test_syscon_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test system controller finding */
static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
@@ -45,7 +45,7 @@
return 0;
}
-DM_TEST(dm_test_syscon_by_driver_data, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_by_driver_data, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test system controller by phandle */
static int dm_test_syscon_by_phandle(struct unit_test_state *uts)
@@ -80,4 +80,4 @@
return 0;
}
-DM_TEST(dm_test_syscon_by_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_by_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c
index 24a99da..155da3b 100644
--- a/test/dm/sysinfo-gpio.c
+++ b/test/dm/sysinfo-gpio.c
@@ -65,4 +65,4 @@
return 0;
}
-DM_TEST(dm_test_sysinfo_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysinfo_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c
index 7444a58..6c0d2d7 100644
--- a/test/dm/sysinfo.c
+++ b/test/dm/sysinfo.c
@@ -59,5 +59,4 @@
return 0;
}
-
-DM_TEST(dm_test_sysinfo, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysinfo, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
index f3a859b..8431aaa 100644
--- a/test/dm/sysreset.c
+++ b/test/dm/sysreset.c
@@ -45,7 +45,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_sysreset_get_status(struct unit_test_state *uts)
{
@@ -64,7 +64,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_get_status, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_get_status, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can walk through the sysreset devices */
static int dm_test_sysreset_walk(struct unit_test_state *uts)
@@ -95,7 +95,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_walk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_walk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_sysreset_get_last(struct unit_test_state *uts)
{
@@ -114,4 +114,4 @@
return 0;
}
-DM_TEST(dm_test_sysreset_get_last, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_get_last, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/tag.c b/test/dm/tag.c
index bce8a35..1412171 100644
--- a/test/dm/tag.c
+++ b/test/dm/tag.c
@@ -29,7 +29,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_ptr, 0);
/*
@@ -49,7 +48,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_val, 0);
/*
@@ -63,7 +61,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_inval, 0);
/*
@@ -79,5 +76,4 @@
return 0;
}
-
DM_TEST(dm_test_tag_del_all, 0);
diff --git a/test/dm/tee.c b/test/dm/tee.c
index bb02a9b..b56c982 100644
--- a/test/dm/tee.c
+++ b/test/dm/tee.c
@@ -215,5 +215,4 @@
return rc;
}
-
-DM_TEST(dm_test_tee, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tee, UTF_SCAN_FDT);
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 31effff..af8cd61 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -296,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* More tests for sequence numbers */
static int dm_test_fdt_uclass_seq_manual(struct unit_test_state *uts)
@@ -321,7 +321,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq_manual, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq_manual, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_uclass_seq_more(struct unit_test_state *uts)
{
@@ -360,7 +360,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq_more, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq_more, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find a device by device tree offset */
static int dm_test_fdt_offset(struct unit_test_state *uts)
@@ -390,7 +390,7 @@
return 0;
}
DM_TEST(dm_test_fdt_offset,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
/**
* Test various error conditions with uclass_first_device(),
@@ -455,7 +455,7 @@
return 0;
}
DM_TEST(dm_test_first_next_device_probeall,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through devices in a uclass */
static int dm_test_uclass_foreach(struct unit_test_state *uts)
@@ -476,7 +476,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_foreach, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_foreach, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* check_devices() - Check return values and pointers
@@ -556,7 +556,7 @@
return 0;
}
-DM_TEST(dm_test_first_next_ok_device, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_next_ok_device, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static const struct udevice_id fdt_dummy_ids[] = {
{ .compatible = "denx,u-boot-fdt-dummy", },
@@ -611,7 +611,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_translation, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_translation, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_get_addr_ptr_flat(struct unit_test_state *uts)
{
@@ -632,7 +632,7 @@
return 0;
}
DM_TEST(dm_test_fdt_get_addr_ptr_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_flat(struct unit_test_state *uts)
{
@@ -652,7 +652,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_index_flat(struct unit_test_state *uts)
{
@@ -674,7 +674,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_index_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_name_flat(struct unit_test_state *uts)
{
@@ -696,7 +696,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_name_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_live(struct unit_test_state *uts)
{
@@ -716,7 +716,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_remap_addr_index_live(struct unit_test_state *uts)
{
@@ -738,7 +738,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_index_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_remap_addr_name_live(struct unit_test_state *uts)
{
@@ -760,7 +760,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_name_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_disable_enable_by_path(struct unit_test_state *uts)
{
@@ -787,8 +787,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_disable_enable_by_path, UT_TESTF_SCAN_PDATA |
- UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_disable_enable_by_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test a few uclass phandle functions */
static int dm_test_fdt_phandle(struct unit_test_state *uts)
@@ -810,7 +809,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_find_first_child_by_uclass() */
static int dm_test_first_child(struct unit_test_state *uts)
@@ -837,7 +836,7 @@
return 0;
}
-DM_TEST(dm_test_first_child, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_child, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test integer functions in dm_read_...() */
static int dm_test_read_int(struct unit_test_state *uts)
@@ -901,7 +900,7 @@
return 0;
}
-DM_TEST(dm_test_read_int, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_int, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_read_int_index(struct unit_test_state *uts)
{
@@ -930,7 +929,7 @@
return 0;
}
-DM_TEST(dm_test_read_int_index, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_int_index, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_read_phandle(struct unit_test_state *uts)
{
@@ -995,7 +994,7 @@
return 0;
}
-DM_TEST(dm_test_read_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through devices by drvdata */
static int dm_test_uclass_drvdata(struct unit_test_state *uts)
@@ -1016,7 +1015,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_drvdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_first_child_ofdata_err(), etc. */
static int dm_test_child_ofdata(struct unit_test_state *uts)
@@ -1035,7 +1034,7 @@
return 0;
}
-DM_TEST(dm_test_child_ofdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_child_ofdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_first_child_err(), etc. */
static int dm_test_first_child_probe(struct unit_test_state *uts)
@@ -1054,7 +1053,7 @@
return 0;
}
-DM_TEST(dm_test_first_child_probe, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_child_probe, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that ofdata is read for parents before children */
static int dm_test_ofdata_order(struct unit_test_state *uts)
@@ -1079,7 +1078,7 @@
return 0;
}
-DM_TEST(dm_test_ofdata_order, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofdata_order, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test dev_decode_display_timing() */
static int dm_test_decode_display_timing(struct unit_test_state *uts)
@@ -1159,7 +1158,7 @@
ut_assert(dev_decode_display_timing(dev, 3, &timing));
return 0;
}
-DM_TEST(dm_test_decode_display_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_decode_display_timing, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test dev_decode_panel_timing() */
static int dm_test_decode_panel_timing(struct unit_test_state *uts)
@@ -1194,7 +1193,7 @@
return 0;
}
-DM_TEST(dm_test_decode_panel_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_decode_panel_timing, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test read_resourcee() */
static int dm_test_read_resource(struct unit_test_state *uts)
@@ -1225,5 +1224,4 @@
return 0;
}
-
-DM_TEST(dm_test_read_resource, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_resource, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/timer.c b/test/dm/timer.c
index 7fcefc4..a32059d 100644
--- a/test/dm/timer.c
+++ b/test/dm/timer.c
@@ -23,7 +23,7 @@
return 0;
}
-DM_TEST(dm_test_timer_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_timer_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test of timebase fallback
@@ -46,4 +46,4 @@
return 0;
}
DM_TEST(dm_test_timer_timebase_fallback,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/tpm.c b/test/dm/tpm.c
index 0e413c0..962a3fd 100644
--- a/test/dm/tpm.c
+++ b/test/dm/tpm.c
@@ -56,7 +56,7 @@
return 0;
}
-DM_TEST(dm_test_tpm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm, UTF_SCAN_FDT);
/* Test report_state */
static int dm_test_tpm_report_state(struct unit_test_state *uts)
@@ -77,7 +77,7 @@
return 0;
}
-DM_TEST(dm_test_tpm_report_state, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_report_state, UTF_SCAN_FDT);
/**
* test_tpm_autostart() - check the tpm_auto_start() call
@@ -114,7 +114,7 @@
return 0;
}
-DM_TEST(dm_test_tpm_autostart, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_autostart, UTF_SCAN_FDT);
static int dm_test_tpm_autostart_reinit(struct unit_test_state *uts)
{
@@ -123,4 +123,4 @@
return 0;
}
-DM_TEST(dm_test_tpm_autostart_reinit, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_autostart_reinit, UTF_SCAN_FDT);
diff --git a/test/dm/usb.c b/test/dm/usb.c
index 0bbea21..fa894c1 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -33,7 +33,7 @@
return 0;
}
-DM_TEST(dm_test_usb_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that we can use the flash stick. This is more of a functional test. It
@@ -82,7 +82,7 @@
return 0;
}
-DM_TEST(dm_test_usb_flash, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_flash, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test that we can handle multiple storage devices */
static int dm_test_usb_multi(struct unit_test_state *uts)
@@ -98,7 +98,7 @@
return 0;
}
-DM_TEST(dm_test_usb_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_multi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test that we have an associated ofnode with the usb device */
static int dm_test_usb_fdt_node(struct unit_test_state *uts)
@@ -120,7 +120,7 @@
return 0;
}
-DM_TEST(dm_test_usb_fdt_node, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_fdt_node, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int count_usb_devices(void)
{
@@ -164,7 +164,7 @@
return 0;
}
-DM_TEST(dm_test_usb_stop, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_stop, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* dm_test_usb_keyb() - test USB keyboard driver
@@ -455,4 +455,4 @@
return 0;
}
-DM_TEST(dm_test_usb_keyb, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_keyb, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/video.c b/test/dm/video.c
index 7dfbeb9..e347c14 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -42,7 +42,7 @@
return 0;
}
-DM_TEST(dm_test_video_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* compress_frame_buffer() - Compress the frame buffer and return its size
@@ -175,7 +175,7 @@
return 0;
}
-DM_TEST(dm_test_video_text, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_text, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_video_text_12x22(struct unit_test_state *uts)
{
@@ -211,7 +211,7 @@
return 0;
}
-DM_TEST(dm_test_video_text_12x22, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_text_12x22, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test handling of special characters in the console */
static int dm_test_video_chars(struct unit_test_state *uts)
@@ -228,7 +228,7 @@
return 0;
}
-DM_TEST(dm_test_video_chars, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_chars, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#ifdef CONFIG_VIDEO_ANSI
#define ANSI_ESC "\x1b"
@@ -262,7 +262,7 @@
return 0;
}
-DM_TEST(dm_test_video_ansi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_ansi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
/**
@@ -320,7 +320,7 @@
return 0;
}
-DM_TEST(dm_test_video_context, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_context, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation1(struct unit_test_state *uts)
@@ -329,7 +329,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation1, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation1, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation2(struct unit_test_state *uts)
@@ -338,7 +338,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation2, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation2, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation3(struct unit_test_state *uts)
@@ -347,7 +347,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation3, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation3, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read a file into memory and return a pointer to it */
static int read_file(struct unit_test_state *uts, const char *fname,
@@ -385,7 +385,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 8bpp display */
static int dm_test_video_bmp8(struct unit_test_state *uts)
@@ -404,7 +404,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp8, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp8, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 16bpp display */
static int dm_test_video_bmp16(struct unit_test_state *uts)
@@ -427,7 +427,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp16, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp16, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a 24bpp bitmap file on a 16bpp display */
static int dm_test_video_bmp24(struct unit_test_state *uts)
@@ -450,7 +450,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp24, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp24, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a 24bpp bitmap file on a 32bpp display */
static int dm_test_video_bmp24_32(struct unit_test_state *uts)
@@ -473,7 +473,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp24_32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp24_32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 32bpp display */
static int dm_test_video_bmp32(struct unit_test_state *uts)
@@ -491,7 +491,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a compressed bitmap file */
static int dm_test_video_bmp_comp(struct unit_test_state *uts)
@@ -507,7 +507,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp_comp, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp_comp, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 32bpp display */
static int dm_test_video_comp_bmp32(struct unit_test_state *uts)
@@ -526,7 +526,7 @@
return 0;
}
-DM_TEST(dm_test_video_comp_bmp32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_comp_bmp32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 8bpp display */
static int dm_test_video_comp_bmp8(struct unit_test_state *uts)
@@ -545,7 +545,7 @@
return 0;
}
-DM_TEST(dm_test_video_comp_bmp8, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_comp_bmp8, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test TrueType console */
static int dm_test_video_truetype(struct unit_test_state *uts)
@@ -560,7 +560,7 @@
return 0;
}
-DM_TEST(dm_test_video_truetype, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test scrolling TrueType console */
static int dm_test_video_truetype_scroll(struct unit_test_state *uts)
@@ -581,7 +581,7 @@
return 0;
}
-DM_TEST(dm_test_video_truetype_scroll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype_scroll, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test TrueType backspace, within and across lines */
static int dm_test_video_truetype_bs(struct unit_test_state *uts)
@@ -602,4 +602,4 @@
return 0;
}
-DM_TEST(dm_test_video_truetype_bs, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype_bs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio.c b/test/dm/virtio.c
index 3efd7c7..2574c4d 100644
--- a/test/dm/virtio.c
+++ b/test/dm/virtio.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_missing_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_missing_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c
index 63dc534..53414e4 100644
--- a/test/dm/virtio_device.c
+++ b/test/dm/virtio_device.c
@@ -44,7 +44,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test all of the virtio uclass ops */
static int dm_test_virtio_all_ops(struct unit_test_state *uts)
@@ -93,7 +93,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_all_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_all_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test removal of virtio device driver */
static int dm_test_virtio_remove(struct unit_test_state *uts)
@@ -122,7 +122,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_remove, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test all of the virtio ring */
static int dm_test_virtio_ring(struct unit_test_state *uts)
@@ -194,4 +194,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_ring, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_ring, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c
index ab7d862..e404b08 100644
--- a/test/dm/virtio_rng.c
+++ b/test/dm/virtio_rng.c
@@ -48,4 +48,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_rng_check_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_rng_check_len, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 1df2da2..541bcba 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_wdt_gpio_toggle(struct unit_test_state *uts)
{
@@ -75,7 +75,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_gpio_toggle, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_gpio_toggle, UTF_SCAN_FDT);
static int dm_test_wdt_gpio_level(struct unit_test_state *uts)
{
@@ -107,7 +107,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_gpio_level, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_gpio_level, UTF_SCAN_FDT);
static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts)
{
@@ -159,4 +159,4 @@
return 0;
}
-DM_TEST(dm_test_wdt_watchdog_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_watchdog_reset, UTF_SCAN_FDT);
diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c
index 13e0998..4af0576 100644
--- a/test/env/cmd_ut_env.c
+++ b/test/env/cmd_ut_env.c
@@ -9,6 +9,33 @@
#include <test/suites.h>
#include <test/ut.h>
+static int env_test_env_cmd(struct unit_test_state *uts)
+{
+ ut_assertok(run_command("setenv non_default_var1 1", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("setenv non_default_var2 1", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env print non_default_var1", 0));
+ ut_assert_nextline("non_default_var1=1");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default non_default_var1 non_default_var2", 0));
+ ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!");
+ ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ return 0;
+}
+ENV_TEST(env_test_env_cmd, UTF_CONSOLE);
+
int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct unit_test *tests = UNIT_TEST_SUITE_START(env_test);
diff --git a/test/env/hashtable.c b/test/env/hashtable.c
index ccdf013..16e4935 100644
--- a/test/env/hashtable.c
+++ b/test/env/hashtable.c
@@ -101,7 +101,6 @@
hdestroy_r(&htab);
return 0;
}
-
ENV_TEST(env_test_htab_fill, 0);
/* Fill the hashtable up halfway an repeateadly delete/create elements
@@ -122,5 +121,4 @@
hdestroy_r(&htab);
return 0;
}
-
ENV_TEST(env_test_htab_deletes, 0);
diff --git a/test/hush/dollar.c b/test/hush/dollar.c
index 4caa07c..077dcd6 100644
--- a/test/hush/dollar.c
+++ b/test/hush/dollar.c
@@ -14,7 +14,6 @@
static int hush_test_simple_dollar(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("echo $dollar_foo", 0));
ut_assert_nextline_empty();
ut_assert_console_end();
@@ -53,29 +52,22 @@
ut_asserteq(1, run_command("dollar_foo='bar quux", 0));
/* Next line contains error message */
ut_assert_skipline();
-
- if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
- /*
- * For some strange reasons, the console is not empty after
- * running above command.
- * So, we reset it to not have side effects for other tests.
- */
- console_record_reset_enable();
- } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
- ut_assert_console_end();
- }
+ ut_assert_console_end();
ut_asserteq(1, run_command("dollar_foo=bar quux\"", 0));
- /* Two next lines contain error message */
- ut_assert_skipline();
+ /* Next line contains error message */
ut_assert_skipline();
-
- if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
- /* See above comments. */
- console_record_reset_enable();
- } else if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
- ut_assert_console_end();
+ /*
+ * Old parser prints the error message on two lines:
+ * Unknown command 'quux
+ * ' - try 'help'
+ * While the new only prints it on one:
+ * syntax error: unterminated \"
+ */
+ if (gd->flags & GD_FLG_HUSH_OLD_PARSER) {
+ ut_assert_skipline();
}
+ ut_assert_console_end();
ut_assertok(run_command("dollar_foo='bar \"quux'", 0));
@@ -121,12 +113,11 @@
return 0;
}
-HUSH_TEST(hush_test_simple_dollar, 0);
+HUSH_TEST(hush_test_simple_dollar, UTF_CONSOLE);
static int hush_test_env_dollar(struct unit_test_state *uts)
{
env_set("env_foo", "bar");
- console_record_reset_enable();
ut_assertok(run_command("echo $env_foo", 0));
ut_assert_nextline("bar");
@@ -154,12 +145,10 @@
return 0;
}
-HUSH_TEST(hush_test_env_dollar, 0);
+HUSH_TEST(hush_test_env_dollar, UTF_CONSOLE);
static int hush_test_command_dollar(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
ut_assertok(run_command("dollar_bar=\"echo bar\"", 0));
ut_assertok(run_command("$dollar_bar", 0));
@@ -222,4 +211,4 @@
return 0;
}
-HUSH_TEST(hush_test_command_dollar, 0);
+HUSH_TEST(hush_test_command_dollar, UTF_CONSOLE);
diff --git a/test/hush/loop.c b/test/hush/loop.c
index d734abf..a9b6a8e 100644
--- a/test/hush/loop.c
+++ b/test/hush/loop.c
@@ -14,8 +14,6 @@
static int hush_test_for(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
ut_assertok(run_command("for loop_i in foo bar quux quux; do echo $loop_i; done", 0));
ut_assert_nextline("foo");
ut_assert_nextline("bar");
@@ -32,12 +30,10 @@
return 0;
}
-HUSH_TEST(hush_test_for, 0);
+HUSH_TEST(hush_test_for, UTF_CONSOLE);
static int hush_test_while(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
/*
* Hush 2021 always returns 0 from while loop...
@@ -65,11 +61,10 @@
return 0;
}
-HUSH_TEST(hush_test_while, 0);
+HUSH_TEST(hush_test_while, UTF_CONSOLE);
static int hush_test_until(struct unit_test_state *uts)
{
- console_record_reset_enable();
env_set("loop_bar", "bar");
/*
@@ -87,4 +82,4 @@
env_set("loop_bar", NULL);
return 0;
}
-HUSH_TEST(hush_test_until, 0);
+HUSH_TEST(hush_test_until, UTF_CONSOLE);
diff --git a/test/image/spl_load.c b/test/image/spl_load.c
index 7cbad40..3b62069 100644
--- a/test/image/spl_load.c
+++ b/test/image/spl_load.c
@@ -343,9 +343,7 @@
} else {
struct spl_load_info load;
- spl_set_bl_len(&load, 1);
- load.priv = img;
- load.read = spl_test_read;
+ spl_load_init(&load, spl_test_read, img, 1);
if (type == IMX8)
ut_assertok(spl_load_imx_container(&info_read, &load,
0));
diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c
index 7d5fb9b..d17cf11 100644
--- a/test/image/spl_load_os.c
+++ b/test/image/spl_load_os.c
@@ -10,64 +10,14 @@
#include <test/spl.h>
#include <test/ut.h>
-/* Context used for this test */
-struct text_ctx {
- int fd;
-};
-
-static ulong read_fit_image(struct spl_load_info *load, ulong offset,
- ulong size, void *buf)
-{
- struct text_ctx *text_ctx = load->priv;
- off_t ret;
- ssize_t res;
-
- ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
- if (ret != offset) {
- printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
- ret, errno);
- return 0;
- }
-
- res = os_read(text_ctx->fd, buf, size);
- if (res == -1) {
- printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
- size, res, errno);
- return 0;
- }
-
- return size;
-}
-
static int spl_test_load(struct unit_test_state *uts)
{
struct spl_image_info image;
- struct legacy_img_hdr *header;
- struct text_ctx text_ctx;
- struct spl_load_info load;
char fname[256];
- int ret;
- int fd;
- memset(&load, '\0', sizeof(load));
- spl_set_bl_len(&load, 512);
- load.read = read_fit_image;
-
- ret = sandbox_find_next_phase(fname, sizeof(fname), true);
- if (ret)
- ut_assertf(0, "%s not found, error %d\n", fname, ret);
-
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
-
- fd = os_open(fname, OS_O_RDONLY);
- ut_assert(fd >= 0);
- ut_asserteq(512, os_read(fd, header, 512));
- text_ctx.fd = fd;
-
- load.priv = &text_ctx;
-
- ut_assertok(spl_load_simple_fit(&image, &load, 0, header));
+ ut_assertok(sandbox_spl_load_fit(fname, sizeof(fname), &image));
return 0;
}
SPL_TEST(spl_test_load, 0);
+
diff --git a/test/lib/Makefile b/test/lib/Makefile
index e75a263..70f14c4 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -5,6 +5,7 @@
ifeq ($(CONFIG_SPL_BUILD),)
obj-y += cmd_ut_lib.o
obj-y += abuf.o
+obj-y += alist.o
obj-$(CONFIG_EFI_LOADER) += efi_device_path.o
obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
diff --git a/test/lib/alist.c b/test/lib/alist.c
new file mode 100644
index 0000000..d41845c
--- /dev/null
+++ b/test/lib/alist.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <alist.h>
+#include <string.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+struct my_struct {
+ uint val;
+ uint other_val;
+};
+
+enum {
+ obj_size = sizeof(struct my_struct),
+};
+
+/* Test alist_init() */
+static int lib_test_alist_init(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ /* with a size of 0, the fields should be inited, with no memory used */
+ memset(&lst, '\xff', sizeof(lst));
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ut_assertok(ut_check_delta(start));
+ alist_uninit(&lst);
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+
+ /* use an impossible size */
+ ut_asserteq(false, alist_init(&lst, obj_size,
+ CONFIG_SYS_MALLOC_LEN));
+ ut_assertnull(lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+
+ /* use a small size */
+ ut_assert(alist_init(&lst, obj_size, 4));
+ ut_assertnonnull(lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(4, lst.alloc);
+
+ /* free it */
+ alist_uninit(&lst);
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ut_assertok(ut_check_delta(start));
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_init, 0);
+
+/* Test alist_get() and alist_getd() */
+static int lib_test_alist_get(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+ void *ptr;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init(&lst, obj_size, 3));
+ ut_asserteq(0, lst.count);
+ ut_asserteq(3, lst.alloc);
+
+ ut_assertnull(alist_get_ptr(&lst, 2));
+ ut_assertnull(alist_get_ptr(&lst, 3));
+
+ ptr = alist_ensure_ptr(&lst, 1);
+ ut_assertnonnull(ptr);
+ ut_asserteq(2, lst.count);
+ ptr = alist_ensure_ptr(&lst, 2);
+ ut_asserteq(3, lst.count);
+ ut_assertnonnull(ptr);
+
+ ptr = alist_ensure_ptr(&lst, 3);
+ ut_assertnonnull(ptr);
+ ut_asserteq(4, lst.count);
+ ut_asserteq(6, lst.alloc);
+
+ ut_assertnull(alist_get_ptr(&lst, 4));
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_get, 0);
+
+/* Test alist_has() */
+static int lib_test_alist_has(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+ void *ptr;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init(&lst, obj_size, 3));
+
+ ut_assert(!alist_has(&lst, 0));
+ ut_assert(!alist_has(&lst, 1));
+ ut_assert(!alist_has(&lst, 2));
+ ut_assert(!alist_has(&lst, 3));
+
+ /* create a new one to force expansion */
+ ptr = alist_ensure_ptr(&lst, 4);
+ ut_assertnonnull(ptr);
+
+ ut_assert(alist_has(&lst, 0));
+ ut_assert(alist_has(&lst, 1));
+ ut_assert(alist_has(&lst, 2));
+ ut_assert(alist_has(&lst, 3));
+ ut_assert(alist_has(&lst, 4));
+ ut_assert(!alist_has(&lst, 5));
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_has, 0);
+
+/* Test alist_ensure() */
+static int lib_test_alist_ensure(struct unit_test_state *uts)
+{
+ struct my_struct *ptr3, *ptr4;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq(obj_size, lst.obj_size);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ptr3 = alist_ensure_ptr(&lst, 3);
+ ut_asserteq(4, lst.count);
+ ut_asserteq(4, lst.alloc);
+ ut_assertnonnull(ptr3);
+ ptr3->val = 3;
+
+ ptr4 = alist_ensure_ptr(&lst, 4);
+ ut_asserteq(8, lst.alloc);
+ ut_asserteq(5, lst.count);
+ ut_assertnonnull(ptr4);
+ ptr4->val = 4;
+ ut_asserteq(4, alist_get(&lst, 4, struct my_struct)->val);
+
+ ut_asserteq_ptr(ptr4, alist_ensure(&lst, 4, struct my_struct));
+
+ alist_ensure(&lst, 4, struct my_struct)->val = 44;
+ ut_asserteq(44, alist_get(&lst, 4, struct my_struct)->val);
+ ut_asserteq(3, alist_get(&lst, 3, struct my_struct)->val);
+ ut_assertnull(alist_get(&lst, 7, struct my_struct));
+ ut_asserteq(8, lst.alloc);
+ ut_asserteq(5, lst.count);
+
+ /* add some more, checking handling of malloc() failure */
+ malloc_enable_testing(0);
+ ut_assertnonnull(alist_ensure(&lst, 7, struct my_struct));
+ ut_assertnull(alist_ensure(&lst, 8, struct my_struct));
+ malloc_disable_testing();
+
+ lst.flags &= ~ALISTF_FAIL;
+ ut_assertnonnull(alist_ensure(&lst, 8, struct my_struct));
+ ut_asserteq(16, lst.alloc);
+ ut_asserteq(9, lst.count);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_ensure, 0);
+
+/* Test alist_add() bits not tested by lib_test_alist_ensure() */
+static int lib_test_alist_add(struct unit_test_state *uts)
+{
+ struct my_struct data, *ptr, *ptr2;
+ const struct my_struct *chk;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+
+ data.val = 123;
+ data.other_val = 456;
+ ptr = alist_add(&lst, data);
+ ut_assertnonnull(ptr);
+ ut_asserteq(4, lst.alloc);
+ ut_asserteq(1, lst.count);
+
+ ut_asserteq(123, ptr->val);
+ ut_asserteq(456, ptr->other_val);
+
+ ptr2 = alist_add_placeholder(&lst);
+ ut_assertnonnull(ptr2);
+
+ ptr2->val = 321;
+ ptr2->other_val = 654;
+
+ chk = alist_get(&lst, 1, struct my_struct);
+ ut_asserteq(321, chk->val);
+ ut_asserteq(654, chk->other_val);
+
+ ptr2 = alist_getw(&lst, 1, struct my_struct);
+ ut_asserteq(321, ptr2->val);
+ ut_asserteq(654, ptr2->other_val);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_add, 0);
diff --git a/test/lib/asn1.c b/test/lib/asn1.c
index 4842b70..f0c7819 100644
--- a/test/lib/asn1.c
+++ b/test/lib/asn1.c
@@ -135,7 +135,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_x509, 0);
#endif /* CONFIG_X509_CERTIFICATE_PARSER */
@@ -324,7 +323,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_pkcs7, 0);
#endif /* CONFIG_PKCS7_MESSAGE_PARSER */
@@ -386,6 +384,5 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_pkey, 0);
#endif /* CONFIG_RSA_PUBLIC_KEY_PARSER */
diff --git a/test/lib/efi_device_path.c b/test/lib/efi_device_path.c
index 290c876..5cc001e 100644
--- a/test/lib/efi_device_path.c
+++ b/test/lib/efi_device_path.c
@@ -45,5 +45,4 @@
return 0;
}
-
LIB_TEST(lib_test_efi_dp_check_length, 0);
diff --git a/test/lib/efi_image_region.c b/test/lib/efi_image_region.c
index 3ca49dc..2102539 100644
--- a/test/lib/efi_image_region.c
+++ b/test/lib/efi_image_region.c
@@ -65,7 +65,6 @@
return 0;
}
-
LIB_TEST(lib_test_efi_image_region_add, 0);
static int lib_test_efi_image_region_sort(struct unit_test_state *uts)
@@ -158,5 +157,4 @@
return 0;
}
-
LIB_TEST(lib_test_efi_image_region_sort, 0);
diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c
index d531a83..7b4592d 100644
--- a/test/lib/hexdump.c
+++ b/test/lib/hexdump.c
@@ -31,7 +31,6 @@
return 0;
}
-
LIB_TEST(lib_test_hex_to_bin, 0);
static int lib_test_hex2bin(struct unit_test_state *uts)
@@ -61,7 +60,6 @@
return 0;
}
-
LIB_TEST(lib_test_hex2bin, 0);
static int lib_test_bin2hex(struct unit_test_state *uts)
@@ -91,5 +89,4 @@
return 0;
}
-
LIB_TEST(lib_test_bin2hex, 0);
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 4b5b6e5..b2c54fb 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -3,6 +3,7 @@
* (C) Copyright 2018 Simon Goldschmidt
*/
+#include <alist.h>
#include <dm.h>
#include <lmb.h>
#include <log.h>
@@ -12,50 +13,64 @@
#include <test/test.h>
#include <test/ut.h>
-static inline bool lmb_is_nomap(struct lmb_property *m)
+static inline bool lmb_is_nomap(struct lmb_region *m)
{
return m->flags & LMB_NOMAP;
}
-static int check_lmb(struct unit_test_state *uts, struct lmb *lmb,
- phys_addr_t ram_base, phys_size_t ram_size,
- unsigned long num_reserved,
+static int check_lmb(struct unit_test_state *uts, struct alist *mem_lst,
+ struct alist *used_lst, phys_addr_t ram_base,
+ phys_size_t ram_size, unsigned long num_reserved,
phys_addr_t base1, phys_size_t size1,
phys_addr_t base2, phys_size_t size2,
phys_addr_t base3, phys_size_t size3)
{
+ struct lmb_region *mem, *used;
+
+ mem = mem_lst->data;
+ used = used_lst->data;
+
if (ram_size) {
- ut_asserteq(lmb->memory.cnt, 1);
- ut_asserteq(lmb->memory.region[0].base, ram_base);
- ut_asserteq(lmb->memory.region[0].size, ram_size);
+ ut_asserteq(mem_lst->count, 1);
+ ut_asserteq(mem[0].base, ram_base);
+ ut_asserteq(mem[0].size, ram_size);
}
- ut_asserteq(lmb->reserved.cnt, num_reserved);
+ ut_asserteq(used_lst->count, num_reserved);
if (num_reserved > 0) {
- ut_asserteq(lmb->reserved.region[0].base, base1);
- ut_asserteq(lmb->reserved.region[0].size, size1);
+ ut_asserteq(used[0].base, base1);
+ ut_asserteq(used[0].size, size1);
}
if (num_reserved > 1) {
- ut_asserteq(lmb->reserved.region[1].base, base2);
- ut_asserteq(lmb->reserved.region[1].size, size2);
+ ut_asserteq(used[1].base, base2);
+ ut_asserteq(used[1].size, size2);
}
if (num_reserved > 2) {
- ut_asserteq(lmb->reserved.region[2].base, base3);
- ut_asserteq(lmb->reserved.region[2].size, size3);
+ ut_asserteq(used[2].base, base3);
+ ut_asserteq(used[2].size, size3);
}
return 0;
}
-#define ASSERT_LMB(lmb, ram_base, ram_size, num_reserved, base1, size1, \
+#define ASSERT_LMB(mem_lst, used_lst, ram_base, ram_size, num_reserved, base1, size1, \
base2, size2, base3, size3) \
- ut_assert(!check_lmb(uts, lmb, ram_base, ram_size, \
+ ut_assert(!check_lmb(uts, mem_lst, used_lst, ram_base, ram_size, \
num_reserved, base1, size1, base2, size2, base3, \
size3))
-/*
- * Test helper function that reserves 64 KiB somewhere in the simulated RAM and
- * then does some alloc + free tests.
- */
+static int setup_lmb_test(struct unit_test_state *uts, struct lmb *store,
+ struct alist **mem_lstp, struct alist **used_lstp)
+{
+ struct lmb *lmb;
+
+ ut_assertok(lmb_push(store));
+ lmb = lmb_get();
+ *mem_lstp = &lmb->free_mem;
+ *used_lstp = &lmb->used_mem;
+
+ return 0;
+}
+
static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram,
const phys_size_t ram_size, const phys_addr_t ram0,
const phys_size_t ram0_size,
@@ -64,9 +79,11 @@
const phys_addr_t ram_end = ram + ram_size;
const phys_addr_t alloc_64k_end = alloc_64k_addr + 0x10000;
- struct lmb lmb;
long ret;
+ struct alist *mem_lst, *used_lst;
+ struct lmb_region *mem, *used;
phys_addr_t a, a2, b, b2, c, d;
+ struct lmb store;
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
@@ -75,106 +92,110 @@
ut_assert(alloc_64k_addr >= ram + 8);
ut_assert(alloc_64k_end <= ram_end - 8);
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
+ mem = mem_lst->data;
+ used = used_lst->data;
if (ram0_size) {
- ret = lmb_add(&lmb, ram0, ram0_size);
+ ret = lmb_add(ram0, ram0_size);
ut_asserteq(ret, 0);
}
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
if (ram0_size) {
- ut_asserteq(lmb.memory.cnt, 2);
- ut_asserteq(lmb.memory.region[0].base, ram0);
- ut_asserteq(lmb.memory.region[0].size, ram0_size);
- ut_asserteq(lmb.memory.region[1].base, ram);
- ut_asserteq(lmb.memory.region[1].size, ram_size);
+ ut_asserteq(mem_lst->count, 2);
+ ut_asserteq(mem[0].base, ram0);
+ ut_asserteq(mem[0].size, ram0_size);
+ ut_asserteq(mem[1].base, ram);
+ ut_asserteq(mem[1].size, ram_size);
} else {
- ut_asserteq(lmb.memory.cnt, 1);
- ut_asserteq(lmb.memory.region[0].base, ram);
- ut_asserteq(lmb.memory.region[0].size, ram_size);
+ ut_asserteq(mem_lst->count, 1);
+ ut_asserteq(mem[0].base, ram);
+ ut_asserteq(mem[0].size, ram_size);
}
/* reserve 64KiB somewhere */
- ret = lmb_reserve(&lmb, alloc_64k_addr, 0x10000);
+ ret = lmb_reserve(alloc_64k_addr, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
/* allocate somewhere, should be at the end of RAM */
- a = lmb_alloc(&lmb, 4, 1);
+ a = lmb_alloc(4, 1);
ut_asserteq(a, ram_end - 4);
- ASSERT_LMB(&lmb, 0, 0, 2, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr, 0x10000,
ram_end - 4, 4, 0, 0);
/* alloc below end of reserved region -> below reserved region */
- b = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
+ b = lmb_alloc_base(4, 1, alloc_64k_end);
ut_asserteq(b, alloc_64k_addr - 4);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 4, 0x10000 + 4, ram_end - 4, 4, 0, 0);
/* 2nd time */
- c = lmb_alloc(&lmb, 4, 1);
+ c = lmb_alloc(4, 1);
ut_asserteq(c, ram_end - 8);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 4, 0x10000 + 4, ram_end - 8, 8, 0, 0);
- d = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
+ d = lmb_alloc_base(4, 1, alloc_64k_end);
ut_asserteq(d, alloc_64k_addr - 8);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0);
- ret = lmb_free(&lmb, a, 4);
+ ret = lmb_free(a, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
/* allocate again to ensure we get the same address */
- a2 = lmb_alloc(&lmb, 4, 1);
+ a2 = lmb_alloc(4, 1);
ut_asserteq(a, a2);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0);
- ret = lmb_free(&lmb, a2, 4);
+ ret = lmb_free(a2, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
- ret = lmb_free(&lmb, b, 4);
+ ret = lmb_free(b, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 3,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 3,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000,
ram_end - 8, 4);
/* allocate again to ensure we get the same address */
- b2 = lmb_alloc_base(&lmb, 4, 1, alloc_64k_end);
+ b2 = lmb_alloc_base(4, 1, alloc_64k_end);
ut_asserteq(b, b2);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0);
- ret = lmb_free(&lmb, b2, 4);
+ ret = lmb_free(b2, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 3,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 3,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000,
ram_end - 8, 4);
- ret = lmb_free(&lmb, c, 4);
+ ret = lmb_free(c, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 2,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 2,
alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, 0, 0);
- ret = lmb_free(&lmb, d, 4);
+ ret = lmb_free(d, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, 0, 0, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
if (ram0_size) {
- ut_asserteq(lmb.memory.cnt, 2);
- ut_asserteq(lmb.memory.region[0].base, ram0);
- ut_asserteq(lmb.memory.region[0].size, ram0_size);
- ut_asserteq(lmb.memory.region[1].base, ram);
- ut_asserteq(lmb.memory.region[1].size, ram_size);
+ ut_asserteq(mem_lst->count, 2);
+ ut_asserteq(mem[0].base, ram0);
+ ut_asserteq(mem[0].size, ram0_size);
+ ut_asserteq(mem[1].base, ram);
+ ut_asserteq(mem[1].size, ram_size);
} else {
- ut_asserteq(lmb.memory.cnt, 1);
- ut_asserteq(lmb.memory.region[0].base, ram);
- ut_asserteq(lmb.memory.region[0].size, ram_size);
+ ut_asserteq(mem_lst->count, 1);
+ ut_asserteq(mem[0].base, ram);
+ ut_asserteq(mem[0].size, ram_size);
}
+ lmb_pop(&store);
+
return 0;
}
@@ -229,48 +250,51 @@
const phys_size_t big_block_size = 0x10000000;
const phys_addr_t ram_end = ram + ram_size;
const phys_addr_t alloc_64k_addr = ram + 0x10000000;
- struct lmb lmb;
+ struct alist *mem_lst, *used_lst;
long ret;
phys_addr_t a, b;
+ struct lmb store;
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
/* reserve 64KiB in the middle of RAM */
- ret = lmb_reserve(&lmb, alloc_64k_addr, 0x10000);
+ ret = lmb_reserve(alloc_64k_addr, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
/* allocate a big block, should be below reserved */
- a = lmb_alloc(&lmb, big_block_size, 1);
+ a = lmb_alloc(big_block_size, 1);
ut_asserteq(a, ram);
- ASSERT_LMB(&lmb, ram, ram_size, 1, a,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a,
big_block_size + 0x10000, 0, 0, 0, 0);
/* allocate 2nd big block */
/* This should fail, printing an error */
- b = lmb_alloc(&lmb, big_block_size, 1);
+ b = lmb_alloc(big_block_size, 1);
ut_asserteq(b, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, a,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a,
big_block_size + 0x10000, 0, 0, 0, 0);
- ret = lmb_free(&lmb, a, big_block_size);
+ ret = lmb_free(a, big_block_size);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
/* allocate too big block */
/* This should fail, printing an error */
- a = lmb_alloc(&lmb, ram_size, 1);
+ a = lmb_alloc(ram_size, 1);
ut_asserteq(a, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, alloc_64k_addr, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000,
0, 0, 0, 0);
+ lmb_pop(&store);
+
return 0;
}
@@ -294,56 +318,62 @@
{
const phys_size_t ram_size = 0x20000000;
const phys_addr_t ram_end = ram + ram_size;
- struct lmb lmb;
long ret;
phys_addr_t a, b;
+ struct lmb store;
+ struct alist *mem_lst, *used_lst;
const phys_addr_t alloc_size_aligned = (alloc_size + align - 1) &
~(align - 1);
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
/* allocate a block */
- a = lmb_alloc(&lmb, alloc_size, align);
+ a = lmb_alloc(alloc_size, align);
ut_assert(a != 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned,
- alloc_size, 0, 0, 0, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1,
+ ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0);
+
/* allocate another block */
- b = lmb_alloc(&lmb, alloc_size, align);
+ b = lmb_alloc(alloc_size, align);
ut_assert(b != 0);
if (alloc_size == alloc_size_aligned) {
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size -
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + ram_size -
(alloc_size_aligned * 2), alloc_size * 2, 0, 0, 0,
0);
} else {
- ASSERT_LMB(&lmb, ram, ram_size, 2, ram + ram_size -
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram + ram_size -
(alloc_size_aligned * 2), alloc_size, ram + ram_size
- alloc_size_aligned, alloc_size, 0, 0);
}
/* and free them */
- ret = lmb_free(&lmb, b, alloc_size);
+ ret = lmb_free(b, alloc_size);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1,
+ ram + ram_size - alloc_size_aligned,
alloc_size, 0, 0, 0, 0);
- ret = lmb_free(&lmb, a, alloc_size);
+ ret = lmb_free(a, alloc_size);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
/* allocate a block with base*/
- b = lmb_alloc_base(&lmb, alloc_size, align, ram_end);
+ b = lmb_alloc_base(alloc_size, align, ram_end);
ut_assert(a == b);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram + ram_size - alloc_size_aligned,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1,
+ ram + ram_size - alloc_size_aligned,
alloc_size, 0, 0, 0, 0);
/* and free it */
- ret = lmb_free(&lmb, b, alloc_size);
+ ret = lmb_free(b, alloc_size);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+
+ lmb_pop(&store);
return 0;
}
@@ -360,7 +390,6 @@
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_noreserved(uts, 0xE0000000, 4, 1);
}
-
LIB_TEST(lib_test_lmb_noreserved, 0);
static int lib_test_lmb_unaligned_size(struct unit_test_state *uts)
@@ -385,36 +414,39 @@
{
const phys_addr_t ram = 0;
const phys_size_t ram_size = 0x20000000;
- struct lmb lmb;
+ struct lmb store;
+ struct alist *mem_lst, *used_lst;
long ret;
phys_addr_t a, b;
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
/* allocate nearly everything */
- a = lmb_alloc(&lmb, ram_size - 4, 1);
+ a = lmb_alloc(ram_size - 4, 1);
ut_asserteq(a, ram + 4);
- ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4,
0, 0, 0, 0);
/* allocate the rest */
/* This should fail as the allocated address would be 0 */
- b = lmb_alloc(&lmb, 4, 1);
+ b = lmb_alloc(4, 1);
ut_asserteq(b, 0);
/* check that this was an error by checking lmb */
- ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4,
0, 0, 0, 0);
/* check that this was an error by freeing b */
- ret = lmb_free(&lmb, b, 4);
+ ret = lmb_free(b, 4);
ut_asserteq(ret, -1);
- ASSERT_LMB(&lmb, ram, ram_size, 1, a, ram_size - 4,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4,
0, 0, 0, 0);
- ret = lmb_free(&lmb, a, ram_size - 4);
+ ret = lmb_free(a, ram_size - 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0);
+
+ lmb_pop(&store);
return 0;
}
@@ -425,45 +457,50 @@
{
const phys_addr_t ram = 0x40000000;
const phys_size_t ram_size = 0x20000000;
- struct lmb lmb;
+ struct lmb store;
+ struct alist *mem_lst, *used_lst;
long ret;
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
- ret = lmb_reserve(&lmb, 0x40010000, 0x10000);
+ ret = lmb_reserve(0x40010000, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
- /* allocate overlapping region should fail */
- ret = lmb_reserve(&lmb, 0x40011000, 0x10000);
- ut_asserteq(ret, -1);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+
+ /* allocate overlapping region should return the coalesced count */
+ ret = lmb_reserve(0x40011000, 0x10000);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000,
0, 0, 0, 0);
/* allocate 3nd region */
- ret = lmb_reserve(&lmb, 0x40030000, 0x10000);
+ ret = lmb_reserve(0x40030000, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40010000, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40010000, 0x11000,
0x40030000, 0x10000, 0, 0);
/* allocate 2nd region , This should coalesced all region into one */
- ret = lmb_reserve(&lmb, 0x40020000, 0x10000);
+ ret = lmb_reserve(0x40020000, 0x10000);
ut_assert(ret >= 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x30000,
0, 0, 0, 0);
/* allocate 2nd region, which should be added as first region */
- ret = lmb_reserve(&lmb, 0x40000000, 0x8000);
+ ret = lmb_reserve(0x40000000, 0x8000);
ut_assert(ret >= 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x8000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x8000,
0x40010000, 0x30000, 0, 0);
/* allocate 3rd region, coalesce with first and overlap with second */
- ret = lmb_reserve(&lmb, 0x40008000, 0x10000);
+ ret = lmb_reserve(0x40008000, 0x10000);
ut_assert(ret >= 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x40000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x40000,
0, 0, 0, 0);
+
+ lmb_pop(&store);
+
return 0;
}
LIB_TEST(lib_test_lmb_overlapping_reserve, 0);
@@ -474,112 +511,116 @@
*/
static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
{
+ struct lmb store;
+ struct alist *mem_lst, *used_lst;
const phys_size_t ram_size = 0x20000000;
const phys_addr_t ram_end = ram + ram_size;
const phys_size_t alloc_addr_a = ram + 0x8000000;
const phys_size_t alloc_addr_b = ram + 0x8000000 * 2;
const phys_size_t alloc_addr_c = ram + 0x8000000 * 3;
- struct lmb lmb;
long ret;
phys_addr_t a, b, c, d, e;
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
/* reserve 3 blocks */
- ret = lmb_reserve(&lmb, alloc_addr_a, 0x10000);
+ ret = lmb_reserve(alloc_addr_a, 0x10000);
ut_asserteq(ret, 0);
- ret = lmb_reserve(&lmb, alloc_addr_b, 0x10000);
+ ret = lmb_reserve(alloc_addr_b, 0x10000);
ut_asserteq(ret, 0);
- ret = lmb_reserve(&lmb, alloc_addr_c, 0x10000);
+ ret = lmb_reserve(alloc_addr_c, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 3, alloc_addr_a, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000,
alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
/* allocate blocks */
- a = lmb_alloc_addr(&lmb, ram, alloc_addr_a - ram);
+ a = lmb_alloc_addr(ram, alloc_addr_a - ram);
ut_asserteq(a, ram);
- ASSERT_LMB(&lmb, ram, ram_size, 3, ram, 0x8010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000,
alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
- b = lmb_alloc_addr(&lmb, alloc_addr_a + 0x10000,
+ b = lmb_alloc_addr(alloc_addr_a + 0x10000,
alloc_addr_b - alloc_addr_a - 0x10000);
ut_asserteq(b, alloc_addr_a + 0x10000);
- ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x10010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000,
alloc_addr_c, 0x10000, 0, 0);
- c = lmb_alloc_addr(&lmb, alloc_addr_b + 0x10000,
+ c = lmb_alloc_addr(alloc_addr_b + 0x10000,
alloc_addr_c - alloc_addr_b - 0x10000);
ut_asserteq(c, alloc_addr_b + 0x10000);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
- d = lmb_alloc_addr(&lmb, alloc_addr_c + 0x10000,
+ d = lmb_alloc_addr(alloc_addr_c + 0x10000,
ram_end - alloc_addr_c - 0x10000);
ut_asserteq(d, alloc_addr_c + 0x10000);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, ram_size,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
0, 0, 0, 0);
/* allocating anything else should fail */
- e = lmb_alloc(&lmb, 1, 1);
+ e = lmb_alloc(1, 1);
ut_asserteq(e, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, ram_size,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
0, 0, 0, 0);
- ret = lmb_free(&lmb, d, ram_end - alloc_addr_c - 0x10000);
+ ret = lmb_free(d, ram_end - alloc_addr_c - 0x10000);
ut_asserteq(ret, 0);
/* allocate at 3 points in free range */
- d = lmb_alloc_addr(&lmb, ram_end - 4, 4);
+ d = lmb_alloc_addr(ram_end - 4, 4);
ut_asserteq(d, ram_end - 4);
- ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
d, 4, 0, 0);
- ret = lmb_free(&lmb, d, 4);
+ ret = lmb_free(d, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
- d = lmb_alloc_addr(&lmb, ram_end - 128, 4);
+ d = lmb_alloc_addr(ram_end - 128, 4);
ut_asserteq(d, ram_end - 128);
- ASSERT_LMB(&lmb, ram, ram_size, 2, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
d, 4, 0, 0);
- ret = lmb_free(&lmb, d, 4);
+ ret = lmb_free(d, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
- d = lmb_alloc_addr(&lmb, alloc_addr_c + 0x10000, 4);
+ d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4);
ut_asserteq(d, alloc_addr_c + 0x10000);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010004,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004,
0, 0, 0, 0);
- ret = lmb_free(&lmb, d, 4);
+ ret = lmb_free(d, 4);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram, 0x18010000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
0, 0, 0, 0);
/* allocate at the bottom */
- ret = lmb_free(&lmb, a, alloc_addr_a - ram);
+ ret = lmb_free(a, alloc_addr_a - ram);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, ram + 0x8000000, 0x10010000,
- 0, 0, 0, 0);
- d = lmb_alloc_addr(&lmb, ram, 4);
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000,
+ 0x10010000, 0, 0, 0, 0);
+
+ d = lmb_alloc_addr(ram, 4);
ut_asserteq(d, ram);
- ASSERT_LMB(&lmb, ram, ram_size, 2, d, 4,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4,
ram + 0x8000000, 0x10010000, 0, 0);
/* check that allocating outside memory fails */
if (ram_end != 0) {
- ret = lmb_alloc_addr(&lmb, ram_end, 1);
+ ret = lmb_alloc_addr(ram_end, 1);
ut_asserteq(ret, 0);
}
if (ram != 0) {
- ret = lmb_alloc_addr(&lmb, ram - 1, 1);
+ ret = lmb_alloc_addr(ram - 1, 1);
ut_asserteq(ret, 0);
}
+ lmb_pop(&store);
+
return 0;
}
@@ -601,55 +642,57 @@
static int test_get_unreserved_size(struct unit_test_state *uts,
const phys_addr_t ram)
{
+ struct lmb store;
+ struct alist *mem_lst, *used_lst;
const phys_size_t ram_size = 0x20000000;
const phys_addr_t ram_end = ram + ram_size;
const phys_size_t alloc_addr_a = ram + 0x8000000;
const phys_size_t alloc_addr_b = ram + 0x8000000 * 2;
const phys_size_t alloc_addr_c = ram + 0x8000000 * 3;
- struct lmb lmb;
long ret;
phys_size_t s;
/* check for overflow */
ut_assert(ram_end == 0 || ram_end > ram);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
- lmb_init(&lmb);
-
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
/* reserve 3 blocks */
- ret = lmb_reserve(&lmb, alloc_addr_a, 0x10000);
+ ret = lmb_reserve(alloc_addr_a, 0x10000);
ut_asserteq(ret, 0);
- ret = lmb_reserve(&lmb, alloc_addr_b, 0x10000);
+ ret = lmb_reserve(alloc_addr_b, 0x10000);
ut_asserteq(ret, 0);
- ret = lmb_reserve(&lmb, alloc_addr_c, 0x10000);
+ ret = lmb_reserve(alloc_addr_c, 0x10000);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 3, alloc_addr_a, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, alloc_addr_a, 0x10000,
alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
/* check addresses in between blocks */
- s = lmb_get_free_size(&lmb, ram);
+ s = lmb_get_free_size(ram);
ut_asserteq(s, alloc_addr_a - ram);
- s = lmb_get_free_size(&lmb, ram + 0x10000);
+ s = lmb_get_free_size(ram + 0x10000);
ut_asserteq(s, alloc_addr_a - ram - 0x10000);
- s = lmb_get_free_size(&lmb, alloc_addr_a - 4);
+ s = lmb_get_free_size(alloc_addr_a - 4);
ut_asserteq(s, 4);
- s = lmb_get_free_size(&lmb, alloc_addr_a + 0x10000);
+ s = lmb_get_free_size(alloc_addr_a + 0x10000);
ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x10000);
- s = lmb_get_free_size(&lmb, alloc_addr_a + 0x20000);
+ s = lmb_get_free_size(alloc_addr_a + 0x20000);
ut_asserteq(s, alloc_addr_b - alloc_addr_a - 0x20000);
- s = lmb_get_free_size(&lmb, alloc_addr_b - 4);
+ s = lmb_get_free_size(alloc_addr_b - 4);
ut_asserteq(s, 4);
- s = lmb_get_free_size(&lmb, alloc_addr_c + 0x10000);
+ s = lmb_get_free_size(alloc_addr_c + 0x10000);
ut_asserteq(s, ram_end - alloc_addr_c - 0x10000);
- s = lmb_get_free_size(&lmb, alloc_addr_c + 0x20000);
+ s = lmb_get_free_size(alloc_addr_c + 0x20000);
ut_asserteq(s, ram_end - alloc_addr_c - 0x20000);
- s = lmb_get_free_size(&lmb, ram_end - 4);
+ s = lmb_get_free_size(ram_end - 4);
ut_asserteq(s, 4);
+ lmb_pop(&store);
+
return 0;
}
@@ -667,158 +710,94 @@
}
LIB_TEST(lib_test_lmb_get_free_size, 0);
-#ifdef CONFIG_LMB_USE_MAX_REGIONS
-static int lib_test_lmb_max_regions(struct unit_test_state *uts)
-{
- const phys_addr_t ram = 0x00000000;
- /*
- * All of 32bit memory space will contain regions for this test, so
- * we need to scale ram_size (which in this case is the size of the lmb
- * region) to match.
- */
- const phys_size_t ram_size = ((0xFFFFFFFF >> CONFIG_LMB_MAX_REGIONS)
- + 1) * CONFIG_LMB_MAX_REGIONS;
- const phys_size_t blk_size = 0x10000;
- phys_addr_t offset;
- struct lmb lmb;
- int ret, i;
-
- lmb_init(&lmb);
-
- ut_asserteq(lmb.memory.cnt, 0);
- ut_asserteq(lmb.memory.max, CONFIG_LMB_MAX_REGIONS);
- ut_asserteq(lmb.reserved.cnt, 0);
- ut_asserteq(lmb.reserved.max, CONFIG_LMB_MAX_REGIONS);
-
- /* Add CONFIG_LMB_MAX_REGIONS memory regions */
- for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) {
- offset = ram + 2 * i * ram_size;
- ret = lmb_add(&lmb, offset, ram_size);
- ut_asserteq(ret, 0);
- }
- ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS);
- ut_asserteq(lmb.reserved.cnt, 0);
-
- /* error for the (CONFIG_LMB_MAX_REGIONS + 1) memory regions */
- offset = ram + 2 * (CONFIG_LMB_MAX_REGIONS + 1) * ram_size;
- ret = lmb_add(&lmb, offset, ram_size);
- ut_asserteq(ret, -1);
-
- ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS);
- ut_asserteq(lmb.reserved.cnt, 0);
-
- /* reserve CONFIG_LMB_MAX_REGIONS regions */
- for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++) {
- offset = ram + 2 * i * blk_size;
- ret = lmb_reserve(&lmb, offset, blk_size);
- ut_asserteq(ret, 0);
- }
-
- ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS);
- ut_asserteq(lmb.reserved.cnt, CONFIG_LMB_MAX_REGIONS);
-
- /* error for the 9th reserved blocks */
- offset = ram + 2 * (CONFIG_LMB_MAX_REGIONS + 1) * blk_size;
- ret = lmb_reserve(&lmb, offset, blk_size);
- ut_asserteq(ret, -1);
-
- ut_asserteq(lmb.memory.cnt, CONFIG_LMB_MAX_REGIONS);
- ut_asserteq(lmb.reserved.cnt, CONFIG_LMB_MAX_REGIONS);
-
- /* check each regions */
- for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++)
- ut_asserteq(lmb.memory.region[i].base, ram + 2 * i * ram_size);
-
- for (i = 0; i < CONFIG_LMB_MAX_REGIONS; i++)
- ut_asserteq(lmb.reserved.region[i].base, ram + 2 * i * blk_size);
-
- return 0;
-}
-LIB_TEST(lib_test_lmb_max_regions, 0);
-#endif
-
static int lib_test_lmb_flags(struct unit_test_state *uts)
{
+ struct lmb store;
+ struct lmb_region *mem, *used;
+ struct alist *mem_lst, *used_lst;
const phys_addr_t ram = 0x40000000;
const phys_size_t ram_size = 0x20000000;
- struct lmb lmb;
long ret;
- lmb_init(&lmb);
+ ut_assertok(setup_lmb_test(uts, &store, &mem_lst, &used_lst));
+ mem = mem_lst->data;
+ used = used_lst->data;
- ret = lmb_add(&lmb, ram, ram_size);
+ ret = lmb_add(ram, ram_size);
ut_asserteq(ret, 0);
/* reserve, same flag */
- ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
/* reserve again, same flag */
- ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
/* reserve again, new flag */
- ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NONE);
+ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NONE);
ut_asserteq(ret, -1);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
0, 0, 0, 0);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&used[0]), 1);
/* merge after */
- ret = lmb_reserve_flags(&lmb, 0x40020000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40020000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 1);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x20000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x20000,
0, 0, 0, 0);
/* merge before */
- ret = lmb_reserve_flags(&lmb, 0x40000000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40000000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 1);
- ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x30000,
0, 0, 0, 0);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&used[0]), 1);
- ret = lmb_reserve_flags(&lmb, 0x40030000, 0x10000, LMB_NONE);
+ ret = lmb_reserve_flags(0x40030000, 0x10000, LMB_NONE);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000,
0x40030000, 0x10000, 0, 0);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+ ut_asserteq(lmb_is_nomap(&used[0]), 1);
+ ut_asserteq(lmb_is_nomap(&used[1]), 0);
/* test that old API use LMB_NONE */
- ret = lmb_reserve(&lmb, 0x40040000, 0x10000);
+ ret = lmb_reserve(0x40040000, 0x10000);
ut_asserteq(ret, 1);
- ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x30000,
0x40030000, 0x20000, 0, 0);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+ ut_asserteq(lmb_is_nomap(&used[0]), 1);
+ ut_asserteq(lmb_is_nomap(&used[1]), 0);
- ret = lmb_reserve_flags(&lmb, 0x40070000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40070000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000,
0x40030000, 0x20000, 0x40070000, 0x10000);
- ret = lmb_reserve_flags(&lmb, 0x40050000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40050000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 0);
- ASSERT_LMB(&lmb, ram, ram_size, 4, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 4, 0x40000000, 0x30000,
0x40030000, 0x20000, 0x40050000, 0x10000);
/* merge with 2 adjacent regions */
- ret = lmb_reserve_flags(&lmb, 0x40060000, 0x10000, LMB_NOMAP);
+ ret = lmb_reserve_flags(0x40060000, 0x10000, LMB_NOMAP);
ut_asserteq(ret, 2);
- ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000,
+ ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, 0x40000000, 0x30000,
0x40030000, 0x20000, 0x40050000, 0x30000);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
- ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1);
+ ut_asserteq(lmb_is_nomap(&used[0]), 1);
+ ut_asserteq(lmb_is_nomap(&used[1]), 0);
+ ut_asserteq(lmb_is_nomap(&used[2]), 1);
+
+ lmb_pop(&store);
return 0;
}
diff --git a/test/lib/rsa.c b/test/lib/rsa.c
index 40f7001..129d03a 100644
--- a/test/lib/rsa.c
+++ b/test/lib/rsa.c
@@ -158,7 +158,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_rsa_verify_valid, 0);
/**
@@ -200,6 +199,5 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_rsa_verify_invalid, 0);
#endif /* RSA_VERIFY_WITH_PKEY */
diff --git a/test/lib/sscanf.c b/test/lib/sscanf.c
index 9fe5521..3a2ec8f 100644
--- a/test/lib/sscanf.c
+++ b/test/lib/sscanf.c
@@ -169,5 +169,4 @@
return 0;
}
-
LIB_TEST(lib_sscanf, 0);
diff --git a/test/lib/string.c b/test/lib/string.c
index d08dbca..8d22f3f 100644
--- a/test/lib/string.c
+++ b/test/lib/string.c
@@ -93,7 +93,6 @@
}
return 0;
}
-
LIB_TEST(lib_memset, 0);
/**
@@ -157,7 +156,6 @@
}
return 0;
}
-
LIB_TEST(lib_memcpy, 0);
/**
@@ -192,7 +190,6 @@
}
return 0;
}
-
LIB_TEST(lib_memmove, 0);
/** lib_memdup() - unit test for memdup() */
diff --git a/test/lib/test_aes.c b/test/lib/test_aes.c
index cfd9d8c..6d9068c 100644
--- a/test/lib/test_aes.c
+++ b/test/lib/test_aes.c
@@ -163,5 +163,4 @@
return ret;
}
-
LIB_TEST(lib_test_aes, 0);
diff --git a/test/lib/test_crc8.c b/test/lib/test_crc8.c
index 0dac97b..52be2dc 100644
--- a/test/lib/test_crc8.c
+++ b/test/lib/test_crc8.c
@@ -25,5 +25,4 @@
return 0;
}
-
LIB_TEST(lib_crc8, 0);
diff --git a/test/lib/test_crypt.c b/test/lib/test_crypt.c
index dcdadd9..b6dd5f0 100644
--- a/test/lib/test_crypt.c
+++ b/test/lib/test_crypt.c
@@ -59,5 +59,4 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_crypt, 0);
diff --git a/test/lib/test_errno_str.c b/test/lib/test_errno_str.c
index 67f7644..967ecfd 100644
--- a/test/lib/test_errno_str.c
+++ b/test/lib/test_errno_str.c
@@ -41,5 +41,4 @@
return 0;
}
-
LIB_TEST(lib_errno_str, 0);
diff --git a/test/lib/test_print.c b/test/lib/test_print.c
index c7fc50a..cd7f3f8 100644
--- a/test/lib/test_print.c
+++ b/test/lib/test_print.c
@@ -17,13 +17,10 @@
static int test_print_freq(struct unit_test_state *uts,
uint64_t freq, char *expected)
{
- ut_silence_console(uts);
- console_record_reset_enable();
print_freq(freq, ";\n");
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str(expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -41,19 +38,15 @@
ut_assertok(test_print_freq(uts, 54321987654321, "54321.99 GHz;"));
return 0;
}
-
-LIB_TEST(lib_test_print_freq, 0);
+LIB_TEST(lib_test_print_freq, UTF_CONSOLE);
static int test_print_size(struct unit_test_state *uts,
uint64_t freq, char *expected)
{
- ut_silence_console(uts);
- console_record_reset_enable();
print_size(freq, ";\n");
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str(expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -74,5 +67,4 @@
ut_assertok(test_print_size(uts, 54321987654321, "49.4 TiB;"));
return 0;
}
-
-LIB_TEST(lib_test_print_size, 0);
+LIB_TEST(lib_test_print_size, UTF_CONSOLE);
diff --git a/test/lib/uuid.c b/test/lib/uuid.c
index 0914f2c..d00e956 100644
--- a/test/lib/uuid.c
+++ b/test/lib/uuid.c
@@ -8,13 +8,18 @@
* Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
*/
-#include <uuid.h>
+#include <charset.h>
+#include <u-boot/uuid.h>
#include <test/lib.h>
#include <test/test.h>
#include <test/ut.h>
+#include <efi.h>
+
/* test UUID */
#define TEST_SVC_UUID "ed32d533-4209-99e6-2d72-cdd998a79cc0"
+/* U-Boot default fw image namespace */
+#define DEFAULT_FW_IMAGE_NAMESPACE "8c9f137e-91dc-427b-b2d6-b420faebaf2a"
#define UUID_SIZE 16
@@ -36,5 +41,121 @@
return 0;
}
-
LIB_TEST(lib_test_uuid_to_le, 0);
+
+#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID)
+/* Test UUID attribute bits (version, variant) */
+static int lib_test_uuid_bits(struct unit_test_state *uts)
+{
+ unsigned char uuid[16];
+ efi_guid_t guid;
+ int i;
+
+ /*
+ * Reduce the chance of a randomly generated UUID disguising
+ * a regression by testing multiple times.
+ */
+ for (i = 0; i < 5; i++) {
+ /* Test UUID v4 */
+ gen_rand_uuid((unsigned char *)&uuid);
+
+ printf("v4 UUID: %pUb\n", (efi_guid_t *)uuid);
+
+ /* version 4 */
+ ut_assert((uuid[6] & 0xf0) == 0x40);
+ /* variant 1 */
+ ut_assert((uuid[8] & UUID_VARIANT_MASK) == (UUID_VARIANT << UUID_VARIANT_SHIFT));
+
+ /* Test v5, use the v4 UUID as the namespace */
+ gen_v5_guid((struct uuid *)uuid,
+ &guid, "test", 4, NULL);
+
+ printf("v5 GUID: %pUl\n", (efi_guid_t *)uuid);
+
+ /* This is a GUID so bits 6 and 7 are swapped (little endian). Version 5 */
+ ut_assert((guid.b[7] & 0xf0) == 0x50);
+ /* variant 1 */
+ ut_assert((guid.b[8] & UUID_VARIANT_MASK) == (UUID_VARIANT << UUID_VARIANT_SHIFT));
+ }
+
+ return 0;
+}
+
+LIB_TEST(lib_test_uuid_bits, 0);
+#endif
+
+struct dynamic_uuid_test_data {
+ const char *compatible;
+ const u16 *images[4];
+ const char *expected_uuids[4];
+};
+
+static int lib_test_dynamic_uuid_case(struct unit_test_state *uts,
+ const struct dynamic_uuid_test_data *data)
+{
+ struct uuid namespace;
+ int j;
+
+ ut_assertok(uuid_str_to_bin(DEFAULT_FW_IMAGE_NAMESPACE, (unsigned char *)&namespace,
+ UUID_STR_FORMAT_GUID));
+
+ for (j = 0; data->images[j]; j++) {
+ const char *expected_uuid = data->expected_uuids[j];
+ const u16 *image = data->images[j];
+ efi_guid_t uuid;
+ char uuid_str[37];
+
+ gen_v5_guid(&namespace, &uuid,
+ data->compatible, strlen(data->compatible),
+ image, u16_strlen(image) * sizeof(uint16_t),
+ NULL);
+ uuid_bin_to_str((unsigned char *)&uuid, uuid_str, UUID_STR_FORMAT_GUID);
+
+ ut_asserteq_str(expected_uuid, uuid_str);
+ }
+
+ return 0;
+}
+
+static int lib_test_dynamic_uuid(struct unit_test_state *uts)
+{
+ int ret, i;
+ const struct dynamic_uuid_test_data test_data[] = {
+ {
+ .compatible = "sandbox",
+ .images = {
+ u"SANDBOX-UBOOT",
+ u"SANDBOX-UBOOT-ENV",
+ u"SANDBOX-FIT",
+ NULL,
+ },
+ .expected_uuids = {
+ "985f2937-7c2e-5e9a-8a5e-8e063312964b",
+ "9e339473-c2eb-530a-a69b-0cd6bbbed40e",
+ "46610520-469e-59dc-a8dd-c11832b877ea",
+ NULL,
+ }
+ },
+ {
+ .compatible = "qcom,qrb4210-rb2",
+ .images = {
+ u"QUALCOMM-UBOOT",
+ NULL,
+ },
+ .expected_uuids = {
+ "d5021fac-8dd0-5ed7-90c2-763c304aaf86",
+ NULL,
+ }
+ },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(test_data); i++) {
+ ret = lib_test_dynamic_uuid_case(uts, &test_data[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+LIB_TEST(lib_test_dynamic_uuid, 0);
diff --git a/test/log/cont_test.c b/test/log/cont_test.c
index 036d44b..32b1c79 100644
--- a/test/log/cont_test.c
+++ b/test/log/cont_test.c
@@ -25,7 +25,6 @@
/* Write two messages, the second continuing the first */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
gd->default_log_level = LOGL_INFO;
- console_record_reset_enable();
log(LOGC_ARCH, LOGL_ERR, "ea%d\n", 1);
log(LOGC_CONT, LOGL_CONT, "cc%d\n", 2);
gd->default_log_level = log_level;
@@ -33,7 +32,7 @@
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1"));
ut_assertok(ut_check_console_line(uts, "ERR.arch, cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Write a third message which is not a continuation */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
@@ -44,7 +43,7 @@
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "INFO.efi, ie3"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Write two messages without a newline between them */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
@@ -56,7 +55,7 @@
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1 cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/log/log_filter.c b/test/log/log_filter.c
index 9cc891d..d36e9d9 100644
--- a/test/log/log_filter.c
+++ b/test/log/log_filter.c
@@ -24,7 +24,7 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_filter_invalid, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_filter_invalid, UTF_CONSOLE);
/* Test adding and removing filters */
static int log_test_filter(struct unit_test_state *uts)
@@ -38,7 +38,6 @@
ulong filt1, filt2;
#define create_filter(args, filter_num) do {\
- ut_assertok(console_record_reset_enable()); \
ut_assertok(run_command("log filter-add -p " args, 0)); \
ut_assert_skipline(); \
ut_assertok(strict_strtoul(uts->actual_str, 10, &(filter_num))); \
@@ -72,7 +71,6 @@
ut_asserteq(true, filt2_found);
#define remove_filter(filter_num) do { \
- ut_assertok(console_record_reset_enable()); \
snprintf(cmd, sizeof(cmd), "log filter-remove %lu", filter_num); \
ut_assertok(run_command(cmd, 0)); \
ut_assert_console_end(); \
@@ -95,7 +93,6 @@
create_filter("", filt1);
create_filter("", filt2);
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("log filter-remove -a", 0));
ut_assert_console_end();
@@ -105,4 +102,4 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_filter, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_filter, UTF_CONSOLE);
diff --git a/test/log/log_test.c b/test/log/log_test.c
index 855353a..1c89df4 100644
--- a/test/log/log_test.c
+++ b/test/log/log_test.c
@@ -110,18 +110,16 @@
filt = log_add_filter("console", cat_list, LOGL_MAX, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_MMC);
check_log_entries_extra();
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_extra();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_allow, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_allow, UTF_CONSOLE);
/* Check a category filter that should block log entries */
int log_test_cat_deny_implicit(struct unit_test_state *uts)
@@ -134,14 +132,13 @@
filt = log_add_filter("console", cat_list, LOGL_MAX, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_none();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_deny_implicit, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_deny_implicit, UTF_CONSOLE);
/* Check passing and failing file filters */
int log_test_file(struct unit_test_state *uts)
@@ -151,18 +148,16 @@
filt = log_add_filter("console", NULL, LOGL_MAX, "file");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file");
check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_none();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file, UTF_CONSOLE);
/* Check a passing file filter (second in list) */
int log_test_file_second(struct unit_test_state *uts)
@@ -172,14 +167,13 @@
filt = log_add_filter("console", NULL, LOGL_MAX, "file,file2");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE);
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_second, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_second, UTF_CONSOLE);
/* Check a passing file filter (middle of list) */
int log_test_file_mid(struct unit_test_state *uts)
@@ -190,14 +184,13 @@
"file,file2,log/log_test.c");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_extra();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_mid, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_mid, UTF_CONSOLE);
/* Check a log level filter */
int log_test_level(struct unit_test_state *uts)
@@ -207,7 +200,6 @@
filt = log_add_filter("console", NULL, LOGL_WARNING, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
LOGL_FIRST, LOGL_WARNING);
@@ -215,7 +207,7 @@
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_level, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_level, UTF_CONSOLE);
/* Check two filters, one of which passes everything */
int log_test_double(struct unit_test_state *uts)
@@ -227,7 +219,6 @@
filt2 = log_add_filter("console", NULL, LOGL_MAX, NULL);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_extra();
@@ -235,7 +226,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_double, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_double, UTF_CONSOLE);
/* Check three filters, which together pass everything */
int log_test_triple(struct unit_test_state *uts)
@@ -249,7 +240,6 @@
filt3 = log_add_filter("console", NULL, LOGL_MAX, "log/log_test.c");
ut_assert(filt3 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_extra();
@@ -258,13 +248,12 @@
ut_assertok(log_remove_filter("console", filt3));
return 0;
}
-LOG_TEST_FLAGS(log_test_triple, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_triple, UTF_CONSOLE);
int do_log_test_helpers(struct unit_test_state *uts)
{
int i;
- ut_assertok(console_record_reset_enable());
log_err("level %d\n", LOGL_EMERG);
log_err("level %d\n", LOGL_ALERT);
log_err("level %d\n", LOGL_CRIT);
@@ -292,11 +281,10 @@
gd->log_fmt = log_get_default_format();
return ret;
}
-LOG_TEST_FLAGS(log_test_helpers, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_helpers, UTF_CONSOLE);
int do_log_test_disable(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
log_err("default\n");
ut_assert_nextline("%*s() default", CONFIG_LOGF_FUNC_PAD, __func__);
@@ -319,7 +307,7 @@
gd->log_fmt = log_get_default_format();
return ret;
}
-LOG_TEST_FLAGS(log_test_disable, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_disable, UTF_CONSOLE);
/* Check denying based on category */
int log_test_cat_deny(struct unit_test_state *uts)
@@ -335,7 +323,6 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_none();
@@ -343,7 +330,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_deny, UTF_CONSOLE);
/* Check denying based on file */
int log_test_file_deny(struct unit_test_state *uts)
@@ -356,7 +343,6 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file");
check_log_entries_none();
@@ -364,7 +350,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_deny, UTF_CONSOLE);
/* Check denying based on level */
int log_test_level_deny(struct unit_test_state *uts)
@@ -377,17 +363,16 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
- check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
- LOGL_WARNING + 1,
- min(gd->default_log_level, LOGL_INFO));
+ check_log_entries_flags_levels(
+ EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
+ LOGL_WARNING + 1, min((int)gd->default_log_level, LOGL_INFO));
ut_assertok(log_remove_filter("console", filt1));
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_level_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_level_deny, UTF_CONSOLE);
/* Check matching based on minimum level */
int log_test_min(struct unit_test_state *uts)
@@ -401,7 +386,6 @@
LOGFF_DENY | LOGFF_LEVEL_MIN);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
LOGL_WARNING, LOGL_INFO - 1);
@@ -410,7 +394,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_min, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_min, UTF_CONSOLE);
/* Check dropped traces */
int log_test_dropped(struct unit_test_state *uts)
@@ -419,8 +403,6 @@
gd->flags &= ~(GD_FLG_LOG_READY);
gd->log_drop_count = 0;
- ut_assertok(console_record_reset_enable());
-
log_run();
ut_asserteq(2 * (LOGL_COUNT - LOGL_FIRST) +
_LOG_MAX_LEVEL - LOGL_FIRST + 1,
@@ -432,7 +414,7 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_dropped, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_dropped, UTF_CONSOLE);
/* Check log_buffer() */
int log_test_buffer(struct unit_test_state *uts)
@@ -446,17 +428,18 @@
for (i = 0; i < 0x11; i++)
buf[i] = i * 0x11;
- ut_assertok(console_record_reset_enable());
log_buffer(LOGC_BOOT, LOGL_INFO, 0, buf, 1, 0x12, 0);
/* This one should product no output due to the debug level */
log_buffer(LOGC_BOOT, LOGL_DEBUG, 0, buf, 1, 0x12, 0);
- ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
- ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_nextline(
+ " log_test_buffer() 00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline(
+ " log_test_buffer() 00000010: 10 00 ..");
ut_assert_console_end();
free(buf);
return 0;
}
-LOG_TEST_FLAGS(log_test_buffer, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_buffer, UTF_CONSOLE);
diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c
index b714a16..4dc0f2d 100644
--- a/test/log/nolog_ndebug.c
+++ b/test/log/nolog_ndebug.c
@@ -21,7 +21,6 @@
int i;
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
/* Output a log record at every level */
for (i = LOGL_EMERG; i < LOGL_COUNT; i++)
@@ -31,7 +30,7 @@
/* Since DEBUG is not defined, we expect to not get debug output */
for (i = LOGL_EMERG; i < LOGL_DEBUG; i++)
ut_assertok(ut_check_console_line(uts, "testing level %d", i));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c
index c4c0fa6..341dbfc 100644
--- a/test/log/nolog_test.c
+++ b/test/log/nolog_test.c
@@ -25,11 +25,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_err("testing %s\n", "log_err");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_err"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_err);
@@ -39,11 +38,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_warning("testing %s\n", "log_warning");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_warning"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_warning);
@@ -53,11 +51,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_notice("testing %s\n", "log_notice");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_notice"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_notice);
@@ -67,11 +64,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_err("testing %s\n", "log_info");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_info"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_info);
@@ -83,10 +79,9 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
debug("testing %s\n", "debug");
gd->flags &= ~GD_FLG_RECORD;
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(nolog_test_nodebug);
@@ -96,11 +91,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_debug("testing %s\n", "log_debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assert(!strcmp(buf, ""));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_nodebug);
@@ -112,11 +106,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
debug("testing %s\n", "debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing debug"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(nolog_test_debug);
@@ -126,13 +119,12 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_debug("testing %s\n", "log_debug");
log(LOGC_NONE, LOGL_DEBUG, "more %s\n", "log_debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_debug"));
ut_assertok(ut_check_console_line(uts, "more log_debug"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_debug);
diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c
index 30f30d9..7734e92 100644
--- a/test/log/pr_cont_test.c
+++ b/test/log/pr_cont_test.c
@@ -28,14 +28,13 @@
/* Write two messages, the second continuing the first */
gd->log_fmt = BIT(LOGF_MSG);
gd->default_log_level = LOGL_INFO;
- console_record_reset_enable();
pr_err("ea%d ", 1);
pr_cont("cc%d\n", 2);
gd->default_log_level = log_level;
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ea1 cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig
index a4f1544..8818489 100644
--- a/test/overlay/Kconfig
+++ b/test/overlay/Kconfig
@@ -1,6 +1,6 @@
config UT_OVERLAY
bool "Enable Device Tree Overlays Unit Tests"
- depends on UNIT_TEST && OF_CONTROL
+ depends on UNIT_TEST && OF_CONTROL && SANDBOX
default y
select OF_LIBFDT_OVERLAY
help
diff --git a/test/print_ut.c b/test/print_ut.c
index 53d3354..f5e607b 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -180,14 +180,12 @@
buf[i] = i * 0x11;
/* bytes */
- console_record_reset();
print_buffer(0, buf, 1, 0x12, 0);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
ut_assert_nextline("00000010: 10 00 ..");
ut_assert_console_end();
/* line length */
- console_record_reset();
print_buffer(0, buf, 1, 0x12, 8);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw");
ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........");
@@ -195,7 +193,6 @@
ut_assert_console_end();
/* long line */
- console_record_reset();
buf[0x41] = 0x41;
print_buffer(0, buf, 1, 0x42, 0x40);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................");
@@ -203,35 +200,30 @@
ut_assert_console_end();
/* address */
- console_record_reset();
print_buffer(0x12345678, buf, 1, 0x12, 0);
ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
ut_assert_nextline("12345688: 10 00 ..");
ut_assert_console_end();
/* 16-bit */
- console_record_reset();
print_buffer(0, buf, 2, 9, 0);
ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........");
ut_assert_nextline("00000010: 0010 ..");
ut_assert_console_end();
/* 32-bit */
- console_record_reset();
print_buffer(0, buf, 4, 5, 0);
ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........");
ut_assert_nextline("00000010: 00000010 ....");
ut_assert_console_end();
/* 64-bit */
- console_record_reset();
print_buffer(0, buf, 8, 3, 0);
ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........");
ut_assert_nextline("00000010: 0000000000000010 ........");
ut_assert_console_end();
/* ASCII */
- console_record_reset();
buf[1] = 31;
buf[2] = 32;
buf[3] = 33;
@@ -246,7 +238,7 @@
return 0;
}
-PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_display_buffer, UTF_CONSOLE);
static int print_hexdump_line(struct unit_test_state *uts)
{
@@ -272,7 +264,7 @@
return 0;
}
-PRINT_TEST(print_hexdump_line, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_hexdump_line, UTF_CONSOLE);
static int print_do_hex_dump(struct unit_test_state *uts)
{
@@ -289,7 +281,6 @@
buf[i] = i * 0x11;
/* bytes */
- console_record_reset();
print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -298,7 +289,6 @@
ut_assert_console_end();
/* line length */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 ..\"3DUfw",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -310,7 +300,6 @@
unmap_sysmem(buf);
/* long line */
- console_record_reset();
buf[0x41] = 0x41;
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................",
@@ -320,7 +309,6 @@
ut_assert_console_end();
/* 16-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true);
ut_assert_nextline("%0*lx: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -330,7 +318,6 @@
unmap_sysmem(buf);
/* 32-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true);
ut_assert_nextline("%0*lx: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -340,7 +327,6 @@
unmap_sysmem(buf);
/* 64-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true);
ut_assert_nextline("%0*lx: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -350,7 +336,6 @@
unmap_sysmem(buf);
/* ASCII */
- console_record_reset();
buf[1] = 31;
buf[2] = 32;
buf[3] = 33;
@@ -365,7 +350,7 @@
return 0;
}
-PRINT_TEST(print_do_hex_dump, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_do_hex_dump, UTF_CONSOLE);
static int snprint(struct unit_test_state *uts)
{
diff --git a/test/py/tests/test_bootstage.py b/test/py/tests/test_bootstage.py
index a9eb9f0..bd71a1a 100644
--- a/test/py/tests/test_bootstage.py
+++ b/test/py/tests/test_bootstage.py
@@ -33,7 +33,7 @@
@pytest.mark.buildconfigspec('bootstage')
@pytest.mark.buildconfigspec('cmd_bootstage')
@pytest.mark.buildconfigspec('bootstage_stash')
-def test_bootstage_stash(u_boot_console):
+def test_bootstage_stash_and_unstash(u_boot_console):
f = u_boot_console.config.env.get('env__bootstage_cmd_file', None)
if not f:
pytest.skip('No bootstage environment file is defined')
@@ -55,13 +55,8 @@
# Check expected string in last column of output
output_last_col = ''.join([i.split()[-1] for i in output.split('\n')])
assert expected_text in output_last_col
- return addr, size
-@pytest.mark.buildconfigspec('bootstage')
-@pytest.mark.buildconfigspec('cmd_bootstage')
-@pytest.mark.buildconfigspec('bootstage_stash')
-def test_bootstage_unstash(u_boot_console):
- addr, size = test_bootstage_stash(u_boot_console)
+ # Check that unstash works as expected
u_boot_console.run_command('bootstage unstash %x %x' % (addr, size))
output = u_boot_console.run_command('echo $?')
assert output.endswith('0')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index 11bcdc2..a726c71 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -147,7 +147,7 @@
verify_content(u_boot_console, '150000', 'u-boot-env:Old')
else:
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
- assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+ assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
index f3a2dff..8a790405 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
@@ -145,10 +145,10 @@
'efidebug capsule esrt'])
# ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
- assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+ assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output)
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
- assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+ assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
check_file_removed(u_boot_console, disk_img, capsule_files)
@@ -199,12 +199,12 @@
verify_content(u_boot_console, '150000', 'u-boot-env:Old')
else:
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
- assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+ assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
# ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
- assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+ assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output)
assert 'ESRT: fw_version=10' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index 44a58ba..debbce8 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -157,7 +157,7 @@
'efidebug capsule esrt'])
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
- assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output)
+ assert '46610520-469E-59DC-A8DD-C11832B877EA' in ''.join(output)
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 83a10e1..439bd71 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -151,12 +151,12 @@
'efidebug capsule esrt'])
# ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
- assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output)
+ assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
assert 'ESRT: fw_version=5' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
# ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT.
- assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output)
+ assert '9E339473-C2EB-530A-A69B-0CD6BBBED40E' in ''.join(output)
assert 'ESRT: fw_version=10' in ''.join(output)
assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
diff --git a/test/py/tests/test_efi_capsule/version.dtso b/test/py/tests/test_efi_capsule/version.dtso
index 07850cc..3aebb5b 100644
--- a/test/py/tests/test_efi_capsule/version.dtso
+++ b/test/py/tests/test_efi_capsule/version.dtso
@@ -8,17 +8,17 @@
image1 {
lowest-supported-version = <3>;
image-index = <1>;
- image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8";
+ image-type-id = "985F2937-7C2E-5E9A-8A5E-8E063312964B";
};
image2 {
lowest-supported-version = <7>;
image-index = <2>;
- image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0";
+ image-type-id = "9E339473-C2EB-530A-A69B-0CD6BBBED40E";
};
image3 {
lowest-supported-version = <3>;
image-index = <1>;
- image-type-id = "3673B45D-6A7C-46F3-9E60-ADABB03F7937";
+ image-type-id = "46610520-469E-59DC-A8DD-C11832B877EA";
};
};
};
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 85473a9..5f3b448 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -45,11 +45,18 @@
'crc32': 'c2244b26', # CRC32 check sum
'addr': 0x40400000, # load address
}
+
+# False if the helloworld EFI over HTTP boot test should be performed.
+# If HTTP boot testing is not possible or desired, set this variable to True or
+# ommit it.
+env__efi_helloworld_net_http_test_skip = True
"""
import pytest
import u_boot_utils
+PROTO_TFTP, PROTO_HTTP = range(0, 2)
+
net_set_up = False
def test_efi_pre_commands(u_boot_console):
@@ -110,10 +117,10 @@
global net_set_up
net_set_up = True
-def fetch_tftp_file(u_boot_console, env_conf):
- """Grab an env described file via TFTP and return its address
+def fetch_file(u_boot_console, env_conf, proto):
+ """Grab an env described file via TFTP or HTTP and return its address
- A file as described by an env config <env_conf> is downloaded from the TFTP
+ A file as described by an env config <env_conf> is downloaded from the
server. The address to that file is returned.
"""
if not net_set_up:
@@ -128,7 +135,13 @@
addr = u_boot_utils.find_ram_base(u_boot_console)
fn = f['fn']
- output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+ if proto == PROTO_TFTP:
+ cmd = 'tftpboot'
+ elif proto == PROTO_HTTP:
+ cmd = 'wget'
+ else:
+ assert False
+ output = u_boot_console.run_command('%s %x %s' % (cmd, addr, fn))
expected_text = 'Bytes transferred = '
sz = f.get('size', None)
if sz:
@@ -147,22 +160,40 @@
return addr
+def do_test_efi_helloworld_net(u_boot_console, proto):
+ addr = fetch_file(u_boot_console, 'env__efi_loader_helloworld_file', proto)
+
+ output = u_boot_console.run_command('bootefi %x' % addr)
+ expected_text = 'Hello, world'
+ assert expected_text in output
+ expected_text = '## Application failed'
+ assert expected_text not in output
+
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile')
-def test_efi_helloworld_net(u_boot_console):
+@pytest.mark.buildconfigspec('cmd_tftpboot')
+def test_efi_helloworld_net_tftp(u_boot_console):
"""Run the helloworld.efi binary via TFTP.
The helloworld.efi file is downloaded from the TFTP server and is executed
using the fallback device tree at $fdtcontroladdr.
"""
- addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_helloworld_file')
+ do_test_efi_helloworld_net(u_boot_console, PROTO_TFTP);
- output = u_boot_console.run_command('bootefi %x' % addr)
- expected_text = 'Hello, world'
- assert expected_text in output
- expected_text = '## Application failed'
- assert expected_text not in output
+@pytest.mark.buildconfigspec('of_control')
+@pytest.mark.buildconfigspec('cmd_bootefi_hello_compile')
+@pytest.mark.buildconfigspec('cmd_wget')
+def test_efi_helloworld_net_http(u_boot_console):
+ """Run the helloworld.efi binary via HTTP.
+
+ The helloworld.efi file is downloaded from the HTTP server and is executed
+ using the fallback device tree at $fdtcontroladdr.
+ """
+ if u_boot_console.config.env.get('env__efi_helloworld_net_http_test_skip', True):
+ pytest.skip('helloworld.efi HTTP test is not enabled!')
+
+ do_test_efi_helloworld_net(u_boot_console, PROTO_HTTP);
@pytest.mark.buildconfigspec('cmd_bootefi_hello')
def test_efi_helloworld_builtin(u_boot_console):
@@ -178,6 +209,7 @@
@pytest.mark.buildconfigspec('of_control')
@pytest.mark.buildconfigspec('cmd_bootefi')
+@pytest.mark.buildconfigspec('cmd_tftpboot')
def test_efi_grub_net(u_boot_console):
"""Run the grub.efi binary via TFTP.
@@ -185,7 +217,7 @@
executed.
"""
- addr = fetch_tftp_file(u_boot_console, 'env__efi_loader_grub_file')
+ addr = fetch_file(u_boot_console, 'env__efi_loader_grub_file', PROTO_TFTP)
u_boot_console.run_command('bootefi %x' % addr, wait_for_prompt=False)
diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py
index 63309fe..d7d7435 100644
--- a/test/py/tests/test_net_boot.py
+++ b/test/py/tests/test_net_boot.py
@@ -75,7 +75,7 @@
'check_pattern': 'ERROR',
}
-# False or omitted if a PXE boot test should be tested.
+# False if a PXE boot test should be tested.
# If PXE boot testing is not possible or desired, set this variable to True.
# For example: If pxe configuration file is not proper to boot
env__pxe_boot_test_skip = False
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
new file mode 100644
index 0000000..3160d58
--- /dev/null
+++ b/test/py/tests/test_spi.py
@@ -0,0 +1,696 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2024, Advanced Micro Devices, Inc.
+
+"""
+Note: This test relies on boardenv_* containing configuration values to define
+spi minimum and maximum frequencies at which the flash part can operate on and
+these tests run at different spi frequency randomised values in the range
+multiple times based on the user defined iteration value.
+It also defines the SPI bus number containing the SPI-flash chip, SPI
+chip-select, SPI mode, SPI flash part name and timeout parameters. If minimum
+and maximum frequency is not defined, it will run on freq 0 by default.
+
+Without the boardenv_* configuration, this test will be automatically skipped.
+
+It also relies on configuration values for supported flashes for lock and
+unlock cases for SPI family flash. It will run lock-unlock cases only for the
+supported flash parts.
+
+For Example:
+
+# Details of SPI device test parameters required for SPI device testing:
+
+# bus - SPI bus number to init the flash device
+# chip_select - SPI chip select number to init the flash device
+# min_freq - Minimum frequency in hz at which the flash part can operate, set 0
+# or None for default frequency
+# max_freq - Maximum frequency in hz at which the flash part can operate, set 0
+# or None for default frequency
+# mode - SPI mode to init the flash device
+# part_name - SPI flash part name to be detected
+# timeout - Default timeout to run the sf commands
+# iteration - No of iteration to run SPI flash test
+
+env__spi_device_test = {
+ 'bus': 0,
+ 'chip_select': 0,
+ 'min_freq': 10000000,
+ 'max_freq': 100000000,
+ 'mode': 0,
+ 'part_name': 'n25q00a',
+ 'timeout': 100000,
+ 'iteration': 5,
+}
+
+# supported_flash - Flash parts name which support lock-unlock functionality
+env__spi_lock_unlock = {
+ 'supported_flash': 'mt25qu512a, n25q00a, n25q512ax3',
+}
+"""
+
+import random
+import re
+import pytest
+import u_boot_utils
+
+SPI_DATA = {}
+EXPECTED_ERASE = 'Erased: OK'
+EXPECTED_WRITE = 'Written: OK'
+EXPECTED_READ = 'Read: OK'
+EXPECTED_ERASE_ERRORS = [
+ 'Erase operation failed',
+ 'Attempted to modify a protected sector',
+ 'Erased: ERROR',
+ 'is protected and cannot be erased',
+ 'ERROR: flash area is locked',
+]
+EXPECTED_WRITE_ERRORS = [
+ 'ERROR: flash area is locked',
+ 'Program operation failed',
+ 'Attempted to modify a protected sector',
+ 'Written: ERROR',
+]
+
+def get_params_spi(u_boot_console):
+ ''' Get SPI device test parameters from boardenv file '''
+ f = u_boot_console.config.env.get('env__spi_device_test', None)
+ if not f:
+ pytest.skip('No env file to read for SPI family device test')
+
+ bus = f.get('bus', 0)
+ cs = f.get('chip_select', 0)
+ mode = f.get('mode', 0)
+ part_name = f.get('part_name', None)
+ timeout = f.get('timeout', None)
+
+ if not part_name:
+ pytest.skip('No env file to read SPI family flash part name')
+
+ return bus, cs, mode, part_name, timeout
+
+def spi_find_freq_range(u_boot_console):
+ '''Find out minimum and maximum frequnecies that SPI device can operate'''
+ f = u_boot_console.config.env.get('env__spi_device_test', None)
+ if not f:
+ pytest.skip('No env file to read for SPI family device test')
+
+ min_f = f.get('min_freq', None)
+ max_f = f.get('max_freq', None)
+ iterations = f.get('iteration', 1)
+
+ if not min_f:
+ min_f = 0
+ if not max_f:
+ max_f = 0
+
+ max_f = max(max_f, min_f)
+
+ return min_f, max_f, iterations
+
+def spi_pre_commands(u_boot_console, freq):
+ ''' Find out SPI family flash memory parameters '''
+ bus, cs, mode, part_name, timeout = get_params_spi(u_boot_console)
+
+ output = u_boot_console.run_command(f'sf probe {bus}:{cs} {freq} {mode}')
+ if not 'SF: Detected' in output:
+ pytest.fail('No SPI device available')
+
+ if not part_name in output:
+ pytest.fail('SPI flash part name not recognized')
+
+ m = re.search('page size (.+?) Bytes', output)
+ if m:
+ try:
+ page_size = int(m.group(1))
+ except ValueError:
+ pytest.fail('SPI page size not recognized')
+
+ m = re.search('erase size (.+?) KiB', output)
+ if m:
+ try:
+ erase_size = int(m.group(1))
+ except ValueError:
+ pytest.fail('SPI erase size not recognized')
+
+ erase_size *= 1024
+
+ m = re.search('total (.+?) MiB', output)
+ if m:
+ try:
+ total_size = int(m.group(1))
+ except ValueError:
+ pytest.fail('SPI total size not recognized')
+
+ total_size *= 1024 * 1024
+
+ m = re.search('Detected (.+?) with', output)
+ if m:
+ try:
+ flash_part = m.group(1)
+ assert flash_part == part_name
+ except ValueError:
+ pytest.fail('SPI flash part not recognized')
+
+ global SPI_DATA
+ SPI_DATA = {
+ 'page_size': page_size,
+ 'erase_size': erase_size,
+ 'total_size': total_size,
+ 'flash_part': flash_part,
+ 'timeout': timeout,
+ }
+
+def get_page_size():
+ ''' Get the SPI page size from spi data '''
+ return SPI_DATA['page_size']
+
+def get_erase_size():
+ ''' Get the SPI erase size from spi data '''
+ return SPI_DATA['erase_size']
+
+def get_total_size():
+ ''' Get the SPI total size from spi data '''
+ return SPI_DATA['total_size']
+
+def get_flash_part():
+ ''' Get the SPI flash part name from spi data '''
+ return SPI_DATA['flash_part']
+
+def get_timeout():
+ ''' Get the SPI timeout from spi data '''
+ return SPI_DATA['timeout']
+
+def spi_erase_block(u_boot_console, erase_size, total_size):
+ ''' Erase SPI flash memory block wise '''
+ for start in range(0, total_size, erase_size):
+ output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(erase_size)}')
+ assert EXPECTED_ERASE in output
+
+@pytest.mark.buildconfigspec('cmd_sf')
+def test_spi_erase_block(u_boot_console):
+ ''' Test case to check SPI erase functionality by erasing memory regions
+ block-wise '''
+
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_erase_block(u_boot_console, get_erase_size(), get_total_size())
+ i = i + 1
+
+def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
+ ''' Random write till page size, random till size and full size '''
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
+ old_size = 0
+ for size in (
+ random.randint(4, page_size),
+ random.randint(page_size, total_size),
+ total_size,
+ ):
+ offset = random.randint(4, page_size)
+ offset = offset & ~3
+ size = size & ~3
+ size = size - old_size
+ output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+ m = re.search('==> (.+?)$', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+
+ expected_crc32 = m.group(1)
+ if old_size % page_size:
+ old_size = int(old_size / page_size)
+ old_size *= page_size
+
+ if size % erase_size:
+ erasesize = int(size / erase_size + 1)
+ erasesize *= erase_size
+
+ eraseoffset = int(old_size / erase_size)
+ eraseoffset *= erase_size
+
+ timeout = 100000000
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf erase {hex(eraseoffset)} {hex(erasesize)}'
+ )
+ assert EXPECTED_ERASE in output
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf write {hex(addr + total_size)} {hex(old_size)} {hex(size)}'
+ )
+ assert EXPECTED_WRITE in output
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf read {hex(addr + total_size + offset)} {hex(old_size)} {hex(size)}'
+ )
+ assert EXPECTED_READ in output
+ output = u_boot_console.run_command(
+ f'crc32 {hex(addr + total_size + offset)} {hex(size)}'
+ )
+ assert expected_crc32 in output
+ old_size = size
+
+@pytest.mark.buildconfigspec('cmd_bdi')
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_spi_write_twice(u_boot_console):
+ ''' Test to write data with random size twice for SPI '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_write_twice(
+ u_boot_console,
+ get_page_size(),
+ get_erase_size(),
+ get_total_size(),
+ get_timeout()
+ )
+ i = i + 1
+
+def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeout):
+ ''' Write with random size of data to continue SPI write case '''
+ spi_erase_block(u_boot_console, erase_size, total_size)
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
+ output = u_boot_console.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}')
+ m = re.search('==> (.+?)$', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+
+ old_size = 0
+ for size in (
+ random.randint(4, page_size),
+ random.randint(page_size, total_size),
+ total_size,
+ ):
+ size = size & ~3
+ size = size - old_size
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf write {hex(addr + 0x10000 + old_size)} {hex(old_size)} {hex(size)}'
+ )
+ assert EXPECTED_WRITE in output
+ old_size += size
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf read {hex(addr + 0x10000 + total_size)} 0 {hex(total_size)}'
+ )
+ assert EXPECTED_READ in output
+
+ output = u_boot_console.run_command(
+ f'crc32 {hex(addr + 0x10000 + total_size)} {hex(total_size)}'
+ )
+ assert expected_crc32 in output
+
+@pytest.mark.buildconfigspec('cmd_bdi')
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_spi_write_continues(u_boot_console):
+ ''' Test to write more random size data for SPI '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_write_twice(
+ u_boot_console,
+ get_page_size(),
+ get_erase_size(),
+ get_total_size(),
+ get_timeout(),
+ )
+ i = i + 1
+
+def spi_read_twice(u_boot_console, page_size, total_size, timeout):
+ ''' Read the whole SPI flash twice, random_size till full flash size,
+ random till page size '''
+ for size in random.randint(4, page_size), random.randint(4, total_size), total_size:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ size = size & ~3
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf read {hex(addr + total_size)} 0 {hex(size)}'
+ )
+ assert EXPECTED_READ in output
+ output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+ m = re.search('==> (.+?)$', output)
+ if not m:
+ pytest.fail('CRC32 failed')
+ expected_crc32 = m.group(1)
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf read {hex(addr + total_size + 10)} 0 {hex(size)}'
+ )
+ assert EXPECTED_READ in output
+ output = u_boot_console.run_command(
+ f'crc32 {hex(addr + total_size + 10)} {hex(size)}'
+ )
+ assert expected_crc32 in output
+
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_bdi')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_spi_read_twice(u_boot_console):
+ ''' Test to read random data twice from SPI '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_read_twice(u_boot_console, get_page_size(), get_total_size(), get_timeout())
+ i = i + 1
+
+def spi_erase_all(u_boot_console, total_size, timeout):
+ ''' Erase the full chip SPI '''
+ start = 0
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(f'sf erase {start} {hex(total_size)}')
+ assert EXPECTED_ERASE in output
+
+@pytest.mark.buildconfigspec('cmd_sf')
+def test_spi_erase_all(u_boot_console):
+ ''' Test to check full chip erase for SPI '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ spi_erase_all(u_boot_console, get_total_size(), get_timeout())
+ i = i + 1
+
+def flash_ops(
+ u_boot_console, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str=''
+):
+ ''' Flash operations: erase, write and read '''
+
+ f = u_boot_console.config.env.get('env__spi_device_test', None)
+ if not f:
+ timeout = 1000000
+
+ timeout = f.get('timeout', 1000000)
+
+ if ops == 'erase':
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(size)}')
+ else:
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ f'sf {ops} {hex(offset)} {hex(start)} {hex(size)}'
+ )
+
+ if exp_str:
+ assert exp_str in output
+ if not_exp_str:
+ assert not_exp_str not in output
+
+ ret_code = u_boot_console.run_command('echo $?')
+ if exp_ret >= 0:
+ assert ret_code.endswith(str(exp_ret))
+
+ return output, ret_code
+
+def spi_unlock_exit(u_boot_console, addr, size):
+ ''' Unlock the flash before making it fail '''
+ u_boot_console.run_command(f'sf protect unlock {hex(addr)} {hex(size)}')
+ assert False, 'FAIL: Flash lock is unable to protect the data!'
+
+def find_prot_region(lock_addr, lock_size):
+ ''' Get the protected and un-protected region of flash '''
+ total_size = get_total_size()
+ erase_size = get_erase_size()
+
+ if lock_addr < (total_size // 2):
+ sect_num = (lock_addr + lock_size) // erase_size
+ x = 1
+ while x < sect_num:
+ x *= 2
+ prot_start = 0
+ prot_size = x * erase_size
+ unprot_start = prot_start + prot_size
+ unprot_size = total_size - unprot_start
+ else:
+ sect_num = (total_size - lock_addr) // erase_size
+ x = 1
+ while x < sect_num:
+ x *= 2
+ prot_start = total_size - (x * erase_size)
+ prot_size = total_size - prot_start
+ unprot_start = 0
+ unprot_size = prot_start
+
+ return prot_start, prot_size, unprot_start, unprot_size
+
+def protect_ops(u_boot_console, lock_addr, lock_size, ops="unlock"):
+ ''' Run the command to lock or Unlock the flash '''
+ u_boot_console.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}')
+ output = u_boot_console.run_command('echo $?')
+ if ops == "lock" and not output.endswith('0'):
+ u_boot_console.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}')
+ assert False, "sf protect lock command exits with non-zero return code"
+ assert output.endswith('0')
+
+def erase_write_ops(u_boot_console, start, size):
+ ''' Basic erase and write operation for flash '''
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ flash_ops(u_boot_console, 'erase', start, size, 0, 0, EXPECTED_ERASE)
+ flash_ops(u_boot_console, 'write', start, size, addr, 0, EXPECTED_WRITE)
+
+def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
+ ''' Lock unlock operations for SPI family flash '''
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ erase_size = get_erase_size()
+
+ # Find the protected/un-protected region
+ prot_start, prot_size, unprot_start, unprot_size = find_prot_region(lock_addr, lock_size)
+
+ # Check erase/write operation before locking
+ erase_write_ops(u_boot_console, prot_start, prot_size)
+
+ # Locking the flash
+ protect_ops(u_boot_console, lock_addr, lock_size, 'lock')
+
+ # Check erase/write operation after locking
+ output, ret_code = flash_ops(u_boot_console, 'erase', prot_start, prot_size, 0, -1)
+ if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
+ '0'
+ ):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ output, ret_code = flash_ops(
+ u_boot_console, 'write', prot_start, prot_size, addr, -1
+ )
+ if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
+ '0'
+ ):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ # Check locked sectors
+ sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
+ if prot_size > erase_size:
+ sect_lock_size = random.randrange(
+ erase_size, (prot_start + prot_size - sect_lock_start), erase_size
+ )
+ else:
+ sect_lock_size = erase_size
+ sect_write_size = random.randint(1, sect_lock_size)
+
+ output, ret_code = flash_ops(
+ u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, -1
+ )
+ if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
+ '0'
+ ):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ output, ret_code = flash_ops(
+ u_boot_console, 'write', sect_lock_start, sect_write_size, addr, -1
+ )
+ if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
+ '0'
+ ):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ # Check unlocked sectors
+ if unprot_size != 0:
+ sect_unlock_start = random.randrange(
+ unprot_start, (unprot_start + unprot_size), erase_size
+ )
+ if unprot_size > erase_size:
+ sect_unlock_size = random.randrange(
+ erase_size, (unprot_start + unprot_size - sect_unlock_start), erase_size
+ )
+ else:
+ sect_unlock_size = erase_size
+ sect_write_size = random.randint(1, sect_unlock_size)
+
+ output, ret_code = flash_ops(
+ u_boot_console, 'erase', sect_unlock_start, sect_unlock_size, 0, -1
+ )
+ if EXPECTED_ERASE not in output or ret_code.endswith('1'):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ output, ret_code = flash_ops(
+ u_boot_console, 'write', sect_unlock_start, sect_write_size, addr, -1
+ )
+ if EXPECTED_WRITE not in output or ret_code.endswith('1'):
+ spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+
+ # Unlocking the flash
+ protect_ops(u_boot_console, lock_addr, lock_size, 'unlock')
+
+ # Check erase/write operation after un-locking
+ erase_write_ops(u_boot_console, prot_start, prot_size)
+
+ # Check previous locked sectors
+ sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
+ if prot_size > erase_size:
+ sect_lock_size = random.randrange(
+ erase_size, (prot_start + prot_size - sect_lock_start), erase_size
+ )
+ else:
+ sect_lock_size = erase_size
+ sect_write_size = random.randint(1, sect_lock_size)
+
+ flash_ops(
+ u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE
+ )
+ flash_ops(
+ u_boot_console,
+ 'write',
+ sect_lock_start,
+ sect_write_size,
+ addr,
+ 0,
+ EXPECTED_WRITE,
+ )
+
+@pytest.mark.buildconfigspec('cmd_bdi')
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_spi_lock_unlock(u_boot_console):
+ ''' Test to check the lock-unlock functionality for SPI family flash '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ flashes = u_boot_console.config.env.get('env__spi_lock_unlock', False)
+ if not flashes:
+ pytest.skip('No supported flash list for lock/unlock provided')
+
+ i = 0
+ while i < loop:
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ total_size = get_total_size()
+ flash_part = get_flash_part()
+
+ flashes_list = flashes.get('supported_flash', None).split(',')
+ flashes_list = [x.strip() for x in flashes_list]
+ if flash_part not in flashes_list:
+ pytest.skip('Detected flash does not support lock/unlock')
+
+ # For lower half of memory
+ lock_addr = random.randint(0, (total_size // 2) - 1)
+ lock_size = random.randint(1, ((total_size // 2) - lock_addr))
+ spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+
+ # For upper half of memory
+ lock_addr = random.randint((total_size // 2), total_size - 1)
+ lock_size = random.randint(1, (total_size - lock_addr))
+ spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+
+ # For entire flash
+ lock_addr = random.randint(0, total_size - 1)
+ lock_size = random.randint(1, (total_size - lock_addr))
+ spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+
+ i = i + 1
+
+@pytest.mark.buildconfigspec('cmd_bdi')
+@pytest.mark.buildconfigspec('cmd_sf')
+@pytest.mark.buildconfigspec('cmd_memory')
+def test_spi_negative(u_boot_console):
+ ''' Negative tests for SPI '''
+ min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+ spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+ total_size = get_total_size()
+ erase_size = get_erase_size()
+ page_size = get_page_size()
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+ i = 0
+ while i < loop:
+ # Erase negative test
+ start = random.randint(0, total_size)
+ esize = erase_size
+
+ # If erasesize is not multiple of flash's erase size
+ while esize % erase_size == 0:
+ esize = random.randint(0, total_size - start)
+
+ error_msg = 'Erased: ERROR'
+ flash_ops(
+ u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ )
+
+ # If eraseoffset exceeds beyond flash size
+ eoffset = random.randint(total_size, (total_size + int(0x1000000)))
+ error_msg = 'Offset exceeds device limit'
+ flash_ops(
+ u_boot_console, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE
+ )
+
+ # If erasesize exceeds beyond flash size
+ esize = random.randint((total_size - start), (total_size + int(0x1000000)))
+ error_msg = 'ERROR: attempting erase past flash size'
+ flash_ops(
+ u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ )
+
+ # If erase size is 0
+ esize = 0
+ error_msg = None
+ flash_ops(
+ u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ )
+
+ # If erasesize is less than flash's page size
+ esize = random.randint(0, page_size)
+ start = random.randint(0, (total_size - page_size))
+ error_msg = 'Erased: ERROR'
+ flash_ops(
+ u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+ )
+
+ # Write/Read negative test
+ # if Write/Read size exceeds beyond flash size
+ offset = random.randint(0, total_size)
+ size = random.randint((total_size - offset), (total_size + int(0x1000000)))
+ error_msg = 'Size exceeds partition or device limit'
+ flash_ops(
+ u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ )
+ flash_ops(
+ u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ )
+
+ # if Write/Read offset exceeds beyond flash size
+ offset = random.randint(total_size, (total_size + int(0x1000000)))
+ size = random.randint(0, total_size)
+ error_msg = 'Offset exceeds device limit'
+ flash_ops(
+ u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ )
+ flash_ops(
+ u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ )
+
+ # if Write/Read size is 0
+ offset = random.randint(0, 2)
+ size = 0
+ error_msg = None
+ flash_ops(
+ u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+ )
+ flash_ops(
+ u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+ )
+
+ i = i + 1
diff --git a/test/py/tests/test_upl.py b/test/py/tests/test_upl.py
new file mode 100644
index 0000000..3164bda
--- /dev/null
+++ b/test/py/tests/test_upl.py
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Google LLC
+#
+# Test addition of Universal Payload
+
+import os
+
+import pytest
+import u_boot_utils
+
+@pytest.mark.boardspec('sandbox_vpl')
+def test_upl_handoff(u_boot_console):
+ """Test of UPL handoff
+
+ This works by starting up U-Boot VPL, which gets to SPL and then sets up a
+ UPL handoff using the FIT containing U-Boot proper. It then jumps to U-Boot
+ proper and runs a test to check that the parameters are correct.
+
+ The entire FIT is loaded into memory in SPL (in upl_load_from_image()) so
+ that it can be inpected in upl_test_info_norun
+ """
+ cons = u_boot_console
+ ram = os.path.join(cons.config.build_dir, 'ram.bin')
+ fdt = os.path.join(cons.config.build_dir, 'u-boot.dtb')
+
+ # Remove any existing RAM file, so we don't have old data present
+ if os.path.exists(ram):
+ os.remove(ram)
+ flags = ['-m', ram, '-d', fdt, '--upl']
+ cons.restart_uboot_with_flags(flags, use_dtb=False)
+
+ # Make sure that Universal Payload is detected in U-Boot proper
+ output = cons.run_command('upl info')
+ assert 'UPL state: active' == output
+
+ # Check the FIT offsets look correct
+ output = cons.run_command('ut upl -f upl_test_info_norun')
+ assert 'Failures: 0' in output
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 05e1583..39aa103 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
-# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+"""
+Unit-test runner
+Provides a test_ut() function which is used by conftest.py to run each unit
+test one at a time, as well setting up some files needed by the tests.
+
+# Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+"""
import collections
import getpass
import gzip
@@ -44,8 +50,8 @@
if second_part:
spec += '\ntype=c'
- u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
- u_boot_utils.run_and_log(cons, 'sudo sfdisk %s' % fname,
+ u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
+ u_boot_utils.run_and_log(cons, f'sudo sfdisk {fname}',
stdin=spec.encode('utf-8'))
return fname, mnt
@@ -61,13 +67,13 @@
Returns:
str: Name of loop device used
"""
- out = u_boot_utils.run_and_log(cons, 'sudo losetup --show -f -P %s' % fname)
+ out = u_boot_utils.run_and_log(cons, f'sudo losetup --show -f -P {fname}')
loop = out.strip()
part = f'{loop}p1'
u_boot_utils.run_and_log(cons, f'sudo mkfs.{fstype} {part}')
opts = ''
if fstype == 'vfat':
- opts += f' -o uid={os.getuid()},gid={os.getgid()}'
+ opts += f' -o uid={os.getuid()},gid={os.getgid()}'
u_boot_utils.run_and_log(cons, f'sudo mount -o loop {part} {mnt}{opts}')
u_boot_utils.run_and_log(cons, f'sudo chown {getpass.getuser()} {mnt}')
return loop
@@ -82,9 +88,7 @@
"""
infname = os.path.join(cons.config.source_dir,
f'test/py/tests/bootstd/mmc{mmc_dev}.img.xz')
- u_boot_utils.run_and_log(
- cons,
- ['sh', '-c', 'xz -dc %s >%s' % (infname, fname)])
+ u_boot_utils.run_and_log(cons, ['sh', '-c', f'xz -dc {infname} >{fname}'])
def setup_bootmenu_image(cons):
"""Create a 20MB disk image with a single ext4 partition
@@ -101,9 +105,6 @@
loop = mount_image(cons, fname, mnt, 'ext4')
mounted = True
- vmlinux = 'Image'
- initrd = 'uInitrd'
- dtbdir = 'dtb'
script = '''# DO NOT EDIT THIS FILE
#
# Please edit /boot/armbianEnv.txt to set supported parameters
@@ -177,12 +178,12 @@
# Recompile with:
# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr
-''' % (mmc_dev)
+'''
bootdir = os.path.join(mnt, 'boot')
mkdir_cond(bootdir)
cmd_fname = os.path.join(bootdir, 'boot.cmd')
scr_fname = os.path.join(bootdir, 'boot.scr')
- with open(cmd_fname, 'w') as outf:
+ with open(cmd_fname, 'w', encoding='ascii') as outf:
print(script, file=outf)
infname = os.path.join(cons.config.source_dir,
@@ -212,13 +213,12 @@
complete = True
except ValueError as exc:
- print('Falled to create image, failing back to prepared copy: %s',
- str(exc))
+ print(f'Falled to create image, failing back to prepared copy: {exc}')
finally:
if mounted:
- u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
+ u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}')
if loop:
- u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
+ u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}')
if not complete:
copy_prepared_image(cons, mmc_dev, fname)
@@ -254,32 +254,32 @@
ext = os.path.join(mnt, 'extlinux')
mkdir_cond(ext)
- with open(os.path.join(ext, 'extlinux.conf'), 'w') as fd:
+ conf = os.path.join(ext, 'extlinux.conf')
+ with open(conf, 'w', encoding='ascii') as fd:
print(script, file=fd)
inf = os.path.join(cons.config.persistent_data_dir, 'inf')
with open(inf, 'wb') as fd:
fd.write(gzip.compress(b'vmlinux'))
- u_boot_utils.run_and_log(cons, 'mkimage -f auto -d %s %s' %
- (inf, os.path.join(mnt, vmlinux)))
+ u_boot_utils.run_and_log(
+ cons, f'mkimage -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
- with open(os.path.join(mnt, initrd), 'w') as fd:
+ with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd:
print('initrd', file=fd)
mkdir_cond(os.path.join(mnt, dtbdir))
- dtb_file = os.path.join(mnt, '%s/sandbox.dtb' % dtbdir)
+ dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb')
u_boot_utils.run_and_log(
- cons, 'dtc -o %s' % dtb_file, stdin=b'/dts-v1/; / {};')
+ cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
complete = True
except ValueError as exc:
- print('Falled to create image, failing back to prepared copy: %s',
- str(exc))
+ print(f'Falled to create image, failing back to prepared copy: {exc}')
finally:
if mounted:
- u_boot_utils.run_and_log(cons, 'sudo umount --lazy %s' % mnt)
+ u_boot_utils.run_and_log(cons, f'sudo umount --lazy {mnt}')
if loop:
- u_boot_utils.run_and_log(cons, 'sudo losetup -d %s' % loop)
+ u_boot_utils.run_and_log(cons, f'sudo losetup -d {loop}')
if not complete:
copy_prepared_image(cons, mmc_dev, fname)
@@ -303,7 +303,8 @@
Return:
bytes: Packed-kernel data
"""
- kern_part = os.path.join(cons.config.result_dir, 'kern-part-{arch}.bin')
+ kern_part = os.path.join(cons.config.result_dir,
+ f'kern-part-{arch}.bin')
u_boot_utils.run_and_log(
cons,
f'futility vbutil_kernel --pack {kern_part} '
@@ -332,7 +333,7 @@
mmc_dev = 5
fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
- u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
+ u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
#mnt = os.path.join(cons.config.persistent_data_dir, 'mnt')
#mkdir_cond(mnt)
u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
@@ -381,20 +382,20 @@
u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
- '''We expect something like this:
- 8239 2048 1 Basic data
- 45 2048 2 ChromeOS kernel
- 8238 1 3 ChromeOS rootfs
- 2093 2048 4 ChromeOS kernel
- 8237 1 5 ChromeOS rootfs
- 41 1 6 ChromeOS kernel
- 42 1 7 ChromeOS rootfs
- 4141 2048 8 Basic data
- 43 1 9 ChromeOS reserved
- 44 1 10 ChromeOS reserved
- 40 1 11 ChromeOS firmware
- 6189 2048 12 EFI System Partition
- '''
+
+ # We expect something like this:
+ # 8239 2048 1 Basic data
+ # 45 2048 2 ChromeOS kernel
+ # 8238 1 3 ChromeOS rootfs
+ # 2093 2048 4 ChromeOS kernel
+ # 8237 1 5 ChromeOS rootfs
+ # 41 1 6 ChromeOS kernel
+ # 42 1 7 ChromeOS rootfs
+ # 4141 2048 8 Basic data
+ # 43 1 9 ChromeOS reserved
+ # 44 1 10 ChromeOS reserved
+ # 40 1 11 ChromeOS firmware
+ # 6189 2048 12 EFI System Partition
# Create a dict (indexed by partition number) containing the above info
for line in out.splitlines():
@@ -446,7 +447,7 @@
mmc_dev = 7
fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
- u_boot_utils.run_and_log(cons, 'qemu-img create %s 20M' % fname)
+ u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
ptr = 40
@@ -498,11 +499,12 @@
with open(fname, 'wb') as outf:
outf.write(disk_data)
- print('wrote to {}'.format(fname))
+ print(f'wrote to {fname}')
return fname
def setup_cedit_file(cons):
+ """Set up a .dtb file for use with testing expo and configuration editor"""
infname = os.path.join(cons.config.source_dir,
'test/boot/files/expo_layout.dts')
inhname = os.path.join(cons.config.source_dir,
@@ -584,7 +586,7 @@
# ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
with u_boot_console.disable_check('unknown_command'):
output = u_boot_console.run_command('ut ' + ut_subtest)
- assert('Unknown command \'quux\' - try \'help\'' in output)
+ assert 'Unknown command \'quux\' - try \'help\'' in output
else:
output = u_boot_console.run_command('ut ' + ut_subtest)
assert output.endswith('Failures: 0')
diff --git a/test/str_ut.c b/test/str_ut.c
index 3897798..96e0489 100644
--- a/test/str_ut.c
+++ b/test/str_ut.c
@@ -342,9 +342,7 @@
ut_asserteq_str("space", ptr[3]);
ut_assertnonnull(ptr[4]);
ut_asserteq_str("", ptr[4]);
- ut_assertnonnull(ptr[5]);
- ut_asserteq_str("", ptr[5]);
- ut_assertnull(ptr[6]);
+ ut_assertnull(ptr[5]);
str_free_list(ptr);
ut_assertok(ut_check_delta(start));
diff --git a/test/test-main.c b/test/test-main.c
index 3fa6f6e..b3d3e24 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -12,6 +12,7 @@
#include <net.h>
#include <of_live.h>
#include <os.h>
+#include <usb.h>
#include <dm/ofnode.h>
#include <dm/root.h>
#include <dm/test.h>
@@ -181,7 +182,7 @@
{
const char *fname = strrchr(test->file, '/') + 1;
- if (!(test->flags & UT_TESTF_DM))
+ if (!(test->flags & UTF_DM))
return false;
return !strstr(fname, "video") || strstr(test->name, "video_base");
@@ -240,14 +241,14 @@
*
* @tests: List of tests to run
* @count: Number of tests to ru
- * Return: true if any of the tests have the UT_TESTF_DM flag
+ * Return: true if any of the tests have the UTF_DM flag
*/
static bool ut_list_has_dm_tests(struct unit_test *tests, int count)
{
struct unit_test *test;
for (test = tests; test < tests + count; test++) {
- if (test->flags & UT_TESTF_DM)
+ if (test->flags & UTF_DM)
return true;
}
@@ -289,26 +290,63 @@
{
ut_assertok(event_init());
- if (test->flags & UT_TESTF_DM)
+ /*
+ * Remove any USB keyboard, so that we can add and remove USB devices
+ * in tests.
+ *
+ * For UT_TESTF_DM tests, the old driver model state is saved and
+ * restored across each test. Within in each test there is therefore a
+ * new driver model state, which means that any USB keyboard device in
+ * stdio points to the old state.
+ *
+ * This is fine in most cases. But if a non-UT_TESTF_DM test starts up
+ * USB (thus creating a stdio record pointing to the USB keyboard
+ * device) then when the test finishes, the new driver model state is
+ * freed, meaning that there is now a stale pointer in stdio.
+ *
+ * This means that any future UT_TESTF_DM test which uses stdin will
+ * cause the console system to call tstc() on the stale device pointer,
+ * causing a crash.
+ *
+ * We don't want to fix this by enabling UT_TESTF_DM for all tests as
+ * this causes other problems. For example, bootflow_efi relies on
+ * U-Boot going through a proper init - without that we don't have the
+ * TCG measurement working and get an error
+ * 'tcg2 measurement fails(0x8000000000000007)'. Once we tidy up how EFI
+ * runs tests (e.g. get rid of all the restarting of U-Boot) we could
+ * potentially make the bootstd tests set UT_TESTF_DM, but other tests
+ * might do the same thing.
+ *
+ * We could add a test flag to declare that USB is being used, but that
+ * seems unnecessary, at least for now. We could detect USB being used
+ * in a test, but there is no obvious drawback to clearing out stale
+ * pointers always.
+ *
+ * So just remove any USB keyboards from the console tables. This allows
+ * UT_TESTF_DM and non-UT_TESTF_DM tests to coexist happily.
+ */
+ usb_kbd_remove_for_test();
+
+ if (test->flags & UTF_DM)
ut_assertok(dm_test_pre_run(uts));
ut_set_skip_delays(uts, false);
uts->start = mallinfo();
- if (test->flags & UT_TESTF_SCAN_PDATA)
+ if (test->flags & UTF_SCAN_PDATA)
ut_assertok(dm_scan_plat(false));
- if (test->flags & UT_TESTF_PROBE_TEST)
+ if (test->flags & UTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
if (CONFIG_IS_ENABLED(OF_REAL) &&
- (test->flags & UT_TESTF_SCAN_FDT)) {
+ (test->flags & UTF_SCAN_FDT)) {
/*
* only set this if we know the ethernet uclass will be created
*/
- eth_set_enable_bootdevs(test->flags & UT_TESTF_ETH_BOOTDEV);
- test_sf_set_enable_bootdevs(test->flags & UT_TESTF_SF_BOOTDEV);
+ eth_set_enable_bootdevs(test->flags & UTF_ETH_BOOTDEV);
+ test_sf_set_enable_bootdevs(test->flags & UTF_SF_BOOTDEV);
ut_assertok(dm_extended_scan(false));
}
@@ -316,10 +354,10 @@
* Do this after FDT scan since dm_scan_other() in bootstd-uclass.c
* checks for the existence of bootstd
*/
- if (test->flags & UT_TESTF_SCAN_PDATA)
+ if (test->flags & UTF_SCAN_PDATA)
ut_assertok(dm_scan_other(false));
- if (IS_ENABLED(CONFIG_SANDBOX) && (test->flags & UT_TESTF_OTHER_FDT)) {
+ if (IS_ENABLED(CONFIG_SANDBOX) && (test->flags & UTF_OTHER_FDT)) {
/* make sure the other FDT is available */
ut_assertok(test_load_other_fdt(uts));
@@ -333,7 +371,7 @@
}
}
- if (test->flags & UT_TESTF_CONSOLE_REC) {
+ if (test->flags & UTF_CONSOLE) {
int ret = console_record_reset_enable();
if (ret) {
@@ -356,7 +394,7 @@
static int test_post_run(struct unit_test_state *uts, struct unit_test *test)
{
ut_unsilence_console(uts);
- if (test->flags & UT_TESTF_DM)
+ if (test->flags & UTF_DM)
ut_assertok(dm_test_post_run(uts));
ut_assertok(cyclic_unregister_all());
ut_assertok(event_uninit());
@@ -403,7 +441,7 @@
const char *note = "";
int ret;
- if ((test->flags & UT_TESTF_DM) && !uts->of_live)
+ if ((test->flags & UTF_DM) && !uts->of_live)
note = " (flat tree)";
printf("Test: %s: %s%s\n", test_name, fname, note);
@@ -450,13 +488,13 @@
{
int runs;
- if ((test->flags & UT_TESTF_OTHER_FDT) && !IS_ENABLED(CONFIG_SANDBOX))
+ if ((test->flags & UTF_OTHER_FDT) && !IS_ENABLED(CONFIG_SANDBOX))
return skip_test(uts);
/* Run with the live tree if possible */
runs = 0;
if (CONFIG_IS_ENABLED(OF_LIVE)) {
- if (!(test->flags & UT_TESTF_FLAT_TREE)) {
+ if (!(test->flags & UTF_FLAT_TREE)) {
uts->of_live = true;
ut_assertok(ut_run_test(uts, test, test->name));
runs++;
@@ -476,10 +514,10 @@
* boards)
*/
if ((!CONFIG_IS_ENABLED(OF_LIVE) ||
- (test->flags & UT_TESTF_SCAN_FDT)) &&
- !(test->flags & UT_TESTF_LIVE_TREE) &&
+ (test->flags & UTF_SCAN_FDT)) &&
+ !(test->flags & UTF_LIVE_TREE) &&
(CONFIG_IS_ENABLED(OFNODE_MULTI_TREE) ||
- !(test->flags & UT_TESTF_OTHER_FDT)) &&
+ !(test->flags & UTF_OTHER_FDT)) &&
(!runs || ut_test_run_on_flattree(test)) &&
!(gd->flags & GD_FLG_FDT_CHANGED)) {
uts->of_live = false;
@@ -540,7 +578,7 @@
if (!test_matches(prefix, test_name, select_name))
continue;
- if (test->flags & UT_TESTF_MANUAL) {
+ if (test->flags & UTF_MANUAL) {
int len;
/*
diff --git a/test/ut.c b/test/ut.c
index ae99831..7454da3 100644
--- a/test/ut.c
+++ b/test/ut.c
@@ -59,9 +59,11 @@
ut_fail(uts, __FILE__, __LINE__, __func__,
"Console record buffer too small - increase CONFIG_CONSOLE_RECORD_OUT_SIZE");
return ret;
+ } else if (ret == -ENOENT) {
+ strcpy(uts->actual_str, "<no-more-output>");
}
- return 0;
+ return ret;
}
int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...)
@@ -79,8 +81,8 @@
return -EOVERFLOW;
}
ret = readline_check(uts);
- if (ret < 0)
- return ret;
+ if (ret == -ENOENT)
+ return 1;
return strcmp(uts->expect_str, uts->actual_str);
}
diff --git a/tools/Makefile b/tools/Makefile
index 6a4280e..ee08a96 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -246,12 +246,12 @@
HOSTCFLAGS_mkeficapsule.o += \
$(shell pkg-config --cflags gnutls 2> /dev/null || echo "")
-HOSTCFLAGS_mkeficapsule.o += \
- $(shell pkg-config --cflags uuid 2> /dev/null || echo "")
HOSTLDLIBS_mkeficapsule += \
$(shell pkg-config --libs gnutls 2> /dev/null || echo "-lgnutls")
-HOSTLDLIBS_mkeficapsule += \
- $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid")
+mkeficapsule-objs := generated/lib/uuid.o \
+ generated/lib/sha1.o \
+ $(LIBFDT_OBJS) \
+ mkeficapsule.o
hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule
mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 0cafc36..f9a3a42 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -494,12 +494,18 @@
For example, say SPL is at the start of the image and linked to start at address
80108000. If U-Boot's image-pos is 0x8000 then binman will write an image-pos
for U-Boot of 80110000 into the SPL binary, since it assumes the image is loaded
-to 80108000, with SPL at 80108000 and U-Boot at 80110000.
+to 80108000, with SPL at 80108000 and U-Boot at 80110000. In other words, the
+positions are calculated relative to the start address of the image to which
+they are being written.
For x86 devices (with the end-at-4gb property) this base address is not added
since it is assumed that images are XIP and the offsets already include the
address.
+For non-x86 cases where the symbol is used as a flash offset, the symbols-base
+property can be set to that offset (e.g. 0), so that the unadjusted image-pos
+is written into the image.
+
While U-Boot's symbol updating is handled automatically by the u-boot-spl
entry type (and others), it is possible to use this feature with any blob. To
do this, add a `write-symbols` (boolean) property to the node, set the ELF
@@ -741,6 +747,17 @@
properties are brought into the target node. See Templates_ below for
more information.
+symbols-base:
+ When writing symbols into a binary, the value of that symbol is assumed to
+ be relative to the base address of the binary. This allow the binary to be
+ loaded in memory at its base address, so that symbols point into the binary
+ correctly. In some cases the binary is in fact not yet in memory, but must
+ be read from storage. In this case there is no base address for the symbols.
+ This property can be set to 0 to indicate this. Other values for
+ symbols-base are allowed, but care must be taken that the code which uses
+ the symbol is aware of the base being used. If omitted, the binary's base
+ address is used.
+
The attributes supported for images and sections are described below. Several
are similar to those for entries.
diff --git a/tools/binman/btool/fdtgrep.py b/tools/binman/btool/fdtgrep.py
index da1f8c7..446b2f4 100644
--- a/tools/binman/btool/fdtgrep.py
+++ b/tools/binman/btool/fdtgrep.py
@@ -74,8 +74,7 @@
(with only neceesary nodes and properties)
Returns:
- CommandResult: Resulting output from the bintool, or None if the
- tool is not present
+ str or bytes: Resulting stdout from the bintool
"""
if phase == 'tpl':
tag = 'bootph-pre-sram'
diff --git a/tools/binman/elf.py b/tools/binman/elf.py
index a469405..c75f447 100644
--- a/tools/binman/elf.py
+++ b/tools/binman/elf.py
@@ -234,7 +234,7 @@
return val - base
def LookupAndWriteSymbols(elf_fname, entry, section, is_elf=False,
- base_sym=None):
+ base_sym=None, base_addr=None):
"""Replace all symbols in an entry with their correct values
The entry contents is updated so that values for referenced symbols will be
@@ -247,7 +247,10 @@
entry
entry: Entry to process
section: Section which can be used to lookup symbol values
- base_sym: Base symbol marking the start of the image
+ base_sym: Base symbol marking the start of the image (__image_copy_start
+ by default)
+ base_addr (int): Base address to use for the entry being written. If
+ None then the value of base_sym is used
Returns:
int: Number of symbols written
@@ -277,7 +280,8 @@
if not base and not is_elf:
tout.debug(f'LookupAndWriteSymbols: no base: elf_fname={elf_fname}, base_sym={base_sym}, is_elf={is_elf}')
return 0
- base_addr = 0 if is_elf else base.address
+ if base_addr is None:
+ base_addr = 0 if is_elf else base.address
count = 0
for name, sym in syms.items():
if name.startswith('_binman'):
@@ -301,8 +305,8 @@
value = BINMAN_SYM_MAGIC_VALUE
else:
# Look up the symbol in our entry tables.
- value = section.GetImage().LookupImageSymbol(name, sym.weak,
- msg, base_addr)
+ value = section.GetImage().GetImageSymbolValue(name, sym.weak,
+ msg, base_addr)
if value is None:
value = -1
pack_string = pack_string.lower()
diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py
index b641341..2f22639 100644
--- a/tools/binman/elf_test.py
+++ b/tools/binman/elf_test.py
@@ -37,7 +37,7 @@
"""A fake Section object, used for testing
This has the minimum feature set needed to support testing elf functions.
- A LookupSymbol() function is provided which returns a fake value for amu
+ A GetSymbolValue() function is provided which returns a fake value for any
symbol requested.
"""
def __init__(self, sym_value=1):
@@ -46,7 +46,7 @@
def GetPath(self):
return 'section_path'
- def LookupImageSymbol(self, name, weak, msg, base_addr):
+ def GetImageSymbolValue(self, name, weak, msg, base_addr):
"""Fake implementation which returns the same value for all symbols"""
return self.sym_value
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 1248270..d82f7b8 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -221,7 +221,7 @@
.. _FIP: https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#firmware-image-package-fip
.. _`TF-A source tree`: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
-.. _`send a patch`: https://www.denx.de/wiki/U-Boot/Patches
+.. _`send a patch`: https://docs.u-boot.org/en/latest/develop/sending_patches.html
diff --git a/tools/binman/entry.py b/tools/binman/entry.py
index 6d2f378..68f8d62 100644
--- a/tools/binman/entry.py
+++ b/tools/binman/entry.py
@@ -108,6 +108,9 @@
not need to be done again. This is only used with 'binman replace',
to stop sections from being rebuilt if their entries have not been
replaced
+ symbols_base (int): Use this value as the assumed load address of the
+ target entry, when calculating the symbol value. If None, this is
+ 0 for blobs and the image-start address for ELF files
"""
fake_dir = None
@@ -159,6 +162,7 @@
self.preserve = False
self.build_done = False
self.no_write_symbols = False
+ self.symbols_base = None
@staticmethod
def FindEntryClass(etype, expanded):
@@ -324,6 +328,7 @@
self.preserve = fdt_util.GetBool(self._node, 'preserve')
self.no_write_symbols = fdt_util.GetBool(self._node, 'no-write-symbols')
+ self.symbols_base = fdt_util.GetInt(self._node, 'symbols-base')
def GetDefaultFilename(self):
return None
@@ -576,8 +581,16 @@
def GetEntryArgsOrProps(self, props, required=False):
"""Return the values of a set of properties
+ Looks up the named entryargs and returns the value for each. If any
+ required ones are missing, the error is reported to the user.
+
Args:
- props: List of EntryArg objects
+ props (list of EntryArg): List of entry arguments to look up
+ required (bool): True if these entry arguments are required
+
+ Returns:
+ list of values: one for each item in props, the type is determined
+ by the EntryArg's 'datatype' property (str or int)
Raises:
ValueError if a property is not found
@@ -698,14 +711,22 @@
def WriteSymbols(self, section):
"""Write symbol values into binary files for access at run time
+ As a special case, if symbols_base is not specified and this is an
+ end-at-4gb image, a symbols_base of 0 is used
+
Args:
section: Section containing the entry
"""
if self.auto_write_symbols and not self.no_write_symbols:
# Check if we are writing symbols into an ELF file
is_elf = self.GetDefaultFilename() == self.elf_fname
+
+ symbols_base = self.symbols_base
+ if symbols_base is None and self.GetImage()._end_4gb:
+ symbols_base = 0
+
elf.LookupAndWriteSymbols(self.elf_fname, self, section.GetImage(),
- is_elf, self.elf_base_sym)
+ is_elf, self.elf_base_sym, symbols_base)
def CheckEntries(self):
"""Check that the entry offsets are correct
diff --git a/tools/binman/etype/atf_fip.py b/tools/binman/etype/atf_fip.py
index 73a3f85..636e073 100644
--- a/tools/binman/etype/atf_fip.py
+++ b/tools/binman/etype/atf_fip.py
@@ -163,7 +163,7 @@
.. _FIP: https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#firmware-image-package-fip
.. _`TF-A source tree`: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
- .. _`send a patch`: https://www.denx.de/wiki/U-Boot/Patches
+ .. _`send a patch`: https://docs.u-boot.org/en/latest/develop/sending_patches.html
"""
def __init__(self, section, etype, node):
# Put this here to allow entry-docs and help to work without libfdt
@@ -248,7 +248,7 @@
fent = entry._fip_entry
entry.size = fent.size
entry.offset = fent.offset
- entry.image_pos = self.image_pos + entry.offset
+ entry.SetImagePos(image_pos + self.offset)
def ReadChildData(self, child, decomp=True, alt_format=None):
if not self.reader:
diff --git a/tools/binman/etype/blob_phase.py b/tools/binman/etype/blob_phase.py
index 951d993..09bb89b 100644
--- a/tools/binman/etype/blob_phase.py
+++ b/tools/binman/etype/blob_phase.py
@@ -57,3 +57,8 @@
if self.no_write_symbols:
for entry in self._entries.values():
entry.no_write_symbols = True
+
+ # Propagate the symbols-base property
+ if self.symbols_base is not None:
+ for entry in self._entries.values():
+ entry.symbols_base = self.symbols_base
diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py
index 575aa62..124fa1e 100644
--- a/tools/binman/etype/cbfs.py
+++ b/tools/binman/etype/cbfs.py
@@ -245,7 +245,7 @@
cfile = entry._cbfs_file
entry.size = cfile.data_len
entry.offset = cfile.calced_cbfs_offset
- entry.image_pos = self.image_pos + entry.offset
+ entry.SetImagePos(image_pos + self.offset)
if entry._cbfs_compress:
entry.uncomp_size = cfile.memlen
diff --git a/tools/binman/etype/efi_capsule.py b/tools/binman/etype/efi_capsule.py
index 5941545..9f06cc8 100644
--- a/tools/binman/etype/efi_capsule.py
+++ b/tools/binman/etype/efi_capsule.py
@@ -24,7 +24,7 @@
The actual GUID value (str)
"""
TYPE_TO_GUID = {
- 'binman-test' : '09d7cf52-0720-4710-91d1-08469b7fe9c8'
+ 'binman-test' : '985f2937-7c2e-5e9a-8a5e-8e063312964b'
}
return TYPE_TO_GUID[type_str]
@@ -151,6 +151,8 @@
return tools.read_file(capsule_fname)
else:
# Bintool is missing; just use the input data as the output
+ if not self.GetAllowMissing():
+ self.Raise("Missing tool: 'mkeficapsule'")
self.record_missing_bintool(self.mkeficapsule)
return data
diff --git a/tools/binman/etype/fit.py b/tools/binman/etype/fit.py
index ee44e5a..0abe1c7 100644
--- a/tools/binman/etype/fit.py
+++ b/tools/binman/etype/fit.py
@@ -6,9 +6,10 @@
"""Entry-type module for producing a FIT"""
import glob
-import libfdt
import os
+import libfdt
+
from binman.entry import Entry, EntryArg
from binman.etype.section import Entry_section
from binman import elf
@@ -23,6 +24,7 @@
'split-elf': OP_SPLIT_ELF,
}
+# pylint: disable=invalid-name
class Entry_fit(Entry_section):
"""Flat Image Tree (FIT)
@@ -94,7 +96,10 @@
can be provided as a directory. Each .dtb file in the directory is
processed, , e.g.::
+ fit,fdt-list-dir = "arch/arm/dts";
+
- fit,fdt-list-dir = "arch/arm/dts
+ In this case the input directories are ignored and all devicetree
+ files must be in that directory.
Substitutions
~~~~~~~~~~~~~
@@ -381,31 +386,46 @@
def __init__(self, section, etype, node):
"""
Members:
- _fit: FIT file being built
- _entries: dict from Entry_section:
+ _fit (str): FIT file being built
+ _fit_props (list of str): 'fit,...' properties found in the
+ top-level node
+ _fdts (list of str): Filenames of .dtb files to process
+ _fdt_dir (str): Directory to scan to find .dtb files, or None
+ _fit_list_prop (str): Name of the EntryArg containing a list of .dtb
+ files
+ _fit_default_dt (str): Name of the EntryArg containing the default
+ .dtb file
+ _entries (dict of entries): from Entry_section:
key: relative path to entry Node (from the base of the FIT)
value: Entry_section object comprising the contents of this
node
- _priv_entries: Internal copy of _entries which includes 'generator'
- entries which are used to create the FIT, but should not be
- processed as real entries. This is set up once we have the
- entries
- _loadables: List of generated split-elf nodes, each a node name
+ _priv_entries (dict of entries): Internal copy of _entries which
+ includes 'generator' entries which are used to create the FIT,
+ but should not be processed as real entries. This is set up once
+ we have the entries
+ _loadables (list of str): List of generated split-elf nodes, each
+ a node name
+ _remove_props (list of str): Value of of-spl-remove-props EntryArg,
+ the list of properties to remove with fdtgrep
+ mkimage (Bintool): mkimage tool
+ fdtgrep (Bintool): fdtgrep tool
"""
super().__init__(section, etype, node)
self._fit = None
self._fit_props = {}
self._fdts = None
self._fdt_dir = None
- self.mkimage = None
- self.fdtgrep = None
+ self._fit_list_prop = None
+ self._fit_default_dt = None
self._priv_entries = {}
self._loadables = []
self._remove_props = []
- props, = self.GetEntryArgsOrProps(
- [EntryArg('of-spl-remove-props', str)], required=False)
+ props = self.GetEntryArgsOrProps(
+ [EntryArg('of-spl-remove-props', str)], required=False)[0]
if props:
self._remove_props = props.split()
+ self.mkimage = None
+ self.fdtgrep = None
def ReadNode(self):
super().ReadNode()
@@ -414,8 +434,8 @@
self._fit_props[pname] = prop
self._fit_list_prop = self._fit_props.get('fit,fdt-list')
if self._fit_list_prop:
- fdts, = self.GetEntryArgsOrProps(
- [EntryArg(self._fit_list_prop.value, str)])
+ fdts = self.GetEntryArgsOrProps(
+ [EntryArg(self._fit_list_prop.value, str)])[0]
if fdts is not None:
self._fdts = fdts.split()
else:
@@ -431,7 +451,7 @@
self._fit_default_dt = self.GetEntryArgsOrProps([EntryArg('default-dt',
str)])[0]
- def _get_operation(self, base_node, node):
+ def _get_operation(self, node):
"""Get the operation referenced by a subnode
Args:
@@ -550,6 +570,9 @@
phase (str): Phase to generate for ('tpl', 'vpl', 'spl')
outfile (str): Output filename to write the grepped FDT contents to
(with only neceesary nodes and properties)
+
+ Returns:
+ str or bytes: Resulting stdout from fdtgrep
"""
return self.fdtgrep.create_for_phase(infile, phase, outfile,
self._remove_props)
@@ -557,9 +580,6 @@
def _build_input(self):
"""Finish the FIT by adding the 'data' properties to it
- Arguments:
- fdt: FIT to update
-
Returns:
bytes: New fdt contents
"""
@@ -580,13 +600,17 @@
if val.startswith('@'):
if not self._fdts:
return
- if not self._fit_default_dt:
+ default_dt = self._fit_default_dt
+ if not default_dt:
self.Raise("Generated 'default' node requires default-dt entry argument")
- if self._fit_default_dt not in self._fdts:
- self.Raise(
- f"default-dt entry argument '{self._fit_default_dt}' "
- f"not found in fdt list: {', '.join(self._fdts)}")
- seq = self._fdts.index(self._fit_default_dt)
+ if default_dt not in self._fdts:
+ if self._fdt_dir:
+ default_dt = os.path.basename(default_dt)
+ if default_dt not in self._fdts:
+ self.Raise(
+ f"default-dt entry argument '{self._fit_default_dt}' "
+ f"not found in fdt list: {', '.join(self._fdts)}")
+ seq = self._fdts.index(default_dt)
val = val[1:].replace('DEFAULT-SEQ', str(seq + 1))
fsw.property_string(pname, val)
return
@@ -634,7 +658,7 @@
result.append(name)
return firmware, result
- def _gen_fdt_nodes(base_node, node, depth, in_images):
+ def _gen_fdt_nodes(node, depth, in_images):
"""Generate FDT nodes
This creates one node for each member of self._fdts using the
@@ -654,7 +678,10 @@
# Generate nodes for each FDT
for seq, fdt_fname in enumerate(self._fdts):
node_name = node.name[1:].replace('SEQ', str(seq + 1))
- fname = tools.get_input_filename(fdt_fname + '.dtb')
+ if self._fdt_dir:
+ fname = os.path.join(self._fdt_dir, fdt_fname + '.dtb')
+ else:
+ fname = tools.get_input_filename(fdt_fname + '.dtb')
fdt_phase = None
with fsw.add_node(node_name):
for pname, prop in node.props.items():
@@ -688,8 +715,9 @@
# Add data for 'images' nodes (but not 'config')
if depth == 1 and in_images:
if fdt_phase:
+ leaf = os.path.basename(fdt_fname)
phase_fname = tools.get_output_filename(
- f'{fdt_fname}-{fdt_phase}.dtb')
+ f'{leaf}-{fdt_phase}.dtb')
self._run_fdtgrep(fname, fdt_phase, phase_fname)
data = tools.read_file(phase_fname)
else:
@@ -707,11 +735,10 @@
else:
self.Raise("Generator node requires 'fit,fdt-list' property")
- def _gen_split_elf(base_node, node, depth, segments, entry_addr):
+ def _gen_split_elf(node, depth, segments, entry_addr):
"""Add nodes for the ELF file, one per group of contiguous segments
Args:
- base_node (Node): Template node from the binman definition
node (Node): Node to replace (in the FIT being built)
depth: Current node depth (0 is the base 'fit' node)
segments (list): list of segments, each:
@@ -742,7 +769,7 @@
with fsw.add_node(subnode.name):
_add_node(node, depth + 1, subnode)
- def _gen_node(base_node, node, depth, in_images, entry):
+ def _gen_node(node, depth, in_images, entry):
"""Generate nodes from a template
This creates one or more nodes depending on the fit,operation being
@@ -758,8 +785,6 @@
If the file is missing, nothing is generated.
Args:
- base_node (Node): Base Node of the FIT (with 'description'
- property)
node (Node): Generator node to process
depth (int): Current node depth (0 is the base 'fit' node)
in_images (bool): True if this is inside the 'images' node, so
@@ -767,13 +792,12 @@
entry (entry_Section): Entry for the section containing the
contents of this node
"""
- oper = self._get_operation(base_node, node)
+ oper = self._get_operation(node)
if oper == OP_GEN_FDT_NODES:
- _gen_fdt_nodes(base_node, node, depth, in_images)
+ _gen_fdt_nodes(node, depth, in_images)
elif oper == OP_SPLIT_ELF:
# Entry_section.ObtainContents() either returns True or
# raises an exception.
- data = None
missing_opt_list = []
entry.ObtainContents()
entry.Pack(0)
@@ -795,7 +819,7 @@
self._raise_subnode(
node, f'Failed to read ELF file: {str(exc)}')
- _gen_split_elf(base_node, node, depth, segments, entry_addr)
+ _gen_split_elf(node, depth, segments, entry_addr)
def _add_node(base_node, depth, node):
"""Add nodes to the output FIT
@@ -826,7 +850,6 @@
fsw.property('data', bytes(data))
for subnode in node.subnodes:
- subnode_path = f'{rel_path}/{subnode.name}'
if has_images and not self.IsSpecialSubnode(subnode):
# This subnode is a content node not meant to appear in
# the FIT (e.g. "/images/kernel/u-boot"), so don't call
@@ -834,7 +857,7 @@
pass
elif self.GetImage().generate and subnode.name.startswith('@'):
entry = self._priv_entries.get(subnode.name)
- _gen_node(base_node, subnode, depth, in_images, entry)
+ _gen_node(subnode, depth, in_images, entry)
# This is a generator (template) entry, so remove it from
# the list of entries used by PackEntries(), etc. Otherwise
# it will appear in the binman output
@@ -876,7 +899,10 @@
"""
if self.build_done:
return
- super().SetImagePos(image_pos)
+
+ # Skip the section processing, since we do that below. Just call the
+ # entry method
+ Entry.SetImagePos(self, image_pos)
# If mkimage is missing we'll have empty data,
# which will cause a FDT_ERR_BADMAGIC error
@@ -886,7 +912,7 @@
fdt = Fdt.FromData(self.GetData())
fdt.Scan()
- for image_name, section in self._entries.items():
+ for image_name, entry in self._entries.items():
path = f"/images/{image_name}"
node = fdt.GetNode(path)
@@ -914,10 +940,12 @@
# This should never happen
else: # pragma: no cover
+ offset = None
+ size = None
self.Raise(f'{path}: missing data properties')
- section.SetOffsetSize(offset, size)
- section.SetImagePos(self.image_pos)
+ entry.SetOffsetSize(offset, size)
+ entry.SetImagePos(image_pos + self.offset)
def AddBintools(self, btools):
super().AddBintools(btools)
@@ -947,7 +975,7 @@
if input_fname:
fname = input_fname
else:
- fname = tools.get_output_filename('%s.fit' % uniq)
+ fname = tools.get_output_filename(f'{uniq}.fit')
tools.write_file(fname, self.GetData())
args.append(fname)
diff --git a/tools/binman/etype/nxp_imx8mimage.py b/tools/binman/etype/nxp_imx8mimage.py
index 3585120..8ad177b 100644
--- a/tools/binman/etype/nxp_imx8mimage.py
+++ b/tools/binman/etype/nxp_imx8mimage.py
@@ -27,7 +27,8 @@
def __init__(self, section, etype, node):
super().__init__(section, etype, node)
- self.required_props = ['nxp,boot-from', 'nxp,rom-version', 'nxp,loader-address']
+ self.required_props = ['nxp,boot-from', 'nxp,rom-version',
+ 'nxp,loader-address']
def ReadNode(self):
super().ReadNode()
diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py
index 30c1041..f4f48c0 100644
--- a/tools/binman/etype/section.py
+++ b/tools/binman/etype/section.py
@@ -563,13 +563,13 @@
return entry.GetData(required)
def LookupEntry(self, entries, sym_name, msg):
- """Look up the entry for an ENF symbol
+ """Look up the entry for a binman symbol
Args:
entries (dict): entries to search:
key: entry name
value: Entry object
- sym_name: Symbol name in the ELF file to look up in the format
+ sym_name: Symbol name to look up in the format
_binman_<entry>_prop_<property> where <entry> is the name of
the entry and <property> is the property to find (e.g.
_binman_u_boot_prop_offset). As a special case, you can append
@@ -606,11 +606,10 @@
entry = entries[name]
return entry, entry_name, prop_name
- def LookupSymbol(self, sym_name, optional, msg, base_addr, entries=None):
- """Look up a symbol in an ELF file
+ def GetSymbolValue(self, sym_name, optional, msg, base_addr, entries=None):
+ """Get the value of a Binman symbol
- Looks up a symbol in an ELF file. Only entry types which come from an
- ELF image can be used by this function.
+ Look up a Binman symbol and obtain its value.
At present the only entry properties supported are:
offset
@@ -618,7 +617,7 @@
size
Args:
- sym_name: Symbol name in the ELF file to look up in the format
+ sym_name: Symbol name to look up in the format
_binman_<entry>_prop_<property> where <entry> is the name of
the entry and <property> is the property to find (e.g.
_binman_u_boot_prop_offset). As a special case, you can append
@@ -628,12 +627,10 @@
optional: True if the symbol is optional. If False this function
will raise if the symbol is not found
msg: Message to display if an error occurs
- base_addr: Base address of image. This is added to the returned
- image_pos in most cases so that the returned position indicates
- where the targetted entry/binary has actually been loaded. But
- if end-at-4gb is used, this is not done, since the binary is
- already assumed to be linked to the ROM position and using
- execute-in-place (XIP).
+ base_addr (int): Base address of image. This is added to the
+ returned value of image-pos so that the returned position
+ indicates where the targeted entry/binary has actually been
+ loaded
Returns:
Value that should be assigned to that symbol, or None if it was
@@ -656,10 +653,10 @@
if prop_name == 'offset':
return entry.offset
elif prop_name == 'image_pos':
- value = entry.image_pos
- if not self.GetImage()._end_4gb:
- value += base_addr
- return value
+ if not entry.image_pos:
+ tout.info(f'Symbol-writing: no value for {entry._node.path}')
+ return None
+ return base_addr + entry.image_pos
if prop_name == 'size':
return entry.size
else:
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 93f3d22..e3f231e 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -125,7 +125,7 @@
# Firmware Management Protocol(FMP) GUID
FW_MGMT_GUID = '6dcbd5ed-e82d-4c44-bda1-7194199ad92a'
# Image GUID specified in the DTS
-CAPSULE_IMAGE_GUID = '09d7cf52-0720-4710-91d1-08469b7fe9c8'
+CAPSULE_IMAGE_GUID = '985F2937-7C2E-5E9A-8A5E-8E063312964B'
# Windows cert GUID
WIN_CERT_TYPE_EFI_GUID = '4aafd29d-68df-49ee-8aa9-347d375665a7'
# Empty capsule GUIDs
@@ -403,8 +403,10 @@
test_section_timeout: True to force the first time to timeout, as
used in testThreadTimeout()
update_fdt_in_elf: Value to pass with --update-fdt-in-elf=xxx
- force_missing_tools (str): comma-separated list of bintools to
+ force_missing_bintools (str): comma-separated list of bintools to
regard as missing
+ ignore_missing (bool): True to return success even if there are
+ missing blobs or bintools
output_dir: Specific output directory to use for image using -O
Returns:
@@ -503,8 +505,9 @@
return dtb.GetContents()
def _DoReadFileDtb(self, fname, use_real_dtb=False, use_expanded=False,
- map=False, update_dtb=False, entry_args=None,
- reset_dtbs=True, extra_indirs=None, threads=None):
+ verbosity=None, map=False, update_dtb=False,
+ entry_args=None, reset_dtbs=True, extra_indirs=None,
+ threads=None):
"""Run binman and return the resulting image
This runs binman with a given test file and then reads the resulting
@@ -521,6 +524,7 @@
But in some test we need the real contents.
use_expanded: True to use expanded entries where available, e.g.
'u-boot-expanded' instead of 'u-boot'
+ verbosity: Verbosity level to use (0-3, None=don't set it)
map: True to output map files for the images
update_dtb: Update the offset and size of each entry in the device
tree before packing it into the image
@@ -557,7 +561,8 @@
try:
retcode = self._DoTestFile(fname, map=map, update_dtb=update_dtb,
entry_args=entry_args, use_real_dtb=use_real_dtb,
- use_expanded=use_expanded, extra_indirs=extra_indirs,
+ use_expanded=use_expanded, verbosity=verbosity,
+ extra_indirs=extra_indirs,
threads=threads)
self.assertEqual(0, retcode)
out_dtb_fname = tools.get_output_filename('u-boot.dtb.out')
@@ -1498,18 +1503,22 @@
self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)])
def checkSymbols(self, dts, base_data, u_boot_offset, entry_args=None,
- use_expanded=False, no_write_symbols=False):
+ use_expanded=False, no_write_symbols=False,
+ symbols_base=None):
"""Check the image contains the expected symbol values
Args:
dts: Device tree file to use for test
base_data: Data before and after 'u-boot' section
- u_boot_offset: Offset of 'u-boot' section in image
+ u_boot_offset (int): Offset of 'u-boot' section in image, or None if
+ the offset not available due to it being in a compressed section
entry_args: Dict of entry args to supply to binman
key: arg name
value: value of that arg
use_expanded: True to use expanded entries where available, e.g.
'u-boot-expanded' instead of 'u-boot'
+ symbols_base (int): Value to expect for symbols-base in u-boot-spl,
+ None if none
"""
elf_fname = self.ElfTestFile('u_boot_binman_syms')
syms = elf.GetSymbols(elf_fname, ['binman', 'image'])
@@ -1520,22 +1529,64 @@
self._SetupSplElf('u_boot_binman_syms')
data = self._DoReadFileDtb(dts, entry_args=entry_args,
- use_expanded=use_expanded)[0]
+ use_expanded=use_expanded,
+ verbosity=None if u_boot_offset else 3)[0]
+
+ # The lz4-compressed version of the U-Boot data is 19 bytes long
+ comp_uboot_len = 19
+
# The image should contain the symbols from u_boot_binman_syms.c
# Note that image_pos is adjusted by the base address of the image,
# which is 0x10 in our test image
- sym_values = struct.pack('<LLQLL', elf.BINMAN_SYM_MAGIC_VALUE,
- 0x00, u_boot_offset + len(U_BOOT_DATA),
- 0x10 + u_boot_offset, 0x04)
+ # If u_boot_offset is None, Binman should write -1U into the image
+ vals2 = (elf.BINMAN_SYM_MAGIC_VALUE, 0x00,
+ u_boot_offset + len(U_BOOT_DATA) if u_boot_offset else
+ len(U_BOOT_SPL_DATA) + 1 + comp_uboot_len,
+ 0x10 + u_boot_offset if u_boot_offset else 0xffffffff, 0x04)
+
+ # u-boot-spl has a symbols-base property, so take that into account if
+ # required. The caller must supply the value
+ vals = list(vals2)
+ if symbols_base is not None:
+ vals[3] = symbols_base + u_boot_offset
+ vals = tuple(vals)
+
+ sym_values = struct.pack('<LLQLL', *vals)
+ sym_values2 = struct.pack('<LLQLL', *vals2)
if no_write_symbols:
- expected = (base_data +
- tools.get_bytes(0xff, 0x38 - len(base_data)) +
- U_BOOT_DATA + base_data)
+ self.assertEqual(
+ base_data +
+ tools.get_bytes(0xff, 0x38 - len(base_data)) +
+ U_BOOT_DATA + base_data, data)
else:
- expected = (sym_values + base_data[24:] +
- tools.get_bytes(0xff, 1) + U_BOOT_DATA + sym_values +
- base_data[24:])
- self.assertEqual(expected, data)
+ got_vals = struct.unpack('<LLQLL', data[:24])
+
+ # For debugging:
+ #print('expect:', list(f'{v:x}' for v in vals))
+ #print(' got:', list(f'{v:x}' for v in got_vals))
+
+ self.assertEqual(vals, got_vals)
+ self.assertEqual(sym_values, data[:24])
+
+ blen = len(base_data)
+ self.assertEqual(base_data[24:], data[24:blen])
+ self.assertEqual(0xff, data[blen])
+
+ if u_boot_offset:
+ ofs = blen + 1 + len(U_BOOT_DATA)
+ self.assertEqual(U_BOOT_DATA, data[blen + 1:ofs])
+ else:
+ ofs = blen + 1 + comp_uboot_len
+
+ self.assertEqual(sym_values2, data[ofs:ofs + 24])
+ self.assertEqual(base_data[24:], data[ofs + 24:])
+
+ # Just repeating the above asserts all at once, for clarity
+ if u_boot_offset:
+ expected = (sym_values + base_data[24:] +
+ tools.get_bytes(0xff, 1) + U_BOOT_DATA +
+ sym_values2 + base_data[24:])
+ self.assertEqual(expected, data)
def testSymbols(self):
"""Test binman can assign symbols embedded in U-Boot"""
@@ -4181,7 +4232,8 @@
data = self._DoReadFile('172_scp.dts')
self.assertEqual(SCP_DATA, data[:len(SCP_DATA)])
- def CheckFitFdt(self, dts='170_fit_fdt.dts', use_fdt_list=True):
+ def CheckFitFdt(self, dts='170_fit_fdt.dts', use_fdt_list=True,
+ default_dt=None):
"""Check an image with an FIT with multiple FDT images"""
def _CheckFdt(seq, expected_data):
"""Check the FDT nodes
@@ -4225,6 +4277,8 @@
}
if use_fdt_list:
entry_args['of-list'] = 'test-fdt1 test-fdt2'
+ if default_dt:
+ entry_args['default-dt'] = default_dt
data = self._DoReadFileDtb(
dts,
entry_args=entry_args,
@@ -7624,7 +7678,22 @@
def testFitFdtListDir(self):
"""Test an image with an FIT with FDT images using fit,fdt-list-dir"""
- self.CheckFitFdt('333_fit_fdt_dir.dts', False)
+ old_dir = os.getcwd()
+ try:
+ os.chdir(self._indir)
+ self.CheckFitFdt('333_fit_fdt_dir.dts', False)
+ finally:
+ os.chdir(old_dir)
+
+ def testFitFdtListDirDefault(self):
+ """Test an FIT fit,fdt-list-dir where the default DT in is a subdir"""
+ old_dir = os.getcwd()
+ try:
+ os.chdir(self._indir)
+ self.CheckFitFdt('333_fit_fdt_dir.dts', False,
+ default_dt='rockchip/test-fdt2')
+ finally:
+ os.chdir(old_dir)
def testFitFdtCompat(self):
"""Test an image with an FIT with compatible in the config nodes"""
@@ -7690,6 +7759,51 @@
# Make sure the other node is gone
self.assertIsNone(dtb.GetNode('/node/other-node'))
+ def testMkeficapsuleMissing(self):
+ """Test that binman complains if mkeficapsule is missing"""
+ with self.assertRaises(ValueError) as e:
+ self._DoTestFile('311_capsule.dts',
+ force_missing_bintools='mkeficapsule')
+ self.assertIn("Node '/binman/efi-capsule': Missing tool: 'mkeficapsule'",
+ str(e.exception))
+
+ def testMkeficapsuleMissingOk(self):
+ """Test that binman deals with mkeficapsule being missing"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ ret = self._DoTestFile('311_capsule.dts',
+ force_missing_bintools='mkeficapsule',
+ allow_missing=True)
+ self.assertEqual(103, ret)
+ err = stderr.getvalue()
+ self.assertRegex(err, "Image 'image'.*missing bintools.*: mkeficapsule")
+
+ def testSymbolsBase(self):
+ """Test handling of symbols-base"""
+ self.checkSymbols('336_symbols_base.dts', U_BOOT_SPL_DATA, 0x1c,
+ symbols_base=0)
+
+ def testSymbolsBaseExpanded(self):
+ """Test handling of symbols-base with expanded entries"""
+ entry_args = {
+ 'spl-dtb': '1',
+ }
+ self.checkSymbols('337_symbols_base_expand.dts', U_BOOT_SPL_NODTB_DATA +
+ U_BOOT_SPL_DTB_DATA, 0x38,
+ entry_args=entry_args, use_expanded=True,
+ symbols_base=0)
+
+ def testSymbolsCompressed(self):
+ """Test binman complains about symbols from a compressed section"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self.checkSymbols('338_symbols_comp.dts', U_BOOT_SPL_DATA, None)
+ out = stdout.getvalue()
+ self.assertIn('Symbol-writing: no value for /binman/section/u-boot',
+ out)
+
+ def testNxpImx8Image(self):
+ """Test that binman can produce an iMX8 image"""
+ self._DoTestFile('339_nxp_imx8.dts')
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/image.py b/tools/binman/image.py
index 702c905..24ce0af 100644
--- a/tools/binman/image.py
+++ b/tools/binman/image.py
@@ -381,11 +381,10 @@
selected_entries.append(entry)
return selected_entries, lines, widths
- def LookupImageSymbol(self, sym_name, optional, msg, base_addr):
- """Look up a symbol in an ELF file
+ def GetImageSymbolValue(self, sym_name, optional, msg, base_addr):
+ """Get the value of a Binman symbol
- Looks up a symbol in an ELF file. Only entry types which come from an
- ELF image can be used by this function.
+ Look up a Binman symbol and obtain its value.
This searches through this image including all of its subsections.
@@ -405,12 +404,10 @@
optional: True if the symbol is optional. If False this function
will raise if the symbol is not found
msg: Message to display if an error occurs
- base_addr: Base address of image. This is added to the returned
- image_pos in most cases so that the returned position indicates
- where the targeted entry/binary has actually been loaded. But
- if end-at-4gb is used, this is not done, since the binary is
- already assumed to be linked to the ROM position and using
- execute-in-place (XIP).
+ base_addr (int): Base address of image. This is added to the
+ returned value of image-pos so that the returned position
+ indicates where the targeted entry/binary has actually been
+ loaded
Returns:
Value that should be assigned to that symbol, or None if it was
@@ -423,8 +420,8 @@
entries = OrderedDict()
entries_by_name = {}
self._CollectEntries(entries, entries_by_name, self)
- return self.LookupSymbol(sym_name, optional, msg, base_addr,
- entries_by_name)
+ return self.GetSymbolValue(sym_name, optional, msg, base_addr,
+ entries_by_name)
def CollectBintools(self):
"""Collect all the bintools used by this image
diff --git a/tools/binman/image_test.py b/tools/binman/image_test.py
index bd51c1e..7d65e2d 100644
--- a/tools/binman/image_test.py
+++ b/tools/binman/image_test.py
@@ -13,7 +13,7 @@
def testInvalidFormat(self):
image = Image('name', 'node', test=True)
with self.assertRaises(ValueError) as e:
- image.LookupSymbol('_binman_something_prop_', False, 'msg', 0)
+ image.GetSymbolValue('_binman_something_prop_', False, 'msg', 0)
self.assertIn(
"msg: Symbol '_binman_something_prop_' has invalid format",
str(e.exception))
@@ -22,7 +22,7 @@
image = Image('name', 'node', test=True)
image._entries = {}
with self.assertRaises(ValueError) as e:
- image.LookupSymbol('_binman_type_prop_pname', False, 'msg', 0)
+ image.GetSymbolValue('_binman_type_prop_pname', False, 'msg', 0)
self.assertIn("msg: Entry 'type' not found in list ()",
str(e.exception))
@@ -30,7 +30,7 @@
image = Image('name', 'node', test=True)
image._entries = {}
with capture_sys_output() as (stdout, stderr):
- val = image.LookupSymbol('_binman_type_prop_pname', True, 'msg', 0)
+ val = image.GetSymbolValue('_binman_type_prop_pname', True, 'msg', 0)
self.assertEqual(val, None)
self.assertEqual("Warning: msg: Entry 'type' not found in list ()\n",
stderr.getvalue())
@@ -40,5 +40,5 @@
image = Image('name', 'node', test=True)
image._entries = {'u-boot': 1}
with self.assertRaises(ValueError) as e:
- image.LookupSymbol('_binman_u_boot_prop_bad', False, 'msg', 0)
+ image.GetSymbolValue('_binman_u_boot_prop_bad', False, 'msg', 0)
self.assertIn("msg: No such property 'bad", str(e.exception))
diff --git a/tools/binman/test/336_symbols_base.dts b/tools/binman/test/336_symbols_base.dts
new file mode 100644
index 0000000..e4dccd3
--- /dev/null
+++ b/tools/binman/test/336_symbols_base.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ symbols-base = <0>;
+ };
+
+ u-boot {
+ offset = <0x1c>;
+ };
+
+ u-boot-spl2 {
+ type = "u-boot-spl";
+ };
+ };
+};
diff --git a/tools/binman/test/337_symbols_base_expand.dts b/tools/binman/test/337_symbols_base_expand.dts
new file mode 100644
index 0000000..5a777ae
--- /dev/null
+++ b/tools/binman/test/337_symbols_base_expand.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ symbols-base = <0>;
+ };
+
+ u-boot {
+ offset = <0x38>;
+ no-expanded;
+ };
+
+ u-boot-spl2 {
+ type = "u-boot-spl";
+ };
+ };
+};
diff --git a/tools/binman/test/338_symbols_comp.dts b/tools/binman/test/338_symbols_comp.dts
new file mode 100644
index 0000000..1500850
--- /dev/null
+++ b/tools/binman/test/338_symbols_comp.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ pad-byte = <0xff>;
+ u-boot-spl {
+ };
+
+ section {
+ offset = <0x1c>;
+ compress = "lz4";
+
+ u-boot {
+ };
+ };
+
+ u-boot-spl2 {
+ type = "u-boot-spl";
+ };
+ };
+};
diff --git a/tools/binman/test/339_nxp_imx8.dts b/tools/binman/test/339_nxp_imx8.dts
new file mode 100644
index 0000000..cb512ae
--- /dev/null
+++ b/tools/binman/test/339_nxp_imx8.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ nxp-imx8mimage {
+ args; /* TODO: Needed by mkimage etype superclass */
+ nxp,boot-from = "sd";
+ nxp,rom-version = <1>;
+ nxp,loader-address = <0x10>;
+ };
+ };
+};
diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py
index aea724f..a7358cf 100644
--- a/tools/buildman/bsettings.py
+++ b/tools/buildman/bsettings.py
@@ -31,6 +31,9 @@
def add_file(data):
settings.read_file(io.StringIO(data))
+def add_section(name):
+ settings.add_section(name)
+
def get_items(section):
"""Get the items from a section of the config.
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index c4384f5..4090d32 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -22,6 +22,7 @@
from patman import gitutil
from u_boot_pylib import command
from u_boot_pylib import terminal
+from u_boot_pylib import tools
from u_boot_pylib.terminal import tprint
# This indicates an new int or hex Kconfig property with no default
@@ -263,7 +264,8 @@
adjust_cfg=None, allow_missing=False, no_lto=False,
reproducible_builds=False, force_build=False,
force_build_failures=False, force_reconfig=False,
- in_tree=False, force_config_on_failure=False, make_func=None):
+ in_tree=False, force_config_on_failure=False, make_func=None,
+ dtc_skip=False):
"""Create a new Builder object
Args:
@@ -312,6 +314,7 @@
force_config_on_failure (bool): Reconfigure the build before
retrying a failed build
make_func (function): Function to call to run 'make'
+ dtc_skip (bool): True to skip building dtc and use the system one
"""
self.toolchains = toolchains
self.base_dir = base_dir
@@ -354,6 +357,12 @@
self.in_tree = in_tree
self.force_config_on_failure = force_config_on_failure
self.fallback_mrproper = fallback_mrproper
+ if dtc_skip:
+ self.dtc = shutil.which('dtc')
+ if not self.dtc:
+ raise ValueError('Cannot find dtc')
+ else:
+ self.dtc = None
if not self.squash_config_y:
self.config_filenames += EXTRA_CONFIG_FILENAMES
@@ -407,6 +416,22 @@
def signal_handler(self, signal, frame):
sys.exit(1)
+ def make_environment(self, toolchain):
+ """Create the environment to use for building
+
+ Args:
+ toolchain (Toolchain): Toolchain to use for building
+
+ Returns:
+ dict:
+ key (str): Variable name
+ value (str): Variable value
+ """
+ env = toolchain.MakeEnvironment(self.full_path)
+ if self.dtc:
+ env[b'DTC'] = tools.to_bytes(self.dtc)
+ return env
+
def set_display_options(self, show_errors=False, show_sizes=False,
show_detail=False, show_bloat=False,
list_error_boards=False, show_config=False,
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index bbe2f6f..b5afee6 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -406,7 +406,7 @@
the next incremental build
"""
# Set up the environment and command line
- env = self.toolchain.MakeEnvironment(self.builder.full_path)
+ env = self.builder.make_environment(self.toolchain)
mkdir(out_dir)
args, cwd, src_dir = self._build_args(brd, out_dir, out_rel_dir,
@@ -574,7 +574,7 @@
outf.write(f'{result.return_code}')
# Write out the image and function size information and an objdump
- env = result.toolchain.MakeEnvironment(self.builder.full_path)
+ env = self.builder.make_environment(self.toolchain)
with open(os.path.join(build_dir, 'out-env'), 'wb') as outf:
for var in sorted(env.keys()):
outf.write(b'%s="%s"' % (var, env[var]))
@@ -755,6 +755,14 @@
self.mrproper, self.builder.config_only, True,
self.builder.force_build_failures, job.work_in_output,
job.adjust_cfg)
+ failed = result.return_code or result.stderr
+ if failed and not self.mrproper:
+ result, request_config = self.run_commit(None, brd, work_dir,
+ True, self.builder.fallback_mrproper,
+ self.builder.config_only, True,
+ self.builder.force_build_failures,
+ job.work_in_output, job.adjust_cfg)
+
result.commit_upto = 0
self._write_result(result, job.keep_outputs, job.work_in_output)
self._send_result(result)
diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst
index b8ff3bf..e873611 100644
--- a/tools/buildman/buildman.rst
+++ b/tools/buildman/buildman.rst
@@ -1030,6 +1030,9 @@
./tools/buildman/buildman -Pr tegra
+Note also the `--dtc-skip` option which uses the system device-tree compiler to
+avoid needing to build it for each board. This can save 10-20% of build time.
+An alternative is to set DTC=/path/to/dtc when running buildman.
Checking configuration
----------------------
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 544a391..7573e5b 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -46,6 +46,8 @@
help='Show detailed size delta for each board in the -S summary')
parser.add_argument('-D', '--debug', action='store_true',
help='Enabling debugging (provides a full traceback on error)')
+ parser.add_argument('--dtc-skip', action='store_true', default=False,
+ help='Skip building of dtc and use the system version')
parser.add_argument('-e', '--show_errors', action='store_true',
default=False, help='Show errors and warnings')
parser.add_argument('-E', '--warnings-as-errors', action='store_true',
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index d3d027f..55d4d77 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -809,7 +809,8 @@
force_build = args.force_build,
force_build_failures = args.force_build_failures,
force_reconfig = args.force_reconfig, in_tree = args.in_tree,
- force_config_on_failure=not args.quick, make_func=make_func)
+ force_config_on_failure=not args.quick, make_func=make_func,
+ dtc_skip=args.dtc_skip)
TEST_BUILDER = builder
diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py
index b9f3756..27abbf9 100644
--- a/tools/buildman/kconfiglib.py
+++ b/tools/buildman/kconfiglib.py
@@ -6,7 +6,7 @@
========
Kconfiglib is a Python 2/3 library for scripting and extracting information
-from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
+from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.rst)
configuration systems.
See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer
@@ -709,7 +709,7 @@
mainmenu_text:
The prompt (title) of the top menu (top_node). Defaults to "Main menu".
- Can be changed with the 'mainmenu' statement (see kconfig-language.txt).
+ Can be changed with the 'mainmenu' statement (see kconfig-language.rst).
variables:
A dictionary with all preprocessor variables, indexed by name. See the
@@ -3562,7 +3562,7 @@
#
# - Propagates dependencies from parent to child nodes
#
- # - Creates implicit menus (see kconfig-language.txt)
+ # - Creates implicit menus (see kconfig-language.rst)
#
# - Removes 'if' nodes
#
@@ -5030,7 +5030,7 @@
0 (n) - The choice is disabled and no symbols can be selected. For
visible choices, this mode is only possible for choices with
- the 'optional' flag set (see kconfig-language.txt).
+ the 'optional' flag set (see kconfig-language.rst).
1 (m) - Any number of choice symbols can be set to m, the rest will
be n.
@@ -5498,7 +5498,7 @@
Choices and menus naturally have children, but Symbols can also have
children because of menus created automatically from dependencies (see
- kconfig-language.txt).
+ kconfig-language.rst).
parent:
The parent menu node. None if there is no parent.
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index bfad309..15801f6 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -36,6 +36,16 @@
x86: i386 x86_64
'''
+settings_data_wrapper = '''
+# Buildman settings file
+
+[toolchain]
+main: /usr/sbin
+
+[toolchain-wrapper]
+wrapper = ccache
+'''
+
migration = '''===================== WARNING ======================
This board does not use CONFIG_DM. CONFIG_DM will be
compulsory starting with the v2020.01 release.
@@ -148,6 +158,7 @@
self.toolchains.Add('arm-linux-gcc', test=False)
self.toolchains.Add('sparc-linux-gcc', test=False)
self.toolchains.Add('powerpc-linux-gcc', test=False)
+ self.toolchains.Add('/path/to/aarch64-linux-gcc', test=False)
self.toolchains.Add('gcc', test=False)
# Avoid sending any output
@@ -605,6 +616,9 @@
tc.GetEnvArgs(toolchain.VAR_ARCH))
self.assertEqual('', tc.GetEnvArgs(toolchain.VAR_MAKE_ARGS))
+ tc = self.toolchains.Select('sandbox')
+ self.assertEqual('', tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+
self.toolchains.Add('/path/to/x86_64-linux-gcc', test=False)
tc = self.toolchains.Select('x86')
self.assertEqual('/path/to',
@@ -613,6 +627,39 @@
self.assertEqual('HOSTCC=clang CC=clang',
tc.GetEnvArgs(toolchain.VAR_MAKE_ARGS))
+ # Test config with ccache wrapper
+ bsettings.setup(None)
+ bsettings.add_file(settings_data_wrapper)
+
+ tc = self.toolchains.Select('arm')
+ self.assertEqual('ccache arm-linux-',
+ tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+
+ tc = self.toolchains.Select('sandbox')
+ self.assertEqual('', tc.GetEnvArgs(toolchain.VAR_CROSS_COMPILE))
+
+ def testMakeEnvironment(self):
+ """Test the MakeEnvironment function"""
+ tc = self.toolchains.Select('arm')
+ env = tc.MakeEnvironment(False)
+ self.assertEqual(env[b'CROSS_COMPILE'], b'arm-linux-')
+
+ tc = self.toolchains.Select('sandbox')
+ env = tc.MakeEnvironment(False)
+ self.assertTrue(b'CROSS_COMPILE' not in env)
+
+ # Test config with ccache wrapper
+ bsettings.setup(None)
+ bsettings.add_file(settings_data_wrapper)
+
+ tc = self.toolchains.Select('arm')
+ env = tc.MakeEnvironment(False)
+ self.assertEqual(env[b'CROSS_COMPILE'], b'ccache arm-linux-')
+
+ tc = self.toolchains.Select('sandbox')
+ env = tc.MakeEnvironment(False)
+ self.assertTrue(b'CROSS_COMPILE' not in env)
+
def testPrepareOutputSpace(self):
def _Touch(fname):
tools.write_file(os.path.join(base_dir, fname), b'')
@@ -779,6 +826,7 @@
tmpdir = self.base_dir
with (patch('time.time', side_effect=self.get_time),
+ patch('time.monotonic', side_effect=self.get_time),
patch('time.sleep', side_effect=self.inc_time),
patch('os.kill', side_effect=self.kill)):
# Grab the process. Since there is no other profcess, this should
@@ -868,6 +916,120 @@
self.assertEqual([4, 5], control.read_procs(tmpdir))
self.assertEqual(self.finish_time, self.cur_time)
+ def call_make_environment(self, tchn, full_path, in_env=None):
+ """Call Toolchain.MakeEnvironment() and process the result
+
+ Args:
+ tchn (Toolchain): Toolchain to use
+ full_path (bool): True to return the full path in CROSS_COMPILE
+ rather than adding it to the PATH variable
+ in_env (dict): Input environment to use, None to use current env
+
+ Returns:
+ tuple:
+ dict: Changes that MakeEnvironment has made to the environment
+ key: Environment variable that was changed
+ value: New value (for PATH this only includes components
+ which were added)
+ str: Full value of the new PATH variable
+ """
+ env = tchn.MakeEnvironment(full_path, env=in_env)
+
+ # Get the original environment
+ orig_env = dict(os.environb if in_env is None else in_env)
+ orig_path = orig_env[b'PATH'].split(b':')
+
+ # Find new variables
+ diff = dict((k, env[k]) for k in env if orig_env.get(k) != env[k])
+
+ # Find new / different path components
+ diff_path = None
+ new_path = None
+ if b'PATH' in diff:
+ new_path = diff[b'PATH'].split(b':')
+ diff_paths = [p for p in new_path if p not in orig_path]
+ diff_path = b':'.join(p for p in new_path if p not in orig_path)
+ if diff_path:
+ diff[b'PATH'] = diff_path
+ else:
+ del diff[b'PATH']
+ return diff, new_path
+
+ def test_toolchain_env(self):
+ """Test PATH and other environment settings for toolchains"""
+ # Use a toolchain which has a path, so that full_path makes a difference
+ tchn = self.toolchains.Select('aarch64')
+
+ # Normal cases
+ diff = self.call_make_environment(tchn, full_path=False)[0]
+ self.assertEqual(
+ {b'CROSS_COMPILE': b'aarch64-linux-', b'LC_ALL': b'C',
+ b'PATH': b'/path/to'}, diff)
+
+ diff = self.call_make_environment(tchn, full_path=True)[0]
+ self.assertEqual(
+ {b'CROSS_COMPILE': b'/path/to/aarch64-linux-', b'LC_ALL': b'C'},
+ diff)
+
+ # When overriding the toolchain, only LC_ALL should be set
+ tchn.override_toolchain = True
+ diff = self.call_make_environment(tchn, full_path=True)[0]
+ self.assertEqual({b'LC_ALL': b'C'}, diff)
+
+ # Test that virtualenv is handled correctly
+ tchn.override_toolchain = False
+ sys.prefix = '/some/venv'
+ env = dict(os.environb)
+ env[b'PATH'] = b'/some/venv/bin:other/things'
+ tchn.path = '/my/path'
+ diff, diff_path = self.call_make_environment(tchn, False, env)
+
+ self.assertIn(b'PATH', diff)
+ self.assertEqual([b'/some/venv/bin', b'/my/path', b'other/things'],
+ diff_path)
+ self.assertEqual(
+ {b'CROSS_COMPILE': b'aarch64-linux-', b'LC_ALL': b'C',
+ b'PATH': b'/my/path'}, diff)
+
+ # Handle a toolchain wrapper
+ tchn.path = ''
+ bsettings.add_section('toolchain-wrapper')
+ bsettings.set_item('toolchain-wrapper', 'my-wrapper', 'fred')
+ diff = self.call_make_environment(tchn, full_path=True)[0]
+ self.assertEqual(
+ {b'CROSS_COMPILE': b'fred aarch64-linux-', b'LC_ALL': b'C'}, diff)
+
+ def test_skip_dtc(self):
+ """Test skipping building the dtc tool"""
+ old_path = os.getenv('PATH')
+ try:
+ os.environ['PATH'] = self.base_dir
+
+ # Check a missing tool
+ with self.assertRaises(ValueError) as exc:
+ builder.Builder(self.toolchains, self.base_dir, None, 0, 2,
+ dtc_skip=True)
+ self.assertIn('Cannot find dtc', str(exc.exception))
+
+ # Create a fake tool to use
+ dtc = os.path.join(self.base_dir, 'dtc')
+ tools.write_file(dtc, b'xx')
+ os.chmod(dtc, 0o777)
+
+ build = builder.Builder(self.toolchains, self.base_dir, None, 0, 2,
+ dtc_skip=True)
+ toolchain = self.toolchains.Select('arm')
+ env = build.make_environment(toolchain)
+ self.assertIn(b'DTC', env)
+
+ # Try the normal case, i.e. not skipping the dtc build
+ build = builder.Builder(self.toolchains, self.base_dir, None, 0, 2)
+ toolchain = self.toolchains.Select('arm')
+ env = build.make_environment(toolchain)
+ self.assertNotIn(b'DTC', env)
+ finally:
+ os.environ['PATH'] = old_path
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 324ad0e..a7d7883 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -159,6 +159,8 @@
if which == VAR_CROSS_COMPILE:
wrapper = self.GetWrapper()
base = '' if self.arch == 'sandbox' else self.path
+ if (base == '' and self.cross == ''):
+ return ''
return wrapper + os.path.join(base, self.cross)
elif which == VAR_PATH:
return self.path
@@ -172,13 +174,14 @@
else:
raise ValueError('Unknown arg to GetEnvArgs (%d)' % which)
- def MakeEnvironment(self, full_path):
+ def MakeEnvironment(self, full_path, env=None):
"""Returns an environment for using the toolchain.
This takes the current environment and adds CROSS_COMPILE so that
the tool chain will operate correctly. This also disables localized
output and possibly Unicode encoded output of all build tools by
- adding LC_ALL=C.
+ adding LC_ALL=C. For the case where full_path is False, it prepends
+ the toolchain to PATH
Note that os.environb is used to obtain the environment, since in some
cases the environment many contain non-ASCII characters and we see
@@ -187,26 +190,48 @@
UnicodeEncodeError: 'utf-8' codec can't encode characters in position
569-570: surrogates not allowed
+ When running inside a Python venv, care is taken not to put the
+ toolchain path before the venv path, so that builds initiated by
+ buildman will still respect the venv.
+
Args:
full_path: Return the full path in CROSS_COMPILE and don't set
PATH
+ env (dict of bytes): Original environment, used for testing
Returns:
Dict containing the (bytes) environment to use. This is based on the
current environment, with changes as needed to CROSS_COMPILE, PATH
and LC_ALL.
"""
- env = dict(os.environb)
+ env = dict(env or os.environb)
+
wrapper = self.GetWrapper()
if self.override_toolchain:
# We'll use MakeArgs() to provide this
pass
- elif full_path:
+ elif full_path and self.cross:
env[b'CROSS_COMPILE'] = tools.to_bytes(
wrapper + os.path.join(self.path, self.cross))
- else:
+ elif self.cross:
env[b'CROSS_COMPILE'] = tools.to_bytes(wrapper + self.cross)
- env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH']
+
+ # Detect a Python virtualenv and avoid defeating it
+ if sys.prefix != sys.base_prefix:
+ paths = env[b'PATH'].split(b':')
+ new_paths = []
+ to_insert = tools.to_bytes(self.path)
+ insert_after = tools.to_bytes(sys.prefix)
+ for path in paths:
+ new_paths.append(path)
+ if to_insert and path.startswith(insert_after):
+ new_paths.append(to_insert)
+ to_insert = None
+ if to_insert:
+ new_paths.append(to_insert)
+ env[b'PATH'] = b':'.join(new_paths)
+ else:
+ env[b'PATH'] = tools.to_bytes(self.path) + b':' + env[b'PATH']
env[b'LC_ALL'] = b'C'
diff --git a/tools/eficapsule.h b/tools/eficapsule.h
index 6efd07d..97d0775 100644
--- a/tools/eficapsule.h
+++ b/tools/eficapsule.h
@@ -24,7 +24,7 @@
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-typedef struct {
+typedef struct efi_guid {
uint8_t b[16];
} efi_guid_t __aligned(8);
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 1b53151..49f5b78 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -16,16 +16,20 @@
#include <sys/stat.h>
#include <sys/types.h>
-#include <uuid/uuid.h>
#include <gnutls/gnutls.h>
#include <gnutls/pkcs7.h>
#include <gnutls/abstract.h>
#include <version.h>
+#include <libfdt.h>
+#include <u-boot/uuid.h>
#include "eficapsule.h"
+// Matches CONFIG_EFI_CAPSULE_NAMESPACE_GUID
+#define DEFAULT_NAMESPACE_GUID "8c9f137e-91dc-427b-b2d6-b420faebaf2a"
+
static const char *tool_name = "mkeficapsule";
efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
@@ -56,11 +60,22 @@
{NULL, 0, NULL, 0},
};
-static void print_usage(void)
+static void print_usage_guidgen(void)
{
- fprintf(stderr, "Usage: %s [options] <image blob> <output file>\n"
+ fprintf(stderr, "%s guidgen [GUID] DTB IMAGE_NAME...\n"
"Options:\n"
+ "\tGUID Namespace GUID (default: %s)\n"
+ "\tDTB Device Tree Blob\n"
+ "\tIMAGE_NAME... One or more names of fw_images to generate GUIDs for\n",
+ tool_name, DEFAULT_NAMESPACE_GUID);
+}
+
+static void print_usage_mkeficapsule(void)
+{
+ fprintf(stderr, "Usage:\n\n%s [options] <image blob> <output file>\n"
+ "Options:\n"
+
"\t-g, --guid <guid string> guid for image blob type\n"
"\t-i, --index <index> update image index\n"
"\t-I, --instance <instance> update hardware instance\n"
@@ -74,8 +89,9 @@
"\t-o, --capoemflag Capsule OEM Flag, an integer between 0x0000 and 0xffff\n"
"\t-D, --dump-capsule dump the contents of the capsule headers\n"
"\t-V, --version show version number\n"
- "\t-h, --help print a help message\n",
+ "\t-h, --help print a help message\n\n",
tool_name);
+ print_usage_guidgen();
}
/**
@@ -578,37 +594,6 @@
return ret;
}
-/**
- * convert_uuid_to_guid() - convert UUID to GUID
- * @buf: UUID binary
- *
- * UUID and GUID have the same data structure, but their binary
- * formats are different due to the endianness. See lib/uuid.c.
- * Since uuid_parse() can handle only UUID, this function must
- * be called to get correct data for GUID when parsing a string.
- *
- * The correct data will be returned in @buf.
- */
-void convert_uuid_to_guid(unsigned char *buf)
-{
- unsigned char c;
-
- c = buf[0];
- buf[0] = buf[3];
- buf[3] = c;
- c = buf[1];
- buf[1] = buf[2];
- buf[2] = c;
-
- c = buf[4];
- buf[4] = buf[5];
- buf[5] = c;
-
- c = buf[6];
- buf[6] = buf[7];
- buf[7] = c;
-}
-
static int create_empty_capsule(char *path, efi_guid_t *guid, bool fw_accept)
{
struct efi_capsule_header header = { 0 };
@@ -654,20 +639,10 @@
static void print_guid(void *ptr)
{
- int i;
- efi_guid_t *guid = ptr;
- const uint8_t seq[] = {
- 3, 2, 1, 0, '-', 5, 4, '-', 7, 6,
- '-', 8, 9, '-', 10, 11, 12, 13, 14, 15 };
-
- for (i = 0; i < ARRAY_SIZE(seq); i++) {
- if (seq[i] == '-')
- putchar(seq[i]);
- else
- printf("%02X", guid->b[seq[i]]);
- }
+ static char buf[37] = { 0 };
- printf("\n");
+ uuid_bin_to_str(ptr, buf, UUID_STR_FORMAT_GUID | UUID_STR_UPPER_CASE);
+ printf("%s\n", buf);
}
static uint32_t dump_fmp_payload_header(
@@ -859,6 +834,129 @@
capsule_file);
exit(EXIT_FAILURE);
}
+}
+
+static struct fdt_header *load_dtb(const char *path)
+{
+ struct fdt_header *dtb;
+ ssize_t dtb_size;
+ FILE *f;
+
+ /* Open and parse DTB */
+ f = fopen(path, "r");
+ if (!f) {
+ fprintf(stderr, "Cannot open %s\n", path);
+ return NULL;
+ }
+
+ if (fseek(f, 0, SEEK_END)) {
+ fprintf(stderr, "Cannot seek to the end of %s: %s\n",
+ path, strerror(errno));
+ return NULL;
+ }
+
+ dtb_size = ftell(f);
+ if (dtb_size < 0) {
+ fprintf(stderr, "Cannot ftell %s: %s\n",
+ path, strerror(errno));
+ return NULL;
+ }
+
+ fseek(f, 0, SEEK_SET);
+
+ dtb = malloc(dtb_size);
+ if (!dtb) {
+ fprintf(stderr, "Can't allocated %ld\n", dtb_size);
+ return NULL;
+ }
+
+ if (fread(dtb, dtb_size, 1, f) != 1) {
+ fprintf(stderr, "Can't read %ld bytes from %s\n",
+ dtb_size, path);
+ free(dtb);
+ return NULL;
+ }
+
+ fclose(f);
+
+ return dtb;
+}
+
+#define MAX_IMAGE_NAME_LEN 128
+static int genguid(int argc, char **argv)
+{
+ int idx = 2, ret;
+ unsigned char namespace[16];
+ struct efi_guid image_type_id;
+ const char *dtb_path;
+ struct fdt_header *dtb;
+ const char *compatible;
+ int compatlen, namelen;
+ uint16_t fw_image[MAX_IMAGE_NAME_LEN];
+
+ if (argc < 2) {
+ fprintf(stderr, "Usage: ");
+ print_usage_guidgen();
+ return -1;
+ }
+
+ if (uuid_str_to_bin(argv[1], namespace, UUID_STR_FORMAT_GUID)) {
+ uuid_str_to_bin(DEFAULT_NAMESPACE_GUID, namespace, UUID_STR_FORMAT_GUID);
+ dtb_path = argv[1];
+ } else {
+ dtb_path = argv[2];
+ idx = 3;
+ }
+
+ if (idx == argc) {
+ fprintf(stderr, "Usage: ");
+ print_usage_guidgen();
+ return -1;
+ }
+
+ dtb = load_dtb(dtb_path);
+ if (!dtb)
+ return -1;
+
+ ret = fdt_check_header(dtb);
+ if (ret) {
+ fprintf(stderr, "Invalid DTB header: %d\n", ret);
+ return -1;
+ }
+
+ compatible = fdt_getprop(dtb, 0, "compatible", &compatlen);
+ if (!compatible) {
+ fprintf(stderr, "No compatible string found in DTB\n");
+ return -1;
+ }
+ if (strnlen(compatible, compatlen) >= compatlen) {
+ fprintf(stderr, "Compatible string not null-terminated\n");
+ return -1;
+ }
+
+ printf("Generating GUIDs for %s with namespace %s:\n",
+ compatible, DEFAULT_NAMESPACE_GUID);
+ for (; idx < argc; idx++) {
+ memset(fw_image, 0, sizeof(fw_image));
+ namelen = strlen(argv[idx]);
+ if (namelen > MAX_IMAGE_NAME_LEN) {
+ fprintf(stderr, "Image name too long: %s\n", argv[idx]);
+ return -1;
+ }
+
+ for (int i = 0; i < namelen; i++)
+ fw_image[i] = (uint16_t)argv[idx][i];
+
+ gen_v5_guid((struct uuid *)&namespace, &image_type_id,
+ compatible, strlen(compatible),
+ fw_image, namelen * sizeof(uint16_t),
+ NULL);
+
+ printf("%s: ", argv[idx]);
+ print_guid(&image_type_id);
+ }
+
+ return 0;
}
/**
@@ -885,6 +983,13 @@
int c, idx;
struct fmp_payload_header_params fmp_ph_params = { 0 };
+ /* Generate dynamic GUIDs */
+ if (argc > 1 && !strcmp(argv[1], "guidgen")) {
+ if (genguid(argc - 1, argv + 1))
+ exit(EXIT_FAILURE);
+ exit(EXIT_SUCCESS);
+ }
+
guid = NULL;
index = 0;
instance = 0;
@@ -907,11 +1012,10 @@
"Image type already specified\n");
exit(EXIT_FAILURE);
}
- if (uuid_parse(optarg, uuid_buf)) {
+ if (uuid_str_to_bin(optarg, uuid_buf, UUID_STR_FORMAT_GUID)) {
fprintf(stderr, "Wrong guid format\n");
exit(EXIT_FAILURE);
}
- convert_uuid_to_guid(uuid_buf);
guid = (efi_guid_t *)uuid_buf;
break;
case 'i':
@@ -977,7 +1081,7 @@
printf("mkeficapsule version %s\n", PLAIN_VERSION);
exit(EXIT_SUCCESS);
default:
- print_usage();
+ print_usage_mkeficapsule();
exit(EXIT_FAILURE);
}
}
@@ -1000,7 +1104,7 @@
((argc != optind + 1) ||
((capsule_type == CAPSULE_ACCEPT) && !guid) ||
((capsule_type == CAPSULE_REVERT) && guid)))) {
- print_usage();
+ print_usage_mkeficapsule();
exit(EXIT_FAILURE);
}
diff --git a/tools/patman/commit.py b/tools/patman/commit.py
index 684225c..ce37a3d 100644
--- a/tools/patman/commit.py
+++ b/tools/patman/commit.py
@@ -6,7 +6,7 @@
import re
# Separates a tag: at the beginning of the subject from the rest of it
-re_subject_tag = re.compile('([^:\s]*):\s*(.*)')
+re_subject_tag = re.compile(r'([^:\s]*):\s*(.*)')
class Commit:
"""Holds information about a single commit/patch in the series.
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index a09ae9c..4955f6a 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -48,7 +48,7 @@
RE_COMMIT = re.compile('^commit ([0-9a-f]*)$')
# We detect these since checkpatch doesn't always do it
-RE_SPACE_BEFORE_TAB = re.compile('^[+].* \t')
+RE_SPACE_BEFORE_TAB = re.compile(r'^[+].* \t')
# Match indented lines for changes
RE_LEADING_WHITESPACE = re.compile(r'^\s')
diff --git a/tools/qconfig.py b/tools/qconfig.py
index 7b868c7..8c2fc9e 100755
--- a/tools/qconfig.py
+++ b/tools/qconfig.py
@@ -1595,7 +1595,7 @@
if flag == 'help' or bad:
print("Imply flags: (separate with ',')")
for name, info in IMPLY_FLAGS.items():
- print(f' {name:-15s}: {info[1]}')
+ print(f' {name.ljust(15)}: {info[1]}')
return 1
imply_flags |= IMPLY_FLAGS[flag][0]