dts/upstream/Bindings/phy/fsl,imx8qm-hsio.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY

maintainers:
  - Richard Zhu <hongxing.zhu@nxp.com>

properties:
  compatible:
    enum:
      - fsl,imx8qm-hsio
      - fsl,imx8qxp-hsio
  reg:
    items:
      - description: Base address and length of the PHY block
      - description: HSIO control and status registers(CSR) of the PHY
      - description: HSIO CSR of the controller bound to the PHY
      - description: HSIO CSR for MISC

  reg-names:
    items:
      - const: reg
      - const: phy
      - const: ctrl
      - const: misc

  "#phy-cells":
    const: 3
    description:
      The first defines lane index.
      The second defines the type of the PHY refer to the include phy.h.
      The third defines the controller index, indicated which controller
      is bound to the lane.

  clocks:
    minItems: 5
    maxItems: 14

  clock-names:
    minItems: 5
    maxItems: 14

  fsl,hsio-cfg:
    description: |
      Specifies the use case of the HSIO module in the hardware design.
      Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
      confiured as following three use cases.
      +---------------------------------------+
      |                  | i.MX8QM            |
      |------------------|--------------------|
      |                  | Lane0| Lane1| Lane2|
      |------------------|------|------|------|
      | pciea-x2-sata    | PCIEA| PCIEA| SATA |
      |------------------|------|------|------|
      | pciea-x2-pcieb   | PCIEA| PCIEA| PCIEB|
      |------------------|------|------|------|
      | pciea-pcieb-sata | PCIEA| PCIEB| SATA |
      +---------------------------------------+
    $ref: /schemas/types.yaml#/definitions/string
    enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
    default: pciea-pcieb-sata

  fsl,refclk-pad-mode:
    description:
      Specifies the mode of the refclk pad used. INPUT(PHY refclock is
      provided externally via the refclk pad) or OUTPUT(PHY refclock is
      derived from SoC internal source and provided on the refclk pad).
      This property not exists means unused(PHY refclock is derived from
      SoC internal source).
    $ref: /schemas/types.yaml#/definitions/string
    enum: [ input, output, unused ]
    default: unused

  power-domains:
    minItems: 1
    maxItems: 2

required:
  - compatible
  - reg
  - reg-names
  - "#phy-cells"
  - clocks
  - clock-names
  - fsl,hsio-cfg

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8qxp-hsio
    then:
      properties:
        clock-names:
          items:
            - const: pclk0
            - const: apb_pclk0
            - const: phy0_crr
            - const: ctl0_crr
            - const: misc_crr
        power-domains:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8qm-hsio
    then:
      properties:
        clock-names:
          items:
            - const: pclk0
            - const: pclk1
            - const: apb_pclk0
            - const: apb_pclk1
            - const: pclk2
            - const: epcs_tx
            - const: epcs_rx
            - const: apb_pclk2
            - const: phy0_crr
            - const: phy1_crr
            - const: ctl0_crr
            - const: ctl1_crr
            - const: ctl2_crr
            - const: misc_crr
        power-domains:
          minItems: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-clock.h>
    #include <dt-bindings/clock/imx8-lpcg.h>
    #include <dt-bindings/firmware/imx/rsrc.h>
    #include <dt-bindings/phy/phy-imx8-pcie.h>

    phy@5f1a0000 {
        compatible = "fsl,imx8qxp-hsio";
        reg = <0x5f1a0000 0x10000>,
              <0x5f120000 0x10000>,
              <0x5f140000 0x10000>,
              <0x5f160000 0x10000>;
        reg-names = "reg", "phy", "ctrl", "misc";
        clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
                 <&phyx1_lpcg IMX_LPCG_CLK_4>,
                 <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
                 <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
                 <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
        clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr";
        power-domains = <&pd IMX_SC_R_SERDES_1>;
        #phy-cells = <3>;
        fsl,hsio-cfg = "pciea-pcieb-sata";
        fsl,refclk-pad-mode = "input";
    };
...