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git01.mediatek.com / filogic / atf / de7657cc0a504242dc1b3b276e82c81f07d61f0b / include / lib / cpus / aarch64 / cortex_a72.h
  1. 619d6fb feat(ti): set snoop-delayed exclusive handling on A72 cores by Andrew Davis · 1 year, 6 months ago
  2. b3fd376 feat(ti): set L2 cache ECC and and parity on A72 cores by Andrew Davis · 1 year, 6 months ago
  3. e7d7d11 feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles by Andrew Davis · 1 year, 6 months ago
  4. cf4d50a fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72 by Bipin Ravi · 2 years, 5 months ago
  5. 9ab98aa lib: cpu: Add additional field definition for A72 L2 control by Sheetal Tigadoli · 5 years ago
  6. 5e79cfe cpus: Add casts to all definitions in CPU headers by Antonio Nino Diaz · 5 years ago
  7. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · 6 years ago
  8. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · 6 years ago
  9. dc9fab1 Remove all other deprecated interfaces and files by Antonio Nino Diaz · 6 years ago
  10. 9eb5cf4 lib: cpu: Add L2 cache aux control register definition to CA72 by Konstantin Porotchkin · 6 years ago
  11. e6625ec Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · 6 years ago
  12. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · 7 years ago
  13. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · 7 years ago
  14. b83e42b CPU: Make shifted constants unsigned by Eleanor Bonnici · 7 years ago
  15. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · 7 years ago
  16. fa3cf0b Use SPDX license identifiers by dp-arm · 7 years ago
  17. 6a72a91 bl31: Add error reporting registers by Naga Sureshkumar Relli · 8 years ago
  18. 29a7a03 Juno R2: Configure the correct L2 RAM latency values by Sandrine Bailleux · 9 years ago
  19. c47e011 Add support for ARM Cortex-A72 processor by Vikram Kanigiri · 9 years ago