commit | b3fd3768ea56ed539d3fc0d757afccc2b22881c4 | [log] [tgz] |
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author | Andrew Davis <afd@ti.com> | Tue Jan 10 13:25:42 2023 -0600 |
committer | Andrew Davis <afd@ti.com> | Thu Jan 12 18:42:57 2023 -0600 |
tree | b7ff1786b13c6dac4bc1e84c1542d6dca192f7dc | |
parent | e7d7d1198f2de5bf0b69e19792d4ee41d896add6 [diff] |
feat(ti): set L2 cache ECC and and parity on A72 cores The Cortex-A72 based cores on K3 platforms have cache ECC and parity protection, enable these. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c