| commit | e7d7d1198f2de5bf0b69e19792d4ee41d896add6 | [log] [tgz] |
|---|---|---|
| author | Andrew Davis <afd@ti.com> | Tue Jan 10 13:14:37 2023 -0600 |
| committer | Andrew Davis <afd@ti.com> | Thu Jan 12 18:42:57 2023 -0600 |
| tree | 45fd80bb3588e3ed6506872215cf50d3f4cd597e | |
| parent | 3a170041cfdd0bcf03df1233ca7f83f6d9bf4036 [diff] |
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883