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filogic
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atf
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609186a6bb5fe1fe16d514c957ef99d67b5040fe
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include
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lib
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cpus
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aarch64
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cortex_a72.h
eee28e7
chore: update to use Arm word across TF-A
by Govindraj Raja
· 1 year, 1 month ago
619d6fb
feat(ti): set snoop-delayed exclusive handling on A72 cores
by Andrew Davis
· 1 year, 7 months ago
b3fd376
feat(ti): set L2 cache ECC and and parity on A72 cores
by Andrew Davis
· 1 year, 7 months ago
e7d7d11
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
by Andrew Davis
· 1 year, 7 months ago
cf4d50a
fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72
by Bipin Ravi
· 2 years, 6 months ago
9ab98aa
lib: cpu: Add additional field definition for A72 L2 control
by Sheetal Tigadoli
· 5 years ago
5e79cfe
cpus: Add casts to all definitions in CPU headers
by Antonio Nino Diaz
· 6 years ago
e0f9063
Sanitise includes across codebase
by Antonio Nino Diaz
· 6 years ago
5eb8837
Standardise header guards across codebase
by Antonio Nino Diaz
· 6 years ago
dc9fab1
Remove all other deprecated interfaces and files
by Antonio Nino Diaz
· 6 years ago
9eb5cf4
lib: cpu: Add L2 cache aux control register definition to CA72
by Konstantin Porotchkin
· 6 years ago
e6625ec
Implement static workaround for CVE-2018-3639
by Dimitris Papastamos
· 6 years ago
c3b4ca1
Cortex-A72: Implement workaround for erratum 859971
by Eleanor Bonnici
· 7 years ago
41b61be
CPU: Correct names of implementation-defined aux regs
by Eleanor Bonnici
· 7 years ago
b83e42b
CPU: Make shifted constants unsigned
by Eleanor Bonnici
· 7 years ago
1384a16
Unique names for defines in the CPU libraries
by Varun Wadekar
· 7 years ago
fa3cf0b
Use SPDX license identifiers
by dp-arm
· 7 years ago
6a72a91
bl31: Add error reporting registers
by Naga Sureshkumar Relli
· 8 years ago
29a7a03
Juno R2: Configure the correct L2 RAM latency values
by Sandrine Bailleux
· 9 years ago
c47e011
Add support for ARM Cortex-A72 processor
by Vikram Kanigiri
· 10 years ago