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git01.mediatek.com / filogic / atf / 1676aced1268efa01eb445bde20472bb1619e3d9 / plat / intel / soc / agilex
  1. 86f6fb3 feat(intel): restructure sys mgr for Agilex by Jit Loon Lim · 1 year, 6 months ago
  2. 2be03c0 fix(tree): correct some typos by Elyes Haouas · 1 year, 9 months ago
  3. a9fca83 fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 1 year, 11 months ago
  4. f48707a feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 2 years, 5 months ago
  5. 11b9b49 refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years ago
  6. bd8da63 feat(intel): extending to support SMMU in FCS by Sieu Mun Tang · 2 years, 1 month ago
  7. b9ae467 feat(intel): setup FPGA interface for Agilex by Jit Loon Lim · 2 years, 5 months ago
  8. a3e5635 fix(intel): fix pinmux handoff bug on Agilex by Jit Loon Lim · 2 years, 5 months ago
  9. 55803a2 fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 2 years, 4 months ago
  10. dc2daae build(agilex): platform changes for verifying gpt header crc by Rohit Ner · 2 years, 6 months ago
  11. b56c078 fix(intel): remove redundant NOC header declarations by Sieu Mun Tang · 2 years, 6 months ago
  12. 044ed48 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years, 6 months ago
  13. 2cebbc6 Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years, 6 months ago
  14. a4a4327 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years, 7 months ago
  15. 82cf5df feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years, 6 months ago
  16. 2f94ca4 feat(intel): enable firewall for OCRAM in BL31 by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
  17. 1205ef0 feat(intel): create source file for firewall configuration by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
  18. 616b5e7 fix(intel): refactor NOC header by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
  19. b19ac61 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 3 years, 3 months ago
  20. a544da1 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 8 months ago
  21. dbcc2cf fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 8 months ago
  22. f3a5d02 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 4 months ago
  23. 9f22cbf build(intel): initial commit for crypto driver by Sieu Mun Tang · 2 years, 8 months ago
  24. c353b0a Merge "fix(intel): assert if bl_mem_params is NULL pointer" into integration by Madhukar Pappireddy · 2 years, 8 months ago
  25. 380924d fix(intel): assert if bl_mem_params is NULL pointer by Siew Chin Lim · 3 years, 5 months ago
  26. ae4cd3a fix(intel): enable HPS QSPI access by default by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 1 month ago
  27. cf93158 plat/intel: do not keep mmc_device_info in stack by Yann Gautier · 3 years, 8 months ago
  28. 6474096 intel: mailbox: Ensure time out duration is predictive by Chee Hong Ang · 4 years, 6 months ago
  29. 2382b11 intel: clear 'PLAT_SEC_ENTRY' in early platform setup by Chee Hong Ang · 4 years, 7 months ago
  30. 0ae8d9a intel: platform: Include GICv2 makefile by Abdul Halim, Muhammad Hadi Asyrafi · 4 years, 3 months ago
  31. c5baddf plat: intel: Add FPGAINTF configuration to when configuring pinmux by Tien Hock Loh · 4 years, 6 months ago
  32. fcbc33d plat: intel: set DRVSEL and SMPLSEL for DWMMC by Tien Hock Loh · 4 years, 6 months ago
  33. 7a5f8da plat: intel: Fix clock configuration bugs by Tien Hock Loh · 4 years, 6 months ago
  34. 7dd4add Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration by Sandrine Bailleux · 4 years, 8 months ago
  35. 98b5a11 16550: Use generic console_t data structure by Andre Przywara · 4 years, 10 months ago
  36. 8d9e891 intel: Enable EMAC PHY in Intel FPGA platform by Tien Hock, Loh · 5 years ago
  37. 7f95059 Merge "intel: Change boot source selection" into integration by Sandrine Bailleux · 4 years, 9 months ago
  38. 593c4c5 intel: Extend SiP service to support mailbox's RSU by Hadi Asyrafi · 4 years, 11 months ago
  39. 786db4d intel: Change boot source selection by Hadi Asyrafi · 4 years, 10 months ago
  40. 218d8fe intel: agilex: Enable uboot BL31 loading by Hadi Asyrafi · 4 years, 10 months ago
  41. 6aeb55d intel: Add function to check fpga readiness by Hadi Asyrafi · 4 years, 11 months ago
  42. 36a9f30 intel: Add bridge control for FPGA reconfig by Hadi Asyrafi · 4 years, 11 months ago
  43. 8ebd237 intel: System Manager refactoring by Hadi Asyrafi · 4 years, 11 months ago
  44. 67cb0ea intel: Refactor reset manager driver by Hadi Asyrafi · 4 years, 11 months ago
  45. e73c511 intel: Enable bridge access in Intel platform by Hadi Asyrafi · 5 years ago
  46. 3afb87a intel: Modify non secure access function by Hadi Asyrafi · 5 years ago
  47. 99361aa Merge "intel: Fix memory calibration" into integration by Manish Pandey · 4 years, 10 months ago
  48. 1fab9c3 Remove redundant declarations. by Madhukar Pappireddy · 4 years, 10 months ago
  49. 966f282 intel: Fix memory calibration by Hadi Asyrafi · 5 years ago
  50. 5ae876f intel: Refactor common platform code [5/5] by Hadi Asyrafi · 5 years ago
  51. 4d9f395 intel: Refactor common platform code [4/5] by Hadi Asyrafi · 5 years ago
  52. 6f8a2b2 intel: Refactor common platform code [3/5] by Hadi Asyrafi · 5 years ago
  53. f0fa807 intel: Refactor common platform code [2/5] by Hadi Asyrafi · 5 years ago
  54. 9f5dfc9 intel: Refactor common platform code [1/5] by Hadi Asyrafi · 5 years ago
  55. 461f8f4 Invalidate dcache build option for bl2 entry at EL3 by Hadi Asyrafi · 5 years ago
  56. 91071fc intel: agilex: Fix psci power domain off by Hadi Asyrafi · 5 years ago
  57. cc077d9 Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration by Paul Beesley · 5 years ago
  58. 5d7c656 intel: agilex: HMC driver calculate DDR size by Hadi Asyrafi · 5 years ago
  59. 56c4901 intel: agilex: Clear PLL lostlock bypass mode by Hadi Asyrafi · 5 years ago
  60. ad90712 Merge "intel: agilex: Fix memory controller driver" into integration by Paul Beesley · 5 years ago
  61. 83fe38e intel: agilex: Fix memory controller driver by Hadi Asyrafi · 5 years ago
  62. a813fed intel: agilex: Fix reliance on hard coded clock information by Hadi Asyrafi · 5 years ago
  63. 462c6c4 Merge changes from topic "intel-plat-refactor" into integration by Sandrine Bailleux · 5 years ago
  64. 309ac01 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
  65. 6a240c7 intel: Platform common code refactor by Hadi Asyrafi · 5 years ago
  66. e944d22 intel: agilex: Fix BL31 memory mapping by Hadi Asyrafi · 5 years ago
  67. a724e43 intel: agilex: Fix build error by Ambroise Vincent · 5 years ago
  68. 616da77 intel: Adds support for Agilex platform by Hadi Asyrafi · 5 years ago