| commit | fcbc33d314094d8d28caa980aedb0253f0dc8066 | [log] [tgz] |
|---|---|---|
| author | Tien Hock Loh <tien.hock.loh@intel.com> | Mon May 11 01:11:39 2020 -0700 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Mon Jun 08 22:03:34 2020 +0000 |
| tree | 45f096232af0d8df97b6bb2809234005b09bb559 | |
| parent | 7a5f8daf2c0af59aaad9dcfe4cc0d9e659f84394 [diff] |
plat: intel: set DRVSEL and SMPLSEL for DWMMC DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677