a9fca836fb9392cb2956923a6c8427c253a4c874 - filogic/atf

commit	a9fca836fb9392cb2956923a6c8427c253a4c874	[log] [tgz]
author	Jit Loon Lim <jit.loon.lim@intel.com>	Thu Dec 22 21:52:36 2022 +0800
committer	Sieu Mun Tang <sieu.mun.tang@intel.com>	Fri Apr 14 09:19:31 2023 +0800
tree	d4af3aeee5040bb2f39f5c087d5316723247b653
parent	f48707a01f958c99dc53be7731f5c799c96c4296 [diff]

fix(intel): fix Agilex and N5X clock manager to main PLL C0

Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19

plat/intel/soc/agilex/include/agilex_clock_manager.h[diff]
plat/intel/soc/agilex/soc/agilex_clock_manager.c[diff]
plat/intel/soc/common/include/platform_def.h[diff]
plat/intel/soc/n5x/include/n5x_clock_manager.h[diff]
plat/intel/soc/n5x/soc/n5x_clock_manager.c[diff]
plat/intel/soc/stratix10/soc/s10_clock_manager.c[diff]

6 files changed

tree: d4af3aeee5040bb2f39f5c087d5316723247b653