commit | 56c490106b01196300ccfd7e8701c4e22d020b99 | [log] [tgz] |
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author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | Fri Aug 16 11:08:14 2019 +0800 |
committer | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | Mon Aug 19 10:56:31 2019 +0800 |
tree | 6a33c0a28c429705fcc976f2addae8c758dc8098 | |
parent | ad90712c120ca238656efbd55b93a0a4a88620f3 [diff] |
intel: agilex: Clear PLL lostlock bypass mode To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1