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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/desc_image_load.h>
16#include <drivers/generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010017#ifdef SPD_opteed
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <lib/optee_utils.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010019#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000021#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <plat/common/platform.h>
23
Dan Handley9df48042015-03-19 18:58:55 +000024/* Data structure which holds the extents of the trusted SRAM for BL2 */
25static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
Soby Mathewc44110d2018-02-20 12:50:47 +000027/*
Soby Mathewaf14b462018-06-01 16:53:38 +010028 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
29 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000030 */
Soby Mathewaf14b462018-06-01 16:53:38 +010031CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000032
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010033/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000034#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010035#pragma weak bl2_platform_setup
36#pragma weak bl2_plat_arch_setup
37#pragma weak bl2_plat_sec_mem_layout
38
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010039#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
40 bl2_tzram_layout.total_base, \
41 bl2_tzram_layout.total_size, \
42 MT_MEMORY | MT_RW | MT_SECURE)
43
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010044
Daniel Boulby07d26872018-06-27 16:45:48 +010045#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010046
Dan Handley9df48042015-03-19 18:58:55 +000047/*******************************************************************************
48 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
49 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
50 * Copy it to a safe location before its reclaimed by later BL2 functionality.
51 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020052void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
53 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000054{
55 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010056 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000057
58 /* Setup the BL2 memory layout */
59 bl2_tzram_layout = *mem_layout;
60
61 /* Initialise the IO layer and register platform IO devices */
62 plat_arm_io_setup();
Soby Mathew96a1c6b2018-01-15 14:45:33 +000063
Soby Mathewcc364842018-02-21 01:16:39 +000064 if (tb_fw_config != 0U)
Soby Mathew96a1c6b2018-01-15 14:45:33 +000065 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
Dan Handley9df48042015-03-19 18:58:55 +000066}
67
Soby Mathew7d5a2e72018-01-10 15:59:31 +000068void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000069{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000070 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
71
Soby Mathew1ced6b82017-06-12 12:37:10 +010072 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +000073}
74
75/*
Soby Mathew45e39e22018-03-26 15:16:46 +010076 * Perform BL2 preload setup. Currently we initialise the dynamic
77 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +000078 */
Soby Mathew45e39e22018-03-26 15:16:46 +010079void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000080{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000081 arm_bl2_dyn_cfg_init();
Soby Mathew45e39e22018-03-26 15:16:46 +010082}
Soby Mathew96a1c6b2018-01-15 14:45:33 +000083
Soby Mathew45e39e22018-03-26 15:16:46 +010084/*
85 * Perform ARM standard platform setup.
86 */
87void arm_bl2_platform_setup(void)
88{
Dan Handley9df48042015-03-19 18:58:55 +000089 /* Initialize the secure environment */
90 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010091
92#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +000093 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010094#endif
Dan Handley9df48042015-03-19 18:58:55 +000095}
96
97void bl2_platform_setup(void)
98{
99 arm_bl2_platform_setup();
100}
101
102/*******************************************************************************
103 * Perform the very early platform specific architectural setup here. At the
104 * moment this is only initializes the mmu in a quick and dirty way.
105 ******************************************************************************/
106void arm_bl2_plat_arch_setup(void)
107{
Soby Mathewb9856482018-09-18 11:42:42 +0100108#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
109 /*
110 * Ensure ARM platforms don't use coherent memory in BL2 unless
111 * cryptocell integration is enabled.
112 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100113 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000114#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100115
116 const mmap_region_t bl_regions[] = {
117 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100118 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100119#if USE_ROMLIB
120 ARM_MAP_ROMLIB_CODE,
121 ARM_MAP_ROMLIB_DATA,
122#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100123#if ARM_CRYPTOCELL_INTEG
124 ARM_MAP_BL_COHERENT_RAM,
125#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100126 {0}
127 };
128
Roberto Vargas344ff022018-10-19 16:44:18 +0100129 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100130
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700131#ifdef __aarch64__
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100132 enable_mmu_el1(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700133#else
134 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100135#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100136
137 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000138}
139
140void bl2_plat_arch_setup(void)
141{
142 arm_bl2_plat_arch_setup();
143}
144
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000145int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100146{
147 int err = 0;
148 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100149#ifdef SPD_opteed
150 bl_mem_params_node_t *pager_mem_params = NULL;
151 bl_mem_params_node_t *paged_mem_params = NULL;
152#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100153 assert(bl_mem_params);
154
155 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700156#ifdef __aarch64__
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100157 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100158#ifdef SPD_opteed
159 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
160 assert(pager_mem_params);
161
162 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
163 assert(paged_mem_params);
164
165 err = parse_optee_header(&bl_mem_params->ep_info,
166 &pager_mem_params->image_info,
167 &paged_mem_params->image_info);
168 if (err != 0) {
169 WARN("OPTEE header parse error.\n");
170 }
171#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100172 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
173 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100174#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100175
176 case BL33_IMAGE_ID:
177 /* BL33 expects to receive the primary CPU MPID (through r0) */
178 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
179 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
180 break;
181
182#ifdef SCP_BL2_BASE
183 case SCP_BL2_IMAGE_ID:
184 /* The subsequent handling of SCP_BL2 is platform specific */
185 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
186 if (err) {
187 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
188 }
189 break;
190#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000191 default:
192 /* Do nothing in default case */
193 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100194 }
195
196 return err;
197}
198
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000199/*******************************************************************************
200 * This function can be used by the platforms to update/use image
201 * information for given `image_id`.
202 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100203int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000204{
205 return arm_bl2_handle_post_image_load(image_id);
206}
207
Daniel Boulby07d26872018-06-27 16:45:48 +0100208int bl2_plat_handle_post_image_load(unsigned int image_id)
209{
210 return arm_bl2_plat_handle_post_image_load(image_id);
211}